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MachineConvergenceVerifier.cpp
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//===- MachineConvergenceVerifier.cpp - Verify convergencectrl ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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#include "
llvm/CodeGen/MachineConvergenceVerifier.h
"
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#include "
llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
"
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#include "
llvm/CodeGen/MachineDominators.h
"
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#include "
llvm/CodeGen/MachineRegisterInfo.h
"
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#include "
llvm/CodeGen/MachineSSAContext.h
"
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#include "
llvm/IR/GenericConvergenceVerifierImpl.h
"
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using namespace
llvm
;
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template
<>
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auto
GenericConvergenceVerifier<MachineSSAContext>::getConvOp
(
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const
MachineInstr
&
MI
) -> ConvOpKind {
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switch
(
MI
.getOpcode()) {
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default
:
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return
CONV_NONE;
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case
TargetOpcode::CONVERGENCECTRL_ENTRY:
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return
CONV_ENTRY;
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case
TargetOpcode::CONVERGENCECTRL_ANCHOR:
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return
CONV_ANCHOR;
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case
TargetOpcode::CONVERGENCECTRL_LOOP:
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return
CONV_LOOP;
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}
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}
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template
<>
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void
GenericConvergenceVerifier
<
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MachineSSAContext
>::checkConvergenceTokenProduced(
const
MachineInstr
&
MI
) {
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Check
(!
MI
.hasImplicitDef(),
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"Convergence control tokens are defined explicitly."
,
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{Context.print(&MI)});
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const
MachineOperand
&
Def
=
MI
.getOperand(0);
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const
MachineRegisterInfo
&
MRI
=
Context
.getFunction()->getRegInfo();
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Check
(
MRI
.getUniqueVRegDef(
Def
.getReg()),
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"Convergence control tokens must have unique definitions."
,
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{Context.print(&MI)});
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}
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template
<>
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const
MachineInstr
*
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GenericConvergenceVerifier<MachineSSAContext>::findAndCheckConvergenceTokenUsed
(
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const
MachineInstr
&
MI
) {
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const
MachineRegisterInfo
&
MRI
=
Context
.getFunction()->getRegInfo();
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const
MachineInstr
*TokenDef =
nullptr
;
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for
(
unsigned
I
= 0, E =
MI
.getNumOperands();
I
!= E; ++
I
) {
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const
MachineOperand
&MO =
MI
.getOperand(
I
);
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if
(!MO.
isReg
() || !MO.
isUse
())
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continue
;
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Register
OpReg = MO.
getReg
();
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if
(!OpReg.
isVirtual
())
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continue
;
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const
MachineInstr
*
Def
=
MRI
.getUniqueVRegDef(OpReg);
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if
(!Def)
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continue
;
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if
(getConvOp(*Def) == CONV_NONE)
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continue
;
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CheckOrNull
(
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MI
.isConvergent(),
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"Convergence control tokens can only be used by convergent operations."
,
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{Context.print(OpReg), Context.print(&MI)});
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CheckOrNull
(!TokenDef,
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"An operation can use at most one convergence control token."
,
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{
Context
.print(OpReg),
Context
.print(&
MI
)});
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TokenDef =
Def
;
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}
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if
(TokenDef)
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Tokens[&
MI
] = TokenDef;
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return
TokenDef;
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}
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template
<>
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bool
GenericConvergenceVerifier<MachineSSAContext>::isInsideConvergentFunction
(
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const
MachineInstr
&
MI
) {
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// The class MachineFunction does not have any property to indicate whether it
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// is convergent. Trivially return true so that the check always passes.
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return
true
;
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}
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template
<>
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bool
GenericConvergenceVerifier<MachineSSAContext>::isConvergent
(
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const
MachineInstr
&
MI
) {
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return
MI
.isConvergent();
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}
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template
class
llvm::GenericConvergenceVerifier<MachineSSAContext>
;
MRI
unsigned const MachineRegisterInfo * MRI
Definition:
AArch64AdvSIMDScalarPass.cpp:105
GenericConvergenceVerifierImpl.h
A verifier for the static rules of convergence control tokens that works with both LLVM IR and MIR.
Check
#define Check(C,...)
Definition:
GenericConvergenceVerifierImpl.h:34
CheckOrNull
#define CheckOrNull(C,...)
Definition:
GenericConvergenceVerifierImpl.h:42
GenericMachineInstrs.h
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
MI
IRTranslator LLVM IR MI
Definition:
IRTranslator.cpp:113
I
#define I(x, y, z)
Definition:
MD5.cpp:58
MachineConvergenceVerifier.h
This file declares the MIR specialization of the GenericConvergenceVerifier template.
MachineDominators.h
MachineRegisterInfo.h
MachineSSAContext.h
This file declares a specialization of the GenericSSAContext<X> template class for Machine IR.
Context
LLVMContext & Context
Definition:
NVVMIntrRange.cpp:66
llvm::GenericConvergenceVerifier
Definition:
GenericConvergenceVerifier.h:23
llvm::GenericSSAContext
Definition:
GenericSSAContext.h:41
llvm::MachineInstr
Representation of each machine instruction.
Definition:
MachineInstr.h:69
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition:
MachineOperand.h:48
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition:
MachineOperand.h:329
llvm::MachineOperand::isUse
bool isUse() const
Definition:
MachineOperand.h:379
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition:
MachineOperand.h:369
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition:
MachineRegisterInfo.h:51
llvm::Register
Wrapper class representing virtual and physical registers.
Definition:
Register.h:19
llvm::Register::isVirtual
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition:
Register.h:91
llvm::rdf::Def
NodeAddr< DefNode * > Def
Definition:
RDFGraph.h:384
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition:
AddressRanges.h:18
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