LLVM 17.0.0git
MachineRegisterInfo.cpp
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1//===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implementation of the MachineRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
23#include "llvm/Config/llvm-config.h"
24#include "llvm/IR/Attributes.h"
25#include "llvm/IR/DebugLoc.h"
26#include "llvm/IR/Function.h"
33#include <cassert>
34
35using namespace llvm;
36
37static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
38 cl::init(true), cl::desc("Enable subregister liveness tracking."));
39
40// Pin the vtable to this file.
41void MachineRegisterInfo::Delegate::anchor() {}
42
44 : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
46 unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
47 VRegInfo.reserve(256);
48 RegAllocHints.reserve(256);
49 UsedPhysRegMask.resize(NumRegs);
50 PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
51 TheDelegates.clear();
52}
53
54/// setRegClass - Set the register class of the specified virtual register.
55///
56void
58 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
59 VRegInfo[Reg].first = RC;
60}
61
63 const RegisterBank &RegBank) {
64 VRegInfo[Reg].first = &RegBank;
65}
66
67static const TargetRegisterClass *
69 const TargetRegisterClass *OldRC,
70 const TargetRegisterClass *RC, unsigned MinNumRegs) {
71 if (OldRC == RC)
72 return RC;
73 const TargetRegisterClass *NewRC =
74 MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
75 if (!NewRC || NewRC == OldRC)
76 return NewRC;
77 if (NewRC->getNumRegs() < MinNumRegs)
78 return nullptr;
79 MRI.setRegClass(Reg, NewRC);
80 return NewRC;
81}
82
84 Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) {
85 if (Reg.isPhysical())
86 return nullptr;
87 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
88}
89
90bool
92 Register ConstrainingReg,
93 unsigned MinNumRegs) {
94 const LLT RegTy = getType(Reg);
95 const LLT ConstrainingRegTy = getType(ConstrainingReg);
96 if (RegTy.isValid() && ConstrainingRegTy.isValid() &&
97 RegTy != ConstrainingRegTy)
98 return false;
99 const auto ConstrainingRegCB = getRegClassOrRegBank(ConstrainingReg);
100 if (!ConstrainingRegCB.isNull()) {
101 const auto RegCB = getRegClassOrRegBank(Reg);
102 if (RegCB.isNull())
103 setRegClassOrRegBank(Reg, ConstrainingRegCB);
104 else if (RegCB.is<const TargetRegisterClass *>() !=
105 ConstrainingRegCB.is<const TargetRegisterClass *>())
106 return false;
107 else if (RegCB.is<const TargetRegisterClass *>()) {
109 *this, Reg, RegCB.get<const TargetRegisterClass *>(),
110 ConstrainingRegCB.get<const TargetRegisterClass *>(), MinNumRegs))
111 return false;
112 } else if (RegCB != ConstrainingRegCB)
113 return false;
114 }
115 if (ConstrainingRegTy.isValid())
116 setType(Reg, ConstrainingRegTy);
117 return true;
118}
119
120bool
123 const TargetRegisterClass *OldRC = getRegClass(Reg);
124 const TargetRegisterClass *NewRC =
126
127 // Stop early if there is no room to grow.
128 if (NewRC == OldRC)
129 return false;
130
131 // Accumulate constraints from all uses.
132 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
133 // Apply the effect of the given operand to NewRC.
134 MachineInstr *MI = MO.getParent();
135 unsigned OpNo = &MO - &MI->getOperand(0);
136 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
138 if (!NewRC || NewRC == OldRC)
139 return false;
140 }
141 setRegClass(Reg, NewRC);
142 return true;
143}
144
147 VRegInfo.grow(Reg);
148 RegAllocHints.grow(Reg);
150 return Reg;
151}
152
153/// createVirtualRegister - Create and return a new virtual register in the
154/// function with the specified register class.
155///
158 StringRef Name) {
159 assert(RegClass && "Cannot create register without RegClass!");
160 assert(RegClass->isAllocatable() &&
161 "Virtual register RegClass must be allocatable.");
162
163 // New virtual register number.
165 VRegInfo[Reg].first = RegClass;
167 return Reg;
168}
169
171 StringRef Name) {
173 VRegInfo[Reg].first = VRegInfo[VReg].first;
174 setType(Reg, getType(VReg));
175 noteCloneVirtualRegister(Reg, VReg);
176 return Reg;
177}
178
180 VRegToType.grow(VReg);
181 VRegToType[VReg] = Ty;
182}
183
186 // New virtual register number.
188 // FIXME: Should we use a dummy register class?
189 VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
190 setType(Reg, Ty);
192 return Reg;
193}
194
196
197/// clearVirtRegs - Remove all virtual registers (after physreg assignment).
199#ifndef NDEBUG
200 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
202 if (!VRegInfo[Reg].second)
203 continue;
204 verifyUseList(Reg);
205 errs() << "Remaining virtual register "
206 << printReg(Reg, getTargetRegisterInfo()) << "...\n";
207 for (MachineInstr &MI : reg_instructions(Reg))
208 errs() << "...in instruction: " << MI << "\n";
209 std::abort();
210 }
211#endif
212 VRegInfo.clear();
213 for (auto &I : LiveIns)
214 I.second = 0;
215}
216
218#ifndef NDEBUG
219 bool Valid = true;
220 for (MachineOperand &M : reg_operands(Reg)) {
221 MachineOperand *MO = &M;
222 MachineInstr *MI = MO->getParent();
223 if (!MI) {
225 << " use list MachineOperand " << MO
226 << " has no parent instruction.\n";
227 Valid = false;
228 continue;
229 }
230 MachineOperand *MO0 = &MI->getOperand(0);
231 unsigned NumOps = MI->getNumOperands();
232 if (!(MO >= MO0 && MO < MO0+NumOps)) {
234 << " use list MachineOperand " << MO
235 << " doesn't belong to parent MI: " << *MI;
236 Valid = false;
237 }
238 if (!MO->isReg()) {
240 << " MachineOperand " << MO << ": " << *MO
241 << " is not a register\n";
242 Valid = false;
243 }
244 if (MO->getReg() != Reg) {
246 << " use-list MachineOperand " << MO << ": "
247 << *MO << " is the wrong register\n";
248 Valid = false;
249 }
250 }
251 assert(Valid && "Invalid use list");
252#endif
253}
254
256#ifndef NDEBUG
257 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
259 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
260 verifyUseList(i);
261#endif
262}
263
264/// Add MO to the linked list of operands for its register.
266 assert(!MO->isOnRegUseList() && "Already on list");
267 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
268 MachineOperand *const Head = HeadRef;
269
270 // Head points to the first list element.
271 // Next is NULL on the last list element.
272 // Prev pointers are circular, so Head->Prev == Last.
273
274 // Head is NULL for an empty list.
275 if (!Head) {
276 MO->Contents.Reg.Prev = MO;
277 MO->Contents.Reg.Next = nullptr;
278 HeadRef = MO;
279 return;
280 }
281 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
282
283 // Insert MO between Last and Head in the circular Prev chain.
284 MachineOperand *Last = Head->Contents.Reg.Prev;
285 assert(Last && "Inconsistent use list");
286 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
287 Head->Contents.Reg.Prev = MO;
288 MO->Contents.Reg.Prev = Last;
289
290 // Def operands always precede uses. This allows def_iterator to stop early.
291 // Insert def operands at the front, and use operands at the back.
292 if (MO->isDef()) {
293 // Insert def at the front.
294 MO->Contents.Reg.Next = Head;
295 HeadRef = MO;
296 } else {
297 // Insert use at the end.
298 MO->Contents.Reg.Next = nullptr;
299 Last->Contents.Reg.Next = MO;
300 }
301}
302
303/// Remove MO from its use-def list.
305 assert(MO->isOnRegUseList() && "Operand not on use list");
306 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
307 MachineOperand *const Head = HeadRef;
308 assert(Head && "List already empty");
309
310 // Unlink this from the doubly linked list of operands.
311 MachineOperand *Next = MO->Contents.Reg.Next;
312 MachineOperand *Prev = MO->Contents.Reg.Prev;
313
314 // Prev links are circular, next link is NULL instead of looping back to Head.
315 if (MO == Head)
316 HeadRef = Next;
317 else
318 Prev->Contents.Reg.Next = Next;
319
320 (Next ? Next : Head)->Contents.Reg.Prev = Prev;
321
322 MO->Contents.Reg.Prev = nullptr;
323 MO->Contents.Reg.Next = nullptr;
324}
325
326/// Move NumOps operands from Src to Dst, updating use-def lists as needed.
327///
328/// The Dst range is assumed to be uninitialized memory. (Or it may contain
329/// operands that won't be destroyed, which is OK because the MO destructor is
330/// trivial anyway).
331///
332/// The Src and Dst ranges may overlap.
334 MachineOperand *Src,
335 unsigned NumOps) {
336 assert(Src != Dst && NumOps && "Noop moveOperands");
337
338 // Copy backwards if Dst is within the Src range.
339 int Stride = 1;
340 if (Dst >= Src && Dst < Src + NumOps) {
341 Stride = -1;
342 Dst += NumOps - 1;
343 Src += NumOps - 1;
344 }
345
346 // Copy one operand at a time.
347 do {
348 new (Dst) MachineOperand(*Src);
349
350 // Dst takes Src's place in the use-def chain.
351 if (Src->isReg()) {
352 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
353 MachineOperand *Prev = Src->Contents.Reg.Prev;
354 MachineOperand *Next = Src->Contents.Reg.Next;
355 assert(Head && "List empty, but operand is chained");
356 assert(Prev && "Operand was not on use-def list");
357
358 // Prev links are circular, next link is NULL instead of looping back to
359 // Head.
360 if (Src == Head)
361 Head = Dst;
362 else
363 Prev->Contents.Reg.Next = Dst;
364
365 // Update Prev pointer. This also works when Src was pointing to itself
366 // in a 1-element list. In that case Head == Dst.
367 (Next ? Next : Head)->Contents.Reg.Prev = Dst;
368 }
369
370 Dst += Stride;
371 Src += Stride;
372 } while (--NumOps);
373}
374
375/// replaceRegWith - Replace all instances of FromReg with ToReg in the
376/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
377/// except that it also changes any definitions of the register as well.
378/// If ToReg is a physical register we apply the sub register to obtain the
379/// final/proper physical register.
381 assert(FromReg != ToReg && "Cannot replace a reg with itself");
382
384
385 // TODO: This could be more efficient by bulk changing the operands.
387 if (ToReg.isPhysical()) {
388 O.substPhysReg(ToReg, *TRI);
389 } else {
390 O.setReg(ToReg);
391 }
392 }
393}
394
395/// getVRegDef - Return the machine instr that defines the specified virtual
396/// register or null if none is found. This assumes that the code is in SSA
397/// form, so there should only be one definition.
399 // Since we are in SSA form, we can use the first definition.
401 assert((I.atEnd() || std::next(I) == def_instr_end()) &&
402 "getVRegDef assumes a single definition or no definition");
403 return !I.atEnd() ? &*I : nullptr;
404}
405
406/// getUniqueVRegDef - Return the unique machine instr that defines the
407/// specified virtual register or null if none is found. If there are
408/// multiple definitions or no definition, return null.
410 if (def_empty(Reg)) return nullptr;
412 if (std::next(I) != def_instr_end())
413 return nullptr;
414 return &*I;
415}
416
419}
420
423}
424
426 unsigned MaxUsers) const {
428 MaxUsers);
429}
430
431/// clearKillFlags - Iterate over all the uses of the given register and
432/// clear the kill flag from the MachineOperand. This function is used by
433/// optimization passes which extend register lifetimes and need only
434/// preserve conservative kill flag information.
436 for (MachineOperand &MO : use_operands(Reg))
437 MO.setIsKill(false);
438}
439
441 for (const std::pair<MCRegister, Register> &LI : liveins())
442 if ((Register)LI.first == Reg || LI.second == Reg)
443 return true;
444 return false;
445}
446
447/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
448/// corresponding live-in physical register.
450 for (const std::pair<MCRegister, Register> &LI : liveins())
451 if (LI.second == VReg)
452 return LI.first;
453 return MCRegister();
454}
455
456/// getLiveInVirtReg - If PReg is a live-in physical register, return the
457/// corresponding live-in physical register.
459 for (const std::pair<MCRegister, Register> &LI : liveins())
460 if (LI.first == PReg)
461 return LI.second;
462 return Register();
463}
464
465/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
466/// into the given entry block.
467void
469 const TargetRegisterInfo &TRI,
470 const TargetInstrInfo &TII) {
471 // Emit the copies into the top of the block.
472 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
473 if (LiveIns[i].second) {
474 if (use_nodbg_empty(LiveIns[i].second)) {
475 // The livein has no non-dbg uses. Drop it.
476 //
477 // It would be preferable to have isel avoid creating live-in
478 // records for unused arguments in the first place, but it's
479 // complicated by the debug info code for arguments.
480 LiveIns.erase(LiveIns.begin() + i);
481 --i; --e;
482 } else {
483 // Emit a copy.
484 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
485 TII.get(TargetOpcode::COPY), LiveIns[i].second)
486 .addReg(LiveIns[i].first);
487
488 // Add the register to the entry block live-in set.
489 EntryMBB->addLiveIn(LiveIns[i].first);
490 }
491 } else {
492 // Add the register to the entry block live-in set.
493 EntryMBB->addLiveIn(LiveIns[i].first);
494 }
495}
496
498 // Lane masks are only defined for vregs.
499 assert(Reg.isVirtual());
500 const TargetRegisterClass &TRC = *getRegClass(Reg);
501 return TRC.getLaneMask();
502}
503
504#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
506 for (MachineInstr &I : use_instructions(Reg))
507 I.dump();
508}
509#endif
510
512 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
513 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
514 "Invalid ReservedRegs vector from target");
515}
516
519
521 if (TRI->isConstantPhysReg(PhysReg))
522 return true;
523
524 // Check if any overlapping register is modified, or allocatable so it may be
525 // used later.
526 for (MCRegAliasIterator AI(PhysReg, TRI, true);
527 AI.isValid(); ++AI)
528 if (!def_empty(*AI) || isAllocatable(*AI))
529 return false;
530 return true;
531}
532
533/// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
534/// specified register as undefined which causes the DBG_VALUE to be
535/// deleted during LiveDebugVariables analysis.
537 // Mark any DBG_VALUE* that uses Reg as undef (but don't delete it.)
538 // We use make_early_inc_range because setReg invalidates the iterator.
540 if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg))
541 UseMI.setDebugValueUndef();
542 }
543}
544
546 for (const MachineOperand &MO : MI.operands()) {
547 if (!MO.isGlobal())
548 continue;
549 const Function *Func = dyn_cast<Function>(MO.getGlobal());
550 if (Func != nullptr)
551 return Func;
552 }
553 return nullptr;
554}
555
556static bool isNoReturnDef(const MachineOperand &MO) {
557 // Anything which is not a noreturn function is a real def.
558 const MachineInstr &MI = *MO.getParent();
559 if (!MI.isCall())
560 return false;
561 const MachineBasicBlock &MBB = *MI.getParent();
562 if (!MBB.succ_empty())
563 return false;
564 const MachineFunction &MF = *MBB.getParent();
565 // We need to keep correct unwind information even if the function will
566 // not return, since the runtime may need it.
567 if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
568 return false;
569 const Function *Called = getCalledFunction(MI);
570 return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
571 !Called->hasFnAttribute(Attribute::NoUnwind));
572}
573
575 bool SkipNoReturnDef) const {
576 if (UsedPhysRegMask.test(PhysReg))
577 return true;
579 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
580 for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
581 if (!SkipNoReturnDef && isNoReturnDef(MO))
582 continue;
583 return true;
584 }
585 }
586 return false;
587}
588
590 bool SkipRegMaskTest) const {
591 if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg))
592 return true;
594 for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
595 ++AliasReg) {
596 if (!reg_nodbg_empty(*AliasReg))
597 return true;
598 }
599 return false;
600}
601
603
605 assert(Reg && (Reg < TRI->getNumRegs()) &&
606 "Trying to disable an invalid register");
607
608 if (!IsUpdatedCSRsInitialized) {
609 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
610 for (const MCPhysReg *I = CSR; *I; ++I)
611 UpdatedCSRs.push_back(*I);
612
613 // Zero value represents the end of the register list
614 // (no more registers should be pushed).
615 UpdatedCSRs.push_back(0);
616
617 IsUpdatedCSRsInitialized = true;
618 }
619
620 // Remove the register (and its aliases from the list).
621 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
622 llvm::erase_value(UpdatedCSRs, *AI);
623}
624
626 if (IsUpdatedCSRsInitialized)
627 return UpdatedCSRs.data();
628
630}
631
633 if (IsUpdatedCSRsInitialized)
634 UpdatedCSRs.clear();
635
636 append_range(UpdatedCSRs, CSRs);
637
638 // Zero value represents the end of the register list
639 // (no more registers should be pushed).
640 UpdatedCSRs.push_back(0);
641 IsUpdatedCSRsInitialized = true;
642}
643
644bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
646 for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
647 bool IsRootReserved = true;
648 for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
649 Super.isValid(); ++Super) {
650 MCRegister Reg = *Super;
651 if (!isReserved(Reg)) {
652 IsRootReserved = false;
653 break;
654 }
655 }
656 if (IsRootReserved)
657 return true;
658 }
659 return false;
660}
661
663 MCRegister Reg) const {
664 return getTargetRegisterInfo()->isArgumentRegister(MF, Reg);
665}
666
668 MCRegister Reg) const {
669 return getTargetRegisterInfo()->isFixedRegister(MF, Reg);
670}
671
673 MCRegister Reg) const {
675}
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineBasicBlock & MBB
This file contains the simple types necessary to represent the attributes associated with functions a...
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:492
std::string Name
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))
static bool isNoReturnDef(const MachineOperand &MO)
static const TargetRegisterClass * constrainRegClass(MachineRegisterInfo &MRI, Register Reg, const TargetRegisterClass *OldRC, const TargetRegisterClass *RC, unsigned MinNumRegs)
unsigned const TargetRegisterInfo * TRI
static const Function * getCalledFunction(const Value *V, bool &IsNoBuiltin)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool test(unsigned Idx) const
Definition: BitVector.h:454
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:334
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:152
A debug info location.
Definition: DebugLoc.h:33
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:640
void grow(IndexT n)
Definition: IndexedMap.h:68
constexpr bool isValid() const
MCRegAliasIterator enumerates all registers aliasing Reg.
MCRegUnitRootIterator enumerates the root registers of a register unit.
bool isValid() const
Check if the iterator is at the end of the list.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
MCSuperRegIterator enumerates all super-registers of Reg.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void verifyUseList(Register Reg) const
Verify the sanity of the use list for Reg.
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
void insertVRegByName(StringRef Name, Register Reg)
bool isFixedRegister(const MachineFunction &MF, MCRegister Reg) const
Returns true if a register is a fixed register.
void verifyUseLists() const
Verify the use list of all registers.
void markUsesInDebugValueAsUndef(Register Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
iterator_range< reg_iterator > reg_operands(Register Reg) const
bool recomputeRegClass(Register Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
MachineRegisterInfo(MachineFunction *MF)
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
static def_instr_iterator def_instr_end()
void dumpUses(Register RegNo) const
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
def_iterator def_begin(Register RegNo) const
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
def_instr_iterator def_instr_begin(Register RegNo) const
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
bool isLiveIn(Register Reg) const
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
bool isGeneralPurposeRegister(const MachineFunction &MF, MCRegister Reg) const
Returns true if a register is a general purpose register.
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
ArrayRef< std::pair< MCRegister, Register > > liveins() const
bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const
hasAtMostUses - Return true if the given register has at most MaxUsers non-debug user instructions.
bool hasOneNonDBGUser(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
void setRegBank(Register Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
MCRegister getLiveInPhysReg(Register VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
static def_iterator def_end()
void disableCalleeSavedRegister(MCRegister Reg)
Disables the register from the list of CSRs.
iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const
void noteNewVirtualRegister(Register Reg)
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
const TargetRegisterInfo * getTargetRegisterInfo() const
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
bool constrainRegAttrs(Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
void noteCloneVirtualRegister(Register NewReg, Register SrcReg)
iterator_range< use_iterator > use_operands(Register Reg) const
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const
Returns true if a register can be used as an argument to a function.
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
static use_instr_nodbg_iterator use_instr_nodbg_end()
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getNumRegs() const
Return the number of registers in this class.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg is a general purpose register.
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
virtual bool isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg can be used as an argument to a function.
virtual bool isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg is a fixed register.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
virtual const TargetInstrInfo * getInstrInfo() const
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
Definition: STLExtras.h:2014
bool hasNItemsOrLess(IterTy &&Begin, IterTy &&End, unsigned N, Pred &&ShouldBeCounted=[](const decltype(*std::declval< IterTy >()) &) { return true;})
Returns true if the sequence [Begin, End) has N or less items.
Definition: STLExtras.h:2358
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:721
bool hasSingleElement(ContainerTy &&C)
Returns true if the given container only contains a single element.
Definition: STLExtras.h:379
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void erase_value(Container &C, ValueType V)
Wrapper function to remove a value from a container:
Definition: STLExtras.h:2006
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.