LLVM  15.0.0git
MachineRegisterInfo.cpp
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1 //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implementation of the MachineRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
23 #include "llvm/Config/llvm-config.h"
24 #include "llvm/IR/Attributes.h"
25 #include "llvm/IR/DebugLoc.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/Support/Casting.h"
30 #include "llvm/Support/Compiler.h"
33 #include <cassert>
34 
35 using namespace llvm;
36 
37 static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
38  cl::init(true), cl::desc("Enable subregister liveness tracking."));
39 
40 // Pin the vtable to this file.
41 void MachineRegisterInfo::Delegate::anchor() {}
42 
44  : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
46  unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
47  VRegInfo.reserve(256);
48  RegAllocHints.reserve(256);
49  UsedPhysRegMask.resize(NumRegs);
50  PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
51 }
52 
53 /// setRegClass - Set the register class of the specified virtual register.
54 ///
55 void
57  assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
58  VRegInfo[Reg].first = RC;
59 }
60 
62  const RegisterBank &RegBank) {
63  VRegInfo[Reg].first = &RegBank;
64 }
65 
66 static const TargetRegisterClass *
68  const TargetRegisterClass *OldRC,
69  const TargetRegisterClass *RC, unsigned MinNumRegs) {
70  if (OldRC == RC)
71  return RC;
72  const TargetRegisterClass *NewRC =
74  if (!NewRC || NewRC == OldRC)
75  return NewRC;
76  if (NewRC->getNumRegs() < MinNumRegs)
77  return nullptr;
78  MRI.setRegClass(Reg, NewRC);
79  return NewRC;
80 }
81 
82 const TargetRegisterClass *
84  const TargetRegisterClass *RC,
85  unsigned MinNumRegs) {
86  return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
87 }
88 
89 bool
91  Register ConstrainingReg,
92  unsigned MinNumRegs) {
93  const LLT RegTy = getType(Reg);
94  const LLT ConstrainingRegTy = getType(ConstrainingReg);
95  if (RegTy.isValid() && ConstrainingRegTy.isValid() &&
96  RegTy != ConstrainingRegTy)
97  return false;
98  const auto ConstrainingRegCB = getRegClassOrRegBank(ConstrainingReg);
99  if (!ConstrainingRegCB.isNull()) {
100  const auto RegCB = getRegClassOrRegBank(Reg);
101  if (RegCB.isNull())
102  setRegClassOrRegBank(Reg, ConstrainingRegCB);
103  else if (RegCB.is<const TargetRegisterClass *>() !=
104  ConstrainingRegCB.is<const TargetRegisterClass *>())
105  return false;
106  else if (RegCB.is<const TargetRegisterClass *>()) {
107  if (!::constrainRegClass(
108  *this, Reg, RegCB.get<const TargetRegisterClass *>(),
109  ConstrainingRegCB.get<const TargetRegisterClass *>(), MinNumRegs))
110  return false;
111  } else if (RegCB != ConstrainingRegCB)
112  return false;
113  }
114  if (ConstrainingRegTy.isValid())
115  setType(Reg, ConstrainingRegTy);
116  return true;
117 }
118 
119 bool
121  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
122  const TargetRegisterClass *OldRC = getRegClass(Reg);
123  const TargetRegisterClass *NewRC =
125 
126  // Stop early if there is no room to grow.
127  if (NewRC == OldRC)
128  return false;
129 
130  // Accumulate constraints from all uses.
131  for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
132  // Apply the effect of the given operand to NewRC.
133  MachineInstr *MI = MO.getParent();
134  unsigned OpNo = &MO - &MI->getOperand(0);
135  NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
137  if (!NewRC || NewRC == OldRC)
138  return false;
139  }
140  setRegClass(Reg, NewRC);
141  return true;
142 }
143 
146  VRegInfo.grow(Reg);
147  RegAllocHints.grow(Reg);
149  return Reg;
150 }
151 
152 /// createVirtualRegister - Create and return a new virtual register in the
153 /// function with the specified register class.
154 ///
155 Register
157  StringRef Name) {
158  assert(RegClass && "Cannot create register without RegClass!");
159  assert(RegClass->isAllocatable() &&
160  "Virtual register RegClass must be allocatable.");
161 
162  // New virtual register number.
164  VRegInfo[Reg].first = RegClass;
165  if (TheDelegate)
166  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
167  return Reg;
168 }
169 
171  StringRef Name) {
173  VRegInfo[Reg].first = VRegInfo[VReg].first;
174  setType(Reg, getType(VReg));
175  if (TheDelegate)
176  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
177  return Reg;
178 }
179 
181  VRegToType.grow(VReg);
182  VRegToType[VReg] = Ty;
183 }
184 
185 Register
187  // New virtual register number.
189  // FIXME: Should we use a dummy register class?
190  VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
191  setType(Reg, Ty);
192  if (TheDelegate)
193  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
194  return Reg;
195 }
196 
198 
199 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
201 #ifndef NDEBUG
202  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
204  if (!VRegInfo[Reg].second)
205  continue;
207  llvm_unreachable("Remaining virtual register operands");
208  }
209 #endif
210  VRegInfo.clear();
211  for (auto &I : LiveIns)
212  I.second = 0;
213 }
214 
216 #ifndef NDEBUG
217  bool Valid = true;
218  for (MachineOperand &M : reg_operands(Reg)) {
219  MachineOperand *MO = &M;
220  MachineInstr *MI = MO->getParent();
221  if (!MI) {
223  << " use list MachineOperand " << MO
224  << " has no parent instruction.\n";
225  Valid = false;
226  continue;
227  }
228  MachineOperand *MO0 = &MI->getOperand(0);
229  unsigned NumOps = MI->getNumOperands();
230  if (!(MO >= MO0 && MO < MO0+NumOps)) {
232  << " use list MachineOperand " << MO
233  << " doesn't belong to parent MI: " << *MI;
234  Valid = false;
235  }
236  if (!MO->isReg()) {
238  << " MachineOperand " << MO << ": " << *MO
239  << " is not a register\n";
240  Valid = false;
241  }
242  if (MO->getReg() != Reg) {
244  << " use-list MachineOperand " << MO << ": "
245  << *MO << " is the wrong register\n";
246  Valid = false;
247  }
248  }
249  assert(Valid && "Invalid use list");
250 #endif
251 }
252 
254 #ifndef NDEBUG
255  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
257  for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
258  verifyUseList(i);
259 #endif
260 }
261 
262 /// Add MO to the linked list of operands for its register.
264  assert(!MO->isOnRegUseList() && "Already on list");
265  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
266  MachineOperand *const Head = HeadRef;
267 
268  // Head points to the first list element.
269  // Next is NULL on the last list element.
270  // Prev pointers are circular, so Head->Prev == Last.
271 
272  // Head is NULL for an empty list.
273  if (!Head) {
274  MO->Contents.Reg.Prev = MO;
275  MO->Contents.Reg.Next = nullptr;
276  HeadRef = MO;
277  return;
278  }
279  assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
280 
281  // Insert MO between Last and Head in the circular Prev chain.
282  MachineOperand *Last = Head->Contents.Reg.Prev;
283  assert(Last && "Inconsistent use list");
284  assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
285  Head->Contents.Reg.Prev = MO;
286  MO->Contents.Reg.Prev = Last;
287 
288  // Def operands always precede uses. This allows def_iterator to stop early.
289  // Insert def operands at the front, and use operands at the back.
290  if (MO->isDef()) {
291  // Insert def at the front.
292  MO->Contents.Reg.Next = Head;
293  HeadRef = MO;
294  } else {
295  // Insert use at the end.
296  MO->Contents.Reg.Next = nullptr;
297  Last->Contents.Reg.Next = MO;
298  }
299 }
300 
301 /// Remove MO from its use-def list.
303  assert(MO->isOnRegUseList() && "Operand not on use list");
304  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
305  MachineOperand *const Head = HeadRef;
306  assert(Head && "List already empty");
307 
308  // Unlink this from the doubly linked list of operands.
309  MachineOperand *Next = MO->Contents.Reg.Next;
310  MachineOperand *Prev = MO->Contents.Reg.Prev;
311 
312  // Prev links are circular, next link is NULL instead of looping back to Head.
313  if (MO == Head)
314  HeadRef = Next;
315  else
316  Prev->Contents.Reg.Next = Next;
317 
318  (Next ? Next : Head)->Contents.Reg.Prev = Prev;
319 
320  MO->Contents.Reg.Prev = nullptr;
321  MO->Contents.Reg.Next = nullptr;
322 }
323 
324 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
325 ///
326 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
327 /// operands that won't be destroyed, which is OK because the MO destructor is
328 /// trivial anyway).
329 ///
330 /// The Src and Dst ranges may overlap.
332  MachineOperand *Src,
333  unsigned NumOps) {
334  assert(Src != Dst && NumOps && "Noop moveOperands");
335 
336  // Copy backwards if Dst is within the Src range.
337  int Stride = 1;
338  if (Dst >= Src && Dst < Src + NumOps) {
339  Stride = -1;
340  Dst += NumOps - 1;
341  Src += NumOps - 1;
342  }
343 
344  // Copy one operand at a time.
345  do {
346  new (Dst) MachineOperand(*Src);
347 
348  // Dst takes Src's place in the use-def chain.
349  if (Src->isReg()) {
350  MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
351  MachineOperand *Prev = Src->Contents.Reg.Prev;
352  MachineOperand *Next = Src->Contents.Reg.Next;
353  assert(Head && "List empty, but operand is chained");
354  assert(Prev && "Operand was not on use-def list");
355 
356  // Prev links are circular, next link is NULL instead of looping back to
357  // Head.
358  if (Src == Head)
359  Head = Dst;
360  else
361  Prev->Contents.Reg.Next = Dst;
362 
363  // Update Prev pointer. This also works when Src was pointing to itself
364  // in a 1-element list. In that case Head == Dst.
365  (Next ? Next : Head)->Contents.Reg.Prev = Dst;
366  }
367 
368  Dst += Stride;
369  Src += Stride;
370  } while (--NumOps);
371 }
372 
373 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
374 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
375 /// except that it also changes any definitions of the register as well.
376 /// If ToReg is a physical register we apply the sub register to obtain the
377 /// final/proper physical register.
379  assert(FromReg != ToReg && "Cannot replace a reg with itself");
380 
382 
383  // TODO: This could be more efficient by bulk changing the operands.
385  if (Register::isPhysicalRegister(ToReg)) {
386  O.substPhysReg(ToReg, *TRI);
387  } else {
388  O.setReg(ToReg);
389  }
390  }
391 }
392 
393 /// getVRegDef - Return the machine instr that defines the specified virtual
394 /// register or null if none is found. This assumes that the code is in SSA
395 /// form, so there should only be one definition.
397  // Since we are in SSA form, we can use the first definition.
399  assert((I.atEnd() || std::next(I) == def_instr_end()) &&
400  "getVRegDef assumes a single definition or no definition");
401  return !I.atEnd() ? &*I : nullptr;
402 }
403 
404 /// getUniqueVRegDef - Return the unique machine instr that defines the
405 /// specified virtual register or null if none is found. If there are
406 /// multiple definitions or no definition, return null.
408  if (def_empty(Reg)) return nullptr;
410  if (std::next(I) != def_instr_end())
411  return nullptr;
412  return &*I;
413 }
414 
416  return hasSingleElement(use_nodbg_operands(RegNo));
417 }
418 
421 }
422 
423 /// clearKillFlags - Iterate over all the uses of the given register and
424 /// clear the kill flag from the MachineOperand. This function is used by
425 /// optimization passes which extend register lifetimes and need only
426 /// preserve conservative kill flag information.
428  for (MachineOperand &MO : use_operands(Reg))
429  MO.setIsKill(false);
430 }
431 
433  for (const std::pair<MCRegister, Register> &LI : liveins())
434  if ((Register)LI.first == Reg || LI.second == Reg)
435  return true;
436  return false;
437 }
438 
439 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
440 /// corresponding live-in physical register.
442  for (const std::pair<MCRegister, Register> &LI : liveins())
443  if (LI.second == VReg)
444  return LI.first;
445  return MCRegister();
446 }
447 
448 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
449 /// corresponding live-in physical register.
451  for (const std::pair<MCRegister, Register> &LI : liveins())
452  if (LI.first == PReg)
453  return LI.second;
454  return Register();
455 }
456 
457 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
458 /// into the given entry block.
459 void
461  const TargetRegisterInfo &TRI,
462  const TargetInstrInfo &TII) {
463  // Emit the copies into the top of the block.
464  for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
465  if (LiveIns[i].second) {
466  if (use_nodbg_empty(LiveIns[i].second)) {
467  // The livein has no non-dbg uses. Drop it.
468  //
469  // It would be preferable to have isel avoid creating live-in
470  // records for unused arguments in the first place, but it's
471  // complicated by the debug info code for arguments.
472  LiveIns.erase(LiveIns.begin() + i);
473  --i; --e;
474  } else {
475  // Emit a copy.
476  BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
477  TII.get(TargetOpcode::COPY), LiveIns[i].second)
478  .addReg(LiveIns[i].first);
479 
480  // Add the register to the entry block live-in set.
481  EntryMBB->addLiveIn(LiveIns[i].first);
482  }
483  } else {
484  // Add the register to the entry block live-in set.
485  EntryMBB->addLiveIn(LiveIns[i].first);
486  }
487 }
488 
490  // Lane masks are only defined for vregs.
492  const TargetRegisterClass &TRC = *getRegClass(Reg);
493  return TRC.getLaneMask();
494 }
495 
496 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
499  I.dump();
500 }
501 #endif
502 
504  ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
505  assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
506  "Invalid ReservedRegs vector from target");
507 }
508 
511 
513  if (TRI->isConstantPhysReg(PhysReg))
514  return true;
515 
516  // Check if any overlapping register is modified, or allocatable so it may be
517  // used later.
518  for (MCRegAliasIterator AI(PhysReg, TRI, true);
519  AI.isValid(); ++AI)
520  if (!def_empty(*AI) || isAllocatable(*AI))
521  return false;
522  return true;
523 }
524 
525 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
526 /// specified register as undefined which causes the DBG_VALUE to be
527 /// deleted during LiveDebugVariables analysis.
529  // Mark any DBG_VALUE* that uses Reg as undef (but don't delete it.)
530  // We use make_early_inc_range because setReg invalidates the iterator.
532  if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg))
533  UseMI.setDebugValueUndef();
534  }
535 }
536 
537 static const Function *getCalledFunction(const MachineInstr &MI) {
538  for (const MachineOperand &MO : MI.operands()) {
539  if (!MO.isGlobal())
540  continue;
541  const Function *Func = dyn_cast<Function>(MO.getGlobal());
542  if (Func != nullptr)
543  return Func;
544  }
545  return nullptr;
546 }
547 
548 static bool isNoReturnDef(const MachineOperand &MO) {
549  // Anything which is not a noreturn function is a real def.
550  const MachineInstr &MI = *MO.getParent();
551  if (!MI.isCall())
552  return false;
553  const MachineBasicBlock &MBB = *MI.getParent();
554  if (!MBB.succ_empty())
555  return false;
556  const MachineFunction &MF = *MBB.getParent();
557  // We need to keep correct unwind information even if the function will
558  // not return, since the runtime may need it.
559  if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
560  return false;
561  const Function *Called = getCalledFunction(MI);
562  return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
563  !Called->hasFnAttribute(Attribute::NoUnwind));
564 }
565 
567  bool SkipNoReturnDef) const {
568  if (UsedPhysRegMask.test(PhysReg))
569  return true;
571  for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
572  for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
573  if (!SkipNoReturnDef && isNoReturnDef(MO))
574  continue;
575  return true;
576  }
577  }
578  return false;
579 }
580 
582  bool SkipRegMaskTest) const {
583  if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg))
584  return true;
586  for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
587  ++AliasReg) {
588  if (!reg_nodbg_empty(*AliasReg))
589  return true;
590  }
591  return false;
592 }
593 
595 
597  assert(Reg && (Reg < TRI->getNumRegs()) &&
598  "Trying to disable an invalid register");
599 
600  if (!IsUpdatedCSRsInitialized) {
601  const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
602  for (const MCPhysReg *I = CSR; *I; ++I)
603  UpdatedCSRs.push_back(*I);
604 
605  // Zero value represents the end of the register list
606  // (no more registers should be pushed).
607  UpdatedCSRs.push_back(0);
608 
609  IsUpdatedCSRsInitialized = true;
610  }
611 
612  // Remove the register (and its aliases from the list).
613  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
614  llvm::erase_value(UpdatedCSRs, *AI);
615 }
616 
618  if (IsUpdatedCSRsInitialized)
619  return UpdatedCSRs.data();
620 
622 }
623 
625  if (IsUpdatedCSRsInitialized)
626  UpdatedCSRs.clear();
627 
628  append_range(UpdatedCSRs, CSRs);
629 
630  // Zero value represents the end of the register list
631  // (no more registers should be pushed).
632  UpdatedCSRs.push_back(0);
633  IsUpdatedCSRsInitialized = true;
634 }
635 
636 bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
638  for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
639  bool IsRootReserved = true;
640  for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
641  Super.isValid(); ++Super) {
642  MCRegister Reg = *Super;
643  if (!isReserved(Reg)) {
644  IsRootReserved = false;
645  break;
646  }
647  }
648  if (IsRootReserved)
649  return true;
650  }
651  return false;
652 }
653 
655  MCRegister Reg) const {
657 }
658 
660  MCRegister Reg) const {
662 }
663 
665  MCRegister Reg) const {
667 }
llvm::MachineRegisterInfo::def_instr_end
static def_instr_iterator def_instr_end()
Definition: MachineRegisterInfo.h:408
llvm::LaneBitmask
Definition: LaneBitmask.h:40
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getLargestLegalSuperClass
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Definition: TargetRegisterInfo.h:788
llvm::MachineRegisterInfo::markUsesInDebugValueAsUndef
void markUsesInDebugValueAsUndef(Register Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
Definition: MachineRegisterInfo.cpp:528
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:494
llvm::MachineRegisterInfo::def_begin
def_iterator def_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:392
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::TargetRegisterInfo::isFixedRegister
virtual bool isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg is a fixed register.
Definition: TargetRegisterInfo.h:570
llvm::MachineRegisterInfo::isPhysRegUsed
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
Definition: MachineRegisterInfo.cpp:581
llvm::MachineRegisterInfo::constrainRegAttrs
bool constrainRegAttrs(Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...
Definition: MachineRegisterInfo.cpp:90
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::MachineRegisterInfo::createIncompleteVirtualRegister
Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
Definition: MachineRegisterInfo.cpp:144
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::TargetRegisterClass::getLaneMask
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
Definition: TargetRegisterInfo.h:207
llvm::TargetRegisterInfo::isGeneralPurposeRegister
virtual bool isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg is a general purpose register.
Definition: TargetRegisterInfo.h:576
llvm::TargetRegisterClass::isAllocatable
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
Definition: TargetRegisterInfo.h:118
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::TargetRegisterInfo::isArgumentRegister
virtual bool isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg can be used as an argument to a function.
Definition: TargetRegisterInfo.h:564
llvm::Function
Definition: Function.h:60
llvm::MachineRegisterInfo::recomputeRegClass
bool recomputeRegClass(Register Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
Definition: MachineRegisterInfo.cpp:120
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::MachineRegisterInfo::disableCalleeSavedRegister
void disableCalleeSavedRegister(MCRegister Reg)
Disables the register from the list of CSRs.
Definition: MachineRegisterInfo.cpp:594
llvm::MachineRegisterInfo::def_instr_begin
def_instr_iterator def_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:405
llvm::TargetRegisterInfo::isConstantPhysReg
virtual bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: TargetRegisterInfo.h:541
ErrorHandling.h
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::TargetRegisterInfo::getReservedRegs
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:151
llvm::MachineRegisterInfo::getUniqueVRegDef
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:407
llvm::MachineRegisterInfo::defusechain_instr_iterator
defusechain_iterator - This class provides iterator support for machine operands in the function that...
Definition: MachineRegisterInfo.h:277
MachineBasicBlock.h
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::MachineRegisterInfo::use_nodbg_instructions
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:551
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::IndexedMap::clear
void clear()
Definition: IndexedMap.h:64
llvm::MachineRegisterInfo::use_instructions
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:493
llvm::BitVector::resize
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:334
TargetInstrInfo.h
llvm::MachineRegisterInfo::getLiveInVirtReg
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
Definition: MachineRegisterInfo.cpp:450
llvm::MachineRegisterInfo::use_operands
iterator_range< use_iterator > use_operands(Register Reg) const
Definition: MachineRegisterInfo.h:477
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:765
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:893
isNoReturnDef
static bool isNoReturnDef(const MachineOperand &MO)
Definition: MachineRegisterInfo.cpp:548
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
MachineRegisterInfo.h
llvm::TargetRegisterInfo::getCalleeSavedRegs
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
CommandLine.h
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineRegisterInfo::use_nodbg_operands
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:534
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::MachineRegisterInfo::setRegClassOrRegBank
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
Definition: MachineRegisterInfo.h:686
llvm::MachineRegisterInfo::setType
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
Definition: MachineRegisterInfo.cpp:180
llvm::MachineRegisterInfo::Delegate::MRI_NoteNewVirtualRegister
virtual void MRI_NoteNewVirtualRegister(Register Reg)=0
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:925
llvm::BitVector::size
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:152
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::MachineRegisterInfo::reg_nodbg_operands
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:345
llvm::MachineRegisterInfo::insertVRegByName
void insertVRegByName(StringRef Name, Register Reg)
Definition: MachineRegisterInfo.h:440
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineRegisterInfo::setCalleeSavedRegs
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
Definition: MachineRegisterInfo.cpp:624
llvm::MachineRegisterInfo::freezeReservedRegs
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Definition: MachineRegisterInfo.cpp:503
DebugLoc.h
llvm::MachineRegisterInfo::clearVirtRegTypes
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
Definition: MachineRegisterInfo.cpp:197
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::erase_value
void erase_value(Container &C, ValueType V)
Wrapper function to remove a value from a container:
Definition: STLExtras.h:1815
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MCRegUnitRootIterator::isValid
bool isValid() const
Check if the iterator is at the end of the list.
Definition: MCRegisterInfo.h:773
llvm::MachineRegisterInfo::def_empty
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:434
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
llvm::MachineRegisterInfo::clearKillFlags
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Definition: MachineRegisterInfo.cpp:427
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:625
llvm::cl::opt< bool >
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:239
llvm::MachineRegisterInfo::verifyUseList
void verifyUseList(Register Reg) const
Verify the sanity of the use list for Reg.
Definition: MachineRegisterInfo.cpp:215
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineRegisterInfo::setRegBank
void setRegBank(Register Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
Definition: MachineRegisterInfo.cpp:61
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::MachineRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
Definition: MachineRegisterInfo.cpp:617
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineRegisterInfo::getLiveInPhysReg
MCRegister getLiveInPhysReg(Register VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
Definition: MachineRegisterInfo.cpp:441
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::make_early_inc_range
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:618
MCRegisterInfo.h
llvm::MachineRegisterInfo::liveins
ArrayRef< std::pair< MCRegister, Register > > liveins() const
Definition: MachineRegisterInfo.h:966
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineRegisterInfo::reg_operands
iterator_range< reg_iterator > reg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:294
llvm::MachineRegisterInfo::isAllocatable
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
Definition: MachineRegisterInfo.h:943
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:289
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:644
iterator_range.h
llvm::MachineRegisterInfo::isArgumentRegister
bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const
Returns true if a register can be used as an argument to a function.
Definition: MachineRegisterInfo.cpp:654
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:186
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineRegisterInfo::def_end
static def_iterator def_end()
Definition: MachineRegisterInfo.h:395
llvm::MachineRegisterInfo::getRegClassOrRegBank
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
Definition: MachineRegisterInfo.h:676
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineRegisterInfo::use_nodbg_empty
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Definition: MachineRegisterInfo.h:574
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:357
llvm::hasSingleElement
bool hasSingleElement(ContainerTy &&C)
Returns true if the given container only contains a single element.
Definition: STLExtras.h:273
llvm::IndexedMap::grow
void grow(IndexT n)
Definition: IndexedMap.h:68
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:415
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MachineRegisterInfo::isFixedRegister
bool isFixedRegister(const MachineFunction &MF, MCRegister Reg) const
Returns true if a register is a fixed register.
Definition: MachineRegisterInfo.cpp:659
Compiler.h
llvm::append_range
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
Definition: STLExtras.h:1823
TargetSubtargetInfo.h
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
llvm::MachineRegisterInfo::removeRegOperandFromUseList
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Definition: MachineRegisterInfo.cpp:302
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:377
llvm::MachineRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: MachineRegisterInfo.cpp:509
llvm::MachineRegisterInfo::replaceRegWith
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
Definition: MachineRegisterInfo.cpp:378
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
EnableSubRegLiveness
static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))
Attributes.h
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:454
llvm::MachineRegisterInfo::addRegOperandToUseList
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Definition: MachineRegisterInfo.cpp:263
llvm::MachineRegisterInfo::isLiveIn
bool isLiveIn(Register Reg) const
Definition: MachineRegisterInfo.cpp:432
llvm::TargetRegisterClass::getNumRegs
unsigned getNumRegs() const
Return the number of registers in this class.
Definition: TargetRegisterInfo.h:80
llvm::MachineRegisterInfo::getMaxLaneMaskForVReg
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Definition: MachineRegisterInfo.cpp:489
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
uint16_t
Casting.h
Function.h
getCalledFunction
static const Function * getCalledFunction(const MachineInstr &MI)
Definition: MachineRegisterInfo.cpp:537
llvm::MachineRegisterInfo::clearVirtRegs
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
Definition: MachineRegisterInfo.cpp:200
constrainRegClass
static const TargetRegisterClass * constrainRegClass(MachineRegisterInfo &MRI, Register Reg, const TargetRegisterClass *OldRC, const TargetRegisterClass *RC, unsigned MinNumRegs)
Definition: MachineRegisterInfo.cpp:67
llvm::MachineRegisterInfo::isPhysRegModified
bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
Definition: MachineRegisterInfo.cpp:566
llvm::MachineRegisterInfo::hasOneNonDBGUser
bool hasOneNonDBGUser(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
Definition: MachineRegisterInfo.cpp:419
llvm::VRegInfo
Definition: MIParser.h:37
llvm::MCRegUnitRootIterator
MCRegUnitRootIterator enumerates the root registers of a register unit.
Definition: MCRegisterInfo.h:754
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:813
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:278
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:740
MachineInstrBuilder.h
llvm::MachineRegisterInfo::cloneVirtualRegister
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
Definition: MachineRegisterInfo.cpp:170
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::MachineRegisterInfo::isGeneralPurposeRegister
bool isGeneralPurposeRegister(const MachineFunction &MF, MCRegister Reg) const
Returns true if a register is a general purpose register.
Definition: MachineRegisterInfo.cpp:664
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:83
MachineOperand.h
llvm::MachineRegisterInfo::MachineRegisterInfo
MachineRegisterInfo(MachineFunction *MF)
Definition: MachineRegisterInfo.cpp:43
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineRegisterInfo::isReservedRegUnit
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
Definition: MachineRegisterInfo.cpp:636
llvm::cl::desc
Definition: CommandLine.h:405
llvm::MachineRegisterInfo::reg_nodbg_empty
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition: MachineRegisterInfo.h:385
raw_ostream.h
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::MachineRegisterInfo::dumpUses
void dumpUses(Register RegNo) const
Definition: MachineRegisterInfo.cpp:497
llvm::MachineRegisterInfo::moveOperands
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
Definition: MachineRegisterInfo.cpp:331
TargetRegisterInfo.h
llvm::MachineRegisterInfo::EmitLiveInCopies
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.
Definition: MachineRegisterInfo.cpp:460
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:56
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
llvm::MachineRegisterInfo::verifyUseLists
void verifyUseLists() const
Verify the use list of all registers.
Definition: MachineRegisterInfo.cpp:253
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::LLT
Definition: LowLevelTypeImpl.h:39