LLVM 19.0.0git
MachineRegisterInfo.cpp
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1//===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implementation of the MachineRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
23#include "llvm/Config/llvm-config.h"
24#include "llvm/IR/Attributes.h"
25#include "llvm/IR/DebugLoc.h"
26#include "llvm/IR/Function.h"
33#include <cassert>
34
35using namespace llvm;
36
37static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
38 cl::init(true), cl::desc("Enable subregister liveness tracking."));
39
40// Pin the vtable to this file.
41void MachineRegisterInfo::Delegate::anchor() {}
42
44 : MF(MF),
45 TracksSubRegLiveness(EnableSubRegLiveness.getNumOccurrences()
47 : MF->getSubtarget().enableSubRegLiveness()) {
48 unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
49 VRegInfo.reserve(256);
50 RegAllocHints.reserve(256);
51 UsedPhysRegMask.resize(NumRegs);
52 PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
53 TheDelegates.clear();
54}
55
56/// setRegClass - Set the register class of the specified virtual register.
57///
58void
60 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
61 VRegInfo[Reg].first = RC;
62}
63
65 const RegisterBank &RegBank) {
66 VRegInfo[Reg].first = &RegBank;
67}
68
69static const TargetRegisterClass *
71 const TargetRegisterClass *OldRC,
72 const TargetRegisterClass *RC, unsigned MinNumRegs) {
73 if (OldRC == RC)
74 return RC;
75 const TargetRegisterClass *NewRC =
76 MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
77 if (!NewRC || NewRC == OldRC)
78 return NewRC;
79 if (NewRC->getNumRegs() < MinNumRegs)
80 return nullptr;
81 MRI.setRegClass(Reg, NewRC);
82 return NewRC;
83}
84
86 Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) {
87 if (Reg.isPhysical())
88 return nullptr;
89 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
90}
91
92bool
94 Register ConstrainingReg,
95 unsigned MinNumRegs) {
96 const LLT RegTy = getType(Reg);
97 const LLT ConstrainingRegTy = getType(ConstrainingReg);
98 if (RegTy.isValid() && ConstrainingRegTy.isValid() &&
99 RegTy != ConstrainingRegTy)
100 return false;
101 const auto &ConstrainingRegCB = getRegClassOrRegBank(ConstrainingReg);
102 if (!ConstrainingRegCB.isNull()) {
103 const auto &RegCB = getRegClassOrRegBank(Reg);
104 if (RegCB.isNull())
105 setRegClassOrRegBank(Reg, ConstrainingRegCB);
106 else if (isa<const TargetRegisterClass *>(RegCB) !=
107 isa<const TargetRegisterClass *>(ConstrainingRegCB))
108 return false;
109 else if (isa<const TargetRegisterClass *>(RegCB)) {
111 *this, Reg, cast<const TargetRegisterClass *>(RegCB),
112 cast<const TargetRegisterClass *>(ConstrainingRegCB), MinNumRegs))
113 return false;
114 } else if (RegCB != ConstrainingRegCB)
115 return false;
116 }
117 if (ConstrainingRegTy.isValid())
118 setType(Reg, ConstrainingRegTy);
119 return true;
120}
121
122bool
125 const TargetRegisterClass *OldRC = getRegClass(Reg);
126 const TargetRegisterClass *NewRC =
128
129 // Stop early if there is no room to grow.
130 if (NewRC == OldRC)
131 return false;
132
133 // Accumulate constraints from all uses.
134 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
135 // Apply the effect of the given operand to NewRC.
136 MachineInstr *MI = MO.getParent();
137 unsigned OpNo = &MO - &MI->getOperand(0);
138 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
140 if (!NewRC || NewRC == OldRC)
141 return false;
142 }
143 setRegClass(Reg, NewRC);
144 return true;
145}
146
149 VRegInfo.grow(Reg);
150 RegAllocHints.grow(Reg);
152 return Reg;
153}
154
155/// createVirtualRegister - Create and return a new virtual register in the
156/// function with the specified register class.
157///
160 StringRef Name) {
161 assert(RegClass && "Cannot create register without RegClass!");
162 assert(RegClass->isAllocatable() &&
163 "Virtual register RegClass must be allocatable.");
164
165 // New virtual register number.
167 VRegInfo[Reg].first = RegClass;
169 return Reg;
170}
171
173 StringRef Name) {
175 VRegInfo[Reg].first = RegAttr.RCOrRB;
176 setType(Reg, RegAttr.Ty);
178 return Reg;
179}
180
182 StringRef Name) {
184 VRegInfo[Reg].first = VRegInfo[VReg].first;
185 setType(Reg, getType(VReg));
186 noteCloneVirtualRegister(Reg, VReg);
187 return Reg;
188}
189
191 VRegToType.grow(VReg);
192 VRegToType[VReg] = Ty;
193}
194
197 // New virtual register number.
199 // FIXME: Should we use a dummy register class?
200 VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
201 setType(Reg, Ty);
203 return Reg;
204}
205
207
208/// clearVirtRegs - Remove all virtual registers (after physreg assignment).
210#ifndef NDEBUG
211 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
213 if (!VRegInfo[Reg].second)
214 continue;
215 verifyUseList(Reg);
216 errs() << "Remaining virtual register "
217 << printReg(Reg, getTargetRegisterInfo()) << "...\n";
218 for (MachineInstr &MI : reg_instructions(Reg))
219 errs() << "...in instruction: " << MI << "\n";
220 std::abort();
221 }
222#endif
223 VRegInfo.clear();
224 for (auto &I : LiveIns)
225 I.second = 0;
226}
227
229#ifndef NDEBUG
230 bool Valid = true;
231 for (MachineOperand &M : reg_operands(Reg)) {
232 MachineOperand *MO = &M;
233 MachineInstr *MI = MO->getParent();
234 if (!MI) {
236 << " use list MachineOperand " << MO
237 << " has no parent instruction.\n";
238 Valid = false;
239 continue;
240 }
241 MachineOperand *MO0 = &MI->getOperand(0);
242 unsigned NumOps = MI->getNumOperands();
243 if (!(MO >= MO0 && MO < MO0+NumOps)) {
245 << " use list MachineOperand " << MO
246 << " doesn't belong to parent MI: " << *MI;
247 Valid = false;
248 }
249 if (!MO->isReg()) {
251 << " MachineOperand " << MO << ": " << *MO
252 << " is not a register\n";
253 Valid = false;
254 }
255 if (MO->getReg() != Reg) {
257 << " use-list MachineOperand " << MO << ": "
258 << *MO << " is the wrong register\n";
259 Valid = false;
260 }
261 }
262 assert(Valid && "Invalid use list");
263#endif
264}
265
267#ifndef NDEBUG
268 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
270 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
271 verifyUseList(i);
272#endif
273}
274
275/// Add MO to the linked list of operands for its register.
277 assert(!MO->isOnRegUseList() && "Already on list");
278 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
279 MachineOperand *const Head = HeadRef;
280
281 // Head points to the first list element.
282 // Next is NULL on the last list element.
283 // Prev pointers are circular, so Head->Prev == Last.
284
285 // Head is NULL for an empty list.
286 if (!Head) {
287 MO->Contents.Reg.Prev = MO;
288 MO->Contents.Reg.Next = nullptr;
289 HeadRef = MO;
290 return;
291 }
292 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
293
294 // Insert MO between Last and Head in the circular Prev chain.
295 MachineOperand *Last = Head->Contents.Reg.Prev;
296 assert(Last && "Inconsistent use list");
297 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
298 Head->Contents.Reg.Prev = MO;
299 MO->Contents.Reg.Prev = Last;
300
301 // Def operands always precede uses. This allows def_iterator to stop early.
302 // Insert def operands at the front, and use operands at the back.
303 if (MO->isDef()) {
304 // Insert def at the front.
305 MO->Contents.Reg.Next = Head;
306 HeadRef = MO;
307 } else {
308 // Insert use at the end.
309 MO->Contents.Reg.Next = nullptr;
310 Last->Contents.Reg.Next = MO;
311 }
312}
313
314/// Remove MO from its use-def list.
316 assert(MO->isOnRegUseList() && "Operand not on use list");
317 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
318 MachineOperand *const Head = HeadRef;
319 assert(Head && "List already empty");
320
321 // Unlink this from the doubly linked list of operands.
322 MachineOperand *Next = MO->Contents.Reg.Next;
323 MachineOperand *Prev = MO->Contents.Reg.Prev;
324
325 // Prev links are circular, next link is NULL instead of looping back to Head.
326 if (MO == Head)
327 HeadRef = Next;
328 else
329 Prev->Contents.Reg.Next = Next;
330
331 (Next ? Next : Head)->Contents.Reg.Prev = Prev;
332
333 MO->Contents.Reg.Prev = nullptr;
334 MO->Contents.Reg.Next = nullptr;
335}
336
337/// Move NumOps operands from Src to Dst, updating use-def lists as needed.
338///
339/// The Dst range is assumed to be uninitialized memory. (Or it may contain
340/// operands that won't be destroyed, which is OK because the MO destructor is
341/// trivial anyway).
342///
343/// The Src and Dst ranges may overlap.
345 MachineOperand *Src,
346 unsigned NumOps) {
347 assert(Src != Dst && NumOps && "Noop moveOperands");
348
349 // Copy backwards if Dst is within the Src range.
350 int Stride = 1;
351 if (Dst >= Src && Dst < Src + NumOps) {
352 Stride = -1;
353 Dst += NumOps - 1;
354 Src += NumOps - 1;
355 }
356
357 // Copy one operand at a time.
358 do {
359 new (Dst) MachineOperand(*Src);
360
361 // Dst takes Src's place in the use-def chain.
362 if (Src->isReg()) {
363 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
364 MachineOperand *Prev = Src->Contents.Reg.Prev;
365 MachineOperand *Next = Src->Contents.Reg.Next;
366 assert(Head && "List empty, but operand is chained");
367 assert(Prev && "Operand was not on use-def list");
368
369 // Prev links are circular, next link is NULL instead of looping back to
370 // Head.
371 if (Src == Head)
372 Head = Dst;
373 else
374 Prev->Contents.Reg.Next = Dst;
375
376 // Update Prev pointer. This also works when Src was pointing to itself
377 // in a 1-element list. In that case Head == Dst.
378 (Next ? Next : Head)->Contents.Reg.Prev = Dst;
379 }
380
381 Dst += Stride;
382 Src += Stride;
383 } while (--NumOps);
384}
385
386/// replaceRegWith - Replace all instances of FromReg with ToReg in the
387/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
388/// except that it also changes any definitions of the register as well.
389/// If ToReg is a physical register we apply the sub register to obtain the
390/// final/proper physical register.
392 assert(FromReg != ToReg && "Cannot replace a reg with itself");
393
395
396 // TODO: This could be more efficient by bulk changing the operands.
398 if (ToReg.isPhysical()) {
399 O.substPhysReg(ToReg, *TRI);
400 } else {
401 O.setReg(ToReg);
402 }
403 }
404}
405
406/// getVRegDef - Return the machine instr that defines the specified virtual
407/// register or null if none is found. This assumes that the code is in SSA
408/// form, so there should only be one definition.
410 // Since we are in SSA form, we can use the first definition.
412 assert((I.atEnd() || std::next(I) == def_instr_end()) &&
413 "getVRegDef assumes a single definition or no definition");
414 return !I.atEnd() ? &*I : nullptr;
415}
416
417/// getUniqueVRegDef - Return the unique machine instr that defines the
418/// specified virtual register or null if none is found. If there are
419/// multiple definitions or no definition, return null.
421 if (def_empty(Reg)) return nullptr;
423 if (std::next(I) != def_instr_end())
424 return nullptr;
425 return &*I;
426}
427
430}
431
434}
435
437 unsigned MaxUsers) const {
439 MaxUsers);
440}
441
442/// clearKillFlags - Iterate over all the uses of the given register and
443/// clear the kill flag from the MachineOperand. This function is used by
444/// optimization passes which extend register lifetimes and need only
445/// preserve conservative kill flag information.
447 for (MachineOperand &MO : use_operands(Reg))
448 MO.setIsKill(false);
449}
450
452 for (const std::pair<MCRegister, Register> &LI : liveins())
453 if ((Register)LI.first == Reg || LI.second == Reg)
454 return true;
455 return false;
456}
457
458/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
459/// corresponding live-in physical register.
461 for (const std::pair<MCRegister, Register> &LI : liveins())
462 if (LI.second == VReg)
463 return LI.first;
464 return MCRegister();
465}
466
467/// getLiveInVirtReg - If PReg is a live-in physical register, return the
468/// corresponding live-in physical register.
470 for (const std::pair<MCRegister, Register> &LI : liveins())
471 if (LI.first == PReg)
472 return LI.second;
473 return Register();
474}
475
476/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
477/// into the given entry block.
478void
480 const TargetRegisterInfo &TRI,
481 const TargetInstrInfo &TII) {
482 // Emit the copies into the top of the block.
483 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
484 if (LiveIns[i].second) {
485 if (use_nodbg_empty(LiveIns[i].second)) {
486 // The livein has no non-dbg uses. Drop it.
487 //
488 // It would be preferable to have isel avoid creating live-in
489 // records for unused arguments in the first place, but it's
490 // complicated by the debug info code for arguments.
491 LiveIns.erase(LiveIns.begin() + i);
492 --i; --e;
493 } else {
494 // Emit a copy.
495 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
496 TII.get(TargetOpcode::COPY), LiveIns[i].second)
497 .addReg(LiveIns[i].first);
498
499 // Add the register to the entry block live-in set.
500 EntryMBB->addLiveIn(LiveIns[i].first);
501 }
502 } else {
503 // Add the register to the entry block live-in set.
504 EntryMBB->addLiveIn(LiveIns[i].first);
505 }
506}
507
509 // Lane masks are only defined for vregs.
510 assert(Reg.isVirtual());
511 const TargetRegisterClass &TRC = *getRegClass(Reg);
512 return TRC.getLaneMask();
513}
514
515#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
517 for (MachineInstr &I : use_instructions(Reg))
518 I.dump();
519}
520#endif
521
523 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(*MF);
524 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
525 "Invalid ReservedRegs vector from target");
526}
527
530
532 if (TRI->isConstantPhysReg(PhysReg))
533 return true;
534
535 // Check if any overlapping register is modified, or allocatable so it may be
536 // used later.
537 for (MCRegAliasIterator AI(PhysReg, TRI, true);
538 AI.isValid(); ++AI)
539 if (!def_empty(*AI) || isAllocatable(*AI))
540 return false;
541 return true;
542}
543
544/// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
545/// specified register as undefined which causes the DBG_VALUE to be
546/// deleted during LiveDebugVariables analysis.
548 // Mark any DBG_VALUE* that uses Reg as undef (but don't delete it.)
549 // We use make_early_inc_range because setReg invalidates the iterator.
551 if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg))
552 UseMI.setDebugValueUndef();
553 }
554}
555
557 for (const MachineOperand &MO : MI.operands()) {
558 if (!MO.isGlobal())
559 continue;
560 const Function *Func = dyn_cast<Function>(MO.getGlobal());
561 if (Func != nullptr)
562 return Func;
563 }
564 return nullptr;
565}
566
567static bool isNoReturnDef(const MachineOperand &MO) {
568 // Anything which is not a noreturn function is a real def.
569 const MachineInstr &MI = *MO.getParent();
570 if (!MI.isCall())
571 return false;
572 const MachineBasicBlock &MBB = *MI.getParent();
573 if (!MBB.succ_empty())
574 return false;
575 const MachineFunction &MF = *MBB.getParent();
576 // We need to keep correct unwind information even if the function will
577 // not return, since the runtime may need it.
578 if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
579 return false;
580 const Function *Called = getCalledFunction(MI);
581 return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
582 !Called->hasFnAttribute(Attribute::NoUnwind));
583}
584
586 bool SkipNoReturnDef) const {
587 if (UsedPhysRegMask.test(PhysReg))
588 return true;
590 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
591 for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
592 if (!SkipNoReturnDef && isNoReturnDef(MO))
593 continue;
594 return true;
595 }
596 }
597 return false;
598}
599
601 bool SkipRegMaskTest) const {
602 if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg))
603 return true;
605 for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
606 ++AliasReg) {
607 if (!reg_nodbg_empty(*AliasReg))
608 return true;
609 }
610 return false;
611}
612
614
616 assert(Reg && (Reg < TRI->getNumRegs()) &&
617 "Trying to disable an invalid register");
618
619 if (!IsUpdatedCSRsInitialized) {
620 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
621 for (const MCPhysReg *I = CSR; *I; ++I)
622 UpdatedCSRs.push_back(*I);
623
624 // Zero value represents the end of the register list
625 // (no more registers should be pushed).
626 UpdatedCSRs.push_back(0);
627
628 IsUpdatedCSRsInitialized = true;
629 }
630
631 // Remove the register (and its aliases from the list).
632 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
633 llvm::erase(UpdatedCSRs, *AI);
634}
635
637 if (IsUpdatedCSRsInitialized)
638 return UpdatedCSRs.data();
639
641}
642
644 if (IsUpdatedCSRsInitialized)
645 UpdatedCSRs.clear();
646
647 append_range(UpdatedCSRs, CSRs);
648
649 // Zero value represents the end of the register list
650 // (no more registers should be pushed).
651 UpdatedCSRs.push_back(0);
652 IsUpdatedCSRsInitialized = true;
653}
654
655bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
657 for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
658 if (all_of(TRI->superregs_inclusive(*Root),
659 [&](MCPhysReg Super) { return isReserved(Super); }))
660 return true;
661 }
662 return false;
663}
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineBasicBlock & MBB
This file contains the simple types necessary to represent the attributes associated with functions a...
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:537
std::string Name
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))
static bool isNoReturnDef(const MachineOperand &MO)
static const TargetRegisterClass * constrainRegClass(MachineRegisterInfo &MRI, Register Reg, const TargetRegisterClass *OldRC, const TargetRegisterClass *RC, unsigned MinNumRegs)
unsigned const TargetRegisterInfo * TRI
static const Function * getCalledFunction(const Value *V, bool &IsNoBuiltin)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool test(unsigned Idx) const
Definition: BitVector.h:461
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:341
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:159
A debug info location.
Definition: DebugLoc.h:33
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:719
void grow(IndexT n)
Definition: IndexedMap.h:69
constexpr bool isValid() const
Definition: LowLevelType.h:145
MCRegAliasIterator enumerates all registers aliasing Reg.
MCRegUnitRootIterator enumerates the root registers of a register unit.
bool isValid() const
Check if the iterator is at the end of the list.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void verifyUseList(Register Reg) const
Verify the sanity of the use list for Reg.
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
void insertVRegByName(StringRef Name, Register Reg)
void verifyUseLists() const
Verify the use list of all registers.
void markUsesInDebugValueAsUndef(Register Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
iterator_range< reg_iterator > reg_operands(Register Reg) const
bool recomputeRegClass(Register Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
void freezeReservedRegs()
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
MachineRegisterInfo(MachineFunction *MF)
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
static def_instr_iterator def_instr_end()
void dumpUses(Register RegNo) const
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
def_iterator def_begin(Register RegNo) const
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
def_instr_iterator def_instr_begin(Register RegNo) const
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
bool isLiveIn(Register Reg) const
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
ArrayRef< std::pair< MCRegister, Register > > liveins() const
bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const
hasAtMostUses - Return true if the given register has at most MaxUsers non-debug user instructions.
bool hasOneNonDBGUser(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
void setRegBank(Register Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
MCRegister getLiveInPhysReg(Register VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
static def_iterator def_end()
void disableCalleeSavedRegister(MCRegister Reg)
Disables the register from the list of CSRs.
iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const
void noteNewVirtualRegister(Register Reg)
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
const TargetRegisterInfo * getTargetRegisterInfo() const
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
bool constrainRegAttrs(Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
void noteCloneVirtualRegister(Register NewReg, Register SrcReg)
iterator_range< use_iterator > use_operands(Register Reg) const
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
static use_instr_nodbg_iterator use_instr_nodbg_end()
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getNumRegs() const
Return the number of registers in this class.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
virtual const TargetInstrInfo * getInstrInfo() const
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1722
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
Definition: STLExtras.h:2067
bool hasNItemsOrLess(IterTy &&Begin, IterTy &&End, unsigned N, Pred &&ShouldBeCounted=[](const decltype(*std::declval< IterTy >()) &) { return true;})
Returns true if the sequence [Begin, End) has N or less items.
Definition: STLExtras.h:2505
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:656
void erase(Container &C, ValueType V)
Wrapper function to remove a value from a container:
Definition: STLExtras.h:2059
bool hasSingleElement(ContainerTy &&C)
Returns true if the given container only contains a single element.
Definition: STLExtras.h:322
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
All attributes(register class or bank and low-level type) a virtual register can have.