LLVM 19.0.0git
MachineRegisterInfo.cpp
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1//===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implementation of the MachineRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
23#include "llvm/Config/llvm-config.h"
24#include "llvm/IR/Attributes.h"
25#include "llvm/IR/DebugLoc.h"
26#include "llvm/IR/Function.h"
33#include <cassert>
34
35using namespace llvm;
36
37static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
38 cl::init(true), cl::desc("Enable subregister liveness tracking."));
39
40// Pin the vtable to this file.
41void MachineRegisterInfo::Delegate::anchor() {}
42
44 : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
46 unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
47 VRegInfo.reserve(256);
48 RegAllocHints.reserve(256);
49 UsedPhysRegMask.resize(NumRegs);
50 PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
51 TheDelegates.clear();
52}
53
54/// setRegClass - Set the register class of the specified virtual register.
55///
56void
58 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
59 VRegInfo[Reg].first = RC;
60}
61
63 const RegisterBank &RegBank) {
64 VRegInfo[Reg].first = &RegBank;
65}
66
67static const TargetRegisterClass *
69 const TargetRegisterClass *OldRC,
70 const TargetRegisterClass *RC, unsigned MinNumRegs) {
71 if (OldRC == RC)
72 return RC;
73 const TargetRegisterClass *NewRC =
74 MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
75 if (!NewRC || NewRC == OldRC)
76 return NewRC;
77 if (NewRC->getNumRegs() < MinNumRegs)
78 return nullptr;
79 MRI.setRegClass(Reg, NewRC);
80 return NewRC;
81}
82
84 Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) {
85 if (Reg.isPhysical())
86 return nullptr;
87 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
88}
89
90bool
92 Register ConstrainingReg,
93 unsigned MinNumRegs) {
94 const LLT RegTy = getType(Reg);
95 const LLT ConstrainingRegTy = getType(ConstrainingReg);
96 if (RegTy.isValid() && ConstrainingRegTy.isValid() &&
97 RegTy != ConstrainingRegTy)
98 return false;
99 const auto &ConstrainingRegCB = getRegClassOrRegBank(ConstrainingReg);
100 if (!ConstrainingRegCB.isNull()) {
101 const auto &RegCB = getRegClassOrRegBank(Reg);
102 if (RegCB.isNull())
103 setRegClassOrRegBank(Reg, ConstrainingRegCB);
104 else if (isa<const TargetRegisterClass *>(RegCB) !=
105 isa<const TargetRegisterClass *>(ConstrainingRegCB))
106 return false;
107 else if (isa<const TargetRegisterClass *>(RegCB)) {
109 *this, Reg, cast<const TargetRegisterClass *>(RegCB),
110 cast<const TargetRegisterClass *>(ConstrainingRegCB), MinNumRegs))
111 return false;
112 } else if (RegCB != ConstrainingRegCB)
113 return false;
114 }
115 if (ConstrainingRegTy.isValid())
116 setType(Reg, ConstrainingRegTy);
117 return true;
118}
119
120bool
123 const TargetRegisterClass *OldRC = getRegClass(Reg);
124 const TargetRegisterClass *NewRC =
126
127 // Stop early if there is no room to grow.
128 if (NewRC == OldRC)
129 return false;
130
131 // Accumulate constraints from all uses.
132 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
133 // Apply the effect of the given operand to NewRC.
134 MachineInstr *MI = MO.getParent();
135 unsigned OpNo = &MO - &MI->getOperand(0);
136 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
138 if (!NewRC || NewRC == OldRC)
139 return false;
140 }
141 setRegClass(Reg, NewRC);
142 return true;
143}
144
147 VRegInfo.grow(Reg);
148 RegAllocHints.grow(Reg);
150 return Reg;
151}
152
153/// createVirtualRegister - Create and return a new virtual register in the
154/// function with the specified register class.
155///
158 StringRef Name) {
159 assert(RegClass && "Cannot create register without RegClass!");
160 assert(RegClass->isAllocatable() &&
161 "Virtual register RegClass must be allocatable.");
162
163 // New virtual register number.
165 VRegInfo[Reg].first = RegClass;
167 return Reg;
168}
169
171 StringRef Name) {
173 VRegInfo[Reg].first = RegAttr.RCOrRB;
174 setType(Reg, RegAttr.Ty);
176 return Reg;
177}
178
180 StringRef Name) {
182 VRegInfo[Reg].first = VRegInfo[VReg].first;
183 setType(Reg, getType(VReg));
184 noteCloneVirtualRegister(Reg, VReg);
185 return Reg;
186}
187
189 VRegToType.grow(VReg);
190 VRegToType[VReg] = Ty;
191}
192
195 // New virtual register number.
197 // FIXME: Should we use a dummy register class?
198 VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
199 setType(Reg, Ty);
201 return Reg;
202}
203
205
206/// clearVirtRegs - Remove all virtual registers (after physreg assignment).
208#ifndef NDEBUG
209 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
211 if (!VRegInfo[Reg].second)
212 continue;
213 verifyUseList(Reg);
214 errs() << "Remaining virtual register "
215 << printReg(Reg, getTargetRegisterInfo()) << "...\n";
216 for (MachineInstr &MI : reg_instructions(Reg))
217 errs() << "...in instruction: " << MI << "\n";
218 std::abort();
219 }
220#endif
221 VRegInfo.clear();
222 for (auto &I : LiveIns)
223 I.second = 0;
224}
225
227#ifndef NDEBUG
228 bool Valid = true;
229 for (MachineOperand &M : reg_operands(Reg)) {
230 MachineOperand *MO = &M;
231 MachineInstr *MI = MO->getParent();
232 if (!MI) {
234 << " use list MachineOperand " << MO
235 << " has no parent instruction.\n";
236 Valid = false;
237 continue;
238 }
239 MachineOperand *MO0 = &MI->getOperand(0);
240 unsigned NumOps = MI->getNumOperands();
241 if (!(MO >= MO0 && MO < MO0+NumOps)) {
243 << " use list MachineOperand " << MO
244 << " doesn't belong to parent MI: " << *MI;
245 Valid = false;
246 }
247 if (!MO->isReg()) {
249 << " MachineOperand " << MO << ": " << *MO
250 << " is not a register\n";
251 Valid = false;
252 }
253 if (MO->getReg() != Reg) {
255 << " use-list MachineOperand " << MO << ": "
256 << *MO << " is the wrong register\n";
257 Valid = false;
258 }
259 }
260 assert(Valid && "Invalid use list");
261#endif
262}
263
265#ifndef NDEBUG
266 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
268 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
269 verifyUseList(i);
270#endif
271}
272
273/// Add MO to the linked list of operands for its register.
275 assert(!MO->isOnRegUseList() && "Already on list");
276 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
277 MachineOperand *const Head = HeadRef;
278
279 // Head points to the first list element.
280 // Next is NULL on the last list element.
281 // Prev pointers are circular, so Head->Prev == Last.
282
283 // Head is NULL for an empty list.
284 if (!Head) {
285 MO->Contents.Reg.Prev = MO;
286 MO->Contents.Reg.Next = nullptr;
287 HeadRef = MO;
288 return;
289 }
290 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
291
292 // Insert MO between Last and Head in the circular Prev chain.
293 MachineOperand *Last = Head->Contents.Reg.Prev;
294 assert(Last && "Inconsistent use list");
295 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
296 Head->Contents.Reg.Prev = MO;
297 MO->Contents.Reg.Prev = Last;
298
299 // Def operands always precede uses. This allows def_iterator to stop early.
300 // Insert def operands at the front, and use operands at the back.
301 if (MO->isDef()) {
302 // Insert def at the front.
303 MO->Contents.Reg.Next = Head;
304 HeadRef = MO;
305 } else {
306 // Insert use at the end.
307 MO->Contents.Reg.Next = nullptr;
308 Last->Contents.Reg.Next = MO;
309 }
310}
311
312/// Remove MO from its use-def list.
314 assert(MO->isOnRegUseList() && "Operand not on use list");
315 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
316 MachineOperand *const Head = HeadRef;
317 assert(Head && "List already empty");
318
319 // Unlink this from the doubly linked list of operands.
320 MachineOperand *Next = MO->Contents.Reg.Next;
321 MachineOperand *Prev = MO->Contents.Reg.Prev;
322
323 // Prev links are circular, next link is NULL instead of looping back to Head.
324 if (MO == Head)
325 HeadRef = Next;
326 else
327 Prev->Contents.Reg.Next = Next;
328
329 (Next ? Next : Head)->Contents.Reg.Prev = Prev;
330
331 MO->Contents.Reg.Prev = nullptr;
332 MO->Contents.Reg.Next = nullptr;
333}
334
335/// Move NumOps operands from Src to Dst, updating use-def lists as needed.
336///
337/// The Dst range is assumed to be uninitialized memory. (Or it may contain
338/// operands that won't be destroyed, which is OK because the MO destructor is
339/// trivial anyway).
340///
341/// The Src and Dst ranges may overlap.
343 MachineOperand *Src,
344 unsigned NumOps) {
345 assert(Src != Dst && NumOps && "Noop moveOperands");
346
347 // Copy backwards if Dst is within the Src range.
348 int Stride = 1;
349 if (Dst >= Src && Dst < Src + NumOps) {
350 Stride = -1;
351 Dst += NumOps - 1;
352 Src += NumOps - 1;
353 }
354
355 // Copy one operand at a time.
356 do {
357 new (Dst) MachineOperand(*Src);
358
359 // Dst takes Src's place in the use-def chain.
360 if (Src->isReg()) {
361 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
362 MachineOperand *Prev = Src->Contents.Reg.Prev;
363 MachineOperand *Next = Src->Contents.Reg.Next;
364 assert(Head && "List empty, but operand is chained");
365 assert(Prev && "Operand was not on use-def list");
366
367 // Prev links are circular, next link is NULL instead of looping back to
368 // Head.
369 if (Src == Head)
370 Head = Dst;
371 else
372 Prev->Contents.Reg.Next = Dst;
373
374 // Update Prev pointer. This also works when Src was pointing to itself
375 // in a 1-element list. In that case Head == Dst.
376 (Next ? Next : Head)->Contents.Reg.Prev = Dst;
377 }
378
379 Dst += Stride;
380 Src += Stride;
381 } while (--NumOps);
382}
383
384/// replaceRegWith - Replace all instances of FromReg with ToReg in the
385/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
386/// except that it also changes any definitions of the register as well.
387/// If ToReg is a physical register we apply the sub register to obtain the
388/// final/proper physical register.
390 assert(FromReg != ToReg && "Cannot replace a reg with itself");
391
393
394 // TODO: This could be more efficient by bulk changing the operands.
396 if (ToReg.isPhysical()) {
397 O.substPhysReg(ToReg, *TRI);
398 } else {
399 O.setReg(ToReg);
400 }
401 }
402}
403
404/// getVRegDef - Return the machine instr that defines the specified virtual
405/// register or null if none is found. This assumes that the code is in SSA
406/// form, so there should only be one definition.
408 // Since we are in SSA form, we can use the first definition.
410 assert((I.atEnd() || std::next(I) == def_instr_end()) &&
411 "getVRegDef assumes a single definition or no definition");
412 return !I.atEnd() ? &*I : nullptr;
413}
414
415/// getUniqueVRegDef - Return the unique machine instr that defines the
416/// specified virtual register or null if none is found. If there are
417/// multiple definitions or no definition, return null.
419 if (def_empty(Reg)) return nullptr;
421 if (std::next(I) != def_instr_end())
422 return nullptr;
423 return &*I;
424}
425
428}
429
432}
433
435 unsigned MaxUsers) const {
437 MaxUsers);
438}
439
440/// clearKillFlags - Iterate over all the uses of the given register and
441/// clear the kill flag from the MachineOperand. This function is used by
442/// optimization passes which extend register lifetimes and need only
443/// preserve conservative kill flag information.
445 for (MachineOperand &MO : use_operands(Reg))
446 MO.setIsKill(false);
447}
448
450 for (const std::pair<MCRegister, Register> &LI : liveins())
451 if ((Register)LI.first == Reg || LI.second == Reg)
452 return true;
453 return false;
454}
455
456/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
457/// corresponding live-in physical register.
459 for (const std::pair<MCRegister, Register> &LI : liveins())
460 if (LI.second == VReg)
461 return LI.first;
462 return MCRegister();
463}
464
465/// getLiveInVirtReg - If PReg is a live-in physical register, return the
466/// corresponding live-in physical register.
468 for (const std::pair<MCRegister, Register> &LI : liveins())
469 if (LI.first == PReg)
470 return LI.second;
471 return Register();
472}
473
474/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
475/// into the given entry block.
476void
478 const TargetRegisterInfo &TRI,
479 const TargetInstrInfo &TII) {
480 // Emit the copies into the top of the block.
481 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
482 if (LiveIns[i].second) {
483 if (use_nodbg_empty(LiveIns[i].second)) {
484 // The livein has no non-dbg uses. Drop it.
485 //
486 // It would be preferable to have isel avoid creating live-in
487 // records for unused arguments in the first place, but it's
488 // complicated by the debug info code for arguments.
489 LiveIns.erase(LiveIns.begin() + i);
490 --i; --e;
491 } else {
492 // Emit a copy.
493 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
494 TII.get(TargetOpcode::COPY), LiveIns[i].second)
495 .addReg(LiveIns[i].first);
496
497 // Add the register to the entry block live-in set.
498 EntryMBB->addLiveIn(LiveIns[i].first);
499 }
500 } else {
501 // Add the register to the entry block live-in set.
502 EntryMBB->addLiveIn(LiveIns[i].first);
503 }
504}
505
507 // Lane masks are only defined for vregs.
508 assert(Reg.isVirtual());
509 const TargetRegisterClass &TRC = *getRegClass(Reg);
510 return TRC.getLaneMask();
511}
512
513#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
515 for (MachineInstr &I : use_instructions(Reg))
516 I.dump();
517}
518#endif
519
521 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(*MF);
522 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
523 "Invalid ReservedRegs vector from target");
524}
525
528
530 if (TRI->isConstantPhysReg(PhysReg))
531 return true;
532
533 // Check if any overlapping register is modified, or allocatable so it may be
534 // used later.
535 for (MCRegAliasIterator AI(PhysReg, TRI, true);
536 AI.isValid(); ++AI)
537 if (!def_empty(*AI) || isAllocatable(*AI))
538 return false;
539 return true;
540}
541
542/// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
543/// specified register as undefined which causes the DBG_VALUE to be
544/// deleted during LiveDebugVariables analysis.
546 // Mark any DBG_VALUE* that uses Reg as undef (but don't delete it.)
547 // We use make_early_inc_range because setReg invalidates the iterator.
549 if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg))
550 UseMI.setDebugValueUndef();
551 }
552}
553
555 for (const MachineOperand &MO : MI.operands()) {
556 if (!MO.isGlobal())
557 continue;
558 const Function *Func = dyn_cast<Function>(MO.getGlobal());
559 if (Func != nullptr)
560 return Func;
561 }
562 return nullptr;
563}
564
565static bool isNoReturnDef(const MachineOperand &MO) {
566 // Anything which is not a noreturn function is a real def.
567 const MachineInstr &MI = *MO.getParent();
568 if (!MI.isCall())
569 return false;
570 const MachineBasicBlock &MBB = *MI.getParent();
571 if (!MBB.succ_empty())
572 return false;
573 const MachineFunction &MF = *MBB.getParent();
574 // We need to keep correct unwind information even if the function will
575 // not return, since the runtime may need it.
576 if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
577 return false;
578 const Function *Called = getCalledFunction(MI);
579 return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
580 !Called->hasFnAttribute(Attribute::NoUnwind));
581}
582
584 bool SkipNoReturnDef) const {
585 if (UsedPhysRegMask.test(PhysReg))
586 return true;
588 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
589 for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
590 if (!SkipNoReturnDef && isNoReturnDef(MO))
591 continue;
592 return true;
593 }
594 }
595 return false;
596}
597
599 bool SkipRegMaskTest) const {
600 if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg))
601 return true;
603 for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
604 ++AliasReg) {
605 if (!reg_nodbg_empty(*AliasReg))
606 return true;
607 }
608 return false;
609}
610
612
614 assert(Reg && (Reg < TRI->getNumRegs()) &&
615 "Trying to disable an invalid register");
616
617 if (!IsUpdatedCSRsInitialized) {
618 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
619 for (const MCPhysReg *I = CSR; *I; ++I)
620 UpdatedCSRs.push_back(*I);
621
622 // Zero value represents the end of the register list
623 // (no more registers should be pushed).
624 UpdatedCSRs.push_back(0);
625
626 IsUpdatedCSRsInitialized = true;
627 }
628
629 // Remove the register (and its aliases from the list).
630 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
631 llvm::erase(UpdatedCSRs, *AI);
632}
633
635 if (IsUpdatedCSRsInitialized)
636 return UpdatedCSRs.data();
637
639}
640
642 if (IsUpdatedCSRsInitialized)
643 UpdatedCSRs.clear();
644
645 append_range(UpdatedCSRs, CSRs);
646
647 // Zero value represents the end of the register list
648 // (no more registers should be pushed).
649 UpdatedCSRs.push_back(0);
650 IsUpdatedCSRsInitialized = true;
651}
652
653bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
655 for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
656 if (all_of(TRI->superregs_inclusive(*Root),
657 [&](MCPhysReg Super) { return isReserved(Super); }))
658 return true;
659 }
660 return false;
661}
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineBasicBlock & MBB
This file contains the simple types necessary to represent the attributes associated with functions a...
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:529
std::string Name
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))
static bool isNoReturnDef(const MachineOperand &MO)
static const TargetRegisterClass * constrainRegClass(MachineRegisterInfo &MRI, Register Reg, const TargetRegisterClass *OldRC, const TargetRegisterClass *RC, unsigned MinNumRegs)
unsigned const TargetRegisterInfo * TRI
static const Function * getCalledFunction(const Value *V, bool &IsNoBuiltin)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool test(unsigned Idx) const
Definition: BitVector.h:461
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:341
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:159
A debug info location.
Definition: DebugLoc.h:33
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:683
void grow(IndexT n)
Definition: IndexedMap.h:69
constexpr bool isValid() const
Definition: LowLevelType.h:145
MCRegAliasIterator enumerates all registers aliasing Reg.
MCRegUnitRootIterator enumerates the root registers of a register unit.
bool isValid() const
Check if the iterator is at the end of the list.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void verifyUseList(Register Reg) const
Verify the sanity of the use list for Reg.
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
void insertVRegByName(StringRef Name, Register Reg)
void verifyUseLists() const
Verify the use list of all registers.
void markUsesInDebugValueAsUndef(Register Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
iterator_range< reg_iterator > reg_operands(Register Reg) const
bool recomputeRegClass(Register Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
void freezeReservedRegs()
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
MachineRegisterInfo(MachineFunction *MF)
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
static def_instr_iterator def_instr_end()
void dumpUses(Register RegNo) const
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
def_iterator def_begin(Register RegNo) const
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
def_instr_iterator def_instr_begin(Register RegNo) const
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
bool isLiveIn(Register Reg) const
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
ArrayRef< std::pair< MCRegister, Register > > liveins() const
bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const
hasAtMostUses - Return true if the given register has at most MaxUsers non-debug user instructions.
bool hasOneNonDBGUser(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
void setRegBank(Register Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
MCRegister getLiveInPhysReg(Register VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
static def_iterator def_end()
void disableCalleeSavedRegister(MCRegister Reg)
Disables the register from the list of CSRs.
iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const
void noteNewVirtualRegister(Register Reg)
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
const TargetRegisterInfo * getTargetRegisterInfo() const
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
bool constrainRegAttrs(Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
void noteCloneVirtualRegister(Register NewReg, Register SrcReg)
iterator_range< use_iterator > use_operands(Register Reg) const
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
static use_instr_nodbg_iterator use_instr_nodbg_end()
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getNumRegs() const
Return the number of registers in this class.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
virtual const TargetInstrInfo * getInstrInfo() const
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1722
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
Definition: STLExtras.h:2073
bool hasNItemsOrLess(IterTy &&Begin, IterTy &&End, unsigned N, Pred &&ShouldBeCounted=[](const decltype(*std::declval< IterTy >()) &) { return true;})
Returns true if the sequence [Begin, End) has N or less items.
Definition: STLExtras.h:2511
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:656
void erase(Container &C, ValueType V)
Wrapper function to remove a value from a container:
Definition: STLExtras.h:2059
bool hasSingleElement(ContainerTy &&C)
Returns true if the given container only contains a single element.
Definition: STLExtras.h:322
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
All attributes(register class or bank and low-level type) a virtual register can have.