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24 #include "llvm/Config/llvm-config.h"
42 void MachineRegisterInfo::Delegate::anchor() {}
45 : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
47 IsUpdatedCSRsInitialized(
false) {
50 RegAllocHints.reserve(256);
51 UsedPhysRegMask.
resize(NumRegs);
76 if (!NewRC || NewRC == OldRC)
87 unsigned MinNumRegs) {
94 unsigned MinNumRegs) {
96 const LLT ConstrainingRegTy =
getType(ConstrainingReg);
98 RegTy != ConstrainingRegTy)
101 if (!ConstrainingRegCB.isNull()) {
113 }
else if (RegCB != ConstrainingRegCB)
116 if (ConstrainingRegTy.
isValid())
136 unsigned OpNo = &MO - &
MI->getOperand(0);
137 NewRC =
MI->getRegClassConstraintEffect(OpNo, NewRC,
TII,
139 if (!NewRC || NewRC == OldRC)
149 RegAllocHints.grow(
Reg);
160 assert(RegClass &&
"Cannot create register without RegClass!");
162 "Virtual register RegClass must be allocatable.");
183 VRegToType.
grow(VReg);
184 VRegToType[VReg] = Ty;
213 for (
auto &
I : LiveIns)
225 <<
" use list MachineOperand " << MO
226 <<
" has no parent instruction.\n";
231 unsigned NumOps =
MI->getNumOperands();
232 if (!(MO >= MO0 && MO < MO0+NumOps)) {
234 <<
" use list MachineOperand " << MO
235 <<
" doesn't belong to parent MI: " << *
MI;
240 <<
" MachineOperand " << MO <<
": " << *MO
241 <<
" is not a register\n";
246 <<
" use-list MachineOperand " << MO <<
": "
247 << *MO <<
" is the wrong register\n";
251 assert(Valid &&
"Invalid use list");
266 assert(!MO->isOnRegUseList() &&
"Already on list");
276 MO->Contents.Reg.Prev = MO;
277 MO->Contents.Reg.Next =
nullptr;
285 assert(Last &&
"Inconsistent use list");
286 assert(MO->
getReg() == Last->getReg() &&
"Different regs on the same list!");
287 Head->Contents.Reg.Prev = MO;
288 MO->Contents.Reg.Prev = Last;
294 MO->Contents.Reg.Next = Head;
298 MO->Contents.Reg.Next =
nullptr;
299 Last->Contents.Reg.Next = MO;
305 assert(MO->isOnRegUseList() &&
"Operand not on use list");
308 assert(Head &&
"List already empty");
318 Prev->Contents.Reg.Next = Next;
320 (Next ? Next : Head)->Contents.Reg.Prev = Prev;
322 MO->Contents.Reg.Prev =
nullptr;
323 MO->Contents.Reg.Next =
nullptr;
336 assert(Src != Dst && NumOps &&
"Noop moveOperands");
340 if (Dst >= Src && Dst < Src + NumOps) {
355 assert(Head &&
"List empty, but operand is chained");
356 assert(Prev &&
"Operand was not on use-def list");
363 Prev->Contents.Reg.Next = Dst;
367 (Next ? Next : Head)->Contents.Reg.Prev = Dst;
381 assert(FromReg != ToReg &&
"Cannot replace a reg with itself");
390 O.substPhysReg(ToReg, *
TRI);
404 "getVRegDef assumes a single definition or no definition");
405 return !
I.atEnd() ? &*
I :
nullptr;
437 for (
const std::pair<MCRegister, Register> &LI :
liveins())
446 for (
const std::pair<MCRegister, Register> &LI :
liveins())
447 if (LI.second == VReg)
455 for (
const std::pair<MCRegister, Register> &LI :
liveins())
456 if (LI.first == PReg)
468 for (
unsigned i = 0,
e = LiveIns.size();
i !=
e; ++
i)
469 if (LiveIns[
i].second) {
476 LiveIns.erase(LiveIns.begin() +
i);
481 TII.get(TargetOpcode::COPY), LiveIns[
i].second)
500 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
510 "Invalid ReservedRegs vector from target");
536 if (
UseMI.isDebugValue() &&
UseMI.hasDebugOperandForReg(
Reg))
537 UseMI.setDebugValueUndef();
545 const Function *Func = dyn_cast<Function>(MO.getGlobal());
566 return !(Called ==
nullptr || !Called->
hasFnAttribute(Attribute::NoReturn) ||
571 bool SkipNoReturnDef)
const {
572 if (UsedPhysRegMask.
test(PhysReg))
586 if (UsedPhysRegMask.
test(PhysReg))
600 assert(
Reg && (Reg < TRI->getNumRegs()) &&
601 "Trying to disable an invalid register");
603 if (!IsUpdatedCSRsInitialized) {
606 UpdatedCSRs.push_back(*
I);
610 UpdatedCSRs.push_back(0);
612 IsUpdatedCSRsInitialized =
true;
621 if (IsUpdatedCSRsInitialized)
622 return UpdatedCSRs.data();
628 if (IsUpdatedCSRsInitialized)
635 UpdatedCSRs.push_back(0);
636 IsUpdatedCSRsInitialized =
true;
642 bool IsRootReserved =
true;
647 IsRootReserved =
false;
static def_instr_iterator def_instr_end()
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
void markUsesInDebugValueAsUndef(Register Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
def_iterator def_begin(Register RegNo) const
bool constrainRegAttrs(Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
MachineInstrBuilder & UseMI
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool recomputeRegClass(Register Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
virtual const TargetInstrInfo * getInstrInfo() const
void disableCalleeSavedRegister(MCRegister Reg)
Disables the register from the list of CSRs.
def_instr_iterator def_instr_begin(Register RegNo) const
virtual bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
const TargetRegisterInfo * getTargetRegisterInfo() const
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
defusechain_iterator - This class provides iterator support for machine operands in the function that...
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
iterator_range< use_iterator > use_operands(Register Reg) const
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
static reg_iterator reg_end()
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
static bool isNoReturnDef(const MachineOperand &MO)
unsigned const TargetRegisterInfo * TRI
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
TargetInstrInfo - Interface to description of machine instruction set.
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
This class implements the register bank concept.
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
virtual void MRI_NoteNewVirtualRegister(Register Reg)=0
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
size_type size() const
size - Returns the number of bits in this bitvector.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
void insertVRegByName(StringRef Name, Register Reg)
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void erase_value(Container &C, ValueType V)
Wrapper function to remove a value from a container:
bool isValid() const
Check if the iterator is at the end of the list.
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void verifyUseList(Register Reg) const
Verify the sanity of the use list for Reg.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
void setRegBank(Register Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
MCRegister getLiveInPhysReg(Register VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
initializer< Ty > init(const Ty &Val)
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
ArrayRef< std::pair< MCRegister, Register > > liveins() const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator_range< reg_iterator > reg_operands(Register Reg) const
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
MCSuperRegIterator enumerates all super-registers of Reg.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
static def_iterator def_end()
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
bool hasSingleElement(ContainerTy &&C)
Returns true if the given container only contains a single element.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
StringRef - Represent a constant reference to a string, i.e.
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))
reg_iterator reg_begin(Register RegNo) const
bool test(unsigned Idx) const
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
bool isLiveIn(Register Reg) const
unsigned getNumRegs() const
Return the number of registers in this class.
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Function & getFunction()
Return the LLVM function that this machine code represents.
static const Function * getCalledFunction(const MachineInstr &MI)
bool isPhysRegUsed(MCRegister PhysReg) const
Return true if the specified register is modified or read in this function.
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
static const TargetRegisterClass * constrainRegClass(MachineRegisterInfo &MRI, Register Reg, const TargetRegisterClass *OldRC, const TargetRegisterClass *RC, unsigned MinNumRegs)
bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
bool hasOneNonDBGUser(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
MCRegUnitRootIterator enumerates the root registers of a register unit.
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
MachineRegisterInfo(MachineFunction *MF)
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
void dumpUses(Register RegNo) const
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
MCRegAliasIterator enumerates all registers aliasing Reg.
void verifyUseLists() const
Verify the use list of all registers.
Wrapper class representing physical registers. Should be passed by value.