LLVM  14.0.0git
MachineRegisterInfo.cpp
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1 //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implementation of the MachineRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
24 #include "llvm/Config/llvm-config.h"
25 #include "llvm/IR/Attributes.h"
26 #include "llvm/IR/DebugLoc.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/Support/Casting.h"
31 #include "llvm/Support/Compiler.h"
34 #include <cassert>
35 
36 using namespace llvm;
37 
38 static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
39  cl::init(true), cl::desc("Enable subregister liveness tracking."));
40 
41 // Pin the vtable to this file.
42 void MachineRegisterInfo::Delegate::anchor() {}
43 
45  : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
47  IsUpdatedCSRsInitialized(false) {
48  unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
49  VRegInfo.reserve(256);
50  RegAllocHints.reserve(256);
51  UsedPhysRegMask.resize(NumRegs);
52  PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
53 }
54 
55 /// setRegClass - Set the register class of the specified virtual register.
56 ///
57 void
59  assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
60  VRegInfo[Reg].first = RC;
61 }
62 
64  const RegisterBank &RegBank) {
65  VRegInfo[Reg].first = &RegBank;
66 }
67 
68 static const TargetRegisterClass *
70  const TargetRegisterClass *OldRC,
71  const TargetRegisterClass *RC, unsigned MinNumRegs) {
72  if (OldRC == RC)
73  return RC;
74  const TargetRegisterClass *NewRC =
76  if (!NewRC || NewRC == OldRC)
77  return NewRC;
78  if (NewRC->getNumRegs() < MinNumRegs)
79  return nullptr;
80  MRI.setRegClass(Reg, NewRC);
81  return NewRC;
82 }
83 
84 const TargetRegisterClass *
86  const TargetRegisterClass *RC,
87  unsigned MinNumRegs) {
88  return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
89 }
90 
91 bool
93  Register ConstrainingReg,
94  unsigned MinNumRegs) {
95  const LLT RegTy = getType(Reg);
96  const LLT ConstrainingRegTy = getType(ConstrainingReg);
97  if (RegTy.isValid() && ConstrainingRegTy.isValid() &&
98  RegTy != ConstrainingRegTy)
99  return false;
100  const auto ConstrainingRegCB = getRegClassOrRegBank(ConstrainingReg);
101  if (!ConstrainingRegCB.isNull()) {
102  const auto RegCB = getRegClassOrRegBank(Reg);
103  if (RegCB.isNull())
104  setRegClassOrRegBank(Reg, ConstrainingRegCB);
105  else if (RegCB.is<const TargetRegisterClass *>() !=
106  ConstrainingRegCB.is<const TargetRegisterClass *>())
107  return false;
108  else if (RegCB.is<const TargetRegisterClass *>()) {
109  if (!::constrainRegClass(
110  *this, Reg, RegCB.get<const TargetRegisterClass *>(),
111  ConstrainingRegCB.get<const TargetRegisterClass *>(), MinNumRegs))
112  return false;
113  } else if (RegCB != ConstrainingRegCB)
114  return false;
115  }
116  if (ConstrainingRegTy.isValid())
117  setType(Reg, ConstrainingRegTy);
118  return true;
119 }
120 
121 bool
123  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
124  const TargetRegisterClass *OldRC = getRegClass(Reg);
125  const TargetRegisterClass *NewRC =
127 
128  // Stop early if there is no room to grow.
129  if (NewRC == OldRC)
130  return false;
131 
132  // Accumulate constraints from all uses.
133  for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
134  // Apply the effect of the given operand to NewRC.
135  MachineInstr *MI = MO.getParent();
136  unsigned OpNo = &MO - &MI->getOperand(0);
137  NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
139  if (!NewRC || NewRC == OldRC)
140  return false;
141  }
142  setRegClass(Reg, NewRC);
143  return true;
144 }
145 
148  VRegInfo.grow(Reg);
149  RegAllocHints.grow(Reg);
151  return Reg;
152 }
153 
154 /// createVirtualRegister - Create and return a new virtual register in the
155 /// function with the specified register class.
156 ///
157 Register
159  StringRef Name) {
160  assert(RegClass && "Cannot create register without RegClass!");
161  assert(RegClass->isAllocatable() &&
162  "Virtual register RegClass must be allocatable.");
163 
164  // New virtual register number.
166  VRegInfo[Reg].first = RegClass;
167  if (TheDelegate)
168  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
169  return Reg;
170 }
171 
173  StringRef Name) {
175  VRegInfo[Reg].first = VRegInfo[VReg].first;
176  setType(Reg, getType(VReg));
177  if (TheDelegate)
178  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
179  return Reg;
180 }
181 
183  VRegToType.grow(VReg);
184  VRegToType[VReg] = Ty;
185 }
186 
187 Register
189  // New virtual register number.
191  // FIXME: Should we use a dummy register class?
192  VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
193  setType(Reg, Ty);
194  if (TheDelegate)
195  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
196  return Reg;
197 }
198 
200 
201 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
203 #ifndef NDEBUG
204  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
206  if (!VRegInfo[Reg].second)
207  continue;
209  llvm_unreachable("Remaining virtual register operands");
210  }
211 #endif
212  VRegInfo.clear();
213  for (auto &I : LiveIns)
214  I.second = 0;
215 }
216 
218 #ifndef NDEBUG
219  bool Valid = true;
220  for (MachineOperand &M : reg_operands(Reg)) {
221  MachineOperand *MO = &M;
222  MachineInstr *MI = MO->getParent();
223  if (!MI) {
225  << " use list MachineOperand " << MO
226  << " has no parent instruction.\n";
227  Valid = false;
228  continue;
229  }
230  MachineOperand *MO0 = &MI->getOperand(0);
231  unsigned NumOps = MI->getNumOperands();
232  if (!(MO >= MO0 && MO < MO0+NumOps)) {
234  << " use list MachineOperand " << MO
235  << " doesn't belong to parent MI: " << *MI;
236  Valid = false;
237  }
238  if (!MO->isReg()) {
240  << " MachineOperand " << MO << ": " << *MO
241  << " is not a register\n";
242  Valid = false;
243  }
244  if (MO->getReg() != Reg) {
246  << " use-list MachineOperand " << MO << ": "
247  << *MO << " is the wrong register\n";
248  Valid = false;
249  }
250  }
251  assert(Valid && "Invalid use list");
252 #endif
253 }
254 
256 #ifndef NDEBUG
257  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
259  for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
260  verifyUseList(i);
261 #endif
262 }
263 
264 /// Add MO to the linked list of operands for its register.
266  assert(!MO->isOnRegUseList() && "Already on list");
267  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
268  MachineOperand *const Head = HeadRef;
269 
270  // Head points to the first list element.
271  // Next is NULL on the last list element.
272  // Prev pointers are circular, so Head->Prev == Last.
273 
274  // Head is NULL for an empty list.
275  if (!Head) {
276  MO->Contents.Reg.Prev = MO;
277  MO->Contents.Reg.Next = nullptr;
278  HeadRef = MO;
279  return;
280  }
281  assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
282 
283  // Insert MO between Last and Head in the circular Prev chain.
284  MachineOperand *Last = Head->Contents.Reg.Prev;
285  assert(Last && "Inconsistent use list");
286  assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
287  Head->Contents.Reg.Prev = MO;
288  MO->Contents.Reg.Prev = Last;
289 
290  // Def operands always precede uses. This allows def_iterator to stop early.
291  // Insert def operands at the front, and use operands at the back.
292  if (MO->isDef()) {
293  // Insert def at the front.
294  MO->Contents.Reg.Next = Head;
295  HeadRef = MO;
296  } else {
297  // Insert use at the end.
298  MO->Contents.Reg.Next = nullptr;
299  Last->Contents.Reg.Next = MO;
300  }
301 }
302 
303 /// Remove MO from its use-def list.
305  assert(MO->isOnRegUseList() && "Operand not on use list");
306  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
307  MachineOperand *const Head = HeadRef;
308  assert(Head && "List already empty");
309 
310  // Unlink this from the doubly linked list of operands.
311  MachineOperand *Next = MO->Contents.Reg.Next;
312  MachineOperand *Prev = MO->Contents.Reg.Prev;
313 
314  // Prev links are circular, next link is NULL instead of looping back to Head.
315  if (MO == Head)
316  HeadRef = Next;
317  else
318  Prev->Contents.Reg.Next = Next;
319 
320  (Next ? Next : Head)->Contents.Reg.Prev = Prev;
321 
322  MO->Contents.Reg.Prev = nullptr;
323  MO->Contents.Reg.Next = nullptr;
324 }
325 
326 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
327 ///
328 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
329 /// operands that won't be destroyed, which is OK because the MO destructor is
330 /// trivial anyway).
331 ///
332 /// The Src and Dst ranges may overlap.
334  MachineOperand *Src,
335  unsigned NumOps) {
336  assert(Src != Dst && NumOps && "Noop moveOperands");
337 
338  // Copy backwards if Dst is within the Src range.
339  int Stride = 1;
340  if (Dst >= Src && Dst < Src + NumOps) {
341  Stride = -1;
342  Dst += NumOps - 1;
343  Src += NumOps - 1;
344  }
345 
346  // Copy one operand at a time.
347  do {
348  new (Dst) MachineOperand(*Src);
349 
350  // Dst takes Src's place in the use-def chain.
351  if (Src->isReg()) {
352  MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
353  MachineOperand *Prev = Src->Contents.Reg.Prev;
354  MachineOperand *Next = Src->Contents.Reg.Next;
355  assert(Head && "List empty, but operand is chained");
356  assert(Prev && "Operand was not on use-def list");
357 
358  // Prev links are circular, next link is NULL instead of looping back to
359  // Head.
360  if (Src == Head)
361  Head = Dst;
362  else
363  Prev->Contents.Reg.Next = Dst;
364 
365  // Update Prev pointer. This also works when Src was pointing to itself
366  // in a 1-element list. In that case Head == Dst.
367  (Next ? Next : Head)->Contents.Reg.Prev = Dst;
368  }
369 
370  Dst += Stride;
371  Src += Stride;
372  } while (--NumOps);
373 }
374 
375 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
376 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
377 /// except that it also changes any definitions of the register as well.
378 /// If ToReg is a physical register we apply the sub register to obtain the
379 /// final/proper physical register.
381  assert(FromReg != ToReg && "Cannot replace a reg with itself");
382 
384 
385  // TODO: This could be more efficient by bulk changing the operands.
387  if (Register::isPhysicalRegister(ToReg)) {
388  O.substPhysReg(ToReg, *TRI);
389  } else {
390  O.setReg(ToReg);
391  }
392  }
393 }
394 
395 /// getVRegDef - Return the machine instr that defines the specified virtual
396 /// register or null if none is found. This assumes that the code is in SSA
397 /// form, so there should only be one definition.
399  // Since we are in SSA form, we can use the first definition.
401  assert((I.atEnd() || std::next(I) == def_instr_end()) &&
402  "getVRegDef assumes a single definition or no definition");
403  return !I.atEnd() ? &*I : nullptr;
404 }
405 
406 /// getUniqueVRegDef - Return the unique machine instr that defines the
407 /// specified virtual register or null if none is found. If there are
408 /// multiple definitions or no definition, return null.
410  if (def_empty(Reg)) return nullptr;
412  if (std::next(I) != def_instr_end())
413  return nullptr;
414  return &*I;
415 }
416 
418  return hasSingleElement(use_nodbg_operands(RegNo));
419 }
420 
423 }
424 
425 /// clearKillFlags - Iterate over all the uses of the given register and
426 /// clear the kill flag from the MachineOperand. This function is used by
427 /// optimization passes which extend register lifetimes and need only
428 /// preserve conservative kill flag information.
430  for (MachineOperand &MO : use_operands(Reg))
431  MO.setIsKill(false);
432 }
433 
435  for (const std::pair<MCRegister, Register> &LI : liveins())
436  if ((Register)LI.first == Reg || LI.second == Reg)
437  return true;
438  return false;
439 }
440 
441 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
442 /// corresponding live-in physical register.
444  for (const std::pair<MCRegister, Register> &LI : liveins())
445  if (LI.second == VReg)
446  return LI.first;
447  return MCRegister();
448 }
449 
450 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
451 /// corresponding live-in physical register.
453  for (const std::pair<MCRegister, Register> &LI : liveins())
454  if (LI.first == PReg)
455  return LI.second;
456  return Register();
457 }
458 
459 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
460 /// into the given entry block.
461 void
463  const TargetRegisterInfo &TRI,
464  const TargetInstrInfo &TII) {
465  // Emit the copies into the top of the block.
466  for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
467  if (LiveIns[i].second) {
468  if (use_nodbg_empty(LiveIns[i].second)) {
469  // The livein has no non-dbg uses. Drop it.
470  //
471  // It would be preferable to have isel avoid creating live-in
472  // records for unused arguments in the first place, but it's
473  // complicated by the debug info code for arguments.
474  LiveIns.erase(LiveIns.begin() + i);
475  --i; --e;
476  } else {
477  // Emit a copy.
478  BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
479  TII.get(TargetOpcode::COPY), LiveIns[i].second)
480  .addReg(LiveIns[i].first);
481 
482  // Add the register to the entry block live-in set.
483  EntryMBB->addLiveIn(LiveIns[i].first);
484  }
485  } else {
486  // Add the register to the entry block live-in set.
487  EntryMBB->addLiveIn(LiveIns[i].first);
488  }
489 }
490 
492  // Lane masks are only defined for vregs.
494  const TargetRegisterClass &TRC = *getRegClass(Reg);
495  return TRC.getLaneMask();
496 }
497 
498 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
501  I.dump();
502 }
503 #endif
504 
506  ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
507  assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
508  "Invalid ReservedRegs vector from target");
509 }
510 
513 
515  if (TRI->isConstantPhysReg(PhysReg))
516  return true;
517 
518  // Check if any overlapping register is modified, or allocatable so it may be
519  // used later.
520  for (MCRegAliasIterator AI(PhysReg, TRI, true);
521  AI.isValid(); ++AI)
522  if (!def_empty(*AI) || isAllocatable(*AI))
523  return false;
524  return true;
525 }
526 
527 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
528 /// specified register as undefined which causes the DBG_VALUE to be
529 /// deleted during LiveDebugVariables analysis.
531  // Mark any DBG_VALUE* that uses Reg as undef (but don't delete it.)
532  // We use make_early_inc_range because setReg invalidates the iterator.
534  if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg))
535  UseMI.setDebugValueUndef();
536  }
537 }
538 
539 static const Function *getCalledFunction(const MachineInstr &MI) {
540  for (const MachineOperand &MO : MI.operands()) {
541  if (!MO.isGlobal())
542  continue;
543  const Function *Func = dyn_cast<Function>(MO.getGlobal());
544  if (Func != nullptr)
545  return Func;
546  }
547  return nullptr;
548 }
549 
550 static bool isNoReturnDef(const MachineOperand &MO) {
551  // Anything which is not a noreturn function is a real def.
552  const MachineInstr &MI = *MO.getParent();
553  if (!MI.isCall())
554  return false;
555  const MachineBasicBlock &MBB = *MI.getParent();
556  if (!MBB.succ_empty())
557  return false;
558  const MachineFunction &MF = *MBB.getParent();
559  // We need to keep correct unwind information even if the function will
560  // not return, since the runtime may need it.
561  if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
562  return false;
563  const Function *Called = getCalledFunction(MI);
564  return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
565  !Called->hasFnAttribute(Attribute::NoUnwind));
566 }
567 
569  bool SkipNoReturnDef) const {
570  if (UsedPhysRegMask.test(PhysReg))
571  return true;
573  for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
574  for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
575  if (!SkipNoReturnDef && isNoReturnDef(MO))
576  continue;
577  return true;
578  }
579  }
580  return false;
581 }
582 
584  bool SkipRegMaskTest) const {
585  if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg))
586  return true;
588  for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
589  ++AliasReg) {
590  if (!reg_nodbg_empty(*AliasReg))
591  return true;
592  }
593  return false;
594 }
595 
597 
599  assert(Reg && (Reg < TRI->getNumRegs()) &&
600  "Trying to disable an invalid register");
601 
602  if (!IsUpdatedCSRsInitialized) {
603  const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
604  for (const MCPhysReg *I = CSR; *I; ++I)
605  UpdatedCSRs.push_back(*I);
606 
607  // Zero value represents the end of the register list
608  // (no more registers should be pushed).
609  UpdatedCSRs.push_back(0);
610 
611  IsUpdatedCSRsInitialized = true;
612  }
613 
614  // Remove the register (and its aliases from the list).
615  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
616  llvm::erase_value(UpdatedCSRs, *AI);
617 }
618 
620  if (IsUpdatedCSRsInitialized)
621  return UpdatedCSRs.data();
622 
624 }
625 
627  if (IsUpdatedCSRsInitialized)
628  UpdatedCSRs.clear();
629 
630  append_range(UpdatedCSRs, CSRs);
631 
632  // Zero value represents the end of the register list
633  // (no more registers should be pushed).
634  UpdatedCSRs.push_back(0);
635  IsUpdatedCSRsInitialized = true;
636 }
637 
638 bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
640  for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
641  bool IsRootReserved = true;
642  for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
643  Super.isValid(); ++Super) {
644  MCRegister Reg = *Super;
645  if (!isReserved(Reg)) {
646  IsRootReserved = false;
647  break;
648  }
649  }
650  if (IsRootReserved)
651  return true;
652  }
653  return false;
654 }
llvm::MachineRegisterInfo::def_instr_end
static def_instr_iterator def_instr_end()
Definition: MachineRegisterInfo.h:400
llvm::LaneBitmask
Definition: LaneBitmask.h:40
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getLargestLegalSuperClass
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Definition: TargetRegisterInfo.h:777
llvm::MachineRegisterInfo::markUsesInDebugValueAsUndef
void markUsesInDebugValueAsUndef(Register Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
Definition: MachineRegisterInfo.cpp:530
LowLevelType.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:510
llvm::MachineRegisterInfo::def_begin
def_iterator def_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:384
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1563
llvm::MachineRegisterInfo::isPhysRegUsed
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
Definition: MachineRegisterInfo.cpp:583
llvm::MachineRegisterInfo::constrainRegAttrs
bool constrainRegAttrs(Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...
Definition: MachineRegisterInfo.cpp:92
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
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Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::MachineRegisterInfo::createIncompleteVirtualRegister
Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
Definition: MachineRegisterInfo.cpp:146
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::TargetRegisterClass::getLaneMask
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
Definition: TargetRegisterInfo.h:206
llvm::TargetRegisterClass::isAllocatable
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
Definition: TargetRegisterInfo.h:117
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
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Definition: Function.h:62
llvm::MachineRegisterInfo::recomputeRegClass
bool recomputeRegClass(Register Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
Definition: MachineRegisterInfo.cpp:122
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::MachineRegisterInfo::disableCalleeSavedRegister
void disableCalleeSavedRegister(MCRegister Reg)
Disables the register from the list of CSRs.
Definition: MachineRegisterInfo.cpp:596
llvm::MachineRegisterInfo::def_instr_begin
def_instr_iterator def_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:397
llvm::TargetRegisterInfo::isConstantPhysReg
virtual bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: TargetRegisterInfo.h:548
ErrorHandling.h
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::TargetRegisterInfo::getReservedRegs
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:153
llvm::MachineRegisterInfo::getUniqueVRegDef
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:409
llvm::MachineRegisterInfo::defusechain_instr_iterator
defusechain_iterator - This class provides iterator support for machine operands in the function that...
Definition: MachineRegisterInfo.h:269
MachineBasicBlock.h
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MachineRegisterInfo::use_nodbg_instructions
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:543
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::IndexedMap::clear
void clear()
Definition: IndexedMap.h:63
llvm::MachineRegisterInfo::use_instructions
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:485
llvm::BitVector::resize
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:333
TargetInstrInfo.h
llvm::MachineRegisterInfo::getLiveInVirtReg
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
Definition: MachineRegisterInfo.cpp:452
llvm::MachineRegisterInfo::use_operands
iterator_range< use_iterator > use_operands(Register Reg) const
Definition: MachineRegisterInfo.h:469
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:757
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:894
isNoReturnDef
static bool isNoReturnDef(const MachineOperand &MO)
Definition: MachineRegisterInfo.cpp:550
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1564
MachineRegisterInfo.h
llvm::TargetRegisterInfo::getCalleeSavedRegs
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
CommandLine.h
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineRegisterInfo::use_nodbg_operands
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:526
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::MachineRegisterInfo::setRegClassOrRegBank
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
Definition: MachineRegisterInfo.h:678
llvm::MachineRegisterInfo::setType
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
Definition: MachineRegisterInfo.cpp:182
llvm::MachineRegisterInfo::Delegate::MRI_NoteNewVirtualRegister
virtual void MRI_NoteNewVirtualRegister(Register Reg)=0
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:928
llvm::BitVector::size
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:151
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MachineRegisterInfo::reg_nodbg_operands
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:337
false
Definition: StackSlotColoring.cpp:142
llvm::MachineRegisterInfo::insertVRegByName
void insertVRegByName(StringRef Name, Register Reg)
Definition: MachineRegisterInfo.h:432
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineRegisterInfo::setCalleeSavedRegs
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
Definition: MachineRegisterInfo.cpp:626
llvm::MachineRegisterInfo::freezeReservedRegs
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Definition: MachineRegisterInfo.cpp:505
DebugLoc.h
llvm::MachineRegisterInfo::clearVirtRegTypes
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
Definition: MachineRegisterInfo.cpp:199
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:398
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::erase_value
void erase_value(Container &C, ValueType V)
Wrapper function to remove a value from a container:
Definition: STLExtras.h:1838
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MCRegUnitRootIterator::isValid
bool isValid() const
Check if the iterator is at the end of the list.
Definition: MCRegisterInfo.h:765
llvm::MachineRegisterInfo::def_empty
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:426
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::MachineRegisterInfo::clearKillFlags
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Definition: MachineRegisterInfo.cpp:429
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:626
llvm::cl::opt< bool >
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:206
llvm::MachineRegisterInfo::verifyUseList
void verifyUseList(Register Reg) const
Verify the sanity of the use list for Reg.
Definition: MachineRegisterInfo.cpp:217
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineRegisterInfo::setRegBank
void setRegBank(Register Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
Definition: MachineRegisterInfo.cpp:63
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::MachineRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
Definition: MachineRegisterInfo.cpp:619
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineRegisterInfo::getLiveInPhysReg
MCRegister getLiveInPhysReg(Register VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
Definition: MachineRegisterInfo.cpp:443
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::make_early_inc_range
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:642
MCRegisterInfo.h
llvm::MachineRegisterInfo::liveins
ArrayRef< std::pair< MCRegister, Register > > liveins() const
Definition: MachineRegisterInfo.h:969
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineRegisterInfo::reg_operands
iterator_range< reg_iterator > reg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:286
llvm::MachineRegisterInfo::isAllocatable
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
Definition: MachineRegisterInfo.h:946
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:229
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:288
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:641
iterator_range.h
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:188
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineRegisterInfo::def_end
static def_iterator def_end()
Definition: MachineRegisterInfo.h:387
llvm::MachineRegisterInfo::getRegClassOrRegBank
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
Definition: MachineRegisterInfo.h:668
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MachineRegisterInfo::use_nodbg_empty
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Definition: MachineRegisterInfo.h:566
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:351
llvm::hasSingleElement
bool hasSingleElement(ContainerTy &&C)
Returns true if the given container only contains a single element.
Definition: STLExtras.h:314
llvm::IndexedMap::grow
void grow(IndexT n)
Definition: IndexedMap.h:67
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:417
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
Compiler.h
llvm::append_range
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
Definition: STLExtras.h:1846
TargetSubtargetInfo.h
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
llvm::MachineRegisterInfo::removeRegOperandFromUseList
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Definition: MachineRegisterInfo.cpp:304
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:371
llvm::MachineRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: MachineRegisterInfo.cpp:511
llvm::MachineRegisterInfo::replaceRegWith
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
Definition: MachineRegisterInfo.cpp:380
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
EnableSubRegLiveness
static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))
Attributes.h
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:447
llvm::MachineRegisterInfo::addRegOperandToUseList
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Definition: MachineRegisterInfo.cpp:265
llvm::MachineRegisterInfo::isLiveIn
bool isLiveIn(Register Reg) const
Definition: MachineRegisterInfo.cpp:434
llvm::TargetRegisterClass::getNumRegs
unsigned getNumRegs() const
Return the number of registers in this class.
Definition: TargetRegisterInfo.h:79
llvm::MachineRegisterInfo::getMaxLaneMaskForVReg
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Definition: MachineRegisterInfo.cpp:491
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
uint16_t
Casting.h
Function.h
getCalledFunction
static const Function * getCalledFunction(const MachineInstr &MI)
Definition: MachineRegisterInfo.cpp:539
llvm::MachineRegisterInfo::clearVirtRegs
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
Definition: MachineRegisterInfo.cpp:202
constrainRegClass
static const TargetRegisterClass * constrainRegClass(MachineRegisterInfo &MRI, Register Reg, const TargetRegisterClass *OldRC, const TargetRegisterClass *RC, unsigned MinNumRegs)
Definition: MachineRegisterInfo.cpp:69
llvm::MachineRegisterInfo::isPhysRegModified
bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
Definition: MachineRegisterInfo.cpp:568
llvm::MachineRegisterInfo::hasOneNonDBGUser
bool hasOneNonDBGUser(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
Definition: MachineRegisterInfo.cpp:421
llvm::VRegInfo
Definition: MIParser.h:37
llvm::MCRegUnitRootIterator
MCRegUnitRootIterator enumerates the root registers of a register unit.
Definition: MCRegisterInfo.h:746
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:805
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:272
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
MachineInstrBuilder.h
llvm::MachineRegisterInfo::cloneVirtualRegister
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
Definition: MachineRegisterInfo.cpp:172
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:85
MachineOperand.h
llvm::MachineRegisterInfo::MachineRegisterInfo
MachineRegisterInfo(MachineFunction *MF)
Definition: MachineRegisterInfo.cpp:44
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineRegisterInfo::isReservedRegUnit
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
Definition: MachineRegisterInfo.cpp:638
llvm::cl::desc
Definition: CommandLine.h:412
llvm::MachineRegisterInfo::reg_nodbg_empty
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition: MachineRegisterInfo.h:377
raw_ostream.h
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachineRegisterInfo::dumpUses
void dumpUses(Register RegNo) const
Definition: MachineRegisterInfo.cpp:499
llvm::MachineRegisterInfo::moveOperands
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
Definition: MachineRegisterInfo.cpp:333
TargetRegisterInfo.h
llvm::MachineRegisterInfo::EmitLiveInCopies
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.
Definition: MachineRegisterInfo.cpp:462
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:58
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
llvm::MachineRegisterInfo::verifyUseLists
void verifyUseLists() const
Verify the use list of all registers.
Definition: MachineRegisterInfo.cpp:255
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::LLT
Definition: LowLevelTypeImpl.h:39