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15 #ifndef LLVM_CODEGEN_MACHINESSACONTEXT_H
16 #define LLVM_CODEGEN_MACHINESSACONTEXT_H
22 class MachineRegisterInfo;
24 class MachineFunction;
26 template <
typename _FunctionT>
class GenericSSAContext;
27 template <
typename,
bool>
class DominatorTreeBase;
31 return BB->predecessors();
34 return BB->succ_size();
37 return BB->pred_size();
75 #endif // LLVM_CODEGEN_MACHINESSACONTEXT_H
we get the following basic block
This is an optimization pass for GlobalISel generic memory operations.
unsigned succ_size(const MachineBasicBlock *BB)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
auto successors(const MachineBasicBlock *BB)
MachineFunction * getFunction() const
auto instrs(const MachineBasicBlock &BB)
Promote Memory to Register
auto predecessors(const MachineBasicBlock *BB)
Representation of each machine instruction.
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
Core dominator tree base class.
Wrapper class representing virtual and physical registers.
Simple wrapper around std::function<void(raw_ostream&)>.
static const Register ValueRefNull
unsigned pred_size(const MachineBasicBlock *BB)
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
LLVM Value Representation.