LLVM 17.0.0git
MachineSSAContext.h
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1//===- MachineSSAContext.h --------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This file declares a specialization of the GenericSSAContext<X>
11/// template class for Machine IR.
12///
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_MACHINESSACONTEXT_H
16#define LLVM_CODEGEN_MACHINESSACONTEXT_H
17
20
21namespace llvm {
22class MachineRegisterInfo;
23class MachineInstr;
24class MachineFunction;
25class Register;
26template <typename _FunctionT> class GenericSSAContext;
27template <typename, bool> class DominatorTreeBase;
28
29inline unsigned succ_size(const MachineBasicBlock *BB) {
30 return BB->succ_size();
31}
32inline unsigned pred_size(const MachineBasicBlock *BB) {
33 return BB->pred_size();
34}
35inline auto instrs(const MachineBasicBlock &BB) { return BB.instrs(); }
36
38 const MachineRegisterInfo *RegInfo = nullptr;
39 MachineFunction *MF = nullptr;
40
41public:
47 static const Register ValueRefNull;
50
51 void setFunction(MachineFunction &Fn);
52 MachineFunction *getFunction() const { return MF; }
53
54 static MachineBasicBlock *getEntryBlock(MachineFunction &F);
55 static void appendBlockDefs(SmallVectorImpl<Register> &defs,
59 static void appendBlockTerms(SmallVectorImpl<const MachineInstr *> &terms,
61 MachineBasicBlock *getDefBlock(Register) const;
62 static bool isConstantOrUndefValuePhi(const MachineInstr &Phi);
63
65 Printable print(const MachineInstr *Inst) const;
67};
68
70} // namespace llvm
71
72#endif // LLVM_CODEGEN_MACHINESSACONTEXT_H
#define F(x, y, z)
Definition: MD5.cpp:55
Promote Memory to Register
Definition: Mem2Reg.cpp:114
unify loop Fixup each natural loop to have a single exit block
Core dominator tree base class.
static void appendBlockTerms(SmallVectorImpl< MachineInstr * > &terms, MachineBasicBlock &block)
unsigned pred_size() const
unsigned succ_size() const
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
LLVM Value Representation.
Definition: Value.h:74
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
auto instrs(const MachineBasicBlock &BB)
unsigned succ_size(const MachineBasicBlock *BB)
unsigned pred_size(const MachineBasicBlock *BB)