LLVM  17.0.0git
MachineSSAContext.h
Go to the documentation of this file.
1 //===- MachineSSAContext.h --------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file declares a specialization of the GenericSSAContext<X>
11 /// template class for Machine IR.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_MACHINESSACONTEXT_H
16 #define LLVM_CODEGEN_MACHINESSACONTEXT_H
17 
19 #include "llvm/Support/Printable.h"
20 
21 namespace llvm {
22 class MachineRegisterInfo;
23 class MachineInstr;
24 class MachineFunction;
25 class Register;
26 template <typename _FunctionT> class GenericSSAContext;
27 template <typename, bool> class DominatorTreeBase;
28 
29 inline auto successors(const MachineBasicBlock *BB) { return BB->successors(); }
30 inline auto predecessors(const MachineBasicBlock *BB) {
31  return BB->predecessors();
32 }
33 inline unsigned succ_size(const MachineBasicBlock *BB) {
34  return BB->succ_size();
35 }
36 inline unsigned pred_size(const MachineBasicBlock *BB) {
37  return BB->pred_size();
38 }
39 inline auto instrs(const MachineBasicBlock &BB) { return BB.instrs(); }
40 
41 template <> class GenericSSAContext<MachineFunction> {
42  const MachineRegisterInfo *RegInfo = nullptr;
43  MachineFunction *MF;
44 
45 public:
51  static const Register ValueRefNull;
53 
54  void setFunction(MachineFunction &Fn);
55  MachineFunction *getFunction() const { return MF; }
56 
57  static MachineBasicBlock *getEntryBlock(MachineFunction &F);
58  static void appendBlockDefs(SmallVectorImpl<Register> &defs,
59  const MachineBasicBlock &block);
60  static void appendBlockTerms(SmallVectorImpl<MachineInstr *> &terms,
62  static void appendBlockTerms(SmallVectorImpl<const MachineInstr *> &terms,
63  const MachineBasicBlock &block);
64  MachineBasicBlock *getDefBlock(Register) const;
65  static bool isConstantValuePhi(const MachineInstr &Phi);
66 
67  Printable print(const MachineBasicBlock *Block) const;
68  Printable print(const MachineInstr *Inst) const;
70 };
71 
73 } // namespace llvm
74 
75 #endif // LLVM_CODEGEN_MACHINESSACONTEXT_H
block
we get the following basic block
Definition: README_ALTIVEC.txt:95
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::succ_size
unsigned succ_size(const MachineBasicBlock *BB)
Definition: MachineSSAContext.h:33
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:51
Printable.h
llvm::successors
auto successors(const MachineBasicBlock *BB)
Definition: MachineSSAContext.h:29
llvm::GenericSSAContext< MachineFunction >::getFunction
MachineFunction * getFunction() const
Definition: MachineSSAContext.h:55
MachineBasicBlock.h
llvm::instrs
auto instrs(const MachineBasicBlock &BB)
Definition: MachineSSAContext.h:39
F
#define F(x, y, z)
Definition: MD5.cpp:55
Register
Promote Memory to Register
Definition: Mem2Reg.cpp:110
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::GenericSSAContext
Definition: GenericSSAContext.h:24
llvm::predecessors
auto predecessors(const MachineBasicBlock *BB)
Definition: MachineSSAContext.h:30
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineFunction
Definition: MachineFunction.h:258
llvm::print
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
Definition: GCNRegPressure.cpp:138
RegInfo
Definition: AMDGPUAsmParser.cpp:2557
llvm::DominatorTreeBase
Core dominator tree base class.
Definition: LoopInfo.h:66
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::GenericSSAContext< MachineFunction >
Definition: MachineSSAContext.h:41
llvm::Printable
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
llvm::GenericSSAContext< MachineFunction >::ValueRefNull
static const Register ValueRefNull
Definition: MachineSSAContext.h:51
llvm::SmallVectorImpl< Register >
llvm::pred_size
unsigned pred_size(const MachineBasicBlock *BB)
Definition: MachineSSAContext.h:36
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::Value
LLVM Value Representation.
Definition: Value.h:74