LLVM  16.0.0git
MachineSSAContext.h
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1 //===- MachineSSAContext.h --------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file declares a specialization of the GenericSSAContext<X>
11 /// template class for Machine IR.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_MACHINESSACONTEXT_H
16 #define LLVM_CODEGEN_MACHINESSACONTEXT_H
17 
19 #include "llvm/Support/Printable.h"
20 
21 namespace llvm {
22 class MachineRegisterInfo;
23 class MachineInstr;
24 class MachineFunction;
25 class Register;
26 template <typename _FunctionT> class GenericSSAContext;
27 template <typename, bool> class DominatorTreeBase;
28 
29 inline auto successors(MachineBasicBlock *BB) { return BB->successors(); }
30 inline auto predecessors(MachineBasicBlock *BB) { return BB->predecessors(); }
31 inline unsigned succ_size(MachineBasicBlock *BB) { return BB->succ_size(); }
32 inline unsigned pred_size(MachineBasicBlock *BB) { return BB->pred_size(); }
33 
34 template <> class GenericSSAContext<MachineFunction> {
35  const MachineRegisterInfo *RegInfo = nullptr;
36  MachineFunction *MF;
37 
38 public:
44 
45  static MachineBasicBlock *getEntryBlock(MachineFunction &F);
46 
47  void setFunction(MachineFunction &Fn);
48  MachineFunction *getFunction() const { return MF; }
49 
50  Printable print(MachineBasicBlock *Block) const;
51  Printable print(MachineInstr *Inst) const;
53 };
54 
56 } // namespace llvm
57 
58 #endif // LLVM_CODEGEN_MACHINESSACONTEXT_H
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
print
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
Definition: ArchiveWriter.cpp:189
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
Printable.h
llvm::pred_size
unsigned pred_size(MachineBasicBlock *BB)
Definition: MachineSSAContext.h:32
llvm::GenericSSAContext< MachineFunction >::getFunction
MachineFunction * getFunction() const
Definition: MachineSSAContext.h:48
MachineBasicBlock.h
llvm::successors
auto successors(MachineBasicBlock *BB)
Definition: MachineSSAContext.h:29
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::succ_size
unsigned succ_size(MachineBasicBlock *BB)
Definition: MachineSSAContext.h:31
llvm::predecessors
auto predecessors(MachineBasicBlock *BB)
Definition: MachineSSAContext.h:30
Register
Promote Memory to Register
Definition: Mem2Reg.cpp:110
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::GenericSSAContext
Definition: GenericSSAContext.h:24
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineFunction
Definition: MachineFunction.h:257
RegInfo
Definition: AMDGPUAsmParser.cpp:2582
llvm::DominatorTreeBase
Core dominator tree base class.
Definition: LoopInfo.h:65
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::GenericSSAContext< MachineFunction >
Definition: MachineSSAContext.h:34
llvm::Printable
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::Value
LLVM Value Representation.
Definition: Value.h:74