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llvm::MachineRegisterInfo Class Reference

MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc. More...

#include "llvm/CodeGen/MachineRegisterInfo.h"

Classes

class  defusechain_instr_iterator
 defusechain_iterator - This class provides iterator support for machine operands in the function that use or define a specific register. More...
 
class  defusechain_iterator
 reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register within the MachineFunction that corresponds to this MachineRegisterInfo object. More...
 
class  Delegate
 

Public Types

using reg_iterator = defusechain_iterator< true, true, false, true, false, false >
 reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register. More...
 
using reg_instr_iterator = defusechain_instr_iterator< true, true, false, false, true, false >
 reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register, stepping by MachineInstr. More...
 
using reg_bundle_iterator = defusechain_instr_iterator< true, true, false, false, false, true >
 reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified register, stepping by bundle. More...
 
using reg_nodbg_iterator = defusechain_iterator< true, true, true, true, false, false >
 reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register, skipping those marked as Debug. More...
 
using reg_instr_nodbg_iterator = defusechain_instr_iterator< true, true, true, false, true, false >
 reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the specified register, stepping by MachineInstr, skipping those marked as Debug. More...
 
using reg_bundle_nodbg_iterator = defusechain_instr_iterator< true, true, true, false, false, true >
 reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the specified register, stepping by bundle, skipping those marked as Debug. More...
 
using def_iterator = defusechain_iterator< false, true, false, true, false, false >
 def_iterator/def_begin/def_end - Walk all defs of the specified register. More...
 
using def_instr_iterator = defusechain_instr_iterator< false, true, false, false, true, false >
 def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register, stepping by MachineInst. More...
 
using def_bundle_iterator = defusechain_instr_iterator< false, true, false, false, false, true >
 def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register, stepping by bundle. More...
 
using use_iterator = defusechain_iterator< true, false, false, true, false, false >
 use_iterator/use_begin/use_end - Walk all uses of the specified register. More...
 
using use_instr_iterator = defusechain_instr_iterator< true, false, false, false, true, false >
 use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register, stepping by MachineInstr. More...
 
using use_bundle_iterator = defusechain_instr_iterator< true, false, false, false, false, true >
 use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register, stepping by bundle. More...
 
using use_nodbg_iterator = defusechain_iterator< true, false, true, true, false, false >
 use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register, skipping those marked as Debug. More...
 
using use_instr_nodbg_iterator = defusechain_instr_iterator< true, false, true, false, true, false >
 use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified register, stepping by MachineInstr, skipping those marked as Debug. More...
 
using use_bundle_nodbg_iterator = defusechain_instr_iterator< true, false, true, false, false, true >
 use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specified register, stepping by bundle, skipping those marked as Debug. More...
 
using livein_iterator = std::vector< std::pair< MCRegister, Register > >::const_iterator
 

Public Member Functions

 MachineRegisterInfo (MachineFunction *MF)
 
 MachineRegisterInfo (const MachineRegisterInfo &)=delete
 
MachineRegisterInfooperator= (const MachineRegisterInfo &)=delete
 
const TargetRegisterInfogetTargetRegisterInfo () const
 
void resetDelegate (Delegate *delegate)
 
void setDelegate (Delegate *delegate)
 
bool isSSA () const
 
void leaveSSA ()
 
bool tracksLiveness () const
 tracksLiveness - Returns true when tracking register liveness accurately. More...
 
void invalidateLiveness ()
 invalidateLiveness - Indicates that register liveness is no longer being tracked accurately. More...
 
bool shouldTrackSubRegLiveness (const TargetRegisterClass &RC) const
 Returns true if liveness for register class RC should be tracked at the subregister level. More...
 
bool shouldTrackSubRegLiveness (Register VReg) const
 
bool subRegLivenessEnabled () const
 
bool isUpdatedCSRsInitialized () const
 Returns true if the updated CSR list was initialized and false otherwise. More...
 
void disableCalleeSavedRegister (MCRegister Reg)
 Disables the register from the list of CSRs. More...
 
const MCPhysReggetCalleeSavedRegs () const
 Returns list of callee saved registers. More...
 
void setCalleeSavedRegs (ArrayRef< MCPhysReg > CSRs)
 Sets the updated Callee Saved Registers list. More...
 
void addRegOperandToUseList (MachineOperand *MO)
 Add MO to the linked list of operands for its register. More...
 
void removeRegOperandFromUseList (MachineOperand *MO)
 Remove MO from its use-def list. More...
 
void moveOperands (MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
 Move NumOps operands from Src to Dst, updating use-def lists as needed. More...
 
void verifyUseList (Register Reg) const
 Verify the sanity of the use list for Reg. More...
 
void verifyUseLists () const
 Verify the use list of all registers. More...
 
reg_iterator reg_begin (Register RegNo) const
 
iterator_range< reg_iteratorreg_operands (Register Reg) const
 
reg_instr_iterator reg_instr_begin (Register RegNo) const
 
iterator_range< reg_instr_iteratorreg_instructions (Register Reg) const
 
reg_bundle_iterator reg_bundle_begin (Register RegNo) const
 
iterator_range< reg_bundle_iteratorreg_bundles (Register Reg) const
 
bool reg_empty (Register RegNo) const
 reg_empty - Return true if there are no instructions using or defining the specified register (it may be live-in). More...
 
reg_nodbg_iterator reg_nodbg_begin (Register RegNo) const
 
iterator_range< reg_nodbg_iteratorreg_nodbg_operands (Register Reg) const
 
reg_instr_nodbg_iterator reg_instr_nodbg_begin (Register RegNo) const
 
iterator_range< reg_instr_nodbg_iteratorreg_nodbg_instructions (Register Reg) const
 
reg_bundle_nodbg_iterator reg_bundle_nodbg_begin (Register RegNo) const
 
iterator_range< reg_bundle_nodbg_iteratorreg_nodbg_bundles (Register Reg) const
 
bool reg_nodbg_empty (Register RegNo) const
 reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions. More...
 
def_iterator def_begin (Register RegNo) const
 
iterator_range< def_iteratordef_operands (Register Reg) const
 
def_instr_iterator def_instr_begin (Register RegNo) const
 
iterator_range< def_instr_iteratordef_instructions (Register Reg) const
 
def_bundle_iterator def_bundle_begin (Register RegNo) const
 
iterator_range< def_bundle_iteratordef_bundles (Register Reg) const
 
bool def_empty (Register RegNo) const
 def_empty - Return true if there are no instructions defining the specified register (it may be live-in). More...
 
StringRef getVRegName (Register Reg) const
 
void insertVRegByName (StringRef Name, Register Reg)
 
bool hasOneDef (Register RegNo) const
 Return true if there is exactly one operand defining the specified register. More...
 
MachineOperandgetOneDef (Register Reg) const
 Returns the defining operand if there is exactly one operand defining the specified register, otherwise nullptr. More...
 
use_iterator use_begin (Register RegNo) const
 
iterator_range< use_iteratoruse_operands (Register Reg) const
 
use_instr_iterator use_instr_begin (Register RegNo) const
 
iterator_range< use_instr_iteratoruse_instructions (Register Reg) const
 
use_bundle_iterator use_bundle_begin (Register RegNo) const
 
iterator_range< use_bundle_iteratoruse_bundles (Register Reg) const
 
bool use_empty (Register RegNo) const
 use_empty - Return true if there are no instructions using the specified register. More...
 
bool hasOneUse (Register RegNo) const
 hasOneUse - Return true if there is exactly one instruction using the specified register. More...
 
use_nodbg_iterator use_nodbg_begin (Register RegNo) const
 
iterator_range< use_nodbg_iteratoruse_nodbg_operands (Register Reg) const
 
use_instr_nodbg_iterator use_instr_nodbg_begin (Register RegNo) const
 
iterator_range< use_instr_nodbg_iteratoruse_nodbg_instructions (Register Reg) const
 
use_bundle_nodbg_iterator use_bundle_nodbg_begin (Register RegNo) const
 
iterator_range< use_bundle_nodbg_iteratoruse_nodbg_bundles (Register Reg) const
 
bool use_nodbg_empty (Register RegNo) const
 use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register. More...
 
bool hasOneNonDBGUse (Register RegNo) const
 hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register. More...
 
bool hasOneNonDBGUser (Register RegNo) const
 hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified register. More...
 
void replaceRegWith (Register FromReg, Register ToReg)
 replaceRegWith - Replace all instances of FromReg with ToReg in the machine function. More...
 
MachineInstrgetVRegDef (Register Reg) const
 getVRegDef - Return the machine instr that defines the specified virtual register or null if none is found. More...
 
MachineInstrgetUniqueVRegDef (Register Reg) const
 getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or null if none is found. More...
 
void clearKillFlags (Register Reg) const
 clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the MachineOperand. More...
 
void dumpUses (Register RegNo) const
 
bool isConstantPhysReg (MCRegister PhysReg) const
 Returns true if PhysReg is unallocatable and constant throughout the function. More...
 
PSetIterator getPressureSets (Register RegUnit) const
 Get an iterator over the pressure sets affected by the given physical or virtual register. More...
 
const TargetRegisterClassgetRegClass (Register Reg) const
 Return the register class of the specified virtual register. More...
 
const TargetRegisterClassgetRegClassOrNull (Register Reg) const
 Return the register class of Reg, or null if Reg has not been assigned a register class yet. More...
 
const RegisterBankgetRegBankOrNull (Register Reg) const
 Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been assigned a register class. More...
 
const RegClassOrRegBankgetRegClassOrRegBank (Register Reg) const
 Return the register bank or register class of Reg. More...
 
void setRegClass (Register Reg, const TargetRegisterClass *RC)
 setRegClass - Set the register class of the specified virtual register. More...
 
void setRegBank (Register Reg, const RegisterBank &RegBank)
 Set the register bank to RegBank for Reg. More...
 
void setRegClassOrRegBank (Register Reg, const RegClassOrRegBank &RCOrRB)
 
const TargetRegisterClassconstrainRegClass (Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
 constrainRegClass - Constrain the register class of the specified virtual register to be a common subclass of RC and the current register class, but only if the new class has at least MinNumRegs registers. More...
 
bool constrainRegAttrs (Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0)
 Constrain the register class or the register bank of the virtual register Reg (and low-level type) to be a common subclass or a common bank of both registers provided respectively (and a common low-level type). More...
 
bool recomputeRegClass (Register Reg)
 recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the constraints from the instructions using Reg. More...
 
Register createVirtualRegister (const TargetRegisterClass *RegClass, StringRef Name="")
 createVirtualRegister - Create and return a new virtual register in the function with the specified register class. More...
 
Register cloneVirtualRegister (Register VReg, StringRef Name="")
 Create and return a new virtual register in the function with the same attributes as the given register. More...
 
LLT getType (Register Reg) const
 Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register. More...
 
void setType (Register VReg, LLT Ty)
 Set the low-level type of VReg to Ty. More...
 
Register createGenericVirtualRegister (LLT Ty, StringRef Name="")
 Create and return a new generic virtual register with low-level type Ty. More...
 
void clearVirtRegTypes ()
 Remove all types associated to virtual registers (after instruction selection and constraining of all generic virtual registers). More...
 
Register createIncompleteVirtualRegister (StringRef Name="")
 Creates a new virtual register that has no register class, register bank or size assigned yet. More...
 
unsigned getNumVirtRegs () const
 getNumVirtRegs - Return the number of virtual registers created. More...
 
void clearVirtRegs ()
 clearVirtRegs - Remove all virtual registers (after physreg assignment). More...
 
void setRegAllocationHint (Register VReg, unsigned Type, Register PrefReg)
 setRegAllocationHint - Specify a register allocation hint for the specified virtual register. More...
 
void addRegAllocationHint (Register VReg, Register PrefReg)
 addRegAllocationHint - Add a register allocation hint to the hints vector for VReg. More...
 
void setSimpleHint (Register VReg, Register PrefReg)
 Specify the preferred (target independent) register allocation hint for the specified virtual register. More...
 
void clearSimpleHint (Register VReg)
 
std::pair< Register, RegistergetRegAllocationHint (Register VReg) const
 getRegAllocationHint - Return the register allocation hint for the specified virtual register. More...
 
Register getSimpleHint (Register VReg) const
 getSimpleHint - same as getRegAllocationHint except it will only return a target independent hint. More...
 
const std::pair< Register, SmallVector< Register, 4 > > & getRegAllocationHints (Register VReg) const
 getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg. More...
 
void markUsesInDebugValueAsUndef (Register Reg) const
 markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined which causes the DBG_VALUE to be deleted during LiveDebugVariables analysis. More...
 
void updateDbgUsersToReg (MCRegister OldReg, MCRegister NewReg, ArrayRef< MachineInstr * > Users) const
 updateDbgUsersToReg - Update a collection of DBG_VALUE instructions to refer to the designated register. More...
 
bool isPhysRegModified (MCRegister PhysReg, bool SkipNoReturnDef=false) const
 Return true if the specified register is modified in this function. More...
 
bool isPhysRegUsed (MCRegister PhysReg, bool SkipRegMaskTest=false) const
 Return true if the specified register is modified or read in this function. More...
 
void addPhysRegsUsedFromRegMask (const uint32_t *RegMask)
 addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used. More...
 
const BitVectorgetUsedPhysRegsMask () const
 
void freezeReservedRegs (const MachineFunction &)
 freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before allocation begins. More...
 
bool reservedRegsFrozen () const
 reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved registers stays constant. More...
 
bool canReserveReg (MCRegister PhysReg) const
 canReserveReg - Returns true if PhysReg can be used as a reserved register. More...
 
const BitVectorgetReservedRegs () const
 getReservedRegs - Returns a reference to the frozen set of reserved registers. More...
 
bool isReserved (MCRegister PhysReg) const
 isReserved - Returns true when PhysReg is a reserved register. More...
 
bool isReservedRegUnit (unsigned Unit) const
 Returns true when the given register unit is considered reserved. More...
 
bool isAllocatable (MCRegister PhysReg) const
 isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been reserved. More...
 
void addLiveIn (MCRegister Reg, Register vreg=Register())
 addLiveIn - Add the specified register as a live-in. More...
 
livein_iterator livein_begin () const
 
livein_iterator livein_end () const
 
bool livein_empty () const
 
ArrayRef< std::pair< MCRegister, Register > > liveins () const
 
bool isLiveIn (Register Reg) const
 
MCRegister getLiveInPhysReg (Register VReg) const
 getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical register. More...
 
Register getLiveInVirtReg (MCRegister PReg) const
 getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical register. More...
 
void EmitLiveInCopies (MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
 EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block. More...
 
LaneBitmask getMaxLaneMaskForVReg (Register Reg) const
 Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual register Reg. More...
 

Static Public Member Functions

static reg_iterator reg_end ()
 
static reg_instr_iterator reg_instr_end ()
 
static reg_bundle_iterator reg_bundle_end ()
 
static reg_nodbg_iterator reg_nodbg_end ()
 
static reg_instr_nodbg_iterator reg_instr_nodbg_end ()
 
static reg_bundle_nodbg_iterator reg_bundle_nodbg_end ()
 
static def_iterator def_end ()
 
static def_instr_iterator def_instr_end ()
 
static def_bundle_iterator def_bundle_end ()
 
static use_iterator use_end ()
 
static use_instr_iterator use_instr_end ()
 
static use_bundle_iterator use_bundle_end ()
 
static use_nodbg_iterator use_nodbg_end ()
 
static use_instr_nodbg_iterator use_instr_nodbg_end ()
 
static use_bundle_nodbg_iterator use_bundle_nodbg_end ()
 

Friends

template<bool , bool , bool , bool , bool , bool >
class defusechain_iterator
 
template<bool , bool , bool , bool , bool , bool >
class defusechain_instr_iterator
 

Detailed Description

MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.

Definition at line 52 of file MachineRegisterInfo.h.

Member Typedef Documentation

◆ def_bundle_iterator

def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register, stepping by bundle.

Definition at line 412 of file MachineRegisterInfo.h.

◆ def_instr_iterator

def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register, stepping by MachineInst.

Definition at line 396 of file MachineRegisterInfo.h.

◆ def_iterator

def_iterator/def_begin/def_end - Walk all defs of the specified register.

Definition at line 383 of file MachineRegisterInfo.h.

◆ livein_iterator

Definition at line 951 of file MachineRegisterInfo.h.

◆ reg_bundle_iterator

reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified register, stepping by bundle.

Definition at line 309 of file MachineRegisterInfo.h.

◆ reg_bundle_nodbg_iterator

reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the specified register, stepping by bundle, skipping those marked as Debug.

Definition at line 362 of file MachineRegisterInfo.h.

◆ reg_instr_iterator

reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register, stepping by MachineInstr.

Definition at line 293 of file MachineRegisterInfo.h.

◆ reg_instr_nodbg_iterator

reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the specified register, stepping by MachineInstr, skipping those marked as Debug.

Definition at line 345 of file MachineRegisterInfo.h.

◆ reg_iterator

reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.

Definition at line 280 of file MachineRegisterInfo.h.

◆ reg_nodbg_iterator

reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register, skipping those marked as Debug.

Definition at line 328 of file MachineRegisterInfo.h.

◆ use_bundle_iterator

use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register, stepping by bundle.

Definition at line 492 of file MachineRegisterInfo.h.

◆ use_bundle_nodbg_iterator

use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specified register, stepping by bundle, skipping those marked as Debug.

Definition at line 551 of file MachineRegisterInfo.h.

◆ use_instr_iterator

use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register, stepping by MachineInstr.

Definition at line 476 of file MachineRegisterInfo.h.

◆ use_instr_nodbg_iterator

use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified register, stepping by MachineInstr, skipping those marked as Debug.

Definition at line 534 of file MachineRegisterInfo.h.

◆ use_iterator

use_iterator/use_begin/use_end - Walk all uses of the specified register.

Definition at line 463 of file MachineRegisterInfo.h.

◆ use_nodbg_iterator

use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register, skipping those marked as Debug.

Definition at line 517 of file MachineRegisterInfo.h.

Constructor & Destructor Documentation

◆ MachineRegisterInfo() [1/2]

MachineRegisterInfo::MachineRegisterInfo ( MachineFunction MF)
explicit

◆ MachineRegisterInfo() [2/2]

llvm::MachineRegisterInfo::MachineRegisterInfo ( const MachineRegisterInfo )
delete

Member Function Documentation

◆ addLiveIn()

void llvm::MachineRegisterInfo::addLiveIn ( MCRegister  Reg,
Register  vreg = Register() 
)
inline

◆ addPhysRegsUsedFromRegMask()

void llvm::MachineRegisterInfo::addPhysRegsUsedFromRegMask ( const uint32_t RegMask)
inline

addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.

This corresponds to the bit mask attached to register mask operands.

Definition at line 866 of file MachineRegisterInfo.h.

Referenced by llvm::MIRParserImpl::setupRegisterInfo().

◆ addRegAllocationHint()

void llvm::MachineRegisterInfo::addRegAllocationHint ( Register  VReg,
Register  PrefReg 
)
inline

addRegAllocationHint - Add a register allocation hint to the hints vector for VReg.

Definition at line 774 of file MachineRegisterInfo.h.

References assert(), and llvm::Register::isVirtualRegister().

◆ addRegOperandToUseList()

void MachineRegisterInfo::addRegOperandToUseList ( MachineOperand MO)

◆ canReserveReg()

bool llvm::MachineRegisterInfo::canReserveReg ( MCRegister  PhysReg) const
inline

canReserveReg - Returns true if PhysReg can be used as a reserved register.

Any register can be reserved before freezeReservedRegs() is called.

Definition at line 897 of file MachineRegisterInfo.h.

References reservedRegsFrozen().

Referenced by llvm::MipsRegisterInfo::canRealignStack(), llvm::M68kRegisterInfo::canRealignStack(), llvm::X86RegisterInfo::canRealignStack(), and llvm::ARMBaseRegisterInfo::canRealignStack().

◆ clearKillFlags()

void MachineRegisterInfo::clearKillFlags ( Register  Reg) const

clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the MachineOperand.

This function is used by optimization passes which extend register lifetimes and need only preserve conservative kill flag information.

Definition at line 431 of file MachineRegisterInfo.cpp.

References Reg, and use_operands().

Referenced by emitIndirectDst(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::fixupIsDeadOrKill(), hoistAndMergeSGPRInits(), INITIALIZE_PASS(), insertPHI(), llvm::AArch64InstrInfo::insertSelect(), llvm::SIInstrInfo::moveToVALU(), llvm::HexagonInstrInfo::PredicateInstruction(), and llvm::SelectionDAGISel::runOnMachineFunction().

◆ clearSimpleHint()

void llvm::MachineRegisterInfo::clearSimpleHint ( Register  VReg)
inline

Definition at line 785 of file MachineRegisterInfo.h.

References assert(), and llvm::IndexedMap< T, ToIndexT >::clear().

◆ clearVirtRegs()

void MachineRegisterInfo::clearVirtRegs ( )

◆ clearVirtRegTypes()

void MachineRegisterInfo::clearVirtRegTypes ( )

Remove all types associated to virtual registers (after instruction selection and constraining of all generic virtual registers).

Definition at line 199 of file MachineRegisterInfo.cpp.

References llvm::IndexedMap< T, ToIndexT >::clear().

Referenced by llvm::InstructionSelect::runOnMachineFunction().

◆ cloneVirtualRegister()

Register MachineRegisterInfo::cloneVirtualRegister ( Register  VReg,
StringRef  Name = "" 
)

◆ constrainRegAttrs()

bool MachineRegisterInfo::constrainRegAttrs ( Register  Reg,
Register  ConstrainingReg,
unsigned  MinNumRegs = 0 
)

Constrain the register class or the register bank of the virtual register Reg (and low-level type) to be a common subclass or a common bank of both registers provided respectively (and a common low-level type).

Do nothing if any of the attributes (classes, banks, or low-level types) of the registers are deemed incompatible, or if the resulting register will have a class smaller than before and of size less than MinNumRegs. Return true if such register attributes exist, false otherwise.

Note
Use this method instead of constrainRegClass and RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG ISel / FastISel and GlobalISel's InstructionSelect pass respectively.

Definition at line 92 of file MachineRegisterInfo.cpp.

References constrainRegClass(), getRegClassOrRegBank(), getType(), llvm::LLT::isValid(), Reg, setRegClassOrRegBank(), and setType().

Referenced by llvm::CombinerHelper::replaceRegWith().

◆ constrainRegClass()

const TargetRegisterClass * MachineRegisterInfo::constrainRegClass ( Register  Reg,
const TargetRegisterClass RC,
unsigned  MinNumRegs = 0 
)

constrainRegClass - Constrain the register class of the specified virtual register to be a common subclass of RC and the current register class, but only if the new class has at least MinNumRegs registers.

Return the new register class, or NULL if no such class exists. This should only be used when the constraint is known to be trivial, like GR32 -> GR32_NOSP. Beware of increasing register pressure.

Note
Assumes that the register has a register class assigned. Use RegisterBankInfo::constrainGenericRegister in GlobalISel's InstructionSelect pass and constrainRegAttrs in every other pass, including non-select passes of GlobalISel, instead.

Definition at line 85 of file MachineRegisterInfo.cpp.

References constrainRegClass(), getRegClass(), and Reg.

Referenced by llvm::MachineBasicBlock::addLiveIn(), AdjustBaseAndOffset(), llvm::X86InstrInfo::classifyLEAReg(), llvm::RegisterBankInfo::constrainGenericRegister(), llvm::FastISel::constrainOperandRegClass(), constrainRegAttrs(), llvm::X86InstrInfo::convertToThreeAddress(), createPostIncLoadStore(), llvm::FastISel::fastEmitInst_extractsubreg(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::SIInstrInfo::foldMemoryOperandImpl(), genFusedMultiply(), genMaddR(), llvm::AArch64InstrInfo::insertSelect(), llvm::SystemZInstrInfo::insertSelect(), llvm::Thumb2InstrInfo::loadRegFromStackSlot(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::AArch64RegisterInfo::materializeFrameBaseRegister(), llvm::PPCRegisterInfo::materializeFrameBaseRegister(), llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister(), llvm::SIInstrInfo::moveToVALU(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::PeelSingleBlockLoop(), llvm::TargetInstrInfo::reassociateOps(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::rewriteT2FrameIndex(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::Thumb2InstrInfo::storeRegToStackSlot(), llvm::AArch64InstrInfo::storeRegToStackSlot(), llvm::SIInstrInfo::storeRegToStackSlot(), llvm::TailDuplicator::tailDuplicateAndUpdate(), UpdateOperandRegClass(), and updateOperandRegConstraints().

◆ createGenericVirtualRegister()

Register MachineRegisterInfo::createGenericVirtualRegister ( LLT  Ty,
StringRef  Name = "" 
)

Create and return a new generic virtual register with low-level type Ty.

Definition at line 188 of file MachineRegisterInfo.cpp.

References createIncompleteVirtualRegister(), llvm::MachineRegisterInfo::Delegate::MRI_NoteNewVirtualRegister(), Reg, and setType().

Referenced by allocateHSAUserSGPRs(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::applyMappingSBufferLoad(), llvm::LegalizerHelper::bitcastDst(), buildCopyToRegs(), llvm::MachineIRBuilder::buildMaskLowPtrBits(), llvm::MachineIRBuilder::buildSequence(), llvm::RegisterBankInfo::OperandsMapper::createVRegs(), llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), llvm::CallLowering::ValueHandler::extendRegister(), extractParts(), llvm::LegalizerHelper::fewerElementsVectorCasts(), llvm::LegalizerHelper::fewerElementsVectorCmp(), llvm::LegalizerHelper::fewerElementsVectorMultiEltType(), llvm::LegalizerHelper::fewerElementsVectorPhi(), llvm::LegalizerHelper::fewerElementsVectorSelect(), llvm::AMDGPULegalizerInfo::getImplicitArgPtr(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), llvm::CallLowering::handleAssignments(), llvm::CallLowering::insertSRetIncomingArgument(), llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::AMDGPULegalizerInfo::legalizeFFloor(), llvm::AMDGPULegalizerInfo::legalizeGlobalValue(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeSignedDIV_REM(), llvm::AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr(), llvm::LegalizerHelper::lower(), llvm::MipsCallLowering::lowerCall(), llvm::AMDGPUCallLowering::lowerFormalArgumentsKernel(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::LegalizerHelper::lowerLoad(), llvm::LegalizerHelper::lowerMergeValues(), llvm::CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(), llvm::MachineIRBuilder::materializePtrAdd(), mergeVectorRegsToResultRegs(), llvm::LegalizerHelper::moreElementsVector(), llvm::LegalizerHelper::moreElementsVectorSrc(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarAddSub(), llvm::LegalizerHelper::narrowScalarDst(), llvm::LegalizerHelper::narrowScalarExtract(), llvm::LegalizerHelper::narrowScalarInsert(), llvm::LegalizerHelper::narrowScalarShift(), llvm::LegalizerHelper::narrowScalarShiftByConstant(), llvm::AMDGPUCallLowering::passSpecialInputs(), llvm::LegalizerHelper::reduceLoadStoreWidth(), llvm::LegalizerHelper::reduceOperationWidth(), llvm::AMDGPURegisterBankInfo::split64BitValueForMapping(), llvm::LegalizerHelper::widenScalar(), llvm::LegalizerHelper::widenScalarDst(), and llvm::LegalizerHelper::widenWithUnmerge().

◆ createIncompleteVirtualRegister()

Register MachineRegisterInfo::createIncompleteVirtualRegister ( StringRef  Name = "")

Creates a new virtual register that has no register class, register bank or size assigned yet.

This is only allowed to be used temporarily while constructing machine instructions. Most operations are undefined on an incomplete register until one of setRegClass(), setRegBank() or setSize() has been called on it.

Definition at line 146 of file MachineRegisterInfo.cpp.

References getNumVirtRegs(), llvm::Register::index2VirtReg(), insertVRegByName(), and Reg.

Referenced by cloneVirtualRegister(), createGenericVirtualRegister(), createVirtualRegister(), llvm::PerFunctionMIParsingState::getVRegInfo(), and llvm::PerFunctionMIParsingState::getVRegInfoNamed().

◆ createVirtualRegister()

Register MachineRegisterInfo::createVirtualRegister ( const TargetRegisterClass RegClass,
StringRef  Name = "" 
)

createVirtualRegister - Create and return a new virtual register in the function with the specified register class.

Definition at line 158 of file MachineRegisterInfo.cpp.

References assert(), createIncompleteVirtualRegister(), llvm::TargetRegisterClass::isAllocatable(), llvm::MachineRegisterInfo::Delegate::MRI_NoteNewVirtualRegister(), and Reg.

Referenced by llvm::SITargetLowering::AddIMGInit(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineFunction::addLiveIn(), addLiveIn(), llvm::SIInstrInfo::buildExtractSubReg(), buildRSRC(), llvm::AMDGPURegisterBankInfo::buildVCopy(), llvm::X86InstrInfo::classifyLEAReg(), llvm::AMDGPURegisterBankInfo::constrainOpWithReadfirstlane(), llvm::constrainRegToClass(), llvm::SIInstrInfo::convertNonUniformIfRegion(), llvm::SIInstrInfo::convertNonUniformLoopRegion(), createBBSelectReg(), llvm::SwiftErrorValueTracking::createEntriesInEntryBlock(), llvm::LiveRangeEdit::createFrom(), createLaneMaskReg(), llvm::PeelingModuloScheduleExpander::CreateLCSSAExitingBlock(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::FunctionLoweringInfo::CreateReg(), llvm::FastISel::createResultReg(), llvm::HexagonInstrInfo::createVR(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::RISCVRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::SystemZRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::PPCTargetLowering::EmitAtomicBinary(), llvm::VETargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::VETargetLowering::emitEHSjLjSetJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::WebAssemblyFrameLowering::emitEpilogue(), emitFrameOffsetAdj(), llvm::SITargetLowering::emitGWSMemViolTestLoop(), emitIndirectDst(), emitIndirectSrc(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), emitLoadM0FromVGPRLoop(), emitLoadSRsrcFromVGPRLoop(), llvm::PPCTargetLowering::EmitPartwordAtomicBinary(), llvm::PPCTargetLowering::emitProbedAlloca(), llvm::MipsSEFrameLowering::emitPrologue(), llvm::WebAssemblyFrameLowering::emitPrologue(), emitReadCycleWidePseudo(), llvm::MSP430TargetLowering::EmitShiftInstr(), llvm::VETargetLowering::emitSjLjDispatchBlock(), emitThumbRegPlusImmInReg(), emitXBegin(), llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), llvm::SIInstrInfo::expandMovDPP64(), extractRsrcPtr(), llvm::ARMBaseInstrInfo::FoldImmediate(), foldVGPRCopyIntoRegSequence(), forceReg(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), genNeg(), genTPEntry(), genTPLoopBody(), llvm::SIInstrInfo::getAddNoCarry(), llvm::FunctionLoweringInfo::getCatchPadExceptionPointerVReg(), llvm::MipsFunctionInfo::getGlobalBaseReg(), llvm::SparcInstrInfo::getGlobalBaseReg(), llvm::M68kInstrInfo::getGlobalBaseReg(), llvm::X86InstrInfo::getGlobalBaseReg(), getIndirectSGPRIdx(), llvm::SwiftErrorValueTracking::getOrCreateVReg(), llvm::SwiftErrorValueTracking::getOrCreateVRegDefAt(), getRegistersForValue(), GetRegistersForValue(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), llvm::RISCVInstrInfo::getVLENFactoredAmount(), llvm::MipsFunctionInfo::initGlobalBaseReg(), INITIALIZE_PASS(), llvm::SIInstrInfo::insertEQ(), llvm::RISCVInstrInfo::insertIndirectBranch(), llvm::SIInstrInfo::insertIndirectBranch(), llvm::SIInstrInfo::insertNE(), InsertNewDef(), insertPHI(), llvm::SystemZInstrInfo::insertSelect(), llvm::SIInstrInfo::insertSelect(), llvm::PPCInstrInfo::insertSelect(), llvm::SIInstrInfo::insertVectorSelect(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::MipsSEInstrInfo::loadImmediate(), loadM0FromVGPR(), llvm::X86InstrInfo::loadRegFromStackSlot(), llvm::HexagonTargetLowering::LowerCallResult(), LowerCallResults(), llvm::PPCRegisterInfo::lowerCRBitRestore(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), LowerFPToInt(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::AMDGPUCallLowering::lowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SIRegisterInfo::materializeFrameBaseRegister(), llvm::AArch64RegisterInfo::materializeFrameBaseRegister(), llvm::PPCRegisterInfo::materializeFrameBaseRegister(), llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister(), maybeRewriteToDrop(), moveAndTeeForMultiUse(), moveForSingleUse(), llvm::PeelingModuloScheduleExpander::moveStageBetweenBlocks(), llvm::SIInstrInfo::moveToVALU(), llvm::RISCVInstrInfo::movImm(), llvm::PeelSingleBlockLoop(), llvm::PPCRegisterInfo::prepareDynamicAlloca(), llvm::VETargetLowering::prepareMBB(), llvm::VETargetLowering::prepareSymbol(), llvm::SwiftErrorValueTracking::propagateVRegs(), llvm::SIInstrInfo::readlaneVGPRToSGPR(), llvm::TargetInstrInfo::reassociateOps(), rematerializeCheapDef(), llvm::AVRDynAllocaSR::runOnMachineFunction(), selectCopy(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::LiveIntervals::splitSeparateComponents(), llvm::X86InstrInfo::storeRegToStackSlot(), unpackF64OnRV32DSoftABI(), unpackFromRegLoc(), and updateOperand().

◆ def_begin()

def_iterator llvm::MachineRegisterInfo::def_begin ( Register  RegNo) const
inline

◆ def_bundle_begin()

def_bundle_iterator llvm::MachineRegisterInfo::def_bundle_begin ( Register  RegNo) const
inline

Definition at line 413 of file MachineRegisterInfo.h.

Referenced by def_bundles().

◆ def_bundle_end()

static def_bundle_iterator llvm::MachineRegisterInfo::def_bundle_end ( )
inlinestatic

Definition at line 416 of file MachineRegisterInfo.h.

Referenced by def_bundles().

◆ def_bundles()

iterator_range<def_bundle_iterator> llvm::MachineRegisterInfo::def_bundles ( Register  Reg) const
inline

Definition at line 420 of file MachineRegisterInfo.h.

References def_bundle_begin(), def_bundle_end(), llvm::make_range(), and Reg.

◆ def_empty()

bool llvm::MachineRegisterInfo::def_empty ( Register  RegNo) const
inline

def_empty - Return true if there are no instructions defining the specified register (it may be live-in).

Definition at line 426 of file MachineRegisterInfo.h.

References def_begin(), and def_end().

Referenced by getUniqueVRegDef(), isConstantPhysReg(), isSSA(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::MachineOperand::print(), and llvm::InstructionSelect::runOnMachineFunction().

◆ def_end()

static def_iterator llvm::MachineRegisterInfo::def_end ( )
inlinestatic

◆ def_instr_begin()

def_instr_iterator llvm::MachineRegisterInfo::def_instr_begin ( Register  RegNo) const
inline

◆ def_instr_end()

static def_instr_iterator llvm::MachineRegisterInfo::def_instr_end ( )
inlinestatic

◆ def_instructions()

iterator_range<def_instr_iterator> llvm::MachineRegisterInfo::def_instructions ( Register  Reg) const
inline

◆ def_operands()

iterator_range<def_iterator> llvm::MachineRegisterInfo::def_operands ( Register  Reg) const
inline

◆ disableCalleeSavedRegister()

void MachineRegisterInfo::disableCalleeSavedRegister ( MCRegister  Reg)

Disables the register from the list of CSRs.

I.e. the register will not appear as part of the CSR mask.

See also
UpdatedCalleeSavedRegs.

Definition at line 598 of file MachineRegisterInfo.cpp.

References assert(), llvm::erase_value(), llvm::TargetRegisterInfo::getCalleeSavedRegs(), getTargetRegisterInfo(), I, llvm::MCRegAliasIterator::isValid(), Reg, and TRI.

◆ dumpUses()

LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses ( Register  RegNo) const

Definition at line 501 of file MachineRegisterInfo.cpp.

References I, Reg, and use_instructions().

◆ EmitLiveInCopies()

void MachineRegisterInfo::EmitLiveInCopies ( MachineBasicBlock EntryMBB,
const TargetRegisterInfo TRI,
const TargetInstrInfo TII 
)

EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.

Definition at line 464 of file MachineRegisterInfo.cpp.

References llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::numbers::e, i, TII, and use_nodbg_empty().

Referenced by llvm::SelectionDAGISel::runOnMachineFunction().

◆ freezeReservedRegs()

void MachineRegisterInfo::freezeReservedRegs ( const MachineFunction MF)

freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before allocation begins.

Definition at line 507 of file MachineRegisterInfo.cpp.

References assert(), llvm::TargetRegisterInfo::getReservedRegs(), getTargetRegisterInfo(), and llvm::BitVector::size().

Referenced by createFrameHelperMachineFunction(), llvm::TargetLoweringBase::finalizeLowering(), llvm::RegAllocBase::init(), and llvm::MIRParserImpl::initializeMachineFunction().

◆ getCalleeSavedRegs()

const MCPhysReg * MachineRegisterInfo::getCalleeSavedRegs ( ) const

◆ getLiveInPhysReg()

MCRegister MachineRegisterInfo::getLiveInPhysReg ( Register  VReg) const

getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical register.

Definition at line 445 of file MachineRegisterInfo.cpp.

References liveins().

Referenced by llvm::TargetLowering::parametersInCSRMatch().

◆ getLiveInVirtReg()

Register MachineRegisterInfo::getLiveInVirtReg ( MCRegister  PReg) const

getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical register.

Definition at line 454 of file MachineRegisterInfo.cpp.

References liveins().

Referenced by llvm::MachineFunction::addLiveIn(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), and llvm::getFunctionLiveInPhysReg().

◆ getMaxLaneMaskForVReg()

LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg ( Register  Reg) const

◆ getNumVirtRegs()

unsigned llvm::MachineRegisterInfo::getNumVirtRegs ( ) const
inline

◆ getOneDef()

MachineOperand* llvm::MachineRegisterInfo::getOneDef ( Register  Reg) const
inline

Returns the defining operand if there is exactly one operand defining the specified register, otherwise nullptr.

Definition at line 450 of file MachineRegisterInfo.h.

References def_begin(), def_end(), and Reg.

Referenced by isSSA().

◆ getPressureSets()

PSetIterator llvm::MachineRegisterInfo::getPressureSets ( Register  RegUnit) const
inline

Get an iterator over the pressure sets affected by the given physical or virtual register.

If RegUnit is physical, it must be a register unit (from MCRegUnitIterator).

Definition at line 1228 of file MachineRegisterInfo.h.

Referenced by llvm::PressureDiff::addPressureChange(), decreaseSetPressure(), llvm::GCNRegPressure::inc(), llvm::RegPressureTracker::increaseRegPressure(), and increaseSetPressure().

◆ getRegAllocationHint()

std::pair<Register, Register> llvm::MachineRegisterInfo::getRegAllocationHint ( Register  VReg) const
inline

getRegAllocationHint - Return the register allocation hint for the specified virtual register.

If there are many hints, this returns the one with the greatest weight.

Definition at line 795 of file MachineRegisterInfo.h.

References assert(), llvm::Register::id(), llvm::Register::isVirtual(), Register, and llvm::IndexedMap< T, ToIndexT >::size().

Referenced by llvm::ARMBaseRegisterInfo::getRegAllocationHints(), getSimpleHint(), llvm::VirtRegMap::hasKnownPreference(), and llvm::ARMBaseRegisterInfo::updateRegAllocHint().

◆ getRegAllocationHints()

const std::pair<Register, SmallVector<Register, 4> >& llvm::MachineRegisterInfo::getRegAllocationHints ( Register  VReg) const
inline

getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg.

Definition at line 814 of file MachineRegisterInfo.h.

References assert(), and llvm::Register::isVirtual().

Referenced by llvm::TargetRegisterInfo::getRegAllocationHints().

◆ getRegBankOrNull()

const RegisterBank* llvm::MachineRegisterInfo::getRegBankOrNull ( Register  Reg) const
inline

Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been assigned a register class.

Note
It is possible to get the register bank from the register class via RegisterBankInfo::getRegBankFromRegClass.

Definition at line 660 of file MachineRegisterInfo.h.

References llvm::PointerUnion< PTs >::dyn_cast(), and Reg.

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), constrainRegToBank(), fixupPHIOpBanks(), and llvm::printRegClassOrBank().

◆ getRegClass()

const TargetRegisterClass* llvm::MachineRegisterInfo::getRegClass ( Register  Reg) const
inline

Return the register class of the specified virtual register.

This shouldn't be used directly unless Reg has a register class.

See also
getRegClassOrNull when this might happen.

Definition at line 634 of file MachineRegisterInfo.h.

References assert(), and Reg.

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::MachineFunction::addLiveIn(), llvm::RegAllocBase::allocatePhysRegs(), llvm::VirtRegMap::assignVirt2StackSlot(), llvm::LiveRangeEdit::calculateRegClassAndHint(), canFoldCopy(), canFoldIntoCSel(), llvm::AArch64InstrInfo::canInsertSelect(), llvm::SystemZInstrInfo::canInsertSelect(), llvm::SIInstrInfo::canInsertSelect(), llvm::X86InstrInfo::canInsertSelect(), llvm::PPCInstrInfo::canInsertSelect(), llvm::X86_MC::X86MCInstrAnalysis::clearsSuperRegisters(), constrainRegClass(), convertImplicitDefToConstZero(), copyHint(), llvm::WebAssemblyInstrInfo::copyPhysReg(), llvm::NVPTXInstrInfo::copyPhysReg(), llvm::AllocationOrder::create(), llvm::LiveRangeEdit::createFrom(), llvm::PeelingModuloScheduleExpander::CreateLCSSAExitingBlock(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::VETargetLowering::emitEHSjLjSetJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), emitIndirectDst(), emitIndirectSrc(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), emitLoadSRsrcFromVGPRLoop(), emitXBegin(), llvm::RegAllocBase::enqueue(), llvm::HexagonEvaluator::evaluate(), llvm::HexagonBlockRanges::expandToSubRegs(), llvm::FastISel::fastEmitInst_extractsubreg(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::SIInstrInfo::foldMemoryOperandImpl(), foldPatchpoint(), foldVGPRCopyIntoRegSequence(), llvm::BitTracker::MachineEvaluator::getCell(), getCopyRegClasses(), llvm::ScheduleDAGInstrs::getLaneMaskForMO(), getMaxLaneMaskForVReg(), llvm::PPCInstrInfo::getOperandLatency(), llvm::SIInstrInfo::getOpRegClass(), getRC32(), llvm::PPCRegisterInfo::getRegAllocationHints(), llvm::SystemZRegisterInfo::getRegAllocationHints(), llvm::X86RegisterInfo::getRegAllocationHints(), llvm::ARMBaseRegisterInfo::getRegAllocationHints(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::TargetRegisterInfo::getRegSizeInBits(), getRegTy(), llvm::WebAssemblyAsmPrinter::getRegType(), llvm::NVPTXAsmPrinter::getVirtualRegisterName(), hasVectorOperands(), llvm::MachineSSAUpdater::Initialize(), INITIALIZE_PASS(), insertPHI(), llvm::SystemZInstrInfo::insertSelect(), llvm::SIInstrInfo::insertSelect(), llvm::X86InstrInfo::insertSelect(), llvm::PPCInstrInfo::insertSelect(), llvm::SIInstrInfo::insertVectorSelect(), IsAGPROperand(), isCrossCopy(), isFPR64(), llvm::SIInstrInfo::isLegalRegOperand(), isNonFoldablePartialRegisterLoad(), llvm::isOfRegClass(), llvm::HexagonMCInstrInfo::isPredReg(), llvm::SIRegisterInfo::isSGPRReg(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsFLAT(), llvm::SIInstrInfo::legalizeOperandsSMRD(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::WebAssemblyMCInstLower::lower(), LowerCallResults(), LowerFPToInt(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::HexagonEvaluator::mask(), matchAliasCondition(), llvm::SIInstrInfo::materializeImmediate(), maybeRewriteToDrop(), moveAndTeeForMultiUse(), moveForSingleUse(), llvm::PeelingModuloScheduleExpander::moveStageBetweenBlocks(), llvm::SIInstrInfo::moveToVALU(), optimizeCall(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::PeelSingleBlockLoop(), llvm::VirtRegMap::print(), PrintNodeInfo(), llvm::printRegClassOrBank(), propagateLocalCopies(), llvm::SIInstrInfo::readlaneVGPRToSGPR(), recomputeRegClass(), rematerializeCheapDef(), llvm::PeelingModuloScheduleExpander::rewriteUsesOf(), llvm::InstructionSelect::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), scavengeVReg(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::CoalescerPair::setRegisters(), shouldTrackSubRegLiveness(), llvm::LiveIntervals::splitSeparateComponents(), llvm::TailDuplicator::tailDuplicateAndUpdate(), tryChangeVGPRtoSGPRinCopy(), unstackifyVRegsUsedInSplitBB(), updateOperand(), UpdateOperandRegClass(), llvm::SIInstrInfo::usesConstantBus(), and llvm::SIInstrInfo::verifyInstruction().

◆ getRegClassOrNull()

const TargetRegisterClass* llvm::MachineRegisterInfo::getRegClassOrNull ( Register  Reg) const
inline

Return the register class of Reg, or null if Reg has not been assigned a register class yet.

Note
A null register class can only happen when these two conditions are met:
  1. Generic virtual registers are created.
  2. The machine function has not completely been through the instruction selection process. None of this condition is possible without GlobalISel for now. In other words, if GlobalISel is not used or if the query happens after the select pass, using getRegClass is safe.

Definition at line 651 of file MachineRegisterInfo.h.

References llvm::PointerUnion< PTs >::dyn_cast(), and Reg.

Referenced by llvm::SITargetLowering::finalizeLowering(), llvm::AArch64RegisterBankInfo::getInstrMapping(), IsWritingToVCCR(), llvm::printRegClassOrBank(), propagateLocalCopies(), and llvm::InstructionSelect::runOnMachineFunction().

◆ getRegClassOrRegBank()

const RegClassOrRegBank& llvm::MachineRegisterInfo::getRegClassOrRegBank ( Register  Reg) const
inline

Return the register bank or register class of Reg.

Note
Before the register bank gets assigned (i.e., before the RegBankSelect pass) Reg may not have either.

Definition at line 668 of file MachineRegisterInfo.h.

References Reg.

Referenced by llvm::GISelInstProfileBuilder::addNodeIDReg(), llvm::canReplaceReg(), llvm::RegisterBankInfo::constrainGenericRegister(), constrainRegAttrs(), llvm::SIRegisterInfo::getConstrainedRegClassForOperand(), and llvm::RegisterBankInfo::getRegBank().

◆ getReservedRegs()

const BitVector& llvm::MachineRegisterInfo::getReservedRegs ( ) const
inline

getReservedRegs - Returns a reference to the frozen set of reserved registers.

This method should always be preferred to calling TRI::getReservedRegs() when possible.

Definition at line 904 of file MachineRegisterInfo.h.

References assert(), and reservedRegsFrozen().

Referenced by llvm::TargetRegisterInfo::getAllocatableSet(), isReserved(), and llvm::RegisterClassInfo::runOnMachineFunction().

◆ getSimpleHint()

Register llvm::MachineRegisterInfo::getSimpleHint ( Register  VReg) const
inline

getSimpleHint - same as getRegAllocationHint except it will only return a target independent hint.

Definition at line 805 of file MachineRegisterInfo.h.

References assert(), getRegAllocationHint(), llvm::Register::isVirtual(), and Register.

Referenced by llvm::MIRPrinter::convert(), and llvm::VirtRegMap::hasPreferredPhys().

◆ getTargetRegisterInfo()

const TargetRegisterInfo* llvm::MachineRegisterInfo::getTargetRegisterInfo ( ) const
inline

Definition at line 153 of file MachineRegisterInfo.h.

References llvm::TargetSubtargetInfo::getRegisterInfo(), and llvm::MachineFunction::getSubtarget().

Referenced by llvm::addLiveIns(), llvm::LiveIntervalCalc::calculate(), llvm::computeLiveIns(), llvm::LiveInterval::computeSubRangeUndefs(), constrainRegClass(), llvm::WebAssemblyInstrInfo::copyPhysReg(), llvm::PeelingModuloScheduleExpander::CreateLCSSAExitingBlock(), disableCalleeSavedRegister(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyFrameLowering::emitEpilogue(), llvm::WebAssemblyFrameLowering::emitPrologue(), llvm::execMayBeModifiedBeforeAnyUse(), llvm::execMayBeModifiedBeforeUse(), llvm::PeelingModuloScheduleExpander::filterInstructions(), findSurvivorBackwards(), findUseBetween(), freezeReservedRegs(), getCalleeSavedRegs(), getDefRegMask(), llvm::RegisterBankInfo::getRegBankFromConstraints(), getUsedRegMask(), llvm::LiveRegSet::init(), llvm::X86InstrInfo::insertSelect(), isAllocatable(), isConstantPhysReg(), isCrossCopy(), llvm::isOfRegClass(), isPhysRegModified(), isPhysRegUsed(), isReservedRegUnit(), llvm::GCNUpwardRPTracker::isValid(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), MachineRegisterInfo(), llvm::MIPrinter::print(), llvm::GCNRPTracker::printLiveRegs(), llvm::printLivesAt(), PrintNodeInfo(), llvm::recomputeLivenessFlags(), recomputeRegClass(), replaceRegWith(), llvm::PeelingModuloScheduleExpander::rewriteUsesOf(), llvm::MachineFunction::salvageCopySSA(), scavengeFrameVirtualRegsInBlock(), scavengeVReg(), llvm::ARMBaseRegisterInfo::shouldCoalesce(), spillVGPRtoAGPR(), llvm::tryFoldSPUpdateIntoPushPop(), updateDbgUsersToReg(), updateOperandRegConstraints(), llvm::SIInstrInfo::verifyInstruction(), verifyUseList(), and verifyUseLists().

◆ getType()

LLT llvm::MachineRegisterInfo::getType ( Register  Reg) const
inline

Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.

Definition at line 732 of file MachineRegisterInfo.h.

References llvm::Register::isVirtualRegister(), and Reg.

Referenced by llvm::GISelInstProfileBuilder::addNodeIDReg(), llvm::CombinerHelper::applyAshShlToSextInreg(), llvm::CombinerHelper::applyCombineAddP2IToPtrAdd(), llvm::CombinerHelper::applyCombineExtendingLoads(), llvm::CombinerHelper::applyCombineInsertVecElts(), llvm::CombinerHelper::applyCombineMulByNegativeOne(), llvm::CombinerHelper::applyCombineMulToShl(), llvm::CombinerHelper::applyCombineShiftToUnmerge(), llvm::CombinerHelper::applyCombineShlOfExtend(), llvm::CombinerHelper::applyCombineTruncOfExt(), llvm::CombinerHelper::applyCombineTruncOfShl(), llvm::CombinerHelper::applyCombineUnmergeMergeToPlainValues(), llvm::CombinerHelper::applyCombineUnmergeWithDeadLanesToTrunc(), llvm::CombinerHelper::applyCombineUnmergeZExtToZExt(), AMDGPUPostLegalizerCombinerHelper::applyCvtF32UByteN(), llvm::RegisterBankInfo::applyDefaultMapping(), applyDupLane(), llvm::CombinerHelper::applyExtendThroughPhis(), llvm::CombinerHelper::applyExtractVecEltBuildVec(), applyICmpRedundantTrunc(), applyINS(), llvm::AMDGPURegisterBankInfo::applyMappingBFE(), llvm::AMDGPURegisterBankInfo::applyMappingDynStackAlloc(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::applyMappingLoad(), llvm::AMDGPURegisterBankInfo::applyMappingSBufferLoad(), llvm::CombinerHelper::applyOptBrCondByInvertingCond(), llvm::CombinerHelper::applyPtrAddImmedChain(), llvm::CombinerHelper::applyRotateOutOfRange(), llvm::CombinerHelper::applyShiftImmedChain(), llvm::CombinerHelper::applyShiftOfShiftedLogic(), llvm::CombinerHelper::applySimplifyURemByPow2(), AMDGPUPostLegalizerCombinerHelper::applyUCharToFloat(), llvm::CombinerHelper::applyXorOfAndWithSameReg(), llvm::CallLowering::IncomingValueHandler::assignValueToReg(), llvm::LegalizerHelper::bitcast(), llvm::LegalizerHelper::bitcastExtractVectorElt(), llvm::LegalizerHelper::bitcastInsertVectorElt(), buildAnyextOrCopy(), llvm::MachineIRBuilder::buildAtomicCmpXchg(), llvm::MachineIRBuilder::buildAtomicCmpXchgWithSuccess(), buildCopyFromRegs(), buildCopyToRegs(), llvm::MachineIRBuilder::buildSequence(), llvm::AMDGPURegisterBankInfo::buildVCopy(), llvm::canReplaceReg(), cloneVirtualRegister(), llvm::LegalizerHelper::coerceToScalar(), llvm::SITargetLowering::computeKnownBitsForTargetInstr(), llvm::GISelKnownBits::computeKnownBitsImpl(), llvm::GISelKnownBits::computeNumSignBits(), llvm::ConstantFoldExtOp(), llvm::AMDGPURegisterBankInfo::constrainOpWithReadfirstlane(), constrainRegAttrs(), constrainRegToBank(), llvm::CallLowering::ValueHandler::copyArgumentMemory(), llvm::createMemLibcall(), llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), llvm::CallLowering::ValueHandler::extendRegister(), llvm::LegalizerHelper::fewerElementsVectorCasts(), llvm::LegalizerHelper::fewerElementsVectorCmp(), llvm::LegalizerHelper::fewerElementsVectorExtractInsertVectorElt(), llvm::LegalizerHelper::fewerElementsVectorImplicitDef(), llvm::LegalizerHelper::fewerElementsVectorMerge(), llvm::LegalizerHelper::fewerElementsVectorMulo(), llvm::LegalizerHelper::fewerElementsVectorMultiEltType(), llvm::LegalizerHelper::fewerElementsVectorPhi(), llvm::LegalizerHelper::fewerElementsVectorReductions(), llvm::LegalizerHelper::fewerElementsVectorSelect(), llvm::LegalizerHelper::fewerElementsVectorSextInReg(), llvm::LegalizerHelper::fewerElementsVectorShuffle(), llvm::LegalizerHelper::fewerElementsVectorUnmergeValues(), llvm::AMDGPULegalizerInfo::fixStoreSourceType(), fixupPHIOpBanks(), getCmpOperandFoldingProfit(), llvm::getConstantVRegValWithLookThrough(), llvm::SIRegisterInfo::getConstrainedRegClassForOperand(), llvm::getDefSrcRegIgnoringCopies(), llvm::AMDGPULegalizerInfo::getImplicitArgPtr(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::MipsRegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(), llvm::GISelKnownBits::getKnownBits(), llvm::RegisterBankInfo::getRegBank(), llvm::RegisterBankInfo::getRegBankFromConstraints(), llvm::TargetRegisterInfo::getRegSizeInBits(), getTestBitReg(), getTypeFromTypeIdx(), llvm::MachineInstr::getTypeToPrint(), llvm::AMDGPURegisterBankInfo::getValueMappingForPtr(), llvm::LegalizerHelper::getVectorElementPointer(), getVectorFCMP(), getVectorShiftImm(), llvm::CallLowering::handleAssignments(), llvm::AMDGPURegisterBankInfo::handleD16VData(), llvm::AMDGPULegalizerInfo::handleD16VData(), llvm::CallLowering::insertSRetLoads(), llvm::CallLowering::insertSRetStores(), llvm::SITargetLowering::isCanonicalized(), llvm::isKnownToBeAPowerOfTwo(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg(), llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeBufferStore(), llvm::AMDGPULegalizerInfo::legalizeBuildVector(), llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic(), llvm::MipsLegalizerInfo::legalizeCustom(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::AMDGPULegalizerInfo::legalizeExtractVectorElt(), llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV64(), llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFFloor(), llvm::AMDGPULegalizerInfo::legalizeFMad(), llvm::AMDGPULegalizerInfo::legalizeFPTOI(), llvm::AMDGPULegalizerInfo::legalizeFrem(), llvm::AMDGPULegalizerInfo::legalizeFrint(), llvm::AMDGPULegalizerInfo::legalizeGlobalValue(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeInsertVectorElt(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::legalizeITOFP(), llvm::AMDGPULegalizerInfo::legalizeLoad(), llvm::AMDGPULegalizerInfo::legalizeRsqClampIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeShuffleVector(), llvm::AMDGPULegalizerInfo::legalizeSignedDIV_REM(), llvm::AMDGPULegalizerInfo::legalizeSinCos(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM(), llvm::LegalizerHelper::libcall(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerAbsToAddXor(), llvm::LegalizerHelper::lowerAbsToMaxNeg(), llvm::LegalizerHelper::lowerAddSubSatToAddoSubo(), llvm::LegalizerHelper::lowerAddSubSatToMinMax(), llvm::LegalizerHelper::lowerBitcast(), llvm::LegalizerHelper::lowerBitCount(), llvm::LegalizerHelper::lowerBitreverse(), llvm::LegalizerHelper::lowerBswap(), llvm::LegalizerHelper::lowerDynStackAlloc(), llvm::LegalizerHelper::lowerExtract(), llvm::LegalizerHelper::lowerExtractInsertVectorElt(), llvm::LegalizerHelper::lowerFCopySign(), llvm::LegalizerHelper::lowerFFloor(), llvm::LegalizerHelper::lowerFMad(), llvm::LegalizerHelper::lowerFMinNumMaxNum(), llvm::LegalizerHelper::lowerFPOWI(), llvm::LegalizerHelper::lowerFPTOSI(), llvm::LegalizerHelper::lowerFPTOUI(), llvm::LegalizerHelper::lowerFPTRUNC(), llvm::LegalizerHelper::lowerFPTRUNC_F64_TO_F16(), llvm::LegalizerHelper::lowerFunnelShift(), llvm::LegalizerHelper::lowerFunnelShiftAsShifts(), llvm::LegalizerHelper::lowerFunnelShiftWithInverse(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::LegalizerHelper::lowerInsert(), llvm::LegalizerHelper::lowerIntrinsicRound(), llvm::LegalizerHelper::lowerLoad(), llvm::LegalizerHelper::lowerMergeValues(), llvm::LegalizerHelper::lowerMinMax(), llvm::LegalizerHelper::lowerReadWriteRegister(), llvm::AArch64CallLowering::lowerReturn(), llvm::LegalizerHelper::lowerRotate(), llvm::LegalizerHelper::lowerRotateWithReverseRotate(), llvm::LegalizerHelper::lowerSADDO_SSUBO(), llvm::LegalizerHelper::lowerSelect(), llvm::LegalizerHelper::lowerShlSat(), llvm::LegalizerHelper::lowerShuffleVector(), llvm::LegalizerHelper::lowerSITOFP(), llvm::LegalizerHelper::lowerSMULH_UMULH(), llvm::LegalizerHelper::lowerStore(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), llvm::LegalizerHelper::lowerUITOFP(), llvm::LegalizerHelper::lowerUnmergeValues(), lowerVectorFCMP(), matchAArch64MulConstCombine(), llvm::CombinerHelper::matchAshrShlToSextInreg(), llvm::CombinerHelper::matchBitfieldExtractFromAnd(), llvm::CombinerHelper::matchBitfieldExtractFromSExtInReg(), AMDGPUPreLegalizerCombinerHelper::matchClampI64ToI16(), llvm::CombinerHelper::matchCombineAddP2IToPtrAdd(), llvm::CombinerHelper::matchCombineAnyExtTrunc(), llvm::CombinerHelper::matchCombineConcatVectors(), llvm::CombinerHelper::matchCombineConstantFoldFpUnary(), llvm::CombinerHelper::matchCombineDivRem(), llvm::CombinerHelper::matchCombineExtendingLoads(), llvm::CombinerHelper::matchCombineI2PToP2I(), llvm::CombinerHelper::matchCombineInsertVecElts(), llvm::CombinerHelper::matchCombineShiftToUnmerge(), llvm::CombinerHelper::matchCombineShlOfExtend(), llvm::CombinerHelper::matchCombineShuffleVector(), llvm::CombinerHelper::matchCombineTruncOfShl(), llvm::CombinerHelper::matchCombineUnmergeConstant(), llvm::CombinerHelper::matchCombineUnmergeMergeToPlainValues(), llvm::CombinerHelper::matchCombineUnmergeZExtToZExt(), llvm::CombinerHelper::matchCombineZextTrunc(), matchDupLane(), matchEXT(), llvm::CombinerHelper::matchExtendThroughPhis(), llvm::CombinerHelper::matchExtractAllEltsFromBuildVector(), llvm::CombinerHelper::matchExtractVecEltBuildVec(), matchExtractVecEltPairwiseAdd(), matchFConstantToConstant(), AMDGPUPostLegalizerCombinerHelper::matchFMinFMaxLegacy(), matchFoldMergeToZext(), matchFormTruncstore(), llvm::CombinerHelper::matchFunnelShiftToRotate(), llvm::CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(), matchICmpRedundantTrunc(), llvm::CombinerHelper::matchICmpToTrueFalseKnownBits(), matchINS(), AMDGPURegBankCombinerHelper::matchIntMinMaxToMed3(), llvm::CombinerHelper::matchLoadOrCombine(), llvm::CombinerHelper::matchNotCmp(), llvm::CombinerHelper::matchOverlappingAnd(), llvm::CombinerHelper::matchPtrAddZero(), llvm::CombinerHelper::matchReassocPtrAdd(), llvm::CombinerHelper::matchRedundantAnd(), llvm::CombinerHelper::matchRedundantOr(), llvm::CombinerHelper::matchRedundantSExtInReg(), matchREV(), llvm::CombinerHelper::matchRotateOutOfRange(), llvm::CombinerHelper::matchSextInRegOfLoad(), llvm::CombinerHelper::matchSextTruncSextLoad(), llvm::CombinerHelper::matchShiftImmedChain(), llvm::CombinerHelper::matchShiftOfShiftedLogic(), matchTRN(), AMDGPUPostLegalizerCombinerHelper::matchUCharToFloat(), matchUZP(), matchVAshrLshrImm(), matchZeroExtendFromS32(), matchZip(), mergeVectorRegsToResultRegs(), llvm::LegalizerHelper::moreElementsVector(), llvm::LegalizerHelper::moreElementsVectorShuffle(), llvm::LegalizerHelper::moreElementsVectorSrc(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarAddSub(), llvm::LegalizerHelper::narrowScalarBasic(), llvm::LegalizerHelper::narrowScalarCTLZ(), llvm::LegalizerHelper::narrowScalarCTPOP(), llvm::LegalizerHelper::narrowScalarCTTZ(), llvm::LegalizerHelper::narrowScalarExt(), llvm::LegalizerHelper::narrowScalarExtract(), llvm::LegalizerHelper::narrowScalarFPTOI(), llvm::LegalizerHelper::narrowScalarInsert(), llvm::LegalizerHelper::narrowScalarMul(), llvm::LegalizerHelper::narrowScalarSelect(), llvm::LegalizerHelper::narrowScalarShift(), llvm::LegalizerHelper::reduceLoadStoreWidth(), llvm::LegalizerHelper::reduceOperationWidth(), llvm::InstructionSelect::runOnMachineFunction(), selectMergeValues(), llvm::AMDGPURegisterBankInfo::selectStoreIntrinsic(), selectUnmergeValues(), llvm::MipsRegisterBankInfo::setRegBank(), setRegsToType(), llvm::GISelKnownBits::signBitIsZero(), llvm::AMDGPULegalizerInfo::splitBufferOffsets(), tryAdjustICmpImmAndPred(), unsupportedBinOp(), llvm::LegalizerHelper::widenScalar(), llvm::LegalizerHelper::widenWithUnmerge(), and X86SelectAddress().

◆ getUniqueVRegDef()

MachineInstr * MachineRegisterInfo::getUniqueVRegDef ( Register  Reg) const

getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or null if none is found.

If there are multiple definitions or no definition, return null.

Definition at line 411 of file MachineRegisterInfo.cpp.

References def_empty(), def_instr_begin(), def_instr_end(), I, and Reg.

Referenced by llvm::PPCInstrInfo::analyzeLoopForPipelining(), llvm::CombinerHelper::applyCombineIndexedLoadStore(), canCombine(), CombineCVTAToLocal(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), findSingleRegDef(), llvm::SIInstrInfo::FoldImmediate(), foldImmediates(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), genFusedMultiply(), genMaddR(), llvm::PeelingModuloScheduleExpander::getEquivalentRegisterIn(), llvm::PPCInstrInfo::getFMAPatterns(), getFoldableImm(), getVRegDef(), getWinAllocaAmount(), llvm::X86InstrInfo::hasCommutePreference(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableSibling(), hasSameValue(), isCVTAToLocalCombinationCandidate(), isImplicitlyDef(), isVCmpResult(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::CombinerHelper::matchPtrAddImmedChain(), llvm::CombinerHelper::matchShiftImmedChain(), llvm::CombinerHelper::matchShiftOfShiftedLogic(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), llvm::PeelingModuloScheduleExpander::moveStageBetweenBlocks(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::PeelingModuloScheduleExpander::peelPrologAndEpilogs(), llvm::PeelingModuloScheduleExpander::rewriteUsesOf(), shouldPreventUndefRegUpdateMemFold(), llvm::TargetRegisterInfo::shouldRegionSplitForVirtReg(), and unstackifyVRegsUsedInSplitBB().

◆ getUsedPhysRegsMask()

const BitVector& llvm::MachineRegisterInfo::getUsedPhysRegsMask ( ) const
inline

Definition at line 870 of file MachineRegisterInfo.h.

◆ getVRegDef()

MachineInstr * MachineRegisterInfo::getVRegDef ( Register  Reg) const

getVRegDef - Return the machine instr that defines the specified virtual register or null if none is found.

This assumes that the code is in SSA form, so there should only be one definition.

Definition at line 400 of file MachineRegisterInfo.cpp.

References assert(), def_instr_begin(), def_instr_end(), I, and Reg.

Referenced by llvm::CombinerHelper::applyCombineTruncOfShl(), llvm::CombinerHelper::applyCombineUnmergeZExtToZExt(), llvm::CombinerHelper::applyExtendThroughPhis(), llvm::CombinerHelper::applyNotCmp(), llvm::CombinerHelper::applySextInRegOfLoad(), canCompareBeNewValueJump(), canFoldIntoCSel(), canFoldIntoSelect(), llvm::PPCInstrInfo::combineRLWINM(), llvm::SITargetLowering::computeKnownAlignForTargetInstr(), llvm::GISelKnownBits::computeKnownAlignment(), llvm::SITargetLowering::computeKnownBitsForTargetInstr(), llvm::GISelKnownBits::computeKnownBitsImpl(), llvm::GISelKnownBits::computeNumSignBits(), llvm::AMDGPUTargetLowering::computeNumSignBitsForTargetInstr(), llvm::constrainOperandRegClass(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitPartwordAtomicBinary(), llvm::PPCInstrInfo::finalizeInsInstrs(), findLoopComponents(), findStartOfTree(), llvm::PPCInstrInfo::fixupIsDeadOrKill(), fixupPHIOpBanks(), llvm::getConstantFPVRegVal(), llvm::getConstantIntVRegVal(), llvm::getConstantVRegValWithLookThrough(), llvm::getDefSrcRegIgnoringCopies(), llvm::PPCInstrInfo::getFMAPatterns(), llvm::getFunctionLiveInPhysReg(), getImmOrMaterializedImm(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::PeelingModuloScheduleExpander::getPhiCanonicalReg(), getRegSeqInit(), getVectorShiftImm(), llvm::getVRegSubRegDef(), llvm::LiveVariables::HandleVirtRegUse(), INITIALIZE_PASS(), llvm::InstructionSelector::isBaseWithConstantOffset(), llvm::SITargetLowering::isCanonicalized(), llvm::isKnownNeverNaN(), llvm::LiveVariables::VarInfo::isLiveIn(), llvm::SMSchedule::isLoopCarried(), llvm::SMSchedule::isLoopCarriedDefOfUse(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), llvm::MachineLoop::isLoopInvariant(), isSignExtended(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isVShiftRImm(), isZeroExtended(), llvm::SIInstrInfo::legalizeGenericOperand(), LookThroughCOPY(), llvm::TargetRegisterInfo::lookThruCopyLike(), llvm::TargetRegisterInfo::lookThruSingleUseCopyChain(), lowerVectorFCMP(), llvm::CombinerHelper::matchCombineConcatVectors(), llvm::CombinerHelper::matchCombineExtOfExt(), llvm::CombinerHelper::matchCombineTruncOfExt(), llvm::CombinerHelper::matchCombineUnmergeConstant(), matchExtractVecEltPairwiseAdd(), MatchingStackOffset(), llvm::CombinerHelper::matchNotCmp(), llvm::CombinerHelper::matchPtrAddZero(), llvm::CombinerHelper::matchReassocPtrAdd(), llvm::PeelingModuloScheduleExpander::moveStageBetweenBlocks(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::X86InstrInfo::optimizeLoadInstr(), llvm::ARMBaseInstrInfo::produceSameValue(), removeCopies(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::stableHashValue(), llvm::TailDuplicator::tailDuplicateAndUpdate(), tryToFoldACImm(), updatePHIs(), and llvm::SSAUpdaterTraits< MachineSSAUpdater >::ValueIsPHI().

◆ getVRegName()

StringRef llvm::MachineRegisterInfo::getVRegName ( Register  Reg) const
inline

◆ hasOneDef()

bool llvm::MachineRegisterInfo::hasOneDef ( Register  RegNo) const
inline

◆ hasOneNonDBGUse()

bool MachineRegisterInfo::hasOneNonDBGUse ( Register  RegNo) const

hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.

Definition at line 419 of file MachineRegisterInfo.cpp.

References llvm::hasSingleElement(), and use_nodbg_operands().

Referenced by canCombine(), canFoldIntoSelect(), CombineCVTAToLocal(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::PPCTargetLowering::emitProbedAlloca(), findOnlyInterestingUse(), llvm::VEInstrInfo::FoldImmediate(), llvm::SystemZInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), getCmpOperandFoldingProfit(), llvm::PPCInstrInfo::getFMAPatterns(), getTestBitReg(), llvm::TargetInstrInfo::hasReassociableSibling(), llvm::AArch64InstrInfo::isExtendLikelyToBeFolded(), isOperandKill(), llvm::TargetRegisterInfo::lookThruSingleUseCopyChain(), matchAArch64MulConstCombine(), llvm::CombinerHelper::matchCombineTruncOfShl(), llvm::CombinerHelper::matchExtendThroughPhis(), llvm::CombinerHelper::matchExtractVecEltBuildVec(), AMDGPUPostLegalizerCombinerHelper::matchFMinFMaxLegacy(), llvm::CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(), matchLoadAndBytePosition(), llvm::CombinerHelper::matchNotCmp(), llvm::CombinerHelper::matchPtrAddImmedChain(), llvm::CombinerHelper::matchSextInRegOfLoad(), llvm::CombinerHelper::matchShiftOfShiftedLogic(), llvm::CombinerHelper::matchXorOfAndWithSameReg(), oneUseDominatesOtherUses(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::TailDuplicator::tailDuplicateAndUpdate(), and verifyCFIntrinsic().

◆ hasOneNonDBGUser()

bool MachineRegisterInfo::hasOneNonDBGUser ( Register  RegNo) const

hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified register.

Said instruction may have multiple uses.

Definition at line 423 of file MachineRegisterInfo.cpp.

References llvm::hasSingleElement(), and use_nodbg_instructions().

◆ hasOneUse()

bool llvm::MachineRegisterInfo::hasOneUse ( Register  RegNo) const
inline

◆ insertVRegByName()

void llvm::MachineRegisterInfo::insertVRegByName ( StringRef  Name,
Register  Reg 
)
inline

◆ invalidateLiveness()

void llvm::MachineRegisterInfo::invalidateLiveness ( )
inline

invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.

This should be called by late passes that invalidate the liveness information.

Definition at line 207 of file MachineRegisterInfo.h.

References llvm::MachineFunction::getProperties(), llvm::MachineFunctionProperties::reset(), and llvm::MachineFunctionProperties::TracksLiveness.

Referenced by llvm::BranchFolder::OptimizeFunction(), and llvm::MIRParserImpl::parseRegisterInfo().

◆ isAllocatable()

bool llvm::MachineRegisterInfo::isAllocatable ( MCRegister  PhysReg) const
inline

isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been reserved.

Allocatable registers may show up in the allocation order of some virtual register, so a register allocator needs to track its liveness and availability.

Definition at line 933 of file MachineRegisterInfo.h.

References getTargetRegisterInfo(), llvm::TargetRegisterInfo::isInAllocatableClass(), and isReserved().

Referenced by computeLiveOuts(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), llvm::SIRegisterInfo::findUnusedRegister(), llvm::PPCRegisterInfo::getCalleeSavedRegs(), and isConstantPhysReg().

◆ isConstantPhysReg()

bool MachineRegisterInfo::isConstantPhysReg ( MCRegister  PhysReg) const

◆ isLiveIn()

bool MachineRegisterInfo::isLiveIn ( Register  Reg) const

◆ isPhysRegModified()

bool MachineRegisterInfo::isPhysRegModified ( MCRegister  PhysReg,
bool  SkipNoReturnDef = false 
) const

Return true if the specified register is modified in this function.

This checks that no defining machine operands exist for the register or any of its aliases. Definitions found on functions marked noreturn are ignored, to consider them pass 'true' for optional parameter SkipNoReturnDef. The register is also considered modified when it is set in the UsedPhysRegMask.

Definition at line 570 of file MachineRegisterInfo.cpp.

References def_begin(), def_end(), getTargetRegisterInfo(), isNoReturnDef(), llvm::MCRegAliasIterator::isValid(), llvm::make_range(), llvm::BitVector::test(), and TRI.

Referenced by llvm::XCoreFrameLowering::determineCalleeSaves(), llvm::TargetFrameLowering::determineCalleeSaves(), and isSafeToMove().

◆ isPhysRegUsed()

bool MachineRegisterInfo::isPhysRegUsed ( MCRegister  PhysReg,
bool  SkipRegMaskTest = false 
) const

◆ isReserved()

bool llvm::MachineRegisterInfo::isReserved ( MCRegister  PhysReg) const
inline

◆ isReservedRegUnit()

bool MachineRegisterInfo::isReservedRegUnit ( unsigned  Unit) const

Returns true when the given register unit is considered reserved.

Register units are considered reserved when for at least one of their root registers, the root register and all super registers are reserved. This currently iterates the register hierarchy and may be slower than expected.

Definition at line 640 of file MachineRegisterInfo.cpp.

References getTargetRegisterInfo(), isReserved(), llvm::MCRegisterInfo::DiffListIterator::isValid(), llvm::MCRegUnitRootIterator::isValid(), Reg, and TRI.

Referenced by llvm::LiveIntervals::HMEditor::getRegUnitLI().

◆ isSSA()

bool llvm::MachineRegisterInfo::isSSA ( ) const
inline

◆ isUpdatedCSRsInitialized()

bool llvm::MachineRegisterInfo::isUpdatedCSRsInitialized ( ) const
inline

Returns true if the updated CSR list was initialized and false otherwise.

Definition at line 230 of file MachineRegisterInfo.h.

Referenced by llvm::MIRPrinter::convert().

◆ leaveSSA()

void llvm::MachineRegisterInfo::leaveSSA ( )
inline

◆ livein_begin()

livein_iterator llvm::MachineRegisterInfo::livein_begin ( ) const
inline

Definition at line 952 of file MachineRegisterInfo.h.

Referenced by llvm::MachineFunction::print().

◆ livein_empty()

bool llvm::MachineRegisterInfo::livein_empty ( ) const
inline

◆ livein_end()

livein_iterator llvm::MachineRegisterInfo::livein_end ( ) const
inline

Definition at line 953 of file MachineRegisterInfo.h.

Referenced by llvm::MachineFunction::print().

◆ liveins()

ArrayRef<std::pair<MCRegister, Register> > llvm::MachineRegisterInfo::liveins ( ) const
inline

◆ markUsesInDebugValueAsUndef()

void MachineRegisterInfo::markUsesInDebugValueAsUndef ( Register  Reg) const

markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined which causes the DBG_VALUE to be deleted during LiveDebugVariables analysis.

Definition at line 532 of file MachineRegisterInfo.cpp.

References llvm::make_early_inc_range(), Reg, use_instructions(), and UseMI.

Referenced by llvm::MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval().

◆ moveOperands()

void MachineRegisterInfo::moveOperands ( MachineOperand Dst,
MachineOperand Src,
unsigned  NumOps 
)

Move NumOps operands from Src to Dst, updating use-def lists as needed.

The Dst range is assumed to be uninitialized memory. (Or it may contain operands that won't be destroyed, which is OK because the MO destructor is trivial anyway).

The Src and Dst ranges may overlap.

Definition at line 333 of file MachineRegisterInfo.cpp.

References assert(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isReg().

Referenced by llvm::SIInstrInfo::moveFlatAddrToVGPR(), and moveOperands().

◆ operator=()

MachineRegisterInfo& llvm::MachineRegisterInfo::operator= ( const MachineRegisterInfo )
delete

◆ recomputeRegClass()

bool MachineRegisterInfo::recomputeRegClass ( Register  Reg)

recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the constraints from the instructions using Reg.

Returns true if Reg was upgraded.

This method can be used after constraints have been removed from a virtual register, for example after removing instructions or splitting the live range.

Definition at line 122 of file MachineRegisterInfo.cpp.

References llvm::TargetSubtargetInfo::getInstrInfo(), llvm::TargetRegisterInfo::getLargestLegalSuperClass(), getRegClass(), llvm::MachineFunction::getSubtarget(), getTargetRegisterInfo(), MI, Reg, reg_nodbg_operands(), setRegClass(), and TII.

Referenced by llvm::LiveRangeEdit::calculateRegClassAndHint().

◆ reg_begin()

reg_iterator llvm::MachineRegisterInfo::reg_begin ( Register  RegNo) const
inline

◆ reg_bundle_begin()

reg_bundle_iterator llvm::MachineRegisterInfo::reg_bundle_begin ( Register  RegNo) const
inline

Definition at line 310 of file MachineRegisterInfo.h.

Referenced by reg_bundles().

◆ reg_bundle_end()

static reg_bundle_iterator llvm::MachineRegisterInfo::reg_bundle_end ( )
inlinestatic

Definition at line 313 of file MachineRegisterInfo.h.

Referenced by reg_bundles().

◆ reg_bundle_nodbg_begin()

reg_bundle_nodbg_iterator llvm::MachineRegisterInfo::reg_bundle_nodbg_begin ( Register  RegNo) const
inline

Definition at line 363 of file MachineRegisterInfo.h.

Referenced by reg_nodbg_bundles().

◆ reg_bundle_nodbg_end()

static reg_bundle_nodbg_iterator llvm::MachineRegisterInfo::reg_bundle_nodbg_end ( )
inlinestatic

Definition at line 366 of file MachineRegisterInfo.h.

Referenced by reg_nodbg_bundles().

◆ reg_bundles()

iterator_range<reg_bundle_iterator> llvm::MachineRegisterInfo::reg_bundles ( Register  Reg) const
inline

Definition at line 317 of file MachineRegisterInfo.h.

References llvm::make_range(), Reg, reg_bundle_begin(), and reg_bundle_end().

◆ reg_empty()

bool llvm::MachineRegisterInfo::reg_empty ( Register  RegNo) const
inline

reg_empty - Return true if there are no instructions using or defining the specified register (it may be live-in).

Definition at line 323 of file MachineRegisterInfo.h.

References reg_begin(), and reg_end().

◆ reg_end()

static reg_iterator llvm::MachineRegisterInfo::reg_end ( )
inlinestatic

Definition at line 284 of file MachineRegisterInfo.h.

Referenced by reg_empty(), reg_operands(), and replaceRegWith().

◆ reg_instr_begin()

reg_instr_iterator llvm::MachineRegisterInfo::reg_instr_begin ( Register  RegNo) const
inline

◆ reg_instr_end()

static reg_instr_iterator llvm::MachineRegisterInfo::reg_instr_end ( )
inlinestatic

◆ reg_instr_nodbg_begin()

reg_instr_nodbg_iterator llvm::MachineRegisterInfo::reg_instr_nodbg_begin ( Register  RegNo) const
inline

Definition at line 346 of file MachineRegisterInfo.h.

Referenced by reg_nodbg_instructions().

◆ reg_instr_nodbg_end()

static reg_instr_nodbg_iterator llvm::MachineRegisterInfo::reg_instr_nodbg_end ( )
inlinestatic

Definition at line 349 of file MachineRegisterInfo.h.

Referenced by reg_nodbg_instructions().

◆ reg_instructions()

iterator_range<reg_instr_iterator> llvm::MachineRegisterInfo::reg_instructions ( Register  Reg) const
inline

◆ reg_nodbg_begin()

reg_nodbg_iterator llvm::MachineRegisterInfo::reg_nodbg_begin ( Register  RegNo) const
inline

Definition at line 329 of file MachineRegisterInfo.h.

Referenced by reg_nodbg_empty(), and reg_nodbg_operands().

◆ reg_nodbg_bundles()

iterator_range<reg_bundle_nodbg_iterator> llvm::MachineRegisterInfo::reg_nodbg_bundles ( Register  Reg) const
inline

◆ reg_nodbg_empty()

bool llvm::MachineRegisterInfo::reg_nodbg_empty ( Register  RegNo) const
inline

reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.

Definition at line 377 of file MachineRegisterInfo.h.

References reg_nodbg_begin(), and reg_nodbg_end().

Referenced by llvm::LiveIntervals::addKillFlags(), llvm::RegAllocBase::allocatePhysRegs(), llvm::VirtRegAuxInfo::calculateSpillWeightsAndHints(), llvm::X86FrameLowering::emitEpilogue(), and isPhysRegUsed().

◆ reg_nodbg_end()

static reg_nodbg_iterator llvm::MachineRegisterInfo::reg_nodbg_end ( )
inlinestatic

Definition at line 332 of file MachineRegisterInfo.h.

Referenced by reg_nodbg_empty(), and reg_nodbg_operands().

◆ reg_nodbg_instructions()

iterator_range<reg_instr_nodbg_iterator> llvm::MachineRegisterInfo::reg_nodbg_instructions ( Register  Reg) const
inline

◆ reg_nodbg_operands()

iterator_range<reg_nodbg_iterator> llvm::MachineRegisterInfo::reg_nodbg_operands ( Register  Reg) const
inline

◆ reg_operands()

iterator_range<reg_iterator> llvm::MachineRegisterInfo::reg_operands ( Register  Reg) const
inline

◆ removeRegOperandFromUseList()

void MachineRegisterInfo::removeRegOperandFromUseList ( MachineOperand MO)

◆ replaceRegWith()

void MachineRegisterInfo::replaceRegWith ( Register  FromReg,
Register  ToReg 
)

replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.

This is like llvm-level X->replaceAllUsesWith(Y), except that it also changes any definitions of the register as well.

Note that it is usually necessary to first constrain ToReg's register class and register bank to match the FromReg constraints using one of the methods:

constrainRegClass(ToReg, getRegClass(FromReg)) constrainRegAttrs(ToReg, FromReg) RegisterBankInfo::constrainGenericRegister(ToReg, *MRI.getRegClass(FromReg), MRI)

These functions will return a falsy result if the virtual registers have incompatible constraints.

Note that if ToReg is a physical register the function will replace and apply sub registers to ToReg in order to obtain a final/proper physical register.

This is like llvm-level X->replaceAllUsesWith(Y), except that it also changes any definitions of the register as well. If ToReg is a physical register we apply the sub register to obtain the final/proper physical register.

Definition at line 380 of file MachineRegisterInfo.cpp.

References assert(), E, getTargetRegisterInfo(), I, llvm::Register::isPhysicalRegister(), llvm::RISCVFenceField::O, reg_begin(), reg_end(), and TRI.

Referenced by llvm::SITargetLowering::finalizeLowering(), llvm::RISCVInstrInfo::insertIndirectBranch(), llvm::SIInstrInfo::insertIndirectBranch(), lowerVectorFCMP(), llvm::PeelingModuloScheduleExpander::moveStageBetweenBlocks(), llvm::SIInstrInfo::moveToVALU(), llvm::CombinerHelper::replaceRegWith(), llvm::PeelingModuloScheduleExpander::rewriteUsesOf(), llvm::InstructionSelect::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), scavengeVReg(), and llvm::TailDuplicator::tailDuplicateAndUpdate().

◆ reservedRegsFrozen()

bool llvm::MachineRegisterInfo::reservedRegsFrozen ( ) const
inline

reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved registers stays constant.

Definition at line 890 of file MachineRegisterInfo.h.

Referenced by adjustAllocatableRegClass(), canReserveReg(), getReservedRegs(), isCallerPreservedOrConstPhysReg(), and llvm::SIInstrInfo::isOperandLegal().

◆ resetDelegate()

void llvm::MachineRegisterInfo::resetDelegate ( Delegate delegate)
inline

Definition at line 157 of file MachineRegisterInfo.h.

References assert().

◆ setCalleeSavedRegs()

void MachineRegisterInfo::setCalleeSavedRegs ( ArrayRef< MCPhysReg CSRs)

Sets the updated Callee Saved Registers list.

Notice that it will override ant previously disabled/saved CSRs.

Definition at line 628 of file MachineRegisterInfo.cpp.

References llvm::append_range().

Referenced by llvm::MIRParserImpl::parseRegisterInfo(), and llvm::AArch64RegisterInfo::UpdateCustomCalleeSavedRegs().

◆ setDelegate()

void llvm::MachineRegisterInfo::setDelegate ( Delegate delegate)
inline

Definition at line 166 of file MachineRegisterInfo.h.

References assert().

◆ setRegAllocationHint()

void llvm::MachineRegisterInfo::setRegAllocationHint ( Register  VReg,
unsigned  Type,
Register  PrefReg 
)
inline

setRegAllocationHint - Specify a register allocation hint for the specified virtual register.

This is typically used by target, and in case of an earlier hint it will be overwritten.

Definition at line 765 of file MachineRegisterInfo.h.

References assert(), llvm::IndexedMap< T, ToIndexT >::clear(), llvm::Register::isVirtual(), and Type.

Referenced by llvm::SIInstrInfo::getAddNoCarry(), setSimpleHint(), shrinkScalarLogicOp(), and llvm::ARMBaseRegisterInfo::updateRegAllocHint().

◆ setRegBank()

void MachineRegisterInfo::setRegBank ( Register  Reg,
const RegisterBank RegBank 
)

◆ setRegClass()

void MachineRegisterInfo::setRegClass ( Register  Reg,
const TargetRegisterClass RC 
)

◆ setRegClassOrRegBank()

void llvm::MachineRegisterInfo::setRegClassOrRegBank ( Register  Reg,
const RegClassOrRegBank RCOrRB 
)
inline

Definition at line 678 of file MachineRegisterInfo.h.

References Reg.

Referenced by constrainRegAttrs().

◆ setSimpleHint()

void llvm::MachineRegisterInfo::setSimpleHint ( Register  VReg,
Register  PrefReg 
)
inline

Specify the preferred (target independent) register allocation hint for the specified virtual register.

Definition at line 781 of file MachineRegisterInfo.h.

References setRegAllocationHint().

Referenced by emitLoadM0FromVGPRLoop(), emitLoadSRsrcFromVGPRLoop(), llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), and llvm::MIRParserImpl::setupRegisterInfo().

◆ setType()

void MachineRegisterInfo::setType ( Register  VReg,
LLT  Ty 
)

◆ shouldTrackSubRegLiveness() [1/2]

bool llvm::MachineRegisterInfo::shouldTrackSubRegLiveness ( const TargetRegisterClass RC) const
inline

Returns true if liveness for register class RC should be tracked at the subregister level.

Definition at line 214 of file MachineRegisterInfo.h.

References llvm::TargetRegisterClass::HasDisjunctSubRegs, and subRegLivenessEnabled().

Referenced by shouldTrackSubRegLiveness().

◆ shouldTrackSubRegLiveness() [2/2]

bool llvm::MachineRegisterInfo::shouldTrackSubRegLiveness ( Register  VReg) const
inline

◆ subRegLivenessEnabled()

bool llvm::MachineRegisterInfo::subRegLivenessEnabled ( ) const
inline

◆ tracksLiveness()

bool llvm::MachineRegisterInfo::tracksLiveness ( ) const
inline

◆ updateDbgUsersToReg()

void llvm::MachineRegisterInfo::updateDbgUsersToReg ( MCRegister  OldReg,
MCRegister  NewReg,
ArrayRef< MachineInstr * >  Users 
) const
inline

updateDbgUsersToReg - Update a collection of DBG_VALUE instructions to refer to the designated register.

Definition at line 826 of file MachineRegisterInfo.h.

References assert(), llvm::SmallSet< T, N, C >::contains(), getTargetRegisterInfo(), llvm::SmallSet< T, N, C >::insert(), llvm::MCRegisterInfo::DiffListIterator::isValid(), MI, and Users.

◆ use_begin()

use_iterator llvm::MachineRegisterInfo::use_begin ( Register  RegNo) const
inline

◆ use_bundle_begin()

use_bundle_iterator llvm::MachineRegisterInfo::use_bundle_begin ( Register  RegNo) const
inline

Definition at line 493 of file MachineRegisterInfo.h.

Referenced by use_bundles().

◆ use_bundle_end()

static use_bundle_iterator llvm::MachineRegisterInfo::use_bundle_end ( )
inlinestatic

Definition at line 496 of file MachineRegisterInfo.h.

Referenced by use_bundles().

◆ use_bundle_nodbg_begin()

use_bundle_nodbg_iterator llvm::MachineRegisterInfo::use_bundle_nodbg_begin ( Register  RegNo) const
inline

Definition at line 552 of file MachineRegisterInfo.h.

Referenced by use_nodbg_bundles().

◆ use_bundle_nodbg_end()

static use_bundle_nodbg_iterator llvm::MachineRegisterInfo::use_bundle_nodbg_end ( )
inlinestatic

Definition at line 555 of file MachineRegisterInfo.h.

Referenced by use_nodbg_bundles().

◆ use_bundles()

iterator_range<use_bundle_iterator> llvm::MachineRegisterInfo::use_bundles ( Register  Reg) const
inline

Definition at line 500 of file MachineRegisterInfo.h.

References llvm::make_range(), Reg, use_bundle_begin(), and use_bundle_end().

◆ use_empty()

bool llvm::MachineRegisterInfo::use_empty ( Register  RegNo) const
inline

◆ use_end()

static use_iterator llvm::MachineRegisterInfo::use_end ( )
inlinestatic

◆ use_instr_begin()

use_instr_iterator llvm::MachineRegisterInfo::use_instr_begin ( Register  RegNo) const
inline

◆ use_instr_end()

static use_instr_iterator llvm::MachineRegisterInfo::use_instr_end ( )
inlinestatic

◆ use_instr_nodbg_begin()

use_instr_nodbg_iterator llvm::MachineRegisterInfo::use_instr_nodbg_begin ( Register  RegNo) const
inline

◆ use_instr_nodbg_end()

static use_instr_nodbg_iterator llvm::MachineRegisterInfo::use_instr_nodbg_end ( )
inlinestatic

◆ use_instructions()

iterator_range<use_instr_iterator> llvm::MachineRegisterInfo::use_instructions ( Register  Reg) const
inline

◆ use_nodbg_begin()

use_nodbg_iterator llvm::MachineRegisterInfo::use_nodbg_begin ( Register  RegNo) const
inline

◆ use_nodbg_bundles()

iterator_range<use_bundle_nodbg_iterator> llvm::MachineRegisterInfo::use_nodbg_bundles ( Register  Reg) const
inline

◆ use_nodbg_empty()

bool llvm::MachineRegisterInfo::use_nodbg_empty ( Register  RegNo) const
inline

◆ use_nodbg_end()

static use_nodbg_iterator llvm::MachineRegisterInfo::use_nodbg_end ( )
inlinestatic

◆ use_nodbg_instructions()

iterator_range<use_instr_nodbg_iterator> llvm::MachineRegisterInfo::use_nodbg_instructions ( Register  Reg) const
inline

◆ use_nodbg_operands()

iterator_range<use_nodbg_iterator> llvm::MachineRegisterInfo::use_nodbg_operands ( Register  Reg) const
inline

◆ use_operands()

iterator_range<use_iterator> llvm::MachineRegisterInfo::use_operands ( Register  Reg) const
inline

◆ verifyUseList()

void MachineRegisterInfo::verifyUseList ( Register  Reg) const

◆ verifyUseLists()

void MachineRegisterInfo::verifyUseLists ( ) const

Verify the use list of all registers.

Definition at line 255 of file MachineRegisterInfo.cpp.

References llvm::numbers::e, getNumVirtRegs(), getTargetRegisterInfo(), i, llvm::Register::index2VirtReg(), and verifyUseList().

Friends And Related Function Documentation

◆ defusechain_instr_iterator

template<bool , bool , bool , bool , bool , bool >
friend class defusechain_instr_iterator
friend

Definition at line 275 of file MachineRegisterInfo.h.

◆ defusechain_iterator

template<bool , bool , bool , bool , bool , bool >
friend class defusechain_iterator
friend

Definition at line 269 of file MachineRegisterInfo.h.


The documentation for this class was generated from the following files: