26#define DEBUG_TYPE "nvptx-reg-info"
30 if (RC == &NVPTX::Float32RegsRegClass)
32 if (RC == &NVPTX::Float64RegsRegClass)
34 if (RC == &NVPTX::Int128RegsRegClass)
36 if (RC == &NVPTX::Int64RegsRegClass)
56 if (RC == &NVPTX::Int32RegsRegClass)
58 if (RC == &NVPTX::Int16RegsRegClass)
60 if (RC == &NVPTX::Int1RegsRegClass)
62 if (RC == &NVPTX::SpecialRegsRegClass)
68 if (RC == &NVPTX::Float32RegsRegClass)
70 if (RC == &NVPTX::Float64RegsRegClass)
72 if (RC == &NVPTX::Int128RegsRegClass)
74 if (RC == &NVPTX::Int64RegsRegClass)
76 if (RC == &NVPTX::Int32RegsRegClass)
78 if (RC == &NVPTX::Int16RegsRegClass)
80 if (RC == &NVPTX::Int1RegsRegClass)
82 if (RC == &NVPTX::SpecialRegsRegClass)
91#define GET_REGINFO_TARGET_DESC
92#include "NVPTXGenRegisterInfo.inc"
97 static const MCPhysReg CalleeSavedRegs[] = { 0 };
98 return CalleeSavedRegs;
103 for (
unsigned Reg = NVPTX::ENVREG0; Reg <= NVPTX::ENVREG31; ++Reg) {
106 markSuperRegs(
Reserved, NVPTX::VRFrame32);
107 markSuperRegs(
Reserved, NVPTX::VRFrameLocal32);
108 markSuperRegs(
Reserved, NVPTX::VRFrame64);
109 markSuperRegs(
Reserved, NVPTX::VRFrameLocal64);
110 markSuperRegs(
Reserved, NVPTX::VRDepot);
115 int SPAdj,
unsigned FIOperandNum,
117 assert(SPAdj == 0 &&
"Unexpected");
120 int FrameIndex =
MI.getOperand(FIOperandNum).getIndex();
124 MI.getOperand(FIOperandNum + 1).getImm();
128 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(
Offset);
135 return TM.is64Bit() ? NVPTX::VRFrame64 : NVPTX::VRFrame32;
142 return TM.is64Bit() ? NVPTX::VRFrameLocal64 : NVPTX::VRFrameLocal32;
This file implements the BitVector class.
uint64_t IntrinsicInst * II
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Representation of each machine instruction.
Register getFrameLocalRegister(const MachineFunction &MF) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
NVPTX Callee Saved Registers.
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
Register getFrameRegister(const MachineFunction &MF) const override
Wrapper class representing virtual and physical registers.
This is an optimization pass for GlobalISel generic memory operations.
std::string getNVPTXRegClassName(TargetRegisterClass const *RC)
std::string getNVPTXRegClassStr(TargetRegisterClass const *RC)