LLVM 22.0.0git
Classes | Namespaces | Macros | Enumerations | Functions
RISCVBaseInfo.h File Reference
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/TargetParser/RISCVISAInfo.h"
#include "llvm/TargetParser/RISCVTargetParser.h"
#include "llvm/TargetParser/SubtargetFeature.h"
#include "RISCVGenSearchableTables.inc"

Go to the source code of this file.

Classes

struct  llvm::RISCVSysReg::SysReg
struct  llvm::RISCVInsnOpcode::RISCVOpcode
struct  llvm::RISCVVInversePseudosTable::PseudoInfo
struct  llvm::RISCV::VLSEGPseudo
struct  llvm::RISCV::VLXSEGPseudo
struct  llvm::RISCV::VSSEGPseudo
struct  llvm::RISCV::VSXSEGPseudo
struct  llvm::RISCV::VLEPseudo
struct  llvm::RISCV::VSEPseudo
struct  llvm::RISCV::VLX_VSXPseudo
struct  llvm::RISCV::NDSVLNPseudo

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
namespace  llvm::RISCVII
namespace  llvm::RISCVOp
namespace  llvm::RISCVFenceField
namespace  llvm::RISCVFPRndMode
namespace  llvm::RISCVVXRndMode
namespace  llvm::RISCVExceptFlags
namespace  llvm::RISCVLoadFPImm
namespace  llvm::RISCVSysReg
namespace  llvm::RISCVInsnOpcode
namespace  llvm::RISCVABI
namespace  llvm::RISCVFeatures
namespace  llvm::RISCVRVC
namespace  llvm::RISCVZC
namespace  llvm::RISCVVInversePseudosTable
namespace  llvm::RISCV

Macros

#define GET_SysRegEncodings_DECL
#define GET_SysRegsList_DECL
#define GET_RISCVOpcodesList_DECL
#define GET_RISCVVInversePseudosTable_DECL
#define GET_RISCVVSSEGTable_DECL
#define GET_RISCVVLSEGTable_DECL
#define GET_RISCVVLXSEGTable_DECL
#define GET_RISCVVSXSEGTable_DECL
#define GET_RISCVVLETable_DECL
#define GET_RISCVVSETable_DECL
#define GET_RISCVVLXTable_DECL
#define GET_RISCVVSXTable_DECL
#define GET_RISCVNDSVLNTable_DECL

Enumerations

enum  {
  llvm::RISCVII::InstFormatPseudo = 0 , llvm::RISCVII::InstFormatR = 1 , llvm::RISCVII::InstFormatR4 = 2 , llvm::RISCVII::InstFormatI = 3 ,
  llvm::RISCVII::InstFormatS = 4 , llvm::RISCVII::InstFormatB = 5 , llvm::RISCVII::InstFormatU = 6 , llvm::RISCVII::InstFormatJ = 7 ,
  llvm::RISCVII::InstFormatCR = 8 , llvm::RISCVII::InstFormatCI = 9 , llvm::RISCVII::InstFormatCSS = 10 , llvm::RISCVII::InstFormatCIW = 11 ,
  llvm::RISCVII::InstFormatCL = 12 , llvm::RISCVII::InstFormatCS = 13 , llvm::RISCVII::InstFormatCA = 14 , llvm::RISCVII::InstFormatCB = 15 ,
  llvm::RISCVII::InstFormatCJ = 16 , llvm::RISCVII::InstFormatCU = 17 , llvm::RISCVII::InstFormatCLB = 18 , llvm::RISCVII::InstFormatCLH = 19 ,
  llvm::RISCVII::InstFormatCSB = 20 , llvm::RISCVII::InstFormatCSH = 21 , llvm::RISCVII::InstFormatQC_EAI = 22 , llvm::RISCVII::InstFormatQC_EI = 23 ,
  llvm::RISCVII::InstFormatQC_EB = 24 , llvm::RISCVII::InstFormatQC_EJ = 25 , llvm::RISCVII::InstFormatQC_ES = 26 , llvm::RISCVII::InstFormatNDS_BRANCH_10 = 27 ,
  llvm::RISCVII::InstFormatOther = 31 , llvm::RISCVII::InstFormatMask = 31 , llvm::RISCVII::InstFormatShift = 0 , llvm::RISCVII::ConstraintShift = InstFormatShift + 5 ,
  llvm::RISCVII::VS2Constraint = 0b001 << ConstraintShift , llvm::RISCVII::VS1Constraint = 0b010 << ConstraintShift , llvm::RISCVII::VMConstraint = 0b100 << ConstraintShift , llvm::RISCVII::ConstraintMask = 0b111 << ConstraintShift ,
  llvm::RISCVII::VLMulShift = ConstraintShift + 3 , llvm::RISCVII::VLMulMask = 0b111 << VLMulShift , llvm::RISCVII::IsTiedPseudoShift = VLMulShift + 3 , llvm::RISCVII::IsTiedPseudoMask = 1 << IsTiedPseudoShift ,
  llvm::RISCVII::HasSEWOpShift = IsTiedPseudoShift + 1 , llvm::RISCVII::HasSEWOpMask = 1 << HasSEWOpShift , llvm::RISCVII::HasVLOpShift = HasSEWOpShift + 1 , llvm::RISCVII::HasVLOpMask = 1 << HasVLOpShift ,
  llvm::RISCVII::HasVecPolicyOpShift = HasVLOpShift + 1 , llvm::RISCVII::HasVecPolicyOpMask = 1 << HasVecPolicyOpShift , llvm::RISCVII::IsRVVWideningReductionShift = HasVecPolicyOpShift + 1 , llvm::RISCVII::IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift ,
  llvm::RISCVII::UsesMaskPolicyShift = IsRVVWideningReductionShift + 1 , llvm::RISCVII::UsesMaskPolicyMask = 1 << UsesMaskPolicyShift , llvm::RISCVII::IsSignExtendingOpWShift = UsesMaskPolicyShift + 1 , llvm::RISCVII::IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift ,
  llvm::RISCVII::HasRoundModeOpShift = IsSignExtendingOpWShift + 1 , llvm::RISCVII::HasRoundModeOpMask = 1 << HasRoundModeOpShift , llvm::RISCVII::UsesVXRMShift = HasRoundModeOpShift + 1 , llvm::RISCVII::UsesVXRMMask = 1 << UsesVXRMShift ,
  llvm::RISCVII::TargetOverlapConstraintTypeShift = UsesVXRMShift + 1 , llvm::RISCVII::TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift , llvm::RISCVII::ElementsDependOnVLShift = TargetOverlapConstraintTypeShift + 2 , llvm::RISCVII::ElementsDependOnVLMask = 1ULL << ElementsDependOnVLShift ,
  llvm::RISCVII::ElementsDependOnMaskShift = ElementsDependOnVLShift + 1 , llvm::RISCVII::ElementsDependOnMaskMask = 1ULL << ElementsDependOnMaskShift , llvm::RISCVII::DestEEWShift = ElementsDependOnMaskShift + 1 , llvm::RISCVII::DestEEWMask = 3ULL << DestEEWShift ,
  llvm::RISCVII::ReadsPastVLShift = DestEEWShift + 2 , llvm::RISCVII::ReadsPastVLMask = 1ULL << ReadsPastVLShift
}
enum  {
  llvm::RISCVII::MO_None = 0 , llvm::RISCVII::MO_CALL = 1 , llvm::RISCVII::MO_LO = 3 , llvm::RISCVII::MO_HI = 4 ,
  llvm::RISCVII::MO_PCREL_LO = 5 , llvm::RISCVII::MO_PCREL_HI = 6 , llvm::RISCVII::MO_GOT_HI = 7 , llvm::RISCVII::MO_TPREL_LO = 8 ,
  llvm::RISCVII::MO_TPREL_HI = 9 , llvm::RISCVII::MO_TPREL_ADD = 10 , llvm::RISCVII::MO_TLS_GOT_HI = 11 , llvm::RISCVII::MO_TLS_GD_HI = 12 ,
  llvm::RISCVII::MO_TLSDESC_HI = 13 , llvm::RISCVII::MO_TLSDESC_LOAD_LO = 14 , llvm::RISCVII::MO_TLSDESC_ADD_LO = 15 , llvm::RISCVII::MO_TLSDESC_CALL = 16 ,
  llvm::RISCVII::MO_DIRECT_FLAG_MASK = 31
}
enum  llvm::RISCVOp::OperandType : unsigned {
  llvm::RISCVOp::OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET , llvm::RISCVOp::OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM , llvm::RISCVOp::OPERAND_UIMM2 , llvm::RISCVOp::OPERAND_UIMM2_LSB0 ,
  llvm::RISCVOp::OPERAND_UIMM3 , llvm::RISCVOp::OPERAND_UIMM4 , llvm::RISCVOp::OPERAND_UIMM5 , llvm::RISCVOp::OPERAND_UIMM5_NONZERO ,
  llvm::RISCVOp::OPERAND_UIMM5_GT3 , llvm::RISCVOp::OPERAND_UIMM5_PLUS1 , llvm::RISCVOp::OPERAND_UIMM5_GE6_PLUS1 , llvm::RISCVOp::OPERAND_UIMM5_LSB0 ,
  llvm::RISCVOp::OPERAND_UIMM5_SLIST , llvm::RISCVOp::OPERAND_UIMM6 , llvm::RISCVOp::OPERAND_UIMM6_LSB0 , llvm::RISCVOp::OPERAND_UIMM7 ,
  llvm::RISCVOp::OPERAND_UIMM7_LSB00 , llvm::RISCVOp::OPERAND_UIMM7_LSB000 , llvm::RISCVOp::OPERAND_UIMM8_LSB00 , llvm::RISCVOp::OPERAND_UIMM8 ,
  llvm::RISCVOp::OPERAND_UIMM8_LSB000 , llvm::RISCVOp::OPERAND_UIMM8_GE32 , llvm::RISCVOp::OPERAND_UIMM9_LSB000 , llvm::RISCVOp::OPERAND_UIMM9 ,
  llvm::RISCVOp::OPERAND_UIMM10 , llvm::RISCVOp::OPERAND_UIMM10_LSB00_NONZERO , llvm::RISCVOp::OPERAND_UIMM11 , llvm::RISCVOp::OPERAND_UIMM12 ,
  llvm::RISCVOp::OPERAND_UIMM14_LSB00 , llvm::RISCVOp::OPERAND_UIMM16 , llvm::RISCVOp::OPERAND_UIMM16_NONZERO , llvm::RISCVOp::OPERAND_UIMM20 ,
  llvm::RISCVOp::OPERAND_UIMMLOG2XLEN , llvm::RISCVOp::OPERAND_UIMMLOG2XLEN_NONZERO , llvm::RISCVOp::OPERAND_UIMM32 , llvm::RISCVOp::OPERAND_UIMM48 ,
  llvm::RISCVOp::OPERAND_UIMM64 , llvm::RISCVOp::OPERAND_THREE , llvm::RISCVOp::OPERAND_FOUR , llvm::RISCVOp::OPERAND_IMM5_ZIBI ,
  llvm::RISCVOp::OPERAND_SIMM5 , llvm::RISCVOp::OPERAND_SIMM5_NONZERO , llvm::RISCVOp::OPERAND_SIMM5_PLUS1 , llvm::RISCVOp::OPERAND_SIMM6 ,
  llvm::RISCVOp::OPERAND_SIMM6_NONZERO , llvm::RISCVOp::OPERAND_SIMM8 , llvm::RISCVOp::OPERAND_SIMM8_UNSIGNED , llvm::RISCVOp::OPERAND_SIMM10 ,
  llvm::RISCVOp::OPERAND_SIMM10_LSB0000_NONZERO , llvm::RISCVOp::OPERAND_SIMM10_UNSIGNED , llvm::RISCVOp::OPERAND_SIMM11 , llvm::RISCVOp::OPERAND_SIMM12 ,
  llvm::RISCVOp::OPERAND_SIMM12_LSB00000 , llvm::RISCVOp::OPERAND_SIMM16 , llvm::RISCVOp::OPERAND_SIMM16_NONZERO , llvm::RISCVOp::OPERAND_SIMM20_LI ,
  llvm::RISCVOp::OPERAND_SIMM26 , llvm::RISCVOp::OPERAND_BARE_SIMM32 , llvm::RISCVOp::OPERAND_CLUI_IMM , llvm::RISCVOp::OPERAND_VTYPEI10 ,
  llvm::RISCVOp::OPERAND_VTYPEI11 , llvm::RISCVOp::OPERAND_RVKRNUM , llvm::RISCVOp::OPERAND_RVKRNUM_0_7 , llvm::RISCVOp::OPERAND_RVKRNUM_1_10 ,
  llvm::RISCVOp::OPERAND_RVKRNUM_2_14 , llvm::RISCVOp::OPERAND_RLIST , llvm::RISCVOp::OPERAND_RLIST_S0 , llvm::RISCVOp::OPERAND_STACKADJ ,
  llvm::RISCVOp::OPERAND_FRMARG , llvm::RISCVOp::OPERAND_RTZARG , llvm::RISCVOp::OPERAND_COND_CODE , llvm::RISCVOp::OPERAND_VEC_POLICY ,
  llvm::RISCVOp::OPERAND_SEW , llvm::RISCVOp::OPERAND_SEW_MASK , llvm::RISCVOp::OPERAND_VEC_RM , llvm::RISCVOp::OPERAND_LAST_RISCV_IMM = OPERAND_VEC_RM ,
  llvm::RISCVOp::OPERAND_AVL
}
enum  llvm::RISCVFenceField::FenceField { llvm::RISCVFenceField::I = 8 , llvm::RISCVFenceField::O = 4 , llvm::RISCVFenceField::R = 2 , llvm::RISCVFenceField::W = 1 }
enum  llvm::RISCVFPRndMode::RoundingMode {
  llvm::RISCVFPRndMode::RNE = 0 , llvm::RISCVFPRndMode::RTZ = 1 , llvm::RISCVFPRndMode::RDN = 2 , llvm::RISCVFPRndMode::RUP = 3 ,
  llvm::RISCVFPRndMode::RMM = 4 , llvm::RISCVFPRndMode::DYN = 7 , llvm::RISCVFPRndMode::Invalid
}
enum  llvm::RISCVVXRndMode::RoundingMode {
  llvm::RISCVVXRndMode::RNU = 0 , llvm::RISCVVXRndMode::RNE = 1 , llvm::RISCVVXRndMode::RDN = 2 , llvm::RISCVVXRndMode::ROD = 3 ,
  llvm::RISCVVXRndMode::Invalid
}
enum  llvm::RISCVExceptFlags::ExceptionFlag {
  llvm::RISCVExceptFlags::NX = 0x01 , llvm::RISCVExceptFlags::UF = 0x02 , llvm::RISCVExceptFlags::OF = 0x04 , llvm::RISCVExceptFlags::DZ = 0x08 ,
  llvm::RISCVExceptFlags::NV = 0x10 , llvm::RISCVExceptFlags::ALL = 0x1F
}
enum  llvm::RISCVABI::ABI {
  llvm::RISCVABI::ABI_ILP32 , llvm::RISCVABI::ABI_ILP32F , llvm::RISCVABI::ABI_ILP32D , llvm::RISCVABI::ABI_ILP32E ,
  llvm::RISCVABI::ABI_LP64 , llvm::RISCVABI::ABI_LP64F , llvm::RISCVABI::ABI_LP64D , llvm::RISCVABI::ABI_LP64E ,
  llvm::RISCVABI::ABI_Unknown
}
enum  llvm::RISCVZC::RLISTENCODE {
  llvm::RISCVZC::RA = 4 , llvm::RISCVZC::RA_S0 , llvm::RISCVZC::RA_S0_S1 , llvm::RISCVZC::RA_S0_S2 ,
  llvm::RISCVZC::RA_S0_S3 , llvm::RISCVZC::RA_S0_S4 , llvm::RISCVZC::RA_S0_S5 , llvm::RISCVZC::RA_S0_S6 ,
  llvm::RISCVZC::RA_S0_S7 , llvm::RISCVZC::RA_S0_S8 , llvm::RISCVZC::RA_S0_S9 , llvm::RISCVZC::RA_S0_S11 ,
  llvm::RISCVZC::INVALID_RLIST
}

Functions

static unsigned llvm::RISCVII::getFormat (uint64_t TSFlags)
static RISCVVType::VLMUL llvm::RISCVII::getLMul (uint64_t TSFlags)
static bool llvm::RISCVII::isTiedPseudo (uint64_t TSFlags)
static bool llvm::RISCVII::hasSEWOp (uint64_t TSFlags)
static bool llvm::RISCVII::hasVLOp (uint64_t TSFlags)
static bool llvm::RISCVII::hasVecPolicyOp (uint64_t TSFlags)
static bool llvm::RISCVII::isRVVWideningReduction (uint64_t TSFlags)
static bool llvm::RISCVII::usesMaskPolicy (uint64_t TSFlags)
static bool llvm::RISCVII::hasRoundModeOp (uint64_t TSFlags)
static bool llvm::RISCVII::usesVXRM (uint64_t TSFlags)
static bool llvm::RISCVII::elementsDependOnVL (uint64_t TSFlags)
static bool llvm::RISCVII::elementsDependOnMask (uint64_t TSFlags)
static bool llvm::RISCVII::readsPastVL (uint64_t TSFlags)
static unsigned llvm::RISCVII::getVLOpNum (const MCInstrDesc &Desc)
static MCRegister llvm::RISCVII::getTailExpandUseRegNo (const FeatureBitset &FeatureBits)
static unsigned llvm::RISCVII::getSEWOpNum (const MCInstrDesc &Desc)
static unsigned llvm::RISCVII::getVecPolicyOpNum (const MCInstrDesc &Desc)
static int llvm::RISCVII::getFRMOpNum (const MCInstrDesc &Desc)
static int llvm::RISCVII::getVXRMOpNum (const MCInstrDesc &Desc)
static bool llvm::RISCVII::isFirstDefTiedToFirstUse (const MCInstrDesc &Desc)
static StringRef llvm::RISCVFPRndMode::roundingModeToString (RoundingMode RndMode)
static RoundingMode llvm::RISCVFPRndMode::stringToRoundingMode (StringRef Str)
static bool llvm::RISCVFPRndMode::isValidRoundingMode (unsigned Mode)
static StringRef llvm::RISCVVXRndMode::roundingModeToString (RoundingMode RndMode)
static RoundingMode llvm::RISCVVXRndMode::stringToRoundingMode (StringRef Str)
static bool llvm::RISCVVXRndMode::isValidRoundingMode (unsigned Mode)
float llvm::RISCVLoadFPImm::getFPImm (unsigned Imm)
int llvm::RISCVLoadFPImm::getLoadFPImm (APFloat FPImm)
 getLoadFPImm - Return a 5-bit binary encoding of the floating-point immediate value.
ABI llvm::RISCVABI::computeTargetABI (const Triple &TT, const FeatureBitset &FeatureBits, StringRef ABIName)
ABI llvm::RISCVABI::getTargetABI (StringRef ABIName)
MCRegister llvm::RISCVABI::getBPReg ()
MCRegister llvm::RISCVABI::getSCSPReg ()
void llvm::RISCVFeatures::validate (const Triple &TT, const FeatureBitset &FeatureBits)
llvm::Expected< std::unique_ptr< RISCVISAInfo > > llvm::RISCVFeatures::parseFeatureBits (bool IsRV64, const FeatureBitset &FeatureBits)
bool llvm::RISCVRVC::compress (MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
bool llvm::RISCVRVC::uncompress (MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
unsigned llvm::RISCVZC::encodeRegList (MCRegister EndReg, bool IsRVE=false)
static unsigned llvm::RISCVZC::encodeRegListNumRegs (unsigned NumRegs)
static unsigned llvm::RISCVZC::getStackAdjBase (unsigned RlistVal, bool IsRV64)
void llvm::RISCVZC::printRegList (unsigned RlistEncode, raw_ostream &OS)

Macro Definition Documentation

◆ GET_RISCVNDSVLNTable_DECL

#define GET_RISCVNDSVLNTable_DECL

Definition at line 790 of file RISCVBaseInfo.h.

◆ GET_RISCVOpcodesList_DECL

#define GET_RISCVOpcodesList_DECL

Definition at line 573 of file RISCVBaseInfo.h.

◆ GET_RISCVVInversePseudosTable_DECL

#define GET_RISCVVInversePseudosTable_DECL

Definition at line 704 of file RISCVBaseInfo.h.

◆ GET_RISCVVLETable_DECL

#define GET_RISCVVLETable_DECL

Definition at line 786 of file RISCVBaseInfo.h.

◆ GET_RISCVVLSEGTable_DECL

#define GET_RISCVVLSEGTable_DECL

Definition at line 783 of file RISCVBaseInfo.h.

◆ GET_RISCVVLXSEGTable_DECL

#define GET_RISCVVLXSEGTable_DECL

Definition at line 784 of file RISCVBaseInfo.h.

◆ GET_RISCVVLXTable_DECL

#define GET_RISCVVLXTable_DECL

Definition at line 788 of file RISCVBaseInfo.h.

◆ GET_RISCVVSETable_DECL

#define GET_RISCVVSETable_DECL

Definition at line 787 of file RISCVBaseInfo.h.

◆ GET_RISCVVSSEGTable_DECL

#define GET_RISCVVSSEGTable_DECL

Definition at line 782 of file RISCVBaseInfo.h.

◆ GET_RISCVVSXSEGTable_DECL

#define GET_RISCVVSXSEGTable_DECL

Definition at line 785 of file RISCVBaseInfo.h.

◆ GET_RISCVVSXTable_DECL

#define GET_RISCVVSXTable_DECL

Definition at line 789 of file RISCVBaseInfo.h.

◆ GET_SysRegEncodings_DECL

#define GET_SysRegEncodings_DECL

Definition at line 562 of file RISCVBaseInfo.h.

◆ GET_SysRegsList_DECL

#define GET_SysRegsList_DECL

Definition at line 563 of file RISCVBaseInfo.h.

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