LLVM 18.0.0git
RegisterBank.cpp
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1//===- llvm/CodeGen/GlobalISel/RegisterBank.cpp - Register Bank --*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the RegisterBank class.
10//===----------------------------------------------------------------------===//
11
16#include "llvm/Config/llvm-config.h"
17#include "llvm/Support/Debug.h"
18
19#define DEBUG_TYPE "registerbank"
20
21using namespace llvm;
22
23const unsigned RegisterBank::InvalidID = UINT_MAX;
24
25RegisterBank::RegisterBank(unsigned ID, const char *Name,
26 const uint32_t *CoveredClasses,
27 unsigned NumRegClasses)
28 : ID(ID), Name(Name) {
29 ContainedRegClasses.resize(NumRegClasses);
30 ContainedRegClasses.setBitsInMask(CoveredClasses);
31}
32
34 const TargetRegisterInfo &TRI) const {
35 assert(isValid() && "Invalid register bank");
36 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
37 const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
38
39 if (!covers(RC))
40 continue;
41 // Verify that the register bank covers all the sub classes of the
42 // classes it covers.
43
44 // Use a different (slow in that case) method than
45 // RegisterBankInfo to find the subclasses of RC, to make sure
46 // both agree on the covers.
47 for (unsigned SubRCId = 0; SubRCId != End; ++SubRCId) {
48 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
49
50 if (!RC.hasSubClassEq(&SubRC))
51 continue;
52
53 // Verify that the Size of the register bank is big enough to cover
54 // all the register classes it covers.
55 assert(RBI.getMaximumSize(getID()) >= TRI.getRegSizeInBits(SubRC) &&
56 "Size is not big enough for all the subclasses!");
57 assert(covers(SubRC) && "Not all subclasses are covered");
58 }
59 }
60 return true;
61}
62
64 assert(isValid() && "RB hasn't been initialized yet");
65 return ContainedRegClasses.test(RC.getID());
66}
67
69 return ID != InvalidID && Name != nullptr &&
70 // A register bank that does not cover anything is useless.
71 !ContainedRegClasses.empty();
72}
73
74bool RegisterBank::operator==(const RegisterBank &OtherRB) const {
75 // There must be only one instance of a given register bank alive
76 // for the whole compilation.
77 // The RegisterBankInfo is supposed to enforce that.
78 assert((OtherRB.getID() != getID() || &OtherRB == this) &&
79 "ID does not uniquely identify a RegisterBank");
80 return &OtherRB == this;
81}
82
83#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
85 print(dbgs(), /* IsForDebug */ true, TRI);
86}
87#endif
88
89void RegisterBank::print(raw_ostream &OS, bool IsForDebug,
90 const TargetRegisterInfo *TRI) const {
91 OS << getName();
92 if (!IsForDebug)
93 return;
94 OS << "(ID:" << getID() << ")\n"
95 << "isValid:" << isValid() << '\n'
96 << "Number of Covered register classes: " << ContainedRegClasses.count()
97 << '\n';
98 // Print all the subclasses if we can.
99 // This register classes may not be properly initialized yet.
100 if (!TRI || ContainedRegClasses.empty())
101 return;
102 assert(ContainedRegClasses.size() == TRI->getNumRegClasses() &&
103 "TRI does not match the initialization process?");
104 OS << "Covered register classes:\n";
105 ListSeparator LS;
106 for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) {
107 const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
108
109 if (covers(RC))
110 OS << LS << TRI->getRegClassName(&RC);
111 }
112}
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:510
std::string Name
bool End
Definition: ELF_riscv.cpp:469
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file contains some functions that are useful when dealing with strings.
bool test(unsigned Idx) const
Definition: BitVector.h:461
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:341
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:162
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:707
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:159
bool empty() const
empty - Tests whether there are no bits in this bitvector.
Definition: BitVector.h:156
Holds all the information related to register banks.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
This class implements the register bank concept.
Definition: RegisterBank.h:28
bool verify(const RegisterBankInfo &RBI, const TargetRegisterInfo &TRI) const
Check if this register bank is valid.
void print(raw_ostream &OS, bool IsForDebug=false, const TargetRegisterInfo *TRI=nullptr) const
Print the register mask on OS.
bool isValid() const
Check whether this instance is ready to be used.
void dump(const TargetRegisterInfo *TRI=nullptr) const
Dump the register mask on dbgs() stream.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:50
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:46
bool operator==(const RegisterBank &OtherRB) const
Check whether OtherRB is the same as this.
RegisterBank(unsigned ID, const char *Name, const uint32_t *CoveredClasses, unsigned NumRegClasses)
unsigned getID() const
Return the register class ID number.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163