13#ifndef LLVM_CODEGEN_REGISTERBANK_H
14#define LLVM_CODEGEN_REGISTERBANK_H
20class RegisterBankInfo;
22class TargetRegisterClass;
23class TargetRegisterInfo;
37 static const unsigned InvalidID;
44 const uint32_t *CoveredClasses,
unsigned NumRegClasses);
51 const char *
getName()
const {
return Name; }
This file implements the BitVector class.
unsigned const TargetRegisterInfo * TRI
Holds all the information related to register banks.
This class implements the register bank concept.
void print(raw_ostream &OS, bool IsForDebug=false, const TargetRegisterInfo *TRI=nullptr) const
Print the register mask on OS.
bool isValid() const
Check whether this instance is ready to be used.
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
void dump(const TargetRegisterInfo *TRI=nullptr) const
Dump the register mask on dbgs() stream.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
const char * getName() const
Get a user friendly name of this register bank.
unsigned getID() const
Get the identifier of this register bank.
bool operator!=(const RegisterBank &OtherRB) const
bool operator==(const RegisterBank &OtherRB) const
Check whether OtherRB is the same as this.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class implements an extremely fast bulk output stream that can only output to a stream.
This is an optimization pass for GlobalISel generic memory operations.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)