LLVM 17.0.0git
RegisterBankInfo.h
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1//===- llvm/CodeGen/RegisterBankInfo.h --------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file declares the API for the register bank info.
10/// This API is responsible for handling the register banks.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_REGISTERBANKINFO_H
15#define LLVM_CODEGEN_REGISTERBANKINFO_H
16
17#include "llvm/ADT/DenseMap.h"
18#include "llvm/ADT/Hashing.h"
24#include <cassert>
25#include <initializer_list>
26#include <memory>
27
28namespace llvm {
29
30class MachineInstr;
31class MachineRegisterInfo;
32class raw_ostream;
33class RegisterBank;
34class TargetInstrInfo;
35class TargetRegisterClass;
36class TargetRegisterInfo;
37
38/// Holds all the information related to register banks.
40public:
41 /// Helper struct that represents how a value is partially mapped
42 /// into a register.
43 /// The StartIdx and Length represent what region of the orginal
44 /// value this partial mapping covers.
45 /// This can be represented as a Mask of contiguous bit starting
46 /// at StartIdx bit and spanning Length bits.
47 /// StartIdx is the number of bits from the less significant bits.
49 /// Number of bits at which this partial mapping starts in the
50 /// original value. The bits are counted from less significant
51 /// bits to most significant bits.
52 unsigned StartIdx;
53
54 /// Length of this mapping in bits. This is how many bits this
55 /// partial mapping covers in the original value:
56 /// from StartIdx to StartIdx + Length -1.
57 unsigned Length;
58
59 /// Register bank where the partial value lives.
61
62 PartialMapping() = default;
63
64 /// Provide a shortcut for quickly building PartialMapping.
65 PartialMapping(unsigned StartIdx, unsigned Length,
66 const RegisterBank &RegBank)
68
69 /// \return the index of in the original value of the most
70 /// significant bit that this partial mapping covers.
71 unsigned getHighBitIdx() const { return StartIdx + Length - 1; }
72
73 /// Print this partial mapping on dbgs() stream.
74 void dump() const;
75
76 /// Print this partial mapping on \p OS;
77 void print(raw_ostream &OS) const;
78
79 /// Check that the Mask is compatible with the RegBank.
80 /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask,
81 /// there is no way this mapping is valid.
82 ///
83 /// \note This method does not check anything when assertions are disabled.
84 ///
85 /// \return True is the check was successful.
86 bool verify() const;
87 };
88
89 /// Helper struct that represents how a value is mapped through
90 /// different register banks.
91 ///
92 /// \note: So far we do not have any users of the complex mappings
93 /// (mappings with more than one partial mapping), but when we do,
94 /// we would have needed to duplicate partial mappings.
95 /// The alternative could be to use an array of pointers of partial
96 /// mapping (i.e., PartialMapping **BreakDown) and duplicate the
97 /// pointers instead.
98 ///
99 /// E.g.,
100 /// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We
101 /// can expand the
102 /// <2 x 32-bit> add into 2 x 32-bit add.
103 ///
104 /// Currently the TableGen-like file would look like:
105 /// \code
106 /// PartialMapping[] = {
107 /// /*32-bit add*/ {0, 32, GPR}, // Scalar entry repeated for first
108 /// // vec elt.
109 /// /*2x32-bit add*/ {0, 32, GPR}, {32, 32, GPR},
110 /// /*<2x32-bit> vadd*/ {0, 64, VPR}
111 /// }; // PartialMapping duplicated.
112 ///
113 /// ValueMapping[] {
114 /// /*plain 32-bit add*/ {&PartialMapping[0], 1},
115 /// /*expanded vadd on 2xadd*/ {&PartialMapping[1], 2},
116 /// /*plain <2x32-bit> vadd*/ {&PartialMapping[3], 1}
117 /// };
118 /// \endcode
119 ///
120 /// With the array of pointer, we would have:
121 /// \code
122 /// PartialMapping[] = {
123 /// /*32-bit add lower */ { 0, 32, GPR},
124 /// /*32-bit add upper */ {32, 32, GPR},
125 /// /*<2x32-bit> vadd */ { 0, 64, VPR}
126 /// }; // No more duplication.
127 ///
128 /// BreakDowns[] = {
129 /// /*AddBreakDown*/ &PartialMapping[0],
130 /// /*2xAddBreakDown*/ &PartialMapping[0], &PartialMapping[1],
131 /// /*VAddBreakDown*/ &PartialMapping[2]
132 /// }; // Addresses of PartialMapping duplicated (smaller).
133 ///
134 /// ValueMapping[] {
135 /// /*plain 32-bit add*/ {&BreakDowns[0], 1},
136 /// /*expanded vadd on 2xadd*/ {&BreakDowns[1], 2},
137 /// /*plain <2x32-bit> vadd*/ {&BreakDowns[3], 1}
138 /// };
139 /// \endcode
140 ///
141 /// Given that a PartialMapping is actually small, the code size
142 /// impact is actually a degradation. Moreover the compile time will
143 /// be hit by the additional indirection.
144 /// If PartialMapping gets bigger we may reconsider.
146 /// How the value is broken down between the different register banks.
148
149 /// Number of partial mapping to break down this value.
151
152 /// The default constructor creates an invalid (isValid() == false)
153 /// instance.
154 ValueMapping() : ValueMapping(nullptr, 0) {}
155
156 /// Initialize a ValueMapping with the given parameter.
157 /// \p BreakDown needs to have a life time at least as long
158 /// as this instance.
161
162 /// Iterators through the PartialMappings.
163 const PartialMapping *begin() const { return BreakDown; }
164 const PartialMapping *end() const { return BreakDown + NumBreakDowns; }
165
166 /// \return true if all partial mappings are the same size and register
167 /// bank.
168 bool partsAllUniform() const;
169
170 /// Check if this ValueMapping is valid.
171 bool isValid() const { return BreakDown && NumBreakDowns; }
172
173 /// Verify that this mapping makes sense for a value of
174 /// \p MeaningfulBitWidth.
175 /// \note This method does not check anything when assertions are disabled.
176 ///
177 /// \return True is the check was successful.
178 bool verify(unsigned MeaningfulBitWidth) const;
179
180 /// Print this on dbgs() stream.
181 void dump() const;
182
183 /// Print this on \p OS;
184 void print(raw_ostream &OS) const;
185 };
186
187 /// Helper class that represents how the value of an instruction may be
188 /// mapped and what is the related cost of such mapping.
190 /// Identifier of the mapping.
191 /// This is used to communicate between the target and the optimizers
192 /// which mapping should be realized.
193 unsigned ID = InvalidMappingID;
194
195 /// Cost of this mapping.
196 unsigned Cost = 0;
197
198 /// Mapping of all the operands.
199 const ValueMapping *OperandsMapping = nullptr;
200
201 /// Number of operands.
202 unsigned NumOperands = 0;
203
204 const ValueMapping &getOperandMapping(unsigned i) {
205 assert(i < getNumOperands() && "Out of bound operand");
206 return OperandsMapping[i];
207 }
208
209 public:
210 /// Constructor for the mapping of an instruction.
211 /// \p NumOperands must be equal to number of all the operands of
212 /// the related instruction.
213 /// The rationale is that it is more efficient for the optimizers
214 /// to be able to assume that the mapping of the ith operand is
215 /// at the index i.
216 InstructionMapping(unsigned ID, unsigned Cost,
217 const ValueMapping *OperandsMapping,
218 unsigned NumOperands)
219 : ID(ID), Cost(Cost), OperandsMapping(OperandsMapping),
220 NumOperands(NumOperands) {}
221
222 /// Default constructor.
223 /// Use this constructor to express that the mapping is invalid.
225
226 /// Get the cost.
227 unsigned getCost() const { return Cost; }
228
229 /// Get the ID.
230 unsigned getID() const { return ID; }
231
232 /// Get the number of operands.
233 unsigned getNumOperands() const { return NumOperands; }
234
235 /// Get the value mapping of the ith operand.
236 /// \pre The mapping for the ith operand has been set.
237 /// \pre The ith operand is a register.
238 const ValueMapping &getOperandMapping(unsigned i) const {
239 const ValueMapping &ValMapping =
240 const_cast<InstructionMapping *>(this)->getOperandMapping(i);
241 return ValMapping;
242 }
243
244 /// Set the mapping for all the operands.
245 /// In other words, OpdsMapping should hold at least getNumOperands
246 /// ValueMapping.
247 void setOperandsMapping(const ValueMapping *OpdsMapping) {
248 OperandsMapping = OpdsMapping;
249 }
250
251 /// Check whether this object is valid.
252 /// This is a lightweight check for obvious wrong instance.
253 bool isValid() const {
254 return getID() != InvalidMappingID && OperandsMapping;
255 }
256
257 /// Verifiy that this mapping makes sense for \p MI.
258 /// \pre \p MI must be connected to a MachineFunction.
259 ///
260 /// \note This method does not check anything when assertions are disabled.
261 ///
262 /// \return True is the check was successful.
263 bool verify(const MachineInstr &MI) const;
264
265 /// Print this on dbgs() stream.
266 void dump() const;
267
268 /// Print this on \p OS;
269 void print(raw_ostream &OS) const;
270 };
271
272 /// Convenient type to represent the alternatives for mapping an
273 /// instruction.
274 /// \todo When we move to TableGen this should be an array ref.
276
277 /// Helper class used to get/create the virtual registers that will be used
278 /// to replace the MachineOperand when applying a mapping.
280 /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the
281 /// OpIdx-th operand starts. -1 means we do not have such mapping yet.
282 /// Note: We use a SmallVector to avoid heap allocation for most cases.
283 SmallVector<int, 8> OpToNewVRegIdx;
284
285 /// Hold the registers that will be used to map MI with InstrMapping.
287
288 /// Current MachineRegisterInfo, used to create new virtual registers.
290
291 /// Instruction being remapped.
292 MachineInstr &MI;
293
294 /// New mapping of the instruction.
295 const InstructionMapping &InstrMapping;
296
297 /// Constant value identifying that the index in OpToNewVRegIdx
298 /// for an operand has not been set yet.
299 static const int DontKnowIdx;
300
301 /// Get the range in NewVRegs to store all the partial
302 /// values for the \p OpIdx-th operand.
303 ///
304 /// \return The iterator range for the space created.
305 //
306 /// \pre getMI().getOperand(OpIdx).isReg()
308 getVRegsMem(unsigned OpIdx);
309
310 /// Get the end iterator for a range starting at \p StartIdx and
311 /// spannig \p NumVal in NewVRegs.
312 /// \pre StartIdx + NumVal <= NewVRegs.size()
314 getNewVRegsEnd(unsigned StartIdx, unsigned NumVal) const;
315 SmallVectorImpl<Register>::iterator getNewVRegsEnd(unsigned StartIdx,
316 unsigned NumVal);
317
318 public:
319 /// Create an OperandsMapper that will hold the information to apply \p
320 /// InstrMapping to \p MI.
321 /// \pre InstrMapping.verify(MI)
322 OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping,
324
325 /// \name Getters.
326 /// @{
327 /// The MachineInstr being remapped.
328 MachineInstr &getMI() const { return MI; }
329
330 /// The final mapping of the instruction.
331 const InstructionMapping &getInstrMapping() const { return InstrMapping; }
332
333 /// The MachineRegisterInfo we used to realize the mapping.
334 MachineRegisterInfo &getMRI() const { return MRI; }
335 /// @}
336
337 /// Create as many new virtual registers as needed for the mapping of the \p
338 /// OpIdx-th operand.
339 /// The number of registers is determined by the number of breakdown for the
340 /// related operand in the instruction mapping.
341 /// The type of the new registers is a plain scalar of the right size.
342 /// The proper type is expected to be set when the mapping is applied to
343 /// the instruction(s) that realizes the mapping.
344 ///
345 /// \pre getMI().getOperand(OpIdx).isReg()
346 ///
347 /// \post All the partial mapping of the \p OpIdx-th operand have been
348 /// assigned a new virtual register.
349 void createVRegs(unsigned OpIdx);
350
351 /// Set the virtual register of the \p PartialMapIdx-th partial mapping of
352 /// the OpIdx-th operand to \p NewVReg.
353 ///
354 /// \pre getMI().getOperand(OpIdx).isReg()
355 /// \pre getInstrMapping().getOperandMapping(OpIdx).BreakDown.size() >
356 /// PartialMapIdx
357 /// \pre NewReg != 0
358 ///
359 /// \post the \p PartialMapIdx-th register of the value mapping of the \p
360 /// OpIdx-th operand has been set.
361 void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, Register NewVReg);
362
363 /// Get all the virtual registers required to map the \p OpIdx-th operand of
364 /// the instruction.
365 ///
366 /// This return an empty range when createVRegs or setVRegs has not been
367 /// called.
368 /// The iterator may be invalidated by a call to setVRegs or createVRegs.
369 ///
370 /// When \p ForDebug is true, we will not check that the list of new virtual
371 /// registers does not contain uninitialized values.
372 ///
373 /// \pre getMI().getOperand(OpIdx).isReg()
374 /// \pre ForDebug || All partial mappings have been set a register
376 getVRegs(unsigned OpIdx, bool ForDebug = false) const;
377
378 /// Print this operands mapper on dbgs() stream.
379 void dump() const;
380
381 /// Print this operands mapper on \p OS stream.
382 void print(raw_ostream &OS, bool ForDebug = false) const;
383 };
384
385protected:
386 /// Hold the set of supported register banks.
388
389 /// Total number of register banks.
390 unsigned NumRegBanks;
391
392 /// Keep dynamically allocated PartialMapping in a separate map.
393 /// This shouldn't be needed when everything gets TableGen'ed.
396
397 /// Keep dynamically allocated ValueMapping in a separate map.
398 /// This shouldn't be needed when everything gets TableGen'ed.
401
402 /// Keep dynamically allocated array of ValueMapping in a separate map.
403 /// This shouldn't be needed when everything gets TableGen'ed.
406
407 /// Keep dynamically allocated InstructionMapping in a separate map.
408 /// This shouldn't be needed when everything gets TableGen'ed.
411
412 /// Getting the minimal register class of a physreg is expensive.
413 /// Cache this information as we get it.
415
416 /// Create a RegisterBankInfo that can accommodate up to \p NumRegBanks
417 /// RegisterBank instances.
419
420 /// This constructor is meaningless.
421 /// It just provides a default constructor that can be used at link time
422 /// when GlobalISel is not built.
423 /// That way, targets can still inherit from this class without doing
424 /// crazy gymnastic to avoid link time failures.
425 /// \note That works because the constructor is inlined.
427 llvm_unreachable("This constructor should not be executed");
428 }
429
430 /// Get the register bank identified by \p ID.
432 assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
433 return *RegBanks[ID];
434 }
435
436 /// Get the MinimalPhysRegClass for Reg.
437 /// \pre Reg is a physical register.
438 const TargetRegisterClass *
440
441 /// Try to get the mapping of \p MI.
442 /// See getInstrMapping for more details on what a mapping represents.
443 ///
444 /// Unlike getInstrMapping the returned InstructionMapping may be invalid
445 /// (isValid() == false).
446 /// This means that the target independent code is not smart enough
447 /// to get the mapping of \p MI and thus, the target has to provide the
448 /// information for \p MI.
449 ///
450 /// This implementation is able to get the mapping of:
451 /// - Target specific instructions by looking at the encoding constraints.
452 /// - Any instruction if all the register operands have already been assigned
453 /// a register, a register class, or a register bank.
454 /// - Copies and phis if at least one of the operands has been assigned a
455 /// register, a register class, or a register bank.
456 /// In other words, this method will likely fail to find a mapping for
457 /// any generic opcode that has not been lowered by target specific code.
458 const InstructionMapping &getInstrMappingImpl(const MachineInstr &MI) const;
459
460 /// Get the uniquely generated PartialMapping for the
461 /// given arguments.
462 const PartialMapping &getPartialMapping(unsigned StartIdx, unsigned Length,
463 const RegisterBank &RegBank) const;
464
465 /// \name Methods to get a uniquely generated ValueMapping.
466 /// @{
467
468 /// The most common ValueMapping consists of a single PartialMapping.
469 /// Feature a method for that.
470 const ValueMapping &getValueMapping(unsigned StartIdx, unsigned Length,
471 const RegisterBank &RegBank) const;
472
473 /// Get the ValueMapping for the given arguments.
474 const ValueMapping &getValueMapping(const PartialMapping *BreakDown,
475 unsigned NumBreakDowns) const;
476 /// @}
477
478 /// \name Methods to get a uniquely generated array of ValueMapping.
479 /// @{
480
481 /// Get the uniquely generated array of ValueMapping for the
482 /// elements of between \p Begin and \p End.
483 ///
484 /// Elements that are nullptr will be replaced by
485 /// invalid ValueMapping (ValueMapping::isValid == false).
486 ///
487 /// \pre The pointers on ValueMapping between \p Begin and \p End
488 /// must uniquely identify a ValueMapping. Otherwise, there is no
489 /// guarantee that the return instance will be unique, i.e., another
490 /// OperandsMapping could have the same content.
491 template <typename Iterator>
492 const ValueMapping *getOperandsMapping(Iterator Begin, Iterator End) const;
493
494 /// Get the uniquely generated array of ValueMapping for the
495 /// elements of \p OpdsMapping.
496 ///
497 /// Elements of \p OpdsMapping that are nullptr will be replaced by
498 /// invalid ValueMapping (ValueMapping::isValid == false).
499 const ValueMapping *getOperandsMapping(
500 const SmallVectorImpl<const ValueMapping *> &OpdsMapping) const;
501
502 /// Get the uniquely generated array of ValueMapping for the
503 /// given arguments.
504 ///
505 /// Arguments that are nullptr will be replaced by invalid
506 /// ValueMapping (ValueMapping::isValid == false).
508 std::initializer_list<const ValueMapping *> OpdsMapping) const;
509 /// @}
510
511 /// \name Methods to get a uniquely generated InstructionMapping.
512 /// @{
513
514private:
515 /// Method to get a uniquely generated InstructionMapping.
516 const InstructionMapping &
517 getInstructionMappingImpl(bool IsInvalid, unsigned ID = InvalidMappingID,
518 unsigned Cost = 0,
519 const ValueMapping *OperandsMapping = nullptr,
520 unsigned NumOperands = 0) const;
521
522public:
523 /// Method to get a uniquely generated InstructionMapping.
524 const InstructionMapping &
525 getInstructionMapping(unsigned ID, unsigned Cost,
526 const ValueMapping *OperandsMapping,
527 unsigned NumOperands) const {
528 return getInstructionMappingImpl(/*IsInvalid*/ false, ID, Cost,
529 OperandsMapping, NumOperands);
530 }
531
532 /// Method to get a uniquely generated invalid InstructionMapping.
534 return getInstructionMappingImpl(/*IsInvalid*/ true);
535 }
536 /// @}
537
538 /// Get the register bank for the \p OpIdx-th operand of \p MI form
539 /// the encoding constraints, if any.
540 ///
541 /// \return A register bank that covers the register class of the
542 /// related encoding constraints or nullptr if \p MI did not provide
543 /// enough information to deduce it.
544 const RegisterBank *
545 getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx,
546 const TargetInstrInfo &TII,
547 const MachineRegisterInfo &MRI) const;
548
549 /// Helper method to apply something that is like the default mapping.
550 /// Basically, that means that \p OpdMapper.getMI() is left untouched
551 /// aside from the reassignment of the register operand that have been
552 /// remapped.
553 ///
554 /// The type of all the new registers that have been created by the
555 /// mapper are properly remapped to the type of the original registers
556 /// they replace. In other words, the semantic of the instruction does
557 /// not change, only the register banks.
558 ///
559 /// If the mapping of one of the operand spans several registers, this
560 /// method will abort as this is not like a default mapping anymore.
561 ///
562 /// \pre For OpIdx in {0..\p OpdMapper.getMI().getNumOperands())
563 /// the range OpdMapper.getVRegs(OpIdx) is empty or of size 1.
564 static void applyDefaultMapping(const OperandsMapper &OpdMapper);
565
566 /// See ::applyMapping.
567 virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const {
568 llvm_unreachable("The target has to implement that part");
569 }
570
571public:
572 virtual ~RegisterBankInfo() = default;
573
574 /// Get the register bank identified by \p ID.
575 const RegisterBank &getRegBank(unsigned ID) const {
576 return const_cast<RegisterBankInfo *>(this)->getRegBank(ID);
577 }
578
579 /// Get the register bank of \p Reg.
580 /// If Reg has not been assigned a register, a register class,
581 /// or a register bank, then this returns nullptr.
582 ///
583 /// \pre Reg != 0 (NoRegister)
585 const TargetRegisterInfo &TRI) const;
586
587 /// Get the total number of register banks.
588 unsigned getNumRegBanks() const { return NumRegBanks; }
589
590 /// Get a register bank that covers \p RC.
591 ///
592 /// \pre \p RC is a user-defined register class (as opposed as one
593 /// generated by TableGen).
594 ///
595 /// \note The mapping RC -> RegBank could be built while adding the
596 /// coverage for the register banks. However, we do not do it, because,
597 /// at least for now, we only need this information for register classes
598 /// that are used in the description of instruction. In other words,
599 /// there are just a handful of them and we do not want to waste space.
600 ///
601 /// \todo This should be TableGen'ed.
602 virtual const RegisterBank &
604 llvm_unreachable("The target must override this method");
605 }
606
607 /// Get the cost of a copy from \p B to \p A, or put differently,
608 /// get the cost of A = COPY B. Since register banks may cover
609 /// different size, \p Size specifies what will be the size in bits
610 /// that will be copied around.
611 ///
612 /// \note Since this is a copy, both registers have the same size.
613 virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
614 unsigned Size) const {
615 // Optimistically assume that copies are coalesced. I.e., when
616 // they are on the same bank, they are free.
617 // Otherwise assume a non-zero cost of 1. The targets are supposed
618 // to override that properly anyway if they care.
619 return &A != &B;
620 }
621
622 /// \returns true if emitting a copy from \p Src to \p Dst is impossible.
623 bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src,
624 unsigned Size) const {
625 return copyCost(Dst, Src, Size) == std::numeric_limits<unsigned>::max();
626 }
627
628 /// Get the cost of using \p ValMapping to decompose a register. This is
629 /// similar to ::copyCost, except for cases where multiple copy-like
630 /// operations need to be inserted. If the register is used as a source
631 /// operand and already has a bank assigned, \p CurBank is non-null.
632 virtual unsigned
634 const RegisterBank *CurBank = nullptr) const {
635 return std::numeric_limits<unsigned>::max();
636 }
637
638 /// Constrain the (possibly generic) virtual register \p Reg to \p RC.
639 ///
640 /// \pre \p Reg is a virtual register that either has a bank or a class.
641 /// \returns The constrained register class, or nullptr if there is none.
642 /// \note This is a generic variant of MachineRegisterInfo::constrainRegClass
643 /// \note Use MachineRegisterInfo::constrainRegAttrs instead for any non-isel
644 /// purpose, including non-select passes of GlobalISel
645 static const TargetRegisterClass *
648
649 /// Identifier used when the related instruction mapping instance
650 /// is generated by target independent code.
651 /// Make sure not to use that identifier to avoid possible collision.
652 static const unsigned DefaultMappingID;
653
654 /// Identifier used when the related instruction mapping instance
655 /// is generated by the default constructor.
656 /// Make sure not to use that identifier.
657 static const unsigned InvalidMappingID;
658
659 /// Get the mapping of the different operands of \p MI
660 /// on the register bank.
661 /// This mapping should be the direct translation of \p MI.
662 /// In other words, when \p MI is mapped with the returned mapping,
663 /// only the register banks of the operands of \p MI need to be updated.
664 /// In particular, neither the opcode nor the type of \p MI needs to be
665 /// updated for this direct mapping.
666 ///
667 /// The target independent implementation gives a mapping based on
668 /// the register classes for the target specific opcode.
669 /// It uses the ID RegisterBankInfo::DefaultMappingID for that mapping.
670 /// Make sure you do not use that ID for the alternative mapping
671 /// for MI. See getInstrAlternativeMappings for the alternative
672 /// mappings.
673 ///
674 /// For instance, if \p MI is a vector add, the mapping should
675 /// not be a scalarization of the add.
676 ///
677 /// \post returnedVal.verify(MI).
678 ///
679 /// \note If returnedVal does not verify MI, this would probably mean
680 /// that the target does not support that instruction.
681 virtual const InstructionMapping &
682 getInstrMapping(const MachineInstr &MI) const;
683
684 /// Get the alternative mappings for \p MI.
685 /// Alternative in the sense different from getInstrMapping.
686 virtual InstructionMappings
688
689 /// Get the possible mapping for \p MI.
690 /// A mapping defines where the different operands may live and at what cost.
691 /// For instance, let us consider:
692 /// v0(16) = G_ADD <2 x i8> v1, v2
693 /// The possible mapping could be:
694 ///
695 /// {/*ID*/VectorAdd, /*Cost*/1, /*v0*/{(0xFFFF, VPR)}, /*v1*/{(0xFFFF, VPR)},
696 /// /*v2*/{(0xFFFF, VPR)}}
697 /// {/*ID*/ScalarAddx2, /*Cost*/2, /*v0*/{(0x00FF, GPR),(0xFF00, GPR)},
698 /// /*v1*/{(0x00FF, GPR),(0xFF00, GPR)},
699 /// /*v2*/{(0x00FF, GPR),(0xFF00, GPR)}}
700 ///
701 /// \note The first alternative of the returned mapping should be the
702 /// direct translation of \p MI current form.
703 ///
704 /// \post !returnedVal.empty().
706
707 /// Apply \p OpdMapper.getInstrMapping() to \p OpdMapper.getMI().
708 /// After this call \p OpdMapper.getMI() may not be valid anymore.
709 /// \p OpdMapper.getInstrMapping().getID() carries the information of
710 /// what has been chosen to map \p OpdMapper.getMI(). This ID is set
711 /// by the various getInstrXXXMapping method.
712 ///
713 /// Therefore, getting the mapping and applying it should be kept in
714 /// sync.
715 void applyMapping(const OperandsMapper &OpdMapper) const {
716 // The only mapping we know how to handle is the default mapping.
717 if (OpdMapper.getInstrMapping().getID() == DefaultMappingID)
718 return applyDefaultMapping(OpdMapper);
719 // For other mapping, the target needs to do the right thing.
720 // If that means calling applyDefaultMapping, fine, but this
721 // must be explicitly stated.
722 applyMappingImpl(OpdMapper);
723 }
724
725 /// Get the size in bits of \p Reg.
726 /// Utility method to get the size of any registers. Unlike
727 /// MachineRegisterInfo::getSize, the register does not need to be a
728 /// virtual register.
729 ///
730 /// \pre \p Reg != 0 (NoRegister).
732 const TargetRegisterInfo &TRI) const;
733
734 /// Check that information hold by this instance make sense for the
735 /// given \p TRI.
736 ///
737 /// \note This method does not check anything when assertions are disabled.
738 ///
739 /// \return True is the check was successful.
740 bool verify(const TargetRegisterInfo &TRI) const;
741};
742
745 const RegisterBankInfo::PartialMapping &PartMapping) {
746 PartMapping.print(OS);
747 return OS;
748}
749
752 ValMapping.print(OS);
753 return OS;
754}
755
758 const RegisterBankInfo::InstructionMapping &InstrMapping) {
759 InstrMapping.print(OS);
760 return OS;
761}
762
765 OpdMapper.print(OS, /*ForDebug*/ false);
766 return OS;
767}
768
769/// Hashing function for PartialMapping.
770/// It is required for the hashing of ValueMapping.
771hash_code hash_value(const RegisterBankInfo::PartialMapping &PartMapping);
772
773} // end namespace llvm
774
775#endif // LLVM_CODEGEN_REGISTERBANKINFO_H
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
This file defines the DenseMap class.
uint64_t Size
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
Implement a low-level type suitable for MachineInstr level instruction selection.
unsigned const TargetRegisterInfo * TRI
unsigned Reg
ppc ctr loops verify
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file defines the SmallVector class.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned getNumOperands() const
Get the number of operands.
unsigned getCost() const
Get the cost.
InstructionMapping()=default
Default constructor.
void setOperandsMapping(const ValueMapping *OpdsMapping)
Set the mapping for all the operands.
void dump() const
Print this on dbgs() stream.
void print(raw_ostream &OS) const
Print this on OS;.
InstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands)
Constructor for the mapping of an instruction.
const ValueMapping & getOperandMapping(unsigned i) const
Get the value mapping of the ith operand.
bool isValid() const
Check whether this object is valid.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
const InstructionMapping & getInstrMapping() const
The final mapping of the instruction.
void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, Register NewVReg)
Set the virtual register of the PartialMapIdx-th partial mapping of the OpIdx-th operand to NewVReg.
void print(raw_ostream &OS, bool ForDebug=false) const
Print this operands mapper on OS stream.
void createVRegs(unsigned OpIdx)
Create as many new virtual registers as needed for the mapping of the OpIdx-th operand.
MachineRegisterInfo & getMRI() const
The MachineRegisterInfo we used to realize the mapping.
void dump() const
Print this operands mapper on dbgs() stream.
iterator_range< SmallVectorImpl< Register >::const_iterator > getVRegs(unsigned OpIdx, bool ForDebug=false) const
Get all the virtual registers required to map the OpIdx-th operand of the instruction.
Holds all the information related to register banks.
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
const PartialMapping & getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Get the uniquely generated PartialMapping for the given arguments.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
virtual ~RegisterBankInfo()=default
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const
See applyMapping.
RegisterBankInfo()
This constructor is meaningless.
void applyMapping(const OperandsMapper &OpdMapper) const
Apply OpdMapper.getInstrMapping() to OpdMapper.getMI().
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
unsigned NumRegBanks
Total number of register banks.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
const TargetRegisterClass * getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const
Get the MinimalPhysRegClass for Reg.
const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
The most common ValueMapping consists of a single PartialMapping.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
DenseMap< unsigned, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
Keep dynamically allocated array of ValueMapping in a separate map.
DenseMap< unsigned, std::unique_ptr< const ValueMapping > > MapOfValueMappings
Keep dynamically allocated ValueMapping in a separate map.
DenseMap< unsigned, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
Keep dynamically allocated InstructionMapping in a separate map.
unsigned getNumRegBanks() const
Get the total number of register banks.
const RegisterBank * getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const
Get the register bank for the OpIdx-th operand of MI form the encoding constraints,...
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const
Get a register bank that covers RC.
InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const
Get the possible mapping for MI.
RegisterBank ** RegBanks
Hold the set of supported register banks.
DenseMap< unsigned, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
Keep dynamically allocated PartialMapping in a separate map.
DenseMap< unsigned, const TargetRegisterClass * > PhysRegMinimalRCs
Getting the minimal register class of a physreg is expensive.
const RegisterBank & getRegBank(unsigned ID) const
Get the register bank identified by ID.
static const unsigned InvalidMappingID
Identifier used when the related instruction mapping instance is generated by the default constructor...
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src, unsigned Size) const
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
const ValueMapping * getOperandsMapping(std::initializer_list< const ValueMapping * > OpdsMapping) const
Get the uniquely generated array of ValueMapping for the given arguments.
virtual unsigned getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const
Get the cost of using ValMapping to decompose a register.
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:582
typename SuperClass::iterator iterator
Definition: SmallVector.h:581
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A range adaptor for a pair of iterators.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Length
Definition: DWP.cpp:406
hash_code hash_value(const FixedPointSemantics &Val)
Definition: APFixedPoint.h:128
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:292
Helper struct that represents how a value is partially mapped into a register.
void print(raw_ostream &OS) const
Print this partial mapping on OS;.
unsigned StartIdx
Number of bits at which this partial mapping starts in the original value.
PartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank)
Provide a shortcut for quickly building PartialMapping.
void dump() const
Print this partial mapping on dbgs() stream.
bool verify() const
Check that the Mask is compatible with the RegBank.
const RegisterBank * RegBank
Register bank where the partial value lives.
unsigned Length
Length of this mapping in bits.
Helper struct that represents how a value is mapped through different register banks.
const PartialMapping * begin() const
Iterators through the PartialMappings.
const PartialMapping * end() const
void print(raw_ostream &OS) const
Print this on OS;.
bool isValid() const
Check if this ValueMapping is valid.
unsigned NumBreakDowns
Number of partial mapping to break down this value.
ValueMapping()
The default constructor creates an invalid (isValid() == false) instance.
void dump() const
Print this on dbgs() stream.
ValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns)
Initialize a ValueMapping with the given parameter.
const PartialMapping * BreakDown
How the value is broken down between the different register banks.