LLVM  14.0.0git
RegisterBankInfo.h
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1 //===- llvm/CodeGen/GlobalISel/RegisterBankInfo.h ---------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API for the register bank info.
10 /// This API is responsible for handling the register banks.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
15 #define LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
16 
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/Hashing.h"
19 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/Register.h"
24 #include <cassert>
25 #include <initializer_list>
26 #include <memory>
27 
28 namespace llvm {
29 
30 class MachineInstr;
31 class MachineRegisterInfo;
32 class raw_ostream;
33 class RegisterBank;
34 class TargetInstrInfo;
35 class TargetRegisterClass;
36 class TargetRegisterInfo;
37 
38 /// Holds all the information related to register banks.
40 public:
41  /// Helper struct that represents how a value is partially mapped
42  /// into a register.
43  /// The StartIdx and Length represent what region of the orginal
44  /// value this partial mapping covers.
45  /// This can be represented as a Mask of contiguous bit starting
46  /// at StartIdx bit and spanning Length bits.
47  /// StartIdx is the number of bits from the less significant bits.
48  struct PartialMapping {
49  /// Number of bits at which this partial mapping starts in the
50  /// original value. The bits are counted from less significant
51  /// bits to most significant bits.
52  unsigned StartIdx;
53 
54  /// Length of this mapping in bits. This is how many bits this
55  /// partial mapping covers in the original value:
56  /// from StartIdx to StartIdx + Length -1.
57  unsigned Length;
58 
59  /// Register bank where the partial value lives.
61 
62  PartialMapping() = default;
63 
64  /// Provide a shortcut for quickly building PartialMapping.
65  PartialMapping(unsigned StartIdx, unsigned Length,
66  const RegisterBank &RegBank)
68 
69  /// \return the index of in the original value of the most
70  /// significant bit that this partial mapping covers.
71  unsigned getHighBitIdx() const { return StartIdx + Length - 1; }
72 
73  /// Print this partial mapping on dbgs() stream.
74  void dump() const;
75 
76  /// Print this partial mapping on \p OS;
77  void print(raw_ostream &OS) const;
78 
79  /// Check that the Mask is compatible with the RegBank.
80  /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask,
81  /// there is no way this mapping is valid.
82  ///
83  /// \note This method does not check anything when assertions are disabled.
84  ///
85  /// \return True is the check was successful.
86  bool verify() const;
87  };
88 
89  /// Helper struct that represents how a value is mapped through
90  /// different register banks.
91  ///
92  /// \note: So far we do not have any users of the complex mappings
93  /// (mappings with more than one partial mapping), but when we do,
94  /// we would have needed to duplicate partial mappings.
95  /// The alternative could be to use an array of pointers of partial
96  /// mapping (i.e., PartialMapping **BreakDown) and duplicate the
97  /// pointers instead.
98  ///
99  /// E.g.,
100  /// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We
101  /// can expand the
102  /// <2 x 32-bit> add into 2 x 32-bit add.
103  ///
104  /// Currently the TableGen-like file would look like:
105  /// \code
106  /// PartialMapping[] = {
107  /// /*32-bit add*/ {0, 32, GPR}, // Scalar entry repeated for first
108  /// // vec elt.
109  /// /*2x32-bit add*/ {0, 32, GPR}, {32, 32, GPR},
110  /// /*<2x32-bit> vadd*/ {0, 64, VPR}
111  /// }; // PartialMapping duplicated.
112  ///
113  /// ValueMapping[] {
114  /// /*plain 32-bit add*/ {&PartialMapping[0], 1},
115  /// /*expanded vadd on 2xadd*/ {&PartialMapping[1], 2},
116  /// /*plain <2x32-bit> vadd*/ {&PartialMapping[3], 1}
117  /// };
118  /// \endcode
119  ///
120  /// With the array of pointer, we would have:
121  /// \code
122  /// PartialMapping[] = {
123  /// /*32-bit add lower */ { 0, 32, GPR},
124  /// /*32-bit add upper */ {32, 32, GPR},
125  /// /*<2x32-bit> vadd */ { 0, 64, VPR}
126  /// }; // No more duplication.
127  ///
128  /// BreakDowns[] = {
129  /// /*AddBreakDown*/ &PartialMapping[0],
130  /// /*2xAddBreakDown*/ &PartialMapping[0], &PartialMapping[1],
131  /// /*VAddBreakDown*/ &PartialMapping[2]
132  /// }; // Addresses of PartialMapping duplicated (smaller).
133  ///
134  /// ValueMapping[] {
135  /// /*plain 32-bit add*/ {&BreakDowns[0], 1},
136  /// /*expanded vadd on 2xadd*/ {&BreakDowns[1], 2},
137  /// /*plain <2x32-bit> vadd*/ {&BreakDowns[3], 1}
138  /// };
139  /// \endcode
140  ///
141  /// Given that a PartialMapping is actually small, the code size
142  /// impact is actually a degradation. Moreover the compile time will
143  /// be hit by the additional indirection.
144  /// If PartialMapping gets bigger we may reconsider.
145  struct ValueMapping {
146  /// How the value is broken down between the different register banks.
148 
149  /// Number of partial mapping to break down this value.
150  unsigned NumBreakDowns;
151 
152  /// The default constructor creates an invalid (isValid() == false)
153  /// instance.
154  ValueMapping() : ValueMapping(nullptr, 0) {}
155 
156  /// Initialize a ValueMapping with the given parameter.
157  /// \p BreakDown needs to have a life time at least as long
158  /// as this instance.
161 
162  /// Iterators through the PartialMappings.
163  const PartialMapping *begin() const { return BreakDown; }
164  const PartialMapping *end() const { return BreakDown + NumBreakDowns; }
165 
166  /// \return true if all partial mappings are the same size and register
167  /// bank.
168  bool partsAllUniform() const;
169 
170  /// Check if this ValueMapping is valid.
171  bool isValid() const { return BreakDown && NumBreakDowns; }
172 
173  /// Verify that this mapping makes sense for a value of
174  /// \p MeaningfulBitWidth.
175  /// \note This method does not check anything when assertions are disabled.
176  ///
177  /// \return True is the check was successful.
178  bool verify(unsigned MeaningfulBitWidth) const;
179 
180  /// Print this on dbgs() stream.
181  void dump() const;
182 
183  /// Print this on \p OS;
184  void print(raw_ostream &OS) const;
185  };
186 
187  /// Helper class that represents how the value of an instruction may be
188  /// mapped and what is the related cost of such mapping.
190  /// Identifier of the mapping.
191  /// This is used to communicate between the target and the optimizers
192  /// which mapping should be realized.
193  unsigned ID = InvalidMappingID;
194 
195  /// Cost of this mapping.
196  unsigned Cost = 0;
197 
198  /// Mapping of all the operands.
199  const ValueMapping *OperandsMapping = nullptr;
200 
201  /// Number of operands.
202  unsigned NumOperands = 0;
203 
204  const ValueMapping &getOperandMapping(unsigned i) {
205  assert(i < getNumOperands() && "Out of bound operand");
206  return OperandsMapping[i];
207  }
208 
209  public:
210  /// Constructor for the mapping of an instruction.
211  /// \p NumOperands must be equal to number of all the operands of
212  /// the related instruction.
213  /// The rationale is that it is more efficient for the optimizers
214  /// to be able to assume that the mapping of the ith operand is
215  /// at the index i.
216  InstructionMapping(unsigned ID, unsigned Cost,
217  const ValueMapping *OperandsMapping,
218  unsigned NumOperands)
219  : ID(ID), Cost(Cost), OperandsMapping(OperandsMapping),
220  NumOperands(NumOperands) {
221  }
222 
223  /// Default constructor.
224  /// Use this constructor to express that the mapping is invalid.
225  InstructionMapping() = default;
226 
227  /// Get the cost.
228  unsigned getCost() const { return Cost; }
229 
230  /// Get the ID.
231  unsigned getID() const { return ID; }
232 
233  /// Get the number of operands.
234  unsigned getNumOperands() const { return NumOperands; }
235 
236  /// Get the value mapping of the ith operand.
237  /// \pre The mapping for the ith operand has been set.
238  /// \pre The ith operand is a register.
239  const ValueMapping &getOperandMapping(unsigned i) const {
240  const ValueMapping &ValMapping =
241  const_cast<InstructionMapping *>(this)->getOperandMapping(i);
242  return ValMapping;
243  }
244 
245  /// Set the mapping for all the operands.
246  /// In other words, OpdsMapping should hold at least getNumOperands
247  /// ValueMapping.
248  void setOperandsMapping(const ValueMapping *OpdsMapping) {
249  OperandsMapping = OpdsMapping;
250  }
251 
252  /// Check whether this object is valid.
253  /// This is a lightweight check for obvious wrong instance.
254  bool isValid() const {
255  return getID() != InvalidMappingID && OperandsMapping;
256  }
257 
258  /// Verifiy that this mapping makes sense for \p MI.
259  /// \pre \p MI must be connected to a MachineFunction.
260  ///
261  /// \note This method does not check anything when assertions are disabled.
262  ///
263  /// \return True is the check was successful.
264  bool verify(const MachineInstr &MI) const;
265 
266  /// Print this on dbgs() stream.
267  void dump() const;
268 
269  /// Print this on \p OS;
270  void print(raw_ostream &OS) const;
271  };
272 
273  /// Convenient type to represent the alternatives for mapping an
274  /// instruction.
275  /// \todo When we move to TableGen this should be an array ref.
277 
278  /// Helper class used to get/create the virtual registers that will be used
279  /// to replace the MachineOperand when applying a mapping.
281  /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the
282  /// OpIdx-th operand starts. -1 means we do not have such mapping yet.
283  /// Note: We use a SmallVector to avoid heap allocation for most cases.
284  SmallVector<int, 8> OpToNewVRegIdx;
285 
286  /// Hold the registers that will be used to map MI with InstrMapping.
287  SmallVector<Register, 8> NewVRegs;
288 
289  /// Current MachineRegisterInfo, used to create new virtual registers.
290  MachineRegisterInfo &MRI;
291 
292  /// Instruction being remapped.
293  MachineInstr &MI;
294 
295  /// New mapping of the instruction.
296  const InstructionMapping &InstrMapping;
297 
298  /// Constant value identifying that the index in OpToNewVRegIdx
299  /// for an operand has not been set yet.
300  static const int DontKnowIdx;
301 
302  /// Get the range in NewVRegs to store all the partial
303  /// values for the \p OpIdx-th operand.
304  ///
305  /// \return The iterator range for the space created.
306  //
307  /// \pre getMI().getOperand(OpIdx).isReg()
309  getVRegsMem(unsigned OpIdx);
310 
311  /// Get the end iterator for a range starting at \p StartIdx and
312  /// spannig \p NumVal in NewVRegs.
313  /// \pre StartIdx + NumVal <= NewVRegs.size()
315  getNewVRegsEnd(unsigned StartIdx, unsigned NumVal) const;
316  SmallVectorImpl<Register>::iterator getNewVRegsEnd(unsigned StartIdx,
317  unsigned NumVal);
318 
319  public:
320  /// Create an OperandsMapper that will hold the information to apply \p
321  /// InstrMapping to \p MI.
322  /// \pre InstrMapping.verify(MI)
323  OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping,
325 
326  /// \name Getters.
327  /// @{
328  /// The MachineInstr being remapped.
329  MachineInstr &getMI() const { return MI; }
330 
331  /// The final mapping of the instruction.
332  const InstructionMapping &getInstrMapping() const { return InstrMapping; }
333 
334  /// The MachineRegisterInfo we used to realize the mapping.
335  MachineRegisterInfo &getMRI() const { return MRI; }
336  /// @}
337 
338  /// Create as many new virtual registers as needed for the mapping of the \p
339  /// OpIdx-th operand.
340  /// The number of registers is determined by the number of breakdown for the
341  /// related operand in the instruction mapping.
342  /// The type of the new registers is a plain scalar of the right size.
343  /// The proper type is expected to be set when the mapping is applied to
344  /// the instruction(s) that realizes the mapping.
345  ///
346  /// \pre getMI().getOperand(OpIdx).isReg()
347  ///
348  /// \post All the partial mapping of the \p OpIdx-th operand have been
349  /// assigned a new virtual register.
350  void createVRegs(unsigned OpIdx);
351 
352  /// Set the virtual register of the \p PartialMapIdx-th partial mapping of
353  /// the OpIdx-th operand to \p NewVReg.
354  ///
355  /// \pre getMI().getOperand(OpIdx).isReg()
356  /// \pre getInstrMapping().getOperandMapping(OpIdx).BreakDown.size() >
357  /// PartialMapIdx
358  /// \pre NewReg != 0
359  ///
360  /// \post the \p PartialMapIdx-th register of the value mapping of the \p
361  /// OpIdx-th operand has been set.
362  void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, Register NewVReg);
363 
364  /// Get all the virtual registers required to map the \p OpIdx-th operand of
365  /// the instruction.
366  ///
367  /// This return an empty range when createVRegs or setVRegs has not been
368  /// called.
369  /// The iterator may be invalidated by a call to setVRegs or createVRegs.
370  ///
371  /// When \p ForDebug is true, we will not check that the list of new virtual
372  /// registers does not contain uninitialized values.
373  ///
374  /// \pre getMI().getOperand(OpIdx).isReg()
375  /// \pre ForDebug || All partial mappings have been set a register
377  getVRegs(unsigned OpIdx, bool ForDebug = false) const;
378 
379  /// Print this operands mapper on dbgs() stream.
380  void dump() const;
381 
382  /// Print this operands mapper on \p OS stream.
383  void print(raw_ostream &OS, bool ForDebug = false) const;
384  };
385 
386 protected:
387  /// Hold the set of supported register banks.
389 
390  /// Total number of register banks.
391  unsigned NumRegBanks;
392 
393  /// Keep dynamically allocated PartialMapping in a separate map.
394  /// This shouldn't be needed when everything gets TableGen'ed.
397 
398  /// Keep dynamically allocated ValueMapping in a separate map.
399  /// This shouldn't be needed when everything gets TableGen'ed.
402 
403  /// Keep dynamically allocated array of ValueMapping in a separate map.
404  /// This shouldn't be needed when everything gets TableGen'ed.
407 
408  /// Keep dynamically allocated InstructionMapping in a separate map.
409  /// This shouldn't be needed when everything gets TableGen'ed.
412 
413  /// Getting the minimal register class of a physreg is expensive.
414  /// Cache this information as we get it.
416 
417  /// Create a RegisterBankInfo that can accommodate up to \p NumRegBanks
418  /// RegisterBank instances.
420 
421  /// This constructor is meaningless.
422  /// It just provides a default constructor that can be used at link time
423  /// when GlobalISel is not built.
424  /// That way, targets can still inherit from this class without doing
425  /// crazy gymnastic to avoid link time failures.
426  /// \note That works because the constructor is inlined.
428  llvm_unreachable("This constructor should not be executed");
429  }
430 
431  /// Get the register bank identified by \p ID.
433  assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
434  return *RegBanks[ID];
435  }
436 
437  /// Get the MinimalPhysRegClass for Reg.
438  /// \pre Reg is a physical register.
439  const TargetRegisterClass &
441 
442  /// Try to get the mapping of \p MI.
443  /// See getInstrMapping for more details on what a mapping represents.
444  ///
445  /// Unlike getInstrMapping the returned InstructionMapping may be invalid
446  /// (isValid() == false).
447  /// This means that the target independent code is not smart enough
448  /// to get the mapping of \p MI and thus, the target has to provide the
449  /// information for \p MI.
450  ///
451  /// This implementation is able to get the mapping of:
452  /// - Target specific instructions by looking at the encoding constraints.
453  /// - Any instruction if all the register operands have already been assigned
454  /// a register, a register class, or a register bank.
455  /// - Copies and phis if at least one of the operands has been assigned a
456  /// register, a register class, or a register bank.
457  /// In other words, this method will likely fail to find a mapping for
458  /// any generic opcode that has not been lowered by target specific code.
459  const InstructionMapping &getInstrMappingImpl(const MachineInstr &MI) const;
460 
461  /// Get the uniquely generated PartialMapping for the
462  /// given arguments.
463  const PartialMapping &getPartialMapping(unsigned StartIdx, unsigned Length,
464  const RegisterBank &RegBank) const;
465 
466  /// \name Methods to get a uniquely generated ValueMapping.
467  /// @{
468 
469  /// The most common ValueMapping consists of a single PartialMapping.
470  /// Feature a method for that.
471  const ValueMapping &getValueMapping(unsigned StartIdx, unsigned Length,
472  const RegisterBank &RegBank) const;
473 
474  /// Get the ValueMapping for the given arguments.
475  const ValueMapping &getValueMapping(const PartialMapping *BreakDown,
476  unsigned NumBreakDowns) const;
477  /// @}
478 
479  /// \name Methods to get a uniquely generated array of ValueMapping.
480  /// @{
481 
482  /// Get the uniquely generated array of ValueMapping for the
483  /// elements of between \p Begin and \p End.
484  ///
485  /// Elements that are nullptr will be replaced by
486  /// invalid ValueMapping (ValueMapping::isValid == false).
487  ///
488  /// \pre The pointers on ValueMapping between \p Begin and \p End
489  /// must uniquely identify a ValueMapping. Otherwise, there is no
490  /// guarantee that the return instance will be unique, i.e., another
491  /// OperandsMapping could have the same content.
492  template <typename Iterator>
493  const ValueMapping *getOperandsMapping(Iterator Begin, Iterator End) const;
494 
495  /// Get the uniquely generated array of ValueMapping for the
496  /// elements of \p OpdsMapping.
497  ///
498  /// Elements of \p OpdsMapping that are nullptr will be replaced by
499  /// invalid ValueMapping (ValueMapping::isValid == false).
500  const ValueMapping *getOperandsMapping(
501  const SmallVectorImpl<const ValueMapping *> &OpdsMapping) const;
502 
503  /// Get the uniquely generated array of ValueMapping for the
504  /// given arguments.
505  ///
506  /// Arguments that are nullptr will be replaced by invalid
507  /// ValueMapping (ValueMapping::isValid == false).
508  const ValueMapping *getOperandsMapping(
509  std::initializer_list<const ValueMapping *> OpdsMapping) const;
510  /// @}
511 
512  /// \name Methods to get a uniquely generated InstructionMapping.
513  /// @{
514 
515 private:
516  /// Method to get a uniquely generated InstructionMapping.
517  const InstructionMapping &
518  getInstructionMappingImpl(bool IsInvalid, unsigned ID = InvalidMappingID,
519  unsigned Cost = 0,
520  const ValueMapping *OperandsMapping = nullptr,
521  unsigned NumOperands = 0) const;
522 
523 public:
524  /// Method to get a uniquely generated InstructionMapping.
525  const InstructionMapping &
526  getInstructionMapping(unsigned ID, unsigned Cost,
527  const ValueMapping *OperandsMapping,
528  unsigned NumOperands) const {
529  return getInstructionMappingImpl(/*IsInvalid*/ false, ID, Cost,
530  OperandsMapping, NumOperands);
531  }
532 
533  /// Method to get a uniquely generated invalid InstructionMapping.
535  return getInstructionMappingImpl(/*IsInvalid*/ true);
536  }
537  /// @}
538 
539  /// Get the register bank for the \p OpIdx-th operand of \p MI form
540  /// the encoding constraints, if any.
541  ///
542  /// \return A register bank that covers the register class of the
543  /// related encoding constraints or nullptr if \p MI did not provide
544  /// enough information to deduce it.
545  const RegisterBank *
546  getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx,
547  const TargetInstrInfo &TII,
548  const MachineRegisterInfo &MRI) const;
549 
550  /// Helper method to apply something that is like the default mapping.
551  /// Basically, that means that \p OpdMapper.getMI() is left untouched
552  /// aside from the reassignment of the register operand that have been
553  /// remapped.
554  ///
555  /// The type of all the new registers that have been created by the
556  /// mapper are properly remapped to the type of the original registers
557  /// they replace. In other words, the semantic of the instruction does
558  /// not change, only the register banks.
559  ///
560  /// If the mapping of one of the operand spans several registers, this
561  /// method will abort as this is not like a default mapping anymore.
562  ///
563  /// \pre For OpIdx in {0..\p OpdMapper.getMI().getNumOperands())
564  /// the range OpdMapper.getVRegs(OpIdx) is empty or of size 1.
565  static void applyDefaultMapping(const OperandsMapper &OpdMapper);
566 
567  /// See ::applyMapping.
568  virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const {
569  llvm_unreachable("The target has to implement that part");
570  }
571 
572 public:
573  virtual ~RegisterBankInfo() = default;
574 
575  /// Get the register bank identified by \p ID.
576  const RegisterBank &getRegBank(unsigned ID) const {
577  return const_cast<RegisterBankInfo *>(this)->getRegBank(ID);
578  }
579 
580  /// Get the register bank of \p Reg.
581  /// If Reg has not been assigned a register, a register class,
582  /// or a register bank, then this returns nullptr.
583  ///
584  /// \pre Reg != 0 (NoRegister)
586  const TargetRegisterInfo &TRI) const;
587 
588  /// Get the total number of register banks.
589  unsigned getNumRegBanks() const { return NumRegBanks; }
590 
591  /// Get a register bank that covers \p RC.
592  ///
593  /// \pre \p RC is a user-defined register class (as opposed as one
594  /// generated by TableGen).
595  ///
596  /// \note The mapping RC -> RegBank could be built while adding the
597  /// coverage for the register banks. However, we do not do it, because,
598  /// at least for now, we only need this information for register classes
599  /// that are used in the description of instruction. In other words,
600  /// there are just a handful of them and we do not want to waste space.
601  ///
602  /// \todo This should be TableGen'ed.
603  virtual const RegisterBank &
605  llvm_unreachable("The target must override this method");
606  }
607 
608  /// Get the cost of a copy from \p B to \p A, or put differently,
609  /// get the cost of A = COPY B. Since register banks may cover
610  /// different size, \p Size specifies what will be the size in bits
611  /// that will be copied around.
612  ///
613  /// \note Since this is a copy, both registers have the same size.
614  virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
615  unsigned Size) const {
616  // Optimistically assume that copies are coalesced. I.e., when
617  // they are on the same bank, they are free.
618  // Otherwise assume a non-zero cost of 1. The targets are supposed
619  // to override that properly anyway if they care.
620  return &A != &B;
621  }
622 
623  /// \returns true if emitting a copy from \p Src to \p Dst is impossible.
624  bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src,
625  unsigned Size) const {
626  return copyCost(Dst, Src, Size) == std::numeric_limits<unsigned>::max();
627  }
628 
629  /// Get the cost of using \p ValMapping to decompose a register. This is
630  /// similar to ::copyCost, except for cases where multiple copy-like
631  /// operations need to be inserted. If the register is used as a source
632  /// operand and already has a bank assigned, \p CurBank is non-null.
633  virtual unsigned getBreakDownCost(const ValueMapping &ValMapping,
634  const RegisterBank *CurBank = nullptr) const {
636  }
637 
638  /// Constrain the (possibly generic) virtual register \p Reg to \p RC.
639  ///
640  /// \pre \p Reg is a virtual register that either has a bank or a class.
641  /// \returns The constrained register class, or nullptr if there is none.
642  /// \note This is a generic variant of MachineRegisterInfo::constrainRegClass
643  /// \note Use MachineRegisterInfo::constrainRegAttrs instead for any non-isel
644  /// purpose, including non-select passes of GlobalISel
645  static const TargetRegisterClass *
648 
649  /// Identifier used when the related instruction mapping instance
650  /// is generated by target independent code.
651  /// Make sure not to use that identifier to avoid possible collision.
652  static const unsigned DefaultMappingID;
653 
654  /// Identifier used when the related instruction mapping instance
655  /// is generated by the default constructor.
656  /// Make sure not to use that identifier.
657  static const unsigned InvalidMappingID;
658 
659  /// Get the mapping of the different operands of \p MI
660  /// on the register bank.
661  /// This mapping should be the direct translation of \p MI.
662  /// In other words, when \p MI is mapped with the returned mapping,
663  /// only the register banks of the operands of \p MI need to be updated.
664  /// In particular, neither the opcode nor the type of \p MI needs to be
665  /// updated for this direct mapping.
666  ///
667  /// The target independent implementation gives a mapping based on
668  /// the register classes for the target specific opcode.
669  /// It uses the ID RegisterBankInfo::DefaultMappingID for that mapping.
670  /// Make sure you do not use that ID for the alternative mapping
671  /// for MI. See getInstrAlternativeMappings for the alternative
672  /// mappings.
673  ///
674  /// For instance, if \p MI is a vector add, the mapping should
675  /// not be a scalarization of the add.
676  ///
677  /// \post returnedVal.verify(MI).
678  ///
679  /// \note If returnedVal does not verify MI, this would probably mean
680  /// that the target does not support that instruction.
681  virtual const InstructionMapping &
682  getInstrMapping(const MachineInstr &MI) const;
683 
684  /// Get the alternative mappings for \p MI.
685  /// Alternative in the sense different from getInstrMapping.
686  virtual InstructionMappings
688 
689  /// Get the possible mapping for \p MI.
690  /// A mapping defines where the different operands may live and at what cost.
691  /// For instance, let us consider:
692  /// v0(16) = G_ADD <2 x i8> v1, v2
693  /// The possible mapping could be:
694  ///
695  /// {/*ID*/VectorAdd, /*Cost*/1, /*v0*/{(0xFFFF, VPR)}, /*v1*/{(0xFFFF, VPR)},
696  /// /*v2*/{(0xFFFF, VPR)}}
697  /// {/*ID*/ScalarAddx2, /*Cost*/2, /*v0*/{(0x00FF, GPR),(0xFF00, GPR)},
698  /// /*v1*/{(0x00FF, GPR),(0xFF00, GPR)},
699  /// /*v2*/{(0x00FF, GPR),(0xFF00, GPR)}}
700  ///
701  /// \note The first alternative of the returned mapping should be the
702  /// direct translation of \p MI current form.
703  ///
704  /// \post !returnedVal.empty().
706 
707  /// Apply \p OpdMapper.getInstrMapping() to \p OpdMapper.getMI().
708  /// After this call \p OpdMapper.getMI() may not be valid anymore.
709  /// \p OpdMapper.getInstrMapping().getID() carries the information of
710  /// what has been chosen to map \p OpdMapper.getMI(). This ID is set
711  /// by the various getInstrXXXMapping method.
712  ///
713  /// Therefore, getting the mapping and applying it should be kept in
714  /// sync.
715  void applyMapping(const OperandsMapper &OpdMapper) const {
716  // The only mapping we know how to handle is the default mapping.
717  if (OpdMapper.getInstrMapping().getID() == DefaultMappingID)
718  return applyDefaultMapping(OpdMapper);
719  // For other mapping, the target needs to do the right thing.
720  // If that means calling applyDefaultMapping, fine, but this
721  // must be explicitly stated.
722  applyMappingImpl(OpdMapper);
723  }
724 
725  /// Get the size in bits of \p Reg.
726  /// Utility method to get the size of any registers. Unlike
727  /// MachineRegisterInfo::getSize, the register does not need to be a
728  /// virtual register.
729  ///
730  /// \pre \p Reg != 0 (NoRegister).
732  const TargetRegisterInfo &TRI) const;
733 
734  /// Check that information hold by this instance make sense for the
735  /// given \p TRI.
736  ///
737  /// \note This method does not check anything when assertions are disabled.
738  ///
739  /// \return True is the check was successful.
740  bool verify(const TargetRegisterInfo &TRI) const;
741 };
742 
743 inline raw_ostream &
745  const RegisterBankInfo::PartialMapping &PartMapping) {
746  PartMapping.print(OS);
747  return OS;
748 }
749 
750 inline raw_ostream &
752  ValMapping.print(OS);
753  return OS;
754 }
755 
756 inline raw_ostream &
758  const RegisterBankInfo::InstructionMapping &InstrMapping) {
759  InstrMapping.print(OS);
760  return OS;
761 }
762 
763 inline raw_ostream &
765  OpdMapper.print(OS, /*ForDebug*/ false);
766  return OS;
767 }
768 
769 /// Hashing function for PartialMapping.
770 /// It is required for the hashing of ValueMapping.
771 hash_code hash_value(const RegisterBankInfo::PartialMapping &PartMapping);
772 
773 } // end namespace llvm
774 
775 #endif // LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::RegisterBankInfo::ValueMapping::dump
void dump() const
Print this on dbgs() stream.
Definition: RegisterBankInfo.cpp:578
llvm::RegisterBankInfo::getInstrMappingImpl
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
Definition: RegisterBankInfo.cpp:162
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::RegisterBankInfo::PartialMapping::getHighBitIdx
unsigned getHighBitIdx() const
Definition: RegisterBankInfo.h:71
llvm::RegisterBankInfo::verify
bool verify(const TargetRegisterInfo &TRI) const
Check that information hold by this instance make sense for the given TRI.
Definition: RegisterBankInfo.cpp:69
llvm::RegisterBankInfo::OperandsMapper::getMRI
MachineRegisterInfo & getMRI() const
The MachineRegisterInfo we used to realize the mapping.
Definition: RegisterBankInfo.h:335
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::RegisterBankInfo::InstructionMapping::verify
bool verify(const MachineInstr &MI) const
Verifiy that this mapping makes sense for MI.
Definition: RegisterBankInfo.cpp:595
llvm::RegisterBankInfo::getRegBank
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
Definition: RegisterBankInfo.h:432
ErrorHandling.h
llvm::RegisterBankInfo::applyDefaultMapping
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
Definition: RegisterBankInfo.cpp:438
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
DenseMap.h
llvm::RegisterBankInfo::ValueMapping::isValid
bool isValid() const
Check if this ValueMapping is valid.
Definition: RegisterBankInfo.h:171
llvm::RegisterBankInfo::OperandsMapper::getInstrMapping
const InstructionMapping & getInstrMapping() const
The final mapping of the instruction.
Definition: RegisterBankInfo.h:332
Hashing.h
llvm::RegisterBankInfo::InstructionMapping::isValid
bool isValid() const
Check whether this object is valid.
Definition: RegisterBankInfo.h:254
llvm::hash_value
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4827
llvm::RegisterBankInfo::PhysRegMinimalRCs
DenseMap< unsigned, const TargetRegisterClass * > PhysRegMinimalRCs
Getting the minimal register class of a physreg is expensive.
Definition: RegisterBankInfo.h:415
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::RegisterBankInfo::getValueMapping
const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
The most common ValueMapping consists of a single PartialMapping.
Definition: RegisterBankInfo.cpp:297
llvm::RegisterBankInfo::ValueMapping::verify
bool verify(unsigned MeaningfulBitWidth) const
Verify that this mapping makes sense for a value of MeaningfulBitWidth.
Definition: RegisterBankInfo.cpp:548
llvm::RegisterBankInfo::ValueMapping::BreakDown
const PartialMapping * BreakDown
How the value is broken down between the different register banks.
Definition: RegisterBankInfo.h:147
llvm::RegisterBankInfo::InstructionMapping::getID
unsigned getID() const
Get the ID.
Definition: RegisterBankInfo.h:231
llvm::RegisterBankInfo::ValueMapping::partsAllUniform
bool partsAllUniform() const
Definition: RegisterBankInfo.cpp:535
llvm::RegisterBankInfo::InstructionMapping::InstructionMapping
InstructionMapping()=default
Default constructor.
llvm::RegisterBankInfo::getBreakDownCost
virtual unsigned getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const
Get the cost of using ValMapping to decompose a register.
Definition: RegisterBankInfo.h:633
llvm::RegisterBankInfo::MapOfValueMappings
DenseMap< unsigned, std::unique_ptr< const ValueMapping > > MapOfValueMappings
Keep dynamically allocated ValueMapping in a separate map.
Definition: RegisterBankInfo.h:401
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::RegisterBankInfo::PartialMapping::verify
bool verify() const
Check that the Mask is compatible with the RegBank.
Definition: RegisterBankInfo.cpp:518
llvm::RegisterBankInfo::MapOfInstructionMappings
DenseMap< unsigned, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
Keep dynamically allocated InstructionMapping in a separate map.
Definition: RegisterBankInfo.h:411
llvm::RegisterBankInfo::applyMapping
void applyMapping(const OperandsMapper &OpdMapper) const
Apply OpdMapper.getInstrMapping() to OpdMapper.getMI().
Definition: RegisterBankInfo.h:715
llvm::RegisterBankInfo::PartialMapping
Helper struct that represents how a value is partially mapped into a register.
Definition: RegisterBankInfo.h:48
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::RegisterBankInfo::getInstrPossibleMappings
InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const
Get the possible mapping for MI.
Definition: RegisterBankInfo.cpp:414
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::RegisterBankInfo::InvalidMappingID
static const unsigned InvalidMappingID
Identifier used when the related instruction mapping instance is generated by the default constructor...
Definition: RegisterBankInfo.h:657
llvm::RegisterBankInfo::PartialMapping::dump
void dump() const
Print this partial mapping on dbgs() stream.
Definition: RegisterBankInfo.cpp:512
llvm::RegisterBankInfo::MapOfPartialMappings
DenseMap< unsigned, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
Keep dynamically allocated PartialMapping in a separate map.
Definition: RegisterBankInfo.h:396
llvm::RegisterBankInfo::OperandsMapper::print
void print(raw_ostream &OS, bool ForDebug=false) const
Print this operands mapper on OS stream.
Definition: RegisterBankInfo.cpp:761
llvm::RegisterBankInfo::InstructionMapping::InstructionMapping
InstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands)
Constructor for the mapping of an instruction.
Definition: RegisterBankInfo.h:216
llvm::RegisterBankInfo::ValueMapping::ValueMapping
ValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns)
Initialize a ValueMapping with the given parameter.
Definition: RegisterBankInfo.h:159
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:230
llvm::RegisterBankInfo::NumRegBanks
unsigned NumRegBanks
Total number of register banks.
Definition: RegisterBankInfo.h:391
llvm::RegisterBankInfo::RegBanks
RegisterBank ** RegBanks
Hold the set of supported register banks.
Definition: RegisterBankInfo.h:388
llvm::RegisterBankInfo::InstructionMapping::setOperandsMapping
void setOperandsMapping(const ValueMapping *OpdsMapping)
Set the mapping for all the operands.
Definition: RegisterBankInfo.h:248
llvm::RegisterBankInfo::OperandsMapper::setVRegs
void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, Register NewVReg)
Set the virtual register of the PartialMapIdx-th partial mapping of the OpIdx-th operand to NewVReg.
Definition: RegisterBankInfo.cpp:717
llvm::RegisterBankInfo::InstructionMapping::dump
void dump() const
Print this on dbgs() stream.
Definition: RegisterBankInfo.cpp:632
llvm::RegisterBankInfo::getInstrAlternativeMappings
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
Definition: RegisterBankInfo.cpp:433
llvm::RegisterBankInfo::getSizeInBits
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
Definition: RegisterBankInfo.cpp:493
llvm::RegisterBankInfo::constrainGenericRegister
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
Definition: RegisterBankInfo.cpp:132
LowLevelTypeImpl.h
llvm::RegisterBankInfo::OperandsMapper
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
Definition: RegisterBankInfo.h:280
llvm::RegisterBankInfo::OperandsMapper::dump
void dump() const
Print this operands mapper on dbgs() stream.
Definition: RegisterBankInfo.cpp:755
llvm::RegisterBankInfo::InstructionMapping::print
void print(raw_ostream &OS) const
Print this on OS;.
Definition: RegisterBankInfo.cpp:638
llvm::RegisterBankInfo::~RegisterBankInfo
virtual ~RegisterBankInfo()=default
llvm::RegisterBankInfo::PartialMapping::StartIdx
unsigned StartIdx
Number of bits at which this partial mapping starts in the original value.
Definition: RegisterBankInfo.h:52
llvm::RegisterBankInfo::getNumRegBanks
unsigned getNumRegBanks() const
Get the total number of register banks.
Definition: RegisterBankInfo.h:589
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::RegisterBankInfo::PartialMapping::PartialMapping
PartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank)
Provide a shortcut for quickly building PartialMapping.
Definition: RegisterBankInfo.h:65
llvm::RegisterBankInfo::OperandsMapper::getVRegs
iterator_range< SmallVectorImpl< Register >::const_iterator > getVRegs(unsigned OpIdx, bool ForDebug=false) const
Get all the virtual registers required to map the OpIdx-th operand of the instruction.
Definition: RegisterBankInfo.cpp:732
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::RegisterBankInfo::InstructionMapping
Helper class that represents how the value of an instruction may be mapped and what is the related co...
Definition: RegisterBankInfo.h:189
llvm::RegisterBankInfo::PartialMapping::PartialMapping
PartialMapping()=default
llvm::RegisterBankInfo::InstructionMapping::getNumOperands
unsigned getNumOperands() const
Get the number of operands.
Definition: RegisterBankInfo.h:234
llvm::DenseMap
Definition: DenseMap.h:714
llvm::RegisterBankInfo::DefaultMappingID
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
Definition: RegisterBankInfo.h:652
llvm::RegisterBankInfo::cannotCopy
bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src, unsigned Size) const
Definition: RegisterBankInfo.h:624
llvm::RegisterBankInfo::getOperandsMapping
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
Definition: RegisterBankInfo.cpp:332
llvm::RegisterBankInfo::RegisterBankInfo
RegisterBankInfo()
This constructor is meaningless.
Definition: RegisterBankInfo.h:427
llvm::SmallVectorImpl::const_iterator
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:563
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::RegisterBankInfo::ValueMapping::ValueMapping
ValueMapping()
The default constructor creates an invalid (isValid() == false) instance.
Definition: RegisterBankInfo.h:154
llvm::RegisterBankInfo::ValueMapping::end
const PartialMapping * end() const
Definition: RegisterBankInfo.h:164
llvm::RegisterBankInfo::OperandsMapper::getMI
MachineInstr & getMI() const
Definition: RegisterBankInfo.h:329
llvm::RegisterBankInfo::InstructionMapping::getCost
unsigned getCost() const
Get the cost.
Definition: RegisterBankInfo.h:228
iterator_range.h
llvm::RegisterBankInfo::PartialMapping::RegBank
const RegisterBank * RegBank
Register bank where the partial value lives.
Definition: RegisterBankInfo.h:60
llvm::RegisterBankInfo::OperandsMapper::createVRegs
void createVRegs(unsigned OpIdx)
Create as many new virtual registers as needed for the mapping of the OpIdx-th operand.
Definition: RegisterBankInfo.cpp:697
llvm::RegisterBankInfo::getPartialMapping
const PartialMapping & getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Get the uniquely generated PartialMapping for the given arguments.
Definition: RegisterBankInfo.cpp:280
llvm::RegisterBankInfo::getInstructionMapping
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
Definition: RegisterBankInfo.h:526
llvm::RegisterBankInfo::ValueMapping
Helper struct that represents how a value is mapped through different register banks.
Definition: RegisterBankInfo.h:145
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::RegisterBankInfo::InstructionMapping::getOperandMapping
const ValueMapping & getOperandMapping(unsigned i) const
Get the value mapping of the ith operand.
Definition: RegisterBankInfo.h:239
llvm::RegisterBankInfo::ValueMapping::print
void print(raw_ostream &OS) const
Print this on OS;.
Definition: RegisterBankInfo.cpp:584
llvm::RegisterBankInfo::PartialMapping::Length
unsigned Length
Length of this mapping in bits.
Definition: RegisterBankInfo.h:57
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::RegisterBankInfo::getRegBankFromRegClass
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const
Get a register bank that covers RC.
Definition: RegisterBankInfo.h:604
llvm::RegisterBankInfo::getRegBank
const RegisterBank & getRegBank(unsigned ID) const
Get the register bank identified by ID.
Definition: RegisterBankInfo.h:576
llvm::RegisterBankInfo::getInvalidInstructionMapping
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
Definition: RegisterBankInfo.h:534
llvm::RegisterBankInfo::copyCost
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
Definition: RegisterBankInfo.h:614
llvm::RegisterBankInfo::getInstrMapping
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
Definition: RegisterBankInfo.cpp:406
llvm::RegisterBankInfo::ValueMapping::begin
const PartialMapping * begin() const
Iterators through the PartialMappings.
Definition: RegisterBankInfo.h:163
llvm::RegisterBankInfo::OperandsMapper::OperandsMapper
OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping, MachineRegisterInfo &MRI)
Create an OperandsMapper that will hold the information to apply InstrMapping to MI.
Definition: RegisterBankInfo.cpp:651
llvm::RegisterBankInfo::getRegBankFromConstraints
const RegisterBank * getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const
Get the register bank for the OpIdx-th operand of MI form the encoding constraints,...
Definition: RegisterBankInfo.cpp:112
llvm::RegisterBankInfo::ValueMapping::NumBreakDowns
unsigned NumBreakDowns
Number of partial mapping to break down this value.
Definition: RegisterBankInfo.h:150
SmallVector.h
llvm::SmallVectorImpl::iterator
typename SuperClass::iterator iterator
Definition: SmallVector.h:562
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::RegisterBankInfo::PartialMapping::print
void print(raw_ostream &OS) const
Print this partial mapping on OS;.
Definition: RegisterBankInfo.cpp:527
llvm::RegisterBankInfo::getMinimalPhysRegClass
const TargetRegisterClass & getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const
Get the MinimalPhysRegClass for Reg.
Definition: RegisterBankInfo.cpp:101
Register.h
llvm::RegisterBankInfo::MapOfOperandsMappings
DenseMap< unsigned, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
Keep dynamically allocated array of ValueMapping in a separate map.
Definition: RegisterBankInfo.h:406
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::RegisterBankInfo::applyMappingImpl
virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const
See ::applyMapping.
Definition: RegisterBankInfo.h:568
llvm::LLT
Definition: LowLevelTypeImpl.h:40