LLVM  14.0.0git
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llvm::RegisterBankInfo Class Reference

Holds all the information related to register banks. More...

#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"

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Classes

class  InstructionMapping
 Helper class that represents how the value of an instruction may be mapped and what is the related cost of such mapping. More...
 
class  OperandsMapper
 Helper class used to get/create the virtual registers that will be used to replace the MachineOperand when applying a mapping. More...
 
struct  PartialMapping
 Helper struct that represents how a value is partially mapped into a register. More...
 
struct  ValueMapping
 Helper struct that represents how a value is mapped through different register banks. More...
 

Public Types

using InstructionMappings = SmallVector< const InstructionMapping *, 4 >
 Convenient type to represent the alternatives for mapping an instruction. More...
 

Public Member Functions

const RegisterBankgetRegBankFromConstraints (const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const
 Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any. More...
 
virtual void applyMappingImpl (const OperandsMapper &OpdMapper) const
 See ::applyMapping. More...
 
virtual ~RegisterBankInfo ()=default
 
const RegisterBankgetRegBank (unsigned ID) const
 Get the register bank identified by ID. More...
 
const RegisterBankgetRegBank (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
 Get the register bank of Reg. More...
 
unsigned getNumRegBanks () const
 Get the total number of register banks. More...
 
virtual const RegisterBankgetRegBankFromRegClass (const TargetRegisterClass &RC, LLT Ty) const
 Get a register bank that covers RC. More...
 
virtual unsigned copyCost (const RegisterBank &A, const RegisterBank &B, unsigned Size) const
 Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B. More...
 
bool cannotCopy (const RegisterBank &Dst, const RegisterBank &Src, unsigned Size) const
 
virtual unsigned getBreakDownCost (const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const
 Get the cost of using ValMapping to decompose a register. More...
 
virtual const InstructionMappinggetInstrMapping (const MachineInstr &MI) const
 Get the mapping of the different operands of MI on the register bank. More...
 
virtual InstructionMappings getInstrAlternativeMappings (const MachineInstr &MI) const
 Get the alternative mappings for MI. More...
 
InstructionMappings getInstrPossibleMappings (const MachineInstr &MI) const
 Get the possible mapping for MI. More...
 
void applyMapping (const OperandsMapper &OpdMapper) const
 Apply OpdMapper.getInstrMapping() to OpdMapper.getMI(). More...
 
unsigned getSizeInBits (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
 Get the size in bits of Reg. More...
 
bool verify (const TargetRegisterInfo &TRI) const
 Check that information hold by this instance make sense for the given TRI. More...
 

Static Public Member Functions

static void applyDefaultMapping (const OperandsMapper &OpdMapper)
 Helper method to apply something that is like the default mapping. More...
 
static const TargetRegisterClassconstrainGenericRegister (Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
 Constrain the (possibly generic) virtual register Reg to RC. More...
 

Static Public Attributes

static const unsigned DefaultMappingID = UINT_MAX
 Identifier used when the related instruction mapping instance is generated by target independent code. More...
 
static const unsigned InvalidMappingID = UINT_MAX - 1
 Identifier used when the related instruction mapping instance is generated by the default constructor. More...
 

Protected Member Functions

 RegisterBankInfo (RegisterBank **RegBanks, unsigned NumRegBanks)
 Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances. More...
 
 RegisterBankInfo ()
 This constructor is meaningless. More...
 
RegisterBankgetRegBank (unsigned ID)
 Get the register bank identified by ID. More...
 
const TargetRegisterClassgetMinimalPhysRegClass (Register Reg, const TargetRegisterInfo &TRI) const
 Get the MinimalPhysRegClass for Reg. More...
 
const InstructionMappinggetInstrMappingImpl (const MachineInstr &MI) const
 Try to get the mapping of MI. More...
 
const PartialMappinggetPartialMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
 Get the uniquely generated PartialMapping for the given arguments. More...
 
Methods to get a uniquely generated ValueMapping.
const ValueMappinggetValueMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
 The most common ValueMapping consists of a single PartialMapping. More...
 
const ValueMappinggetValueMapping (const PartialMapping *BreakDown, unsigned NumBreakDowns) const
 Get the ValueMapping for the given arguments. More...
 
Methods to get a uniquely generated array of ValueMapping.
template<typename Iterator >
const ValueMappinggetOperandsMapping (Iterator Begin, Iterator End) const
 Get the uniquely generated array of ValueMapping for the elements of between Begin and End. More...
 
const ValueMappinggetOperandsMapping (const SmallVectorImpl< const ValueMapping * > &OpdsMapping) const
 Get the uniquely generated array of ValueMapping for the elements of OpdsMapping. More...
 
const ValueMappinggetOperandsMapping (std::initializer_list< const ValueMapping * > OpdsMapping) const
 Get the uniquely generated array of ValueMapping for the given arguments. More...
 

Protected Attributes

RegisterBank ** RegBanks
 Hold the set of supported register banks. More...
 
unsigned NumRegBanks
 Total number of register banks. More...
 
DenseMap< unsigned, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
 Keep dynamically allocated PartialMapping in a separate map. More...
 
DenseMap< unsigned, std::unique_ptr< const ValueMapping > > MapOfValueMappings
 Keep dynamically allocated ValueMapping in a separate map. More...
 
DenseMap< unsigned, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
 Keep dynamically allocated array of ValueMapping in a separate map. More...
 
DenseMap< unsigned, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
 Keep dynamically allocated InstructionMapping in a separate map. More...
 
DenseMap< unsigned, const TargetRegisterClass * > PhysRegMinimalRCs
 Getting the minimal register class of a physreg is expensive. More...
 

Methods to get a uniquely generated InstructionMapping.

const InstructionMappinggetInstructionMapping (unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
 Method to get a uniquely generated InstructionMapping. More...
 
const InstructionMappinggetInvalidInstructionMapping () const
 Method to get a uniquely generated invalid InstructionMapping. More...
 

Detailed Description

Holds all the information related to register banks.

Definition at line 39 of file RegisterBankInfo.h.

Member Typedef Documentation

◆ InstructionMappings

Convenient type to represent the alternatives for mapping an instruction.

Todo:
When we move to TableGen this should be an array ref.

Definition at line 276 of file RegisterBankInfo.h.

Constructor & Destructor Documentation

◆ RegisterBankInfo() [1/2]

RegisterBankInfo::RegisterBankInfo ( RegisterBank **  RegBanks,
unsigned  NumRegBanks 
)
protected

Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.

Definition at line 58 of file RegisterBankInfo.cpp.

◆ RegisterBankInfo() [2/2]

llvm::RegisterBankInfo::RegisterBankInfo ( )
inlineprotected

This constructor is meaningless.

It just provides a default constructor that can be used at link time when GlobalISel is not built. That way, targets can still inherit from this class without doing crazy gymnastic to avoid link time failures.

Note
That works because the constructor is inlined.

Definition at line 427 of file RegisterBankInfo.h.

References llvm_unreachable.

◆ ~RegisterBankInfo()

virtual llvm::RegisterBankInfo::~RegisterBankInfo ( )
virtualdefault

Member Function Documentation

◆ applyDefaultMapping()

void RegisterBankInfo::applyDefaultMapping ( const OperandsMapper OpdMapper)
static

Helper method to apply something that is like the default mapping.

Basically, that means that OpdMapper.getMI() is left untouched aside from the reassignment of the register operand that have been remapped.

The type of all the new registers that have been created by the mapper are properly remapped to the type of the original registers they replace. In other words, the semantic of the instruction does not change, only the register banks.

If the mapping of one of the operand spans several registers, this method will abort as this is not like a default mapping anymore.

Precondition
For OpIdx in {0..OpdMapper.getMI().getNumOperands()) the range OpdMapper.getVRegs(OpIdx) is empty or of size 1.

Definition at line 438 of file RegisterBankInfo.cpp.

References assert(), llvm::iterator_range< IteratorT >::begin(), llvm::dbgs(), llvm::iterator_range< IteratorT >::empty(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::RegisterBankInfo::InstructionMapping::getNumOperands(), llvm::MachineOperand::getReg(), llvm::LLT::getSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::RegisterBankInfo::OperandsMapper::getVRegs(), llvm::MachineOperand::isReg(), LLVM_DEBUG, MI, MRI, llvm::RegisterBankInfo::ValueMapping::NumBreakDowns, llvm::printReg(), llvm::MachineOperand::setReg(), and llvm::MachineRegisterInfo::setType().

Referenced by applyMapping(), llvm::AMDGPURegisterBankInfo::applyMappingBFE(), llvm::AMDGPURegisterBankInfo::applyMappingImage(), llvm::MipsRegisterBankInfo::applyMappingImpl(), llvm::X86RegisterBankInfo::applyMappingImpl(), and llvm::AMDGPURegisterBankInfo::applyMappingImpl().

◆ applyMapping()

void llvm::RegisterBankInfo::applyMapping ( const OperandsMapper OpdMapper) const
inline

Apply OpdMapper.getInstrMapping() to OpdMapper.getMI().

After this call OpdMapper.getMI() may not be valid anymore. OpdMapper.getInstrMapping().getID() carries the information of what has been chosen to map OpdMapper.getMI(). This ID is set by the various getInstrXXXMapping method.

Therefore, getting the mapping and applying it should be kept in sync.

Definition at line 715 of file RegisterBankInfo.h.

References applyDefaultMapping(), applyMappingImpl(), DefaultMappingID, llvm::RegisterBankInfo::InstructionMapping::getID(), and llvm::RegisterBankInfo::OperandsMapper::getInstrMapping().

◆ applyMappingImpl()

virtual void llvm::RegisterBankInfo::applyMappingImpl ( const OperandsMapper OpdMapper) const
inlinevirtual

See ::applyMapping.

Reimplemented in llvm::AMDGPURegisterBankInfo, llvm::X86RegisterBankInfo, and llvm::MipsRegisterBankInfo.

Definition at line 568 of file RegisterBankInfo.h.

References llvm_unreachable.

Referenced by applyMapping().

◆ cannotCopy()

bool llvm::RegisterBankInfo::cannotCopy ( const RegisterBank Dst,
const RegisterBank Src,
unsigned  Size 
) const
inline
Returns
true if emitting a copy from Src to Dst is impossible.

Definition at line 624 of file RegisterBankInfo.h.

References copyCost(), llvm::max(), and llvm::Check::Size.

Referenced by llvm::AMDGPURegisterBankInfo::getInstrMapping(), and getInstrMappingImpl().

◆ constrainGenericRegister()

const TargetRegisterClass * RegisterBankInfo::constrainGenericRegister ( Register  Reg,
const TargetRegisterClass RC,
MachineRegisterInfo MRI 
)
static

Constrain the (possibly generic) virtual register Reg to RC.

Precondition
Reg is a virtual register that either has a bank or a class.
Returns
The constrained register class, or nullptr if there is none.
Note
This is a generic variant of MachineRegisterInfo::constrainRegClass
Use MachineRegisterInfo::constrainRegAttrs instead for any non-isel purpose, including non-select passes of GlobalISel

Definition at line 132 of file RegisterBankInfo.cpp.

References llvm::MachineRegisterInfo::constrainRegClass(), llvm::RegisterBank::covers(), llvm::MachineRegisterInfo::getRegClassOrRegBank(), MRI, Reg, and llvm::MachineRegisterInfo::setRegClass().

Referenced by llvm::AMDGPURegisterBankInfo::buildVCopy(), llvm::AMDGPURegisterBankInfo::constrainOpWithReadfirstlane(), llvm::constrainRegToClass(), copySubReg(), llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), and selectCopy().

◆ copyCost()

virtual unsigned llvm::RegisterBankInfo::copyCost ( const RegisterBank A,
const RegisterBank B,
unsigned  Size 
) const
inlinevirtual

Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.

Since register banks may cover different size, Size specifies what will be the size in bits that will be copied around.

Note
Since this is a copy, both registers have the same size.

Reimplemented in llvm::AMDGPURegisterBankInfo, and llvm::AArch64RegisterBankInfo.

Definition at line 614 of file RegisterBankInfo.h.

References B.

Referenced by cannotCopy(), llvm::AArch64RegisterBankInfo::copyCost(), and llvm::AMDGPURegisterBankInfo::copyCost().

◆ getBreakDownCost()

virtual unsigned llvm::RegisterBankInfo::getBreakDownCost ( const ValueMapping ValMapping,
const RegisterBank CurBank = nullptr 
) const
inlinevirtual

Get the cost of using ValMapping to decompose a register.

This is similar to ::copyCost, except for cases where multiple copy-like operations need to be inserted. If the register is used as a source operand and already has a bank assigned, CurBank is non-null.

Reimplemented in llvm::AMDGPURegisterBankInfo.

Definition at line 633 of file RegisterBankInfo.h.

References llvm::max().

◆ getInstrAlternativeMappings()

RegisterBankInfo::InstructionMappings RegisterBankInfo::getInstrAlternativeMappings ( const MachineInstr MI) const
virtual

◆ getInstrMapping()

const RegisterBankInfo::InstructionMapping & RegisterBankInfo::getInstrMapping ( const MachineInstr MI) const
virtual

Get the mapping of the different operands of MI on the register bank.

This mapping should be the direct translation of MI. In other words, when MI is mapped with the returned mapping, only the register banks of the operands of MI need to be updated. In particular, neither the opcode nor the type of MI needs to be updated for this direct mapping.

The target independent implementation gives a mapping based on the register classes for the target specific opcode. It uses the ID RegisterBankInfo::DefaultMappingID for that mapping. Make sure you do not use that ID for the alternative mapping for MI. See getInstrAlternativeMappings for the alternative mappings.

For instance, if MI is a vector add, the mapping should not be a scalarization of the add.

Postcondition
returnedVal.verify(MI).
Note
If returnedVal does not verify MI, this would probably mean that the target does not support that instruction.

Reimplemented in llvm::AMDGPURegisterBankInfo, llvm::AArch64RegisterBankInfo, llvm::X86RegisterBankInfo, llvm::M68kRegisterBankInfo, llvm::ARMRegisterBankInfo, and llvm::MipsRegisterBankInfo.

Definition at line 406 of file RegisterBankInfo.cpp.

References getInstrMappingImpl(), llvm::RegisterBankInfo::InstructionMapping::isValid(), llvm_unreachable, and MI.

Referenced by llvm::RegisterBankInfo::OperandsMapper::createVRegs(), getInstrPossibleMappings(), llvm::RegisterBankInfo::OperandsMapper::getVRegs(), llvm::RegisterBankInfo::OperandsMapper::print(), and llvm::RegisterBankInfo::OperandsMapper::setVRegs().

◆ getInstrMappingImpl()

const RegisterBankInfo::InstructionMapping & RegisterBankInfo::getInstrMappingImpl ( const MachineInstr MI) const
protected

Try to get the mapping of MI.

See getInstrMapping for more details on what a mapping represents.

Unlike getInstrMapping the returned InstructionMapping may be invalid (isValid() == false). This means that the target independent code is not smart enough to get the mapping of MI and thus, the target has to provide the information for MI.

This implementation is able to get the mapping of:

  • Target specific instructions by looking at the encoding constraints.
  • Any instruction if all the register operands have already been assigned a register, a register class, or a register bank.
  • Copies and phis if at least one of the operands has been assigned a register, a register class, or a register bank. In other words, this method will likely fail to find a mapping for any generic opcode that has not been lowered by target specific code.

Definition at line 162 of file RegisterBankInfo.cpp.

References assert(), cannotCopy(), DefaultMappingID, llvm::TargetSubtargetInfo::getInstrInfo(), getInstructionMapping(), getInvalidInstructionMapping(), getOperandsMapping(), llvm::MachineOperand::getReg(), getRegBank(), getRegBankFromConstraints(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), getSizeInBits(), llvm::MachineFunction::getSubtarget(), getValueMapping(), isCopyLike(), llvm::MachineOperand::isReg(), MI, MRI, Reg, llvm::Check::Size, TII, and TRI.

Referenced by llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::MipsRegisterBankInfo::getInstrMapping(), llvm::M68kRegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), and getInstrMapping().

◆ getInstrPossibleMappings()

RegisterBankInfo::InstructionMappings RegisterBankInfo::getInstrPossibleMappings ( const MachineInstr MI) const

Get the possible mapping for MI.

A mapping defines where the different operands may live and at what cost. For instance, let us consider: v0(16) = G_ADD <2 x i8> v1, v2 The possible mapping could be:

{/*ID*‍/VectorAdd, /*Cost*‍/1, /*v0*‍/{(0xFFFF, VPR)}, /*v1*‍/{(0xFFFF, VPR)}, /*v2*‍/{(0xFFFF, VPR)}} {/*ID*‍/ScalarAddx2, /*Cost*‍/2, /*v0*‍/{(0x00FF, GPR),(0xFF00, GPR)}, /*v1*‍/{(0x00FF, GPR),(0xFF00, GPR)}, /*v2*‍/{(0x00FF, GPR),(0xFF00, GPR)}}

Note
The first alternative of the returned mapping should be the direct translation of MI current form.
Postcondition
!returnedVal.empty().

Definition at line 414 of file RegisterBankInfo.cpp.

References llvm::append_range(), assert(), getInstrAlternativeMappings(), getInstrMapping(), and MI.

◆ getInstructionMapping()

const InstructionMapping& llvm::RegisterBankInfo::getInstructionMapping ( unsigned  ID,
unsigned  Cost,
const ValueMapping OperandsMapping,
unsigned  NumOperands 
) const
inline

◆ getInvalidInstructionMapping()

const InstructionMapping& llvm::RegisterBankInfo::getInvalidInstructionMapping ( ) const
inline

◆ getMinimalPhysRegClass()

const TargetRegisterClass & RegisterBankInfo::getMinimalPhysRegClass ( Register  Reg,
const TargetRegisterInfo TRI 
) const
protected

Get the MinimalPhysRegClass for Reg.

Precondition
Reg is a physical register.

Definition at line 101 of file RegisterBankInfo.cpp.

References assert(), llvm::TargetRegisterInfo::getMinimalPhysRegClass(), llvm::Register::isPhysicalRegister(), PhysRegMinimalRCs, Reg, and TRI.

Referenced by getRegBank(), and getSizeInBits().

◆ getNumRegBanks()

unsigned llvm::RegisterBankInfo::getNumRegBanks ( ) const
inline

Get the total number of register banks.

Definition at line 589 of file RegisterBankInfo.h.

References NumRegBanks.

Referenced by getRegBank().

◆ getOperandsMapping() [1/3]

const RegisterBankInfo::ValueMapping * RegisterBankInfo::getOperandsMapping ( const SmallVectorImpl< const ValueMapping * > &  OpdsMapping) const
protected

Get the uniquely generated array of ValueMapping for the elements of OpdsMapping.

Elements of OpdsMapping that are nullptr will be replaced by invalid ValueMapping (ValueMapping::isValid == false).

Definition at line 361 of file RegisterBankInfo.cpp.

References getOperandsMapping().

◆ getOperandsMapping() [2/3]

template<typename Iterator >
const RegisterBankInfo::ValueMapping * RegisterBankInfo::getOperandsMapping ( Iterator  Begin,
Iterator  End 
) const
protected

◆ getOperandsMapping() [3/3]

const ValueMapping* llvm::RegisterBankInfo::getOperandsMapping ( std::initializer_list< const ValueMapping * >  OpdsMapping) const
protected

Get the uniquely generated array of ValueMapping for the given arguments.

Arguments that are nullptr will be replaced by invalid ValueMapping (ValueMapping::isValid == false).

◆ getPartialMapping()

const RegisterBankInfo::PartialMapping & RegisterBankInfo::getPartialMapping ( unsigned  StartIdx,
unsigned  Length,
const RegisterBank RegBank 
) const
protected

Get the uniquely generated PartialMapping for the given arguments.

Definition at line 280 of file RegisterBankInfo.cpp.

References hashPartialMapping(), and MapOfPartialMappings.

Referenced by getValueMapping().

◆ getRegBank() [1/3]

const RegisterBank * RegisterBankInfo::getRegBank ( Register  Reg,
const MachineRegisterInfo MRI,
const TargetRegisterInfo TRI 
) const

Get the register bank of Reg.

If Reg has not been assigned a register, a register class, or a register bank, then this returns nullptr.

Precondition
Reg != 0 (NoRegister)

Definition at line 83 of file RegisterBankInfo.cpp.

References assert(), llvm::PointerUnion< PTs >::dyn_cast(), getMinimalPhysRegClass(), getRegBankFromRegClass(), llvm::MachineRegisterInfo::getRegClassOrRegBank(), llvm::MachineRegisterInfo::getType(), llvm::Register::isPhysicalRegister(), MRI, Reg, and TRI.

◆ getRegBank() [2/3]

RegisterBank& llvm::RegisterBankInfo::getRegBank ( unsigned  ID)
inlineprotected

Get the register bank identified by ID.

Definition at line 432 of file RegisterBankInfo.h.

References assert(), getNumRegBanks(), and RegBanks.

Referenced by llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo(), llvm::AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(), llvm::AMDGPURegisterBankInfo::applyMappingDynStackAlloc(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::ARMRegisterBankInfo::ARMRegisterBankInfo(), llvm::AMDGPURegisterBankInfo::collectWaterfallOperands(), llvm::AMDGPURegisterBankInfo::constrainOpWithReadfirstlane(), llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), llvm::InstructionSelector::executeMatchTable(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(), getInstrMappingImpl(), llvm::AMDGPURegisterBankInfo::getMappingType(), llvm::CombinerHelper::getRegBank(), getRegBank(), llvm::MipsRegisterBankInfo::getRegBankFromRegClass(), llvm::ARMRegisterBankInfo::getRegBankFromRegClass(), llvm::M68kRegisterBankInfo::getRegBankFromRegClass(), llvm::X86RegisterBankInfo::getRegBankFromRegClass(), llvm::AArch64RegisterBankInfo::getRegBankFromRegClass(), llvm::AMDGPURegisterBankInfo::getRegBankID(), getRegClassesForCopy(), llvm::AMDGPURegisterBankInfo::getValueMappingForPtr(), llvm::AMDGPURegisterBankInfo::isSALUMapping(), selectCopy(), selectMergeValues(), selectUnmergeValues(), setBufferOffsets(), llvm::MipsRegisterBankInfo::setRegBank(), llvm::AMDGPURegisterBankInfo::split64BitValueForMapping(), unsupportedBinOp(), and llvm::X86RegisterBankInfo::X86RegisterBankInfo().

◆ getRegBank() [3/3]

const RegisterBank& llvm::RegisterBankInfo::getRegBank ( unsigned  ID) const
inline

Get the register bank identified by ID.

Definition at line 576 of file RegisterBankInfo.h.

References getRegBank().

◆ getRegBankFromConstraints()

const RegisterBank * RegisterBankInfo::getRegBankFromConstraints ( const MachineInstr MI,
unsigned  OpIdx,
const TargetInstrInfo TII,
const MachineRegisterInfo MRI 
) const

Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any.

Returns
A register bank that covers the register class of the related encoding constraints or nullptr if MI did not provide enough information to deduce it.

Definition at line 112 of file RegisterBankInfo.cpp.

References assert(), llvm::RegisterBank::covers(), getRegBankFromRegClass(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), llvm::MachineRegisterInfo::getType(), MI, MRI, Reg, TII, and TRI.

Referenced by getInstrMappingImpl().

◆ getRegBankFromRegClass()

virtual const RegisterBank& llvm::RegisterBankInfo::getRegBankFromRegClass ( const TargetRegisterClass RC,
LLT  Ty 
) const
inlinevirtual

Get a register bank that covers RC.

Precondition
RC is a user-defined register class (as opposed as one generated by TableGen).
Note
The mapping RC -> RegBank could be built while adding the coverage for the register banks. However, we do not do it, because, at least for now, we only need this information for register classes that are used in the description of instruction. In other words, there are just a handful of them and we do not want to waste space.
Todo:
This should be TableGen'ed.

Reimplemented in llvm::AMDGPURegisterBankInfo, llvm::AArch64RegisterBankInfo, llvm::X86RegisterBankInfo, llvm::M68kRegisterBankInfo, llvm::ARMRegisterBankInfo, and llvm::MipsRegisterBankInfo.

Definition at line 604 of file RegisterBankInfo.h.

References llvm_unreachable.

Referenced by llvm::InstructionSelector::executeMatchTable(), getRegBank(), and getRegBankFromConstraints().

◆ getSizeInBits()

unsigned RegisterBankInfo::getSizeInBits ( Register  Reg,
const MachineRegisterInfo MRI,
const TargetRegisterInfo TRI 
) const

◆ getValueMapping() [1/2]

const RegisterBankInfo::ValueMapping & RegisterBankInfo::getValueMapping ( const PartialMapping BreakDown,
unsigned  NumBreakDowns 
) const
protected

Get the ValueMapping for the given arguments.

Definition at line 314 of file RegisterBankInfo.cpp.

References hashValueMapping(), and MapOfValueMappings.

◆ getValueMapping() [2/2]

const RegisterBankInfo::ValueMapping & RegisterBankInfo::getValueMapping ( unsigned  StartIdx,
unsigned  Length,
const RegisterBank RegBank 
) const
protected

The most common ValueMapping consists of a single PartialMapping.

Feature a method for that.

Definition at line 297 of file RegisterBankInfo.cpp.

References getPartialMapping().

Referenced by llvm::AMDGPURegisterBankInfo::getInstrMapping(), and getInstrMappingImpl().

◆ verify()

bool RegisterBankInfo::verify ( const TargetRegisterInfo TRI) const

Check that information hold by this instance make sense for the given TRI.

Note
This method does not check anything when assertions are disabled.
Returns
True is the check was successful.

Definition at line 69 of file RegisterBankInfo.cpp.

Referenced by llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo().

Member Data Documentation

◆ DefaultMappingID

const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX
static

Identifier used when the related instruction mapping instance is generated by target independent code.

Make sure not to use that identifier to avoid possible collision.

Definition at line 652 of file RegisterBankInfo.h.

Referenced by applyMapping(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::MipsRegisterBankInfo::getInstrMapping(), llvm::M68kRegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), llvm::AArch64RegisterBankInfo::getInstrMapping(), and getInstrMappingImpl().

◆ InvalidMappingID

const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1
static

Identifier used when the related instruction mapping instance is generated by the default constructor.

Make sure not to use that identifier.

Definition at line 657 of file RegisterBankInfo.h.

Referenced by llvm::RegisterBankInfo::InstructionMapping::isValid().

◆ MapOfInstructionMappings

DenseMap<unsigned, std::unique_ptr<const InstructionMapping> > llvm::RegisterBankInfo::MapOfInstructionMappings
mutableprotected

Keep dynamically allocated InstructionMapping in a separate map.

This shouldn't be needed when everything gets TableGen'ed.

Definition at line 411 of file RegisterBankInfo.h.

◆ MapOfOperandsMappings

DenseMap<unsigned, std::unique_ptr<ValueMapping[]> > llvm::RegisterBankInfo::MapOfOperandsMappings
mutableprotected

Keep dynamically allocated array of ValueMapping in a separate map.

This shouldn't be needed when everything gets TableGen'ed.

Definition at line 406 of file RegisterBankInfo.h.

◆ MapOfPartialMappings

DenseMap<unsigned, std::unique_ptr<const PartialMapping> > llvm::RegisterBankInfo::MapOfPartialMappings
mutableprotected

Keep dynamically allocated PartialMapping in a separate map.

This shouldn't be needed when everything gets TableGen'ed.

Definition at line 396 of file RegisterBankInfo.h.

Referenced by getPartialMapping().

◆ MapOfValueMappings

DenseMap<unsigned, std::unique_ptr<const ValueMapping> > llvm::RegisterBankInfo::MapOfValueMappings
mutableprotected

Keep dynamically allocated ValueMapping in a separate map.

This shouldn't be needed when everything gets TableGen'ed.

Definition at line 401 of file RegisterBankInfo.h.

Referenced by getValueMapping().

◆ NumRegBanks

unsigned llvm::RegisterBankInfo::NumRegBanks
protected

Total number of register banks.

Definition at line 391 of file RegisterBankInfo.h.

Referenced by getNumRegBanks().

◆ PhysRegMinimalRCs

DenseMap<unsigned, const TargetRegisterClass *> llvm::RegisterBankInfo::PhysRegMinimalRCs
mutableprotected

Getting the minimal register class of a physreg is expensive.

Cache this information as we get it.

Definition at line 415 of file RegisterBankInfo.h.

Referenced by getMinimalPhysRegClass().

◆ RegBanks

RegisterBank** llvm::RegisterBankInfo::RegBanks
protected

Hold the set of supported register banks.

Definition at line 388 of file RegisterBankInfo.h.

Referenced by getRegBank().


The documentation for this class was generated from the following files: