13#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVUTILS_H
14#define LLVM_LIB_TARGET_SPIRV_SPIRVUTILS_H
24class MachineInstrBuilder;
25class MachineIRBuilder;
26class MachineRegisterInfo;
35void addStringImm(
const StringRef &Str, MachineInstrBuilder &MIB);
37 std::vector<Value *> &Args);
41std::string
getStringImm(
const MachineInstr &
MI,
unsigned StartIndex);
44void addNumImm(
const APInt &Imm, MachineInstrBuilder &MIB);
48 MachineIRBuilder &MIRBuilder);
52 SPIRV::Decoration::Decoration Dec,
53 const std::vector<uint32_t> &DecArgs,
54 StringRef StrImm =
"");
56 SPIRV::Decoration::Decoration Dec,
57 const std::vector<uint32_t> &DecArgs,
58 StringRef StrImm =
"");
64SPIRV::StorageClass::StorageClass
67SPIRV::MemorySemantics::MemorySemantics
76 const MachineRegisterInfo *
MRI);
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const HexagonInstrInfo * TII
Promote Memory to Register
This is an optimization pass for GlobalISel generic memory operations.
void buildOpName(Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
unsigned storageClassToAddressSpace(SPIRV::StorageClass::StorageClass SC)
std::string getStringImm(const MachineInstr &MI, unsigned StartIndex)
void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB)
uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI)
SPIRV::MemorySemantics::MemorySemantics getMemSemanticsForStorageClass(SPIRV::StorageClass::StorageClass SC)
std::string getOclOrSpirvBuiltinDemangledName(StringRef Name)
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
SPIRV::StorageClass::StorageClass addressSpaceToStorageClass(unsigned AddrSpace)
bool isSpecialOpaqueType(const Type *Ty)
bool isSpvIntrinsic(MachineInstr &MI, Intrinsic::ID IntrinsicID)
AtomicOrdering
Atomic ordering for LLVM's memory model.
const Type * getTypedPtrEltType(const Type *Ty)
MachineInstr * getDefInstrMaybeConstant(Register &ConstReg, const MachineRegisterInfo *MRI)
bool hasBuiltinTypePrefix(StringRef Name)
Type * getMDOperandAsType(const MDNode *N, unsigned I)
void addStringImm(const StringRef &Str, MCInst &Inst)
SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord)