23#include "llvm/IR/IntrinsicsSPIRV.h"
33 for (
unsigned WordIndex = 0; WordIndex < 4; ++WordIndex) {
34 unsigned StrIndex = i + WordIndex;
35 uint8_t CharToAdd = 0;
36 if (StrIndex < Str.size()) {
37 CharToAdd = Str[StrIndex];
39 Word |= (CharToAdd << (WordIndex * 8));
46 const size_t Len = Str.size() + 1;
47 return (Len % 4 == 0) ? Len : Len + (4 - (Len % 4));
52 for (
unsigned i = 0; i < PaddedLen; i += 4) {
60 for (
unsigned i = 0; i < PaddedLen; i += 4) {
67 std::vector<Value *> &Args) {
69 for (
unsigned i = 0; i < PaddedLen; i += 4) {
80 const auto Bitwidth = Imm.getBitWidth();
83 else if (Bitwidth <= 32) {
84 MIB.
addImm(Imm.getZExtValue());
86 }
else if (Bitwidth <= 64) {
87 uint64_t FullImm = Imm.getZExtValue();
88 uint32_t LowBits = FullImm & 0xffffffff;
89 uint32_t HighBits = (FullImm >> 32) & 0xffffffff;
105 const std::vector<uint32_t> &DecArgs,
109 for (
const auto &DecArg : DecArgs)
114 SPIRV::Decoration::Decoration Dec,
115 const std::vector<uint32_t> &DecArgs,
StringRef StrImm) {
116 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpDecorate)
123 SPIRV::Decoration::Decoration Dec,
124 const std::vector<uint32_t> &DecArgs,
StringRef StrImm) {
126 auto MIB =
BuildMI(
MBB,
I,
I.getDebugLoc(),
TII.get(SPIRV::OpDecorate))
136 case SPIRV::StorageClass::Function:
138 case SPIRV::StorageClass::CrossWorkgroup:
140 case SPIRV::StorageClass::UniformConstant:
142 case SPIRV::StorageClass::Workgroup:
144 case SPIRV::StorageClass::Generic:
146 case SPIRV::StorageClass::Input:
153SPIRV::StorageClass::StorageClass
157 return SPIRV::StorageClass::Function;
159 return SPIRV::StorageClass::CrossWorkgroup;
161 return SPIRV::StorageClass::UniformConstant;
163 return SPIRV::StorageClass::Workgroup;
165 return SPIRV::StorageClass::Generic;
167 return SPIRV::StorageClass::Input;
173SPIRV::MemorySemantics::MemorySemantics
176 case SPIRV::StorageClass::StorageBuffer:
177 case SPIRV::StorageClass::Uniform:
178 return SPIRV::MemorySemantics::UniformMemory;
179 case SPIRV::StorageClass::Workgroup:
180 return SPIRV::MemorySemantics::WorkgroupMemory;
181 case SPIRV::StorageClass::CrossWorkgroup:
182 return SPIRV::MemorySemantics::CrossWorkgroupMemory;
183 case SPIRV::StorageClass::AtomicCounter:
184 return SPIRV::MemorySemantics::AtomicCounterMemory;
185 case SPIRV::StorageClass::Image:
186 return SPIRV::MemorySemantics::ImageMemory;
188 return SPIRV::MemorySemantics::None;
195 return SPIRV::MemorySemantics::Acquire;
197 return SPIRV::MemorySemantics::Release;
199 return SPIRV::MemorySemantics::AcquireRelease;
201 return SPIRV::MemorySemantics::SequentiallyConsistent;
205 return SPIRV::MemorySemantics::None;
213 if (
auto *GI = dyn_cast<GIntrinsic>(ConstInstr)) {
214 if (GI->is(Intrinsic::spv_track_constant)) {
216 return MRI->getVRegDef(ConstReg);
218 }
else if (ConstInstr->
getOpcode() == SPIRV::ASSIGN_TYPE) {
220 return MRI->getVRegDef(ConstReg);
222 return MRI->getVRegDef(ConstReg);
227 assert(
MI &&
MI->getOpcode() == TargetOpcode::G_CONSTANT);
228 return MI->getOperand(1).getCImm()->getValue().getZExtValue();
232 if (
auto *GI = dyn_cast<GIntrinsic>(&
MI))
233 return GI->is(IntrinsicID);
238 return cast<ValueAsMetadata>(
N->getOperand(
I))->getType();
244 return MangledName ==
"write_pipe_2" || MangledName ==
"read_pipe_2" ||
245 MangledName ==
"write_pipe_2_bl" || MangledName ==
"read_pipe_2_bl" ||
246 MangledName ==
"write_pipe_4" || MangledName ==
"read_pipe_4" ||
247 MangledName ==
"reserve_write_pipe" ||
248 MangledName ==
"reserve_read_pipe" ||
249 MangledName ==
"commit_write_pipe" ||
250 MangledName ==
"commit_read_pipe" ||
251 MangledName ==
"work_group_reserve_write_pipe" ||
252 MangledName ==
"work_group_reserve_read_pipe" ||
253 MangledName ==
"work_group_commit_write_pipe" ||
254 MangledName ==
"work_group_commit_read_pipe" ||
255 MangledName ==
"get_pipe_num_packets_ro" ||
256 MangledName ==
"get_pipe_max_packets_ro" ||
257 MangledName ==
"get_pipe_num_packets_wo" ||
258 MangledName ==
"get_pipe_max_packets_wo" ||
259 MangledName ==
"sub_group_reserve_write_pipe" ||
260 MangledName ==
"sub_group_reserve_read_pipe" ||
261 MangledName ==
"sub_group_commit_write_pipe" ||
262 MangledName ==
"sub_group_commit_read_pipe" ||
263 MangledName ==
"to_global" || MangledName ==
"to_local" ||
264 MangledName ==
"to_private";
268 return MangledName ==
"__enqueue_kernel_basic" ||
269 MangledName ==
"__enqueue_kernel_basic_events" ||
270 MangledName ==
"__enqueue_kernel_varargs" ||
271 MangledName ==
"__enqueue_kernel_events_varargs";
275 return MangledName ==
"__get_kernel_work_group_size_impl" ||
276 MangledName ==
"__get_kernel_sub_group_count_for_ndrange_impl" ||
277 MangledName ==
"__get_kernel_max_sub_group_size_for_ndrange_impl" ||
278 MangledName ==
"__get_kernel_preferred_work_group_size_multiple_impl";
282 if (!
Name.startswith(
"__"))
287 Name ==
"__translate_sampler_initializer";
292 bool IsNonMangledSPIRV =
Name.startswith(
"__spirv_");
293 bool IsMangled =
Name.startswith(
"_Z");
295 if (!IsNonMangledOCL && !IsNonMangledSPIRV && !IsMangled)
296 return std::string();
300 std::string Result = DemangledName;
305 if (IsNonMangledOCL || IsNonMangledSPIRV)
312 size_t Start, Len = 0;
313 size_t DemangledNameLenStart = 2;
314 if (
Name.startswith(
"_ZN")) {
316 size_t NameSpaceStart =
Name.find_first_not_of(
"rVKRO", 3);
318 if (
Name.substr(NameSpaceStart, 11) !=
"2cl7__spirv")
319 return std::string();
320 DemangledNameLenStart = NameSpaceStart + 11;
322 Start =
Name.find_first_not_of(
"0123456789", DemangledNameLenStart);
323 Name.substr(DemangledNameLenStart, Start - DemangledNameLenStart)
324 .getAsInteger(10, Len);
325 return Name.substr(Start, Len).str();
329 auto PType = dyn_cast<PointerType>(Ty);
330 if (!PType || PType->isOpaque())
336 if (
Name.starts_with(
"opencl.") ||
Name.starts_with(
"spirv."))
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
This file declares the MachineIRBuilder class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Class for arbitrary precision integers.
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Instances of this class represent a single low-level machine instruction.
void addOperand(const MCOperand Op)
static MCOperand createImm(int64_t Val)
Helper class to build MachineInstr.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
Class to represent struct types.
bool hasName() const
Return true if this is a named struct that has a non-empty name.
StringRef getName() const
Return the name for this struct type if it has an identity.
Class to represent target extensions types, which are generally unintrospectable from target-independ...
Target - Wrapper for Target specific information.
The instances of the Type class are immutable: once they are created, they are never changed.
Type * getNonOpaquePointerElementType() const
Only use this method in code that is not reachable with opaque pointers, or part of deprecated method...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
void buildOpName(Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
unsigned storageClassToAddressSpace(SPIRV::StorageClass::StorageClass SC)
std::string getStringImm(const MachineInstr &MI, unsigned StartIndex)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static void finishBuildOpDecorate(MachineInstrBuilder &MIB, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
static uint32_t convertCharsToWord(const StringRef &Str, unsigned i)
void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB)
uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI)
SPIRV::MemorySemantics::MemorySemantics getMemSemanticsForStorageClass(SPIRV::StorageClass::StorageClass SC)
std::string getOclOrSpirvBuiltinDemangledName(StringRef Name)
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
std::string getSPIRVStringOperand(const InstType &MI, unsigned StartIndex)
SPIRV::StorageClass::StorageClass addressSpaceToStorageClass(unsigned AddrSpace)
bool isSpecialOpaqueType(const Type *Ty)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool isSpvIntrinsic(MachineInstr &MI, Intrinsic::ID IntrinsicID)
static bool isNonMangledOCLBuiltin(StringRef Name)
AtomicOrdering
Atomic ordering for LLVM's memory model.
static bool isPipeOrAddressSpaceCastBI(const StringRef MangledName)
const Type * getTypedPtrEltType(const Type *Ty)
MachineInstr * getDefInstrMaybeConstant(Register &ConstReg, const MachineRegisterInfo *MRI)
bool hasBuiltinTypePrefix(StringRef Name)
Type * getMDOperandAsType(const MDNode *N, unsigned I)
char * itaniumDemangle(std::string_view mangled_name)
Returns a non-NULL pointer to a NUL-terminated C style string that should be explicitly freed,...
static size_t getPaddedLen(const StringRef &Str)
void addStringImm(const StringRef &Str, MCInst &Inst)
static bool isKernelQueryBI(const StringRef MangledName)
static bool isEnqueueKernelBI(const StringRef MangledName)
SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord)