LLVM  16.0.0git
SPIRVUtils.cpp
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1 //===--- SPIRVUtils.cpp ---- SPIR-V Utility Functions -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains miscellaneous utility functions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SPIRVUtils.h"
15 #include "SPIRV.h"
16 #include "SPIRVInstrInfo.h"
17 #include "llvm/ADT/StringRef.h"
21 #include "llvm/Demangle/Demangle.h"
22 #include "llvm/IR/IntrinsicsSPIRV.h"
23 
24 namespace llvm {
25 
26 // The following functions are used to add these string literals as a series of
27 // 32-bit integer operands with the correct format, and unpack them if necessary
28 // when making string comparisons in compiler passes.
29 // SPIR-V requires null-terminated UTF-8 strings padded to 32-bit alignment.
30 static uint32_t convertCharsToWord(const StringRef &Str, unsigned i) {
31  uint32_t Word = 0u; // Build up this 32-bit word from 4 8-bit chars.
32  for (unsigned WordIndex = 0; WordIndex < 4; ++WordIndex) {
33  unsigned StrIndex = i + WordIndex;
34  uint8_t CharToAdd = 0; // Initilize char as padding/null.
35  if (StrIndex < Str.size()) { // If it's within the string, get a real char.
36  CharToAdd = Str[StrIndex];
37  }
38  Word |= (CharToAdd << (WordIndex * 8));
39  }
40  return Word;
41 }
42 
43 // Get length including padding and null terminator.
44 static size_t getPaddedLen(const StringRef &Str) {
45  const size_t Len = Str.size() + 1;
46  return (Len % 4 == 0) ? Len : Len + (4 - (Len % 4));
47 }
48 
49 void addStringImm(const StringRef &Str, MCInst &Inst) {
50  const size_t PaddedLen = getPaddedLen(Str);
51  for (unsigned i = 0; i < PaddedLen; i += 4) {
52  // Add an operand for the 32-bits of chars or padding.
54  }
55 }
56 
57 void addStringImm(const StringRef &Str, MachineInstrBuilder &MIB) {
58  const size_t PaddedLen = getPaddedLen(Str);
59  for (unsigned i = 0; i < PaddedLen; i += 4) {
60  // Add an operand for the 32-bits of chars or padding.
61  MIB.addImm(convertCharsToWord(Str, i));
62  }
63 }
64 
65 void addStringImm(const StringRef &Str, IRBuilder<> &B,
66  std::vector<Value *> &Args) {
67  const size_t PaddedLen = getPaddedLen(Str);
68  for (unsigned i = 0; i < PaddedLen; i += 4) {
69  // Add a vector element for the 32-bits of chars or padding.
70  Args.push_back(B.getInt32(convertCharsToWord(Str, i)));
71  }
72 }
73 
74 std::string getStringImm(const MachineInstr &MI, unsigned StartIndex) {
75  return getSPIRVStringOperand(MI, StartIndex);
76 }
77 
78 void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB) {
79  const auto Bitwidth = Imm.getBitWidth();
80  switch (Bitwidth) {
81  case 1:
82  break; // Already handled.
83  case 8:
84  case 16:
85  case 32:
86  MIB.addImm(Imm.getZExtValue());
87  break;
88  case 64: {
89  uint64_t FullImm = Imm.getZExtValue();
90  uint32_t LowBits = FullImm & 0xffffffff;
91  uint32_t HighBits = (FullImm >> 32) & 0xffffffff;
92  MIB.addImm(LowBits).addImm(HighBits);
93  break;
94  }
95  default:
96  report_fatal_error("Unsupported constant bitwidth");
97  }
98 }
99 
101  MachineIRBuilder &MIRBuilder) {
102  if (!Name.empty()) {
103  auto MIB = MIRBuilder.buildInstr(SPIRV::OpName).addUse(Target);
104  addStringImm(Name, MIB);
105  }
106 }
107 
109  const std::vector<uint32_t> &DecArgs,
110  StringRef StrImm) {
111  if (!StrImm.empty())
112  addStringImm(StrImm, MIB);
113  for (const auto &DecArg : DecArgs)
114  MIB.addImm(DecArg);
115 }
116 
118  SPIRV::Decoration::Decoration Dec,
119  const std::vector<uint32_t> &DecArgs, StringRef StrImm) {
120  auto MIB = MIRBuilder.buildInstr(SPIRV::OpDecorate)
121  .addUse(Reg)
122  .addImm(static_cast<uint32_t>(Dec));
123  finishBuildOpDecorate(MIB, DecArgs, StrImm);
124 }
125 
127  SPIRV::Decoration::Decoration Dec,
128  const std::vector<uint32_t> &DecArgs, StringRef StrImm) {
129  MachineBasicBlock &MBB = *I.getParent();
130  auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpDecorate))
131  .addUse(Reg)
132  .addImm(static_cast<uint32_t>(Dec));
133  finishBuildOpDecorate(MIB, DecArgs, StrImm);
134 }
135 
136 // TODO: maybe the following two functions should be handled in the subtarget
137 // to allow for different OpenCL vs Vulkan handling.
139  switch (SC) {
140  case SPIRV::StorageClass::Function:
141  return 0;
142  case SPIRV::StorageClass::CrossWorkgroup:
143  return 1;
144  case SPIRV::StorageClass::UniformConstant:
145  return 2;
146  case SPIRV::StorageClass::Workgroup:
147  return 3;
148  case SPIRV::StorageClass::Generic:
149  return 4;
150  case SPIRV::StorageClass::Input:
151  return 7;
152  default:
153  llvm_unreachable("Unable to get address space id");
154  }
155 }
156 
158 addressSpaceToStorageClass(unsigned AddrSpace) {
159  switch (AddrSpace) {
160  case 0:
161  return SPIRV::StorageClass::Function;
162  case 1:
163  return SPIRV::StorageClass::CrossWorkgroup;
164  case 2:
165  return SPIRV::StorageClass::UniformConstant;
166  case 3:
167  return SPIRV::StorageClass::Workgroup;
168  case 4:
169  return SPIRV::StorageClass::Generic;
170  case 7:
171  return SPIRV::StorageClass::Input;
172  default:
173  llvm_unreachable("Unknown address space");
174  }
175 }
176 
177 SPIRV::MemorySemantics::MemorySemantics
179  switch (SC) {
180  case SPIRV::StorageClass::StorageBuffer:
181  case SPIRV::StorageClass::Uniform:
182  return SPIRV::MemorySemantics::UniformMemory;
183  case SPIRV::StorageClass::Workgroup:
184  return SPIRV::MemorySemantics::WorkgroupMemory;
185  case SPIRV::StorageClass::CrossWorkgroup:
186  return SPIRV::MemorySemantics::CrossWorkgroupMemory;
188  return SPIRV::MemorySemantics::AtomicCounterMemory;
189  case SPIRV::StorageClass::Image:
190  return SPIRV::MemorySemantics::ImageMemory;
191  default:
192  return SPIRV::MemorySemantics::None;
193  }
194 }
195 
196 SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord) {
197  switch (Ord) {
199  return SPIRV::MemorySemantics::Acquire;
201  return SPIRV::MemorySemantics::Release;
203  return SPIRV::MemorySemantics::AcquireRelease;
205  return SPIRV::MemorySemantics::SequentiallyConsistent;
209  default:
210  return SPIRV::MemorySemantics::None;
211  }
212 }
213 
215  const MachineRegisterInfo *MRI) {
216  MachineInstr *ConstInstr = MRI->getVRegDef(ConstReg);
217  if (ConstInstr->getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS &&
218  ConstInstr->getIntrinsicID() == Intrinsic::spv_track_constant) {
219  ConstReg = ConstInstr->getOperand(2).getReg();
220  ConstInstr = MRI->getVRegDef(ConstReg);
221  } else if (ConstInstr->getOpcode() == SPIRV::ASSIGN_TYPE) {
222  ConstReg = ConstInstr->getOperand(1).getReg();
223  ConstInstr = MRI->getVRegDef(ConstReg);
224  }
225  return ConstInstr;
226 }
227 
229  const MachineInstr *MI = getDefInstrMaybeConstant(ConstReg, MRI);
230  assert(MI && MI->getOpcode() == TargetOpcode::G_CONSTANT);
231  return MI->getOperand(1).getCImm()->getValue().getZExtValue();
232 }
233 
235  return MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS &&
236  MI.getIntrinsicID() == IntrinsicID;
237 }
238 
239 Type *getMDOperandAsType(const MDNode *N, unsigned I) {
240  return cast<ValueAsMetadata>(N->getOperand(I))->getType();
241 }
242 
243 // The set of names is borrowed from the SPIR-V translator.
244 // TODO: may be implemented in SPIRVBuiltins.td.
245 static bool isPipeOrAddressSpaceCastBI(const StringRef MangledName) {
246  return MangledName == "write_pipe_2" || MangledName == "read_pipe_2" ||
247  MangledName == "write_pipe_2_bl" || MangledName == "read_pipe_2_bl" ||
248  MangledName == "write_pipe_4" || MangledName == "read_pipe_4" ||
249  MangledName == "reserve_write_pipe" ||
250  MangledName == "reserve_read_pipe" ||
251  MangledName == "commit_write_pipe" ||
252  MangledName == "commit_read_pipe" ||
253  MangledName == "work_group_reserve_write_pipe" ||
254  MangledName == "work_group_reserve_read_pipe" ||
255  MangledName == "work_group_commit_write_pipe" ||
256  MangledName == "work_group_commit_read_pipe" ||
257  MangledName == "get_pipe_num_packets_ro" ||
258  MangledName == "get_pipe_max_packets_ro" ||
259  MangledName == "get_pipe_num_packets_wo" ||
260  MangledName == "get_pipe_max_packets_wo" ||
261  MangledName == "sub_group_reserve_write_pipe" ||
262  MangledName == "sub_group_reserve_read_pipe" ||
263  MangledName == "sub_group_commit_write_pipe" ||
264  MangledName == "sub_group_commit_read_pipe" ||
265  MangledName == "to_global" || MangledName == "to_local" ||
266  MangledName == "to_private";
267 }
268 
269 static bool isEnqueueKernelBI(const StringRef MangledName) {
270  return MangledName == "__enqueue_kernel_basic" ||
271  MangledName == "__enqueue_kernel_basic_events" ||
272  MangledName == "__enqueue_kernel_varargs" ||
273  MangledName == "__enqueue_kernel_events_varargs";
274 }
275 
276 static bool isKernelQueryBI(const StringRef MangledName) {
277  return MangledName == "__get_kernel_work_group_size_impl" ||
278  MangledName == "__get_kernel_sub_group_count_for_ndrange_impl" ||
279  MangledName == "__get_kernel_max_sub_group_size_for_ndrange_impl" ||
280  MangledName == "__get_kernel_preferred_work_group_size_multiple_impl";
281 }
282 
284  if (!Name.startswith("__"))
285  return false;
286 
287  return isEnqueueKernelBI(Name) || isKernelQueryBI(Name) ||
288  isPipeOrAddressSpaceCastBI(Name.drop_front(2)) ||
289  Name == "__translate_sampler_initializer";
290 }
291 
293  bool IsNonMangledOCL = isNonMangledOCLBuiltin(Name);
294  bool IsNonMangledSPIRV = Name.startswith("__spirv_");
295  bool IsMangled = Name.startswith("_Z");
296 
297  if (!IsNonMangledOCL && !IsNonMangledSPIRV && !IsMangled)
298  return std::string();
299 
300  // Try to use the itanium demangler.
301  size_t n;
302  int Status;
303  char *DemangledName = itaniumDemangle(Name.data(), nullptr, &n, &Status);
304 
305  if (Status == demangle_success) {
306  std::string Result = DemangledName;
307  free(DemangledName);
308  return Result;
309  }
310  free(DemangledName);
311  // Otherwise use simple demangling to return the function name.
312  if (IsNonMangledOCL || IsNonMangledSPIRV)
313  return Name.str();
314 
315  // Autocheck C++, maybe need to do explicit check of the source language.
316  // OpenCL C++ built-ins are declared in cl namespace.
317  // TODO: consider using 'St' abbriviation for cl namespace mangling.
318  // Similar to ::std:: in C++.
319  size_t Start, Len = 0;
320  size_t DemangledNameLenStart = 2;
321  if (Name.startswith("_ZN")) {
322  // Skip CV and ref qualifiers.
323  size_t NameSpaceStart = Name.find_first_not_of("rVKRO", 3);
324  // All built-ins are in the ::cl:: namespace.
325  if (Name.substr(NameSpaceStart, 11) != "2cl7__spirv")
326  return std::string();
327  DemangledNameLenStart = NameSpaceStart + 11;
328  }
329  Start = Name.find_first_not_of("0123456789", DemangledNameLenStart);
330  Name.substr(DemangledNameLenStart, Start - DemangledNameLenStart)
331  .getAsInteger(10, Len);
332  return Name.substr(Start, Len).str();
333 }
334 
335 static bool isOpenCLBuiltinType(const StructType *SType) {
336  return SType->isOpaque() && SType->hasName() &&
337  SType->getName().startswith("opencl.");
338 }
339 
340 static bool isSPIRVBuiltinType(const StructType *SType) {
341  return SType->isOpaque() && SType->hasName() &&
342  SType->getName().startswith("spirv.");
343 }
344 
345 const Type *getTypedPtrEltType(const Type *Ty) {
346  auto PType = dyn_cast<PointerType>(Ty);
347  if (!PType || PType->isOpaque())
348  return Ty;
349  return PType->getNonOpaquePointerElementType();
350 }
351 
352 bool isSpecialOpaqueType(const Type *Ty) {
353  if (auto SType = dyn_cast<StructType>(getTypedPtrEltType(Ty)))
354  return isOpenCLBuiltinType(SType) || isSPIRVBuiltinType(SType);
355  return false;
356 }
357 
359  StringRef Name = F->hasName() ? F->getName() : ".anonymous";
360  GlobalValue::LinkageTypes Linkage = F->getLinkage();
361  StringRef ModuleFileName = F->getParent()->getSourceFileName();
362  return GlobalValue::getGlobalIdentifier(Name, Linkage, ModuleFileName);
363 }
364 } // namespace llvm
i
i
Definition: README.txt:29
llvm::demangle_success
@ demangle_success
Definition: Demangle.h:28
llvm::AtomicOrdering::AcquireRelease
@ AcquireRelease
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
MachineInstr.h
llvm::isNonMangledOCLBuiltin
static bool isNonMangledOCLBuiltin(StringRef Name)
Definition: SPIRVUtils.cpp:283
llvm::isKernelQueryBI
static bool isKernelQueryBI(const StringRef MangledName)
Definition: SPIRVUtils.cpp:276
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::StructType::getName
StringRef getName() const
Return the name for this struct type if it has an identity.
Definition: Type.cpp:581
llvm::GlobalValue::getGlobalIdentifier
std::string getGlobalIdentifier() const
Return the modified name for this global value suitable to be used as the key for a global lookup (e....
Definition: Globals.cpp:161
AtomicCounter
static cl::opt< bool > AtomicCounter("gcov-atomic-counter", cl::Hidden, cl::desc("Make counter updates atomic"))
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::Function
Definition: Function.h:60
StringRef.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::IRBuilder<>
llvm::AtomicOrdering::SequentiallyConsistent
@ SequentiallyConsistent
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
MachineIRBuilder.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::GlobalValue::LinkageTypes
LinkageTypes
An enumeration for the kinds of linkage for global values.
Definition: GlobalValue.h:47
llvm::Type::getNonOpaquePointerElementType
Type * getNonOpaquePointerElementType() const
Only use this method in code that is not reachable with opaque pointers, or part of deprecated method...
Definition: Type.h:401
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::AtomicOrdering::Monotonic
@ Monotonic
llvm::addStringImm
void addStringImm(const StringRef &Str, MCInst &Inst)
Definition: SPIRVUtils.cpp:49
llvm::PPCISD::SC
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
Definition: PPCISelLowering.h:419
llvm::buildOpName
void buildOpName(Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
Definition: SPIRVUtils.cpp:100
llvm::StringRef::startswith
bool startswith(StringRef Prefix) const
Definition: StringRef.h:260
SPIRVBaseInfo.h
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
StorageClass
COFF::SymbolStorageClass StorageClass
Definition: COFFYAML.cpp:361
llvm::getPaddedLen
static size_t getPaddedLen(const StringRef &Str)
Definition: SPIRVUtils.cpp:44
llvm::getTypedPtrEltType
const Type * getTypedPtrEltType(const Type *Ty)
Definition: SPIRVUtils.cpp:345
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const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
SPIRVUtils.h
llvm::AtomicOrdering::Acquire
@ Acquire
llvm::addressSpaceToStorageClass
SPIRV::StorageClass::StorageClass addressSpaceToStorageClass(unsigned AddrSpace)
Definition: SPIRVUtils.cpp:158
llvm::MachineInstr::getIntrinsicID
unsigned getIntrinsicID() const
Returns the Intrinsic::ID for this instruction.
Definition: MachineInstr.h:1875
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::convertCharsToWord
static uint32_t convertCharsToWord(const StringRef &Str, unsigned i)
Definition: SPIRVUtils.cpp:30
llvm::isOpenCLBuiltinType
static bool isOpenCLBuiltinType(const StructType *SType)
Definition: SPIRVUtils.cpp:335
llvm::isEnqueueKernelBI
static bool isEnqueueKernelBI(const StringRef MangledName)
Definition: SPIRVUtils.cpp:269
llvm::finishBuildOpDecorate
static void finishBuildOpDecorate(MachineInstrBuilder &MIB, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
Definition: SPIRVUtils.cpp:108
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::getMDOperandAsType
Type * getMDOperandAsType(const MDNode *N, unsigned I)
Definition: SPIRVUtils.cpp:239
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std::string getOclOrSpirvBuiltinDemangledName(StringRef Name)
Definition: SPIRVUtils.cpp:292
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
SPIRVInstrInfo.h
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::getMemSemantics
SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord)
Definition: SPIRVUtils.cpp:196
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std::string getStringImm(const MachineInstr &MI, unsigned StartIndex)
Definition: SPIRVUtils.cpp:74
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:221
llvm::getIConstVal
uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI)
Definition: SPIRVUtils.cpp:228
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::StructType::isOpaque
bool isOpaque() const
Return true if this is a type with an identity that has no body specified yet.
Definition: DerivedTypes.h:281
llvm::AtomicOrdering::Unordered
@ Unordered
I
#define I(x, y, z)
Definition: MD5.cpp:58
SPIRV.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
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MachineInstr * getDefInstrMaybeConstant(Register &ConstReg, const MachineRegisterInfo *MRI)
Definition: SPIRVUtils.cpp:214
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
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Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MDNode
Metadata node.
Definition: Metadata.h:944
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support::ulittle32_t Word
Definition: IRSymtab.h:52
Status
Definition: SIModeRegister.cpp:29
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:383
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Definition: SPIRVInstrInfo.h:24
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Class to represent struct types.
Definition: DerivedTypes.h:213
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StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:516
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
uint32_t
llvm::addNumImm
void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB)
Definition: SPIRVUtils.cpp:78
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AtomicOrdering::Release
@ Release
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::StructType::hasName
bool hasName() const
Return true if this is a named struct that has a non-empty name.
Definition: DerivedTypes.h:290
llvm::isPipeOrAddressSpaceCastBI
static bool isPipeOrAddressSpaceCastBI(const StringRef MangledName)
Definition: SPIRVUtils.cpp:245
llvm::isSpecialOpaqueType
bool isSpecialOpaqueType(const Type *Ty)
Definition: SPIRVUtils.cpp:352
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::getMemSemanticsForStorageClass
SPIRV::MemorySemantics::MemorySemantics getMemSemanticsForStorageClass(SPIRV::StorageClass::StorageClass SC)
Definition: SPIRVUtils.cpp:178
MachineInstrBuilder.h
N
#define N
llvm::storageClassToAddressSpace
unsigned storageClassToAddressSpace(SPIRV::StorageClass::StorageClass SC)
Definition: SPIRVUtils.cpp:138
llvm::getFunctionGlobalIdentifier
std::string getFunctionGlobalIdentifier(const Function *F)
Definition: SPIRVUtils.cpp:358
llvm::isSPIRVBuiltinType
static bool isSPIRVBuiltinType(const StructType *SType)
Definition: SPIRVUtils.cpp:340
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void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
Definition: SPIRVUtils.cpp:117
llvm::itaniumDemangle
char * itaniumDemangle(const char *mangled_name, char *buf, size_t *n, int *status)
Definition: ItaniumDemangle.cpp:368
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bool isSpvIntrinsic(MachineInstr &MI, Intrinsic::ID IntrinsicID)
Definition: SPIRVUtils.cpp:234
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::getSPIRVStringOperand
std::string getSPIRVStringOperand(const InstType &MI, unsigned StartIndex)
Definition: SPIRVBaseInfo.h:242
n
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Definition: README.txt:685
llvm::AtomicOrdering::NotAtomic
@ NotAtomic
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:39