24 #define DEBUG_TYPE "sparc-disassembler"
35 virtual ~SparcDisassembler() =
default;
46 return new SparcDisassembler(STI, Ctx);
61 SP::G0, SP::G1, SP::G2, SP::G3,
62 SP::G4, SP::G5, SP::G6, SP::G7,
63 SP::O0, SP::O1, SP::O2, SP::O3,
64 SP::O4, SP::O5, SP::O6, SP::O7,
67 SP::I0,
SP::I1, SP::I2, SP::I3,
68 SP::I4, SP::I5, SP::I6, SP::I7 };
71 SP::F0, SP::F1, SP::F2, SP::F3,
72 SP::F4, SP::F5, SP::F6, SP::F7,
73 SP::F8, SP::F9, SP::F10, SP::F11,
74 SP::F12, SP::F13, SP::F14, SP::F15,
75 SP::F16, SP::F17, SP::F18, SP::F19,
76 SP::F20, SP::F21, SP::F22, SP::F23,
77 SP::F24, SP::F25, SP::F26, SP::F27,
78 SP::F28, SP::F29, SP::F30, SP::F31 };
81 SP::D0, SP::D16, SP::D1, SP::D17,
82 SP::D2, SP::D18, SP::D3, SP::D19,
83 SP::D4, SP::D20, SP::D5, SP::D21,
84 SP::D6, SP::D22, SP::D7, SP::D23,
85 SP::D8, SP::D24, SP::D9, SP::D25,
86 SP::D10, SP::D26, SP::D11, SP::D27,
87 SP::D12, SP::D28, SP::D13, SP::D29,
88 SP::D14, SP::D30, SP::D15, SP::D31 };
91 SP::Q0, SP::Q8, ~0U, ~0U,
92 SP::Q1, SP::Q9, ~0U, ~0U,
93 SP::Q2, SP::Q10, ~0U, ~0U,
94 SP::Q3, SP::Q11, ~0U, ~0U,
95 SP::Q4, SP::Q12, ~0U, ~0U,
96 SP::Q5, SP::Q13, ~0U, ~0U,
97 SP::Q6, SP::Q14, ~0U, ~0U,
98 SP::Q7, SP::Q15, ~0U, ~0U } ;
101 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
104 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
105 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
106 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
107 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
108 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
109 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
110 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
111 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
114 SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE,
115 SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN,
116 SP::OTHERWIN, SP::WSTATE, SP::PC
120 SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7,
121 SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,
122 SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7,
123 SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7,
127 SP::C0,
SP::C1, SP::C2, SP::C3,
128 SP::C4, SP::C5, SP::C6, SP::C7,
129 SP::C8, SP::C9, SP::C10, SP::C11,
130 SP::C12, SP::C13, SP::C14, SP::C15,
131 SP::C16, SP::C17, SP::C18, SP::C19,
132 SP::C20, SP::C21, SP::C22, SP::C23,
133 SP::C24, SP::C25, SP::C26, SP::C27,
134 SP::C28, SP::C29, SP::C30, SP::C31
139 SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7,
140 SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15,
141 SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23,
142 SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31
310 #include "SparcGenDisassemblerTables.inc"
315 bool IsLittleEndian) {
317 if (Bytes.
size() < 4) {
322 Insn = IsLittleEndian
323 ? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
325 : (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) |
336 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
344 if (STI.getFeatureBits()[Sparc::FeatureV9])
346 Result = decodeInstruction(DecoderTableSparcV932, Instr,
Insn, Address,
this, STI);
350 Result = decodeInstruction(DecoderTableSparcV832, Instr,
Insn, Address,
this, STI);
356 decodeInstruction(DecoderTableSparc32, Instr,
Insn, Address,
this, STI);
372 unsigned rd = fieldFromInstruction(insn, 25, 5);
373 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
374 bool isImm = fieldFromInstruction(insn, 13, 1);
375 bool hasAsi = fieldFromInstruction(insn, 23, 1);
376 unsigned asi = fieldFromInstruction(insn, 5, 8);
380 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
382 rs2 = fieldFromInstruction(insn, 0, 5);
386 status = DecodeRD(
MI, rd, Address, Decoder);
409 status = DecodeRD(
MI, rd, Address, Decoder);
418 return DecodeMem(Inst, insn, Address, Decoder,
true,
425 return DecodeMem(Inst, insn, Address, Decoder,
true,
431 return DecodeMem(Inst, insn, Address, Decoder,
true,
437 return DecodeMem(Inst, insn, Address, Decoder,
true,
443 return DecodeMem(Inst, insn, Address, Decoder,
true,
449 return DecodeMem(Inst, insn, Address, Decoder,
true,
456 return DecodeMem(Inst, insn, Address, Decoder,
true,
463 return DecodeMem(Inst, insn, Address, Decoder,
false,
470 return DecodeMem(Inst, insn, Address, Decoder,
false,
476 return DecodeMem(Inst, insn, Address, Decoder,
false,
483 return DecodeMem(Inst, insn, Address, Decoder,
false,
490 return DecodeMem(Inst, insn, Address, Decoder,
false,
496 return DecodeMem(Inst, insn, Address, Decoder,
false,
503 return DecodeMem(Inst, insn, Address, Decoder,
false,
517 unsigned tgt = fieldFromInstruction(insn, 0, 30);
527 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
535 unsigned rd = fieldFromInstruction(insn, 25, 5);
536 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
537 unsigned isImm = fieldFromInstruction(insn, 13, 1);
541 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
543 rs2 = fieldFromInstruction(insn, 0, 5);
569 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
570 unsigned isImm = fieldFromInstruction(insn, 13, 1);
574 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
576 rs2 = fieldFromInstruction(insn, 0, 5);
597 unsigned rd = fieldFromInstruction(insn, 25, 5);
598 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
599 unsigned isImm = fieldFromInstruction(insn, 13, 1);
600 bool hasAsi = fieldFromInstruction(insn, 23, 1);
601 unsigned asi = fieldFromInstruction(insn, 5, 8);
605 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
607 rs2 = fieldFromInstruction(insn, 0, 5);
637 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
638 unsigned isImm = fieldFromInstruction(insn, 13, 1);
639 unsigned cc =fieldFromInstruction(insn, 25, 4);
643 imm7 = fieldFromInstruction(insn, 0, 7);
645 rs2 = fieldFromInstruction(insn, 0, 5);