LLVM 17.0.0git
SparcInstPrinter.cpp
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1//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax -----==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an Sparc MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SparcInstPrinter.h"
14#include "Sparc.h"
15#include "llvm/MC/MCExpr.h"
16#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCSymbol.h"
21using namespace llvm;
22
23#define DEBUG_TYPE "asm-printer"
24
25// The generated AsmMatcher SparcGenAsmWriter uses "Sparc" as the target
26// namespace. But SPARC backend uses "SP" as its namespace.
27namespace llvm {
28namespace Sparc {
29 using namespace SP;
30}
31}
32
33#define GET_INSTRUCTION_NAME
34#define PRINT_ALIAS_INSTR
35#include "SparcGenAsmWriter.inc"
36
38 return (STI.hasFeature(Sparc::FeatureV9)) != 0;
39}
40
42 OS << '%' << StringRef(getRegisterName(Reg)).lower();
43}
44
46 StringRef Annot, const MCSubtargetInfo &STI,
47 raw_ostream &O) {
48 if (!printAliasInstr(MI, Address, STI, O) &&
49 !printSparcAliasInstr(MI, STI, O))
50 printInstruction(MI, Address, STI, O);
51 printAnnotation(O, Annot);
52}
53
55 const MCSubtargetInfo &STI,
56 raw_ostream &O) {
57 switch (MI->getOpcode()) {
58 default: return false;
59 case SP::JMPLrr:
60 case SP::JMPLri: {
61 if (MI->getNumOperands() != 3)
62 return false;
63 if (!MI->getOperand(0).isReg())
64 return false;
65 switch (MI->getOperand(0).getReg()) {
66 default: return false;
67 case SP::G0: // jmp $addr | ret | retl
68 if (MI->getOperand(2).isImm() &&
69 MI->getOperand(2).getImm() == 8) {
70 switch(MI->getOperand(1).getReg()) {
71 default: break;
72 case SP::I7: O << "\tret"; return true;
73 case SP::O7: O << "\tretl"; return true;
74 }
75 }
76 O << "\tjmp "; printMemOperand(MI, 1, STI, O);
77 return true;
78 case SP::O7: // call $addr
79 O << "\tcall "; printMemOperand(MI, 1, STI, O);
80 return true;
81 }
82 }
83 case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ:
84 case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: {
85 if (isV9(STI)
86 || (MI->getNumOperands() != 3)
87 || (!MI->getOperand(0).isReg())
88 || (MI->getOperand(0).getReg() != SP::FCC0))
89 return false;
90 // if V8, skip printing %fcc0.
91 switch(MI->getOpcode()) {
92 default:
93 case SP::V9FCMPS: O << "\tfcmps "; break;
94 case SP::V9FCMPD: O << "\tfcmpd "; break;
95 case SP::V9FCMPQ: O << "\tfcmpq "; break;
96 case SP::V9FCMPES: O << "\tfcmpes "; break;
97 case SP::V9FCMPED: O << "\tfcmped "; break;
98 case SP::V9FCMPEQ: O << "\tfcmpeq "; break;
99 }
100 printOperand(MI, 1, STI, O);
101 O << ", ";
102 printOperand(MI, 2, STI, O);
103 return true;
104 }
105 }
106}
107
109 const MCSubtargetInfo &STI,
110 raw_ostream &O) {
111 const MCOperand &MO = MI->getOperand (opNum);
112
113 if (MO.isReg()) {
114 printRegName(O, MO.getReg());
115 return ;
116 }
117
118 if (MO.isImm()) {
119 switch (MI->getOpcode()) {
120 default:
121 O << (int)MO.getImm();
122 return;
123
124 case SP::TICCri: // Fall through
125 case SP::TICCrr: // Fall through
126 case SP::TRAPri: // Fall through
127 case SP::TRAPrr: // Fall through
128 case SP::TXCCri: // Fall through
129 case SP::TXCCrr: // Fall through
130 // Only seven-bit values up to 127.
131 O << ((int) MO.getImm() & 0x7f);
132 return;
133 }
134 }
135
136 assert(MO.isExpr() && "Unknown operand kind in printOperand");
137 MO.getExpr()->print(O, &MAI);
138}
139
141 const MCSubtargetInfo &STI,
142 raw_ostream &O, const char *Modifier) {
143 // If this is an ADD operand, emit it like normal operands.
144 if (Modifier && !strcmp(Modifier, "arith")) {
145 printOperand(MI, opNum, STI, O);
146 O << ", ";
147 printOperand(MI, opNum + 1, STI, O);
148 return;
149 }
150
151 const MCOperand &Op1 = MI->getOperand(opNum);
152 const MCOperand &Op2 = MI->getOperand(opNum + 1);
153
154 bool PrintedFirstOperand = false;
155 if (Op1.isReg() && Op1.getReg() != SP::G0) {
156 printOperand(MI, opNum, STI, O);
157 PrintedFirstOperand = true;
158 }
159
160 // Skip the second operand iff it adds nothing (literal 0 or %g0) and we've
161 // already printed the first one
162 const bool SkipSecondOperand =
163 PrintedFirstOperand && ((Op2.isReg() && Op2.getReg() == SP::G0) ||
164 (Op2.isImm() && Op2.getImm() == 0));
165
166 if (!SkipSecondOperand) {
167 if (PrintedFirstOperand)
168 O << '+';
169 printOperand(MI, opNum + 1, STI, O);
170 }
171}
172
174 const MCSubtargetInfo &STI,
175 raw_ostream &O) {
176 int CC = (int)MI->getOperand(opNum).getImm();
177 switch (MI->getOpcode()) {
178 default: break;
179 case SP::FBCOND:
180 case SP::FBCONDA:
181 case SP::FBCOND_V9:
182 case SP::FBCONDA_V9:
183 case SP::BPFCC:
184 case SP::BPFCCA:
185 case SP::BPFCCNT:
186 case SP::BPFCCANT:
187 case SP::MOVFCCrr: case SP::V9MOVFCCrr:
188 case SP::MOVFCCri: case SP::V9MOVFCCri:
189 case SP::FMOVS_FCC: case SP::V9FMOVS_FCC:
190 case SP::FMOVD_FCC: case SP::V9FMOVD_FCC:
191 case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC:
192 // Make sure CC is a fp conditional flag.
194 break;
195 case SP::CBCOND:
196 case SP::CBCONDA:
197 // Make sure CC is a cp conditional flag.
199 break;
200 case SP::MOVRri:
201 case SP::MOVRrr:
202 case SP::FMOVRS:
203 case SP::FMOVRD:
204 case SP::FMOVRQ:
205 // Make sure CC is a register conditional flag.
207 break;
208 }
210}
211
212bool SparcInstPrinter::printGetPCX(const MCInst *MI, unsigned opNum,
213 const MCSubtargetInfo &STI,
214 raw_ostream &O) {
215 llvm_unreachable("FIXME: Implement SparcInstPrinter::printGetPCX.");
216 return true;
217}
218
220 const MCSubtargetInfo &STI,
221 raw_ostream &O) {
222 static const char *const TagNames[] = {
223 "#LoadLoad", "#StoreLoad", "#LoadStore", "#StoreStore",
224 "#Lookaside", "#MemIssue", "#Sync"};
225
226 unsigned Imm = MI->getOperand(opNum).getImm();
227
228 if (Imm > 127) {
229 O << Imm;
230 return;
231 }
232
233 bool First = true;
234 for (unsigned i = 0; i < std::size(TagNames); i++) {
235 if (Imm & (1 << i)) {
236 O << (First ? "" : " | ") << TagNames[i];
237 First = false;
238 }
239 }
240}
IRTranslator LLVM IR MI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:41
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:50
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
int64_t getImm() const
Definition: MCInst.h:80
bool isImm() const
Definition: MCInst.h:62
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
bool isReg() const
Definition: MCInst.h:61
const MCExpr * getExpr() const
Definition: MCInst.h:114
bool isExpr() const
Definition: MCInst.h:65
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &OS)
bool isV9(const MCSubtargetInfo &STI) const
bool printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &OS)
void printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &OS)
void printRegName(raw_ostream &OS, MCRegister Reg) const override
Print the assembler register name.
bool printGetPCX(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &OS)
static const char * getRegisterName(MCRegister Reg)
void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &OS, const char *Modifier=nullptr)
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printMembarTag(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string lower() const
Definition: StringRef.cpp:111
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CondCodes
Definition: Sparc.h:41
@ FCC_BEGIN
Definition: Sparc.h:59
@ REG_BEGIN
Definition: Sparc.h:95
@ CPCC_BEGIN
Definition: Sparc.h:77
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
static const char * SPARCCondCodeToString(SPCC::CondCodes CC)
Definition: Sparc.h:105