62 enum class TailRelocKind { Load_GOT, Add_TLS, Load_TLS, Call_TLS };
67#define GET_ASSEMBLER_HEADER
68#include "SparcGenAsmMatcher.inc"
76 bool MatchingInlineAsm)
override;
79 SMLoc &EndLoc)
override;
85 unsigned Kind)
override;
94 template <TailRelocKind Kind>
103 ParseStatus parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Operand,
104 bool isCall =
false);
115 bool matchSparcAsmModifiers(
const MCExpr *&EVal,
SMLoc &EndLoc);
133 MRI(*Parser.getContext().getRegisterInfo()) {
150 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
151 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
152 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
153 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
154 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
155 Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
156 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
157 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
160 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
161 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
162 Sparc::D8, Sparc::D9, Sparc::D10, Sparc::D11,
163 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
164 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
165 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
166 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
167 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
170 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
171 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
172 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
173 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
176 Sparc::G0_G1, Sparc::G2_G3, Sparc::G4_G5, Sparc::G6_G7,
177 Sparc::O0_O1, Sparc::O2_O3, Sparc::O4_O5, Sparc::O6_O7,
178 Sparc::L0_L1, Sparc::L2_L3, Sparc::L4_L5, Sparc::L6_L7,
179 Sparc::I0_I1, Sparc::I2_I3, Sparc::I4_I5, Sparc::I6_I7};
182 Sparc::C0_C1, Sparc::C2_C3, Sparc::C4_C5, Sparc::C6_C7,
183 Sparc::C8_C9, Sparc::C10_C11, Sparc::C12_C13, Sparc::C14_C15,
184 Sparc::C16_C17, Sparc::C18_C19, Sparc::C20_C21, Sparc::C22_C23,
185 Sparc::C24_C25, Sparc::C26_C27, Sparc::C28_C29, Sparc::C30_C31};
215 SMLoc StartLoc, EndLoc;
246 SparcOperand(KindTy K) :
Kind(
K) {}
248 bool isToken()
const override {
return Kind == k_Token; }
249 bool isReg()
const override {
return Kind == k_Register; }
250 bool isImm()
const override {
return Kind == k_Immediate; }
251 bool isMem()
const override {
return isMEMrr() || isMEMri(); }
252 bool isMEMrr()
const {
return Kind == k_MemoryReg; }
253 bool isMEMri()
const {
return Kind == k_MemoryImm; }
254 bool isMembarTag()
const {
return Kind == k_Immediate; }
255 bool isASITag()
const {
return Kind == k_ASITag; }
256 bool isTailRelocSym()
const {
return Kind == k_Immediate; }
258 bool isCallTarget()
const {
263 return CE->getValue() % 4 == 0;
268 bool isShiftAmtImm5()
const {
273 return isUInt<5>(
CE->getValue());
278 bool isShiftAmtImm6()
const {
283 return isUInt<6>(
CE->getValue());
289 return (Kind == k_Register &&
Reg.Kind == rk_IntReg);
292 bool isFloatReg()
const {
293 return (Kind == k_Register &&
Reg.Kind == rk_FloatReg);
296 bool isFloatOrDoubleReg()
const {
297 return (Kind == k_Register && (
Reg.Kind == rk_FloatReg
298 ||
Reg.Kind == rk_DoubleReg));
301 bool isCoprocReg()
const {
302 return (Kind == k_Register &&
Reg.Kind == rk_CoprocReg);
306 assert(Kind == k_Token &&
"Invalid access!");
311 assert((Kind == k_Register) &&
"Invalid access!");
315 const MCExpr *getImm()
const {
316 assert((Kind == k_Immediate) &&
"Invalid access!");
320 unsigned getMemBase()
const {
321 assert((Kind == k_MemoryReg || Kind == k_MemoryImm) &&
"Invalid access!");
325 unsigned getMemOffsetReg()
const {
326 assert((Kind == k_MemoryReg) &&
"Invalid access!");
327 return Mem.OffsetReg;
330 const MCExpr *getMemOff()
const {
331 assert((Kind == k_MemoryImm) &&
"Invalid access!");
335 unsigned getASITag()
const {
336 assert((Kind == k_ASITag) &&
"Invalid access!");
351 case k_Token:
OS <<
"Token: " << getToken() <<
"\n";
break;
352 case k_Register:
OS <<
"Reg: #" <<
getReg() <<
"\n";
break;
353 case k_Immediate:
OS <<
"Imm: " << getImm() <<
"\n";
break;
354 case k_MemoryReg:
OS <<
"Mem: " << getMemBase() <<
"+"
355 << getMemOffsetReg() <<
"\n";
break;
356 case k_MemoryImm:
assert(getMemOff() !=
nullptr);
357 OS <<
"Mem: " << getMemBase()
358 <<
"+" << *getMemOff()
361 OS <<
"ASI tag: " << getASITag() <<
"\n";
366 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
367 assert(
N == 1 &&
"Invalid number of operands!");
371 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
372 assert(
N == 1 &&
"Invalid number of operands!");
373 const MCExpr *Expr = getImm();
377 void addShiftAmtImm5Operands(
MCInst &Inst,
unsigned N)
const {
378 assert(
N == 1 &&
"Invalid number of operands!");
379 addExpr(Inst, getImm());
381 void addShiftAmtImm6Operands(
MCInst &Inst,
unsigned N)
const {
382 assert(
N == 1 &&
"Invalid number of operands!");
383 addExpr(Inst, getImm());
390 else if (
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
396 void addMEMrrOperands(
MCInst &Inst,
unsigned N)
const {
397 assert(
N == 2 &&
"Invalid number of operands!");
401 assert(getMemOffsetReg() != 0 &&
"Invalid offset");
405 void addMEMriOperands(
MCInst &Inst,
unsigned N)
const {
406 assert(
N == 2 &&
"Invalid number of operands!");
410 const MCExpr *Expr = getMemOff();
414 void addASITagOperands(
MCInst &Inst,
unsigned N)
const {
415 assert(
N == 1 &&
"Invalid number of operands!");
419 void addMembarTagOperands(
MCInst &Inst,
unsigned N)
const {
420 assert(
N == 1 &&
"Invalid number of operands!");
421 const MCExpr *Expr = getImm();
426 assert(
N == 1 &&
"Invalid number of operands!");
427 addExpr(Inst, getImm());
430 void addTailRelocSymOperands(
MCInst &Inst,
unsigned N)
const {
431 assert(
N == 1 &&
"Invalid number of operands!");
432 addExpr(Inst, getImm());
435 static std::unique_ptr<SparcOperand> CreateToken(
StringRef Str,
SMLoc S) {
436 auto Op = std::make_unique<SparcOperand>(k_Token);
437 Op->Tok.Data = Str.data();
438 Op->Tok.Length = Str.size();
444 static std::unique_ptr<SparcOperand> CreateReg(
unsigned RegNum,
unsigned Kind,
446 auto Op = std::make_unique<SparcOperand>(k_Register);
447 Op->Reg.RegNum = RegNum;
448 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind;
454 static std::unique_ptr<SparcOperand> CreateImm(
const MCExpr *Val,
SMLoc S,
456 auto Op = std::make_unique<SparcOperand>(k_Immediate);
463 static std::unique_ptr<SparcOperand> CreateASITag(
unsigned Val,
SMLoc S,
465 auto Op = std::make_unique<SparcOperand>(k_ASITag);
472 static bool MorphToIntPairReg(SparcOperand &
Op) {
473 unsigned Reg =
Op.getReg();
475 unsigned regIdx = 32;
476 if (
Reg >= Sparc::G0 &&
Reg <= Sparc::G7)
477 regIdx =
Reg - Sparc::G0;
478 else if (
Reg >= Sparc::O0 &&
Reg <= Sparc::O7)
479 regIdx =
Reg - Sparc::O0 + 8;
480 else if (
Reg >= Sparc::L0 &&
Reg <= Sparc::L7)
481 regIdx =
Reg - Sparc::L0 + 16;
482 else if (
Reg >= Sparc::I0 &&
Reg <= Sparc::I7)
483 regIdx =
Reg - Sparc::I0 + 24;
484 if (regIdx % 2 || regIdx > 31)
487 Op.Reg.Kind = rk_IntPairReg;
491 static bool MorphToDoubleReg(SparcOperand &
Op) {
492 unsigned Reg =
Op.getReg();
494 unsigned regIdx =
Reg - Sparc::F0;
495 if (regIdx % 2 || regIdx > 31)
498 Op.Reg.Kind = rk_DoubleReg;
502 static bool MorphToQuadReg(SparcOperand &
Op) {
503 unsigned Reg =
Op.getReg();
505 switch (
Op.Reg.Kind) {
508 regIdx =
Reg - Sparc::F0;
509 if (regIdx % 4 || regIdx > 31)
514 regIdx =
Reg - Sparc::D0;
515 if (regIdx % 2 || regIdx > 31)
521 Op.Reg.Kind = rk_QuadReg;
525 static bool MorphToCoprocPairReg(SparcOperand &
Op) {
526 unsigned Reg =
Op.getReg();
527 assert(
Op.Reg.Kind == rk_CoprocReg);
528 unsigned regIdx = 32;
529 if (
Reg >= Sparc::C0 &&
Reg <= Sparc::C31)
530 regIdx =
Reg - Sparc::C0;
531 if (regIdx % 2 || regIdx > 31)
534 Op.Reg.Kind = rk_CoprocPairReg;
538 static std::unique_ptr<SparcOperand>
539 MorphToMEMrr(
unsigned Base, std::unique_ptr<SparcOperand>
Op) {
540 unsigned offsetReg =
Op->getReg();
541 Op->Kind = k_MemoryReg;
543 Op->Mem.OffsetReg = offsetReg;
544 Op->Mem.Off =
nullptr;
548 static std::unique_ptr<SparcOperand>
550 auto Op = std::make_unique<SparcOperand>(k_MemoryReg);
552 Op->Mem.OffsetReg = Sparc::G0;
553 Op->Mem.Off =
nullptr;
559 static std::unique_ptr<SparcOperand>
560 MorphToMEMri(
unsigned Base, std::unique_ptr<SparcOperand>
Op) {
562 Op->Kind = k_MemoryImm;
564 Op->Mem.OffsetReg = 0;
572bool SparcAsmParser::expandSET(
MCInst &Inst,
SMLoc IDLoc,
581 int64_t RawImmValue = IsImm ? MCValOp.
getImm() : 0;
584 if (RawImmValue < -2147483648LL || RawImmValue > 4294967295LL) {
586 "set: argument must be between -2147483648 and 4294967295");
591 int32_t ImmValue = RawImmValue;
595 bool IsEffectivelyImm13 =
596 IsImm && ((
is64Bit() ? 0 : -4096) <= ImmValue && ImmValue < 4096);
608 if (!IsEffectivelyImm13) {
629 if (!IsImm || IsEffectivelyImm13 || (ImmValue & 0x3ff)) {
632 if (IsEffectivelyImm13)
646bool SparcAsmParser::expandSETX(
MCInst &Inst,
SMLoc IDLoc,
655 bool IsImm = MCValOp.
isImm();
656 int64_t ImmValue = IsImm ? MCValOp.
getImm() : 0;
662 if (IsImm && isInt<13>(ImmValue)) {
687 if (IsImm && isUInt<32>(ImmValue))
718bool SparcAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
722 bool MatchingInlineAsm) {
727 switch (MatchResult) {
728 case Match_Success: {
735 if (expandSET(Inst, IDLoc, Instructions))
739 if (expandSETX(Inst, IDLoc, Instructions))
744 for (
const MCInst &
I : Instructions) {
750 case Match_MissingFeature:
752 "instruction requires a CPU feature not currently enabled");
754 case Match_InvalidOperand: {
755 SMLoc ErrorLoc = IDLoc;
758 return Error(IDLoc,
"too few operands for instruction");
761 if (ErrorLoc ==
SMLoc())
765 return Error(ErrorLoc,
"invalid operand for instruction");
767 case Match_MnemonicFail:
768 return Error(IDLoc,
"invalid instruction mnemonic");
775 if (!tryParseRegister(Reg, StartLoc, EndLoc).isSuccess())
776 return Error(StartLoc,
"invalid register name");
785 Reg = Sparc::NoRegister;
789 unsigned RegKind = SparcOperand::rk_None;
790 Reg = matchRegisterName(Tok, RegKind);
796 getLexer().UnLex(Tok);
809 Operands.push_back(SparcOperand::CreateToken(
Name, NameLoc));
817 if (!parseBranchModifiers(
Operands).isSuccess()) {
818 SMLoc Loc = getLexer().getLoc();
819 return Error(Loc,
"unexpected token");
823 SMLoc Loc = getLexer().getLoc();
824 return Error(Loc,
"unexpected token");
835 SMLoc Loc = getLexer().getLoc();
836 return Error(Loc,
"unexpected token");
841 SMLoc Loc = getLexer().getLoc();
842 return Error(Loc,
"unexpected token");
851 if (IDVal ==
".register") {
856 if (IDVal ==
".proc") {
870 std::unique_ptr<SparcOperand>
LHS;
871 if (!parseSparcAsmOperand(LHS).isSuccess())
876 Operands.push_back(SparcOperand::MorphToMEMri(Sparc::G0, std::move(LHS)));
880 if (!
LHS->isIntReg())
881 return Error(
LHS->getStartLoc(),
"invalid register kind for this operand");
889 std::unique_ptr<SparcOperand>
RHS;
890 if (!parseSparcAsmOperand(RHS).isSuccess())
893 if (
RHS->isReg() && !
RHS->isIntReg())
895 "invalid register kind for this operand");
899 ? SparcOperand::MorphToMEMri(
LHS->getReg(), std::move(RHS))
905 Operands.push_back(SparcOperand::CreateMEMr(
LHS->getReg(), S, E));
919 if (getParser().parseExpression(Expr))
924 return Error(S,
"constant expression expected");
926 if (!isUInt<N>(
CE->getValue()))
927 return Error(S,
"immediate shift value out of range");
929 Operands.push_back(SparcOperand::CreateImm(Expr, S, E));
933template <SparcAsmParser::TailRelocKind Kind>
940 case TailRelocKind::Load_GOT:
944 case TailRelocKind::Add_TLS:
956 case TailRelocKind::Load_TLS:
966 case TailRelocKind::Call_TLS:
981 return Error(getLoc(),
"expected '%' for operand modifier");
987 return Error(getLoc(),
"expected valid identifier for operand modifier");
992 return Error(getLoc(),
"invalid operand modifier");
994 if (!MatchesKind(VK)) {
996 getLexer().UnLex(Tok);
1002 return Error(getLoc(),
"expected '('");
1006 if (getParser().parseParenExpression(SubExpr, E))
1009 const MCExpr *Val = adjustPICRelocation(VK, SubExpr);
1010 Operands.push_back(SparcOperand::CreateImm(Val, S, E));
1019 std::unique_ptr<SparcOperand>
Mask;
1020 if (parseSparcAsmOperand(Mask).isSuccess()) {
1021 if (!
Mask->isImm() || !
Mask->getImm()->evaluateAsAbsolute(ImmVal) ||
1022 ImmVal < 0 || ImmVal > 127)
1023 return Error(S,
"invalid membar mask number");
1027 SMLoc TagStart = getLexer().getLoc();
1030 .
Case(
"LoadLoad", 0x1)
1031 .
Case(
"StoreLoad", 0x2)
1032 .
Case(
"LoadStore", 0x4)
1033 .
Case(
"StoreStore", 0x8)
1034 .
Case(
"Lookaside", 0x10)
1035 .
Case(
"MemIssue", 0x20)
1042 return Error(TagStart,
"unknown membar tag");
1052 Operands.push_back(SparcOperand::CreateImm(EVal, S, E));
1064 SMLoc TagStart = getLexer().peekTok(
false).getLoc();
1067 auto ASITag = SparcASITag::lookupASITagByName(ASIName);
1069 ASITag = SparcASITag::lookupASITagByAltName(ASIName);
1073 return Error(TagStart,
"unknown ASI tag");
1075 ASIVal = ASITag->Encoding;
1076 }
else if (!getParser().parseAbsoluteExpression(ASIVal)) {
1077 if (!isUInt<8>(ASIVal))
1078 return Error(S,
"invalid ASI number, must be between 0 and 255");
1082 ?
"malformed ASI tag, must be %asi, a constant integer "
1083 "expression, or a named tag"
1084 :
"malformed ASI tag, must be a constant integer expression");
1087 Operands.push_back(SparcOperand::CreateASITag(ASIVal, S, E));
1095 switch (getLexer().getKind()) {
1106 if (getParser().parseExpression(DestValue))
1109 bool IsPic = getContext().getObjectFileInfo()->isPositionIndependent();
1114 Operands.push_back(SparcOperand::CreateImm(DestExpr, S, E));
1131 Operands.push_back(SparcOperand::CreateToken(
"[",
1135 if (Mnemonic ==
"cas" || Mnemonic ==
"casl" || Mnemonic ==
"casa" ||
1136 Mnemonic ==
"casx" || Mnemonic ==
"casxl" || Mnemonic ==
"casxa") {
1149 Operands.push_back(SparcOperand::CreateReg(Reg, RegKind, S, E));
1161 Operands.push_back(SparcOperand::CreateToken(
"]",
1179 if (OldMemOp.isMEMrr()) {
1180 if (OldMemOp.getMemOffsetReg() != Sparc::G0) {
1181 return Error(S,
"invalid operand for instruction");
1184 OldMemOp.getMemBase(),
1186 OldMemOp.getStartLoc(),
1187 OldMemOp.getEndLoc()));
1194 Operands.push_back(SparcOperand::CreateToken(
"%asi", S));
1198 return Error(S,
"malformed ASI tag, must be %asi, a constant integer "
1199 "expression, or a named tag");
1210 std::unique_ptr<SparcOperand>
Op;
1212 Res = parseSparcAsmOperand(
Op, (Mnemonic ==
"call"));
1223SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &
Op,
1230 switch (getLexer().getKind()) {
1240 if (Reg == Sparc::ICC &&
Name ==
"xcc")
1241 Op = SparcOperand::CreateToken(
"%xcc", S);
1243 Op = SparcOperand::CreateReg(Reg, RegKind, S, E);
1246 if (matchSparcAsmModifiers(EVal, E)) {
1248 Op = SparcOperand::CreateImm(EVal, S, E);
1259 if (getParser().parseExpression(EVal, E))
1263 if (!EVal->evaluateAsAbsolute(Res)) {
1266 if (getContext().getObjectFileInfo()->isPositionIndependent()) {
1274 Op = SparcOperand::CreateImm(EVal, S, E);
1289 if (modName ==
"a" || modName ==
"pn" || modName ==
"pt") {
1290 Operands.push_back(SparcOperand::CreateToken(modName,
1298#define GET_REGISTER_MATCHER
1299#include "SparcGenAsmMatcher.inc"
1302 unsigned &RegKind) {
1303 RegKind = SparcOperand::rk_None;
1305 return SP::NoRegister;
1319 if (Reg == SP::ASR4 &&
Name ==
"tick") {
1320 RegKind = SparcOperand::rk_Special;
1324 if (
MRI.getRegClass(SP::IntRegsRegClassID).contains(Reg)) {
1325 RegKind = SparcOperand::rk_IntReg;
1328 if (
MRI.getRegClass(SP::FPRegsRegClassID).contains(Reg)) {
1329 RegKind = SparcOperand::rk_FloatReg;
1332 if (
MRI.getRegClass(SP::CoprocRegsRegClassID).contains(Reg)) {
1333 RegKind = SparcOperand::rk_CoprocReg;
1338 if (
MRI.getRegClass(SP::IntPairRegClassID).contains(Reg)) {
1339 RegKind = SparcOperand::rk_IntReg;
1340 return MRI.getSubReg(Reg, SP::sub_even);
1344 if (
MRI.getRegClass(SP::DFPRegsRegClassID).contains(Reg)) {
1347 RegKind = SparcOperand::rk_FloatReg;
1350 RegKind = SparcOperand::rk_DoubleReg;
1356 assert(!
MRI.getRegClass(SP::QFPRegsRegClassID).contains(Reg));
1359 if (
MRI.getRegClass(SP::CoprocPairRegClassID).contains(Reg)) {
1360 RegKind = SparcOperand::rk_CoprocReg;
1361 return MRI.getSubReg(Reg, SP::sub_even);
1365 RegKind = SparcOperand::rk_Special;
1374 if (
Name.starts_with_insensitive(
"r") &&
1375 !
Name.substr(1, 2).getAsInteger(10, RegNo) && RegNo < 31) {
1376 RegKind = SparcOperand::rk_IntReg;
1380 if (
Name.equals(
"xcc")) {
1382 RegKind = SparcOperand::rk_Special;
1388 if (
Name.equals(
"pcr")) {
1389 RegKind = SparcOperand::rk_Special;
1393 if (
Name.equals(
"pic")) {
1394 RegKind = SparcOperand::rk_Special;
1397 if (
Name.equals(
"dcr")) {
1398 RegKind = SparcOperand::rk_Special;
1401 if (
Name.equals(
"gsr")) {
1402 RegKind = SparcOperand::rk_Special;
1405 if (
Name.equals(
"softint")) {
1406 RegKind = SparcOperand::rk_Special;
1409 if (
Name.equals(
"tick_cmpr")) {
1410 RegKind = SparcOperand::rk_Special;
1413 if (
Name.equals(
"stick") ||
Name.equals(
"sys_tick")) {
1414 RegKind = SparcOperand::rk_Special;
1417 if (
Name.equals(
"stick_cmpr") ||
Name.equals(
"sys_tick_cmpr")) {
1418 RegKind = SparcOperand::rk_Special;
1422 return SP::NoRegister;
1430 if (
const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
1461 if (getContext().getObjectFileInfo()->isPositionIndependent()) {
1478bool SparcAsmParser::matchSparcAsmModifiers(
const MCExpr *&EVal,
1489 Error(getLoc(),
"invalid operand modifier");
1517 EVal = adjustPICRelocation(VK, subExpr);
1527#define GET_MATCHER_IMPLEMENTATION
1528#include "SparcGenAsmMatcher.inc"
1532 SparcOperand &
Op = (SparcOperand &)GOp;
1533 if (
Op.isFloatOrDoubleReg()) {
1537 if (!
Op.isFloatReg() || SparcOperand::MorphToDoubleReg(
Op))
1541 if (SparcOperand::MorphToQuadReg(
Op))
1546 if (
Op.isIntReg() && Kind == MCK_IntPair) {
1547 if (SparcOperand::MorphToIntPairReg(
Op))
1550 if (
Op.isCoprocReg() && Kind == MCK_CoprocPair) {
1551 if (SparcOperand::MorphToCoprocPairReg(
Op))
1554 return Match_InvalidOperand;
unsigned const MachineRegisterInfo * MRI
static MCRegister MatchRegisterName(StringRef Name)
static bool addCallTargetOperands(MachineInstrBuilder &CallInst, MachineIRBuilder &MIRBuilder, AMDGPUCallLowering::CallLoweringInfo &Info)
static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI)
static MCRegister MatchRegisterAltName(StringRef Name)
Maps from the set of all alternative registernames to a register number.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_EXTERNAL_VISIBILITY
mir Rename Register Operands
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
static const MCPhysReg DoubleRegs[32]
static bool hasGOTReference(const MCExpr *Expr)
static const MCPhysReg IntRegs[32]
static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcAsmParser()
static const MCPhysReg IntPairRegs[]
static const MCPhysReg QuadFPRegs[32]
static const MCPhysReg CoprocPairRegs[]
static bool is64Bit(const char *name)
Target independent representation for an assembler token.
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
bool is(TokenKind K) const
TokenKind getKind() const
This class represents an Operation in the Expression.
Base class for user error types.
Lightweight error class with error context and mandatory checking.
Container class for subtarget features.
MCAsmParser & getParser()
Generic assembler parser interface, for use by target specific assembly parsers.
virtual void eatToEndOfStatement()=0
Skip to the end of the current statement, for error recovery.
const AsmToken & getTok() const
Get the current AsmToken from the stream.
virtual bool parseParenExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression, assuming that an initial '(' has already been consumed.
bool parseOptionalToken(AsmToken::TokenKind T)
Attempt to parse and consume token, returning true on success.
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
virtual void addAliasForDirective(StringRef Directive, StringRef Alias)=0
Binary assembler expressions.
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Base class for the full range of assembler expressions which are needed for parsing.
@ Unary
Unary expressions.
@ Constant
Constant expressions.
@ SymbolRef
References to labels and assigned expressions.
@ Target
Target specific expression.
@ Binary
Binary expressions.
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Interface to description of machine instruction set.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createImm(int64_t Val)
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
virtual SMLoc getStartLoc() const =0
getStartLoc - Get the location of the first token of this operand.
virtual bool isReg() const =0
isReg - Is this a register operand?
virtual bool isMem() const =0
isMem - Is this a memory operand?
virtual MCRegister getReg() const =0
virtual void print(raw_ostream &OS) const =0
print - Print a debug representation of the operand to the given stream.
virtual bool isToken() const =0
isToken - Is this a token operand?
virtual bool isImm() const =0
isImm - Is this an immediate operand?
virtual SMLoc getEndLoc() const =0
getEndLoc - Get the location of the last token of this operand.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
Streaming machine code generation interface.
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
Represent a reference to a symbol from inside an expression.
const MCSymbol & getSymbol() const
StringRef getName() const
getName - Get the symbol name.
MCTargetAsmParser - Generic interface to target specific assembly parsers.
virtual ParseStatus parseDirective(AsmToken DirectiveID)
Parses a target-specific assembler directive.
virtual bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc)=0
virtual ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc)=0
tryParseRegister - parse one register if possible
void setAvailableFeatures(const FeatureBitset &Value)
const MCSubtargetInfo & getSTI() const
virtual unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind)
Allow a target to add special case operand matching for things that tblgen doesn't/can't handle effec...
virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands)=0
ParseInstruction - Parse one assembly instruction.
virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm)=0
MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst ...
Ternary parse status returned by various parse* methods.
constexpr bool isFailure() const
static constexpr StatusTy Failure
constexpr bool isSuccess() const
static constexpr StatusTy Success
static constexpr StatusTy NoMatch
Represents a location in source code.
static SMLoc getFromPointer(const char *Ptr)
constexpr const char * getPointer() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
static const SparcMCExpr * create(VariantKind Kind, const MCExpr *Expr, MCContext &Ctx)
static VariantKind parseVariantKind(StringRef name)
StringRef - Represent a constant reference to a string, i.e.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
ArchType getArch() const
Get the parsed architecture type of this triple.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ C
The default llvm calling convention, compatible with C.
MCExpr const & getExpr(MCExpr const &Expr)
bool isIntReg(unsigned Reg)
@ CE
Windows NT (Windows on ARM)
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheSparcTarget()
Target & getTheSparcV9Target()
DWARFExpression::Operation Op
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Target & getTheSparcelTarget()
Implement std::hash so that hash_code can be used in STL containers.
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...