58 enum class TailRelocKind { Load_GOT, Add_TLS, Load_TLS, Call_TLS };
63 #define GET_ASSEMBLER_HEADER
64 #include "SparcGenAsmMatcher.inc"
69 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
72 bool MatchingInlineAsm)
override;
73 bool ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc)
override;
75 SMLoc &EndLoc)
override;
78 bool ParseDirective(
AsmToken DirectiveID)
override;
81 unsigned Kind)
override;
88 template <TailRelocKind Kind>
99 parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Operand,
100 bool isCall =
false);
109 bool matchRegisterName(
const AsmToken &Tok,
unsigned &RegNo,
112 bool matchSparcAsmModifiers(
const MCExpr *&EVal,
SMLoc &EndLoc);
121 SMLoc getLoc()
const {
return getParser().getTok().getLoc(); }
137 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
144 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
145 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
146 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
147 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
150 Sparc::I0,
Sparc::I1, Sparc::I2, Sparc::I3,
151 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
154 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
155 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
156 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
157 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
158 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
159 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
160 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
161 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
164 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
165 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
166 Sparc::D8, Sparc::D9, Sparc::D10, Sparc::D11,
167 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
168 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
169 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
170 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
171 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
174 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
175 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
176 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
177 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
180 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
181 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
182 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
183 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
184 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
185 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
186 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
187 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
190 Sparc::G0_G1, Sparc::G2_G3, Sparc::G4_G5, Sparc::G6_G7,
191 Sparc::O0_O1, Sparc::O2_O3, Sparc::O4_O5, Sparc::O6_O7,
192 Sparc::L0_L1, Sparc::L2_L3, Sparc::L4_L5, Sparc::L6_L7,
193 Sparc::I0_I1, Sparc::I2_I3, Sparc::I4_I5, Sparc::I6_I7};
196 Sparc::C0,
Sparc::C1, Sparc::C2, Sparc::C3,
197 Sparc::C4, Sparc::C5, Sparc::C6, Sparc::C7,
198 Sparc::C8, Sparc::C9, Sparc::C10, Sparc::C11,
199 Sparc::C12, Sparc::C13, Sparc::C14, Sparc::C15,
200 Sparc::C16, Sparc::C17, Sparc::C18, Sparc::C19,
201 Sparc::C20, Sparc::C21, Sparc::C22, Sparc::C23,
202 Sparc::C24, Sparc::C25, Sparc::C26, Sparc::C27,
203 Sparc::C28, Sparc::C29, Sparc::C30, Sparc::C31 };
206 Sparc::C0_C1, Sparc::C2_C3, Sparc::C4_C5, Sparc::C6_C7,
207 Sparc::C8_C9, Sparc::C10_C11, Sparc::C12_C13, Sparc::C14_C15,
208 Sparc::C16_C17, Sparc::C18_C19, Sparc::C20_C21, Sparc::C22_C23,
209 Sparc::C24_C25, Sparc::C26_C27, Sparc::C28_C29, Sparc::C30_C31};
238 SMLoc StartLoc, EndLoc;
268 SparcOperand(KindTy K) :
Kind(K) {}
270 bool isToken()
const override {
return Kind == k_Token; }
271 bool isReg()
const override {
return Kind == k_Register; }
272 bool isImm()
const override {
return Kind == k_Immediate; }
273 bool isMem()
const override {
return isMEMrr() || isMEMri(); }
274 bool isMEMrr()
const {
return Kind == k_MemoryReg; }
275 bool isMEMri()
const {
return Kind == k_MemoryImm; }
276 bool isMembarTag()
const {
return Kind == k_Immediate; }
277 bool isTailRelocSym()
const {
return Kind == k_Immediate; }
279 bool isCallTarget()
const {
284 return CE->getValue() % 4 == 0;
289 bool isShiftAmtImm5()
const {
294 return isUInt<5>(
CE->getValue());
299 bool isShiftAmtImm6()
const {
304 return isUInt<6>(
CE->getValue());
310 return (
Kind == k_Register &&
Reg.Kind == rk_IntReg);
313 bool isFloatReg()
const {
314 return (
Kind == k_Register &&
Reg.Kind == rk_FloatReg);
317 bool isFloatOrDoubleReg()
const {
318 return (
Kind == k_Register && (
Reg.Kind == rk_FloatReg
319 ||
Reg.Kind == rk_DoubleReg));
322 bool isCoprocReg()
const {
323 return (
Kind == k_Register &&
Reg.Kind == rk_CoprocReg);
331 unsigned getReg()
const override {
332 assert((
Kind == k_Register) &&
"Invalid access!");
336 const MCExpr *getImm()
const {
337 assert((
Kind == k_Immediate) &&
"Invalid access!");
341 unsigned getMemBase()
const {
342 assert((
Kind == k_MemoryReg ||
Kind == k_MemoryImm) &&
"Invalid access!");
346 unsigned getMemOffsetReg()
const {
347 assert((
Kind == k_MemoryReg) &&
"Invalid access!");
348 return Mem.OffsetReg;
351 const MCExpr *getMemOff()
const {
352 assert((
Kind == k_MemoryImm) &&
"Invalid access!");
357 SMLoc getStartLoc()
const override {
361 SMLoc getEndLoc()
const override {
367 case k_Token: OS <<
"Token: " << getToken() <<
"\n";
break;
368 case k_Register: OS <<
"Reg: #" <<
getReg() <<
"\n";
break;
369 case k_Immediate: OS <<
"Imm: " << getImm() <<
"\n";
break;
370 case k_MemoryReg: OS <<
"Mem: " << getMemBase() <<
"+"
371 << getMemOffsetReg() <<
"\n";
break;
372 case k_MemoryImm:
assert(getMemOff() !=
nullptr);
373 OS <<
"Mem: " << getMemBase()
374 <<
"+" << *getMemOff()
379 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
380 assert(
N == 1 &&
"Invalid number of operands!");
384 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
385 assert(
N == 1 &&
"Invalid number of operands!");
386 const MCExpr *Expr = getImm();
390 void addShiftAmtImm5Operands(
MCInst &Inst,
unsigned N)
const {
391 assert(
N == 1 &&
"Invalid number of operands!");
392 addExpr(Inst, getImm());
394 void addShiftAmtImm6Operands(
MCInst &Inst,
unsigned N)
const {
395 assert(
N == 1 &&
"Invalid number of operands!");
396 addExpr(Inst, getImm());
403 else if (
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
409 void addMEMrrOperands(
MCInst &Inst,
unsigned N)
const {
410 assert(
N == 2 &&
"Invalid number of operands!");
414 assert(getMemOffsetReg() != 0 &&
"Invalid offset");
418 void addMEMriOperands(
MCInst &Inst,
unsigned N)
const {
419 assert(
N == 2 &&
"Invalid number of operands!");
423 const MCExpr *Expr = getMemOff();
427 void addMembarTagOperands(
MCInst &Inst,
unsigned N)
const {
428 assert(
N == 1 &&
"Invalid number of operands!");
429 const MCExpr *Expr = getImm();
434 assert(
N == 1 &&
"Invalid number of operands!");
435 addExpr(Inst, getImm());
438 void addTailRelocSymOperands(
MCInst &Inst,
unsigned N)
const {
439 assert(
N == 1 &&
"Invalid number of operands!");
440 addExpr(Inst, getImm());
443 static std::unique_ptr<SparcOperand> CreateToken(
StringRef Str,
SMLoc S) {
444 auto Op = std::make_unique<SparcOperand>(k_Token);
445 Op->Tok.Data = Str.data();
446 Op->Tok.Length = Str.size();
452 static std::unique_ptr<SparcOperand> CreateReg(
unsigned RegNum,
unsigned Kind,
454 auto Op = std::make_unique<SparcOperand>(k_Register);
455 Op->Reg.RegNum = RegNum;
456 Op->Reg.Kind = (SparcOperand::RegisterKind)
Kind;
462 static std::unique_ptr<SparcOperand> CreateImm(
const MCExpr *Val,
SMLoc S,
464 auto Op = std::make_unique<SparcOperand>(k_Immediate);
471 static bool MorphToIntPairReg(SparcOperand &
Op) {
472 unsigned Reg =
Op.getReg();
474 unsigned regIdx = 32;
475 if (
Reg >= Sparc::G0 &&
Reg <= Sparc::G7)
476 regIdx =
Reg - Sparc::G0;
477 else if (
Reg >= Sparc::O0 &&
Reg <= Sparc::O7)
478 regIdx =
Reg - Sparc::O0 + 8;
480 regIdx =
Reg - Sparc::L0 + 16;
481 else if (
Reg >= Sparc::I0 &&
Reg <= Sparc::I7)
482 regIdx =
Reg - Sparc::I0 + 24;
483 if (regIdx % 2 || regIdx > 31)
486 Op.Reg.Kind = rk_IntPairReg;
490 static bool MorphToDoubleReg(SparcOperand &
Op) {
491 unsigned Reg =
Op.getReg();
493 unsigned regIdx =
Reg - Sparc::F0;
494 if (regIdx % 2 || regIdx > 31)
497 Op.Reg.Kind = rk_DoubleReg;
501 static bool MorphToQuadReg(SparcOperand &
Op) {
502 unsigned Reg =
Op.getReg();
504 switch (
Op.Reg.Kind) {
507 regIdx =
Reg - Sparc::F0;
508 if (regIdx % 4 || regIdx > 31)
513 regIdx =
Reg - Sparc::D0;
514 if (regIdx % 2 || regIdx > 31)
520 Op.Reg.Kind = rk_QuadReg;
524 static bool MorphToCoprocPairReg(SparcOperand &
Op) {
525 unsigned Reg =
Op.getReg();
526 assert(
Op.Reg.Kind == rk_CoprocReg);
527 unsigned regIdx = 32;
528 if (
Reg >= Sparc::C0 &&
Reg <= Sparc::C31)
529 regIdx =
Reg - Sparc::C0;
530 if (regIdx % 2 || regIdx > 31)
533 Op.Reg.Kind = rk_CoprocPairReg;
537 static std::unique_ptr<SparcOperand>
538 MorphToMEMrr(
unsigned Base, std::unique_ptr<SparcOperand>
Op) {
539 unsigned offsetReg =
Op->getReg();
540 Op->Kind = k_MemoryReg;
542 Op->Mem.OffsetReg = offsetReg;
543 Op->Mem.Off =
nullptr;
547 static std::unique_ptr<SparcOperand>
549 auto Op = std::make_unique<SparcOperand>(k_MemoryReg);
551 Op->Mem.OffsetReg = Sparc::G0;
552 Op->Mem.Off =
nullptr;
558 static std::unique_ptr<SparcOperand>
559 MorphToMEMri(
unsigned Base, std::unique_ptr<SparcOperand>
Op) {
561 Op->Kind = k_MemoryImm;
563 Op->Mem.OffsetReg = 0;
571 bool SparcAsmParser::expandSET(
MCInst &Inst,
SMLoc IDLoc,
580 int64_t RawImmValue = IsImm ? MCValOp.
getImm() : 0;
583 if (RawImmValue < -2147483648LL || RawImmValue > 4294967295LL) {
585 "set: argument must be between -2147483648 and 4294967295");
590 int32_t ImmValue = RawImmValue;
594 bool IsEffectivelyImm13 =
595 IsImm && ((
is64Bit() ? 0 : -4096) <= ImmValue && ImmValue < 4096);
607 if (!IsEffectivelyImm13) {
628 if (!IsImm || IsEffectivelyImm13 || (ImmValue & 0x3ff)) {
631 if (IsEffectivelyImm13)
645 bool SparcAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
649 bool MatchingInlineAsm) {
654 switch (MatchResult) {
655 case Match_Success: {
673 case Match_MissingFeature:
675 "instruction requires a CPU feature not currently enabled");
677 case Match_InvalidOperand: {
678 SMLoc ErrorLoc = IDLoc;
681 return Error(IDLoc,
"too few operands for instruction");
684 if (ErrorLoc ==
SMLoc())
688 return Error(ErrorLoc,
"invalid operand for instruction");
690 case Match_MnemonicFail:
691 return Error(IDLoc,
"invalid instruction mnemonic");
696 bool SparcAsmParser::ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
699 return Error(StartLoc,
"invalid register name");
713 unsigned regKind = SparcOperand::rk_None;
714 if (matchRegisterName(Tok, RegNo, regKind)) {
719 getLexer().UnLex(Tok);
732 Operands.push_back(SparcOperand::CreateToken(
Name, NameLoc));
741 SMLoc Loc = getLexer().getLoc();
742 return Error(Loc,
"unexpected token");
746 SMLoc Loc = getLexer().getLoc();
747 return Error(Loc,
"unexpected token");
758 SMLoc Loc = getLexer().getLoc();
759 return Error(Loc,
"unexpected token");
764 SMLoc Loc = getLexer().getLoc();
765 return Error(Loc,
"unexpected token");
771 bool SparcAsmParser::
772 ParseDirective(
AsmToken DirectiveID)
776 if (IDVal ==
".register") {
781 if (IDVal ==
".proc") {
796 std::unique_ptr<SparcOperand>
LHS;
806 if (!
LHS->isIntReg()) {
807 Error(
LHS->getStartLoc(),
"invalid register kind for this operand");
817 std::unique_ptr<SparcOperand>
RHS;
821 if (
RHS->isReg() && !
RHS->isIntReg()) {
822 Error(
RHS->getStartLoc(),
"invalid register kind for this operand");
834 Operands.push_back(SparcOperand::CreateMEMr(
LHS->getReg(),
S,
E));
838 template <
unsigned N>
848 if (getParser().parseExpression(Expr))
853 Error(
S,
"constant expression expected");
857 if (!isUInt<N>(
CE->getValue())) {
858 Error(
S,
"immediate shift value out of range");
862 Operands.push_back(SparcOperand::CreateImm(Expr,
S,
E));
866 template <SparcAsmParser::TailRelocKind Kind>
874 case TailRelocKind::Load_GOT:
878 case TailRelocKind::Add_TLS:
890 case TailRelocKind::Load_TLS:
900 case TailRelocKind::Call_TLS:
915 Error(getLoc(),
"expected '%' for operand modifier");
923 Error(getLoc(),
"expected valid identifier for operand modifier");
930 Error(getLoc(),
"invalid operand modifier");
934 if (!MatchesKind(VK)) {
936 getLexer().UnLex(Tok);
942 Error(getLoc(),
"expected '('");
948 if (getParser().parseParenExpression(SubExpr,
E)) {
952 const MCExpr *Val = adjustPICRelocation(VK, SubExpr);
953 Operands.push_back(SparcOperand::CreateImm(Val,
S,
E));
962 std::unique_ptr<SparcOperand>
Mask;
964 if (!
Mask->isImm() || !
Mask->getImm()->evaluateAsAbsolute(ImmVal) ||
965 ImmVal < 0 || ImmVal > 127) {
966 Error(
S,
"invalid membar mask number");
972 SMLoc TagStart = getLexer().getLoc();
975 .
Case(
"LoadLoad", 0x1)
977 .
Case(
"LoadStore", 0x4)
978 .
Case(
"StoreStore", 0x8)
979 .
Case(
"Lookaside", 0x10)
980 .
Case(
"MemIssue", 0x20)
987 Error(TagStart,
"unknown membar tag");
999 Operands.push_back(SparcOperand::CreateImm(EVal,
S,
E));
1007 switch (getLexer().getKind()) {
1018 if (getParser().parseExpression(DestValue))
1021 bool IsPic = getContext().getObjectFileInfo()->isPositionIndependent();
1026 Operands.push_back(SparcOperand::CreateImm(DestExpr,
S,
E));
1043 Operands.push_back(SparcOperand::CreateToken(
"[",
1047 if (Mnemonic ==
"cas" || Mnemonic ==
"casx" || Mnemonic ==
"casa") {
1053 unsigned RegNo, RegKind;
1054 if (!matchRegisterName(Parser.
getTok(), RegNo, RegKind))
1059 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind,
S,
E));
1071 Operands.push_back(SparcOperand::CreateToken(
"]",
1077 std::unique_ptr<SparcOperand>
Op;
1078 ResTy = parseSparcAsmOperand(
Op,
false);
1086 std::unique_ptr<SparcOperand>
Op;
1088 ResTy = parseSparcAsmOperand(
Op, (Mnemonic ==
"call"));
1099 SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &
Op,
1106 switch (getLexer().getKind()) {
1113 if (matchRegisterName(Parser.
getTok(), RegNo, RegKind)) {
1119 Op = SparcOperand::CreateReg(RegNo, RegKind,
S,
E);
1122 Op = SparcOperand::CreateToken(
"%psr",
S);
1125 Op = SparcOperand::CreateToken(
"%fsr",
S);
1128 Op = SparcOperand::CreateToken(
"%fq",
S);
1131 Op = SparcOperand::CreateToken(
"%csr",
S);
1134 Op = SparcOperand::CreateToken(
"%cq",
S);
1137 Op = SparcOperand::CreateToken(
"%wim",
S);
1140 Op = SparcOperand::CreateToken(
"%tbr",
S);
1143 Op = SparcOperand::CreateToken(
"%pc",
S);
1147 Op = SparcOperand::CreateToken(
"%xcc",
S);
1149 Op = SparcOperand::CreateToken(
"%icc",
S);
1154 if (matchSparcAsmModifiers(EVal,
E)) {
1156 Op = SparcOperand::CreateImm(EVal,
S,
E);
1166 if (getParser().parseExpression(EVal,
E))
1170 if (!EVal->evaluateAsAbsolute(Res)) {
1173 if (getContext().getObjectFileInfo()->isPositionIndependent()) {
1181 Op = SparcOperand::CreateImm(EVal,
S,
E);
1197 if (modName ==
"a" || modName ==
"pn" || modName ==
"pt") {
1198 Operands.push_back(SparcOperand::CreateToken(modName,
1206 bool SparcAsmParser::matchRegisterName(
const AsmToken &Tok,
unsigned &RegNo,
1207 unsigned &RegKind) {
1210 RegKind = SparcOperand::rk_None;
1215 if (
name.equals(
"fp")) {
1217 RegKind = SparcOperand::rk_IntReg;
1221 if (
name.equals(
"sp")) {
1223 RegKind = SparcOperand::rk_IntReg;
1227 if (
name.equals(
"y")) {
1229 RegKind = SparcOperand::rk_Special;
1233 if (
name.substr(0, 3).equals_insensitive(
"asr") &&
1234 !
name.substr(3).getAsInteger(10, intVal) && intVal > 0 && intVal < 32) {
1236 RegKind = SparcOperand::rk_Special;
1241 if (
name.equals(
"fprs")) {
1243 RegKind = SparcOperand::rk_Special;
1247 if (
name.equals(
"icc")) {
1249 RegKind = SparcOperand::rk_Special;
1253 if (
name.equals(
"psr")) {
1255 RegKind = SparcOperand::rk_Special;
1259 if (
name.equals(
"fsr")) {
1261 RegKind = SparcOperand::rk_Special;
1265 if (
name.equals(
"fq")) {
1267 RegKind = SparcOperand::rk_Special;
1271 if (
name.equals(
"csr")) {
1272 RegNo = Sparc::CPSR;
1273 RegKind = SparcOperand::rk_Special;
1277 if (
name.equals(
"cq")) {
1279 RegKind = SparcOperand::rk_Special;
1283 if (
name.equals(
"wim")) {
1285 RegKind = SparcOperand::rk_Special;
1289 if (
name.equals(
"tbr")) {
1291 RegKind = SparcOperand::rk_Special;
1295 if (
name.equals(
"xcc")) {
1298 RegKind = SparcOperand::rk_Special;
1303 if (
name.substr(0, 3).equals_insensitive(
"fcc") &&
1304 !
name.substr(3).getAsInteger(10, intVal) && intVal < 4) {
1306 RegNo = Sparc::FCC0 + intVal;
1307 RegKind = SparcOperand::rk_Special;
1312 if (
name.substr(0, 1).equals_insensitive(
"g") &&
1313 !
name.substr(1).getAsInteger(10, intVal) && intVal < 8) {
1315 RegKind = SparcOperand::rk_IntReg;
1319 if (
name.substr(0, 1).equals_insensitive(
"o") &&
1320 !
name.substr(1).getAsInteger(10, intVal) && intVal < 8) {
1322 RegKind = SparcOperand::rk_IntReg;
1325 if (
name.substr(0, 1).equals_insensitive(
"l") &&
1326 !
name.substr(1).getAsInteger(10, intVal) && intVal < 8) {
1328 RegKind = SparcOperand::rk_IntReg;
1331 if (
name.substr(0, 1).equals_insensitive(
"i") &&
1332 !
name.substr(1).getAsInteger(10, intVal) && intVal < 8) {
1334 RegKind = SparcOperand::rk_IntReg;
1338 if (
name.substr(0, 1).equals_insensitive(
"f") &&
1339 !
name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
1341 RegKind = SparcOperand::rk_FloatReg;
1345 if (
name.substr(0, 1).equals_insensitive(
"f") &&
1346 !
name.substr(1, 2).getAsInteger(10, intVal) && intVal >= 32 &&
1347 intVal <= 62 && (intVal % 2 == 0)) {
1350 RegKind = SparcOperand::rk_DoubleReg;
1355 if (
name.substr(0, 1).equals_insensitive(
"r") &&
1356 !
name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
1358 RegKind = SparcOperand::rk_IntReg;
1363 if (
name.substr(0, 1).equals_insensitive(
"c") &&
1364 !
name.substr(1).getAsInteger(10, intVal) && intVal < 32) {
1366 RegKind = SparcOperand::rk_CoprocReg;
1370 if (
name.equals(
"tpc")) {
1372 RegKind = SparcOperand::rk_Special;
1375 if (
name.equals(
"tnpc")) {
1376 RegNo = Sparc::TNPC;
1377 RegKind = SparcOperand::rk_Special;
1380 if (
name.equals(
"tstate")) {
1381 RegNo = Sparc::TSTATE;
1382 RegKind = SparcOperand::rk_Special;
1385 if (
name.equals(
"tt")) {
1387 RegKind = SparcOperand::rk_Special;
1390 if (
name.equals(
"tick")) {
1391 RegNo = Sparc::TICK;
1392 RegKind = SparcOperand::rk_Special;
1395 if (
name.equals(
"tba")) {
1397 RegKind = SparcOperand::rk_Special;
1400 if (
name.equals(
"pstate")) {
1401 RegNo = Sparc::PSTATE;
1402 RegKind = SparcOperand::rk_Special;
1405 if (
name.equals(
"tl")) {
1407 RegKind = SparcOperand::rk_Special;
1410 if (
name.equals(
"pil")) {
1412 RegKind = SparcOperand::rk_Special;
1415 if (
name.equals(
"cwp")) {
1417 RegKind = SparcOperand::rk_Special;
1420 if (
name.equals(
"cansave")) {
1421 RegNo = Sparc::CANSAVE;
1422 RegKind = SparcOperand::rk_Special;
1425 if (
name.equals(
"canrestore")) {
1426 RegNo = Sparc::CANRESTORE;
1427 RegKind = SparcOperand::rk_Special;
1430 if (
name.equals(
"cleanwin")) {
1431 RegNo = Sparc::CLEANWIN;
1432 RegKind = SparcOperand::rk_Special;
1435 if (
name.equals(
"otherwin")) {
1436 RegNo = Sparc::OTHERWIN;
1437 RegKind = SparcOperand::rk_Special;
1440 if (
name.equals(
"wstate")) {
1441 RegNo = Sparc::WSTATE;
1442 RegKind = SparcOperand::rk_Special;
1445 if (
name.equals(
"pc")) {
1447 RegKind = SparcOperand::rk_Special;
1459 if (
const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
1490 if (getContext().getObjectFileInfo()->isPositionIndependent()) {
1507 bool SparcAsmParser::matchSparcAsmModifiers(
const MCExpr *&EVal,
1518 Error(getLoc(),
"invalid operand modifier");
1546 EVal = adjustPICRelocation(VK, subExpr);
1556 #define GET_REGISTER_MATCHER
1557 #define GET_MATCHER_IMPLEMENTATION
1558 #include "SparcGenAsmMatcher.inc"
1562 SparcOperand &
Op = (SparcOperand &)GOp;
1563 if (
Op.isFloatOrDoubleReg()) {
1567 if (!
Op.isFloatReg() || SparcOperand::MorphToDoubleReg(
Op))
1571 if (SparcOperand::MorphToQuadReg(
Op))
1576 if (
Op.isIntReg() &&
Kind == MCK_IntPair) {
1577 if (SparcOperand::MorphToIntPairReg(
Op))
1580 if (
Op.isCoprocReg() &&
Kind == MCK_CoprocPair) {
1581 if (SparcOperand::MorphToCoprocPairReg(
Op))
1584 return Match_InvalidOperand;