Go to the documentation of this file.
25 static const char hex_rep[] =
"0123456789abcdef";
32 OS << hex_rep[(
i & 0xF0) >> 4];
33 OS << hex_rep[
i & 0xF];
52 (*CommentStream) << Annot;
55 if (Annot.back() !=
'\n')
56 (*CommentStream) <<
'\n';
66 bool &OrPredicateResult) {
84 bool Res = OrPredicateResult;
85 OrPredicateResult =
false;
97 return Opnd.
isImm() && Opnd.
getImm() == int32_t(
C.Value);
103 return Opnd.
isReg() && Opnd.
getReg() ==
MI.getOperand(
C.Value).getReg();
109 return M.ValidateMCOperand(Opnd, *STI,
C.Value);
130 return L.Opcode < Opcode;
132 if (It ==
M.OpToPatterns.end() || It->Opcode !=
MI->getOpcode())
138 M.Patterns.slice(It->PatternStart, It->NumPatterns);
141 if (
MI->getNumOperands() !=
P.NumOperands)
146 M.PatternConds.slice(
P.AliasCondStart,
P.NumConds);
148 bool OrPredicateResult =
false;
154 AsmStrOffset =
P.AsmStrOffset;
160 if (AsmStrOffset == ~0U)
166 assert(AsmStrOffset <
M.AsmStrings.size() &&
167 (AsmStrOffset == 0 ||
M.AsmStrings[AsmStrOffset - 1] ==
'\0') &&
168 "bad asm string offset");
169 return M.AsmStrings.data() + AsmStrOffset;
185 uint64_t digit = (
Value >> 60) & 0xf;
187 return (digit >= 0xa);
202 return format<int64_t>(
"-0x8000000000000000",
Value);
209 return format<int64_t>(
"-8000000000000000h",
Value);
format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
StringRef getCommentString() const
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
static bool matchAliasCondition(const MCInst &MI, const MCSubtargetInfo *STI, const MCRegisterInfo &MRI, unsigned &OpIdx, const AliasMatchingData &M, const AliasPatternCond &C, bool &OrPredicateResult)
bool getUseMarkup() const
Instances of this class represent a single low-level machine instruction.
Tablegenerated data structures needed to match alias patterns.
const MCRegisterInfo & MRI
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
(vector float) vec_cmpeq(*A, *B) C
into llvm powi allowing the code generator to produce balanced multiplication trees First
const FeatureBitset & getFeatureBits() const
Map from opcode to pattern list by binary search.
const char * matchAliasPatterns(const MCInst *MI, const MCSubtargetInfo *STI, const AliasMatchingData &M)
Helper for matching MCInsts to alias patterns when printing instructions.
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const
Print the assembler register name.
void dumpBytes(ArrayRef< uint8_t > Bytes, raw_ostream &OS)
Convert ‘Bytes’ to a hex string and output to ‘OS’.
multiplies can be turned into SHL s
format_object< int64_t > formatHex(int64_t Value) const
HexStyle::Style PrintHexStyle
Which style to use for printing hexadecimal values.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
static bool needsLeadingZero(uint64_t Value)
StringRef getOpcodeName(unsigned Opcode) const
Return the name of the specified opcode enum (e.g.
StringRef markup(StringRef s) const
Utility functions to make adding mark ups simpler.
Data for each alias pattern.
constexpr bool test(unsigned I) const
Instances of this class represent operands of the MCInst class.
Generic base class for all target subtargets.
LLVM Value Representation.
unsigned getReg() const
Returns the register number.