LLVM
15.0.0git
lib
Target
Sparc
MCTargetDesc
SparcMCTargetDesc.h
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//===-- SparcMCTargetDesc.h - Sparc Target Descriptions ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides Sparc specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCTARGETDESC_H
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#define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCTARGETDESC_H
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#include "
llvm/Support/DataTypes.h
"
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#include <memory>
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namespace
llvm
{
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class
MCAsmBackend;
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class
MCCodeEmitter;
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class
MCContext;
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class
MCInstrInfo;
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class
MCObjectTargetWriter;
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class
MCRegisterInfo;
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class
MCSubtargetInfo;
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class
MCTargetOptions;
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class
Target
;
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MCCodeEmitter *
createSparcMCCodeEmitter
(
const
MCInstrInfo &MCII,
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MCContext &Ctx);
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MCAsmBackend *
createSparcAsmBackend
(
const
Target
&
T
,
const
MCSubtargetInfo &STI,
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const
MCRegisterInfo &
MRI
,
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const
MCTargetOptions &
Options
);
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std::unique_ptr<MCObjectTargetWriter>
createSparcELFObjectWriter
(
bool
Is64Bit,
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uint8_t OSABI);
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}
// End llvm namespace
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// Defines symbolic names for Sparc registers. This defines a mapping from
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// register name to register number.
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//
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#define GET_REGINFO_ENUM
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#include "SparcGenRegisterInfo.inc"
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// Defines symbolic names for the Sparc instructions.
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//
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#define GET_INSTRINFO_ENUM
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#include "SparcGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "SparcGenSubtargetInfo.inc"
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#endif
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition:
AddressRanges.h:17
llvm::createSparcELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createSparcELFObjectWriter(bool Is64Bit, uint8_t OSABI)
Definition:
SparcELFObjectWriter.cpp:147
llvm::createSparcMCCodeEmitter
MCCodeEmitter * createSparcMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition:
SparcMCCodeEmitter.cpp:259
llvm::AMDGPU::Exp::Target
Target
Definition:
SIDefines.h:855
T
#define T
Definition:
Mips16ISelLowering.cpp:341
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition:
PassBuilderBindings.cpp:48
MRI
unsigned const MachineRegisterInfo * MRI
Definition:
AArch64AdvSIMDScalarPass.cpp:105
DataTypes.h
llvm::createSparcAsmBackend
MCAsmBackend * createSparcAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition:
SparcAsmBackend.cpp:371
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