LLVM  14.0.0git
SparcMCTargetDesc.h
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1 //===-- SparcMCTargetDesc.h - Sparc Target Descriptions ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Sparc specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCTARGETDESC_H
14 #define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCTARGETDESC_H
15 
16 #include "llvm/Support/DataTypes.h"
17 
18 #include <memory>
19 
20 namespace llvm {
21 class MCAsmBackend;
22 class MCCodeEmitter;
23 class MCContext;
24 class MCInstrInfo;
25 class MCObjectTargetWriter;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class MCTargetOptions;
29 class Target;
30 
31 MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
32  const MCRegisterInfo &MRI,
33  MCContext &Ctx);
34 MCAsmBackend *createSparcAsmBackend(const Target &T, const MCSubtargetInfo &STI,
35  const MCRegisterInfo &MRI,
36  const MCTargetOptions &Options);
37 std::unique_ptr<MCObjectTargetWriter> createSparcELFObjectWriter(bool Is64Bit,
38  uint8_t OSABI);
39 } // End llvm namespace
40 
41 // Defines symbolic names for Sparc registers. This defines a mapping from
42 // register name to register number.
43 //
44 #define GET_REGINFO_ENUM
45 #include "SparcGenRegisterInfo.inc"
46 
47 // Defines symbolic names for the Sparc instructions.
48 //
49 #define GET_INSTRINFO_ENUM
50 #include "SparcGenInstrInfo.inc"
51 
52 #define GET_SUBTARGETINFO_ENUM
53 #include "SparcGenSubtargetInfo.inc"
54 
55 #endif
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::createSparcELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createSparcELFObjectWriter(bool Is64Bit, uint8_t OSABI)
Definition: SparcELFObjectWriter.cpp:138
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:732
T
#define T
Definition: Mips16ISelLowering.cpp:341
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createSparcMCCodeEmitter
MCCodeEmitter * createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: SparcMCCodeEmitter.cpp:255
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
DataTypes.h
llvm::createSparcAsmBackend
MCAsmBackend * createSparcAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: SparcAsmBackend.cpp:324