LLVM  14.0.0git
SparcMCCodeEmitter.cpp
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1 //===-- SparcMCCodeEmitter.cpp - Convert Sparc code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SparcMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "SparcMCExpr.h"
15 #include "SparcMCTargetDesc.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCFixup.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/Casting.h"
31 #include "llvm/Support/Endian.h"
35 #include <cassert>
36 #include <cstdint>
37 
38 using namespace llvm;
39 
40 #define DEBUG_TYPE "mccodeemitter"
41 
42 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
43 
44 namespace {
45 
46 class SparcMCCodeEmitter : public MCCodeEmitter {
47  const MCInstrInfo &MCII;
48  MCContext &Ctx;
49 
50 public:
51  SparcMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
52  : MCII(mcii), Ctx(ctx) {}
53  SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete;
54  SparcMCCodeEmitter &operator=(const SparcMCCodeEmitter &) = delete;
55  ~SparcMCCodeEmitter() override = default;
56 
57  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
59  const MCSubtargetInfo &STI) const override;
60 
61  // getBinaryCodeForInstr - TableGen'erated function for getting the
62  // binary encoding for an instruction.
63  uint64_t getBinaryCodeForInstr(const MCInst &MI,
65  const MCSubtargetInfo &STI) const;
66 
67  /// getMachineOpValue - Return binary encoding of operand. If the machine
68  /// operand requires relocation, record the relocation and return zero.
69  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
71  const MCSubtargetInfo &STI) const;
72  unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
74  const MCSubtargetInfo &STI) const;
75  unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
77  const MCSubtargetInfo &STI) const;
78  unsigned getSImm13OpValue(const MCInst &MI, unsigned OpNo,
80  const MCSubtargetInfo &STI) const;
81  unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
83  const MCSubtargetInfo &STI) const;
84  unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
86  const MCSubtargetInfo &STI) const;
87 
88 private:
89  FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const;
90  void
91  verifyInstructionPredicates(const MCInst &MI,
92  const FeatureBitset &AvailableFeatures) const;
93 };
94 
95 } // end anonymous namespace
96 
97 void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
99  const MCSubtargetInfo &STI) const {
100  verifyInstructionPredicates(MI,
101  computeAvailableFeatures(STI.getFeatureBits()));
102 
103  unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
105  Ctx.getAsmInfo()->isLittleEndian() ? support::little
106  : support::big);
107  unsigned tlsOpNo = 0;
108  switch (MI.getOpcode()) {
109  default: break;
110  case SP::TLS_CALL: tlsOpNo = 1; break;
111  case SP::TLS_ADDrr:
112  case SP::TLS_ADDXrr:
113  case SP::TLS_LDrr:
114  case SP::TLS_LDXrr: tlsOpNo = 3; break;
115  }
116  if (tlsOpNo != 0) {
117  const MCOperand &MO = MI.getOperand(tlsOpNo);
118  uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
119  assert(op == 0 && "Unexpected operand value!");
120  (void)op; // suppress warning.
121  }
122 
123  ++MCNumEmitted; // Keep track of the # of mi's emitted.
124 }
125 
126 unsigned SparcMCCodeEmitter::
127 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
129  const MCSubtargetInfo &STI) const {
130  if (MO.isReg())
131  return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
132 
133  if (MO.isImm())
134  return MO.getImm();
135 
136  assert(MO.isExpr());
137  const MCExpr *Expr = MO.getExpr();
138  if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
139  MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
140  Fixups.push_back(MCFixup::create(0, Expr, Kind));
141  return 0;
142  }
143 
144  int64_t Res;
145  if (Expr->evaluateAsAbsolute(Res))
146  return Res;
147 
148  llvm_unreachable("Unhandled expression!");
149  return 0;
150 }
151 
152 unsigned
153 SparcMCCodeEmitter::getSImm13OpValue(const MCInst &MI, unsigned OpNo,
155  const MCSubtargetInfo &STI) const {
156  const MCOperand &MO = MI.getOperand(OpNo);
157 
158  if (MO.isImm())
159  return MO.getImm();
160 
161  assert(MO.isExpr() &&
162  "getSImm13OpValue expects only expressions or an immediate");
163 
164  const MCExpr *Expr = MO.getExpr();
165 
166  // Constant value, no fixup is needed
167  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
168  return CE->getValue();
169 
171  if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
172  Kind = MCFixupKind(SExpr->getFixupKind());
173  } else {
174  bool IsPic = Ctx.getObjectFileInfo()->isPositionIndependent();
176  : MCFixupKind(Sparc::fixup_sparc_13);
177  }
178 
179  Fixups.push_back(MCFixup::create(0, Expr, Kind));
180  return 0;
181 }
182 
183 unsigned SparcMCCodeEmitter::
184 getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
186  const MCSubtargetInfo &STI) const {
187  const MCOperand &MO = MI.getOperand(OpNo);
188  const MCExpr *Expr = MO.getExpr();
189  const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr);
190 
191  if (MI.getOpcode() == SP::TLS_CALL) {
192  // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in
193  // encodeInstruction.
194 #ifndef NDEBUG
195  // Verify that the callee is actually __tls_get_addr.
196  assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef &&
197  "Unexpected expression in TLS_CALL");
198  const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr());
199  assert(SymExpr->getSymbol().getName() == "__tls_get_addr" &&
200  "Unexpected function for TLS_CALL");
201 #endif
202  return 0;
203  }
204 
206  Fixups.push_back(MCFixup::create(0, Expr, Kind));
207  return 0;
208 }
209 
210 unsigned SparcMCCodeEmitter::
211 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
213  const MCSubtargetInfo &STI) const {
214  const MCOperand &MO = MI.getOperand(OpNo);
215  if (MO.isReg() || MO.isImm())
216  return getMachineOpValue(MI, MO, Fixups, STI);
217 
218  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
220  return 0;
221 }
222 
223 unsigned SparcMCCodeEmitter::
224 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
226  const MCSubtargetInfo &STI) const {
227  const MCOperand &MO = MI.getOperand(OpNo);
228  if (MO.isReg() || MO.isImm())
229  return getMachineOpValue(MI, MO, Fixups, STI);
230 
231  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
233  return 0;
234 }
235 
236 unsigned SparcMCCodeEmitter::
237 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
239  const MCSubtargetInfo &STI) const {
240  const MCOperand &MO = MI.getOperand(OpNo);
241  if (MO.isReg() || MO.isImm())
242  return getMachineOpValue(MI, MO, Fixups, STI);
243 
244  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
246  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
248 
249  return 0;
250 }
251 
252 #define ENABLE_INSTR_PREDICATE_VERIFIER
253 #include "SparcGenMCCodeEmitter.inc"
254 
256  const MCRegisterInfo &MRI,
257  MCContext &Ctx) {
258  return new SparcMCCodeEmitter(MCII, Ctx);
259 }
llvm::Sparc::fixup_sparc_br22
@ fixup_sparc_br22
fixup_sparc_br22 - 22-bit PC relative relocation for branches
Definition: SparcFixupKinds.h:22
llvm::Sparc::fixup_sparc_br19
@ fixup_sparc_br19
fixup_sparc_br19 - 19-bit PC relative relocation for branches on icc/xcc
Definition: SparcFixupKinds.h:26
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::Sparc::fixup_sparc_br16_2
@ fixup_sparc_br16_2
fixup_sparc_bpr - 16-bit fixup for bpr
Definition: SparcFixupKinds.h:29
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
SparcMCTargetDesc.h
MCCodeEmitter.h
op
#define op(i)
Statistic.h
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
ErrorHandling.h
MCObjectFileInfo.h
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::SparcMCExpr
Definition: SparcMCExpr.h:23
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::Sparc::fixup_sparc_br16_14
@ fixup_sparc_br16_14
Definition: SparcFixupKinds.h:30
SubtargetFeature.h
SparcFixupKinds.h
llvm::support::little
@ little
Definition: Endian.h:27
MCContext.h
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
MCSymbol.h
SparcMCExpr.h
MCInst.h
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
getBranchTargetOpValue
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
Definition: ARMMCCodeEmitter.cpp:620
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::MCSymbolRefExpr::getSymbol
const MCSymbol & getSymbol() const
Definition: MCExpr.h:399
llvm::MCSymbol::getName
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:198
llvm::MCExpr::getKind
ExprKind getKind() const
Definition: MCExpr.h:81
llvm::Sparc::fixup_sparc_13
@ fixup_sparc_13
fixup_sparc_13 - 13-bit fixup
Definition: SparcFixupKinds.h:33
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::support::endian::write
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
Definition: Endian.h:97
llvm::MCConstantExpr
Definition: MCExpr.h:144
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
uint64_t
MCRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::createSparcMCCodeEmitter
MCCodeEmitter * createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: SparcMCCodeEmitter.cpp:255
llvm::WinEH::EncodingType::CE
@ CE
Windows NT (Windows on ARM)
llvm::MCSymbolRefExpr
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
llvm::Sparc::fixup_sparc_got13
@ fixup_sparc_got13
fixup_sparc_got13 - 13-bit fixup corresponding to got13(foo)
Definition: SparcFixupKinds.h:73
MCAsmInfo.h
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
MCFixup.h
llvm::SparcMCExpr::getSubExpr
const MCExpr * getSubExpr() const
getSubExpr - Get the child of this expression.
Definition: SparcMCExpr.h:85
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::SparcMCExpr::getFixupKind
Sparc::Fixups getFixupKind() const
getFixupKind - Get the fixup kind of this expression.
Definition: SparcMCExpr.h:88
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
EndianStream.h
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Casting.h
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
SmallVector.h
llvm::MCExpr::SymbolRef
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
raw_ostream.h
llvm::SPISD::TLS_CALL
@ TLS_CALL
Definition: SparcISelLowering.h:49
Endian.h
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::support::big
@ big
Definition: Endian.h:27
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69