LLVM  14.0.0git
HexagonSubtarget.h
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1 //===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the Hexagon specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
14 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
15 
16 #include "HexagonArch.h"
17 #include "HexagonFrameLowering.h"
18 #include "HexagonISelLowering.h"
19 #include "HexagonInstrInfo.h"
20 #include "HexagonRegisterInfo.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/StringRef.h"
27 #include "llvm/Support/Alignment.h"
28 #include <memory>
29 #include <string>
30 #include <vector>
31 
32 #define GET_SUBTARGETINFO_HEADER
33 #include "HexagonGenSubtargetInfo.inc"
34 
35 namespace llvm {
36 
37 class MachineInstr;
38 class SDep;
39 class SUnit;
40 class TargetMachine;
41 class Triple;
42 
44  virtual void anchor();
45 
46  bool UseHVX64BOps = false;
47  bool UseHVX128BOps = false;
48 
49  bool UseAudioOps = false;
50  bool UseCompound = false;
51  bool UseLongCalls = false;
52  bool UseMemops = false;
53  bool UsePackets = false;
54  bool UseNewValueJumps = false;
55  bool UseNewValueStores = false;
56  bool UseSmallData = false;
57  bool UseUnsafeMath = false;
58  bool UseZRegOps = false;
59 
60  bool HasPreV65 = false;
61  bool HasMemNoShuf = false;
62  bool EnableDuplex = false;
63  bool ReservedR19 = false;
64  bool NoreturnStackElim = false;
65 
66 public:
70  /// True if the target should use Back-Skip-Back scheduling. This is the
71  /// default for V60.
73 
75  void apply(ScheduleDAGInstrs *DAG) override;
76  };
78  void apply(ScheduleDAGInstrs *DAG) override;
79  };
81  void apply(ScheduleDAGInstrs *DAG) override;
82  private:
83  bool shouldTFRICallBind(const HexagonInstrInfo &HII,
84  const SUnit &Inst1, const SUnit &Inst2) const;
85  };
87  void apply(ScheduleDAGInstrs *DAG) override;
88  };
89 
90 private:
91  enum HexagonProcFamilyEnum { Others, TinyCore };
92 
93  std::string CPUString;
94  Triple TargetTriple;
95 
96  // The following objects can use the TargetTriple, so they must be
97  // declared after it.
98  HexagonProcFamilyEnum HexagonProcFamily = Others;
99  HexagonInstrInfo InstrInfo;
101  HexagonTargetLowering TLInfo;
103  HexagonFrameLowering FrameLowering;
104  InstrItineraryData InstrItins;
105 
106 public:
107  HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
108  const TargetMachine &TM);
109 
110  const Triple &getTargetTriple() const { return TargetTriple; }
111  bool isEnvironmentMusl() const {
112  return TargetTriple.getEnvironment() == Triple::Musl;
113  }
114 
115  /// getInstrItins - Return the instruction itineraries based on subtarget
116  /// selection.
117  const InstrItineraryData *getInstrItineraryData() const override {
118  return &InstrItins;
119  }
120  const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
121  const HexagonRegisterInfo *getRegisterInfo() const override {
122  return &RegInfo;
123  }
124  const HexagonTargetLowering *getTargetLowering() const override {
125  return &TLInfo;
126  }
127  const HexagonFrameLowering *getFrameLowering() const override {
128  return &FrameLowering;
129  }
131  return &TSInfo;
132  }
133 
135  StringRef FS);
136 
137  /// ParseSubtargetFeatures - Parses features string setting specified
138  /// subtarget options. Definition of function is auto generated by tblgen.
140 
141  bool hasV5Ops() const {
143  }
144  bool hasV5OpsOnly() const {
146  }
147  bool hasV55Ops() const {
149  }
150  bool hasV55OpsOnly() const {
152  }
153  bool hasV60Ops() const {
155  }
156  bool hasV60OpsOnly() const {
158  }
159  bool hasV62Ops() const {
161  }
162  bool hasV62OpsOnly() const {
164  }
165  bool hasV65Ops() const {
167  }
168  bool hasV65OpsOnly() const {
170  }
171  bool hasV66Ops() const {
173  }
174  bool hasV66OpsOnly() const {
176  }
177  bool hasV67Ops() const {
179  }
180  bool hasV67OpsOnly() const {
182  }
183  bool hasV68Ops() const {
185  }
186  bool hasV68OpsOnly() const {
188  }
189 
190  bool useAudioOps() const { return UseAudioOps; }
191  bool useCompound() const { return UseCompound; }
192  bool useLongCalls() const { return UseLongCalls; }
193  bool useMemops() const { return UseMemops; }
194  bool usePackets() const { return UsePackets; }
195  bool useNewValueJumps() const { return UseNewValueJumps; }
196  bool useNewValueStores() const { return UseNewValueStores; }
197  bool useSmallData() const { return UseSmallData; }
198  bool useUnsafeMath() const { return UseUnsafeMath; }
199  bool useZRegOps() const { return UseZRegOps; }
200 
201  bool isTinyCore() const { return HexagonProcFamily == TinyCore; }
202  bool isTinyCoreWithDuplex() const { return isTinyCore() && EnableDuplex; }
203 
204  bool useHVXOps() const {
206  }
207  bool useHVXV60Ops() const {
209  }
210  bool useHVXV62Ops() const {
212  }
213  bool useHVXV65Ops() const {
215  }
216  bool useHVXV66Ops() const {
218  }
219  bool useHVXV67Ops() const {
221  }
222  bool useHVXV68Ops() const {
224  }
225  bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
226  bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
227 
228  bool hasMemNoShuf() const { return HasMemNoShuf; }
229  bool hasReservedR19() const { return ReservedR19; }
230  bool usePredicatedCalls() const;
231 
232  bool noreturnStackElim() const { return NoreturnStackElim; }
233 
234  bool useBSBScheduling() const { return UseBSBScheduling; }
235  bool enableMachineScheduler() const override;
236 
237  // Always use the TargetLowering default scheduler.
238  // FIXME: This will use the vliw scheduler which is probably just hurting
239  // compiler time and will be removed eventually anyway.
240  bool enableMachineSchedDefaultSched() const override { return false; }
241 
242  // For use with PostRAScheduling: get the anti-dependence breaking that should
243  // be performed before post-RA scheduling.
244  AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
245  /// True if the subtarget should run a scheduler after register
246  /// allocation.
247  bool enablePostRAScheduler() const override { return true; }
248 
249  bool enableSubRegLiveness() const override;
250 
251  const std::string &getCPUString () const { return CPUString; }
252 
254  return HexagonArchVersion;
255  }
256 
257  void getPostRAMutations(
258  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
259  const override;
260 
261  void getSMSMutations(
262  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
263  const override;
264 
265  /// Enable use of alias analysis during code generation (during MI
266  /// scheduling, DAGCombine, etc.).
267  bool useAA() const override;
268 
269  /// Perform target specific adjustments to the latency of a schedule
270  /// dependency.
271  void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
272  SDep &Dep) const override;
273 
274  unsigned getVectorLength() const {
275  assert(useHVXOps());
276  if (useHVX64BOps())
277  return 64;
278  if (useHVX128BOps())
279  return 128;
280  llvm_unreachable("Invalid HVX vector length settings");
281  }
282 
284  static MVT Types[] = { MVT::i8, MVT::i16, MVT::i32 };
285  return makeArrayRef(Types);
286  }
287 
288  bool isHVXElementType(MVT Ty, bool IncludeBool = false) const;
289  bool isHVXVectorType(MVT VecTy, bool IncludeBool = false) const;
290  bool isTypeForHVX(Type *VecTy, bool IncludeBool = false) const;
291 
293  if (isHVXVectorType(Ty, true))
294  return Align(getVectorLength());
295  return Align(std::max<unsigned>(1, Ty.getSizeInBits() / 8));
296  }
297 
298  unsigned getL1CacheLineSize() const;
299  unsigned getL1PrefetchDistance() const;
300 
301 private:
302  // Helper function responsible for increasing the latency only.
303  void updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst, SDep &Dep)
304  const;
305  void restoreLatency(SUnit *Src, SUnit *Dst) const;
306  void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
307  bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
308  SmallSet<SUnit*, 4> &ExclSrc, SmallSet<SUnit*, 4> &ExclDst) const;
309 };
310 
311 } // end namespace llvm
312 
313 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
llvm::HexagonSubtarget::useHVX64BOps
bool useHVX64BOps() const
Definition: HexagonSubtarget.h:226
llvm::HexagonSubtarget::hasV68Ops
bool hasV68Ops() const
Definition: HexagonSubtarget.h:183
llvm::HexagonSubtarget::getVectorLength
unsigned getVectorLength() const
Definition: HexagonSubtarget.h:274
llvm::HexagonSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::Hexagon::ArchEnum
ArchEnum
Definition: HexagonDepArch.h:24
llvm::HexagonSubtarget::useNewValueStores
bool useNewValueStores() const
Definition: HexagonSubtarget.h:196
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::HexagonSubtarget::useSmallData
bool useSmallData() const
Definition: HexagonSubtarget.h:197
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
llvm::Hexagon::ArchEnum::NoArch
@ NoArch
llvm::HexagonSubtarget::getFrameLowering
const HexagonFrameLowering * getFrameLowering() const override
Definition: HexagonSubtarget.h:127
llvm::Hexagon::ArchEnum::V65
@ V65
llvm::HexagonSubtarget::useHVXV60Ops
bool useHVXV60Ops() const
Definition: HexagonSubtarget.h:207
StringRef.h
llvm::HexagonSubtarget::HexagonSubtarget
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
Definition: HexagonSubtarget.cpp:78
llvm::HexagonSubtarget::getHexagonArchVersion
const Hexagon::ArchEnum & getHexagonArchVersion() const
Definition: HexagonSubtarget.h:253
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::HexagonSelectionDAGInfo
Definition: HexagonSelectionDAGInfo.h:20
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::HexagonSubtarget::HexagonArchVersion
Hexagon::ArchEnum HexagonArchVersion
Definition: HexagonSubtarget.h:67
llvm::HexagonSubtarget::useAudioOps
bool useAudioOps() const
Definition: HexagonSubtarget.h:190
llvm::HexagonSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Definition: HexagonSubtarget.cpp:659
llvm::Hexagon::ArchEnum::V5
@ V5
HexagonFrameLowering.h
HexagonArch.h
llvm::HexagonSubtarget::useMemops
bool useMemops() const
Definition: HexagonSubtarget.h:193
llvm::HexagonSubtarget::isTypeForHVX
bool isTypeForHVX(Type *VecTy, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:165
llvm::HexagonSubtarget::BankConflictMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:332
llvm::Hexagon::ArchEnum::V66
@ V66
llvm::HexagonSubtarget::getHVXElementTypes
ArrayRef< MVT > getHVXElementTypes() const
Definition: HexagonSubtarget.h:283
llvm::HexagonSubtarget::hasReservedR19
bool hasReservedR19() const
Definition: HexagonSubtarget.h:229
llvm::HexagonSubtarget::getL1CacheLineSize
unsigned getL1CacheLineSize() const
Definition: HexagonSubtarget.cpp:651
llvm::HexagonSubtarget::isEnvironmentMusl
bool isEnvironmentMusl() const
Definition: HexagonSubtarget.h:111
llvm::HexagonSubtarget::getSMSMutations
void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
Definition: HexagonSubtarget.cpp:453
llvm::HexagonSubtarget::UseBSBScheduling
bool UseBSBScheduling
True if the target should use Back-Skip-Back scheduling.
Definition: HexagonSubtarget.h:72
MCInstrItineraries.h
llvm::Triple::Musl
@ Musl
Definition: Triple.h:221
llvm::HexagonSubtarget::hasV55Ops
bool hasV55Ops() const
Definition: HexagonSubtarget.h:147
llvm::HexagonSubtarget::CallMutation
Definition: HexagonSubtarget.h:80
HexagonSelectionDAGInfo.h
llvm::HexagonSubtarget::OptLevel
CodeGenOpt::Level OptLevel
Definition: HexagonSubtarget.h:69
llvm::HexagonSubtarget::enableMachineSchedDefaultSched
bool enableMachineSchedDefaultSched() const override
Definition: HexagonSubtarget.h:240
llvm::HexagonSubtarget::useHVXV66Ops
bool useHVXV66Ops() const
Definition: HexagonSubtarget.h:216
llvm::HexagonSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Definition: HexagonSubtarget.cpp:462
llvm::HexagonSubtarget::useNewValueJumps
bool useNewValueJumps() const
Definition: HexagonSubtarget.h:195
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::HexagonSubtarget::useHVXOps
bool useHVXOps() const
Definition: HexagonSubtarget.h:204
llvm::HexagonSubtarget::getCPUString
const std::string & getCPUString() const
Definition: HexagonSubtarget.h:251
llvm::HexagonSubtarget::hasV65Ops
bool hasV65Ops() const
Definition: HexagonSubtarget.h:165
llvm::Hexagon::ArchEnum::V62
@ V62
llvm::HexagonSubtarget::isTinyCore
bool isTinyCore() const
Definition: HexagonSubtarget.h:201
HexagonGenSubtargetInfo
llvm::HexagonSubtarget::enablePostRAScheduler
bool enablePostRAScheduler() const override
True if the subtarget should run a scheduler after register allocation.
Definition: HexagonSubtarget.h:247
HexagonInstrInfo.h
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::HexagonSubtarget::HVXMemLatencyMutation
Definition: HexagonSubtarget.h:77
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::HexagonSubtarget::isHVXVectorType
bool isHVXVectorType(MVT VecTy, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:139
llvm::HexagonSubtarget::getL1PrefetchDistance
unsigned getL1PrefetchDistance() const
Definition: HexagonSubtarget.cpp:655
llvm::Hexagon::ArchEnum::V67
@ V67
llvm::HexagonSubtarget::getInstrInfo
const HexagonInstrInfo * getInstrInfo() const override
Definition: HexagonSubtarget.h:120
llvm::HexagonSubtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: HexagonSubtarget.h:110
llvm::HexagonSubtarget::hasV62Ops
bool hasV62Ops() const
Definition: HexagonSubtarget.h:159
llvm::HexagonSubtarget::noreturnStackElim
bool noreturnStackElim() const
Definition: HexagonSubtarget.h:232
llvm::HexagonSubtarget::BankConflictMutation
Definition: HexagonSubtarget.h:86
llvm::HexagonSubtarget::useUnsafeMath
bool useUnsafeMath() const
Definition: HexagonSubtarget.h:198
llvm::HexagonSubtarget::usePackets
bool usePackets() const
Definition: HexagonSubtarget.h:194
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::HexagonSubtarget::useAA
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
Definition: HexagonSubtarget.cpp:381
llvm::HexagonSubtarget::getTypeAlignment
Align getTypeAlignment(MVT Ty) const
Definition: HexagonSubtarget.h:292
llvm::HexagonSubtarget::hasV68OpsOnly
bool hasV68OpsOnly() const
Definition: HexagonSubtarget.h:186
llvm::HexagonSubtarget::CallMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:262
llvm::HexagonSubtarget::hasMemNoShuf
bool hasMemNoShuf() const
Definition: HexagonSubtarget.h:228
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
HexagonRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:860
llvm::Hexagon::ArchEnum::V55
@ V55
llvm::HexagonSubtarget::isTinyCoreWithDuplex
bool isTinyCoreWithDuplex() const
Definition: HexagonSubtarget.h:202
llvm::HexagonSubtarget::hasV55OpsOnly
bool hasV55OpsOnly() const
Definition: HexagonSubtarget.h:150
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
HexagonISelLowering.h
llvm::HexagonSubtarget::hasV60OpsOnly
bool hasV60OpsOnly() const
Definition: HexagonSubtarget.h:156
llvm::HexagonSubtarget::usePredicatedCalls
bool usePredicatedCalls() const
Definition: HexagonSubtarget.cpp:468
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::HexagonSubtarget::useHVXV68Ops
bool useHVXV68Ops() const
Definition: HexagonSubtarget.h:222
llvm::HexagonSubtarget::hasV66Ops
bool hasV66Ops() const
Definition: HexagonSubtarget.h:171
ScheduleDAGMutation.h
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
RegInfo
Definition: AMDGPUAsmParser.cpp:2384
llvm::HexagonSubtarget::useLongCalls
bool useLongCalls() const
Definition: HexagonSubtarget.h:192
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::HexagonSubtarget::isHVXElementType
bool isHVXElementType(MVT Ty, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:128
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::HexagonTargetLowering
Definition: HexagonISelLowering.h:105
llvm::HexagonSubtarget::getPostRAMutations
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
Definition: HexagonSubtarget.cpp:446
TargetSubtargetInfo.h
llvm::HexagonSubtarget::useCompound
bool useCompound() const
Definition: HexagonSubtarget.h:191
llvm::HexagonSubtarget::UsrOverflowMutation
Definition: HexagonSubtarget.h:74
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::HexagonSubtarget::hasV5Ops
bool hasV5Ops() const
Definition: HexagonSubtarget.h:141
llvm::SDep
Scheduling dependency.
Definition: ScheduleDAG.h:49
llvm::HexagonSubtarget::hasV66OpsOnly
bool hasV66OpsOnly() const
Definition: HexagonSubtarget.h:174
llvm::HexagonSubtarget::UsrOverflowMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:198
Alignment.h
llvm::HexagonSubtarget::getSelectionDAGInfo
const HexagonSelectionDAGInfo * getSelectionDAGInfo() const override
Definition: HexagonSubtarget.h:130
llvm::HexagonFrameLowering
Definition: HexagonFrameLowering.h:31
llvm::HexagonSubtarget::getRegisterInfo
const HexagonRegisterInfo * getRegisterInfo() const override
Definition: HexagonSubtarget.h:121
llvm::HexagonSubtarget::hasV65OpsOnly
bool hasV65OpsOnly() const
Definition: HexagonSubtarget.h:168
llvm::HexagonSubtarget::initializeSubtargetDependencies
HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
Definition: HexagonSubtarget.cpp:93
llvm::HexagonSubtarget::getTargetLowering
const HexagonTargetLowering * getTargetLowering() const override
Definition: HexagonSubtarget.h:124
llvm::HexagonSubtarget::hasV62OpsOnly
bool hasV62OpsOnly() const
Definition: HexagonSubtarget.h:162
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::HexagonSubtarget::HexagonHVXVersion
Hexagon::ArchEnum HexagonHVXVersion
Definition: HexagonSubtarget.h:68
llvm::HexagonSubtarget::useBSBScheduling
bool useBSBScheduling() const
Definition: HexagonSubtarget.h:234
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::HexagonSubtarget::useHVXV67Ops
bool useHVXV67Ops() const
Definition: HexagonSubtarget.h:219
llvm::HexagonSubtarget::hasV67OpsOnly
bool hasV67OpsOnly() const
Definition: HexagonSubtarget.h:180
llvm::HexagonSubtarget::getAntiDepBreakMode
AntiDepBreakMode getAntiDepBreakMode() const override
Definition: HexagonSubtarget.h:244
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:476
llvm::HexagonSubtarget::getInstrItineraryData
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: HexagonSubtarget.h:117
llvm::HexagonSubtarget::useHVXV65Ops
bool useHVXV65Ops() const
Definition: HexagonSubtarget.h:213
llvm::HexagonSubtarget::hasV67Ops
bool hasV67Ops() const
Definition: HexagonSubtarget.h:177
llvm::Hexagon::ArchEnum::V68
@ V68
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
llvm::HexagonSubtarget::useHVXV62Ops
bool useHVXV62Ops() const
Definition: HexagonSubtarget.h:210
llvm::ScheduleDAGMutation
Mutate the DAG as a postpass after normal DAG building.
Definition: ScheduleDAGMutation.h:22
llvm::Triple::getEnvironment
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:327
llvm::HexagonSubtarget::useHVX128BOps
bool useHVX128BOps() const
Definition: HexagonSubtarget.h:225
llvm::Hexagon::ArchEnum::V60
@ V60
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::HexagonRegisterInfo
Definition: HexagonRegisterInfo.h:29
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::HexagonSubtarget::hasV5OpsOnly
bool hasV5OpsOnly() const
Definition: HexagonSubtarget.h:144
llvm::HexagonSubtarget::useZRegOps
bool useZRegOps() const
Definition: HexagonSubtarget.h:199
llvm::HexagonSubtarget::hasV60Ops
bool hasV60Ops() const
Definition: HexagonSubtarget.h:153
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::HexagonSubtarget::adjustSchedDependency
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep) const override
Perform target specific adjustments to the latency of a schedule dependency.
Definition: HexagonSubtarget.cpp:389
llvm::HexagonSubtarget::HVXMemLatencyMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:211
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
SmallSet.h