LLVM  13.0.0git
HexagonSubtarget.h
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1 //===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the Hexagon specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
14 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
15 
16 #include "HexagonArch.h"
17 #include "HexagonFrameLowering.h"
18 #include "HexagonISelLowering.h"
19 #include "HexagonInstrInfo.h"
20 #include "HexagonRegisterInfo.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/StringRef.h"
27 #include <memory>
28 #include <string>
29 #include <vector>
30 
31 #define GET_SUBTARGETINFO_HEADER
32 #include "HexagonGenSubtargetInfo.inc"
33 
34 namespace llvm {
35 
36 class MachineInstr;
37 class SDep;
38 class SUnit;
39 class TargetMachine;
40 class Triple;
41 
43  virtual void anchor();
44 
45  bool UseHVX64BOps = false;
46  bool UseHVX128BOps = false;
47 
48  bool UseAudioOps = false;
49  bool UseCompound = false;
50  bool UseLongCalls = false;
51  bool UseMemops = false;
52  bool UsePackets = false;
53  bool UseNewValueJumps = false;
54  bool UseNewValueStores = false;
55  bool UseSmallData = false;
56  bool UseUnsafeMath = false;
57  bool UseZRegOps = false;
58 
59  bool HasPreV65 = false;
60  bool HasMemNoShuf = false;
61  bool EnableDuplex = false;
62  bool ReservedR19 = false;
63  bool NoreturnStackElim = false;
64 
65 public:
69  /// True if the target should use Back-Skip-Back scheduling. This is the
70  /// default for V60.
72 
74  void apply(ScheduleDAGInstrs *DAG) override;
75  };
77  void apply(ScheduleDAGInstrs *DAG) override;
78  };
80  void apply(ScheduleDAGInstrs *DAG) override;
81  private:
82  bool shouldTFRICallBind(const HexagonInstrInfo &HII,
83  const SUnit &Inst1, const SUnit &Inst2) const;
84  };
86  void apply(ScheduleDAGInstrs *DAG) override;
87  };
88 
89 private:
90  enum HexagonProcFamilyEnum { Others, TinyCore };
91 
92  std::string CPUString;
93  Triple TargetTriple;
94 
95  // The following objects can use the TargetTriple, so they must be
96  // declared after it.
97  HexagonProcFamilyEnum HexagonProcFamily = Others;
98  HexagonInstrInfo InstrInfo;
100  HexagonTargetLowering TLInfo;
102  HexagonFrameLowering FrameLowering;
103  InstrItineraryData InstrItins;
104 
105 public:
106  HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
107  const TargetMachine &TM);
108 
109  const Triple &getTargetTriple() const { return TargetTriple; }
110  bool isEnvironmentMusl() const {
111  return TargetTriple.getEnvironment() == Triple::Musl;
112  }
113 
114  /// getInstrItins - Return the instruction itineraries based on subtarget
115  /// selection.
116  const InstrItineraryData *getInstrItineraryData() const override {
117  return &InstrItins;
118  }
119  const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
120  const HexagonRegisterInfo *getRegisterInfo() const override {
121  return &RegInfo;
122  }
123  const HexagonTargetLowering *getTargetLowering() const override {
124  return &TLInfo;
125  }
126  const HexagonFrameLowering *getFrameLowering() const override {
127  return &FrameLowering;
128  }
130  return &TSInfo;
131  }
132 
134  StringRef FS);
135 
136  /// ParseSubtargetFeatures - Parses features string setting specified
137  /// subtarget options. Definition of function is auto generated by tblgen.
139 
140  bool hasV5Ops() const {
142  }
143  bool hasV5OpsOnly() const {
145  }
146  bool hasV55Ops() const {
148  }
149  bool hasV55OpsOnly() const {
151  }
152  bool hasV60Ops() const {
154  }
155  bool hasV60OpsOnly() const {
157  }
158  bool hasV62Ops() const {
160  }
161  bool hasV62OpsOnly() const {
163  }
164  bool hasV65Ops() const {
166  }
167  bool hasV65OpsOnly() const {
169  }
170  bool hasV66Ops() const {
172  }
173  bool hasV66OpsOnly() const {
175  }
176  bool hasV67Ops() const {
178  }
179  bool hasV67OpsOnly() const {
181  }
182  bool hasV68Ops() const {
184  }
185  bool hasV68OpsOnly() const {
187  }
188 
189  bool useAudioOps() const { return UseAudioOps; }
190  bool useCompound() const { return UseCompound; }
191  bool useLongCalls() const { return UseLongCalls; }
192  bool useMemops() const { return UseMemops; }
193  bool usePackets() const { return UsePackets; }
194  bool useNewValueJumps() const { return UseNewValueJumps; }
195  bool useNewValueStores() const { return UseNewValueStores; }
196  bool useSmallData() const { return UseSmallData; }
197  bool useUnsafeMath() const { return UseUnsafeMath; }
198  bool useZRegOps() const { return UseZRegOps; }
199 
200  bool isTinyCore() const { return HexagonProcFamily == TinyCore; }
201  bool isTinyCoreWithDuplex() const { return isTinyCore() && EnableDuplex; }
202 
203  bool useHVXOps() const {
205  }
206  bool useHVXV60Ops() const {
208  }
209  bool useHVXV62Ops() const {
211  }
212  bool useHVXV65Ops() const {
214  }
215  bool useHVXV66Ops() const {
217  }
218  bool useHVXV67Ops() const {
220  }
221  bool useHVXV68Ops() const {
223  }
224  bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
225  bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
226 
227  bool hasMemNoShuf() const { return HasMemNoShuf; }
228  bool hasReservedR19() const { return ReservedR19; }
229  bool usePredicatedCalls() const;
230 
231  bool noreturnStackElim() const { return NoreturnStackElim; }
232 
233  bool useBSBScheduling() const { return UseBSBScheduling; }
234  bool enableMachineScheduler() const override;
235 
236  // Always use the TargetLowering default scheduler.
237  // FIXME: This will use the vliw scheduler which is probably just hurting
238  // compiler time and will be removed eventually anyway.
239  bool enableMachineSchedDefaultSched() const override { return false; }
240 
241  // For use with PostRAScheduling: get the anti-dependence breaking that should
242  // be performed before post-RA scheduling.
243  AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
244  /// True if the subtarget should run a scheduler after register
245  /// allocation.
246  bool enablePostRAScheduler() const override { return true; }
247 
248  bool enableSubRegLiveness() const override;
249 
250  const std::string &getCPUString () const { return CPUString; }
251 
253  return HexagonArchVersion;
254  }
255 
256  void getPostRAMutations(
257  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
258  const override;
259 
260  void getSMSMutations(
261  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
262  const override;
263 
264  /// Enable use of alias analysis during code generation (during MI
265  /// scheduling, DAGCombine, etc.).
266  bool useAA() const override;
267 
268  /// Perform target specific adjustments to the latency of a schedule
269  /// dependency.
270  void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
271  SDep &Dep) const override;
272 
273  unsigned getVectorLength() const {
274  assert(useHVXOps());
275  if (useHVX64BOps())
276  return 64;
277  if (useHVX128BOps())
278  return 128;
279  llvm_unreachable("Invalid HVX vector length settings");
280  }
281 
283  static MVT Types[] = { MVT::i8, MVT::i16, MVT::i32 };
284  return makeArrayRef(Types);
285  }
286 
287  bool isHVXElementType(MVT Ty, bool IncludeBool = false) const;
288  bool isHVXVectorType(MVT VecTy, bool IncludeBool = false) const;
289  bool isTypeForHVX(Type *VecTy, bool IncludeBool = false) const;
290 
291  unsigned getTypeAlignment(MVT Ty) const {
292  if (isHVXVectorType(Ty, true))
293  return getVectorLength();
294  return Ty.getSizeInBits() / 8;
295  }
296 
297  unsigned getL1CacheLineSize() const;
298  unsigned getL1PrefetchDistance() const;
299 
300 private:
301  // Helper function responsible for increasing the latency only.
302  void updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst, SDep &Dep)
303  const;
304  void restoreLatency(SUnit *Src, SUnit *Dst) const;
305  void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
306  bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
307  SmallSet<SUnit*, 4> &ExclSrc, SmallSet<SUnit*, 4> &ExclDst) const;
308 };
309 
310 } // end namespace llvm
311 
312 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
llvm::HexagonSubtarget::useHVX64BOps
bool useHVX64BOps() const
Definition: HexagonSubtarget.h:225
llvm::HexagonSubtarget::hasV68Ops
bool hasV68Ops() const
Definition: HexagonSubtarget.h:182
llvm::HexagonSubtarget::getVectorLength
unsigned getVectorLength() const
Definition: HexagonSubtarget.h:273
llvm::HexagonSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::Hexagon::ArchEnum
ArchEnum
Definition: HexagonDepArch.h:24
llvm::HexagonSubtarget::useNewValueStores
bool useNewValueStores() const
Definition: HexagonSubtarget.h:195
llvm
Definition: AllocatorList.h:23
llvm::HexagonSubtarget::useSmallData
bool useSmallData() const
Definition: HexagonSubtarget.h:196
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
llvm::Hexagon::ArchEnum::NoArch
@ NoArch
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::HexagonSubtarget::getFrameLowering
const HexagonFrameLowering * getFrameLowering() const override
Definition: HexagonSubtarget.h:126
llvm::Hexagon::ArchEnum::V65
@ V65
llvm::HexagonSubtarget::useHVXV60Ops
bool useHVXV60Ops() const
Definition: HexagonSubtarget.h:206
StringRef.h
llvm::HexagonSubtarget::HexagonSubtarget
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
Definition: HexagonSubtarget.cpp:78
llvm::HexagonSubtarget::getHexagonArchVersion
const Hexagon::ArchEnum & getHexagonArchVersion() const
Definition: HexagonSubtarget.h:252
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::HexagonSelectionDAGInfo
Definition: HexagonSelectionDAGInfo.h:20
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::HexagonSubtarget::HexagonArchVersion
Hexagon::ArchEnum HexagonArchVersion
Definition: HexagonSubtarget.h:66
llvm::HexagonSubtarget::useAudioOps
bool useAudioOps() const
Definition: HexagonSubtarget.h:189
llvm::HexagonSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Definition: HexagonSubtarget.cpp:659
llvm::Hexagon::ArchEnum::V5
@ V5
HexagonFrameLowering.h
HexagonArch.h
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::HexagonSubtarget::useMemops
bool useMemops() const
Definition: HexagonSubtarget.h:192
llvm::HexagonSubtarget::isTypeForHVX
bool isTypeForHVX(Type *VecTy, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:165
llvm::HexagonSubtarget::BankConflictMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:332
llvm::Hexagon::ArchEnum::V66
@ V66
llvm::HexagonSubtarget::getTypeAlignment
unsigned getTypeAlignment(MVT Ty) const
Definition: HexagonSubtarget.h:291
llvm::HexagonSubtarget::getHVXElementTypes
ArrayRef< MVT > getHVXElementTypes() const
Definition: HexagonSubtarget.h:282
llvm::HexagonSubtarget::hasReservedR19
bool hasReservedR19() const
Definition: HexagonSubtarget.h:228
llvm::HexagonSubtarget::getL1CacheLineSize
unsigned getL1CacheLineSize() const
Definition: HexagonSubtarget.cpp:651
llvm::HexagonSubtarget::isEnvironmentMusl
bool isEnvironmentMusl() const
Definition: HexagonSubtarget.h:110
llvm::HexagonSubtarget::getSMSMutations
void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
Definition: HexagonSubtarget.cpp:453
llvm::HexagonSubtarget::UseBSBScheduling
bool UseBSBScheduling
True if the target should use Back-Skip-Back scheduling.
Definition: HexagonSubtarget.h:71
MCInstrItineraries.h
llvm::Triple::Musl
@ Musl
Definition: Triple.h:218
llvm::HexagonSubtarget::hasV55Ops
bool hasV55Ops() const
Definition: HexagonSubtarget.h:146
llvm::HexagonSubtarget::CallMutation
Definition: HexagonSubtarget.h:79
HexagonSelectionDAGInfo.h
llvm::HexagonSubtarget::OptLevel
CodeGenOpt::Level OptLevel
Definition: HexagonSubtarget.h:68
llvm::HexagonSubtarget::enableMachineSchedDefaultSched
bool enableMachineSchedDefaultSched() const override
Definition: HexagonSubtarget.h:239
llvm::HexagonSubtarget::useHVXV66Ops
bool useHVXV66Ops() const
Definition: HexagonSubtarget.h:215
llvm::HexagonSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Definition: HexagonSubtarget.cpp:462
llvm::HexagonSubtarget::useNewValueJumps
bool useNewValueJumps() const
Definition: HexagonSubtarget.h:194
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::HexagonSubtarget::useHVXOps
bool useHVXOps() const
Definition: HexagonSubtarget.h:203
llvm::HexagonSubtarget::getCPUString
const std::string & getCPUString() const
Definition: HexagonSubtarget.h:250
llvm::HexagonSubtarget::hasV65Ops
bool hasV65Ops() const
Definition: HexagonSubtarget.h:164
llvm::Hexagon::ArchEnum::V62
@ V62
llvm::HexagonSubtarget::isTinyCore
bool isTinyCore() const
Definition: HexagonSubtarget.h:200
HexagonGenSubtargetInfo
llvm::HexagonSubtarget::enablePostRAScheduler
bool enablePostRAScheduler() const override
True if the subtarget should run a scheduler after register allocation.
Definition: HexagonSubtarget.h:246
HexagonInstrInfo.h
llvm::HexagonSubtarget::HVXMemLatencyMutation
Definition: HexagonSubtarget.h:76
llvm::HexagonSubtarget::isHVXVectorType
bool isHVXVectorType(MVT VecTy, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:139
llvm::HexagonSubtarget::getL1PrefetchDistance
unsigned getL1PrefetchDistance() const
Definition: HexagonSubtarget.cpp:655
llvm::Hexagon::ArchEnum::V67
@ V67
llvm::HexagonSubtarget::getInstrInfo
const HexagonInstrInfo * getInstrInfo() const override
Definition: HexagonSubtarget.h:119
llvm::HexagonSubtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: HexagonSubtarget.h:109
llvm::HexagonSubtarget::hasV62Ops
bool hasV62Ops() const
Definition: HexagonSubtarget.h:158
llvm::HexagonSubtarget::noreturnStackElim
bool noreturnStackElim() const
Definition: HexagonSubtarget.h:231
llvm::HexagonSubtarget::BankConflictMutation
Definition: HexagonSubtarget.h:85
llvm::HexagonSubtarget::useUnsafeMath
bool useUnsafeMath() const
Definition: HexagonSubtarget.h:197
llvm::HexagonSubtarget::usePackets
bool usePackets() const
Definition: HexagonSubtarget.h:193
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::HexagonSubtarget::useAA
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
Definition: HexagonSubtarget.cpp:381
llvm::HexagonSubtarget::hasV68OpsOnly
bool hasV68OpsOnly() const
Definition: HexagonSubtarget.h:185
llvm::HexagonSubtarget::CallMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:262
llvm::HexagonSubtarget::hasMemNoShuf
bool hasMemNoShuf() const
Definition: HexagonSubtarget.h:227
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:41
HexagonRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:821
llvm::Hexagon::ArchEnum::V55
@ V55
llvm::HexagonSubtarget::isTinyCoreWithDuplex
bool isTinyCoreWithDuplex() const
Definition: HexagonSubtarget.h:201
llvm::HexagonSubtarget::hasV55OpsOnly
bool hasV55OpsOnly() const
Definition: HexagonSubtarget.h:149
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
HexagonISelLowering.h
llvm::HexagonSubtarget::hasV60OpsOnly
bool hasV60OpsOnly() const
Definition: HexagonSubtarget.h:155
llvm::HexagonSubtarget::usePredicatedCalls
bool usePredicatedCalls() const
Definition: HexagonSubtarget.cpp:468
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::HexagonSubtarget::useHVXV68Ops
bool useHVXV68Ops() const
Definition: HexagonSubtarget.h:221
llvm::HexagonSubtarget::hasV66Ops
bool hasV66Ops() const
Definition: HexagonSubtarget.h:170
ScheduleDAGMutation.h
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
RegInfo
Definition: AMDGPUAsmParser.cpp:2356
llvm::HexagonSubtarget::useLongCalls
bool useLongCalls() const
Definition: HexagonSubtarget.h:191
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::HexagonSubtarget::isHVXElementType
bool isHVXElementType(MVT Ty, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:128
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::HexagonTargetLowering
Definition: HexagonISelLowering.h:105
llvm::HexagonSubtarget::getPostRAMutations
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
Definition: HexagonSubtarget.cpp:446
TargetSubtargetInfo.h
llvm::HexagonSubtarget::useCompound
bool useCompound() const
Definition: HexagonSubtarget.h:190
llvm::HexagonSubtarget::UsrOverflowMutation
Definition: HexagonSubtarget.h:73
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::HexagonSubtarget::hasV5Ops
bool hasV5Ops() const
Definition: HexagonSubtarget.h:140
llvm::SDep
Scheduling dependency.
Definition: ScheduleDAG.h:49
llvm::HexagonSubtarget::hasV66OpsOnly
bool hasV66OpsOnly() const
Definition: HexagonSubtarget.h:173
llvm::HexagonSubtarget::UsrOverflowMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:198
llvm::HexagonSubtarget::getSelectionDAGInfo
const HexagonSelectionDAGInfo * getSelectionDAGInfo() const override
Definition: HexagonSubtarget.h:129
llvm::HexagonFrameLowering
Definition: HexagonFrameLowering.h:31
llvm::HexagonSubtarget::getRegisterInfo
const HexagonRegisterInfo * getRegisterInfo() const override
Definition: HexagonSubtarget.h:120
llvm::HexagonSubtarget::hasV65OpsOnly
bool hasV65OpsOnly() const
Definition: HexagonSubtarget.h:167
llvm::HexagonSubtarget::initializeSubtargetDependencies
HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
Definition: HexagonSubtarget.cpp:93
llvm::HexagonSubtarget::getTargetLowering
const HexagonTargetLowering * getTargetLowering() const override
Definition: HexagonSubtarget.h:123
llvm::HexagonSubtarget::hasV62OpsOnly
bool hasV62OpsOnly() const
Definition: HexagonSubtarget.h:161
llvm::HexagonSubtarget::HexagonHVXVersion
Hexagon::ArchEnum HexagonHVXVersion
Definition: HexagonSubtarget.h:67
llvm::HexagonSubtarget::useBSBScheduling
bool useBSBScheduling() const
Definition: HexagonSubtarget.h:233
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:43
llvm::HexagonSubtarget::useHVXV67Ops
bool useHVXV67Ops() const
Definition: HexagonSubtarget.h:218
llvm::HexagonSubtarget::hasV67OpsOnly
bool hasV67OpsOnly() const
Definition: HexagonSubtarget.h:179
llvm::HexagonSubtarget::getAntiDepBreakMode
AntiDepBreakMode getAntiDepBreakMode() const override
Definition: HexagonSubtarget.h:243
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:474
llvm::HexagonSubtarget::getInstrItineraryData
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: HexagonSubtarget.h:116
llvm::HexagonSubtarget::useHVXV65Ops
bool useHVXV65Ops() const
Definition: HexagonSubtarget.h:212
llvm::HexagonSubtarget::hasV67Ops
bool hasV67Ops() const
Definition: HexagonSubtarget.h:176
llvm::Hexagon::ArchEnum::V68
@ V68
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:42
llvm::HexagonSubtarget::useHVXV62Ops
bool useHVXV62Ops() const
Definition: HexagonSubtarget.h:209
llvm::ScheduleDAGMutation
Mutate the DAG as a postpass after normal DAG building.
Definition: ScheduleDAGMutation.h:22
llvm::Triple::getEnvironment
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:325
llvm::HexagonSubtarget::useHVX128BOps
bool useHVX128BOps() const
Definition: HexagonSubtarget.h:224
llvm::Hexagon::ArchEnum::V60
@ V60
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:42
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::HexagonRegisterInfo
Definition: HexagonRegisterInfo.h:29
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::HexagonSubtarget::hasV5OpsOnly
bool hasV5OpsOnly() const
Definition: HexagonSubtarget.h:143
llvm::HexagonSubtarget::useZRegOps
bool useZRegOps() const
Definition: HexagonSubtarget.h:198
llvm::HexagonSubtarget::hasV60Ops
bool hasV60Ops() const
Definition: HexagonSubtarget.h:152
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::HexagonSubtarget::adjustSchedDependency
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep) const override
Perform target specific adjustments to the latency of a schedule dependency.
Definition: HexagonSubtarget.cpp:389
llvm::HexagonSubtarget::HVXMemLatencyMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:211
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
SmallSet.h