LLVM 20.0.0git
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llvm::RegisterClassInfo Class Reference

#include "llvm/CodeGen/RegisterClassInfo.h"

Public Member Functions

 RegisterClassInfo ()
 
void runOnMachineFunction (const MachineFunction &MF)
 runOnFunction - Prepare to answer questions about MF.
 
unsigned getNumAllocatableRegs (const TargetRegisterClass *RC) const
 getNumAllocatableRegs - Returns the number of actually allocatable registers in RC in the current function.
 
ArrayRef< MCPhysReggetOrder (const TargetRegisterClass *RC) const
 getOrder - Returns the preferred allocation order for RC.
 
bool isProperSubClass (const TargetRegisterClass *RC) const
 isProperSubClass - Returns true if RC has a legal super-class with more allocatable registers.
 
MCRegister getLastCalleeSavedAlias (MCRegister PhysReg) const
 getLastCalleeSavedAlias - Returns the last callee saved register that overlaps PhysReg, or NoRegister if PhysReg doesn't overlap a CalleeSavedAliases.
 
uint8_t getMinCost (const TargetRegisterClass *RC) const
 Get the minimum register cost in RC's allocation order.
 
unsigned getLastCostChange (const TargetRegisterClass *RC) const
 Get the position of the last cost change in getOrder(RC).
 
unsigned getRegPressureSetLimit (unsigned Idx) const
 Get the register unit limit for the given pressure set index.
 

Protected Member Functions

unsigned computePSetLimit (unsigned Idx) const
 This is not accurate because two overlapping register sets may have some nonoverlapping reserved registers.
 

Detailed Description

Definition at line 29 of file RegisterClassInfo.h.

Constructor & Destructor Documentation

◆ RegisterClassInfo()

RegisterClassInfo::RegisterClassInfo ( )
default

Member Function Documentation

◆ computePSetLimit()

unsigned RegisterClassInfo::computePSetLimit ( unsigned  Idx) const
protected

This is not accurate because two overlapping register sets may have some nonoverlapping reserved registers.

However, computing the allocation order for all register classes would be too expensive.

Definition at line 202 of file RegisterClassInfo.cpp.

References assert(), llvm::CallingConv::C, getNumAllocatableRegs(), llvm::TargetRegisterClass::getNumRegs(), llvm::TargetRegisterInfo::getRegClassPressureSets(), llvm::TargetRegisterInfo::getRegClassWeight(), llvm::TargetRegisterInfo::getRegPressureSetLimit(), Idx, llvm::TargetRegisterInfo::regclasses(), llvm::RegClassWeight::RegWeight, and llvm::RegClassWeight::WeightLimit.

Referenced by getRegPressureSetLimit().

◆ getLastCalleeSavedAlias()

MCRegister llvm::RegisterClassInfo::getLastCalleeSavedAlias ( MCRegister  PhysReg) const
inline

getLastCalleeSavedAlias - Returns the last callee saved register that overlaps PhysReg, or NoRegister if PhysReg doesn't overlap a CalleeSavedAliases.

Definition at line 118 of file RegisterClassInfo.h.

References llvm::MCRegUnitIterator::isValid(), and TRI.

Referenced by llvm::RegAllocEvictionAdvisor::canAllocatePhysReg(), and llvm::RegAllocEvictionAdvisor::isUnusedCalleeSavedReg().

◆ getLastCostChange()

unsigned llvm::RegisterClassInfo::getLastCostChange ( const TargetRegisterClass RC) const
inline

Get the position of the last cost change in getOrder(RC).

All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the same cost according to RegCosts[Reg].

Definition at line 139 of file RegisterClassInfo.h.

Referenced by llvm::RegAllocEvictionAdvisor::getOrderLimit().

◆ getMinCost()

uint8_t llvm::RegisterClassInfo::getMinCost ( const TargetRegisterClass RC) const
inline

Get the minimum register cost in RC's allocation order.

This is the smallest value in RegCosts[Reg] for all the registers in getOrder(RC).

Definition at line 131 of file RegisterClassInfo.h.

Referenced by llvm::RegAllocEvictionAdvisor::getOrderLimit().

◆ getNumAllocatableRegs()

unsigned llvm::RegisterClassInfo::getNumAllocatableRegs ( const TargetRegisterClass RC) const
inline

getNumAllocatableRegs - Returns the number of actually allocatable registers in RC in the current function.

Definition at line 94 of file RegisterClassInfo.h.

Referenced by computePSetLimit(), getNumAllocatableRegsForConstraints(), llvm::GCNSchedStrategy::initialize(), and llvm::GenericScheduler::initPolicy().

◆ getOrder()

ArrayRef< MCPhysReg > llvm::RegisterClassInfo::getOrder ( const TargetRegisterClass RC) const
inline

getOrder - Returns the preferred allocation order for RC.

The order contains no reserved registers, and registers that alias callee saved registers come last.

Definition at line 101 of file RegisterClassInfo.h.

Referenced by llvm::RegAllocBase::allocatePhysRegs(), and llvm::AllocationOrder::create().

◆ getRegPressureSetLimit()

unsigned llvm::RegisterClassInfo::getRegPressureSetLimit ( unsigned  Idx) const
inline

Get the register unit limit for the given pressure set index.

RegisterClassInfo adjusts this limit for reserved registers.

Definition at line 146 of file RegisterClassInfo.h.

References computePSetLimit(), and Idx.

Referenced by computeExcessPressureDelta(), llvm::RegPressureTracker::getUpwardPressureDelta(), llvm::ConvergingVLIWScheduler::initialize(), llvm::ScheduleDAGMILive::initRegPressure(), and llvm::ScheduleDAGMILive::updateScheduledPressure().

◆ isProperSubClass()

bool llvm::RegisterClassInfo::isProperSubClass ( const TargetRegisterClass RC) const
inline

isProperSubClass - Returns true if RC has a legal super-class with more allocatable registers.

Register classes like GR32_NOSP are not proper sub-classes because esp is not allocatable. Similarly, tGPR is not a proper sub-class in Thumb mode because the GPR super-class is not legal.

Definition at line 111 of file RegisterClassInfo.h.

◆ runOnMachineFunction()

void RegisterClassInfo::runOnMachineFunction ( const MachineFunction MF)

The documentation for this class was generated from the following files: