LLVM  13.0.0git
SIRegisterInfo.cpp
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1 //===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// SI implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SIRegisterInfo.h"
15 #include "AMDGPU.h"
16 #include "AMDGPURegisterBankInfo.h"
17 #include "GCNSubtarget.h"
20 #include "SIMachineFunctionInfo.h"
24 
25 using namespace llvm;
26 
27 #define GET_REGINFO_TARGET_DESC
28 #include "AMDGPUGenRegisterInfo.inc"
29 
31  "amdgpu-spill-sgpr-to-vgpr",
32  cl::desc("Enable spilling VGPRs to SGPRs"),
34  cl::init(true));
35 
36 std::array<std::vector<int16_t>, 16> SIRegisterInfo::RegSplitParts;
37 std::array<std::array<uint16_t, 32>, 9> SIRegisterInfo::SubRegFromChannelTable;
38 
39 // Map numbers of DWORDs to indexes in SubRegFromChannelTable.
40 // Valid indexes are shifted 1, such that a 0 mapping means unsupported.
41 // e.g. for 8 DWORDs (256-bit), SubRegFromChannelTableWidthMap[8] = 8,
42 // meaning index 7 in SubRegFromChannelTable.
43 static const std::array<unsigned, 17> SubRegFromChannelTableWidthMap = {
44  0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 9};
45 
46 namespace llvm {
47 
48 // A temporary struct to spill SGPRs.
49 // This is mostly to spill SGPRs to memory. Spilling SGPRs into VGPR lanes emits
50 // just v_writelane and v_readlane.
51 //
52 // When spilling to memory, the SGPRs are written into VGPR lanes and the VGPR
53 // is saved to scratch (or the other way around for loads).
54 // For this, a VGPR is required where the needed lanes can be clobbered. The
55 // RegScavenger can provide a VGPR where currently active lanes can be
56 // clobbered, but we still need to save inactive lanes.
57 // The high-level steps are:
58 // - Try to scavenge SGPR(s) to save exec
59 // - Try to scavenge VGPR
60 // - Save needed, all or inactive lanes of a TmpVGPR
61 // - Spill/Restore SGPRs using TmpVGPR
62 // - Restore TmpVGPR
63 //
64 // To save all lanes of TmpVGPR, exec needs to be saved and modified. If we
65 // cannot scavenge temporary SGPRs to save exec, we use the following code:
66 // buffer_store_dword TmpVGPR ; only if active lanes need to be saved
67 // s_not exec, exec
68 // buffer_store_dword TmpVGPR ; save inactive lanes
69 // s_not exec, exec
71  struct PerVGPRData {
72  unsigned PerVGPR;
73  unsigned NumVGPRs;
74  int64_t VGPRLanes;
75  };
76 
77  // The SGPR to save
81  unsigned NumSubRegs;
82  bool IsKill;
83  const DebugLoc &DL;
84 
85  /* When spilling to stack */
86  // The SGPRs are written into this VGPR, which is then written to scratch
87  // (or vice versa for loads).
88  Register TmpVGPR = AMDGPU::NoRegister;
89  // Temporary spill slot to save TmpVGPR to.
90  int TmpVGPRIndex = 0;
91  // If TmpVGPR is live before the spill or if it is scavenged.
92  bool TmpVGPRLive = false;
93  // Scavenged SGPR to save EXEC.
94  Register SavedExecReg = AMDGPU::NoRegister;
95  // Stack index to write the SGPRs to.
96  int Index;
97  unsigned EltSize = 4;
98 
103  const SIInstrInfo &TII;
105  bool IsWave32;
107  unsigned MovOpc;
108  unsigned NotOpc;
109 
112  RegScavenger *RS)
113  : SuperReg(MI->getOperand(0).getReg()), MI(MI),
114  IsKill(MI->getOperand(0).isKill()), DL(MI->getDebugLoc()), Index(Index),
115  RS(RS), MBB(*MI->getParent()), MF(*MBB.getParent()),
116  MFI(*MF.getInfo<SIMachineFunctionInfo>()), TII(TII), TRI(TRI),
117  IsWave32(IsWave32) {
121 
122  if (IsWave32) {
123  ExecReg = AMDGPU::EXEC_LO;
124  MovOpc = AMDGPU::S_MOV_B32;
125  NotOpc = AMDGPU::S_NOT_B32;
126  } else {
127  ExecReg = AMDGPU::EXEC;
128  MovOpc = AMDGPU::S_MOV_B64;
129  NotOpc = AMDGPU::S_NOT_B64;
130  }
131 
132  assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
133  assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI &&
134  SuperReg != AMDGPU::EXEC && "exec should never spill");
135  }
136 
139  Data.PerVGPR = IsWave32 ? 32 : 64;
140  Data.NumVGPRs = (NumSubRegs + (Data.PerVGPR - 1)) / Data.PerVGPR;
141  Data.VGPRLanes = (1LL << std::min(Data.PerVGPR, NumSubRegs)) - 1LL;
142  return Data;
143  }
144 
145  // Tries to scavenge SGPRs to save EXEC and a VGPR. Uses v0 if no VGPR is
146  // free.
147  // Writes these instructions if an SGPR can be scavenged:
148  // s_mov_b64 s[6:7], exec ; Save exec
149  // s_mov_b64 exec, 3 ; Wanted lanemask
150  // buffer_store_dword v1 ; Write scavenged VGPR to emergency slot
151  //
152  // Writes these instructions if no SGPR can be scavenged:
153  // buffer_store_dword v0 ; Only if no free VGPR was found
154  // s_not_b64 exec, exec
155  // buffer_store_dword v0 ; Save inactive lanes
156  // ; exec stays inverted, it is flipped back in
157  // ; restore.
158  void prepare() {
159  // Scavenged temporary VGPR to use. It must be scavenged once for any number
160  // of spilled subregs.
161  // FIXME: The liveness analysis is limited and does not tell if a register
162  // is in use in lanes that are currently inactive. We can never be sure if
163  // a register as actually in use in another lane, so we need to save all
164  // used lanes of the chosen VGPR.
165  assert(RS && "Cannot spill SGPR to memory without RegScavenger");
166  TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0, false);
167 
168  // Reserve temporary stack slot
170  if (TmpVGPR) {
171  // Found a register that is dead in the currently active lanes, we only
172  // need to spill inactive lanes.
173  TmpVGPRLive = false;
174  } else {
175  // Pick v0 because it doesn't make a difference.
176  TmpVGPR = AMDGPU::VGPR0;
177  TmpVGPRLive = true;
178  }
179 
180  // Try to scavenge SGPRs to save exec
181  assert(!SavedExecReg && "Exec is already saved, refuse to save again");
182  const TargetRegisterClass &RC =
183  IsWave32 ? AMDGPU::SGPR_32RegClass : AMDGPU::SGPR_64RegClass;
185  SavedExecReg = RS->scavengeRegister(&RC, MI, 0, false);
186 
187  int64_t VGPRLanes = getPerVGPRData().VGPRLanes;
188 
189  if (SavedExecReg) {
191  // Set exec to needed lanes
193  auto I = BuildMI(MBB, MI, DL, TII.get(MovOpc), ExecReg).addImm(VGPRLanes);
194  if (!TmpVGPRLive)
196  // Spill needed lanes
197  TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ false);
198  } else {
199  // Spill active lanes
200  if (TmpVGPRLive)
201  TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ false,
202  /*IsKill*/ false);
203  // Spill inactive lanes
204  auto I = BuildMI(MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
205  if (!TmpVGPRLive)
207  TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ false);
208  }
209  }
210 
211  // Writes these instructions if an SGPR can be scavenged:
212  // buffer_load_dword v1 ; Write scavenged VGPR to emergency slot
213  // s_waitcnt vmcnt(0) ; If a free VGPR was found
214  // s_mov_b64 exec, s[6:7] ; Save exec
215  //
216  // Writes these instructions if no SGPR can be scavenged:
217  // buffer_load_dword v0 ; Restore inactive lanes
218  // s_waitcnt vmcnt(0) ; If a free VGPR was found
219  // s_not_b64 exec, exec
220  // buffer_load_dword v0 ; Only if no free VGPR was found
221  void restore() {
222  if (SavedExecReg) {
223  // Restore used lanes
224  TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ true,
225  /*IsKill*/ false);
226  // Restore exec
227  auto I = BuildMI(MBB, MI, DL, TII.get(MovOpc), ExecReg)
229  // Add an implicit use of the load so it is not dead.
230  // FIXME This inserts an unnecessary waitcnt
231  if (!TmpVGPRLive) {
233  }
234  } else {
235  // Restore inactive lanes
236  TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ true,
237  /*IsKill*/ false);
238  auto I = BuildMI(MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
239  if (!TmpVGPRLive) {
241  }
242  // Restore active lanes
243  if (TmpVGPRLive)
244  TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ true);
245  }
246  }
247 
248  // Write TmpVGPR to memory or read TmpVGPR from memory.
249  // Either using a single buffer_load/store if exec is set to the needed mask
250  // or using
251  // buffer_load
252  // s_not exec, exec
253  // buffer_load
254  // s_not exec, exec
255  void readWriteTmpVGPR(unsigned Offset, bool IsLoad) {
256  if (SavedExecReg) {
257  // Spill needed lanes
258  TRI.buildVGPRSpillLoadStore(*this, Index, Offset, IsLoad);
259  } else {
260  // Spill active lanes
261  TRI.buildVGPRSpillLoadStore(*this, Index, Offset, IsLoad,
262  /*IsKill*/ false);
263  // Spill inactive lanes
265  TRI.buildVGPRSpillLoadStore(*this, Index, Offset, IsLoad);
267  }
268  }
269 };
270 
271 } // namespace llvm
272 
274  : AMDGPUGenRegisterInfo(AMDGPU::PC_REG, ST.getAMDGPUDwarfFlavour()), ST(ST),
275  SpillSGPRToVGPR(EnableSpillSGPRToVGPR), isWave32(ST.isWave32()) {
276 
277  assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 &&
278  getSubRegIndexLaneMask(AMDGPU::sub31).getAsInteger() == (3ULL << 62) &&
279  (getSubRegIndexLaneMask(AMDGPU::lo16) |
280  getSubRegIndexLaneMask(AMDGPU::hi16)).getAsInteger() ==
281  getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() &&
282  "getNumCoveredRegs() will not work with generated subreg masks!");
283 
284  RegPressureIgnoredUnits.resize(getNumRegUnits());
285  RegPressureIgnoredUnits.set(
287  for (auto Reg : AMDGPU::VGPR_HI16RegClass)
288  RegPressureIgnoredUnits.set(*MCRegUnitIterator(Reg, this));
289 
290  // HACK: Until this is fully tablegen'd.
291  static llvm::once_flag InitializeRegSplitPartsFlag;
292 
293  static auto InitializeRegSplitPartsOnce = [this]() {
294  for (unsigned Idx = 1, E = getNumSubRegIndices() - 1; Idx < E; ++Idx) {
295  unsigned Size = getSubRegIdxSize(Idx);
296  if (Size & 31)
297  continue;
298  std::vector<int16_t> &Vec = RegSplitParts[Size / 32 - 1];
299  unsigned Pos = getSubRegIdxOffset(Idx);
300  if (Pos % Size)
301  continue;
302  Pos /= Size;
303  if (Vec.empty()) {
304  unsigned MaxNumParts = 1024 / Size; // Maximum register is 1024 bits.
305  Vec.resize(MaxNumParts);
306  }
307  Vec[Pos] = Idx;
308  }
309  };
310 
311  static llvm::once_flag InitializeSubRegFromChannelTableFlag;
312 
313  static auto InitializeSubRegFromChannelTableOnce = [this]() {
314  for (auto &Row : SubRegFromChannelTable)
315  Row.fill(AMDGPU::NoSubRegister);
316  for (uint16_t Idx = 1; Idx < getNumSubRegIndices(); ++Idx) {
317  unsigned Width = AMDGPUSubRegIdxRanges[Idx].Size / 32;
318  unsigned Offset = AMDGPUSubRegIdxRanges[Idx].Offset / 32;
321  if (Width == 0)
322  continue;
323  unsigned TableIdx = Width - 1;
324  assert(TableIdx < SubRegFromChannelTable.size());
325  assert(Offset < SubRegFromChannelTable[TableIdx].size());
326  SubRegFromChannelTable[TableIdx][Offset] = Idx;
327  }
328  };
329 
330  llvm::call_once(InitializeRegSplitPartsFlag, InitializeRegSplitPartsOnce);
331  llvm::call_once(InitializeSubRegFromChannelTableFlag,
332  InitializeSubRegFromChannelTableOnce);
333 }
334 
335 void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved,
336  MCRegister Reg) const {
337  MCRegAliasIterator R(Reg, this, true);
338 
339  for (; R.isValid(); ++R)
340  Reserved.set(*R);
341 }
342 
343 // Forced to be here by one .inc
345  const MachineFunction *MF) const {
347  switch (CC) {
348  case CallingConv::C:
349  case CallingConv::Fast:
350  case CallingConv::Cold:
352  return MF->getSubtarget<GCNSubtarget>().hasGFX90AInsts()
353  ? CSR_AMDGPU_HighRegs_With_AGPRs_SaveList
354  : CSR_AMDGPU_HighRegs_SaveList;
355  default: {
356  // Dummy to not crash RegisterClassInfo.
357  static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
358  return &NoCalleeSavedReg;
359  }
360  }
361 }
362 
363 const MCPhysReg *
365  return nullptr;
366 }
367 
369  CallingConv::ID CC) const {
370  switch (CC) {
371  case CallingConv::C:
372  case CallingConv::Fast:
373  case CallingConv::Cold:
375  return MF.getSubtarget<GCNSubtarget>().hasGFX90AInsts()
376  ? CSR_AMDGPU_HighRegs_With_AGPRs_RegMask
377  : CSR_AMDGPU_HighRegs_RegMask;
378  default:
379  return nullptr;
380  }
381 }
382 
384  return CSR_AMDGPU_NoRegs_RegMask;
385 }
386 
388  const SIFrameLowering *TFI =
389  MF.getSubtarget<GCNSubtarget>().getFrameLowering();
390  const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
391  // During ISel lowering we always reserve the stack pointer in entry
392  // functions, but never actually want to reference it when accessing our own
393  // frame. If we need a frame pointer we use it, but otherwise we can just use
394  // an immediate "0" which we represent by returning NoRegister.
395  if (FuncInfo->isEntryFunction()) {
396  return TFI->hasFP(MF) ? FuncInfo->getFrameOffsetReg() : Register();
397  }
398  return TFI->hasFP(MF) ? FuncInfo->getFrameOffsetReg()
399  : FuncInfo->getStackPtrOffsetReg();
400 }
401 
403  // When we need stack realignment, we can't reference off of the
404  // stack pointer, so we reserve a base pointer.
405  const MachineFrameInfo &MFI = MF.getFrameInfo();
406  return MFI.getNumFixedObjects() && shouldRealignStack(MF);
407 }
408 
409 Register SIRegisterInfo::getBaseRegister() const { return AMDGPU::SGPR34; }
410 
412  return CSR_AMDGPU_AllVGPRs_RegMask;
413 }
414 
416  return CSR_AMDGPU_AllAGPRs_RegMask;
417 }
418 
420  return CSR_AMDGPU_AllVectorRegs_RegMask;
421 }
422 
424  return CSR_AMDGPU_AllAllocatableSRegs_RegMask;
425 }
426 
427 unsigned SIRegisterInfo::getSubRegFromChannel(unsigned Channel,
428  unsigned NumRegs) {
429  assert(NumRegs < SubRegFromChannelTableWidthMap.size());
430  unsigned NumRegIndex = SubRegFromChannelTableWidthMap[NumRegs];
431  assert(NumRegIndex && "Not implemented");
432  assert(Channel < SubRegFromChannelTable[NumRegIndex - 1].size());
433  return SubRegFromChannelTable[NumRegIndex - 1][Channel];
434 }
435 
437  const MachineFunction &MF) const {
438  unsigned BaseIdx = alignDown(ST.getMaxNumSGPRs(MF), 4) - 4;
439  MCRegister BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx));
440  return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SGPR_128RegClass);
441 }
442 
444  BitVector Reserved(getNumRegs());
445  Reserved.set(AMDGPU::MODE);
446 
447  // EXEC_LO and EXEC_HI could be allocated and used as regular register, but
448  // this seems likely to result in bugs, so I'm marking them as reserved.
449  reserveRegisterTuples(Reserved, AMDGPU::EXEC);
450  reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);
451 
452  // M0 has to be reserved so that llvm accepts it as a live-in into a block.
453  reserveRegisterTuples(Reserved, AMDGPU::M0);
454 
455  // Reserve src_vccz, src_execz, src_scc.
456  reserveRegisterTuples(Reserved, AMDGPU::SRC_VCCZ);
457  reserveRegisterTuples(Reserved, AMDGPU::SRC_EXECZ);
458  reserveRegisterTuples(Reserved, AMDGPU::SRC_SCC);
459 
460  // Reserve the memory aperture registers.
461  reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_BASE);
462  reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_LIMIT);
463  reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_BASE);
464  reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_LIMIT);
465 
466  // Reserve src_pops_exiting_wave_id - support is not implemented in Codegen.
467  reserveRegisterTuples(Reserved, AMDGPU::SRC_POPS_EXITING_WAVE_ID);
468 
469  // Reserve xnack_mask registers - support is not implemented in Codegen.
470  reserveRegisterTuples(Reserved, AMDGPU::XNACK_MASK);
471 
472  // Reserve lds_direct register - support is not implemented in Codegen.
473  reserveRegisterTuples(Reserved, AMDGPU::LDS_DIRECT);
474 
475  // Reserve Trap Handler registers - support is not implemented in Codegen.
476  reserveRegisterTuples(Reserved, AMDGPU::TBA);
477  reserveRegisterTuples(Reserved, AMDGPU::TMA);
478  reserveRegisterTuples(Reserved, AMDGPU::TTMP0_TTMP1);
479  reserveRegisterTuples(Reserved, AMDGPU::TTMP2_TTMP3);
480  reserveRegisterTuples(Reserved, AMDGPU::TTMP4_TTMP5);
481  reserveRegisterTuples(Reserved, AMDGPU::TTMP6_TTMP7);
482  reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9);
483  reserveRegisterTuples(Reserved, AMDGPU::TTMP10_TTMP11);
484  reserveRegisterTuples(Reserved, AMDGPU::TTMP12_TTMP13);
485  reserveRegisterTuples(Reserved, AMDGPU::TTMP14_TTMP15);
486 
487  // Reserve null register - it shall never be allocated
488  reserveRegisterTuples(Reserved, AMDGPU::SGPR_NULL);
489 
490  // Disallow vcc_hi allocation in wave32. It may be allocated but most likely
491  // will result in bugs.
492  if (isWave32) {
493  Reserved.set(AMDGPU::VCC);
494  Reserved.set(AMDGPU::VCC_HI);
495  }
496 
497  unsigned MaxNumSGPRs = ST.getMaxNumSGPRs(MF);
498  unsigned TotalNumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
499  for (unsigned i = MaxNumSGPRs; i < TotalNumSGPRs; ++i) {
500  unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
501  reserveRegisterTuples(Reserved, Reg);
502  }
503 
504  unsigned MaxNumVGPRs = ST.getMaxNumVGPRs(MF);
505  // TODO: In an entry function without calls and AGPRs used it is possible
506  // to use the whole register budget for VGPRs. Even more it shall
507  // be possible to estimate maximum AGPR/VGPR pressure and split
508  // register file accordingly.
509  if (ST.hasGFX90AInsts())
510  MaxNumVGPRs /= 2;
511  unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs();
512  for (unsigned i = MaxNumVGPRs; i < TotalNumVGPRs; ++i) {
513  unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
514  reserveRegisterTuples(Reserved, Reg);
515  Reg = AMDGPU::AGPR_32RegClass.getRegister(i);
516  reserveRegisterTuples(Reserved, Reg);
517  }
518 
519  for (auto Reg : AMDGPU::SReg_32RegClass) {
520  Reserved.set(getSubReg(Reg, AMDGPU::hi16));
521  Register Low = getSubReg(Reg, AMDGPU::lo16);
522  // This is to prevent BB vcc liveness errors.
523  if (!AMDGPU::SGPR_LO16RegClass.contains(Low))
524  Reserved.set(Low);
525  }
526 
527  for (auto Reg : AMDGPU::AGPR_32RegClass) {
528  Reserved.set(getSubReg(Reg, AMDGPU::hi16));
529  }
530 
531  // Reserve all the rest AGPRs if there are no instructions to use it.
532  if (!ST.hasMAIInsts()) {
533  for (unsigned i = 0; i < MaxNumVGPRs; ++i) {
534  unsigned Reg = AMDGPU::AGPR_32RegClass.getRegister(i);
535  reserveRegisterTuples(Reserved, Reg);
536  }
537  }
538 
540 
541  Register ScratchRSrcReg = MFI->getScratchRSrcReg();
542  if (ScratchRSrcReg != AMDGPU::NoRegister) {
543  // Reserve 4 SGPRs for the scratch buffer resource descriptor in case we need
544  // to spill.
545  // TODO: May need to reserve a VGPR if doing LDS spilling.
546  reserveRegisterTuples(Reserved, ScratchRSrcReg);
547  }
548 
549  // We have to assume the SP is needed in case there are calls in the function,
550  // which is detected after the function is lowered. If we aren't really going
551  // to need SP, don't bother reserving it.
552  MCRegister StackPtrReg = MFI->getStackPtrOffsetReg();
553 
554  if (StackPtrReg) {
555  reserveRegisterTuples(Reserved, StackPtrReg);
556  assert(!isSubRegister(ScratchRSrcReg, StackPtrReg));
557  }
558 
559  MCRegister FrameReg = MFI->getFrameOffsetReg();
560  if (FrameReg) {
561  reserveRegisterTuples(Reserved, FrameReg);
562  assert(!isSubRegister(ScratchRSrcReg, FrameReg));
563  }
564 
565  if (hasBasePointer(MF)) {
566  MCRegister BasePtrReg = getBaseRegister();
567  reserveRegisterTuples(Reserved, BasePtrReg);
568  assert(!isSubRegister(ScratchRSrcReg, BasePtrReg));
569  }
570 
571  for (MCRegister Reg : MFI->WWMReservedRegs) {
572  reserveRegisterTuples(Reserved, Reg);
573  }
574 
575  // FIXME: Stop using reserved registers for this.
576  for (MCPhysReg Reg : MFI->getAGPRSpillVGPRs())
577  reserveRegisterTuples(Reserved, Reg);
578 
579  for (MCPhysReg Reg : MFI->getVGPRSpillAGPRs())
580  reserveRegisterTuples(Reserved, Reg);
581 
582  for (auto SSpill : MFI->getSGPRSpillVGPRs())
583  reserveRegisterTuples(Reserved, SSpill.VGPR);
584 
585  return Reserved;
586 }
587 
590  // On entry, the base address is 0, so it can't possibly need any more
591  // alignment.
592 
593  // FIXME: Should be able to specify the entry frame alignment per calling
594  // convention instead.
595  if (Info->isEntryFunction())
596  return false;
597 
599 }
600 
603  if (Info->isEntryFunction()) {
604  const MachineFrameInfo &MFI = Fn.getFrameInfo();
605  return MFI.hasStackObjects() || MFI.hasCalls();
606  }
607 
608  // May need scavenger for dealing with callee saved registers.
609  return true;
610 }
611 
613  const MachineFunction &MF) const {
614  // Do not use frame virtual registers. They used to be used for SGPRs, but
615  // once we reach PrologEpilogInserter, we can no longer spill SGPRs. If the
616  // scavenger fails, we can increment/decrement the necessary SGPRs to avoid a
617  // spill.
618  return false;
619 }
620 
622  const MachineFunction &MF) const {
623  const MachineFrameInfo &MFI = MF.getFrameInfo();
624  return MFI.hasStackObjects();
625 }
626 
628  const MachineFunction &) const {
629  // There are no special dedicated stack or frame pointers.
630  return true;
631 }
632 
635 
636  int OffIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
637  AMDGPU::OpName::offset);
638  return MI->getOperand(OffIdx).getImm();
639 }
640 
642  int Idx) const {
644  return 0;
645 
646  assert((Idx == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
647  AMDGPU::OpName::vaddr) ||
648  (Idx == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
649  AMDGPU::OpName::saddr))) &&
650  "Should never see frame index on non-address operand");
651 
652  return getScratchInstrOffset(MI);
653 }
654 
657  return false;
658 
659  int64_t FullOffset = Offset + getScratchInstrOffset(MI);
660 
661  if (SIInstrInfo::isMUBUF(*MI))
662  return !SIInstrInfo::isLegalMUBUFImmOffset(FullOffset);
663 
664  const SIInstrInfo *TII = ST.getInstrInfo();
665  return !TII->isLegalFLATOffset(FullOffset, AMDGPUAS::PRIVATE_ADDRESS,
667 }
668 
670  int FrameIdx,
671  int64_t Offset) const {
673  DebugLoc DL; // Defaults to "unknown"
674 
675  if (Ins != MBB->end())
676  DL = Ins->getDebugLoc();
677 
678  MachineFunction *MF = MBB->getParent();
679  const SIInstrInfo *TII = ST.getInstrInfo();
681  unsigned MovOpc = ST.enableFlatScratch() ? AMDGPU::S_MOV_B32
682  : AMDGPU::V_MOV_B32_e32;
683 
685  ST.enableFlatScratch() ? &AMDGPU::SReg_32_XEXEC_HIRegClass
686  : &AMDGPU::VGPR_32RegClass);
687 
688  if (Offset == 0) {
689  BuildMI(*MBB, Ins, DL, TII->get(MovOpc), BaseReg)
690  .addFrameIndex(FrameIdx);
691  return BaseReg;
692  }
693 
694  Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
695 
697  ST.enableFlatScratch() ? &AMDGPU::SReg_32_XM0RegClass
698  : &AMDGPU::VGPR_32RegClass);
699 
700  BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
701  .addImm(Offset);
702  BuildMI(*MBB, Ins, DL, TII->get(MovOpc), FIReg)
703  .addFrameIndex(FrameIdx);
704 
705  if (ST.enableFlatScratch() ) {
706  BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_ADD_U32), BaseReg)
707  .addReg(OffsetReg, RegState::Kill)
708  .addReg(FIReg);
709  return BaseReg;
710  }
711 
712  TII->getAddNoCarry(*MBB, Ins, DL, BaseReg)
713  .addReg(OffsetReg, RegState::Kill)
714  .addReg(FIReg)
715  .addImm(0); // clamp bit
716 
717  return BaseReg;
718 }
719 
721  int64_t Offset) const {
722  const SIInstrInfo *TII = ST.getInstrInfo();
723  bool IsFlat = TII->isFLATScratch(MI);
724 
725 #ifndef NDEBUG
726  // FIXME: Is it possible to be storing a frame index to itself?
727  bool SeenFI = false;
728  for (const MachineOperand &MO: MI.operands()) {
729  if (MO.isFI()) {
730  if (SeenFI)
731  llvm_unreachable("should not see multiple frame indices");
732 
733  SeenFI = true;
734  }
735  }
736 #endif
737 
738  MachineOperand *FIOp =
739  TII->getNamedOperand(MI, IsFlat ? AMDGPU::OpName::saddr
740  : AMDGPU::OpName::vaddr);
741 
742  MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset);
743  int64_t NewOffset = OffsetOp->getImm() + Offset;
744 
745  assert(FIOp && FIOp->isFI() && "frame index must be address operand");
746  assert(TII->isMUBUF(MI) || TII->isFLATScratch(MI));
747 
748  if (IsFlat) {
749  assert(TII->isLegalFLATOffset(NewOffset, AMDGPUAS::PRIVATE_ADDRESS,
751  "offset should be legal");
752  FIOp->ChangeToRegister(BaseReg, false);
753  OffsetOp->setImm(NewOffset);
754  return;
755  }
756 
757 #ifndef NDEBUG
758  MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset);
759  assert(SOffset->isImm() && SOffset->getImm() == 0);
760 #endif
761 
763  "offset should be legal");
764 
765  FIOp->ChangeToRegister(BaseReg, false);
766  OffsetOp->setImm(NewOffset);
767 }
768 
770  Register BaseReg,
771  int64_t Offset) const {
773  return false;
774 
775  int64_t NewOffset = Offset + getScratchInstrOffset(MI);
776 
777  if (SIInstrInfo::isMUBUF(*MI))
778  return SIInstrInfo::isLegalMUBUFImmOffset(NewOffset);
779 
780  const SIInstrInfo *TII = ST.getInstrInfo();
781  return TII->isLegalFLATOffset(NewOffset, AMDGPUAS::PRIVATE_ADDRESS,
783 }
784 
786  const MachineFunction &MF, unsigned Kind) const {
787  // This is inaccurate. It depends on the instruction and address space. The
788  // only place where we should hit this is for dealing with frame indexes /
789  // private accesses, so this is correct in that case.
790  return &AMDGPU::VGPR_32RegClass;
791 }
792 
793 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
794 
795  switch (Op) {
796  case AMDGPU::SI_SPILL_S1024_SAVE:
797  case AMDGPU::SI_SPILL_S1024_RESTORE:
798  case AMDGPU::SI_SPILL_V1024_SAVE:
799  case AMDGPU::SI_SPILL_V1024_RESTORE:
800  case AMDGPU::SI_SPILL_A1024_SAVE:
801  case AMDGPU::SI_SPILL_A1024_RESTORE:
802  return 32;
803  case AMDGPU::SI_SPILL_S512_SAVE:
804  case AMDGPU::SI_SPILL_S512_RESTORE:
805  case AMDGPU::SI_SPILL_V512_SAVE:
806  case AMDGPU::SI_SPILL_V512_RESTORE:
807  case AMDGPU::SI_SPILL_A512_SAVE:
808  case AMDGPU::SI_SPILL_A512_RESTORE:
809  return 16;
810  case AMDGPU::SI_SPILL_S256_SAVE:
811  case AMDGPU::SI_SPILL_S256_RESTORE:
812  case AMDGPU::SI_SPILL_V256_SAVE:
813  case AMDGPU::SI_SPILL_V256_RESTORE:
814  case AMDGPU::SI_SPILL_A256_SAVE:
815  case AMDGPU::SI_SPILL_A256_RESTORE:
816  return 8;
817  case AMDGPU::SI_SPILL_S192_SAVE:
818  case AMDGPU::SI_SPILL_S192_RESTORE:
819  case AMDGPU::SI_SPILL_V192_SAVE:
820  case AMDGPU::SI_SPILL_V192_RESTORE:
821  case AMDGPU::SI_SPILL_A192_SAVE:
822  case AMDGPU::SI_SPILL_A192_RESTORE:
823  return 6;
824  case AMDGPU::SI_SPILL_S160_SAVE:
825  case AMDGPU::SI_SPILL_S160_RESTORE:
826  case AMDGPU::SI_SPILL_V160_SAVE:
827  case AMDGPU::SI_SPILL_V160_RESTORE:
828  case AMDGPU::SI_SPILL_A160_SAVE:
829  case AMDGPU::SI_SPILL_A160_RESTORE:
830  return 5;
831  case AMDGPU::SI_SPILL_S128_SAVE:
832  case AMDGPU::SI_SPILL_S128_RESTORE:
833  case AMDGPU::SI_SPILL_V128_SAVE:
834  case AMDGPU::SI_SPILL_V128_RESTORE:
835  case AMDGPU::SI_SPILL_A128_SAVE:
836  case AMDGPU::SI_SPILL_A128_RESTORE:
837  return 4;
838  case AMDGPU::SI_SPILL_S96_SAVE:
839  case AMDGPU::SI_SPILL_S96_RESTORE:
840  case AMDGPU::SI_SPILL_V96_SAVE:
841  case AMDGPU::SI_SPILL_V96_RESTORE:
842  case AMDGPU::SI_SPILL_A96_SAVE:
843  case AMDGPU::SI_SPILL_A96_RESTORE:
844  return 3;
845  case AMDGPU::SI_SPILL_S64_SAVE:
846  case AMDGPU::SI_SPILL_S64_RESTORE:
847  case AMDGPU::SI_SPILL_V64_SAVE:
848  case AMDGPU::SI_SPILL_V64_RESTORE:
849  case AMDGPU::SI_SPILL_A64_SAVE:
850  case AMDGPU::SI_SPILL_A64_RESTORE:
851  return 2;
852  case AMDGPU::SI_SPILL_S32_SAVE:
853  case AMDGPU::SI_SPILL_S32_RESTORE:
854  case AMDGPU::SI_SPILL_V32_SAVE:
855  case AMDGPU::SI_SPILL_V32_RESTORE:
856  case AMDGPU::SI_SPILL_A32_SAVE:
857  case AMDGPU::SI_SPILL_A32_RESTORE:
858  return 1;
859  default: llvm_unreachable("Invalid spill opcode");
860  }
861 }
862 
863 static int getOffsetMUBUFStore(unsigned Opc) {
864  switch (Opc) {
865  case AMDGPU::BUFFER_STORE_DWORD_OFFEN:
866  return AMDGPU::BUFFER_STORE_DWORD_OFFSET;
867  case AMDGPU::BUFFER_STORE_BYTE_OFFEN:
868  return AMDGPU::BUFFER_STORE_BYTE_OFFSET;
869  case AMDGPU::BUFFER_STORE_SHORT_OFFEN:
870  return AMDGPU::BUFFER_STORE_SHORT_OFFSET;
871  case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN:
872  return AMDGPU::BUFFER_STORE_DWORDX2_OFFSET;
873  case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN:
874  return AMDGPU::BUFFER_STORE_DWORDX4_OFFSET;
875  case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN:
876  return AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET;
877  case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN:
878  return AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET;
879  default:
880  return -1;
881  }
882 }
883 
884 static int getOffsetMUBUFLoad(unsigned Opc) {
885  switch (Opc) {
886  case AMDGPU::BUFFER_LOAD_DWORD_OFFEN:
887  return AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
888  case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN:
889  return AMDGPU::BUFFER_LOAD_UBYTE_OFFSET;
890  case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN:
891  return AMDGPU::BUFFER_LOAD_SBYTE_OFFSET;
892  case AMDGPU::BUFFER_LOAD_USHORT_OFFEN:
893  return AMDGPU::BUFFER_LOAD_USHORT_OFFSET;
894  case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN:
895  return AMDGPU::BUFFER_LOAD_SSHORT_OFFSET;
896  case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN:
897  return AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET;
898  case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN:
899  return AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET;
900  case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN:
901  return AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET;
902  case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN:
903  return AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET;
904  case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN:
905  return AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET;
906  case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN:
907  return AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET;
908  case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN:
909  return AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET;
910  case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN:
911  return AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET;
912  default:
913  return -1;
914  }
915 }
916 
919  int Index,
920  unsigned Lane,
921  unsigned ValueReg,
922  bool IsKill) {
923  MachineBasicBlock *MBB = MI->getParent();
924  MachineFunction *MF = MI->getParent()->getParent();
926  const SIInstrInfo *TII = ST.getInstrInfo();
927 
928  MCPhysReg Reg = MFI->getVGPRToAGPRSpill(Index, Lane);
929 
930  if (Reg == AMDGPU::NoRegister)
931  return MachineInstrBuilder();
932 
933  bool IsStore = MI->mayStore();
935  auto *TRI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
936 
937  unsigned Dst = IsStore ? Reg : ValueReg;
938  unsigned Src = IsStore ? ValueReg : Reg;
939  unsigned Opc = (IsStore ^ TRI->isVGPR(MRI, Reg)) ? AMDGPU::V_ACCVGPR_WRITE_B32_e64
940  : AMDGPU::V_ACCVGPR_READ_B32_e64;
941 
942  auto MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(Opc), Dst)
943  .addReg(Src, getKillRegState(IsKill));
945  return MIB;
946 }
947 
948 // This differs from buildSpillLoadStore by only scavenging a VGPR. It does not
949 // need to handle the case where an SGPR may need to be spilled while spilling.
951  MachineFrameInfo &MFI,
953  int Index,
954  int64_t Offset) {
955  const SIInstrInfo *TII = ST.getInstrInfo();
956  MachineBasicBlock *MBB = MI->getParent();
957  const DebugLoc &DL = MI->getDebugLoc();
958  bool IsStore = MI->mayStore();
959 
960  unsigned Opc = MI->getOpcode();
961  int LoadStoreOp = IsStore ?
963  if (LoadStoreOp == -1)
964  return false;
965 
966  const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata);
967  if (spillVGPRtoAGPR(ST, MI, Index, 0, Reg->getReg(), false).getInstr())
968  return true;
969 
970  MachineInstrBuilder NewMI =
971  BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
972  .add(*Reg)
973  .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc))
974  .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset))
975  .addImm(Offset)
976  .addImm(0) // cpol
977  .addImm(0) // tfe
978  .addImm(0) // swz
979  .cloneMemRefs(*MI);
980 
981  const MachineOperand *VDataIn = TII->getNamedOperand(*MI,
982  AMDGPU::OpName::vdata_in);
983  if (VDataIn)
984  NewMI.add(*VDataIn);
985  return true;
986 }
987 
989  unsigned LoadStoreOp,
990  unsigned EltSize) {
991  bool IsStore = TII->get(LoadStoreOp).mayStore();
992  bool UseST =
993  AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::vaddr) < 0 &&
994  AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::saddr) < 0;
995 
996  switch (EltSize) {
997  case 4:
998  LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
999  : AMDGPU::SCRATCH_LOAD_DWORD_SADDR;
1000  break;
1001  case 8:
1002  LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX2_SADDR
1003  : AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR;
1004  break;
1005  case 12:
1006  LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX3_SADDR
1007  : AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR;
1008  break;
1009  case 16:
1010  LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX4_SADDR
1011  : AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR;
1012  break;
1013  default:
1014  llvm_unreachable("Unexpected spill load/store size!");
1015  }
1016 
1017  if (UseST)
1018  LoadStoreOp = AMDGPU::getFlatScratchInstSTfromSS(LoadStoreOp);
1019 
1020  return LoadStoreOp;
1021 }
1022 
1024  MachineBasicBlock::iterator MI, unsigned LoadStoreOp, int Index,
1025  Register ValueReg, bool IsKill, MCRegister ScratchOffsetReg,
1026  int64_t InstOffset, MachineMemOperand *MMO, RegScavenger *RS,
1027  LivePhysRegs *LiveRegs) const {
1028  assert((!RS || !LiveRegs) && "Only RS or LiveRegs can be set but not both");
1029 
1030  MachineBasicBlock *MBB = MI->getParent();
1031  MachineFunction *MF = MI->getParent()->getParent();
1032  const SIInstrInfo *TII = ST.getInstrInfo();
1033  const MachineFrameInfo &MFI = MF->getFrameInfo();
1034  const SIMachineFunctionInfo *FuncInfo = MF->getInfo<SIMachineFunctionInfo>();
1035 
1036  const MCInstrDesc *Desc = &TII->get(LoadStoreOp);
1037  const DebugLoc &DL = MI->getDebugLoc();
1038  bool IsStore = Desc->mayStore();
1039  bool IsFlat = TII->isFLATScratch(LoadStoreOp);
1040 
1041  bool Scavenged = false;
1042  MCRegister SOffset = ScratchOffsetReg;
1043 
1044  const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg);
1045  // On gfx90a+ AGPR is a regular VGPR acceptable for loads and stores.
1046  const bool IsAGPR = !ST.hasGFX90AInsts() && hasAGPRs(RC);
1047  const unsigned RegWidth = AMDGPU::getRegBitWidth(RC->getID()) / 8;
1048 
1049  // Always use 4 byte operations for AGPRs because we need to scavenge
1050  // a temporary VGPR.
1051  unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u;
1052  unsigned NumSubRegs = RegWidth / EltSize;
1053  unsigned Size = NumSubRegs * EltSize;
1054  unsigned RemSize = RegWidth - Size;
1055  unsigned NumRemSubRegs = RemSize ? 1 : 0;
1056  int64_t Offset = InstOffset + MFI.getObjectOffset(Index);
1057  int64_t MaxOffset = Offset + Size + RemSize - EltSize;
1058  int64_t ScratchOffsetRegDelta = 0;
1059 
1060  if (IsFlat && EltSize > 4) {
1061  LoadStoreOp = getFlatScratchSpillOpcode(TII, LoadStoreOp, EltSize);
1062  Desc = &TII->get(LoadStoreOp);
1063  }
1064 
1065  Align Alignment = MFI.getObjectAlign(Index);
1066  const MachinePointerInfo &BasePtrInfo = MMO->getPointerInfo();
1067 
1068  assert((IsFlat || ((Offset % EltSize) == 0)) &&
1069  "unexpected VGPR spill offset");
1070 
1071  bool IsOffsetLegal =
1072  IsFlat ? TII->isLegalFLATOffset(MaxOffset, AMDGPUAS::PRIVATE_ADDRESS,
1075  if (!IsOffsetLegal || (IsFlat && !SOffset && !ST.hasFlatScratchSTMode())) {
1076  SOffset = MCRegister();
1077 
1078  // We currently only support spilling VGPRs to EltSize boundaries, meaning
1079  // we can simplify the adjustment of Offset here to just scale with
1080  // WavefrontSize.
1081  if (!IsFlat)
1082  Offset *= ST.getWavefrontSize();
1083 
1084  // We don't have access to the register scavenger if this function is called
1085  // during PEI::scavengeFrameVirtualRegs() so use LiveRegs in this case.
1086  if (RS) {
1087  SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0, false);
1088  } else if (LiveRegs) {
1089  for (MCRegister Reg : AMDGPU::SGPR_32RegClass) {
1090  if (LiveRegs->available(MF->getRegInfo(), Reg)) {
1091  SOffset = Reg;
1092  break;
1093  }
1094  }
1095  }
1096 
1097  if (!SOffset) {
1098  // There are no free SGPRs, and since we are in the process of spilling
1099  // VGPRs too. Since we need a VGPR in order to spill SGPRs (this is true
1100  // on SI/CI and on VI it is true until we implement spilling using scalar
1101  // stores), we have no way to free up an SGPR. Our solution here is to
1102  // add the offset directly to the ScratchOffset or StackPtrOffset
1103  // register, and then subtract the offset after the spill to return the
1104  // register to it's original value.
1105  if (!ScratchOffsetReg)
1106  ScratchOffsetReg = FuncInfo->getStackPtrOffsetReg();
1107  SOffset = ScratchOffsetReg;
1108  ScratchOffsetRegDelta = Offset;
1109  } else {
1110  Scavenged = true;
1111  }
1112 
1113  if (!SOffset)
1114  report_fatal_error("could not scavenge SGPR to spill in entry function");
1115 
1116  if (ScratchOffsetReg == AMDGPU::NoRegister) {
1117  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), SOffset)
1118  .addImm(Offset);
1119  } else {
1120  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset)
1121  .addReg(ScratchOffsetReg)
1122  .addImm(Offset);
1123  }
1124 
1125  Offset = 0;
1126  }
1127 
1128  if (IsFlat && SOffset == AMDGPU::NoRegister) {
1129  assert(AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::vaddr) < 0
1130  && "Unexpected vaddr for flat scratch with a FI operand");
1131 
1133  LoadStoreOp = AMDGPU::getFlatScratchInstSTfromSS(LoadStoreOp);
1134  Desc = &TII->get(LoadStoreOp);
1135  }
1136 
1137  Register TmpReg;
1138 
1139  for (unsigned i = 0, e = NumSubRegs + NumRemSubRegs, RegOffset = 0; i != e;
1140  ++i, RegOffset += EltSize) {
1141  if (i == NumSubRegs) {
1142  EltSize = RemSize;
1143  LoadStoreOp = getFlatScratchSpillOpcode(TII, LoadStoreOp, EltSize);
1144  }
1145  Desc = &TII->get(LoadStoreOp);
1146 
1147  unsigned NumRegs = EltSize / 4;
1148  Register SubReg = e == 1
1149  ? ValueReg
1150  : Register(getSubReg(ValueReg,
1151  getSubRegFromChannel(RegOffset / 4, NumRegs)));
1152 
1153  unsigned SOffsetRegState = 0;
1154  unsigned SrcDstRegState = getDefRegState(!IsStore);
1155  if (i + 1 == e) {
1156  SOffsetRegState |= getKillRegState(Scavenged);
1157  // The last implicit use carries the "Kill" flag.
1158  SrcDstRegState |= getKillRegState(IsKill);
1159  }
1160 
1161  // Make sure the whole register is defined if there are undef components by
1162  // adding an implicit def of the super-reg on the first instruction.
1163  bool NeedSuperRegDef = e > 1 && IsStore && i == 0;
1164  bool NeedSuperRegImpOperand = e > 1;
1165 
1166  unsigned Lane = RegOffset / 4;
1167  unsigned LaneE = (RegOffset + EltSize) / 4;
1168  for ( ; Lane != LaneE; ++Lane) {
1169  bool IsSubReg = e > 1 || EltSize > 4;
1170  Register Sub = IsSubReg
1171  ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane)))
1172  : ValueReg;
1173  auto MIB = spillVGPRtoAGPR(ST, MI, Index, Lane, Sub, IsKill);
1174  if (!MIB.getInstr())
1175  break;
1176  if (NeedSuperRegDef || (IsSubReg && IsStore && Lane == 0)) {
1177  MIB.addReg(ValueReg, RegState::ImplicitDefine);
1178  NeedSuperRegDef = false;
1179  }
1180  if (IsSubReg || NeedSuperRegImpOperand) {
1181  NeedSuperRegImpOperand = true;
1182  unsigned State = SrcDstRegState;
1183  if (Lane + 1 != LaneE)
1184  State &= ~RegState::Kill;
1185  MIB.addReg(ValueReg, RegState::Implicit | State);
1186  }
1187  }
1188 
1189  if (Lane == LaneE) // Fully spilled into AGPRs.
1190  continue;
1191 
1192  // Offset in bytes from the beginning of the ValueReg to its portion we
1193  // still need to spill. It may differ from RegOffset if a portion of
1194  // current SubReg has been already spilled into AGPRs by the loop above.
1195  unsigned RemRegOffset = Lane * 4;
1196  unsigned RemEltSize = EltSize - (RemRegOffset - RegOffset);
1197  if (RemEltSize != EltSize) { // Partially spilled to AGPRs
1198  assert(IsFlat && EltSize > 4);
1199 
1200  unsigned NumRegs = RemEltSize / 4;
1201  SubReg = Register(getSubReg(ValueReg,
1202  getSubRegFromChannel(RemRegOffset / 4, NumRegs)));
1203  unsigned Opc = getFlatScratchSpillOpcode(TII, LoadStoreOp, RemEltSize);
1204  Desc = &TII->get(Opc);
1205  }
1206 
1207  unsigned FinalReg = SubReg;
1208 
1209  if (IsAGPR) {
1210  assert(EltSize == 4);
1211 
1212  if (!TmpReg) {
1213  assert(RS && "Needs to have RegScavenger to spill an AGPR!");
1214  // FIXME: change to scavengeRegisterBackwards()
1215  TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
1216  RS->setRegUsed(TmpReg);
1217  }
1218  if (IsStore) {
1219  auto AccRead = BuildMI(*MBB, MI, DL,
1220  TII->get(AMDGPU::V_ACCVGPR_READ_B32_e64), TmpReg)
1221  .addReg(SubReg, getKillRegState(IsKill));
1222  if (NeedSuperRegDef)
1223  AccRead.addReg(ValueReg, RegState::ImplicitDefine);
1225  }
1226  SubReg = TmpReg;
1227  }
1228 
1229  MachinePointerInfo PInfo = BasePtrInfo.getWithOffset(RemRegOffset);
1230  MachineMemOperand *NewMMO =
1231  MF->getMachineMemOperand(PInfo, MMO->getFlags(), RemEltSize,
1232  commonAlignment(Alignment, RemRegOffset));
1233 
1234  auto MIB = BuildMI(*MBB, MI, DL, *Desc)
1235  .addReg(SubReg,
1236  getDefRegState(!IsStore) | getKillRegState(IsKill));
1237  if (!IsFlat)
1238  MIB.addReg(FuncInfo->getScratchRSrcReg());
1239 
1240  if (SOffset == AMDGPU::NoRegister) {
1241  if (!IsFlat)
1242  MIB.addImm(0);
1243  } else {
1244  MIB.addReg(SOffset, SOffsetRegState);
1245  }
1246  MIB.addImm(Offset + RemRegOffset)
1247  .addImm(0); // cpol
1248  if (!IsFlat)
1249  MIB.addImm(0) // tfe
1250  .addImm(0); // swz
1251  MIB.addMemOperand(NewMMO);
1252 
1253  if (!IsAGPR && NeedSuperRegDef)
1254  MIB.addReg(ValueReg, RegState::ImplicitDefine);
1255 
1256  if (!IsStore && TmpReg != AMDGPU::NoRegister) {
1257  MIB = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64),
1258  FinalReg)
1259  .addReg(TmpReg, RegState::Kill);
1261  }
1262 
1263  if (NeedSuperRegImpOperand)
1264  MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState);
1265  }
1266 
1267  if (ScratchOffsetRegDelta != 0) {
1268  // Subtract the offset we added to the ScratchOffset register.
1269  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), SOffset)
1270  .addReg(SOffset)
1271  .addImm(ScratchOffsetRegDelta);
1272  }
1273 }
1274 
1276  int Offset, bool IsLoad,
1277  bool IsKill) const {
1278  // Load/store VGPR
1279  MachineFrameInfo &FrameInfo = SB.MF.getFrameInfo();
1281 
1282  Register FrameReg =
1283  FrameInfo.isFixedObjectIndex(Index) && hasBasePointer(SB.MF)
1284  ? getBaseRegister()
1285  : getFrameRegister(SB.MF);
1286 
1287  Align Alignment = FrameInfo.getObjectAlign(Index);
1291  SB.EltSize, Alignment);
1292 
1293  if (IsLoad) {
1294  unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR
1295  : AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
1296  buildSpillLoadStore(SB.MI, Opc, Index, SB.TmpVGPR, false, FrameReg,
1297  Offset * SB.EltSize, MMO, SB.RS);
1298  } else {
1299  unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
1300  : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
1301  buildSpillLoadStore(SB.MI, Opc, Index, SB.TmpVGPR, IsKill, FrameReg,
1302  Offset * SB.EltSize, MMO, SB.RS);
1303  // This only ever adds one VGPR spill
1304  SB.MFI.addToSpilledVGPRs(1);
1305  }
1306 }
1307 
1309  int Index,
1310  RegScavenger *RS,
1311  bool OnlyToVGPR) const {
1312  SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS);
1313 
1316  bool SpillToVGPR = !VGPRSpills.empty();
1317  if (OnlyToVGPR && !SpillToVGPR)
1318  return false;
1319 
1320  assert(SpillToVGPR || (SB.SuperReg != SB.MFI.getStackPtrOffsetReg() &&
1321  SB.SuperReg != SB.MFI.getFrameOffsetReg()));
1322 
1323  if (SpillToVGPR) {
1324  for (unsigned i = 0, e = SB.NumSubRegs; i < e; ++i) {
1325  Register SubReg =
1326  SB.NumSubRegs == 1
1327  ? SB.SuperReg
1328  : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
1329  SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i];
1330 
1331  bool UseKill = SB.IsKill && i == SB.NumSubRegs - 1;
1332 
1333  // Mark the "old value of vgpr" input undef only if this is the first sgpr
1334  // spill to this specific vgpr in the first basic block.
1335  auto MIB = BuildMI(SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_WRITELANE_B32),
1336  Spill.VGPR)
1337  .addReg(SubReg, getKillRegState(UseKill))
1338  .addImm(Spill.Lane)
1339  .addReg(Spill.VGPR);
1340 
1341  if (i == 0 && SB.NumSubRegs > 1) {
1342  // We may be spilling a super-register which is only partially defined,
1343  // and need to ensure later spills think the value is defined.
1345  }
1346 
1347  if (SB.NumSubRegs > 1)
1348  MIB.addReg(SB.SuperReg, getKillRegState(UseKill) | RegState::Implicit);
1349 
1350  // FIXME: Since this spills to another register instead of an actual
1351  // frame index, we should delete the frame index when all references to
1352  // it are fixed.
1353  }
1354  } else {
1355  SB.prepare();
1356 
1357  // SubReg carries the "Kill" flag when SubReg == SB.SuperReg.
1358  unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill);
1359 
1360  // Per VGPR helper data
1361  auto PVD = SB.getPerVGPRData();
1362 
1363  for (unsigned Offset = 0; Offset < PVD.NumVGPRs; ++Offset) {
1364  unsigned TmpVGPRFlags = RegState::Undef;
1365 
1366  // Write sub registers into the VGPR
1367  for (unsigned i = Offset * PVD.PerVGPR,
1368  e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs);
1369  i < e; ++i) {
1370  Register SubReg =
1371  SB.NumSubRegs == 1
1372  ? SB.SuperReg
1373  : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
1374 
1375  MachineInstrBuilder WriteLane =
1376  BuildMI(SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_WRITELANE_B32),
1377  SB.TmpVGPR)
1378  .addReg(SubReg, SubKillState)
1379  .addImm(i % PVD.PerVGPR)
1380  .addReg(SB.TmpVGPR, TmpVGPRFlags);
1381  TmpVGPRFlags = 0;
1382 
1383  // There could be undef components of a spilled super register.
1384  // TODO: Can we detect this and skip the spill?
1385  if (SB.NumSubRegs > 1) {
1386  // The last implicit use of the SB.SuperReg carries the "Kill" flag.
1387  unsigned SuperKillState = 0;
1388  if (i + 1 == SB.NumSubRegs)
1389  SuperKillState |= getKillRegState(SB.IsKill);
1390  WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState);
1391  }
1392  }
1393 
1394  // Write out VGPR
1395  SB.readWriteTmpVGPR(Offset, /*IsLoad*/ false);
1396  }
1397 
1398  SB.restore();
1399  }
1400 
1401  MI->eraseFromParent();
1403  return true;
1404 }
1405 
1407  int Index,
1408  RegScavenger *RS,
1409  bool OnlyToVGPR) const {
1410  SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS);
1411 
1414  bool SpillToVGPR = !VGPRSpills.empty();
1415  if (OnlyToVGPR && !SpillToVGPR)
1416  return false;
1417 
1418  if (SpillToVGPR) {
1419  for (unsigned i = 0, e = SB.NumSubRegs; i < e; ++i) {
1420  Register SubReg =
1421  SB.NumSubRegs == 1
1422  ? SB.SuperReg
1423  : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
1424 
1425  SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i];
1426  auto MIB =
1427  BuildMI(SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_READLANE_B32), SubReg)
1428  .addReg(Spill.VGPR)
1429  .addImm(Spill.Lane);
1430  if (SB.NumSubRegs > 1 && i == 0)
1432  }
1433  } else {
1434  SB.prepare();
1435 
1436  // Per VGPR helper data
1437  auto PVD = SB.getPerVGPRData();
1438 
1439  for (unsigned Offset = 0; Offset < PVD.NumVGPRs; ++Offset) {
1440  // Load in VGPR data
1441  SB.readWriteTmpVGPR(Offset, /*IsLoad*/ true);
1442 
1443  // Unpack lanes
1444  for (unsigned i = Offset * PVD.PerVGPR,
1445  e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs);
1446  i < e; ++i) {
1447  Register SubReg =
1448  SB.NumSubRegs == 1
1449  ? SB.SuperReg
1450  : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
1451 
1452  bool LastSubReg = (i + 1 == e);
1453  auto MIB = BuildMI(SB.MBB, MI, SB.DL,
1454  SB.TII.get(AMDGPU::V_READLANE_B32), SubReg)
1455  .addReg(SB.TmpVGPR, getKillRegState(LastSubReg))
1456  .addImm(i);
1457  if (SB.NumSubRegs > 1 && i == 0)
1459  }
1460  }
1461 
1462  SB.restore();
1463  }
1464 
1465  MI->eraseFromParent();
1466  return true;
1467 }
1468 
1469 /// Special case of eliminateFrameIndex. Returns true if the SGPR was spilled to
1470 /// a VGPR and the stack slot can be safely eliminated when all other users are
1471 /// handled.
1474  int FI,
1475  RegScavenger *RS) const {
1476  switch (MI->getOpcode()) {
1477  case AMDGPU::SI_SPILL_S1024_SAVE:
1478  case AMDGPU::SI_SPILL_S512_SAVE:
1479  case AMDGPU::SI_SPILL_S256_SAVE:
1480  case AMDGPU::SI_SPILL_S192_SAVE:
1481  case AMDGPU::SI_SPILL_S160_SAVE:
1482  case AMDGPU::SI_SPILL_S128_SAVE:
1483  case AMDGPU::SI_SPILL_S96_SAVE:
1484  case AMDGPU::SI_SPILL_S64_SAVE:
1485  case AMDGPU::SI_SPILL_S32_SAVE:
1486  return spillSGPR(MI, FI, RS, true);
1487  case AMDGPU::SI_SPILL_S1024_RESTORE:
1488  case AMDGPU::SI_SPILL_S512_RESTORE:
1489  case AMDGPU::SI_SPILL_S256_RESTORE:
1490  case AMDGPU::SI_SPILL_S192_RESTORE:
1491  case AMDGPU::SI_SPILL_S160_RESTORE:
1492  case AMDGPU::SI_SPILL_S128_RESTORE:
1493  case AMDGPU::SI_SPILL_S96_RESTORE:
1494  case AMDGPU::SI_SPILL_S64_RESTORE:
1495  case AMDGPU::SI_SPILL_S32_RESTORE:
1496  return restoreSGPR(MI, FI, RS, true);
1497  default:
1498  llvm_unreachable("not an SGPR spill instruction");
1499  }
1500 }
1501 
1503  int SPAdj, unsigned FIOperandNum,
1504  RegScavenger *RS) const {
1505  MachineFunction *MF = MI->getParent()->getParent();
1506  MachineBasicBlock *MBB = MI->getParent();
1508  MachineFrameInfo &FrameInfo = MF->getFrameInfo();
1509  const SIInstrInfo *TII = ST.getInstrInfo();
1510  DebugLoc DL = MI->getDebugLoc();
1511 
1512  assert(SPAdj == 0 && "unhandled SP adjustment in call sequence?");
1513 
1514  MachineOperand &FIOp = MI->getOperand(FIOperandNum);
1515  int Index = MI->getOperand(FIOperandNum).getIndex();
1516 
1517  Register FrameReg = FrameInfo.isFixedObjectIndex(Index) && hasBasePointer(*MF)
1518  ? getBaseRegister()
1519  : getFrameRegister(*MF);
1520 
1521  switch (MI->getOpcode()) {
1522  // SGPR register spill
1523  case AMDGPU::SI_SPILL_S1024_SAVE:
1524  case AMDGPU::SI_SPILL_S512_SAVE:
1525  case AMDGPU::SI_SPILL_S256_SAVE:
1526  case AMDGPU::SI_SPILL_S192_SAVE:
1527  case AMDGPU::SI_SPILL_S160_SAVE:
1528  case AMDGPU::SI_SPILL_S128_SAVE:
1529  case AMDGPU::SI_SPILL_S96_SAVE:
1530  case AMDGPU::SI_SPILL_S64_SAVE:
1531  case AMDGPU::SI_SPILL_S32_SAVE: {
1532  spillSGPR(MI, Index, RS);
1533  break;
1534  }
1535 
1536  // SGPR register restore
1537  case AMDGPU::SI_SPILL_S1024_RESTORE:
1538  case AMDGPU::SI_SPILL_S512_RESTORE:
1539  case AMDGPU::SI_SPILL_S256_RESTORE:
1540  case AMDGPU::SI_SPILL_S192_RESTORE:
1541  case AMDGPU::SI_SPILL_S160_RESTORE:
1542  case AMDGPU::SI_SPILL_S128_RESTORE:
1543  case AMDGPU::SI_SPILL_S96_RESTORE:
1544  case AMDGPU::SI_SPILL_S64_RESTORE:
1545  case AMDGPU::SI_SPILL_S32_RESTORE: {
1546  restoreSGPR(MI, Index, RS);
1547  break;
1548  }
1549 
1550  // VGPR register spill
1551  case AMDGPU::SI_SPILL_V1024_SAVE:
1552  case AMDGPU::SI_SPILL_V512_SAVE:
1553  case AMDGPU::SI_SPILL_V256_SAVE:
1554  case AMDGPU::SI_SPILL_V192_SAVE:
1555  case AMDGPU::SI_SPILL_V160_SAVE:
1556  case AMDGPU::SI_SPILL_V128_SAVE:
1557  case AMDGPU::SI_SPILL_V96_SAVE:
1558  case AMDGPU::SI_SPILL_V64_SAVE:
1559  case AMDGPU::SI_SPILL_V32_SAVE:
1560  case AMDGPU::SI_SPILL_A1024_SAVE:
1561  case AMDGPU::SI_SPILL_A512_SAVE:
1562  case AMDGPU::SI_SPILL_A256_SAVE:
1563  case AMDGPU::SI_SPILL_A192_SAVE:
1564  case AMDGPU::SI_SPILL_A160_SAVE:
1565  case AMDGPU::SI_SPILL_A128_SAVE:
1566  case AMDGPU::SI_SPILL_A96_SAVE:
1567  case AMDGPU::SI_SPILL_A64_SAVE:
1568  case AMDGPU::SI_SPILL_A32_SAVE: {
1569  const MachineOperand *VData = TII->getNamedOperand(*MI,
1570  AMDGPU::OpName::vdata);
1571  assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() ==
1572  MFI->getStackPtrOffsetReg());
1573 
1574  unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
1575  : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
1576  buildSpillLoadStore(MI, Opc,
1577  Index,
1578  VData->getReg(), VData->isKill(),
1579  FrameReg,
1580  TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(),
1581  *MI->memoperands_begin(),
1582  RS);
1583  MFI->addToSpilledVGPRs(getNumSubRegsForSpillOp(MI->getOpcode()));
1584  MI->eraseFromParent();
1585  break;
1586  }
1587  case AMDGPU::SI_SPILL_V32_RESTORE:
1588  case AMDGPU::SI_SPILL_V64_RESTORE:
1589  case AMDGPU::SI_SPILL_V96_RESTORE:
1590  case AMDGPU::SI_SPILL_V128_RESTORE:
1591  case AMDGPU::SI_SPILL_V160_RESTORE:
1592  case AMDGPU::SI_SPILL_V192_RESTORE:
1593  case AMDGPU::SI_SPILL_V256_RESTORE:
1594  case AMDGPU::SI_SPILL_V512_RESTORE:
1595  case AMDGPU::SI_SPILL_V1024_RESTORE:
1596  case AMDGPU::SI_SPILL_A32_RESTORE:
1597  case AMDGPU::SI_SPILL_A64_RESTORE:
1598  case AMDGPU::SI_SPILL_A96_RESTORE:
1599  case AMDGPU::SI_SPILL_A128_RESTORE:
1600  case AMDGPU::SI_SPILL_A160_RESTORE:
1601  case AMDGPU::SI_SPILL_A192_RESTORE:
1602  case AMDGPU::SI_SPILL_A256_RESTORE:
1603  case AMDGPU::SI_SPILL_A512_RESTORE:
1604  case AMDGPU::SI_SPILL_A1024_RESTORE: {
1605  const MachineOperand *VData = TII->getNamedOperand(*MI,
1606  AMDGPU::OpName::vdata);
1607  assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() ==
1608  MFI->getStackPtrOffsetReg());
1609 
1610  unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR
1611  : AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
1612  buildSpillLoadStore(MI, Opc,
1613  Index,
1614  VData->getReg(), VData->isKill(),
1615  FrameReg,
1616  TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(),
1617  *MI->memoperands_begin(),
1618  RS);
1619  MI->eraseFromParent();
1620  break;
1621  }
1622 
1623  default: {
1624  // Other access to frame index
1625  const DebugLoc &DL = MI->getDebugLoc();
1626 
1627  int64_t Offset = FrameInfo.getObjectOffset(Index);
1628  if (ST.enableFlatScratch()) {
1629  if (TII->isFLATScratch(*MI)) {
1630  assert((int16_t)FIOperandNum ==
1631  AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1632  AMDGPU::OpName::saddr));
1633 
1634  // The offset is always swizzled, just replace it
1635  if (FrameReg)
1636  FIOp.ChangeToRegister(FrameReg, false);
1637 
1638  if (!Offset)
1639  return;
1640 
1641  MachineOperand *OffsetOp =
1642  TII->getNamedOperand(*MI, AMDGPU::OpName::offset);
1643  int64_t NewOffset = Offset + OffsetOp->getImm();
1644  if (TII->isLegalFLATOffset(NewOffset, AMDGPUAS::PRIVATE_ADDRESS,
1646  OffsetOp->setImm(NewOffset);
1647  if (FrameReg)
1648  return;
1649  Offset = 0;
1650  }
1651 
1652  assert(!TII->getNamedOperand(*MI, AMDGPU::OpName::vaddr) &&
1653  "Unexpected vaddr for flat scratch with a FI operand");
1654 
1655  // On GFX10 we have ST mode to use no registers for an address.
1656  // Otherwise we need to materialize 0 into an SGPR.
1657  if (!Offset && ST.hasFlatScratchSTMode()) {
1658  unsigned Opc = MI->getOpcode();
1659  unsigned NewOpc = AMDGPU::getFlatScratchInstSTfromSS(Opc);
1660  MI->RemoveOperand(
1661  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr));
1662  MI->setDesc(TII->get(NewOpc));
1663  return;
1664  }
1665  }
1666 
1667  if (!FrameReg) {
1668  FIOp.ChangeToImmediate(Offset);
1669  if (TII->isImmOperandLegal(*MI, FIOperandNum, FIOp))
1670  return;
1671  }
1672 
1673  // We need to use register here. Check if we can use an SGPR or need
1674  // a VGPR.
1675  FIOp.ChangeToRegister(AMDGPU::M0, false);
1676  bool UseSGPR = TII->isOperandLegal(*MI, FIOperandNum, &FIOp);
1677 
1678  if (!Offset && FrameReg && UseSGPR) {
1679  FIOp.setReg(FrameReg);
1680  return;
1681  }
1682 
1683  const TargetRegisterClass *RC = UseSGPR ? &AMDGPU::SReg_32_XM0RegClass
1684  : &AMDGPU::VGPR_32RegClass;
1685 
1686  Register TmpReg = RS->scavengeRegister(RC, MI, 0, !UseSGPR);
1687  FIOp.setReg(TmpReg);
1688  FIOp.setIsKill(true);
1689 
1690  if ((!FrameReg || !Offset) && TmpReg) {
1691  unsigned Opc = UseSGPR ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
1692  auto MIB = BuildMI(*MBB, MI, DL, TII->get(Opc), TmpReg);
1693  if (FrameReg)
1694  MIB.addReg(FrameReg);
1695  else
1696  MIB.addImm(Offset);
1697 
1698  return;
1699  }
1700 
1701  Register TmpSReg =
1702  UseSGPR ? TmpReg
1703  : RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0,
1704  !UseSGPR);
1705 
1706  // TODO: for flat scratch another attempt can be made with a VGPR index
1707  // if no SGPRs can be scavenged.
1708  if ((!TmpSReg && !FrameReg) || (!TmpReg && !UseSGPR))
1709  report_fatal_error("Cannot scavenge register in FI elimination!");
1710 
1711  if (!TmpSReg) {
1712  // Use frame register and restore it after.
1713  TmpSReg = FrameReg;
1714  FIOp.setReg(FrameReg);
1715  FIOp.setIsKill(false);
1716  }
1717 
1718  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), TmpSReg)
1719  .addReg(FrameReg)
1720  .addImm(Offset);
1721 
1722  if (!UseSGPR)
1723  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
1724  .addReg(TmpSReg, RegState::Kill);
1725 
1726  if (TmpSReg == FrameReg) {
1727  // Undo frame register modification.
1728  BuildMI(*MBB, std::next(MI), DL, TII->get(AMDGPU::S_SUB_U32),
1729  FrameReg)
1730  .addReg(FrameReg)
1731  .addImm(Offset);
1732  }
1733 
1734  return;
1735  }
1736 
1737  bool IsMUBUF = TII->isMUBUF(*MI);
1738 
1739  if (!IsMUBUF && !MFI->isEntryFunction()) {
1740  // Convert to a swizzled stack address by scaling by the wave size.
1741  //
1742  // In an entry function/kernel the offset is already swizzled.
1743 
1744  bool IsCopy = MI->getOpcode() == AMDGPU::V_MOV_B32_e32;
1745  Register ResultReg =
1746  IsCopy ? MI->getOperand(0).getReg()
1747  : RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
1748 
1749  int64_t Offset = FrameInfo.getObjectOffset(Index);
1750  if (Offset == 0) {
1751  // XXX - This never happens because of emergency scavenging slot at 0?
1752  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64), ResultReg)
1754  .addReg(FrameReg);
1755  } else {
1756  if (auto MIB = TII->getAddNoCarry(*MBB, MI, DL, ResultReg, *RS)) {
1757  // Reuse ResultReg in intermediate step.
1758  Register ScaledReg = ResultReg;
1759 
1760  BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64),
1761  ScaledReg)
1763  .addReg(FrameReg);
1764 
1765  const bool IsVOP2 = MIB->getOpcode() == AMDGPU::V_ADD_U32_e32;
1766 
1767  // TODO: Fold if use instruction is another add of a constant.
1769  // FIXME: This can fail
1770  MIB.addImm(Offset);
1771  MIB.addReg(ScaledReg, RegState::Kill);
1772  if (!IsVOP2)
1773  MIB.addImm(0); // clamp bit
1774  } else {
1775  assert(MIB->getOpcode() == AMDGPU::V_ADD_CO_U32_e64 &&
1776  "Need to reuse carry out register");
1777 
1778  // Use scavenged unused carry out as offset register.
1779  Register ConstOffsetReg;
1780  if (!isWave32)
1781  ConstOffsetReg = getSubReg(MIB.getReg(1), AMDGPU::sub0);
1782  else
1783  ConstOffsetReg = MIB.getReg(1);
1784 
1785  BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::S_MOV_B32), ConstOffsetReg)
1786  .addImm(Offset);
1787  MIB.addReg(ConstOffsetReg, RegState::Kill);
1788  MIB.addReg(ScaledReg, RegState::Kill);
1789  MIB.addImm(0); // clamp bit
1790  }
1791  } else {
1792  // We have to produce a carry out, and there isn't a free SGPR pair
1793  // for it. We can keep the whole computation on the SALU to avoid
1794  // clobbering an additional register at the cost of an extra mov.
1795 
1796  // We may have 1 free scratch SGPR even though a carry out is
1797  // unavailable. Only one additional mov is needed.
1798  Register TmpScaledReg =
1799  RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, false);
1800  Register ScaledReg = TmpScaledReg.isValid() ? TmpScaledReg : FrameReg;
1801 
1802  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHR_B32), ScaledReg)
1803  .addReg(FrameReg)
1805  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), ScaledReg)
1806  .addReg(ScaledReg, RegState::Kill)
1807  .addImm(Offset);
1808  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), ResultReg)
1809  .addReg(ScaledReg, RegState::Kill);
1810 
1811  // If there were truly no free SGPRs, we need to undo everything.
1812  if (!TmpScaledReg.isValid()) {
1813  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), ScaledReg)
1814  .addReg(ScaledReg, RegState::Kill)
1815  .addImm(Offset);
1816  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHL_B32), ScaledReg)
1817  .addReg(FrameReg)
1819  }
1820  }
1821  }
1822 
1823  // Don't introduce an extra copy if we're just materializing in a mov.
1824  if (IsCopy)
1825  MI->eraseFromParent();
1826  else
1827  FIOp.ChangeToRegister(ResultReg, false, false, true);
1828  return;
1829  }
1830 
1831  if (IsMUBUF) {
1832  // Disable offen so we don't need a 0 vgpr base.
1833  assert(static_cast<int>(FIOperandNum) ==
1834  AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1835  AMDGPU::OpName::vaddr));
1836 
1837  auto &SOffset = *TII->getNamedOperand(*MI, AMDGPU::OpName::soffset);
1838  assert((SOffset.isImm() && SOffset.getImm() == 0));
1839 
1840  if (FrameReg != AMDGPU::NoRegister)
1841  SOffset.ChangeToRegister(FrameReg, false);
1842 
1843  int64_t Offset = FrameInfo.getObjectOffset(Index);
1844  int64_t OldImm
1845  = TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm();
1846  int64_t NewOffset = OldImm + Offset;
1847 
1848  if (SIInstrInfo::isLegalMUBUFImmOffset(NewOffset) &&
1849  buildMUBUFOffsetLoadStore(ST, FrameInfo, MI, Index, NewOffset)) {
1850  MI->eraseFromParent();
1851  return;
1852  }
1853  }
1854 
1855  // If the offset is simply too big, don't convert to a scratch wave offset
1856  // relative index.
1857 
1858  FIOp.ChangeToImmediate(Offset);
1859  if (!TII->isImmOperandLegal(*MI, FIOperandNum, FIOp)) {
1860  Register TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
1861  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
1862  .addImm(Offset);
1863  FIOp.ChangeToRegister(TmpReg, false, false, true);
1864  }
1865  }
1866  }
1867 }
1868 
1871 }
1872 
1873 static const TargetRegisterClass *
1875  if (BitWidth <= 64)
1876  return &AMDGPU::VReg_64RegClass;
1877  if (BitWidth <= 96)
1878  return &AMDGPU::VReg_96RegClass;
1879  if (BitWidth <= 128)
1880  return &AMDGPU::VReg_128RegClass;
1881  if (BitWidth <= 160)
1882  return &AMDGPU::VReg_160RegClass;
1883  if (BitWidth <= 192)
1884  return &AMDGPU::VReg_192RegClass;
1885  if (BitWidth <= 256)
1886  return &AMDGPU::VReg_256RegClass;
1887  if (BitWidth <= 512)
1888  return &AMDGPU::VReg_512RegClass;
1889  if (BitWidth <= 1024)
1890  return &AMDGPU::VReg_1024RegClass;
1891 
1892  return nullptr;
1893 }
1894 
1895 static const TargetRegisterClass *
1897  if (BitWidth <= 64)
1898  return &AMDGPU::VReg_64_Align2RegClass;
1899  if (BitWidth <= 96)
1900  return &AMDGPU::VReg_96_Align2RegClass;
1901  if (BitWidth <= 128)
1902  return &AMDGPU::VReg_128_Align2RegClass;
1903  if (BitWidth <= 160)
1904  return &AMDGPU::VReg_160_Align2RegClass;
1905  if (BitWidth <= 192)
1906  return &AMDGPU::VReg_192_Align2RegClass;
1907  if (BitWidth <= 256)
1908  return &AMDGPU::VReg_256_Align2RegClass;
1909  if (BitWidth <= 512)
1910  return &AMDGPU::VReg_512_Align2RegClass;
1911  if (BitWidth <= 1024)
1912  return &AMDGPU::VReg_1024_Align2RegClass;
1913 
1914  return nullptr;
1915 }
1916 
1917 const TargetRegisterClass *
1919  if (BitWidth == 1)
1920  return &AMDGPU::VReg_1RegClass;
1921  if (BitWidth <= 16)
1922  return &AMDGPU::VGPR_LO16RegClass;
1923  if (BitWidth <= 32)
1924  return &AMDGPU::VGPR_32RegClass;
1927 }
1928 
1929 static const TargetRegisterClass *
1931  if (BitWidth <= 64)
1932  return &AMDGPU::AReg_64RegClass;
1933  if (BitWidth <= 96)
1934  return &AMDGPU::AReg_96RegClass;
1935  if (BitWidth <= 128)
1936  return &AMDGPU::AReg_128RegClass;
1937  if (BitWidth <= 160)
1938  return &AMDGPU::AReg_160RegClass;
1939  if (BitWidth <= 192)
1940  return &AMDGPU::AReg_192RegClass;
1941  if (BitWidth <= 256)
1942  return &AMDGPU::AReg_256RegClass;
1943  if (BitWidth <= 512)
1944  return &AMDGPU::AReg_512RegClass;
1945  if (BitWidth <= 1024)
1946  return &AMDGPU::AReg_1024RegClass;
1947 
1948  return nullptr;
1949 }
1950 
1951 static const TargetRegisterClass *
1953  if (BitWidth <= 64)
1954  return &AMDGPU::AReg_64_Align2RegClass;
1955  if (BitWidth <= 96)
1956  return &AMDGPU::AReg_96_Align2RegClass;
1957  if (BitWidth <= 128)
1958  return &AMDGPU::AReg_128_Align2RegClass;
1959  if (BitWidth <= 160)
1960  return &AMDGPU::AReg_160_Align2RegClass;
1961  if (BitWidth <= 192)
1962  return &AMDGPU::AReg_192_Align2RegClass;
1963  if (BitWidth <= 256)
1964  return &AMDGPU::AReg_256_Align2RegClass;
1965  if (BitWidth <= 512)
1966  return &AMDGPU::AReg_512_Align2RegClass;
1967  if (BitWidth <= 1024)
1968  return &AMDGPU::AReg_1024_Align2RegClass;
1969 
1970  return nullptr;
1971 }
1972 
1973 const TargetRegisterClass *
1975  if (BitWidth <= 16)
1976  return &AMDGPU::AGPR_LO16RegClass;
1977  if (BitWidth <= 32)
1978  return &AMDGPU::AGPR_32RegClass;
1981 }
1982 
1983 const TargetRegisterClass *
1985  if (BitWidth <= 16)
1986  return &AMDGPU::SGPR_LO16RegClass;
1987  if (BitWidth <= 32)
1988  return &AMDGPU::SReg_32RegClass;
1989  if (BitWidth <= 64)
1990  return &AMDGPU::SReg_64RegClass;
1991  if (BitWidth <= 96)
1992  return &AMDGPU::SGPR_96RegClass;
1993  if (BitWidth <= 128)
1994  return &AMDGPU::SGPR_128RegClass;
1995  if (BitWidth <= 160)
1996  return &AMDGPU::SGPR_160RegClass;
1997  if (BitWidth <= 192)
1998  return &AMDGPU::SGPR_192RegClass;
1999  if (BitWidth <= 256)
2000  return &AMDGPU::SGPR_256RegClass;
2001  if (BitWidth <= 512)
2002  return &AMDGPU::SGPR_512RegClass;
2003  if (BitWidth <= 1024)
2004  return &AMDGPU::SGPR_1024RegClass;
2005 
2006  return nullptr;
2007 }
2008 
2009 // FIXME: This is very slow. It might be worth creating a map from physreg to
2010 // register class.
2011 const TargetRegisterClass *
2013  static const TargetRegisterClass *const BaseClasses[] = {
2014  &AMDGPU::VGPR_LO16RegClass,
2015  &AMDGPU::VGPR_HI16RegClass,
2016  &AMDGPU::SReg_LO16RegClass,
2017  &AMDGPU::AGPR_LO16RegClass,
2018  &AMDGPU::VGPR_32RegClass,
2019  &AMDGPU::SReg_32RegClass,
2020  &AMDGPU::AGPR_32RegClass,
2021  &AMDGPU::AGPR_32RegClass,
2022  &AMDGPU::VReg_64_Align2RegClass,
2023  &AMDGPU::VReg_64RegClass,
2024  &AMDGPU::SReg_64RegClass,
2025  &AMDGPU::AReg_64_Align2RegClass,
2026  &AMDGPU::AReg_64RegClass,
2027  &AMDGPU::VReg_96_Align2RegClass,
2028  &AMDGPU::VReg_96RegClass,
2029  &AMDGPU::SReg_96RegClass,
2030  &AMDGPU::AReg_96_Align2RegClass,
2031  &AMDGPU::AReg_96RegClass,
2032  &AMDGPU::VReg_128_Align2RegClass,
2033  &AMDGPU::VReg_128RegClass,
2034  &AMDGPU::SReg_128RegClass,
2035  &AMDGPU::AReg_128_Align2RegClass,
2036  &AMDGPU::AReg_128RegClass,
2037  &AMDGPU::VReg_160_Align2RegClass,
2038  &AMDGPU::VReg_160RegClass,
2039  &AMDGPU::SReg_160RegClass,
2040  &AMDGPU::AReg_160_Align2RegClass,
2041  &AMDGPU::AReg_160RegClass,
2042  &AMDGPU::VReg_192_Align2RegClass,
2043  &AMDGPU::VReg_192RegClass,
2044  &AMDGPU::SReg_192RegClass,
2045  &AMDGPU::AReg_192_Align2RegClass,
2046  &AMDGPU::AReg_192RegClass,
2047  &AMDGPU::VReg_256_Align2RegClass,
2048  &AMDGPU::VReg_256RegClass,
2049  &AMDGPU::SReg_256RegClass,
2050  &AMDGPU::AReg_256_Align2RegClass,
2051  &AMDGPU::AReg_256RegClass,
2052  &AMDGPU::VReg_512_Align2RegClass,
2053  &AMDGPU::VReg_512RegClass,
2054  &AMDGPU::SReg_512RegClass,
2055  &AMDGPU::AReg_512_Align2RegClass,
2056  &AMDGPU::AReg_512RegClass,
2057  &AMDGPU::SReg_1024RegClass,
2058  &AMDGPU::VReg_1024_Align2RegClass,
2059  &AMDGPU::VReg_1024RegClass,
2060  &AMDGPU::AReg_1024_Align2RegClass,
2061  &AMDGPU::AReg_1024RegClass,
2062  &AMDGPU::SCC_CLASSRegClass,
2063  &AMDGPU::Pseudo_SReg_32RegClass,
2064  &AMDGPU::Pseudo_SReg_128RegClass,
2065  };
2066 
2067  for (const TargetRegisterClass *BaseClass : BaseClasses) {
2068  if (BaseClass->contains(Reg)) {
2069  return BaseClass;
2070  }
2071  }
2072  return nullptr;
2073 }
2074 
2076  Register Reg) const {
2077  const TargetRegisterClass *RC;
2078  if (Reg.isVirtual())
2079  RC = MRI.getRegClass(Reg);
2080  else
2081  RC = getPhysRegClass(Reg);
2082  return isSGPRClass(RC);
2083 }
2084 
2085 // TODO: It might be helpful to have some target specific flags in
2086 // TargetRegisterClass to mark which classes are VGPRs to make this trivial.
2088  unsigned Size = getRegSizeInBits(*RC);
2089  if (Size == 16) {
2090  return getCommonSubClass(&AMDGPU::VGPR_LO16RegClass, RC) != nullptr ||
2091  getCommonSubClass(&AMDGPU::VGPR_HI16RegClass, RC) != nullptr;
2092  }
2094  if (!VRC) {
2095  assert(Size < 32 && "Invalid register class size");
2096  return false;
2097  }
2098  return getCommonSubClass(VRC, RC) != nullptr;
2099 }
2100 
2102  unsigned Size = getRegSizeInBits(*RC);
2103  if (Size < 16)
2104  return false;
2106  if (!ARC) {
2107  assert(getVGPRClassForBitWidth(Size) && "Invalid register class size");
2108  return false;
2109  }
2110  return getCommonSubClass(ARC, RC) != nullptr;
2111 }
2112 
2113 const TargetRegisterClass *
2115  unsigned Size = getRegSizeInBits(*SRC);
2117  assert(VRC && "Invalid register class size");
2118  return VRC;
2119 }
2120 
2121 const TargetRegisterClass *
2123  unsigned Size = getRegSizeInBits(*SRC);
2125  assert(ARC && "Invalid register class size");
2126  return ARC;
2127 }
2128 
2129 const TargetRegisterClass *
2131  unsigned Size = getRegSizeInBits(*VRC);
2132  if (Size == 32)
2133  return &AMDGPU::SGPR_32RegClass;
2135  assert(SRC && "Invalid register class size");
2136  return SRC;
2137 }
2138 
2140  const TargetRegisterClass *RC, unsigned SubIdx) const {
2141  if (SubIdx == AMDGPU::NoSubRegister)
2142  return RC;
2143 
2144  // We can assume that each lane corresponds to one 32-bit register.
2145  unsigned Size = getNumChannelsFromSubReg(SubIdx) * 32;
2146  if (isSGPRClass(RC)) {
2147  if (Size == 32)
2148  RC = &AMDGPU::SGPR_32RegClass;
2149  else
2151  } else if (hasAGPRs(RC)) {
2153  } else {
2155  }
2156  assert(RC && "Invalid sub-register class size");
2157  return RC;
2158 }
2159 
2160 const TargetRegisterClass *
2162  const TargetRegisterClass *SubRC,
2163  unsigned SubIdx) const {
2164  // Ensure this subregister index is aligned in the super register.
2165  const TargetRegisterClass *MatchRC =
2166  getMatchingSuperRegClass(SuperRC, SubRC, SubIdx);
2167  return MatchRC && MatchRC->hasSubClassEq(SuperRC) ? MatchRC : nullptr;
2168 }
2169 
2170 bool SIRegisterInfo::opCanUseInlineConstant(unsigned OpType) const {
2171  if (OpType >= AMDGPU::OPERAND_REG_INLINE_AC_FIRST &&
2173  return !ST.hasMFMAInlineLiteralBug();
2174 
2175  return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
2176  OpType <= AMDGPU::OPERAND_SRC_LAST;
2177 }
2178 
2180  const TargetRegisterClass *DefRC,
2181  unsigned DefSubReg,
2182  const TargetRegisterClass *SrcRC,
2183  unsigned SrcSubReg) const {
2184  // We want to prefer the smallest register class possible, so we don't want to
2185  // stop and rewrite on anything that looks like a subregister
2186  // extract. Operations mostly don't care about the super register class, so we
2187  // only want to stop on the most basic of copies between the same register
2188  // class.
2189  //
2190  // e.g. if we have something like
2191  // %0 = ...
2192  // %1 = ...
2193  // %2 = REG_SEQUENCE %0, sub0, %1, sub1, %2, sub2
2194  // %3 = COPY %2, sub0
2195  //
2196  // We want to look through the COPY to find:
2197  // => %3 = COPY %0
2198 
2199  // Plain copy.
2200  return getCommonSubClass(DefRC, SrcRC) != nullptr;
2201 }
2202 
2203 bool SIRegisterInfo::opCanUseLiteralConstant(unsigned OpType) const {
2204  // TODO: 64-bit operands have extending behavior from 32-bit literal.
2205  return OpType >= AMDGPU::OPERAND_REG_IMM_FIRST &&
2206  OpType <= AMDGPU::OPERAND_REG_IMM_LAST;
2207 }
2208 
2209 /// Returns a lowest register that is not used at any point in the function.
2210 /// If all registers are used, then this function will return
2211 /// AMDGPU::NoRegister. If \p ReserveHighestVGPR = true, then return
2212 /// highest unused register.
2214  const TargetRegisterClass *RC,
2215  const MachineFunction &MF,
2216  bool ReserveHighestVGPR) const {
2217  if (ReserveHighestVGPR) {
2218  for (MCRegister Reg : reverse(*RC))
2220  return Reg;
2221  } else {
2222  for (MCRegister Reg : *RC)
2224  return Reg;
2225  }
2226  return MCRegister();
2227 }
2228 
2230  unsigned EltSize) const {
2231  const unsigned RegBitWidth = AMDGPU::getRegBitWidth(*RC->MC);
2232  assert(RegBitWidth >= 32 && RegBitWidth <= 1024);
2233 
2234  const unsigned RegDWORDs = RegBitWidth / 32;
2235  const unsigned EltDWORDs = EltSize / 4;
2236  assert(RegSplitParts.size() + 1 >= EltDWORDs);
2237 
2238  const std::vector<int16_t> &Parts = RegSplitParts[EltDWORDs - 1];
2239  const unsigned NumParts = RegDWORDs / EltDWORDs;
2240 
2241  return makeArrayRef(Parts.data(), NumParts);
2242 }
2243 
2244 const TargetRegisterClass*
2246  Register Reg) const {
2247  return Reg.isVirtual() ? MRI.getRegClass(Reg) : getPhysRegClass(Reg);
2248 }
2249 
2251  Register Reg) const {
2253  // Registers without classes are unaddressable, SGPR-like registers.
2254  return RC && hasVGPRs(RC);
2255 }
2256 
2258  Register Reg) const {
2260 
2261  // Registers without classes are unaddressable, SGPR-like registers.
2262  return RC && hasAGPRs(RC);
2263 }
2264 
2266  const TargetRegisterClass *SrcRC,
2267  unsigned SubReg,
2268  const TargetRegisterClass *DstRC,
2269  unsigned DstSubReg,
2270  const TargetRegisterClass *NewRC,
2271  LiveIntervals &LIS) const {
2272  unsigned SrcSize = getRegSizeInBits(*SrcRC);
2273  unsigned DstSize = getRegSizeInBits(*DstRC);
2274  unsigned NewSize = getRegSizeInBits(*NewRC);
2275 
2276  // Do not increase size of registers beyond dword, we would need to allocate
2277  // adjacent registers and constraint regalloc more than needed.
2278 
2279  // Always allow dword coalescing.
2280  if (SrcSize <= 32 || DstSize <= 32)
2281  return true;
2282 
2283  return NewSize <= DstSize || NewSize <= SrcSize;
2284 }
2285 
2287  MachineFunction &MF) const {
2289 
2290  unsigned Occupancy = ST.getOccupancyWithLocalMemSize(MFI->getLDSSize(),
2291  MF.getFunction());
2292  switch (RC->getID()) {
2293  default:
2294  return AMDGPUGenRegisterInfo::getRegPressureLimit(RC, MF);
2295  case AMDGPU::VGPR_32RegClassID:
2296  case AMDGPU::VGPR_LO16RegClassID:
2297  case AMDGPU::VGPR_HI16RegClassID:
2298  return std::min(ST.getMaxNumVGPRs(Occupancy), ST.getMaxNumVGPRs(MF));
2299  case AMDGPU::SGPR_32RegClassID:
2300  case AMDGPU::SGPR_LO16RegClassID:
2301  return std::min(ST.getMaxNumSGPRs(Occupancy, true), ST.getMaxNumSGPRs(MF));
2302  }
2303 }
2304 
2306  unsigned Idx) const {
2307  if (Idx == AMDGPU::RegisterPressureSets::VGPR_32 ||
2308  Idx == AMDGPU::RegisterPressureSets::AGPR_32)
2309  return getRegPressureLimit(&AMDGPU::VGPR_32RegClass,
2310  const_cast<MachineFunction &>(MF));
2311 
2312  if (Idx == AMDGPU::RegisterPressureSets::SReg_32)
2313  return getRegPressureLimit(&AMDGPU::SGPR_32RegClass,
2314  const_cast<MachineFunction &>(MF));
2315 
2316  llvm_unreachable("Unexpected register pressure set!");
2317 }
2318 
2319 const int *SIRegisterInfo::getRegUnitPressureSets(unsigned RegUnit) const {
2320  static const int Empty[] = { -1 };
2321 
2322  if (RegPressureIgnoredUnits[RegUnit])
2323  return Empty;
2324 
2325  return AMDGPUGenRegisterInfo::getRegUnitPressureSets(RegUnit);
2326 }
2327 
2329  // Not a callee saved register.
2330  return AMDGPU::SGPR30_SGPR31;
2331 }
2332 
2333 const TargetRegisterClass *
2335  const RegisterBank &RB,
2336  const MachineRegisterInfo &MRI) const {
2337  switch (RB.getID()) {
2338  case AMDGPU::VGPRRegBankID:
2339  return getVGPRClassForBitWidth(std::max(32u, Size));
2340  case AMDGPU::VCCRegBankID:
2341  assert(Size == 1);
2342  return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
2343  : &AMDGPU::SReg_64_XEXECRegClass;
2344  case AMDGPU::SGPRRegBankID:
2345  return getSGPRClassForBitWidth(std::max(32u, Size));
2346  case AMDGPU::AGPRRegBankID:
2347  return getAGPRClassForBitWidth(std::max(32u, Size));
2348  default:
2349  llvm_unreachable("unknown register bank");
2350  }
2351 }
2352 
2353 const TargetRegisterClass *
2355  const MachineRegisterInfo &MRI) const {
2356  const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg());
2357  if (const RegisterBank *RB = RCOrRB.dyn_cast<const RegisterBank*>())
2358  return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB, MRI);
2359 
2360  const TargetRegisterClass *RC = RCOrRB.get<const TargetRegisterClass*>();
2361  return getAllocatableClass(RC);
2362 }
2363 
2365  return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC;
2366 }
2367 
2369  // VGPR tuples have an alignment requirement on gfx90a variants.
2370  return ST.needsAlignedVGPRs() ? &AMDGPU::VReg_64_Align2RegClass
2371  : &AMDGPU::VReg_64RegClass;
2372 }
2373 
2374 const TargetRegisterClass *
2375 SIRegisterInfo::getRegClass(unsigned RCID) const {
2376  switch ((int)RCID) {
2377  case AMDGPU::SReg_1RegClassID:
2378  return getBoolRC();
2379  case AMDGPU::SReg_1_XEXECRegClassID:
2380  return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
2381  : &AMDGPU::SReg_64_XEXECRegClass;
2382  case -1:
2383  return nullptr;
2384  default:
2386  }
2387 }
2388 
2389 // Find reaching register definition
2391  MachineInstr &Use,
2393  LiveIntervals *LIS) const {
2394  auto &MDT = LIS->getAnalysis<MachineDominatorTree>();
2395  SlotIndex UseIdx = LIS->getInstructionIndex(Use);
2396  SlotIndex DefIdx;
2397 
2398  if (Reg.isVirtual()) {
2399  if (!LIS->hasInterval(Reg))
2400  return nullptr;
2401  LiveInterval &LI = LIS->getInterval(Reg);
2402  LaneBitmask SubLanes = SubReg ? getSubRegIndexLaneMask(SubReg)
2404  VNInfo *V = nullptr;
2405  if (LI.hasSubRanges()) {
2406  for (auto &S : LI.subranges()) {
2407  if ((S.LaneMask & SubLanes) == SubLanes) {
2408  V = S.getVNInfoAt(UseIdx);
2409  break;
2410  }
2411  }
2412  } else {
2413  V = LI.getVNInfoAt(UseIdx);
2414  }
2415  if (!V)
2416  return nullptr;
2417  DefIdx = V->def;
2418  } else {
2419  // Find last def.
2420  for (MCRegUnitIterator Units(Reg.asMCReg(), this); Units.isValid();
2421  ++Units) {
2422  LiveRange &LR = LIS->getRegUnit(*Units);
2423  if (VNInfo *V = LR.getVNInfoAt(UseIdx)) {
2424  if (!DefIdx.isValid() ||
2425  MDT.dominates(LIS->getInstructionFromIndex(DefIdx),
2426  LIS->getInstructionFromIndex(V->def)))
2427  DefIdx = V->def;
2428  } else {
2429  return nullptr;
2430  }
2431  }
2432  }
2433 
2434  MachineInstr *Def = LIS->getInstructionFromIndex(DefIdx);
2435 
2436  if (!Def || !MDT.dominates(Def, &Use))
2437  return nullptr;
2438 
2439  assert(Def->modifiesRegister(Reg, this));
2440 
2441  return Def;
2442 }
2443 
2445  assert(getRegSizeInBits(*getPhysRegClass(Reg)) <= 32);
2446 
2447  for (const TargetRegisterClass &RC : { AMDGPU::VGPR_32RegClass,
2448  AMDGPU::SReg_32RegClass,
2449  AMDGPU::AGPR_32RegClass } ) {
2450  if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::lo16, &RC))
2451  return Super;
2452  }
2453  if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::hi16,
2454  &AMDGPU::VGPR_32RegClass)) {
2455  return Super;
2456  }
2457 
2458  return AMDGPU::NoRegister;
2459 }
2460 
2462  if (!ST.needsAlignedVGPRs())
2463  return true;
2464 
2465  if (hasVGPRs(&RC))
2466  return RC.hasSuperClassEq(getVGPRClassForBitWidth(getRegSizeInBits(RC)));
2467  if (hasAGPRs(&RC))
2468  return RC.hasSuperClassEq(getAGPRClassForBitWidth(getRegSizeInBits(RC)));
2469 
2470  return true;
2471 }
2472 
2474  switch (PhysReg) {
2475  case AMDGPU::SGPR_NULL:
2476  case AMDGPU::SRC_SHARED_BASE:
2477  case AMDGPU::SRC_PRIVATE_BASE:
2478  case AMDGPU::SRC_SHARED_LIMIT:
2479  case AMDGPU::SRC_PRIVATE_LIMIT:
2480  return true;
2481  default:
2482  return false;
2483  }
2484 }
2485 
2488  return makeArrayRef(AMDGPU::SGPR_128RegClass.begin(),
2489  ST.getMaxNumSGPRs(MF) / 4);
2490 }
2491 
2494  return makeArrayRef(AMDGPU::SGPR_64RegClass.begin(),
2495  ST.getMaxNumSGPRs(MF) / 2);
2496 }
2497 
2500  return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(), ST.getMaxNumSGPRs(MF));
2501 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::LaneBitmask
Definition: LaneBitmask.h:39
i
i
Definition: README.txt:29
llvm::EngineKind::Kind
Kind
Definition: ExecutionEngine.h:524
llvm::SIRegisterInfo::getVGPRClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getVGPRClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:1918
llvm::SIRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Definition: SIRegisterInfo.cpp:344
llvm::SIRegisterInfo::getEquivalentVGPRClass
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
Definition: SIRegisterInfo.cpp:2114
llvm::SIMachineFunctionInfo::getSGPRSpillVGPRs
ArrayRef< SGPRSpillVGPR > getSGPRSpillVGPRs() const
Definition: SIMachineFunctionInfo.h:512
llvm::AMDGPUSubtarget::hasInv2PiInlineImm
bool hasInv2PiInlineImm() const
Definition: AMDGPUSubtarget.h:164
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm::SGPRSpillBuilder::TRI
const SIRegisterInfo & TRI
Definition: SIRegisterInfo.cpp:104
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:132
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:69
llvm
Definition: AllocatorList.h:23
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::Pass::getAnalysis
AnalysisType & getAnalysis() const
getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information ...
Definition: PassAnalysisSupport.h:230
llvm::SIRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const override
Definition: SIRegisterInfo.cpp:2473
llvm::SIRegisterInfo::needsFrameBaseReg
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:655
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::MachineFrameInfo::getNumFixedObjects
unsigned getNumFixedObjects() const
Return the number of fixed objects.
Definition: MachineFrameInfo.h:394
llvm::SIRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned RCID) const
Definition: SIRegisterInfo.cpp:2375
llvm::SGPRSpillBuilder::PerVGPRData
Definition: SIRegisterInfo.cpp:71
llvm::SIRegisterInfo::requiresVirtualBaseRegisters
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
Definition: SIRegisterInfo.cpp:627
SIMachineFunctionInfo.h
llvm::SlotIndex::isValid
bool isValid() const
Returns true if this is a valid index.
Definition: SlotIndexes.h:151
llvm::SGPRSpillBuilder::MBB
MachineBasicBlock & MBB
Definition: SIRegisterInfo.cpp:100
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MCRegister::from
static MCRegister from(unsigned Val)
Check the provided unsigned value is a valid MCRegister.
Definition: MCRegister.h:65
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:225
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::SIRegisterInfo::getAllSGPR128
ArrayRef< MCPhysReg > getAllSGPR128(const MachineFunction &MF) const
Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:2487
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:497
llvm::SIRegisterInfo::getFrameIndexInstrOffset
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
Definition: SIRegisterInfo.cpp:641
llvm::SIRegisterInfo::getRegUnitPressureSets
const int * getRegUnitPressureSets(unsigned RegUnit) const override
Definition: SIRegisterInfo.cpp:2319
llvm::SIRegisterInfo::getScratchInstrOffset
int64_t getScratchInstrOffset(const MachineInstr *MI) const
Definition: SIRegisterInfo.cpp:633
llvm::SGPRSpillBuilder::IsKill
bool IsKill
Definition: SIRegisterInfo.cpp:82
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::SIRegisterInfo::getAllSGPR64
ArrayRef< MCPhysReg > getAllSGPR64(const MachineFunction &MF) const
Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:2493
llvm::LiveIntervals::getInstructionFromIndex
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Definition: LiveIntervals.h:231
llvm::GCNSubtarget::needsAlignedVGPRs
bool needsAlignedVGPRs() const
Return if operations acting on VGPR tuples require even alignment.
Definition: GCNSubtarget.h:952
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:153
llvm::TargetRegisterInfo::shouldRealignStack
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
Definition: TargetRegisterInfo.cpp:464
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:48
llvm::SIRegisterInfo::SIRegisterInfo
SIRegisterInfo(const GCNSubtarget &ST)
Definition: SIRegisterInfo.cpp:273
llvm::SIMachineFunctionInfo::WWMReservedRegs
SparseBitVector WWMReservedRegs
Definition: SIMachineFunctionInfo.h:464
llvm::SIInstrFlags::FlatScratch
@ FlatScratch
Definition: SIDefines.h:109
llvm::VNInfo::def
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
getOffsetMUBUFStore
static int getOffsetMUBUFStore(unsigned Opc)
Definition: SIRegisterInfo.cpp:863
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:652
llvm::AMDGPUSubtarget::getOccupancyWithLocalMemSize
unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const
Inverse of getMaxLocalMemWithWaveCount.
Definition: AMDGPUSubtarget.cpp:361
llvm::BitVector::resize
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:333
llvm::reverse
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
Definition: STLExtras.h:338
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::AMDGPUMachineFunction::getLDSSize
unsigned getLDSSize() const
Definition: AMDGPUMachineFunction.h:70
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
llvm::SIRegisterInfo::getEquivalentAGPRClass
const TargetRegisterClass * getEquivalentAGPRClass(const TargetRegisterClass *SRC) const
Definition: SIRegisterInfo.cpp:2122
llvm::SIRegisterInfo::materializeFrameBaseRegister
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:669
llvm::SGPRSpillBuilder::TII
const SIInstrInfo & TII
Definition: SIRegisterInfo.cpp:103
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::GCNSubtarget
Definition: GCNSubtarget.h:38
llvm::SIRegisterInfo::getAllAllocatableSRegMask
const uint32_t * getAllAllocatableSRegMask() const
Definition: SIRegisterInfo.cpp:423
llvm::AMDGPU::OPERAND_REG_IMM_LAST
@ OPERAND_REG_IMM_LAST
Definition: SIDefines.h:172
getAlignedVGPRClassForBitWidth
static const TargetRegisterClass * getAlignedVGPRClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:1896
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
llvm::SIRegisterInfo::requiresFrameIndexReplacementScavenging
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:621
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:328
llvm::SIRegisterInfo::hasAGPRs
bool hasAGPRs(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.cpp:2101
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::cl::ReallyHidden
@ ReallyHidden
Definition: CommandLine.h:141
llvm::CallingConv::AMDGPU_Gfx
@ AMDGPU_Gfx
Calling convention used for AMD graphics targets.
Definition: CallingConv.h:245
llvm::Data
@ Data
Definition: SIMachineScheduler.h:56
llvm::PointerUnion::get
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:187
llvm::SIMachineFunctionInfo::SpilledReg
Definition: SIMachineFunctionInfo.h:437
llvm::SIRegisterInfo::getSubRegClass
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
Definition: SIRegisterInfo.cpp:2139
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
llvm::SIRegisterInfo::buildVGPRSpillLoadStore
void buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const
Definition: SIRegisterInfo.cpp:1275
llvm::SIRegisterInfo::findReachingDef
MachineInstr * findReachingDef(Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
Definition: SIRegisterInfo.cpp:2390
llvm::LiveIntervals::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
Definition: LiveIntervals.h:226
llvm::GCNSubtarget::getInstrInfo
const SIInstrInfo * getInstrInfo() const override
Definition: GCNSubtarget.h:214
llvm::SGPRSpillBuilder::getPerVGPRData
PerVGPRData getPerVGPRData()
Definition: SIRegisterInfo.cpp:137
getAnyVGPRClassForBitWidth
static const TargetRegisterClass * getAnyVGPRClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:1874
llvm::MachineFrameInfo::hasStackObjects
bool hasStackObjects() const
Return true if there are any stack objects in this function.
Definition: MachineFrameInfo.h:346
llvm::SIRegisterInfo::getRegClassForTypeOnBank
const TargetRegisterClass * getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank, const MachineRegisterInfo &MRI) const
Definition: SIRegisterInfo.h:268
llvm::SIFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: SIFrameLowering.cpp:1274
llvm::SIRegisterInfo::restoreSGPR
bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
Definition: SIRegisterInfo.cpp:1406
llvm::MachineMemOperand::getPointerInfo
const MachinePointerInfo & getPointerInfo() const
Definition: MachineMemOperand.h:191
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:387
llvm::SIRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:387
llvm::AMDGPU::OPERAND_REG_INLINE_AC_LAST
@ OPERAND_REG_INLINE_AC_LAST
Definition: SIDefines.h:178
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:503
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
lo16
We lo16(.CPI_X_0)(r2) lis r2
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::GCNSubtarget::getMaxNumSGPRs
unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const
Definition: GCNSubtarget.h:1011
llvm::MachineOperand::ChangeToRegister
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
Definition: MachineOperand.cpp:241
GCNSubtarget.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:534
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:653
llvm::RegScavenger::scavengeRegister
Register scavengeRegister(const TargetRegisterClass *RC, MachineBasicBlock::iterator I, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available and do the appropriate bookkeeping.
Definition: RegisterScavenging.cpp:521
llvm::SIRegisterInfo::buildSpillLoadStore
void buildSpillLoadStore(MachineBasicBlock::iterator MI, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LivePhysRegs *LiveRegs=nullptr) const
Definition: SIRegisterInfo.cpp:1023
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SIRegisterInfo::getReturnAddressReg
MCRegister getReturnAddressReg(const MachineFunction &MF) const
Definition: SIRegisterInfo.cpp:2328
llvm::SIRegisterInfo::getRegClassForReg
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2245
llvm::SIRegisterInfo::isAGPR
bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2257
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:156
llvm::alignDown
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
Definition: MathExtras.h:753
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:196
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::SGPRSpillBuilder::SavedExecReg
Register SavedExecReg
Definition: SIRegisterInfo.cpp:94
llvm::SIRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
Definition: SIRegisterInfo.cpp:1502
llvm::M0
unsigned M0(unsigned Val)
Definition: VE.h:371
llvm::SIRegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:2286
llvm::SIMachineFunctionInfo::getStackPtrOffsetReg
Register getStackPtrOffsetReg() const
Definition: SIMachineFunctionInfo.h:752
llvm::TargetRegisterClass::hasSuperClassEq
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Definition: TargetRegisterInfo.h:136
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
getAlignedAGPRClassForBitWidth
static const TargetRegisterClass * getAlignedAGPRClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:1952
llvm::SIRegisterInfo::spillSGPR
bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
If OnlyToVGPR is true, this will only succeed if this.
Definition: SIRegisterInfo.cpp:1308
llvm::MachineFrameInfo::getStackID
uint8_t getStackID(int ObjectIdx) const
Definition: MachineFrameInfo.h:720
llvm::SGPRSpillBuilder::IsWave32
bool IsWave32
Definition: SIRegisterInfo.cpp:105
llvm::RegisterBank::getID
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:47
llvm::SIRegisterInfo::getNumChannelsFromSubReg
unsigned getNumChannelsFromSubReg(unsigned SubReg) const
Definition: SIRegisterInfo.h:324
llvm::SIRegisterInfo::getSubRegFromChannel
static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs=1)
Definition: SIRegisterInfo.cpp:427
buildMUBUFOffsetLoadStore
static bool buildMUBUFOffsetLoadStore(const GCNSubtarget &ST, MachineFrameInfo &MFI, MachineBasicBlock::iterator MI, int Index, int64_t Offset)
Definition: SIRegisterInfo.cpp:950
llvm::SGPRSpillBuilder::ExecReg
Register ExecReg
Definition: SIRegisterInfo.cpp:106
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:504
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:29
llvm::SIRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: SIRegisterInfo.cpp:368
llvm::SIRegisterInfo::getVCC
MCRegister getVCC() const
Definition: SIRegisterInfo.cpp:2364
llvm::BitVector
Definition: BitVector.h:74
llvm::SGPRSpillBuilder::EltSize
unsigned EltSize
Definition: SIRegisterInfo.cpp:97
llvm::SIRegisterInfo::getVGPR64Class
const TargetRegisterClass * getVGPR64Class() const
Definition: SIRegisterInfo.cpp:2368
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:47
llvm::SGPRSpillBuilder::TmpVGPRIndex
int TmpVGPRIndex
Definition: SIRegisterInfo.cpp:90
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
llvm::SIFrameLowering
Definition: SIFrameLowering.h:21
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:677
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
llvm::GCNSubtarget::getMaxNumVGPRs
unsigned getMaxNumVGPRs(unsigned WavesPerEU) const
Definition: GCNSubtarget.h:1056
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:49
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:214
llvm::AMDGPUAS::PRIVATE_ADDRESS
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:378
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::AMDGPUSubtarget::getWavefrontSize
unsigned getWavefrontSize() const
Definition: AMDGPUSubtarget.h:180
llvm::SIRegisterInfo::opCanUseLiteralConstant
bool opCanUseLiteralConstant(unsigned OpType) const
Definition: SIRegisterInfo.cpp:2203
llvm::SIRegisterInfo::isFrameOffsetLegal
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:769
llvm::SIRegisterInfo::getBaseRegister
Register getBaseRegister() const
Definition: SIRegisterInfo.cpp:409
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:153
llvm::cl::opt< bool >
llvm::SIRegisterInfo::getAllVGPRRegMask
const uint32_t * getAllVGPRRegMask() const
Definition: SIRegisterInfo.cpp:411
llvm::AMDGPU::getRegBitWidth
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
Definition: AMDGPUBaseInfo.cpp:1553
llvm::SIMachineFunctionInfo::getVGPRSpillAGPRs
ArrayRef< MCPhysReg > getVGPRSpillAGPRs() const
Definition: SIMachineFunctionInfo.h:526
AMDGPURegisterBankInfo.h
llvm::SGPRSpillBuilder::SplitParts
ArrayRef< int16_t > SplitParts
Definition: SIRegisterInfo.cpp:80
AMDGPUMCTargetDesc.h
llvm::SIRegisterInfo::shouldRewriteCopySrc
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
Definition: SIRegisterInfo.cpp:2179
llvm::SIRegisterInfo::shouldRealignStack
bool shouldRealignStack(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:588
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:70
llvm::SIRegisterInfo::getRegAsmName
StringRef getRegAsmName(MCRegister Reg) const override
Definition: SIRegisterInfo.cpp:1869
LiveIntervals.h
llvm::MachineInstr::ReloadReuse
@ ReloadReuse
Definition: MachineInstr.h:75
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:228
llvm::SGPRSpillBuilder::NumSubRegs
unsigned NumSubRegs
Definition: SIRegisterInfo.cpp:81
llvm::LiveRange
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::SIRegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:612
llvm::SIRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: SIRegisterInfo.cpp:402
llvm::PointerUnion::dyn_cast
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
Definition: PointerUnion.h:194
llvm::LivePhysRegs::available
bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const
Returns true if register Reg and no aliasing register is in the set.
Definition: LivePhysRegs.cpp:139
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:37
llvm::SGPRSpillBuilder::PerVGPRData::VGPRLanes
int64_t VGPRLanes
Definition: SIRegisterInfo.cpp:74
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::SIInstrInfo::isFLATScratch
static bool isFLATScratch(const MachineInstr &MI)
Definition: SIInstrInfo.h:525
llvm::SIRegisterInfo::getAllVectorRegMask
const uint32_t * getAllVectorRegMask() const
Definition: SIRegisterInfo.cpp:419
llvm::SIRegisterInfo::getRegClassForSizeOnBank
const TargetRegisterClass * getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank, const MachineRegisterInfo &MRI) const
Definition: SIRegisterInfo.cpp:2334
llvm::AMDGPU::OPERAND_SRC_FIRST
@ OPERAND_SRC_FIRST
Definition: SIDefines.h:180
llvm::GCNSubtarget::hasMFMAInlineLiteralBug
bool hasMFMAInlineLiteralBug() const
Definition: GCNSubtarget.h:893
llvm::SIRegisterInfo::isSGPRReg
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2075
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:471
llvm::AMDGPUMachineFunction::isEntryFunction
bool isEntryFunction() const
Definition: AMDGPUMachineFunction.h:78
llvm::SIRegisterInfo::isVGPR
bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2250
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:440
llvm::CallingConv::Cold
@ Cold
Definition: CallingConv.h:48
AMDGPUInstPrinter.h
llvm::SIRegisterInfo::getBoolRC
const TargetRegisterClass * getBoolRC() const
Definition: SIRegisterInfo.h:278
llvm::MachineRegisterInfo::isAllocatable
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
Definition: MachineRegisterInfo.h:918
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SIMachineFunctionInfo::SpilledReg::Lane
int Lane
Definition: SIMachineFunctionInfo.h:439
llvm::SIRegisterInfo::getRegSplitParts
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
Definition: SIRegisterInfo.cpp:2229
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
llvm::SIMachineFunctionInfo::getScavengeFI
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:443
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:203
llvm::GCNSubtarget::hasGFX90AInsts
bool hasGFX90AInsts() const
Definition: GCNSubtarget.h:949
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:98
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:357
llvm::SIMachineFunctionInfo::addToSpilledSGPRs
void addToSpilledSGPRs(unsigned num)
Definition: SIMachineFunctionInfo.h:804
llvm::SIRegisterInfo::getAllAGPRRegMask
const uint32_t * getAllAGPRRegMask() const
Definition: SIRegisterInfo.cpp:415
llvm::SIRegisterInfo::isSGPRClass
bool isSGPRClass(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.h:154
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:114
llvm::MachinePointerInfo::getWithOffset
MachinePointerInfo getWithOffset(int64_t O) const
Definition: MachineMemOperand.h:79
llvm::MachineRegisterInfo::getRegClassOrRegBank
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
Definition: MachineRegisterInfo.h:668
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::AMDGPU::getFlatScratchInstSTfromSS
LLVM_READONLY int getFlatScratchInstSTfromSS(uint16_t Opcode)
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1486
llvm::SIRegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: SIRegisterInfo.cpp:383
getDebugLoc
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
Definition: MachineInstrBundle.cpp:109
llvm::SIRegisterInfo::get32BitRegister
MCPhysReg get32BitRegister(MCPhysReg Reg) const
Definition: SIRegisterInfo.cpp:2444
llvm::RegState::ImplicitKill
@ ImplicitKill
Definition: MachineInstrBuilder.h:65
llvm::ArrayRef< int16_t >
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::SGPRSpillBuilder::NotOpc
unsigned NotOpc
Definition: SIRegisterInfo.cpp:108
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
AMDGPU.h
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:478
llvm::SGPRSpillBuilder::TmpVGPR
Register TmpVGPR
Definition: SIRegisterInfo.cpp:88
llvm::SIRegisterInfo::isProperlyAlignedRC
bool isProperlyAlignedRC(const TargetRegisterClass &RC) const
Definition: SIRegisterInfo.cpp:2461
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::AMDGPUInstPrinter::getRegisterName
static const char * getRegisterName(unsigned RegNo)
getNumSubRegsForSpillOp
static unsigned getNumSubRegsForSpillOp(unsigned Op)
Definition: SIRegisterInfo.cpp:793
llvm::SGPRSpillBuilder::TmpVGPRLive
bool TmpVGPRLive
Definition: SIRegisterInfo.cpp:92
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:759
uint32_t
llvm::SGPRSpillBuilder::prepare
void prepare()
Definition: SIRegisterInfo.cpp:158
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SIMachineFunctionInfo::getVGPRToAGPRSpill
MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const
Definition: SIMachineFunctionInfo.h:530
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
SubRegFromChannelTableWidthMap
static const std::array< unsigned, 17 > SubRegFromChannelTableWidthMap
Definition: SIRegisterInfo.cpp:43
llvm::SIRegisterInfo::getCalleeSavedRegsViaCopy
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
Definition: SIRegisterInfo.cpp:364
llvm::SIMachineFunctionInfo::getScratchRSrcReg
Register getScratchRSrcReg() const
Returns the physical register reserved for use as the resource descriptor for scratch accesses.
Definition: SIMachineFunctionInfo.h:725
llvm::once_flag
std::once_flag once_flag
Definition: Threading.h:89
llvm::SIInstrInfo::isMUBUF
static bool isMUBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:449
llvm::SIRegisterInfo::resolveFrameIndex
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:720
llvm::SGPRSpillBuilder::Index
int Index
Definition: SIRegisterInfo.cpp:96
llvm::SIRegisterInfo::hasVGPRs
bool hasVGPRs(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.cpp:2087
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:90
llvm::SGPRSpillBuilder
Definition: SIRegisterInfo.cpp:70
llvm::GCNSubtarget::enableFlatScratch
bool enableFlatScratch() const
Definition: AMDGPUSubtarget.cpp:324
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::PointerUnion
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
Definition: PointerUnion.h:149
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::GCNSubtarget::hasFlatScratchSTMode
bool hasFlatScratchSTMode() const
Definition: GCNSubtarget.h:563
llvm::SIRegisterInfo::getRegPressureSetLimit
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
Definition: SIRegisterInfo.cpp:2305
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:602
llvm::SIInstrInfo::isLegalMUBUFImmOffset
static bool isLegalMUBUFImmOffset(unsigned Imm)
Definition: SIInstrInfo.h:1065
llvm::SIRegisterInfo::getAllSGPR32
ArrayRef< MCPhysReg > getAllSGPR32(const MachineFunction &MF) const
Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:2499
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::SGPRSpillBuilder::RS
RegScavenger * RS
Definition: SIRegisterInfo.cpp:99
llvm::commonAlignment
Align commonAlignment(Align A, Align B)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:221
llvm::AMDGPU::OPERAND_SRC_LAST
@ OPERAND_SRC_LAST
Definition: SIDefines.h:181
llvm::MachineRegisterInfo::getMaxLaneMaskForVReg
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Definition: MachineRegisterInfo.cpp:493
llvm::call_once
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:119
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::SGPRSpillBuilder::PerVGPRData::NumVGPRs
unsigned NumVGPRs
Definition: SIRegisterInfo.cpp:73
uint16_t
llvm::SGPRSpillBuilder::MI
MachineBasicBlock::iterator MI
Definition: SIRegisterInfo.cpp:79
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
AMDGPUGenRegisterInfo
llvm::MachineInstr::setAsmPrinterFlag
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:315
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:53
llvm::SIMachineFunctionInfo::SpilledReg::VGPR
Register VGPR
Definition: SIMachineFunctionInfo.h:438
llvm::RegScavenger::setRegUsed
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
Definition: RegisterScavenging.cpp:53
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
getRegClass
static int getRegClass(RegisterKind Is, unsigned RegWidth)
Definition: AMDGPUAsmParser.cpp:2177
llvm::SGPRSpillBuilder::readWriteTmpVGPR
void readWriteTmpVGPR(unsigned Offset, bool IsLoad)
Definition: SIRegisterInfo.cpp:255
llvm::SIMachineFunctionInfo::getAGPRSpillVGPRs
ArrayRef< MCPhysReg > getAGPRSpillVGPRs() const
Definition: SIMachineFunctionInfo.h:522
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::MachineRegisterInfo::isPhysRegUsed
bool isPhysRegUsed(MCRegister PhysReg) const
Return true if the specified register is modified or read in this function.
Definition: MachineRegisterInfo.cpp:585
llvm::VNInfo
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
llvm::LiveRange::getVNInfoAt
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:413
llvm::TargetRegisterClass::MC
const MCRegisterClass * MC
Definition: TargetRegisterInfo.h:53
llvm::TargetStackID::SGPRSpill
@ SGPRSpill
Definition: TargetFrameLowering.h:29
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:320
llvm::SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const
Special case of eliminateFrameIndex.
Definition: SIRegisterInfo.cpp:1472
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:403
llvm::SGPRSpillBuilder::SuperReg
Register SuperReg
Definition: SIRegisterInfo.cpp:78
llvm::AMDGPU::OPERAND_REG_IMM_FIRST
@ OPERAND_REG_IMM_FIRST
Definition: SIDefines.h:171
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:474
llvm::SGPRSpillBuilder::MFI
SIMachineFunctionInfo & MFI
Definition: SIRegisterInfo.cpp:102
llvm::SIInstrInfo
Definition: SIInstrInfo.h:38
llvm::AMDGPU::isInlinableLiteral32
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:1665
llvm::SIRegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
Definition: SIRegisterInfo.cpp:601
llvm::SIRegisterInfo::getConstrainedRegClassForOperand
const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
Definition: SIRegisterInfo.cpp:2354
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:677
llvm::SGPRSpillBuilder::restore
void restore()
Definition: SIRegisterInfo.cpp:221
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:509
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::SGPRSpillBuilder::DL
const DebugLoc & DL
Definition: SIRegisterInfo.cpp:83
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:995
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
llvm::SGPRSpillBuilder::PerVGPRData::PerVGPR
unsigned PerVGPR
Definition: SIRegisterInfo.cpp:72
spillVGPRtoAGPR
static MachineInstrBuilder spillVGPRtoAGPR(const GCNSubtarget &ST, MachineBasicBlock::iterator MI, int Index, unsigned Lane, unsigned ValueReg, bool IsKill)
Definition: SIRegisterInfo.cpp:917
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:329
llvm::Register::isValid
bool isValid() const
Definition: Register.h:126
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:331
llvm::PseudoProbeAttributes::Reserved
@ Reserved
llvm::LiveInterval::hasSubRanges
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:797
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
llvm::SIRegisterInfo::findUnusedRegister
MCRegister findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const
Returns a lowest register that is not used at any point in the function.
Definition: SIRegisterInfo.cpp:2213
llvm::SGPRSpillBuilder::MovOpc
unsigned MovOpc
Definition: SIRegisterInfo.cpp:107
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SIRegisterInfo::getCompatibleSubRegClass
const TargetRegisterClass * getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const
Returns a register class which is compatible with SuperRC, such that a subregister exists with class ...
Definition: SIRegisterInfo.cpp:2161
llvm::SIRegisterInfo::getAGPRClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getAGPRClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:1974
llvm::TargetRegisterClass::hasSubClassEq
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition: TargetRegisterInfo.h:124
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FIRST
@ OPERAND_REG_INLINE_AC_FIRST
Definition: SIDefines.h:177
getOffsetMUBUFLoad
static int getOffsetMUBUFLoad(unsigned Opc)
Definition: SIRegisterInfo.cpp:884
llvm::SIMachineFunctionInfo::addToSpilledVGPRs
void addToSpilledVGPRs(unsigned num)
Definition: SIMachineFunctionInfo.h:808
llvm::SGPRSpillBuilder::MF
MachineFunction & MF
Definition: SIRegisterInfo.cpp:101
getAnyAGPRClassForBitWidth
static const TargetRegisterClass * getAnyAGPRClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:1930
llvm::LiveIntervals::hasInterval
bool hasInterval(Register Reg) const
Definition: LiveIntervals.h:125
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:411
llvm::SIRegisterInfo::opCanUseInlineConstant
bool opCanUseInlineConstant(unsigned OpType) const
Definition: SIRegisterInfo.cpp:2170
llvm::SIRegisterInfo::shouldCoalesce
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
Definition: SIRegisterInfo.cpp:2265
RegisterScavenging.h
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:45
llvm::SGPRSpillBuilder::SGPRSpillBuilder
SGPRSpillBuilder(const SIRegisterInfo &TRI, const SIInstrInfo &TII, bool IsWave32, MachineBasicBlock::iterator MI, int Index, RegScavenger *RS)
Definition: SIRegisterInfo.cpp:110
llvm::AMDGPUSubtarget::getWavefrontSizeLog2
unsigned getWavefrontSizeLog2() const
Definition: AMDGPUSubtarget.h:184
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:64
llvm::SIMachineFunctionInfo::getSGPRToVGPRSpills
ArrayRef< SpilledReg > getSGPRToVGPRSpills(int FrameIndex) const
Definition: SIMachineFunctionInfo.h:506
getFlatScratchSpillOpcode
static unsigned getFlatScratchSpillOpcode(const SIInstrInfo *TII, unsigned LoadStoreOp, unsigned EltSize)
Definition: SIRegisterInfo.cpp:988
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:209
llvm::SIRegisterInfo::getEquivalentSGPRClass
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
Definition: SIRegisterInfo.cpp:2130
SIRegisterInfo.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::SIRegisterInfo::reservedPrivateSegmentBufferReg
MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed.
Definition: SIRegisterInfo.cpp:436
llvm::SIRegisterInfo::getPhysRegClass
const TargetRegisterClass * getPhysRegClass(MCRegister Reg) const
Return the 'base' register class for this register.
Definition: SIRegisterInfo.cpp:2012
llvm::SIRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:443
llvm::SIMachineFunctionInfo::getFrameOffsetReg
Register getFrameOffsetReg() const
Definition: SIMachineFunctionInfo.h:734
llvm::SIRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: SIRegisterInfo.cpp:785
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
EnableSpillSGPRToVGPR
static cl::opt< bool > EnableSpillSGPRToVGPR("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling VGPRs to SGPRs"), cl::ReallyHidden, cl::init(true))
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:580
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
llvm::LiveIntervals::getRegUnit
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
Definition: LiveIntervals.h:393
llvm::GCNSubtarget::hasMAIInsts
bool hasMAIInsts() const
Definition: GCNSubtarget.h:696
MachineDominators.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
llvm::SIRegisterInfo::getSGPRClassForBitWidth
static const LLVM_READONLY TargetRegisterClass * getSGPRClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:1984
llvm::LiveInterval::subranges
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:769