LLVM  15.0.0git
SIRegisterInfo.cpp
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1 //===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// SI implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SIRegisterInfo.h"
15 #include "AMDGPU.h"
16 #include "AMDGPURegisterBankInfo.h"
17 #include "GCNSubtarget.h"
20 #include "SIMachineFunctionInfo.h"
26 
27 using namespace llvm;
28 
29 #define GET_REGINFO_TARGET_DESC
30 #include "AMDGPUGenRegisterInfo.inc"
31 
33  "amdgpu-spill-sgpr-to-vgpr",
34  cl::desc("Enable spilling VGPRs to SGPRs"),
36  cl::init(true));
37 
38 std::array<std::vector<int16_t>, 16> SIRegisterInfo::RegSplitParts;
39 std::array<std::array<uint16_t, 32>, 9> SIRegisterInfo::SubRegFromChannelTable;
40 
41 // Map numbers of DWORDs to indexes in SubRegFromChannelTable.
42 // Valid indexes are shifted 1, such that a 0 mapping means unsupported.
43 // e.g. for 8 DWORDs (256-bit), SubRegFromChannelTableWidthMap[8] = 8,
44 // meaning index 7 in SubRegFromChannelTable.
45 static const std::array<unsigned, 17> SubRegFromChannelTableWidthMap = {
46  0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 9};
47 
48 namespace llvm {
49 
50 // A temporary struct to spill SGPRs.
51 // This is mostly to spill SGPRs to memory. Spilling SGPRs into VGPR lanes emits
52 // just v_writelane and v_readlane.
53 //
54 // When spilling to memory, the SGPRs are written into VGPR lanes and the VGPR
55 // is saved to scratch (or the other way around for loads).
56 // For this, a VGPR is required where the needed lanes can be clobbered. The
57 // RegScavenger can provide a VGPR where currently active lanes can be
58 // clobbered, but we still need to save inactive lanes.
59 // The high-level steps are:
60 // - Try to scavenge SGPR(s) to save exec
61 // - Try to scavenge VGPR
62 // - Save needed, all or inactive lanes of a TmpVGPR
63 // - Spill/Restore SGPRs using TmpVGPR
64 // - Restore TmpVGPR
65 //
66 // To save all lanes of TmpVGPR, exec needs to be saved and modified. If we
67 // cannot scavenge temporary SGPRs to save exec, we use the following code:
68 // buffer_store_dword TmpVGPR ; only if active lanes need to be saved
69 // s_not exec, exec
70 // buffer_store_dword TmpVGPR ; save inactive lanes
71 // s_not exec, exec
73  struct PerVGPRData {
74  unsigned PerVGPR;
75  unsigned NumVGPRs;
76  int64_t VGPRLanes;
77  };
78 
79  // The SGPR to save
83  unsigned NumSubRegs;
84  bool IsKill;
85  const DebugLoc &DL;
86 
87  /* When spilling to stack */
88  // The SGPRs are written into this VGPR, which is then written to scratch
89  // (or vice versa for loads).
90  Register TmpVGPR = AMDGPU::NoRegister;
91  // Temporary spill slot to save TmpVGPR to.
92  int TmpVGPRIndex = 0;
93  // If TmpVGPR is live before the spill or if it is scavenged.
94  bool TmpVGPRLive = false;
95  // Scavenged SGPR to save EXEC.
96  Register SavedExecReg = AMDGPU::NoRegister;
97  // Stack index to write the SGPRs to.
98  int Index;
99  unsigned EltSize = 4;
100 
105  const SIInstrInfo &TII;
107  bool IsWave32;
109  unsigned MovOpc;
110  unsigned NotOpc;
111 
114  RegScavenger *RS)
115  : SGPRSpillBuilder(TRI, TII, IsWave32, MI, MI->getOperand(0).getReg(),
116  MI->getOperand(0).isKill(), Index, RS) {}
117 
120  bool IsKill, int Index, RegScavenger *RS)
121  : SuperReg(Reg), MI(MI), IsKill(IsKill), DL(MI->getDebugLoc()),
122  Index(Index), RS(RS), MBB(MI->getParent()), MF(*MBB->getParent()),
123  MFI(*MF.getInfo<SIMachineFunctionInfo>()), TII(TII), TRI(TRI),
124  IsWave32(IsWave32) {
128 
129  if (IsWave32) {
130  ExecReg = AMDGPU::EXEC_LO;
131  MovOpc = AMDGPU::S_MOV_B32;
132  NotOpc = AMDGPU::S_NOT_B32;
133  } else {
134  ExecReg = AMDGPU::EXEC;
135  MovOpc = AMDGPU::S_MOV_B64;
136  NotOpc = AMDGPU::S_NOT_B64;
137  }
138 
139  assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
140  assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI &&
141  SuperReg != AMDGPU::EXEC && "exec should never spill");
142  }
143 
146  Data.PerVGPR = IsWave32 ? 32 : 64;
147  Data.NumVGPRs = (NumSubRegs + (Data.PerVGPR - 1)) / Data.PerVGPR;
148  Data.VGPRLanes = (1LL << std::min(Data.PerVGPR, NumSubRegs)) - 1LL;
149  return Data;
150  }
151 
152  // Tries to scavenge SGPRs to save EXEC and a VGPR. Uses v0 if no VGPR is
153  // free.
154  // Writes these instructions if an SGPR can be scavenged:
155  // s_mov_b64 s[6:7], exec ; Save exec
156  // s_mov_b64 exec, 3 ; Wanted lanemask
157  // buffer_store_dword v1 ; Write scavenged VGPR to emergency slot
158  //
159  // Writes these instructions if no SGPR can be scavenged:
160  // buffer_store_dword v0 ; Only if no free VGPR was found
161  // s_not_b64 exec, exec
162  // buffer_store_dword v0 ; Save inactive lanes
163  // ; exec stays inverted, it is flipped back in
164  // ; restore.
165  void prepare() {
166  // Scavenged temporary VGPR to use. It must be scavenged once for any number
167  // of spilled subregs.
168  // FIXME: The liveness analysis is limited and does not tell if a register
169  // is in use in lanes that are currently inactive. We can never be sure if
170  // a register as actually in use in another lane, so we need to save all
171  // used lanes of the chosen VGPR.
172  assert(RS && "Cannot spill SGPR to memory without RegScavenger");
173  TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0, false);
174 
175  // Reserve temporary stack slot
177  if (TmpVGPR) {
178  // Found a register that is dead in the currently active lanes, we only
179  // need to spill inactive lanes.
180  TmpVGPRLive = false;
181  } else {
182  // Pick v0 because it doesn't make a difference.
183  TmpVGPR = AMDGPU::VGPR0;
184  TmpVGPRLive = true;
185  }
186 
187  if (TmpVGPRLive) {
188  // We need to inform the scavenger that this index is already in use until
189  // we're done with the custom emergency spill.
191  }
192 
193  // We may end up recursively calling the scavenger, and don't want to re-use
194  // the same register.
196 
197  // Try to scavenge SGPRs to save exec
198  assert(!SavedExecReg && "Exec is already saved, refuse to save again");
199  const TargetRegisterClass &RC =
200  IsWave32 ? AMDGPU::SGPR_32RegClass : AMDGPU::SGPR_64RegClass;
202  SavedExecReg = RS->scavengeRegister(&RC, MI, 0, false);
203 
204  int64_t VGPRLanes = getPerVGPRData().VGPRLanes;
205 
206  if (SavedExecReg) {
208  // Set exec to needed lanes
210  auto I =
211  BuildMI(*MBB, MI, DL, TII.get(MovOpc), ExecReg).addImm(VGPRLanes);
212  if (!TmpVGPRLive)
214  // Spill needed lanes
215  TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ false);
216  } else {
217  // The modify and restore of exec clobber SCC, which we would have to save
218  // and restore. FIXME: We probably would need to reserve a register for
219  // this.
220  if (RS->isRegUsed(AMDGPU::SCC))
221  MI->emitError("unhandled SGPR spill to memory");
222 
223  // Spill active lanes
224  if (TmpVGPRLive)
225  TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ false,
226  /*IsKill*/ false);
227  // Spill inactive lanes
228  auto I = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
229  if (!TmpVGPRLive)
231  I->getOperand(2).setIsDead(true); // Mark SCC as dead.
232  TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ false);
233  }
234  }
235 
236  // Writes these instructions if an SGPR can be scavenged:
237  // buffer_load_dword v1 ; Write scavenged VGPR to emergency slot
238  // s_waitcnt vmcnt(0) ; If a free VGPR was found
239  // s_mov_b64 exec, s[6:7] ; Save exec
240  //
241  // Writes these instructions if no SGPR can be scavenged:
242  // buffer_load_dword v0 ; Restore inactive lanes
243  // s_waitcnt vmcnt(0) ; If a free VGPR was found
244  // s_not_b64 exec, exec
245  // buffer_load_dword v0 ; Only if no free VGPR was found
246  void restore() {
247  if (SavedExecReg) {
248  // Restore used lanes
249  TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ true,
250  /*IsKill*/ false);
251  // Restore exec
252  auto I = BuildMI(*MBB, MI, DL, TII.get(MovOpc), ExecReg)
254  // Add an implicit use of the load so it is not dead.
255  // FIXME This inserts an unnecessary waitcnt
256  if (!TmpVGPRLive) {
258  }
259  } else {
260  // Restore inactive lanes
261  TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ true,
262  /*IsKill*/ false);
263  auto I = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
264  if (!TmpVGPRLive)
266  I->getOperand(2).setIsDead(true); // Mark SCC as dead.
267 
268  // Restore active lanes
269  if (TmpVGPRLive)
270  TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ true);
271  }
272 
273  // Inform the scavenger where we're releasing our custom scavenged register.
274  if (TmpVGPRLive) {
275  MachineBasicBlock::iterator RestorePt = std::prev(MI);
277  }
278  }
279 
280  // Write TmpVGPR to memory or read TmpVGPR from memory.
281  // Either using a single buffer_load/store if exec is set to the needed mask
282  // or using
283  // buffer_load
284  // s_not exec, exec
285  // buffer_load
286  // s_not exec, exec
287  void readWriteTmpVGPR(unsigned Offset, bool IsLoad) {
288  if (SavedExecReg) {
289  // Spill needed lanes
290  TRI.buildVGPRSpillLoadStore(*this, Index, Offset, IsLoad);
291  } else {
292  // The modify and restore of exec clobber SCC, which we would have to save
293  // and restore. FIXME: We probably would need to reserve a register for
294  // this.
295  if (RS->isRegUsed(AMDGPU::SCC))
296  MI->emitError("unhandled SGPR spill to memory");
297 
298  // Spill active lanes
299  TRI.buildVGPRSpillLoadStore(*this, Index, Offset, IsLoad,
300  /*IsKill*/ false);
301  // Spill inactive lanes
302  auto Not0 = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
303  Not0->getOperand(2).setIsDead(); // Mark SCC as dead.
304  TRI.buildVGPRSpillLoadStore(*this, Index, Offset, IsLoad);
305  auto Not1 = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
306  Not1->getOperand(2).setIsDead(); // Mark SCC as dead.
307  }
308  }
309 
311  assert(MBB->getParent() == &MF);
312  MI = NewMI;
313  MBB = NewMBB;
314  }
315 };
316 
317 } // namespace llvm
318 
320  : AMDGPUGenRegisterInfo(AMDGPU::PC_REG, ST.getAMDGPUDwarfFlavour()), ST(ST),
321  SpillSGPRToVGPR(EnableSpillSGPRToVGPR), isWave32(ST.isWave32()) {
322 
323  assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 &&
324  getSubRegIndexLaneMask(AMDGPU::sub31).getAsInteger() == (3ULL << 62) &&
325  (getSubRegIndexLaneMask(AMDGPU::lo16) |
326  getSubRegIndexLaneMask(AMDGPU::hi16)).getAsInteger() ==
327  getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() &&
328  "getNumCoveredRegs() will not work with generated subreg masks!");
329 
330  RegPressureIgnoredUnits.resize(getNumRegUnits());
331  RegPressureIgnoredUnits.set(
333  for (auto Reg : AMDGPU::VGPR_HI16RegClass)
334  RegPressureIgnoredUnits.set(*MCRegUnitIterator(Reg, this));
335 
336  // HACK: Until this is fully tablegen'd.
337  static llvm::once_flag InitializeRegSplitPartsFlag;
338 
339  static auto InitializeRegSplitPartsOnce = [this]() {
340  for (unsigned Idx = 1, E = getNumSubRegIndices() - 1; Idx < E; ++Idx) {
341  unsigned Size = getSubRegIdxSize(Idx);
342  if (Size & 31)
343  continue;
344  std::vector<int16_t> &Vec = RegSplitParts[Size / 32 - 1];
345  unsigned Pos = getSubRegIdxOffset(Idx);
346  if (Pos % Size)
347  continue;
348  Pos /= Size;
349  if (Vec.empty()) {
350  unsigned MaxNumParts = 1024 / Size; // Maximum register is 1024 bits.
351  Vec.resize(MaxNumParts);
352  }
353  Vec[Pos] = Idx;
354  }
355  };
356 
357  static llvm::once_flag InitializeSubRegFromChannelTableFlag;
358 
359  static auto InitializeSubRegFromChannelTableOnce = [this]() {
360  for (auto &Row : SubRegFromChannelTable)
361  Row.fill(AMDGPU::NoSubRegister);
362  for (unsigned Idx = 1; Idx < getNumSubRegIndices(); ++Idx) {
363  unsigned Width = AMDGPUSubRegIdxRanges[Idx].Size / 32;
364  unsigned Offset = AMDGPUSubRegIdxRanges[Idx].Offset / 32;
367  if (Width == 0)
368  continue;
369  unsigned TableIdx = Width - 1;
370  assert(TableIdx < SubRegFromChannelTable.size());
371  assert(Offset < SubRegFromChannelTable[TableIdx].size());
372  SubRegFromChannelTable[TableIdx][Offset] = Idx;
373  }
374  };
375 
376  llvm::call_once(InitializeRegSplitPartsFlag, InitializeRegSplitPartsOnce);
377  llvm::call_once(InitializeSubRegFromChannelTableFlag,
378  InitializeSubRegFromChannelTableOnce);
379 }
380 
381 void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved,
382  MCRegister Reg) const {
383  MCRegAliasIterator R(Reg, this, true);
384 
385  for (; R.isValid(); ++R)
386  Reserved.set(*R);
387 }
388 
389 // Forced to be here by one .inc
391  const MachineFunction *MF) const {
393  switch (CC) {
394  case CallingConv::C:
395  case CallingConv::Fast:
396  case CallingConv::Cold:
397  return ST.hasGFX90AInsts() ? CSR_AMDGPU_HighRegs_With_AGPRs_SaveList
398  : CSR_AMDGPU_HighRegs_SaveList;
400  return ST.hasGFX90AInsts() ? CSR_AMDGPU_SI_Gfx_With_AGPRs_SaveList
401  : CSR_AMDGPU_SI_Gfx_SaveList;
402  default: {
403  // Dummy to not crash RegisterClassInfo.
404  static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
405  return &NoCalleeSavedReg;
406  }
407  }
408 }
409 
410 const MCPhysReg *
412  return nullptr;
413 }
414 
416  CallingConv::ID CC) const {
417  switch (CC) {
418  case CallingConv::C:
419  case CallingConv::Fast:
420  case CallingConv::Cold:
421  return ST.hasGFX90AInsts() ? CSR_AMDGPU_HighRegs_With_AGPRs_RegMask
422  : CSR_AMDGPU_HighRegs_RegMask;
424  return ST.hasGFX90AInsts() ? CSR_AMDGPU_SI_Gfx_With_AGPRs_RegMask
425  : CSR_AMDGPU_SI_Gfx_RegMask;
426  default:
427  return nullptr;
428  }
429 }
430 
432  return CSR_AMDGPU_NoRegs_RegMask;
433 }
434 
435 const TargetRegisterClass *
437  const MachineFunction &MF) const {
438  // FIXME: Should have a helper function like getEquivalentVGPRClass to get the
439  // equivalent AV class. If used one, the verifier will crash after
440  // RegBankSelect in the GISel flow. The aligned regclasses are not fully given
441  // until Instruction selection.
442  if (ST.hasMAIInsts() && (isVGPRClass(RC) || isAGPRClass(RC))) {
443  if (RC == &AMDGPU::VGPR_32RegClass || RC == &AMDGPU::AGPR_32RegClass)
444  return &AMDGPU::AV_32RegClass;
445  if (RC == &AMDGPU::VReg_64RegClass || RC == &AMDGPU::AReg_64RegClass)
446  return &AMDGPU::AV_64RegClass;
447  if (RC == &AMDGPU::VReg_64_Align2RegClass ||
448  RC == &AMDGPU::AReg_64_Align2RegClass)
449  return &AMDGPU::AV_64_Align2RegClass;
450  if (RC == &AMDGPU::VReg_96RegClass || RC == &AMDGPU::AReg_96RegClass)
451  return &AMDGPU::AV_96RegClass;
452  if (RC == &AMDGPU::VReg_96_Align2RegClass ||
453  RC == &AMDGPU::AReg_96_Align2RegClass)
454  return &AMDGPU::AV_96_Align2RegClass;
455  if (RC == &AMDGPU::VReg_128RegClass || RC == &AMDGPU::AReg_128RegClass)
456  return &AMDGPU::AV_128RegClass;
457  if (RC == &AMDGPU::VReg_128_Align2RegClass ||
458  RC == &AMDGPU::AReg_128_Align2RegClass)
459  return &AMDGPU::AV_128_Align2RegClass;
460  if (RC == &AMDGPU::VReg_160RegClass || RC == &AMDGPU::AReg_160RegClass)
461  return &AMDGPU::AV_160RegClass;
462  if (RC == &AMDGPU::VReg_160_Align2RegClass ||
463  RC == &AMDGPU::AReg_160_Align2RegClass)
464  return &AMDGPU::AV_160_Align2RegClass;
465  if (RC == &AMDGPU::VReg_192RegClass || RC == &AMDGPU::AReg_192RegClass)
466  return &AMDGPU::AV_192RegClass;
467  if (RC == &AMDGPU::VReg_192_Align2RegClass ||
468  RC == &AMDGPU::AReg_192_Align2RegClass)
469  return &AMDGPU::AV_192_Align2RegClass;
470  if (RC == &AMDGPU::VReg_256RegClass || RC == &AMDGPU::AReg_256RegClass)
471  return &AMDGPU::AV_256RegClass;
472  if (RC == &AMDGPU::VReg_256_Align2RegClass ||
473  RC == &AMDGPU::AReg_256_Align2RegClass)
474  return &AMDGPU::AV_256_Align2RegClass;
475  if (RC == &AMDGPU::VReg_512RegClass || RC == &AMDGPU::AReg_512RegClass)
476  return &AMDGPU::AV_512RegClass;
477  if (RC == &AMDGPU::VReg_512_Align2RegClass ||
478  RC == &AMDGPU::AReg_512_Align2RegClass)
479  return &AMDGPU::AV_512_Align2RegClass;
480  if (RC == &AMDGPU::VReg_1024RegClass || RC == &AMDGPU::AReg_1024RegClass)
481  return &AMDGPU::AV_1024RegClass;
482  if (RC == &AMDGPU::VReg_1024_Align2RegClass ||
483  RC == &AMDGPU::AReg_1024_Align2RegClass)
484  return &AMDGPU::AV_1024_Align2RegClass;
485  }
486 
488 }
489 
491  const SIFrameLowering *TFI = ST.getFrameLowering();
492  const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
493  // During ISel lowering we always reserve the stack pointer in entry
494  // functions, but never actually want to reference it when accessing our own
495  // frame. If we need a frame pointer we use it, but otherwise we can just use
496  // an immediate "0" which we represent by returning NoRegister.
497  if (FuncInfo->isEntryFunction()) {
498  return TFI->hasFP(MF) ? FuncInfo->getFrameOffsetReg() : Register();
499  }
500  return TFI->hasFP(MF) ? FuncInfo->getFrameOffsetReg()
501  : FuncInfo->getStackPtrOffsetReg();
502 }
503 
505  // When we need stack realignment, we can't reference off of the
506  // stack pointer, so we reserve a base pointer.
507  const MachineFrameInfo &MFI = MF.getFrameInfo();
508  return MFI.getNumFixedObjects() && shouldRealignStack(MF);
509 }
510 
511 Register SIRegisterInfo::getBaseRegister() const { return AMDGPU::SGPR34; }
512 
514  return CSR_AMDGPU_AllVGPRs_RegMask;
515 }
516 
518  return CSR_AMDGPU_AllAGPRs_RegMask;
519 }
520 
522  return CSR_AMDGPU_AllVectorRegs_RegMask;
523 }
524 
526  return CSR_AMDGPU_AllAllocatableSRegs_RegMask;
527 }
528 
529 unsigned SIRegisterInfo::getSubRegFromChannel(unsigned Channel,
530  unsigned NumRegs) {
531  assert(NumRegs < SubRegFromChannelTableWidthMap.size());
532  unsigned NumRegIndex = SubRegFromChannelTableWidthMap[NumRegs];
533  assert(NumRegIndex && "Not implemented");
534  assert(Channel < SubRegFromChannelTable[NumRegIndex - 1].size());
535  return SubRegFromChannelTable[NumRegIndex - 1][Channel];
536 }
537 
539  const MachineFunction &MF) const {
540  unsigned BaseIdx = alignDown(ST.getMaxNumSGPRs(MF), 4) - 4;
541  MCRegister BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx));
542  return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SGPR_128RegClass);
543 }
544 
546  BitVector Reserved(getNumRegs());
547  Reserved.set(AMDGPU::MODE);
548 
550 
551  // Reserve special purpose registers.
552  //
553  // EXEC_LO and EXEC_HI could be allocated and used as regular register, but
554  // this seems likely to result in bugs, so I'm marking them as reserved.
555  reserveRegisterTuples(Reserved, AMDGPU::EXEC);
556  reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);
557 
558  // M0 has to be reserved so that llvm accepts it as a live-in into a block.
559  reserveRegisterTuples(Reserved, AMDGPU::M0);
560 
561  // Reserve src_vccz, src_execz, src_scc.
562  reserveRegisterTuples(Reserved, AMDGPU::SRC_VCCZ);
563  reserveRegisterTuples(Reserved, AMDGPU::SRC_EXECZ);
564  reserveRegisterTuples(Reserved, AMDGPU::SRC_SCC);
565 
566  // Reserve the memory aperture registers.
567  reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_BASE);
568  reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_LIMIT);
569  reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_BASE);
570  reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_LIMIT);
571 
572  // Reserve src_pops_exiting_wave_id - support is not implemented in Codegen.
573  reserveRegisterTuples(Reserved, AMDGPU::SRC_POPS_EXITING_WAVE_ID);
574 
575  // Reserve xnack_mask registers - support is not implemented in Codegen.
576  reserveRegisterTuples(Reserved, AMDGPU::XNACK_MASK);
577 
578  // Reserve lds_direct register - support is not implemented in Codegen.
579  reserveRegisterTuples(Reserved, AMDGPU::LDS_DIRECT);
580 
581  // Reserve Trap Handler registers - support is not implemented in Codegen.
582  reserveRegisterTuples(Reserved, AMDGPU::TBA);
583  reserveRegisterTuples(Reserved, AMDGPU::TMA);
584  reserveRegisterTuples(Reserved, AMDGPU::TTMP0_TTMP1);
585  reserveRegisterTuples(Reserved, AMDGPU::TTMP2_TTMP3);
586  reserveRegisterTuples(Reserved, AMDGPU::TTMP4_TTMP5);
587  reserveRegisterTuples(Reserved, AMDGPU::TTMP6_TTMP7);
588  reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9);
589  reserveRegisterTuples(Reserved, AMDGPU::TTMP10_TTMP11);
590  reserveRegisterTuples(Reserved, AMDGPU::TTMP12_TTMP13);
591  reserveRegisterTuples(Reserved, AMDGPU::TTMP14_TTMP15);
592 
593  // Reserve null register - it shall never be allocated
594  reserveRegisterTuples(Reserved, AMDGPU::SGPR_NULL);
595 
596  // Disallow vcc_hi allocation in wave32. It may be allocated but most likely
597  // will result in bugs.
598  if (isWave32) {
599  Reserved.set(AMDGPU::VCC);
600  Reserved.set(AMDGPU::VCC_HI);
601  }
602 
603  // Reserve SGPRs.
604  //
605  unsigned MaxNumSGPRs = ST.getMaxNumSGPRs(MF);
606  unsigned TotalNumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
607  for (unsigned i = MaxNumSGPRs; i < TotalNumSGPRs; ++i) {
608  unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
609  reserveRegisterTuples(Reserved, Reg);
610  }
611 
612  for (auto Reg : AMDGPU::SReg_32RegClass) {
613  Reserved.set(getSubReg(Reg, AMDGPU::hi16));
614  Register Low = getSubReg(Reg, AMDGPU::lo16);
615  // This is to prevent BB vcc liveness errors.
616  if (!AMDGPU::SGPR_LO16RegClass.contains(Low))
617  Reserved.set(Low);
618  }
619 
620  Register ScratchRSrcReg = MFI->getScratchRSrcReg();
621  if (ScratchRSrcReg != AMDGPU::NoRegister) {
622  // Reserve 4 SGPRs for the scratch buffer resource descriptor in case we
623  // need to spill.
624  // TODO: May need to reserve a VGPR if doing LDS spilling.
625  reserveRegisterTuples(Reserved, ScratchRSrcReg);
626  }
627 
628  // We have to assume the SP is needed in case there are calls in the function,
629  // which is detected after the function is lowered. If we aren't really going
630  // to need SP, don't bother reserving it.
631  MCRegister StackPtrReg = MFI->getStackPtrOffsetReg();
632  if (StackPtrReg) {
633  reserveRegisterTuples(Reserved, StackPtrReg);
634  assert(!isSubRegister(ScratchRSrcReg, StackPtrReg));
635  }
636 
637  MCRegister FrameReg = MFI->getFrameOffsetReg();
638  if (FrameReg) {
639  reserveRegisterTuples(Reserved, FrameReg);
640  assert(!isSubRegister(ScratchRSrcReg, FrameReg));
641  }
642 
643  if (hasBasePointer(MF)) {
644  MCRegister BasePtrReg = getBaseRegister();
645  reserveRegisterTuples(Reserved, BasePtrReg);
646  assert(!isSubRegister(ScratchRSrcReg, BasePtrReg));
647  }
648 
649  // Reserve VGPRs/AGPRs.
650  //
651  unsigned MaxNumVGPRs = ST.getMaxNumVGPRs(MF);
652  unsigned MaxNumAGPRs = MaxNumVGPRs;
653  unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs();
654 
655  // Reserve all the AGPRs if there are no instructions to use it.
656  if (!ST.hasMAIInsts()) {
657  for (unsigned i = 0; i < MaxNumAGPRs; ++i) {
658  unsigned Reg = AMDGPU::AGPR_32RegClass.getRegister(i);
659  reserveRegisterTuples(Reserved, Reg);
660  }
661  }
662 
663  for (auto Reg : AMDGPU::AGPR_32RegClass) {
664  Reserved.set(getSubReg(Reg, AMDGPU::hi16));
665  }
666 
667  // On GFX90A, the number of VGPRs and AGPRs need not be equal. Theoretically,
668  // a wave may have up to 512 total vector registers combining together both
669  // VGPRs and AGPRs. Hence, in an entry function without calls and without
670  // AGPRs used within it, it is possible to use the whole vector register
671  // budget for VGPRs.
672  //
673  // TODO: it shall be possible to estimate maximum AGPR/VGPR pressure and split
674  // register file accordingly.
675  if (ST.hasGFX90AInsts()) {
676  if (MFI->usesAGPRs(MF)) {
677  MaxNumVGPRs /= 2;
678  MaxNumAGPRs = MaxNumVGPRs;
679  } else {
680  if (MaxNumVGPRs > TotalNumVGPRs) {
681  MaxNumAGPRs = MaxNumVGPRs - TotalNumVGPRs;
682  MaxNumVGPRs = TotalNumVGPRs;
683  } else
684  MaxNumAGPRs = 0;
685  }
686  }
687 
688  for (unsigned i = MaxNumVGPRs; i < TotalNumVGPRs; ++i) {
689  unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
690  reserveRegisterTuples(Reserved, Reg);
691  }
692 
693  for (unsigned i = MaxNumAGPRs; i < TotalNumVGPRs; ++i) {
694  unsigned Reg = AMDGPU::AGPR_32RegClass.getRegister(i);
695  reserveRegisterTuples(Reserved, Reg);
696  }
697 
698  // On GFX908, in order to guarantee copying between AGPRs, we need a scratch
699  // VGPR available at all times.
700  if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
701  reserveRegisterTuples(Reserved, MFI->getVGPRForAGPRCopy());
702  }
703 
704  for (Register Reg : MFI->WWMReservedRegs)
705  reserveRegisterTuples(Reserved, Reg);
706 
707  // FIXME: Stop using reserved registers for this.
708  for (MCPhysReg Reg : MFI->getAGPRSpillVGPRs())
709  reserveRegisterTuples(Reserved, Reg);
710 
711  for (MCPhysReg Reg : MFI->getVGPRSpillAGPRs())
712  reserveRegisterTuples(Reserved, Reg);
713 
714  for (auto SSpill : MFI->getSGPRSpillVGPRs())
715  reserveRegisterTuples(Reserved, SSpill.VGPR);
716 
717  return Reserved;
718 }
719 
721  MCRegister PhysReg) const {
722  return !MF.getRegInfo().isReserved(PhysReg);
723 }
724 
727  // On entry, the base address is 0, so it can't possibly need any more
728  // alignment.
729 
730  // FIXME: Should be able to specify the entry frame alignment per calling
731  // convention instead.
732  if (Info->isEntryFunction())
733  return false;
734 
736 }
737 
740  if (Info->isEntryFunction()) {
741  const MachineFrameInfo &MFI = Fn.getFrameInfo();
742  return MFI.hasStackObjects() || MFI.hasCalls();
743  }
744 
745  // May need scavenger for dealing with callee saved registers.
746  return true;
747 }
748 
750  const MachineFunction &MF) const {
751  // Do not use frame virtual registers. They used to be used for SGPRs, but
752  // once we reach PrologEpilogInserter, we can no longer spill SGPRs. If the
753  // scavenger fails, we can increment/decrement the necessary SGPRs to avoid a
754  // spill.
755  return false;
756 }
757 
759  const MachineFunction &MF) const {
760  const MachineFrameInfo &MFI = MF.getFrameInfo();
761  return MFI.hasStackObjects();
762 }
763 
765  const MachineFunction &) const {
766  // There are no special dedicated stack or frame pointers.
767  return true;
768 }
769 
772 
773  int OffIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
774  AMDGPU::OpName::offset);
775  return MI->getOperand(OffIdx).getImm();
776 }
777 
779  int Idx) const {
781  return 0;
782 
783  assert((Idx == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
784  AMDGPU::OpName::vaddr) ||
785  (Idx == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
786  AMDGPU::OpName::saddr))) &&
787  "Should never see frame index on non-address operand");
788 
789  return getScratchInstrOffset(MI);
790 }
791 
792 bool SIRegisterInfo::needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
794  return false;
795 
796  int64_t FullOffset = Offset + getScratchInstrOffset(MI);
797 
798  if (SIInstrInfo::isMUBUF(*MI))
799  return !SIInstrInfo::isLegalMUBUFImmOffset(FullOffset);
800 
801  const SIInstrInfo *TII = ST.getInstrInfo();
802  return !TII->isLegalFLATOffset(FullOffset, AMDGPUAS::PRIVATE_ADDRESS,
804 }
805 
807  int FrameIdx,
808  int64_t Offset) const {
810  DebugLoc DL; // Defaults to "unknown"
811 
812  if (Ins != MBB->end())
813  DL = Ins->getDebugLoc();
814 
815  MachineFunction *MF = MBB->getParent();
816  const SIInstrInfo *TII = ST.getInstrInfo();
818  unsigned MovOpc = ST.enableFlatScratch() ? AMDGPU::S_MOV_B32
819  : AMDGPU::V_MOV_B32_e32;
820 
822  ST.enableFlatScratch() ? &AMDGPU::SReg_32_XEXEC_HIRegClass
823  : &AMDGPU::VGPR_32RegClass);
824 
825  if (Offset == 0) {
826  BuildMI(*MBB, Ins, DL, TII->get(MovOpc), BaseReg)
827  .addFrameIndex(FrameIdx);
828  return BaseReg;
829  }
830 
831  Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
832 
834  ST.enableFlatScratch() ? &AMDGPU::SReg_32_XM0RegClass
835  : &AMDGPU::VGPR_32RegClass);
836 
837  BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
838  .addImm(Offset);
839  BuildMI(*MBB, Ins, DL, TII->get(MovOpc), FIReg)
840  .addFrameIndex(FrameIdx);
841 
842  if (ST.enableFlatScratch() ) {
843  BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_ADD_I32), BaseReg)
844  .addReg(OffsetReg, RegState::Kill)
845  .addReg(FIReg);
846  return BaseReg;
847  }
848 
849  TII->getAddNoCarry(*MBB, Ins, DL, BaseReg)
850  .addReg(OffsetReg, RegState::Kill)
851  .addReg(FIReg)
852  .addImm(0); // clamp bit
853 
854  return BaseReg;
855 }
856 
858  int64_t Offset) const {
859  const SIInstrInfo *TII = ST.getInstrInfo();
860  bool IsFlat = TII->isFLATScratch(MI);
861 
862 #ifndef NDEBUG
863  // FIXME: Is it possible to be storing a frame index to itself?
864  bool SeenFI = false;
865  for (const MachineOperand &MO: MI.operands()) {
866  if (MO.isFI()) {
867  if (SeenFI)
868  llvm_unreachable("should not see multiple frame indices");
869 
870  SeenFI = true;
871  }
872  }
873 #endif
874 
875  MachineOperand *FIOp =
876  TII->getNamedOperand(MI, IsFlat ? AMDGPU::OpName::saddr
877  : AMDGPU::OpName::vaddr);
878 
879  MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset);
880  int64_t NewOffset = OffsetOp->getImm() + Offset;
881 
882  assert(FIOp && FIOp->isFI() && "frame index must be address operand");
883  assert(TII->isMUBUF(MI) || TII->isFLATScratch(MI));
884 
885  if (IsFlat) {
886  assert(TII->isLegalFLATOffset(NewOffset, AMDGPUAS::PRIVATE_ADDRESS,
888  "offset should be legal");
889  FIOp->ChangeToRegister(BaseReg, false);
890  OffsetOp->setImm(NewOffset);
891  return;
892  }
893 
894 #ifndef NDEBUG
895  MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset);
896  assert(SOffset->isImm() && SOffset->getImm() == 0);
897 #endif
898 
900  "offset should be legal");
901 
902  FIOp->ChangeToRegister(BaseReg, false);
903  OffsetOp->setImm(NewOffset);
904 }
905 
907  Register BaseReg,
908  int64_t Offset) const {
910  return false;
911 
912  int64_t NewOffset = Offset + getScratchInstrOffset(MI);
913 
914  if (SIInstrInfo::isMUBUF(*MI))
915  return SIInstrInfo::isLegalMUBUFImmOffset(NewOffset);
916 
917  const SIInstrInfo *TII = ST.getInstrInfo();
918  return TII->isLegalFLATOffset(NewOffset, AMDGPUAS::PRIVATE_ADDRESS,
920 }
921 
923  const MachineFunction &MF, unsigned Kind) const {
924  // This is inaccurate. It depends on the instruction and address space. The
925  // only place where we should hit this is for dealing with frame indexes /
926  // private accesses, so this is correct in that case.
927  return &AMDGPU::VGPR_32RegClass;
928 }
929 
930 const TargetRegisterClass *
932  if (isAGPRClass(RC) && !ST.hasGFX90AInsts())
933  return getEquivalentVGPRClass(RC);
934 
935  return RC;
936 }
937 
938 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
939 
940  switch (Op) {
941  case AMDGPU::SI_SPILL_S1024_SAVE:
942  case AMDGPU::SI_SPILL_S1024_RESTORE:
943  case AMDGPU::SI_SPILL_V1024_SAVE:
944  case AMDGPU::SI_SPILL_V1024_RESTORE:
945  case AMDGPU::SI_SPILL_A1024_SAVE:
946  case AMDGPU::SI_SPILL_A1024_RESTORE:
947  case AMDGPU::SI_SPILL_AV1024_SAVE:
948  case AMDGPU::SI_SPILL_AV1024_RESTORE:
949  return 32;
950  case AMDGPU::SI_SPILL_S512_SAVE:
951  case AMDGPU::SI_SPILL_S512_RESTORE:
952  case AMDGPU::SI_SPILL_V512_SAVE:
953  case AMDGPU::SI_SPILL_V512_RESTORE:
954  case AMDGPU::SI_SPILL_A512_SAVE:
955  case AMDGPU::SI_SPILL_A512_RESTORE:
956  case AMDGPU::SI_SPILL_AV512_SAVE:
957  case AMDGPU::SI_SPILL_AV512_RESTORE:
958  return 16;
959  case AMDGPU::SI_SPILL_S256_SAVE:
960  case AMDGPU::SI_SPILL_S256_RESTORE:
961  case AMDGPU::SI_SPILL_V256_SAVE:
962  case AMDGPU::SI_SPILL_V256_RESTORE:
963  case AMDGPU::SI_SPILL_A256_SAVE:
964  case AMDGPU::SI_SPILL_A256_RESTORE:
965  case AMDGPU::SI_SPILL_AV256_SAVE:
966  case AMDGPU::SI_SPILL_AV256_RESTORE:
967  return 8;
968  case AMDGPU::SI_SPILL_S224_SAVE:
969  case AMDGPU::SI_SPILL_S224_RESTORE:
970  case AMDGPU::SI_SPILL_V224_SAVE:
971  case AMDGPU::SI_SPILL_V224_RESTORE:
972  case AMDGPU::SI_SPILL_A224_SAVE:
973  case AMDGPU::SI_SPILL_A224_RESTORE:
974  case AMDGPU::SI_SPILL_AV224_SAVE:
975  case AMDGPU::SI_SPILL_AV224_RESTORE:
976  return 7;
977  case AMDGPU::SI_SPILL_S192_SAVE:
978  case AMDGPU::SI_SPILL_S192_RESTORE:
979  case AMDGPU::SI_SPILL_V192_SAVE:
980  case AMDGPU::SI_SPILL_V192_RESTORE:
981  case AMDGPU::SI_SPILL_A192_SAVE:
982  case AMDGPU::SI_SPILL_A192_RESTORE:
983  case AMDGPU::SI_SPILL_AV192_SAVE:
984  case AMDGPU::SI_SPILL_AV192_RESTORE:
985  return 6;
986  case AMDGPU::SI_SPILL_S160_SAVE:
987  case AMDGPU::SI_SPILL_S160_RESTORE:
988  case AMDGPU::SI_SPILL_V160_SAVE:
989  case AMDGPU::SI_SPILL_V160_RESTORE:
990  case AMDGPU::SI_SPILL_A160_SAVE:
991  case AMDGPU::SI_SPILL_A160_RESTORE:
992  case AMDGPU::SI_SPILL_AV160_SAVE:
993  case AMDGPU::SI_SPILL_AV160_RESTORE:
994  return 5;
995  case AMDGPU::SI_SPILL_S128_SAVE:
996  case AMDGPU::SI_SPILL_S128_RESTORE:
997  case AMDGPU::SI_SPILL_V128_SAVE:
998  case AMDGPU::SI_SPILL_V128_RESTORE:
999  case AMDGPU::SI_SPILL_A128_SAVE:
1000  case AMDGPU::SI_SPILL_A128_RESTORE:
1001  case AMDGPU::SI_SPILL_AV128_SAVE:
1002  case AMDGPU::SI_SPILL_AV128_RESTORE:
1003  return 4;
1004  case AMDGPU::SI_SPILL_S96_SAVE:
1005  case AMDGPU::SI_SPILL_S96_RESTORE:
1006  case AMDGPU::SI_SPILL_V96_SAVE:
1007  case AMDGPU::SI_SPILL_V96_RESTORE:
1008  case AMDGPU::SI_SPILL_A96_SAVE:
1009  case AMDGPU::SI_SPILL_A96_RESTORE:
1010  case AMDGPU::SI_SPILL_AV96_SAVE:
1011  case AMDGPU::SI_SPILL_AV96_RESTORE:
1012  return 3;
1013  case AMDGPU::SI_SPILL_S64_SAVE:
1014  case AMDGPU::SI_SPILL_S64_RESTORE:
1015  case AMDGPU::SI_SPILL_V64_SAVE:
1016  case AMDGPU::SI_SPILL_V64_RESTORE:
1017  case AMDGPU::SI_SPILL_A64_SAVE:
1018  case AMDGPU::SI_SPILL_A64_RESTORE:
1019  case AMDGPU::SI_SPILL_AV64_SAVE:
1020  case AMDGPU::SI_SPILL_AV64_RESTORE:
1021  return 2;
1022  case AMDGPU::SI_SPILL_S32_SAVE:
1023  case AMDGPU::SI_SPILL_S32_RESTORE:
1024  case AMDGPU::SI_SPILL_V32_SAVE:
1025  case AMDGPU::SI_SPILL_V32_RESTORE:
1026  case AMDGPU::SI_SPILL_A32_SAVE:
1027  case AMDGPU::SI_SPILL_A32_RESTORE:
1028  case AMDGPU::SI_SPILL_AV32_SAVE:
1029  case AMDGPU::SI_SPILL_AV32_RESTORE:
1030  return 1;
1031  default: llvm_unreachable("Invalid spill opcode");
1032  }
1033 }
1034 
1035 static int getOffsetMUBUFStore(unsigned Opc) {
1036  switch (Opc) {
1037  case AMDGPU::BUFFER_STORE_DWORD_OFFEN:
1038  return AMDGPU::BUFFER_STORE_DWORD_OFFSET;
1039  case AMDGPU::BUFFER_STORE_BYTE_OFFEN:
1040  return AMDGPU::BUFFER_STORE_BYTE_OFFSET;
1041  case AMDGPU::BUFFER_STORE_SHORT_OFFEN:
1042  return AMDGPU::BUFFER_STORE_SHORT_OFFSET;
1043  case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN:
1044  return AMDGPU::BUFFER_STORE_DWORDX2_OFFSET;
1045  case AMDGPU::BUFFER_STORE_DWORDX3_OFFEN:
1046  return AMDGPU::BUFFER_STORE_DWORDX3_OFFSET;
1047  case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN:
1048  return AMDGPU::BUFFER_STORE_DWORDX4_OFFSET;
1049  case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN:
1050  return AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET;
1051  case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN:
1052  return AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET;
1053  default:
1054  return -1;
1055  }
1056 }
1057 
1058 static int getOffsetMUBUFLoad(unsigned Opc) {
1059  switch (Opc) {
1060  case AMDGPU::BUFFER_LOAD_DWORD_OFFEN:
1061  return AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
1062  case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN:
1063  return AMDGPU::BUFFER_LOAD_UBYTE_OFFSET;
1064  case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN:
1065  return AMDGPU::BUFFER_LOAD_SBYTE_OFFSET;
1066  case AMDGPU::BUFFER_LOAD_USHORT_OFFEN:
1067  return AMDGPU::BUFFER_LOAD_USHORT_OFFSET;
1068  case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN:
1069  return AMDGPU::BUFFER_LOAD_SSHORT_OFFSET;
1070  case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN:
1071  return AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET;
1072  case AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN:
1073  return AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET;
1074  case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN:
1075  return AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET;
1076  case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN:
1077  return AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET;
1078  case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN:
1079  return AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET;
1080  case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN:
1081  return AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET;
1082  case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN:
1083  return AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET;
1084  case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN:
1085  return AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET;
1086  case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN:
1087  return AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET;
1088  default:
1089  return -1;
1090  }
1091 }
1092 
1093 static int getOffenMUBUFStore(unsigned Opc) {
1094  switch (Opc) {
1095  case AMDGPU::BUFFER_STORE_DWORD_OFFSET:
1096  return AMDGPU::BUFFER_STORE_DWORD_OFFEN;
1097  case AMDGPU::BUFFER_STORE_BYTE_OFFSET:
1098  return AMDGPU::BUFFER_STORE_BYTE_OFFEN;
1099  case AMDGPU::BUFFER_STORE_SHORT_OFFSET:
1100  return AMDGPU::BUFFER_STORE_SHORT_OFFEN;
1101  case AMDGPU::BUFFER_STORE_DWORDX2_OFFSET:
1102  return AMDGPU::BUFFER_STORE_DWORDX2_OFFEN;
1103  case AMDGPU::BUFFER_STORE_DWORDX3_OFFSET:
1104  return AMDGPU::BUFFER_STORE_DWORDX3_OFFEN;
1105  case AMDGPU::BUFFER_STORE_DWORDX4_OFFSET:
1106  return AMDGPU::BUFFER_STORE_DWORDX4_OFFEN;
1107  case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET:
1108  return AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN;
1109  case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET:
1110  return AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN;
1111  default:
1112  return -1;
1113  }
1114 }
1115 
1116 static int getOffenMUBUFLoad(unsigned Opc) {
1117  switch (Opc) {
1118  case AMDGPU::BUFFER_LOAD_DWORD_OFFSET:
1119  return AMDGPU::BUFFER_LOAD_DWORD_OFFEN;
1120  case AMDGPU::BUFFER_LOAD_UBYTE_OFFSET:
1121  return AMDGPU::BUFFER_LOAD_UBYTE_OFFEN;
1122  case AMDGPU::BUFFER_LOAD_SBYTE_OFFSET:
1123  return AMDGPU::BUFFER_LOAD_SBYTE_OFFEN;
1124  case AMDGPU::BUFFER_LOAD_USHORT_OFFSET:
1125  return AMDGPU::BUFFER_LOAD_USHORT_OFFEN;
1126  case AMDGPU::BUFFER_LOAD_SSHORT_OFFSET:
1127  return AMDGPU::BUFFER_LOAD_SSHORT_OFFEN;
1128  case AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET:
1129  return AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN;
1130  case AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET:
1131  return AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN;
1132  case AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET:
1133  return AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN;
1134  case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET:
1135  return AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN;
1136  case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET:
1137  return AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN;
1138  case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET:
1139  return AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN;
1140  case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET:
1141  return AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN;
1142  case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET:
1143  return AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN;
1144  case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET:
1145  return AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN;
1146  default:
1147  return -1;
1148  }
1149 }
1150 
1154  int Index, unsigned Lane,
1155  unsigned ValueReg, bool IsKill) {
1156  MachineFunction *MF = MBB.getParent();
1158  const SIInstrInfo *TII = ST.getInstrInfo();
1159 
1160  MCPhysReg Reg = MFI->getVGPRToAGPRSpill(Index, Lane);
1161 
1162  if (Reg == AMDGPU::NoRegister)
1163  return MachineInstrBuilder();
1164 
1165  bool IsStore = MI->mayStore();
1167  auto *TRI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
1168 
1169  unsigned Dst = IsStore ? Reg : ValueReg;
1170  unsigned Src = IsStore ? ValueReg : Reg;
1171  bool IsVGPR = TRI->isVGPR(MRI, Reg);
1172  DebugLoc DL = MI->getDebugLoc();
1173  if (IsVGPR == TRI->isVGPR(MRI, ValueReg)) {
1174  // Spiller during regalloc may restore a spilled register to its superclass.
1175  // It could result in AGPR spills restored to VGPRs or the other way around,
1176  // making the src and dst with identical regclasses at this point. It just
1177  // needs a copy in such cases.
1178  auto CopyMIB = BuildMI(MBB, MI, DL, TII->get(AMDGPU::COPY), Dst)
1179  .addReg(Src, getKillRegState(IsKill));
1181  return CopyMIB;
1182  }
1183  unsigned Opc = (IsStore ^ IsVGPR) ? AMDGPU::V_ACCVGPR_WRITE_B32_e64
1184  : AMDGPU::V_ACCVGPR_READ_B32_e64;
1185 
1186  auto MIB = BuildMI(MBB, MI, DL, TII->get(Opc), Dst)
1187  .addReg(Src, getKillRegState(IsKill));
1189  return MIB;
1190 }
1191 
1192 // This differs from buildSpillLoadStore by only scavenging a VGPR. It does not
1193 // need to handle the case where an SGPR may need to be spilled while spilling.
1195  MachineFrameInfo &MFI,
1197  int Index,
1198  int64_t Offset) {
1199  const SIInstrInfo *TII = ST.getInstrInfo();
1200  MachineBasicBlock *MBB = MI->getParent();
1201  const DebugLoc &DL = MI->getDebugLoc();
1202  bool IsStore = MI->mayStore();
1203 
1204  unsigned Opc = MI->getOpcode();
1205  int LoadStoreOp = IsStore ?
1207  if (LoadStoreOp == -1)
1208  return false;
1209 
1210  const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata);
1211  if (spillVGPRtoAGPR(ST, *MBB, MI, Index, 0, Reg->getReg(), false).getInstr())
1212  return true;
1213 
1214  MachineInstrBuilder NewMI =
1215  BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
1216  .add(*Reg)
1217  .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc))
1218  .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset))
1219  .addImm(Offset)
1220  .addImm(0) // cpol
1221  .addImm(0) // tfe
1222  .addImm(0) // swz
1223  .cloneMemRefs(*MI);
1224 
1225  const MachineOperand *VDataIn = TII->getNamedOperand(*MI,
1226  AMDGPU::OpName::vdata_in);
1227  if (VDataIn)
1228  NewMI.add(*VDataIn);
1229  return true;
1230 }
1231 
1233  unsigned LoadStoreOp,
1234  unsigned EltSize) {
1235  bool IsStore = TII->get(LoadStoreOp).mayStore();
1236  bool HasVAddr = AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::vaddr) != -1;
1237  bool UseST =
1238  !HasVAddr &&
1239  AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::saddr) < 0;
1240 
1241  switch (EltSize) {
1242  case 4:
1243  LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
1244  : AMDGPU::SCRATCH_LOAD_DWORD_SADDR;
1245  break;
1246  case 8:
1247  LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX2_SADDR
1248  : AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR;
1249  break;
1250  case 12:
1251  LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX3_SADDR
1252  : AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR;
1253  break;
1254  case 16:
1255  LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX4_SADDR
1256  : AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR;
1257  break;
1258  default:
1259  llvm_unreachable("Unexpected spill load/store size!");
1260  }
1261 
1262  if (HasVAddr)
1263  LoadStoreOp = AMDGPU::getFlatScratchInstSVfromSS(LoadStoreOp);
1264  else if (UseST)
1265  LoadStoreOp = AMDGPU::getFlatScratchInstSTfromSS(LoadStoreOp);
1266 
1267  return LoadStoreOp;
1268 }
1269 
1272  unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill,
1273  MCRegister ScratchOffsetReg, int64_t InstOffset, MachineMemOperand *MMO,
1274  RegScavenger *RS, LivePhysRegs *LiveRegs) const {
1275  assert((!RS || !LiveRegs) && "Only RS or LiveRegs can be set but not both");
1276 
1277  MachineFunction *MF = MBB.getParent();
1278  const SIInstrInfo *TII = ST.getInstrInfo();
1279  const MachineFrameInfo &MFI = MF->getFrameInfo();
1280  const SIMachineFunctionInfo *FuncInfo = MF->getInfo<SIMachineFunctionInfo>();
1281 
1282  const MCInstrDesc *Desc = &TII->get(LoadStoreOp);
1283  bool IsStore = Desc->mayStore();
1284  bool IsFlat = TII->isFLATScratch(LoadStoreOp);
1285 
1286  bool CanClobberSCC = false;
1287  bool Scavenged = false;
1288  MCRegister SOffset = ScratchOffsetReg;
1289 
1290  const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg);
1291  // On gfx90a+ AGPR is a regular VGPR acceptable for loads and stores.
1292  const bool IsAGPR = !ST.hasGFX90AInsts() && isAGPRClass(RC);
1293  const unsigned RegWidth = AMDGPU::getRegBitWidth(RC->getID()) / 8;
1294 
1295  // Always use 4 byte operations for AGPRs because we need to scavenge
1296  // a temporary VGPR.
1297  unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u;
1298  unsigned NumSubRegs = RegWidth / EltSize;
1299  unsigned Size = NumSubRegs * EltSize;
1300  unsigned RemSize = RegWidth - Size;
1301  unsigned NumRemSubRegs = RemSize ? 1 : 0;
1302  int64_t Offset = InstOffset + MFI.getObjectOffset(Index);
1303  int64_t MaterializedOffset = Offset;
1304 
1305  int64_t MaxOffset = Offset + Size + RemSize - EltSize;
1306  int64_t ScratchOffsetRegDelta = 0;
1307 
1308  if (IsFlat && EltSize > 4) {
1309  LoadStoreOp = getFlatScratchSpillOpcode(TII, LoadStoreOp, EltSize);
1310  Desc = &TII->get(LoadStoreOp);
1311  }
1312 
1313  Align Alignment = MFI.getObjectAlign(Index);
1314  const MachinePointerInfo &BasePtrInfo = MMO->getPointerInfo();
1315 
1316  assert((IsFlat || ((Offset % EltSize) == 0)) &&
1317  "unexpected VGPR spill offset");
1318 
1319  // Track a VGPR to use for a constant offset we need to materialize.
1320  Register TmpOffsetVGPR;
1321 
1322  // Track a VGPR to use as an intermediate value.
1323  Register TmpIntermediateVGPR;
1324  bool UseVGPROffset = false;
1325 
1326  // Materialize a VGPR offset required for the given SGPR/VGPR/Immediate
1327  // combination.
1328  auto MaterializeVOffset = [&](Register SGPRBase, Register TmpVGPR,
1329  int64_t VOffset) {
1330  // We are using a VGPR offset
1331  if (IsFlat && SGPRBase) {
1332  // We only have 1 VGPR offset, or 1 SGPR offset. We don't have a free
1333  // SGPR, so perform the add as vector.
1334  // We don't need a base SGPR in the kernel.
1335 
1336  if (ST.getConstantBusLimit(AMDGPU::V_ADD_U32_e64) >= 2) {
1337  BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_ADD_U32_e64), TmpVGPR)
1338  .addReg(SGPRBase)
1339  .addImm(VOffset)
1340  .addImm(0); // clamp
1341  } else {
1342  BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR)
1343  .addReg(SGPRBase);
1344  BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_ADD_U32_e32), TmpVGPR)
1345  .addImm(VOffset)
1346  .addReg(TmpOffsetVGPR);
1347  }
1348  } else {
1349  assert(TmpOffsetVGPR);
1350  BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR)
1351  .addImm(VOffset);
1352  }
1353  };
1354 
1355  bool IsOffsetLegal =
1356  IsFlat ? TII->isLegalFLATOffset(MaxOffset, AMDGPUAS::PRIVATE_ADDRESS,
1359  if (!IsOffsetLegal || (IsFlat && !SOffset && !ST.hasFlatScratchSTMode())) {
1360  SOffset = MCRegister();
1361 
1362  // We don't have access to the register scavenger if this function is called
1363  // during PEI::scavengeFrameVirtualRegs() so use LiveRegs in this case.
1364  // TODO: Clobbering SCC is not necessary for scratch instructions in the
1365  // entry.
1366  if (RS) {
1367  SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0, false);
1368 
1369  // Piggy back on the liveness scan we just did see if SCC is dead.
1370  CanClobberSCC = !RS->isRegUsed(AMDGPU::SCC);
1371  } else if (LiveRegs) {
1372  CanClobberSCC = !LiveRegs->contains(AMDGPU::SCC);
1373  for (MCRegister Reg : AMDGPU::SGPR_32RegClass) {
1374  if (LiveRegs->available(MF->getRegInfo(), Reg)) {
1375  SOffset = Reg;
1376  break;
1377  }
1378  }
1379  }
1380 
1381  if (ScratchOffsetReg != AMDGPU::NoRegister && !CanClobberSCC)
1382  SOffset = Register();
1383 
1384  if (!SOffset) {
1385  UseVGPROffset = true;
1386 
1387  if (RS) {
1388  TmpOffsetVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
1389  } else {
1390  assert(LiveRegs);
1391  for (MCRegister Reg : AMDGPU::VGPR_32RegClass) {
1392  if (LiveRegs->available(MF->getRegInfo(), Reg)) {
1393  TmpOffsetVGPR = Reg;
1394  break;
1395  }
1396  }
1397  }
1398 
1399  assert(TmpOffsetVGPR);
1400  } else if (!SOffset && CanClobberSCC) {
1401  // There are no free SGPRs, and since we are in the process of spilling
1402  // VGPRs too. Since we need a VGPR in order to spill SGPRs (this is true
1403  // on SI/CI and on VI it is true until we implement spilling using scalar
1404  // stores), we have no way to free up an SGPR. Our solution here is to
1405  // add the offset directly to the ScratchOffset or StackPtrOffset
1406  // register, and then subtract the offset after the spill to return the
1407  // register to it's original value.
1408 
1409  // TODO: If we don't have to do an emergency stack slot spill, converting
1410  // to use the VGPR offset is fewer instructions.
1411  if (!ScratchOffsetReg)
1412  ScratchOffsetReg = FuncInfo->getStackPtrOffsetReg();
1413  SOffset = ScratchOffsetReg;
1414  ScratchOffsetRegDelta = Offset;
1415  } else {
1416  Scavenged = true;
1417  }
1418 
1419  // We currently only support spilling VGPRs to EltSize boundaries, meaning
1420  // we can simplify the adjustment of Offset here to just scale with
1421  // WavefrontSize.
1422  if (!IsFlat && !UseVGPROffset)
1423  Offset *= ST.getWavefrontSize();
1424 
1425  if (!UseVGPROffset && !SOffset)
1426  report_fatal_error("could not scavenge SGPR to spill in entry function");
1427 
1428  if (UseVGPROffset) {
1429  // We are using a VGPR offset
1430  MaterializeVOffset(ScratchOffsetReg, TmpOffsetVGPR, Offset);
1431  } else if (ScratchOffsetReg == AMDGPU::NoRegister) {
1432  BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), SOffset).addImm(Offset);
1433  } else {
1434  assert(Offset != 0);
1435  auto Add = BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), SOffset)
1436  .addReg(ScratchOffsetReg)
1437  .addImm(Offset);
1438  Add->getOperand(3).setIsDead(); // Mark SCC as dead.
1439  }
1440 
1441  Offset = 0;
1442  }
1443 
1444  if (IsFlat && SOffset == AMDGPU::NoRegister) {
1445  assert(AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::vaddr) < 0
1446  && "Unexpected vaddr for flat scratch with a FI operand");
1447 
1448  if (UseVGPROffset) {
1449  LoadStoreOp = AMDGPU::getFlatScratchInstSVfromSS(LoadStoreOp);
1450  } else {
1452  LoadStoreOp = AMDGPU::getFlatScratchInstSTfromSS(LoadStoreOp);
1453  }
1454 
1455  Desc = &TII->get(LoadStoreOp);
1456  }
1457 
1458  for (unsigned i = 0, e = NumSubRegs + NumRemSubRegs, RegOffset = 0; i != e;
1459  ++i, RegOffset += EltSize) {
1460  if (i == NumSubRegs) {
1461  EltSize = RemSize;
1462  LoadStoreOp = getFlatScratchSpillOpcode(TII, LoadStoreOp, EltSize);
1463  }
1464  Desc = &TII->get(LoadStoreOp);
1465 
1466  if (!IsFlat && UseVGPROffset) {
1467  int NewLoadStoreOp = IsStore ? getOffenMUBUFStore(LoadStoreOp)
1468  : getOffenMUBUFLoad(LoadStoreOp);
1469  Desc = &TII->get(NewLoadStoreOp);
1470  }
1471 
1472  if (UseVGPROffset && TmpOffsetVGPR == TmpIntermediateVGPR) {
1473  // If we are spilling an AGPR beyond the range of the memory instruction
1474  // offset and need to use a VGPR offset, we ideally have at least 2
1475  // scratch VGPRs. If we don't have a second free VGPR without spilling,
1476  // recycle the VGPR used for the offset which requires resetting after
1477  // each subregister.
1478 
1479  MaterializeVOffset(ScratchOffsetReg, TmpOffsetVGPR, MaterializedOffset);
1480  }
1481 
1482  unsigned NumRegs = EltSize / 4;
1483  Register SubReg = e == 1
1484  ? ValueReg
1485  : Register(getSubReg(ValueReg,
1486  getSubRegFromChannel(RegOffset / 4, NumRegs)));
1487 
1488  unsigned SOffsetRegState = 0;
1489  unsigned SrcDstRegState = getDefRegState(!IsStore);
1490  const bool IsLastSubReg = i + 1 == e;
1491  if (IsLastSubReg) {
1492  SOffsetRegState |= getKillRegState(Scavenged);
1493  // The last implicit use carries the "Kill" flag.
1494  SrcDstRegState |= getKillRegState(IsKill);
1495  }
1496 
1497  // Make sure the whole register is defined if there are undef components by
1498  // adding an implicit def of the super-reg on the first instruction.
1499  bool NeedSuperRegDef = e > 1 && IsStore && i == 0;
1500  bool NeedSuperRegImpOperand = e > 1;
1501 
1502  // Remaining element size to spill into memory after some parts of it
1503  // spilled into either AGPRs or VGPRs.
1504  unsigned RemEltSize = EltSize;
1505 
1506  // AGPRs to spill VGPRs and vice versa are allocated in a reverse order,
1507  // starting from the last lane. In case if a register cannot be completely
1508  // spilled into another register that will ensure its alignment does not
1509  // change. For targets with VGPR alignment requirement this is important
1510  // in case of flat scratch usage as we might get a scratch_load or
1511  // scratch_store of an unaligned register otherwise.
1512  for (int LaneS = (RegOffset + EltSize) / 4 - 1, Lane = LaneS,
1513  LaneE = RegOffset / 4;
1514  Lane >= LaneE; --Lane) {
1515  bool IsSubReg = e > 1 || EltSize > 4;
1516  Register Sub = IsSubReg
1517  ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane)))
1518  : ValueReg;
1519  auto MIB = spillVGPRtoAGPR(ST, MBB, MI, Index, Lane, Sub, IsKill);
1520  if (!MIB.getInstr())
1521  break;
1522  if (NeedSuperRegDef || (IsSubReg && IsStore && Lane == LaneS && !i)) {
1523  MIB.addReg(ValueReg, RegState::ImplicitDefine);
1524  NeedSuperRegDef = false;
1525  }
1526  if (IsSubReg || NeedSuperRegImpOperand) {
1527  NeedSuperRegImpOperand = true;
1528  unsigned State = SrcDstRegState;
1529  if (Lane != LaneE)
1530  State &= ~RegState::Kill;
1531  MIB.addReg(ValueReg, RegState::Implicit | State);
1532  }
1533  RemEltSize -= 4;
1534  }
1535 
1536  if (!RemEltSize) // Fully spilled into AGPRs.
1537  continue;
1538 
1539  if (RemEltSize != EltSize) { // Partially spilled to AGPRs
1540  assert(IsFlat && EltSize > 4);
1541 
1542  unsigned NumRegs = RemEltSize / 4;
1543  SubReg = Register(getSubReg(ValueReg,
1544  getSubRegFromChannel(RegOffset / 4, NumRegs)));
1545  unsigned Opc = getFlatScratchSpillOpcode(TII, LoadStoreOp, RemEltSize);
1546  Desc = &TII->get(Opc);
1547  }
1548 
1549  unsigned FinalReg = SubReg;
1550 
1551  if (IsAGPR) {
1552  assert(EltSize == 4);
1553 
1554  if (!TmpIntermediateVGPR) {
1555  TmpIntermediateVGPR = FuncInfo->getVGPRForAGPRCopy();
1556  assert(MF->getRegInfo().isReserved(TmpIntermediateVGPR));
1557  }
1558  if (IsStore) {
1559  auto AccRead = BuildMI(MBB, MI, DL,
1560  TII->get(AMDGPU::V_ACCVGPR_READ_B32_e64),
1561  TmpIntermediateVGPR)
1562  .addReg(SubReg, getKillRegState(IsKill));
1563  if (NeedSuperRegDef)
1564  AccRead.addReg(ValueReg, RegState::ImplicitDefine);
1566  }
1567  SubReg = TmpIntermediateVGPR;
1568  } else if (UseVGPROffset) {
1569  // FIXME: change to scavengeRegisterBackwards()
1570  if (!TmpOffsetVGPR) {
1571  TmpOffsetVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
1572  RS->setRegUsed(TmpOffsetVGPR);
1573  }
1574  }
1575 
1576  MachinePointerInfo PInfo = BasePtrInfo.getWithOffset(RegOffset);
1577  MachineMemOperand *NewMMO =
1578  MF->getMachineMemOperand(PInfo, MMO->getFlags(), RemEltSize,
1579  commonAlignment(Alignment, RegOffset));
1580 
1581  auto MIB =
1582  BuildMI(MBB, MI, DL, *Desc)
1583  .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill));
1584 
1585  if (UseVGPROffset) {
1586  // For an AGPR spill, we reuse the same temp VGPR for the offset and the
1587  // intermediate accvgpr_write.
1588  MIB.addReg(TmpOffsetVGPR, getKillRegState(IsLastSubReg && !IsAGPR));
1589  }
1590 
1591  if (!IsFlat)
1592  MIB.addReg(FuncInfo->getScratchRSrcReg());
1593 
1594  if (SOffset == AMDGPU::NoRegister) {
1595  if (!IsFlat) {
1596  if (UseVGPROffset && ScratchOffsetReg) {
1597  assert(!FuncInfo->isEntryFunction());
1598  MIB.addReg(ScratchOffsetReg);
1599  } else {
1600  assert(FuncInfo->isEntryFunction());
1601  MIB.addImm(0);
1602  }
1603  }
1604  } else {
1605  MIB.addReg(SOffset, SOffsetRegState);
1606  }
1607  MIB.addImm(Offset + RegOffset)
1608  .addImm(0); // cpol
1609  if (!IsFlat)
1610  MIB.addImm(0) // tfe
1611  .addImm(0); // swz
1612  MIB.addMemOperand(NewMMO);
1613 
1614  if (!IsAGPR && NeedSuperRegDef)
1615  MIB.addReg(ValueReg, RegState::ImplicitDefine);
1616 
1617  if (!IsStore && IsAGPR && TmpIntermediateVGPR != AMDGPU::NoRegister) {
1618  MIB = BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64),
1619  FinalReg)
1620  .addReg(TmpIntermediateVGPR, RegState::Kill);
1622  }
1623 
1624  if (NeedSuperRegImpOperand)
1625  MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState);
1626  }
1627 
1628  if (ScratchOffsetRegDelta != 0) {
1629  // Subtract the offset we added to the ScratchOffset register.
1630  BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), SOffset)
1631  .addReg(SOffset)
1632  .addImm(-ScratchOffsetRegDelta);
1633  }
1634 }
1635 
1637  int Offset, bool IsLoad,
1638  bool IsKill) const {
1639  // Load/store VGPR
1640  MachineFrameInfo &FrameInfo = SB.MF.getFrameInfo();
1641  assert(FrameInfo.getStackID(Index) != TargetStackID::SGPRSpill);
1642 
1643  Register FrameReg =
1644  FrameInfo.isFixedObjectIndex(Index) && hasBasePointer(SB.MF)
1645  ? getBaseRegister()
1646  : getFrameRegister(SB.MF);
1647 
1648  Align Alignment = FrameInfo.getObjectAlign(Index);
1652  SB.EltSize, Alignment);
1653 
1654  if (IsLoad) {
1655  unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR
1656  : AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
1657  buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, false,
1658  FrameReg, Offset * SB.EltSize, MMO, SB.RS);
1659  } else {
1660  unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
1661  : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
1662  buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, IsKill,
1663  FrameReg, Offset * SB.EltSize, MMO, SB.RS);
1664  // This only ever adds one VGPR spill
1665  SB.MFI.addToSpilledVGPRs(1);
1666  }
1667 }
1668 
1670  int Index,
1671  RegScavenger *RS,
1672  LiveIntervals *LIS,
1673  bool OnlyToVGPR) const {
1674  SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS);
1675 
1677  SB.MFI.getSGPRToVGPRSpills(Index);
1678  bool SpillToVGPR = !VGPRSpills.empty();
1679  if (OnlyToVGPR && !SpillToVGPR)
1680  return false;
1681 
1682  assert(SpillToVGPR || (SB.SuperReg != SB.MFI.getStackPtrOffsetReg() &&
1683  SB.SuperReg != SB.MFI.getFrameOffsetReg()));
1684 
1685  if (SpillToVGPR) {
1686 
1687  assert(SB.NumSubRegs == VGPRSpills.size() &&
1688  "Num of VGPR lanes should be equal to num of SGPRs spilled");
1689 
1690  for (unsigned i = 0, e = SB.NumSubRegs; i < e; ++i) {
1691  Register SubReg =
1692  SB.NumSubRegs == 1
1693  ? SB.SuperReg
1694  : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
1695  SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i];
1696 
1697  bool UseKill = SB.IsKill && i == SB.NumSubRegs - 1;
1698 
1699  // Mark the "old value of vgpr" input undef only if this is the first sgpr
1700  // spill to this specific vgpr in the first basic block.
1701  auto MIB = BuildMI(*SB.MBB, MI, SB.DL,
1702  SB.TII.get(AMDGPU::V_WRITELANE_B32), Spill.VGPR)
1703  .addReg(SubReg, getKillRegState(UseKill))
1704  .addImm(Spill.Lane)
1705  .addReg(Spill.VGPR);
1706  if (LIS) {
1707  if (i == 0)
1708  LIS->ReplaceMachineInstrInMaps(*MI, *MIB);
1709  else
1710  LIS->InsertMachineInstrInMaps(*MIB);
1711  }
1712 
1713  if (i == 0 && SB.NumSubRegs > 1) {
1714  // We may be spilling a super-register which is only partially defined,
1715  // and need to ensure later spills think the value is defined.
1716  MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);
1717  }
1718 
1719  if (SB.NumSubRegs > 1)
1720  MIB.addReg(SB.SuperReg, getKillRegState(UseKill) | RegState::Implicit);
1721 
1722  // FIXME: Since this spills to another register instead of an actual
1723  // frame index, we should delete the frame index when all references to
1724  // it are fixed.
1725  }
1726  } else {
1727  SB.prepare();
1728 
1729  // SubReg carries the "Kill" flag when SubReg == SB.SuperReg.
1730  unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill);
1731 
1732  // Per VGPR helper data
1733  auto PVD = SB.getPerVGPRData();
1734 
1735  for (unsigned Offset = 0; Offset < PVD.NumVGPRs; ++Offset) {
1736  unsigned TmpVGPRFlags = RegState::Undef;
1737 
1738  // Write sub registers into the VGPR
1739  for (unsigned i = Offset * PVD.PerVGPR,
1740  e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs);
1741  i < e; ++i) {
1742  Register SubReg =
1743  SB.NumSubRegs == 1
1744  ? SB.SuperReg
1745  : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
1746 
1747  MachineInstrBuilder WriteLane =
1748  BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_WRITELANE_B32),
1749  SB.TmpVGPR)
1750  .addReg(SubReg, SubKillState)
1751  .addImm(i % PVD.PerVGPR)
1752  .addReg(SB.TmpVGPR, TmpVGPRFlags);
1753  TmpVGPRFlags = 0;
1754 
1755  if (LIS) {
1756  if (i == 0)
1757  LIS->ReplaceMachineInstrInMaps(*MI, *WriteLane);
1758  else
1759  LIS->InsertMachineInstrInMaps(*WriteLane);
1760  }
1761 
1762  // There could be undef components of a spilled super register.
1763  // TODO: Can we detect this and skip the spill?
1764  if (SB.NumSubRegs > 1) {
1765  // The last implicit use of the SB.SuperReg carries the "Kill" flag.
1766  unsigned SuperKillState = 0;
1767  if (i + 1 == SB.NumSubRegs)
1768  SuperKillState |= getKillRegState(SB.IsKill);
1769  WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState);
1770  }
1771  }
1772 
1773  // Write out VGPR
1774  SB.readWriteTmpVGPR(Offset, /*IsLoad*/ false);
1775  }
1776 
1777  SB.restore();
1778  }
1779 
1780  MI->eraseFromParent();
1782 
1783  if (LIS)
1785 
1786  return true;
1787 }
1788 
1790  int Index,
1791  RegScavenger *RS,
1792  LiveIntervals *LIS,
1793  bool OnlyToVGPR) const {
1794  SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS);
1795 
1797  SB.MFI.getSGPRToVGPRSpills(Index);
1798  bool SpillToVGPR = !VGPRSpills.empty();
1799  if (OnlyToVGPR && !SpillToVGPR)
1800  return false;
1801 
1802  if (SpillToVGPR) {
1803  for (unsigned i = 0, e = SB.NumSubRegs; i < e; ++i) {
1804  Register SubReg =
1805  SB.NumSubRegs == 1
1806  ? SB.SuperReg
1807  : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
1808 
1809  SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i];
1810  auto MIB = BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_READLANE_B32),
1811  SubReg)
1812  .addReg(Spill.VGPR)
1813  .addImm(Spill.Lane);
1814  if (SB.NumSubRegs > 1 && i == 0)
1816  if (LIS) {
1817  if (i == e - 1)
1818  LIS->ReplaceMachineInstrInMaps(*MI, *MIB);
1819  else
1820  LIS->InsertMachineInstrInMaps(*MIB);
1821  }
1822 
1823  }
1824  } else {
1825  SB.prepare();
1826 
1827  // Per VGPR helper data
1828  auto PVD = SB.getPerVGPRData();
1829 
1830  for (unsigned Offset = 0; Offset < PVD.NumVGPRs; ++Offset) {
1831  // Load in VGPR data
1832  SB.readWriteTmpVGPR(Offset, /*IsLoad*/ true);
1833 
1834  // Unpack lanes
1835  for (unsigned i = Offset * PVD.PerVGPR,
1836  e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs);
1837  i < e; ++i) {
1838  Register SubReg =
1839  SB.NumSubRegs == 1
1840  ? SB.SuperReg
1841  : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
1842 
1843  bool LastSubReg = (i + 1 == e);
1844  auto MIB = BuildMI(*SB.MBB, MI, SB.DL,
1845  SB.TII.get(AMDGPU::V_READLANE_B32), SubReg)
1846  .addReg(SB.TmpVGPR, getKillRegState(LastSubReg))
1847  .addImm(i);
1848  if (SB.NumSubRegs > 1 && i == 0)
1850  if (LIS) {
1851  if (i == e - 1)
1852  LIS->ReplaceMachineInstrInMaps(*MI, *MIB);
1853  else
1854  LIS->InsertMachineInstrInMaps(*MIB);
1855  }
1856  }
1857  }
1858 
1859  SB.restore();
1860  }
1861 
1862  MI->eraseFromParent();
1863 
1864  if (LIS)
1866 
1867  return true;
1868 }
1869 
1871  MachineBasicBlock &RestoreMBB,
1872  Register SGPR, RegScavenger *RS) const {
1873  SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, SGPR, false, 0,
1874  RS);
1875  SB.prepare();
1876  // Generate the spill of SGPR to SB.TmpVGPR.
1877  unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill);
1878  auto PVD = SB.getPerVGPRData();
1879  for (unsigned Offset = 0; Offset < PVD.NumVGPRs; ++Offset) {
1880  unsigned TmpVGPRFlags = RegState::Undef;
1881  // Write sub registers into the VGPR
1882  for (unsigned i = Offset * PVD.PerVGPR,
1883  e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs);
1884  i < e; ++i) {
1885  Register SubReg =
1886  SB.NumSubRegs == 1
1887  ? SB.SuperReg
1888  : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
1889 
1890  MachineInstrBuilder WriteLane =
1891  BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_WRITELANE_B32),
1892  SB.TmpVGPR)
1893  .addReg(SubReg, SubKillState)
1894  .addImm(i % PVD.PerVGPR)
1895  .addReg(SB.TmpVGPR, TmpVGPRFlags);
1896  TmpVGPRFlags = 0;
1897  // There could be undef components of a spilled super register.
1898  // TODO: Can we detect this and skip the spill?
1899  if (SB.NumSubRegs > 1) {
1900  // The last implicit use of the SB.SuperReg carries the "Kill" flag.
1901  unsigned SuperKillState = 0;
1902  if (i + 1 == SB.NumSubRegs)
1903  SuperKillState |= getKillRegState(SB.IsKill);
1904  WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState);
1905  }
1906  }
1907  // Don't need to write VGPR out.
1908  }
1909 
1910  // Restore clobbered registers in the specified restore block.
1911  MI = RestoreMBB.end();
1912  SB.setMI(&RestoreMBB, MI);
1913  // Generate the restore of SGPR from SB.TmpVGPR.
1914  for (unsigned Offset = 0; Offset < PVD.NumVGPRs; ++Offset) {
1915  // Don't need to load VGPR in.
1916  // Unpack lanes
1917  for (unsigned i = Offset * PVD.PerVGPR,
1918  e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs);
1919  i < e; ++i) {
1920  Register SubReg =
1921  SB.NumSubRegs == 1
1922  ? SB.SuperReg
1923  : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
1924  bool LastSubReg = (i + 1 == e);
1925  auto MIB = BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_READLANE_B32),
1926  SubReg)
1927  .addReg(SB.TmpVGPR, getKillRegState(LastSubReg))
1928  .addImm(i);
1929  if (SB.NumSubRegs > 1 && i == 0)
1931  }
1932  }
1933  SB.restore();
1934 
1936  return false;
1937 }
1938 
1939 /// Special case of eliminateFrameIndex. Returns true if the SGPR was spilled to
1940 /// a VGPR and the stack slot can be safely eliminated when all other users are
1941 /// handled.
1944  int FI,
1945  RegScavenger *RS,
1946  LiveIntervals *LIS) const {
1947  switch (MI->getOpcode()) {
1948  case AMDGPU::SI_SPILL_S1024_SAVE:
1949  case AMDGPU::SI_SPILL_S512_SAVE:
1950  case AMDGPU::SI_SPILL_S256_SAVE:
1951  case AMDGPU::SI_SPILL_S224_SAVE:
1952  case AMDGPU::SI_SPILL_S192_SAVE:
1953  case AMDGPU::SI_SPILL_S160_SAVE:
1954  case AMDGPU::SI_SPILL_S128_SAVE:
1955  case AMDGPU::SI_SPILL_S96_SAVE:
1956  case AMDGPU::SI_SPILL_S64_SAVE:
1957  case AMDGPU::SI_SPILL_S32_SAVE:
1958  return spillSGPR(MI, FI, RS, LIS, true);
1959  case AMDGPU::SI_SPILL_S1024_RESTORE:
1960  case AMDGPU::SI_SPILL_S512_RESTORE:
1961  case AMDGPU::SI_SPILL_S256_RESTORE:
1962  case AMDGPU::SI_SPILL_S224_RESTORE:
1963  case AMDGPU::SI_SPILL_S192_RESTORE:
1964  case AMDGPU::SI_SPILL_S160_RESTORE:
1965  case AMDGPU::SI_SPILL_S128_RESTORE:
1966  case AMDGPU::SI_SPILL_S96_RESTORE:
1967  case AMDGPU::SI_SPILL_S64_RESTORE:
1968  case AMDGPU::SI_SPILL_S32_RESTORE:
1969  return restoreSGPR(MI, FI, RS, LIS, true);
1970  default:
1971  llvm_unreachable("not an SGPR spill instruction");
1972  }
1973 }
1974 
1976  int SPAdj, unsigned FIOperandNum,
1977  RegScavenger *RS) const {
1978  MachineFunction *MF = MI->getParent()->getParent();
1979  MachineBasicBlock *MBB = MI->getParent();
1981  MachineFrameInfo &FrameInfo = MF->getFrameInfo();
1982  const SIInstrInfo *TII = ST.getInstrInfo();
1983  DebugLoc DL = MI->getDebugLoc();
1984 
1985  assert(SPAdj == 0 && "unhandled SP adjustment in call sequence?");
1986 
1987  MachineOperand &FIOp = MI->getOperand(FIOperandNum);
1988  int Index = MI->getOperand(FIOperandNum).getIndex();
1989 
1990  Register FrameReg = FrameInfo.isFixedObjectIndex(Index) && hasBasePointer(*MF)
1991  ? getBaseRegister()
1992  : getFrameRegister(*MF);
1993 
1994  switch (MI->getOpcode()) {
1995  // SGPR register spill
1996  case AMDGPU::SI_SPILL_S1024_SAVE:
1997  case AMDGPU::SI_SPILL_S512_SAVE:
1998  case AMDGPU::SI_SPILL_S256_SAVE:
1999  case AMDGPU::SI_SPILL_S224_SAVE:
2000  case AMDGPU::SI_SPILL_S192_SAVE:
2001  case AMDGPU::SI_SPILL_S160_SAVE:
2002  case AMDGPU::SI_SPILL_S128_SAVE:
2003  case AMDGPU::SI_SPILL_S96_SAVE:
2004  case AMDGPU::SI_SPILL_S64_SAVE:
2005  case AMDGPU::SI_SPILL_S32_SAVE: {
2006  spillSGPR(MI, Index, RS);
2007  break;
2008  }
2009 
2010  // SGPR register restore
2011  case AMDGPU::SI_SPILL_S1024_RESTORE:
2012  case AMDGPU::SI_SPILL_S512_RESTORE:
2013  case AMDGPU::SI_SPILL_S256_RESTORE:
2014  case AMDGPU::SI_SPILL_S224_RESTORE:
2015  case AMDGPU::SI_SPILL_S192_RESTORE:
2016  case AMDGPU::SI_SPILL_S160_RESTORE:
2017  case AMDGPU::SI_SPILL_S128_RESTORE:
2018  case AMDGPU::SI_SPILL_S96_RESTORE:
2019  case AMDGPU::SI_SPILL_S64_RESTORE:
2020  case AMDGPU::SI_SPILL_S32_RESTORE: {
2021  restoreSGPR(MI, Index, RS);
2022  break;
2023  }
2024 
2025  // VGPR register spill
2026  case AMDGPU::SI_SPILL_V1024_SAVE:
2027  case AMDGPU::SI_SPILL_V512_SAVE:
2028  case AMDGPU::SI_SPILL_V256_SAVE:
2029  case AMDGPU::SI_SPILL_V224_SAVE:
2030  case AMDGPU::SI_SPILL_V192_SAVE:
2031  case AMDGPU::SI_SPILL_V160_SAVE:
2032  case AMDGPU::SI_SPILL_V128_SAVE:
2033  case AMDGPU::SI_SPILL_V96_SAVE:
2034  case AMDGPU::SI_SPILL_V64_SAVE:
2035  case AMDGPU::SI_SPILL_V32_SAVE:
2036  case AMDGPU::SI_SPILL_A1024_SAVE:
2037  case AMDGPU::SI_SPILL_A512_SAVE:
2038  case AMDGPU::SI_SPILL_A256_SAVE:
2039  case AMDGPU::SI_SPILL_A224_SAVE:
2040  case AMDGPU::SI_SPILL_A192_SAVE:
2041  case AMDGPU::SI_SPILL_A160_SAVE:
2042  case AMDGPU::SI_SPILL_A128_SAVE:
2043  case AMDGPU::SI_SPILL_A96_SAVE:
2044  case AMDGPU::SI_SPILL_A64_SAVE:
2045  case AMDGPU::SI_SPILL_A32_SAVE:
2046  case AMDGPU::SI_SPILL_AV1024_SAVE:
2047  case AMDGPU::SI_SPILL_AV512_SAVE:
2048  case AMDGPU::SI_SPILL_AV256_SAVE:
2049  case AMDGPU::SI_SPILL_AV224_SAVE:
2050  case AMDGPU::SI_SPILL_AV192_SAVE:
2051  case AMDGPU::SI_SPILL_AV160_SAVE:
2052  case AMDGPU::SI_SPILL_AV128_SAVE:
2053  case AMDGPU::SI_SPILL_AV96_SAVE:
2054  case AMDGPU::SI_SPILL_AV64_SAVE:
2055  case AMDGPU::SI_SPILL_AV32_SAVE: {
2056  const MachineOperand *VData = TII->getNamedOperand(*MI,
2057  AMDGPU::OpName::vdata);
2058  assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() ==
2059  MFI->getStackPtrOffsetReg());
2060 
2061  unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
2062  : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
2063  auto *MBB = MI->getParent();
2065  *MBB, MI, DL, Opc, Index, VData->getReg(), VData->isKill(), FrameReg,
2066  TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(),
2067  *MI->memoperands_begin(), RS);
2068  MFI->addToSpilledVGPRs(getNumSubRegsForSpillOp(MI->getOpcode()));
2069  MI->eraseFromParent();
2070  break;
2071  }
2072  case AMDGPU::SI_SPILL_V32_RESTORE:
2073  case AMDGPU::SI_SPILL_V64_RESTORE:
2074  case AMDGPU::SI_SPILL_V96_RESTORE:
2075  case AMDGPU::SI_SPILL_V128_RESTORE:
2076  case AMDGPU::SI_SPILL_V160_RESTORE:
2077  case AMDGPU::SI_SPILL_V192_RESTORE:
2078  case AMDGPU::SI_SPILL_V224_RESTORE:
2079  case AMDGPU::SI_SPILL_V256_RESTORE:
2080  case AMDGPU::SI_SPILL_V512_RESTORE:
2081  case AMDGPU::SI_SPILL_V1024_RESTORE:
2082  case AMDGPU::SI_SPILL_A32_RESTORE:
2083  case AMDGPU::SI_SPILL_A64_RESTORE:
2084  case AMDGPU::SI_SPILL_A96_RESTORE:
2085  case AMDGPU::SI_SPILL_A128_RESTORE:
2086  case AMDGPU::SI_SPILL_A160_RESTORE:
2087  case AMDGPU::SI_SPILL_A192_RESTORE:
2088  case AMDGPU::SI_SPILL_A224_RESTORE:
2089  case AMDGPU::SI_SPILL_A256_RESTORE:
2090  case AMDGPU::SI_SPILL_A512_RESTORE:
2091  case AMDGPU::SI_SPILL_A1024_RESTORE:
2092  case AMDGPU::SI_SPILL_AV32_RESTORE:
2093  case AMDGPU::SI_SPILL_AV64_RESTORE:
2094  case AMDGPU::SI_SPILL_AV96_RESTORE:
2095  case AMDGPU::SI_SPILL_AV128_RESTORE:
2096  case AMDGPU::SI_SPILL_AV160_RESTORE:
2097  case AMDGPU::SI_SPILL_AV192_RESTORE:
2098  case AMDGPU::SI_SPILL_AV224_RESTORE:
2099  case AMDGPU::SI_SPILL_AV256_RESTORE:
2100  case AMDGPU::SI_SPILL_AV512_RESTORE:
2101  case AMDGPU::SI_SPILL_AV1024_RESTORE: {
2102  const MachineOperand *VData = TII->getNamedOperand(*MI,
2103  AMDGPU::OpName::vdata);
2104  assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() ==
2105  MFI->getStackPtrOffsetReg());
2106 
2107  unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR
2108  : AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
2109  auto *MBB = MI->getParent();
2111  *MBB, MI, DL, Opc, Index, VData->getReg(), VData->isKill(), FrameReg,
2112  TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(),
2113  *MI->memoperands_begin(), RS);
2114  MI->eraseFromParent();
2115  break;
2116  }
2117 
2118  default: {
2119  // Other access to frame index
2120  const DebugLoc &DL = MI->getDebugLoc();
2121 
2122  int64_t Offset = FrameInfo.getObjectOffset(Index);
2123  if (ST.enableFlatScratch()) {
2124  if (TII->isFLATScratch(*MI)) {
2125  assert((int16_t)FIOperandNum ==
2126  AMDGPU::getNamedOperandIdx(MI->getOpcode(),
2127  AMDGPU::OpName::saddr));
2128 
2129  // The offset is always swizzled, just replace it
2130  if (FrameReg)
2131  FIOp.ChangeToRegister(FrameReg, false);
2132 
2133  if (!Offset)
2134  return;
2135 
2136  MachineOperand *OffsetOp =
2137  TII->getNamedOperand(*MI, AMDGPU::OpName::offset);
2138  int64_t NewOffset = Offset + OffsetOp->getImm();
2139  if (TII->isLegalFLATOffset(NewOffset, AMDGPUAS::PRIVATE_ADDRESS,
2141  OffsetOp->setImm(NewOffset);
2142  if (FrameReg)
2143  return;
2144  Offset = 0;
2145  }
2146 
2147  if (!Offset) {
2148  unsigned Opc = MI->getOpcode();
2149  int NewOpc = -1;
2150  if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr) != -1) {
2152  } else if (ST.hasFlatScratchSTMode()) {
2153  // On GFX10 we have ST mode to use no registers for an address.
2154  // Otherwise we need to materialize 0 into an SGPR.
2155  NewOpc = AMDGPU::getFlatScratchInstSTfromSS(Opc);
2156  }
2157 
2158  if (NewOpc != -1) {
2159  MI->removeOperand(
2160  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr));
2161  MI->setDesc(TII->get(NewOpc));
2162  return;
2163  }
2164  }
2165  }
2166 
2167  if (!FrameReg) {
2168  FIOp.ChangeToImmediate(Offset);
2169  if (TII->isImmOperandLegal(*MI, FIOperandNum, FIOp))
2170  return;
2171  }
2172 
2173  // We need to use register here. Check if we can use an SGPR or need
2174  // a VGPR.
2175  FIOp.ChangeToRegister(AMDGPU::M0, false);
2176  bool UseSGPR = TII->isOperandLegal(*MI, FIOperandNum, &FIOp);
2177 
2178  if (!Offset && FrameReg && UseSGPR) {
2179  FIOp.setReg(FrameReg);
2180  return;
2181  }
2182 
2183  const TargetRegisterClass *RC = UseSGPR ? &AMDGPU::SReg_32_XM0RegClass
2184  : &AMDGPU::VGPR_32RegClass;
2185 
2186  Register TmpReg = RS->scavengeRegister(RC, MI, 0, !UseSGPR);
2187  FIOp.setReg(TmpReg);
2188  FIOp.setIsKill(true);
2189 
2190  if ((!FrameReg || !Offset) && TmpReg) {
2191  unsigned Opc = UseSGPR ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
2192  auto MIB = BuildMI(*MBB, MI, DL, TII->get(Opc), TmpReg);
2193  if (FrameReg)
2194  MIB.addReg(FrameReg);
2195  else
2196  MIB.addImm(Offset);
2197 
2198  return;
2199  }
2200 
2201  Register TmpSReg =
2202  UseSGPR ? TmpReg
2203  : RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0,
2204  !UseSGPR);
2205 
2206  // TODO: for flat scratch another attempt can be made with a VGPR index
2207  // if no SGPRs can be scavenged.
2208  if ((!TmpSReg && !FrameReg) || (!TmpReg && !UseSGPR))
2209  report_fatal_error("Cannot scavenge register in FI elimination!");
2210 
2211  if (!TmpSReg) {
2212  // Use frame register and restore it after.
2213  TmpSReg = FrameReg;
2214  FIOp.setReg(FrameReg);
2215  FIOp.setIsKill(false);
2216  }
2217 
2218  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), TmpSReg)
2219  .addReg(FrameReg)
2220  .addImm(Offset);
2221 
2222  if (!UseSGPR)
2223  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
2224  .addReg(TmpSReg, RegState::Kill);
2225 
2226  if (TmpSReg == FrameReg) {
2227  // Undo frame register modification.
2228  BuildMI(*MBB, std::next(MI), DL, TII->get(AMDGPU::S_ADD_I32),
2229  FrameReg)
2230  .addReg(FrameReg)
2231  .addImm(-Offset);
2232  }
2233 
2234  return;
2235  }
2236 
2237  bool IsMUBUF = TII->isMUBUF(*MI);
2238 
2239  if (!IsMUBUF && !MFI->isEntryFunction()) {
2240  // Convert to a swizzled stack address by scaling by the wave size.
2241  // In an entry function/kernel the offset is already swizzled.
2242  bool IsSALU = isSGPRClass(TII->getOpRegClass(*MI, FIOperandNum));
2243  bool LiveSCC = RS->isRegUsed(AMDGPU::SCC);
2244  const TargetRegisterClass *RC = IsSALU && !LiveSCC
2245  ? &AMDGPU::SReg_32RegClass
2246  : &AMDGPU::VGPR_32RegClass;
2247  bool IsCopy = MI->getOpcode() == AMDGPU::V_MOV_B32_e32 ||
2248  MI->getOpcode() == AMDGPU::V_MOV_B32_e64;
2249  Register ResultReg = IsCopy ? MI->getOperand(0).getReg()
2250  : RS->scavengeRegister(RC, MI, 0);
2251 
2252  int64_t Offset = FrameInfo.getObjectOffset(Index);
2253  if (Offset == 0) {
2254  unsigned OpCode = IsSALU && !LiveSCC ? AMDGPU::S_LSHR_B32
2255  : AMDGPU::V_LSHRREV_B32_e64;
2256  // XXX - This never happens because of emergency scavenging slot at 0?
2257  auto Shift = BuildMI(*MBB, MI, DL, TII->get(OpCode), ResultReg)
2259  .addReg(FrameReg);
2260  if (IsSALU && !LiveSCC)
2261  Shift.getInstr()->getOperand(3).setIsDead(
2262  true); // Mark SCC as dead.
2263  if (IsSALU && LiveSCC) {
2264  Register NewDest =
2265  RS->scavengeRegister(&AMDGPU::SReg_32RegClass, Shift, 0);
2266  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
2267  NewDest)
2268  .addReg(ResultReg);
2269  ResultReg = NewDest;
2270  }
2271  } else {
2272  MachineInstrBuilder MIB;
2273  if (!IsSALU) {
2274  if ((MIB = TII->getAddNoCarry(*MBB, MI, DL, ResultReg, *RS)) !=
2275  nullptr) {
2276  // Reuse ResultReg in intermediate step.
2277  Register ScaledReg = ResultReg;
2278 
2279  BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64),
2280  ScaledReg)
2282  .addReg(FrameReg);
2283 
2284  const bool IsVOP2 = MIB->getOpcode() == AMDGPU::V_ADD_U32_e32;
2285 
2286  // TODO: Fold if use instruction is another add of a constant.
2287  if (IsVOP2 || AMDGPU::isInlinableLiteral32(Offset, ST.hasInv2PiInlineImm())) {
2288  // FIXME: This can fail
2289  MIB.addImm(Offset);
2290  MIB.addReg(ScaledReg, RegState::Kill);
2291  if (!IsVOP2)
2292  MIB.addImm(0); // clamp bit
2293  } else {
2294  assert(MIB->getOpcode() == AMDGPU::V_ADD_CO_U32_e64 &&
2295  "Need to reuse carry out register");
2296 
2297  // Use scavenged unused carry out as offset register.
2298  Register ConstOffsetReg;
2299  if (!isWave32)
2300  ConstOffsetReg = getSubReg(MIB.getReg(1), AMDGPU::sub0);
2301  else
2302  ConstOffsetReg = MIB.getReg(1);
2303 
2304  BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::S_MOV_B32), ConstOffsetReg)
2305  .addImm(Offset);
2306  MIB.addReg(ConstOffsetReg, RegState::Kill);
2307  MIB.addReg(ScaledReg, RegState::Kill);
2308  MIB.addImm(0); // clamp bit
2309  }
2310  }
2311  }
2312  if (!MIB || IsSALU) {
2313  // We have to produce a carry out, and there isn't a free SGPR pair
2314  // for it. We can keep the whole computation on the SALU to avoid
2315  // clobbering an additional register at the cost of an extra mov.
2316 
2317  // We may have 1 free scratch SGPR even though a carry out is
2318  // unavailable. Only one additional mov is needed.
2319  Register TmpScaledReg =
2320  RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, false);
2321  Register ScaledReg = TmpScaledReg.isValid() ? TmpScaledReg : FrameReg;
2322 
2323  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHR_B32), ScaledReg)
2324  .addReg(FrameReg)
2326  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), ScaledReg)
2327  .addReg(ScaledReg, RegState::Kill)
2328  .addImm(Offset);
2329  if (!IsSALU)
2330  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), ResultReg)
2331  .addReg(ScaledReg, RegState::Kill);
2332  else
2333  ResultReg = ScaledReg;
2334 
2335  // If there were truly no free SGPRs, we need to undo everything.
2336  if (!TmpScaledReg.isValid()) {
2337  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), ScaledReg)
2338  .addReg(ScaledReg, RegState::Kill)
2339  .addImm(-Offset);
2340  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHL_B32), ScaledReg)
2341  .addReg(FrameReg)
2343  }
2344  }
2345  }
2346 
2347  // Don't introduce an extra copy if we're just materializing in a mov.
2348  if (IsCopy)
2349  MI->eraseFromParent();
2350  else
2351  FIOp.ChangeToRegister(ResultReg, false, false, true);
2352  return;
2353  }
2354 
2355  if (IsMUBUF) {
2356  // Disable offen so we don't need a 0 vgpr base.
2357  assert(static_cast<int>(FIOperandNum) ==
2358  AMDGPU::getNamedOperandIdx(MI->getOpcode(),
2359  AMDGPU::OpName::vaddr));
2360 
2361  auto &SOffset = *TII->getNamedOperand(*MI, AMDGPU::OpName::soffset);
2362  assert((SOffset.isImm() && SOffset.getImm() == 0));
2363 
2364  if (FrameReg != AMDGPU::NoRegister)
2365  SOffset.ChangeToRegister(FrameReg, false);
2366 
2367  int64_t Offset = FrameInfo.getObjectOffset(Index);
2368  int64_t OldImm
2369  = TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm();
2370  int64_t NewOffset = OldImm + Offset;
2371 
2372  if (SIInstrInfo::isLegalMUBUFImmOffset(NewOffset) &&
2373  buildMUBUFOffsetLoadStore(ST, FrameInfo, MI, Index, NewOffset)) {
2374  MI->eraseFromParent();
2375  return;
2376  }
2377  }
2378 
2379  // If the offset is simply too big, don't convert to a scratch wave offset
2380  // relative index.
2381 
2382  FIOp.ChangeToImmediate(Offset);
2383  if (!TII->isImmOperandLegal(*MI, FIOperandNum, FIOp)) {
2384  Register TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
2385  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
2386  .addImm(Offset);
2387  FIOp.ChangeToRegister(TmpReg, false, false, true);
2388  }
2389  }
2390  }
2391 }
2392 
2395 }
2396 
2397 static const TargetRegisterClass *
2399  if (BitWidth <= 64)
2400  return &AMDGPU::VReg_64RegClass;
2401  if (BitWidth <= 96)
2402  return &AMDGPU::VReg_96RegClass;
2403  if (BitWidth <= 128)
2404  return &AMDGPU::VReg_128RegClass;
2405  if (BitWidth <= 160)
2406  return &AMDGPU::VReg_160RegClass;
2407  if (BitWidth <= 192)
2408  return &AMDGPU::VReg_192RegClass;
2409  if (BitWidth <= 224)
2410  return &AMDGPU::VReg_224RegClass;
2411  if (BitWidth <= 256)
2412  return &AMDGPU::VReg_256RegClass;
2413  if (BitWidth <= 512)
2414  return &AMDGPU::VReg_512RegClass;
2415  if (BitWidth <= 1024)
2416  return &AMDGPU::VReg_1024RegClass;
2417 
2418  return nullptr;
2419 }
2420 
2421 static const TargetRegisterClass *
2423  if (BitWidth <= 64)
2424  return &AMDGPU::VReg_64_Align2RegClass;
2425  if (BitWidth <= 96)
2426  return &AMDGPU::VReg_96_Align2RegClass;
2427  if (BitWidth <= 128)
2428  return &AMDGPU::VReg_128_Align2RegClass;
2429  if (BitWidth <= 160)
2430  return &AMDGPU::VReg_160_Align2RegClass;
2431  if (BitWidth <= 192)
2432  return &AMDGPU::VReg_192_Align2RegClass;
2433  if (BitWidth <= 224)
2434  return &AMDGPU::VReg_224_Align2RegClass;
2435  if (BitWidth <= 256)
2436  return &AMDGPU::VReg_256_Align2RegClass;
2437  if (BitWidth <= 512)
2438  return &AMDGPU::VReg_512_Align2RegClass;
2439  if (BitWidth <= 1024)
2440  return &AMDGPU::VReg_1024_Align2RegClass;
2441 
2442  return nullptr;
2443 }
2444 
2445 const TargetRegisterClass *
2447  if (BitWidth == 1)
2448  return &AMDGPU::VReg_1RegClass;
2449  if (BitWidth <= 16)
2450  return &AMDGPU::VGPR_LO16RegClass;
2451  if (BitWidth <= 32)
2452  return &AMDGPU::VGPR_32RegClass;
2455 }
2456 
2457 static const TargetRegisterClass *
2459  if (BitWidth <= 64)
2460  return &AMDGPU::AReg_64RegClass;
2461  if (BitWidth <= 96)
2462  return &AMDGPU::AReg_96RegClass;
2463  if (BitWidth <= 128)
2464  return &AMDGPU::AReg_128RegClass;
2465  if (BitWidth <= 160)
2466  return &AMDGPU::AReg_160RegClass;
2467  if (BitWidth <= 192)
2468  return &AMDGPU::AReg_192RegClass;
2469  if (BitWidth <= 224)
2470  return &AMDGPU::AReg_224RegClass;
2471  if (BitWidth <= 256)
2472  return &AMDGPU::AReg_256RegClass;
2473  if (BitWidth <= 512)
2474  return &AMDGPU::AReg_512RegClass;
2475  if (BitWidth <= 1024)
2476  return &AMDGPU::AReg_1024RegClass;
2477 
2478  return nullptr;
2479 }
2480 
2481 static const TargetRegisterClass *
2483  if (BitWidth <= 64)
2484  return &AMDGPU::AReg_64_Align2RegClass;
2485  if (BitWidth <= 96)
2486  return &AMDGPU::AReg_96_Align2RegClass;
2487  if (BitWidth <= 128)
2488  return &AMDGPU::AReg_128_Align2RegClass;
2489  if (BitWidth <= 160)
2490  return &AMDGPU::AReg_160_Align2RegClass;
2491  if (BitWidth <= 192)
2492  return &AMDGPU::AReg_192_Align2RegClass;
2493  if (BitWidth <= 224)
2494  return &AMDGPU::AReg_224_Align2RegClass;
2495  if (BitWidth <= 256)
2496  return &AMDGPU::AReg_256_Align2RegClass;
2497  if (BitWidth <= 512)
2498  return &AMDGPU::AReg_512_Align2RegClass;
2499  if (BitWidth <= 1024)
2500  return &AMDGPU::AReg_1024_Align2RegClass;
2501 
2502  return nullptr;
2503 }
2504 
2505 const TargetRegisterClass *
2507  if (BitWidth <= 16)
2508  return &AMDGPU::AGPR_LO16RegClass;
2509  if (BitWidth <= 32)
2510  return &AMDGPU::AGPR_32RegClass;
2513 }
2514 
2515 static const TargetRegisterClass *
2517  if (BitWidth <= 64)
2518  return &AMDGPU::AV_64RegClass;
2519  if (BitWidth <= 96)
2520  return &AMDGPU::AV_96RegClass;
2521  if (BitWidth <= 128)
2522  return &AMDGPU::AV_128RegClass;
2523  if (BitWidth <= 160)
2524  return &AMDGPU::AV_160RegClass;
2525  if (BitWidth <= 192)
2526  return &AMDGPU::AV_192RegClass;
2527  if (BitWidth <= 224)
2528  return &AMDGPU::AV_224RegClass;
2529  if (BitWidth <= 256)
2530  return &AMDGPU::AV_256RegClass;
2531  if (BitWidth <= 512)
2532  return &AMDGPU::AV_512RegClass;
2533  if (BitWidth <= 1024)
2534  return &AMDGPU::AV_1024RegClass;
2535 
2536  return nullptr;
2537 }
2538 
2539 static const TargetRegisterClass *
2541  if (BitWidth <= 64)
2542  return &AMDGPU::AV_64_Align2RegClass;
2543  if (BitWidth <= 96)
2544  return &AMDGPU::AV_96_Align2RegClass;
2545  if (BitWidth <= 128)
2546  return &AMDGPU::AV_128_Align2RegClass;
2547  if (BitWidth <= 160)
2548  return &AMDGPU::AV_160_Align2RegClass;
2549  if (BitWidth <= 192)
2550  return &AMDGPU::AV_192_Align2RegClass;
2551  if (BitWidth <= 224)
2552  return &AMDGPU::AV_224_Align2RegClass;
2553  if (BitWidth <= 256)
2554  return &AMDGPU::AV_256_Align2RegClass;
2555  if (BitWidth <= 512)
2556  return &AMDGPU::AV_512_Align2RegClass;
2557  if (BitWidth <= 1024)
2558  return &AMDGPU::AV_1024_Align2RegClass;
2559 
2560  return nullptr;
2561 }
2562 
2563 const TargetRegisterClass *
2565  if (BitWidth <= 16)
2566  return &AMDGPU::VGPR_LO16RegClass;
2567  if (BitWidth <= 32)
2568  return &AMDGPU::AV_32RegClass;
2569  return ST.needsAlignedVGPRs()
2572 }
2573 
2574 const TargetRegisterClass *
2576  if (BitWidth <= 16)
2577  return &AMDGPU::SGPR_LO16RegClass;
2578  if (BitWidth <= 32)
2579  return &AMDGPU::SReg_32RegClass;
2580  if (BitWidth <= 64)
2581  return &AMDGPU::SReg_64RegClass;
2582  if (BitWidth <= 96)
2583  return &AMDGPU::SGPR_96RegClass;
2584  if (BitWidth <= 128)
2585  return &AMDGPU::SGPR_128RegClass;
2586  if (BitWidth <= 160)
2587  return &AMDGPU::SGPR_160RegClass;
2588  if (BitWidth <= 192)
2589  return &AMDGPU::SGPR_192RegClass;
2590  if (BitWidth <= 224)
2591  return &AMDGPU::SGPR_224RegClass;
2592  if (BitWidth <= 256)
2593  return &AMDGPU::SGPR_256RegClass;
2594  if (BitWidth <= 512)
2595  return &AMDGPU::SGPR_512RegClass;
2596  if (BitWidth <= 1024)
2597  return &AMDGPU::SGPR_1024RegClass;
2598 
2599  return nullptr;
2600 }
2601 
2602 // FIXME: This is very slow. It might be worth creating a map from physreg to
2603 // register class.
2604 const TargetRegisterClass *
2606  static const TargetRegisterClass *const BaseClasses[] = {
2607  &AMDGPU::VGPR_LO16RegClass,
2608  &AMDGPU::VGPR_HI16RegClass,
2609  &AMDGPU::SReg_LO16RegClass,
2610  &AMDGPU::AGPR_LO16RegClass,
2611  &AMDGPU::VGPR_32RegClass,
2612  &AMDGPU::SReg_32RegClass,
2613  &AMDGPU::AGPR_32RegClass,
2614  &AMDGPU::AGPR_32RegClass,
2615  &AMDGPU::VReg_64_Align2RegClass,
2616  &AMDGPU::VReg_64RegClass,
2617  &AMDGPU::SReg_64RegClass,
2618  &AMDGPU::AReg_64_Align2RegClass,
2619  &AMDGPU::AReg_64RegClass,
2620  &AMDGPU::VReg_96_Align2RegClass,
2621  &AMDGPU::VReg_96RegClass,
2622  &AMDGPU::SReg_96RegClass,
2623  &AMDGPU::AReg_96_Align2RegClass,
2624  &AMDGPU::AReg_96RegClass,
2625  &AMDGPU::VReg_128_Align2RegClass,
2626  &AMDGPU::VReg_128RegClass,
2627  &AMDGPU::SReg_128RegClass,
2628  &AMDGPU::AReg_128_Align2RegClass,
2629  &AMDGPU::AReg_128RegClass,
2630  &AMDGPU::VReg_160_Align2RegClass,
2631  &AMDGPU::VReg_160RegClass,
2632  &AMDGPU::SReg_160RegClass,
2633  &AMDGPU::AReg_160_Align2RegClass,
2634  &AMDGPU::AReg_160RegClass,
2635  &AMDGPU::VReg_192_Align2RegClass,
2636  &AMDGPU::VReg_192RegClass,
2637  &AMDGPU::SReg_192RegClass,
2638  &AMDGPU::AReg_192_Align2RegClass,
2639  &AMDGPU::AReg_192RegClass,
2640  &AMDGPU::VReg_224_Align2RegClass,
2641  &AMDGPU::VReg_224RegClass,
2642  &AMDGPU::SReg_224RegClass,
2643  &AMDGPU::AReg_224_Align2RegClass,
2644  &AMDGPU::AReg_224RegClass,
2645  &AMDGPU::VReg_256_Align2RegClass,
2646  &AMDGPU::VReg_256RegClass,
2647  &AMDGPU::SReg_256RegClass,
2648  &AMDGPU::AReg_256_Align2RegClass,
2649  &AMDGPU::AReg_256RegClass,
2650  &AMDGPU::VReg_512_Align2RegClass,
2651  &AMDGPU::VReg_512RegClass,
2652  &AMDGPU::SReg_512RegClass,
2653  &AMDGPU::AReg_512_Align2RegClass,
2654  &AMDGPU::AReg_512RegClass,
2655  &AMDGPU::SReg_1024RegClass,
2656  &AMDGPU::VReg_1024_Align2RegClass,
2657  &AMDGPU::VReg_1024RegClass,
2658  &AMDGPU::AReg_1024_Align2RegClass,
2659  &AMDGPU::AReg_1024RegClass,
2660  &AMDGPU::SCC_CLASSRegClass,
2661  &AMDGPU::Pseudo_SReg_32RegClass,
2662  &AMDGPU::Pseudo_SReg_128RegClass,
2663  };
2664 
2665  for (const TargetRegisterClass *BaseClass : BaseClasses) {
2666  if (BaseClass->contains(Reg)) {
2667  return BaseClass;
2668  }
2669  }
2670  return nullptr;
2671 }
2672 
2674  Register Reg) const {
2675  const TargetRegisterClass *RC;
2676  if (Reg.isVirtual())
2677  RC = MRI.getRegClass(Reg);
2678  else
2679  RC = getPhysRegClass(Reg);
2680  return isSGPRClass(RC);
2681 }
2682 
2683 const TargetRegisterClass *
2685  unsigned Size = getRegSizeInBits(*SRC);
2686  const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size);
2687  assert(VRC && "Invalid register class size");
2688  return VRC;
2689 }
2690 
2691 const TargetRegisterClass *
2693  unsigned Size = getRegSizeInBits(*SRC);
2694  const TargetRegisterClass *ARC = getAGPRClassForBitWidth(Size);
2695  assert(ARC && "Invalid register class size");
2696  return ARC;
2697 }
2698 
2699 const TargetRegisterClass *
2701  unsigned Size = getRegSizeInBits(*VRC);
2702  if (Size == 32)
2703  return &AMDGPU::SGPR_32RegClass;
2704  const TargetRegisterClass *SRC = getSGPRClassForBitWidth(Size);
2705  assert(SRC && "Invalid register class size");
2706  return SRC;
2707 }
2708 
2710  const TargetRegisterClass *RC, unsigned SubIdx) const {
2711  if (SubIdx == AMDGPU::NoSubRegister)
2712  return RC;
2713 
2714  // We can assume that each lane corresponds to one 32-bit register.
2715  unsigned Size = getNumChannelsFromSubReg(SubIdx) * 32;
2716  if (isAGPRClass(RC)) {
2717  RC = getAGPRClassForBitWidth(Size);
2718  } else if (isVGPRClass(RC)) {
2719  RC = getVGPRClassForBitWidth(Size);
2720  } else if (isVectorSuperClass(RC)) {
2721  RC = getVectorSuperClassForBitWidth(Size);
2722  } else {
2723  RC = getSGPRClassForBitWidth(Size);
2724  }
2725  assert(RC && "Invalid sub-register class size");
2726  return RC;
2727 }
2728 
2729 const TargetRegisterClass *
2731  const TargetRegisterClass *SubRC,
2732  unsigned SubIdx) const {
2733  // Ensure this subregister index is aligned in the super register.
2734  const TargetRegisterClass *MatchRC =
2735  getMatchingSuperRegClass(SuperRC, SubRC, SubIdx);
2736  return MatchRC && MatchRC->hasSubClassEq(SuperRC) ? MatchRC : nullptr;
2737 }
2738 
2739 bool SIRegisterInfo::opCanUseInlineConstant(unsigned OpType) const {
2740  if (OpType >= AMDGPU::OPERAND_REG_INLINE_AC_FIRST &&
2742  return !ST.hasMFMAInlineLiteralBug();
2743 
2744  return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
2745  OpType <= AMDGPU::OPERAND_SRC_LAST;
2746 }
2747 
2749  const TargetRegisterClass *DefRC,
2750  unsigned DefSubReg,
2751  const TargetRegisterClass *SrcRC,
2752  unsigned SrcSubReg) const {
2753  // We want to prefer the smallest register class possible, so we don't want to
2754  // stop and rewrite on anything that looks like a subregister
2755  // extract. Operations mostly don't care about the super register class, so we
2756  // only want to stop on the most basic of copies between the same register
2757  // class.
2758  //
2759  // e.g. if we have something like
2760  // %0 = ...
2761  // %1 = ...
2762  // %2 = REG_SEQUENCE %0, sub0, %1, sub1, %2, sub2
2763  // %3 = COPY %2, sub0
2764  //
2765  // We want to look through the COPY to find:
2766  // => %3 = COPY %0
2767 
2768  // Plain copy.
2769  return getCommonSubClass(DefRC, SrcRC) != nullptr;
2770 }
2771 
2772 bool SIRegisterInfo::opCanUseLiteralConstant(unsigned OpType) const {
2773  // TODO: 64-bit operands have extending behavior from 32-bit literal.
2774  return OpType >= AMDGPU::OPERAND_REG_IMM_FIRST &&
2775  OpType <= AMDGPU::OPERAND_REG_IMM_LAST;
2776 }
2777 
2778 /// Returns a lowest register that is not used at any point in the function.
2779 /// If all registers are used, then this function will return
2780 /// AMDGPU::NoRegister. If \p ReserveHighestVGPR = true, then return
2781 /// highest unused register.
2783  const TargetRegisterClass *RC,
2784  const MachineFunction &MF,
2785  bool ReserveHighestVGPR) const {
2786  if (ReserveHighestVGPR) {
2787  for (MCRegister Reg : reverse(*RC))
2789  return Reg;
2790  } else {
2791  for (MCRegister Reg : *RC)
2793  return Reg;
2794  }
2795  return MCRegister();
2796 }
2797 
2799  unsigned EltSize) const {
2800  const unsigned RegBitWidth = AMDGPU::getRegBitWidth(*RC->MC);
2801  assert(RegBitWidth >= 32 && RegBitWidth <= 1024);
2802 
2803  const unsigned RegDWORDs = RegBitWidth / 32;
2804  const unsigned EltDWORDs = EltSize / 4;
2805  assert(RegSplitParts.size() + 1 >= EltDWORDs);
2806 
2807  const std::vector<int16_t> &Parts = RegSplitParts[EltDWORDs - 1];
2808  const unsigned NumParts = RegDWORDs / EltDWORDs;
2809 
2810  return makeArrayRef(Parts.data(), NumParts);
2811 }
2812 
2813 const TargetRegisterClass*
2815  Register Reg) const {
2816  return Reg.isVirtual() ? MRI.getRegClass(Reg) : getPhysRegClass(Reg);
2817 }
2818 
2820  Register Reg) const {
2822  // Registers without classes are unaddressable, SGPR-like registers.
2823  return RC && isVGPRClass(RC);
2824 }
2825 
2827  Register Reg) const {
2829 
2830  // Registers without classes are unaddressable, SGPR-like registers.
2831  return RC && isAGPRClass(RC);
2832 }
2833 
2835  const TargetRegisterClass *SrcRC,
2836  unsigned SubReg,
2837  const TargetRegisterClass *DstRC,
2838  unsigned DstSubReg,
2839  const TargetRegisterClass *NewRC,
2840  LiveIntervals &LIS) const {
2841  unsigned SrcSize = getRegSizeInBits(*SrcRC);
2842  unsigned DstSize = getRegSizeInBits(*DstRC);
2843  unsigned NewSize = getRegSizeInBits(*NewRC);
2844 
2845  // Do not increase size of registers beyond dword, we would need to allocate
2846  // adjacent registers and constraint regalloc more than needed.
2847 
2848  // Always allow dword coalescing.
2849  if (SrcSize <= 32 || DstSize <= 32)
2850  return true;
2851 
2852  return NewSize <= DstSize || NewSize <= SrcSize;
2853 }
2854 
2856  MachineFunction &MF) const {
2858 
2859  unsigned Occupancy = ST.getOccupancyWithLocalMemSize(MFI->getLDSSize(),
2860  MF.getFunction());
2861  switch (RC->getID()) {
2862  default:
2863  return AMDGPUGenRegisterInfo::getRegPressureLimit(RC, MF);
2864  case AMDGPU::VGPR_32RegClassID:
2865  case AMDGPU::VGPR_LO16RegClassID:
2866  case AMDGPU::VGPR_HI16RegClassID:
2867  return std::min(ST.getMaxNumVGPRs(Occupancy), ST.getMaxNumVGPRs(MF));
2868  case AMDGPU::SGPR_32RegClassID:
2869  case AMDGPU::SGPR_LO16RegClassID:
2870  return std::min(ST.getMaxNumSGPRs(Occupancy, true), ST.getMaxNumSGPRs(MF));
2871  }
2872 }
2873 
2875  unsigned Idx) const {
2876  if (Idx == AMDGPU::RegisterPressureSets::VGPR_32 ||
2877  Idx == AMDGPU::RegisterPressureSets::AGPR_32)
2878  return getRegPressureLimit(&AMDGPU::VGPR_32RegClass,
2879  const_cast<MachineFunction &>(MF));
2880 
2881  if (Idx == AMDGPU::RegisterPressureSets::SReg_32)
2882  return getRegPressureLimit(&AMDGPU::SGPR_32RegClass,
2883  const_cast<MachineFunction &>(MF));
2884 
2885  llvm_unreachable("Unexpected register pressure set!");
2886 }
2887 
2888 const int *SIRegisterInfo::getRegUnitPressureSets(unsigned RegUnit) const {
2889  static const int Empty[] = { -1 };
2890 
2891  if (RegPressureIgnoredUnits[RegUnit])
2892  return Empty;
2893 
2894  return AMDGPUGenRegisterInfo::getRegUnitPressureSets(RegUnit);
2895 }
2896 
2898  // Not a callee saved register.
2899  return AMDGPU::SGPR30_SGPR31;
2900 }
2901 
2902 const TargetRegisterClass *
2904  const RegisterBank &RB) const {
2905  switch (RB.getID()) {
2906  case AMDGPU::VGPRRegBankID:
2907  return getVGPRClassForBitWidth(std::max(32u, Size));
2908  case AMDGPU::VCCRegBankID:
2909  assert(Size == 1);
2910  return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
2911  : &AMDGPU::SReg_64_XEXECRegClass;
2912  case AMDGPU::SGPRRegBankID:
2913  return getSGPRClassForBitWidth(std::max(32u, Size));
2914  case AMDGPU::AGPRRegBankID:
2915  return getAGPRClassForBitWidth(std::max(32u, Size));
2916  default:
2917  llvm_unreachable("unknown register bank");
2918  }
2919 }
2920 
2921 const TargetRegisterClass *
2923  const MachineRegisterInfo &MRI) const {
2924  const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg());
2925  if (const RegisterBank *RB = RCOrRB.dyn_cast<const RegisterBank*>())
2926  return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB);
2927 
2928  if (const auto *RC = RCOrRB.dyn_cast<const TargetRegisterClass *>())
2929  return getAllocatableClass(RC);
2930 
2931  return nullptr;
2932 }
2933 
2935  return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC;
2936 }
2937 
2939  // VGPR tuples have an alignment requirement on gfx90a variants.
2940  return ST.needsAlignedVGPRs() ? &AMDGPU::VReg_64_Align2RegClass
2941  : &AMDGPU::VReg_64RegClass;
2942 }
2943 
2944 const TargetRegisterClass *
2945 SIRegisterInfo::getRegClass(unsigned RCID) const {
2946  switch ((int)RCID) {
2947  case AMDGPU::SReg_1RegClassID:
2948  return getBoolRC();
2949  case AMDGPU::SReg_1_XEXECRegClassID:
2950  return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
2951  : &AMDGPU::SReg_64_XEXECRegClass;
2952  case -1:
2953  return nullptr;
2954  default:
2956  }
2957 }
2958 
2959 // Find reaching register definition
2961  MachineInstr &Use,
2963  LiveIntervals *LIS) const {
2964  auto &MDT = LIS->getAnalysis<MachineDominatorTree>();
2965  SlotIndex UseIdx = LIS->getInstructionIndex(Use);
2966  SlotIndex DefIdx;
2967 
2968  if (Reg.isVirtual()) {
2969  if (!LIS->hasInterval(Reg))
2970  return nullptr;
2971  LiveInterval &LI = LIS->getInterval(Reg);
2972  LaneBitmask SubLanes = SubReg ? getSubRegIndexLaneMask(SubReg)
2974  VNInfo *V = nullptr;
2975  if (LI.hasSubRanges()) {
2976  for (auto &S : LI.subranges()) {
2977  if ((S.LaneMask & SubLanes) == SubLanes) {
2978  V = S.getVNInfoAt(UseIdx);
2979  break;
2980  }
2981  }
2982  } else {
2983  V = LI.getVNInfoAt(UseIdx);
2984  }
2985  if (!V)
2986  return nullptr;
2987  DefIdx = V->def;
2988  } else {
2989  // Find last def.
2990  for (MCRegUnitIterator Units(Reg.asMCReg(), this); Units.isValid();
2991  ++Units) {
2992  LiveRange &LR = LIS->getRegUnit(*Units);
2993  if (VNInfo *V = LR.getVNInfoAt(UseIdx)) {
2994  if (!DefIdx.isValid() ||
2995  MDT.dominates(LIS->getInstructionFromIndex(DefIdx),
2996  LIS->getInstructionFromIndex(V->def)))
2997  DefIdx = V->def;
2998  } else {
2999  return nullptr;
3000  }
3001  }
3002  }
3003 
3004  MachineInstr *Def = LIS->getInstructionFromIndex(DefIdx);
3005 
3006  if (!Def || !MDT.dominates(Def, &Use))
3007  return nullptr;
3008 
3009  assert(Def->modifiesRegister(Reg, this));
3010 
3011  return Def;
3012 }
3013 
3015  assert(getRegSizeInBits(*getPhysRegClass(Reg)) <= 32);
3016 
3017  for (const TargetRegisterClass &RC : { AMDGPU::VGPR_32RegClass,
3018  AMDGPU::SReg_32RegClass,
3019  AMDGPU::AGPR_32RegClass } ) {
3020  if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::lo16, &RC))
3021  return Super;
3022  }
3023  if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::hi16,
3024  &AMDGPU::VGPR_32RegClass)) {
3025  return Super;
3026  }
3027 
3028  return AMDGPU::NoRegister;
3029 }
3030 
3032  if (!ST.needsAlignedVGPRs())
3033  return true;
3034 
3035  if (isVGPRClass(&RC))
3036  return RC.hasSuperClassEq(getVGPRClassForBitWidth(getRegSizeInBits(RC)));
3037  if (isAGPRClass(&RC))
3038  return RC.hasSuperClassEq(getAGPRClassForBitWidth(getRegSizeInBits(RC)));
3039  if (isVectorSuperClass(&RC))
3040  return RC.hasSuperClassEq(
3041  getVectorSuperClassForBitWidth(getRegSizeInBits(RC)));
3042 
3043  return true;
3044 }
3045 
3046 const TargetRegisterClass *
3048  if (!RC || !ST.needsAlignedVGPRs())
3049  return RC;
3050 
3051  unsigned Size = getRegSizeInBits(*RC);
3052  if (Size <= 32)
3053  return RC;
3054 
3055  if (isVGPRClass(RC))
3056  return getAlignedVGPRClassForBitWidth(Size);
3057  if (isAGPRClass(RC))
3058  return getAlignedAGPRClassForBitWidth(Size);
3059  if (isVectorSuperClass(RC))
3061 
3062  return RC;
3063 }
3064 
3066  switch (PhysReg) {
3067  case AMDGPU::SGPR_NULL:
3068  case AMDGPU::SRC_SHARED_BASE:
3069  case AMDGPU::SRC_PRIVATE_BASE:
3070  case AMDGPU::SRC_SHARED_LIMIT:
3071  case AMDGPU::SRC_PRIVATE_LIMIT:
3072  return true;
3073  default:
3074  return false;
3075  }
3076 }
3077 
3080  return makeArrayRef(AMDGPU::SGPR_128RegClass.begin(),
3081  ST.getMaxNumSGPRs(MF) / 4);
3082 }
3083 
3086  return makeArrayRef(AMDGPU::SGPR_64RegClass.begin(),
3087  ST.getMaxNumSGPRs(MF) / 2);
3088 }
3089 
3092  return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(), ST.getMaxNumSGPRs(MF));
3093 }
llvm::LaneBitmask
Definition: LaneBitmask.h:40
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getLargestLegalSuperClass
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Definition: TargetRegisterInfo.h:788
llvm::SIRegisterInfo::getVGPRClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getVGPRClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:2446
llvm::SIRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Definition: SIRegisterInfo.cpp:390
llvm::SIRegisterInfo::getEquivalentVGPRClass
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
Definition: SIRegisterInfo.cpp:2684
llvm::SIMachineFunctionInfo::getSGPRSpillVGPRs
ArrayRef< SGPRSpillVGPR > getSGPRSpillVGPRs() const
Definition: SIMachineFunctionInfo.h:562
getAlignedVectorSuperClassForBitWidth
static const TargetRegisterClass * getAlignedVectorSuperClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:2540
llvm::AMDGPUSubtarget::hasInv2PiInlineImm
bool hasInv2PiInlineImm() const
Definition: AMDGPUSubtarget.h:184
llvm::SIRegisterInfo::isAGPRClass
static bool isAGPRClass(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:193
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::SGPRSpillBuilder::TRI
const SIRegisterInfo & TRI
Definition: SIRegisterInfo.cpp:106
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:72
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
llvm::MachineRegisterInfo::isPhysRegUsed
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
Definition: MachineRegisterInfo.cpp:581
llvm::Pass::getAnalysis
AnalysisType & getAnalysis() const
getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information ...
Definition: PassAnalysisSupport.h:230
llvm::SIMachineFunctionInfo::getVGPRForAGPRCopy
Register getVGPRForAGPRCopy() const
Definition: SIMachineFunctionInfo.h:523
llvm::SIRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const override
Definition: SIRegisterInfo.cpp:3065
llvm::SIRegisterInfo::needsFrameBaseReg
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:792
llvm::AMDGPU::getFlatScratchInstSVfromSS
LLVM_READONLY int getFlatScratchInstSVfromSS(uint16_t Opcode)
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::MachineFrameInfo::getNumFixedObjects
unsigned getNumFixedObjects() const
Return the number of fixed objects.
Definition: MachineFrameInfo.h:412
llvm::SIRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned RCID) const
Definition: SIRegisterInfo.cpp:2945
llvm::SGPRSpillBuilder::PerVGPRData
Definition: SIRegisterInfo.cpp:73
llvm::SIRegisterInfo::requiresVirtualBaseRegisters
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
Definition: SIRegisterInfo.cpp:764
SIMachineFunctionInfo.h
llvm::SIRegisterInfo::restoreSGPR
bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false) const
Definition: SIRegisterInfo.cpp:1789
llvm::SlotIndex::isValid
bool isValid() const
Returns true if this is a valid index.
Definition: SlotIndexes.h:150
llvm::GCNSubtarget::getFrameLowering
const SIFrameLowering * getFrameLowering() const override
Definition: GCNSubtarget.h:218
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MCRegister::from
static MCRegister from(unsigned Val)
Check the provided unsigned value is a valid MCRegister.
Definition: MCRegister.h:67
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::SIRegisterInfo::getAllSGPR128
ArrayRef< MCPhysReg > getAllSGPR128(const MachineFunction &MF) const
Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:3079
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:509
llvm::CallingConv::AMDGPU_Gfx
@ AMDGPU_Gfx
Calling convention used for AMD graphics targets.
Definition: CallingConv.h:250
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::SIRegisterInfo::getFrameIndexInstrOffset
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
Definition: SIRegisterInfo.cpp:778
llvm::SIRegisterInfo::getRegUnitPressureSets
const int * getRegUnitPressureSets(unsigned RegUnit) const override
Definition: SIRegisterInfo.cpp:2888
llvm::SIRegisterInfo::getScratchInstrOffset
int64_t getScratchInstrOffset(const MachineInstr *MI) const
Definition: SIRegisterInfo.cpp:770
llvm::SGPRSpillBuilder::IsKill
bool IsKill
Definition: SIRegisterInfo.cpp:84
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:456
llvm::SIRegisterInfo::getAllSGPR64
ArrayRef< MCPhysReg > getAllSGPR64(const MachineFunction &MF) const
Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:3085
llvm::LiveIntervals::getInstructionFromIndex
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Definition: LiveIntervals.h:231
llvm::GCNSubtarget::needsAlignedVGPRs
bool needsAlignedVGPRs() const
Return if operations acting on VGPR tuples require even alignment.
Definition: GCNSubtarget.h:1025
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:151
llvm::TargetRegisterInfo::shouldRealignStack
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
Definition: TargetRegisterInfo.cpp:483
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:50
llvm::SIRegisterInfo::SIRegisterInfo
SIRegisterInfo(const GCNSubtarget &ST)
Definition: SIRegisterInfo.cpp:319
llvm::VNInfo::def
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
getOffsetMUBUFStore
static int getOffsetMUBUFStore(unsigned Opc)
Definition: SIRegisterInfo.cpp:1035
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:664
llvm::SIRegisterInfo::getVectorSuperClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getVectorSuperClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:2564
llvm::AMDGPUSubtarget::getOccupancyWithLocalMemSize
unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const
Inverse of getMaxLocalMemWithWaveCount.
Definition: AMDGPUSubtarget.cpp:312
llvm::LiveIntervals::removeAllRegUnitsForPhysReg
void removeAllRegUnitsForPhysReg(MCRegister Reg)
Remove associated live ranges for the register units associated with Reg.
Definition: LiveIntervals.h:425
llvm::AMDGPUMachineFunction::getLDSSize
uint32_t getLDSSize() const
Definition: AMDGPUMachineFunction.h:74
Shift
bool Shift
Definition: README.txt:468
llvm::BitVector::resize
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:334
llvm::reverse
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
Definition: STLExtras.h:380
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:126
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:226
llvm::LivePhysRegs::contains
bool contains(MCPhysReg Reg) const
Returns true if register Reg is contained in the set.
Definition: LivePhysRegs.h:108
llvm::SIRegisterInfo::getRegClassForSizeOnBank
const TargetRegisterClass * getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank) const
Definition: SIRegisterInfo.cpp:2903
llvm::SIRegisterInfo::getEquivalentAGPRClass
const TargetRegisterClass * getEquivalentAGPRClass(const TargetRegisterClass *SRC) const
Definition: SIRegisterInfo.cpp:2692
llvm::SIRegisterInfo::materializeFrameBaseRegister
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:806
getOffenMUBUFStore
static int getOffenMUBUFStore(unsigned Opc)
Definition: SIRegisterInfo.cpp:1093
llvm::SGPRSpillBuilder::TII
const SIInstrInfo & TII
Definition: SIRegisterInfo.cpp:105
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::SIRegisterInfo::getAllAllocatableSRegMask
const uint32_t * getAllAllocatableSRegMask() const
Definition: SIRegisterInfo.cpp:525
llvm::CallingConv::Cold
@ Cold
Definition: CallingConv.h:48
llvm::SIRegisterInfo::isAsmClobberable
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
Definition: SIRegisterInfo.cpp:720
llvm::AMDGPU::OPERAND_REG_IMM_LAST
@ OPERAND_REG_IMM_LAST
Definition: SIDefines.h:189
getAlignedVGPRClassForBitWidth
static const TargetRegisterClass * getAlignedVGPRClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:2422
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
llvm::SIRegisterInfo::getProperlyAlignedRC
const TargetRegisterClass * getProperlyAlignedRC(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.cpp:3047
llvm::SIRegisterInfo::requiresFrameIndexReplacementScavenging
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:758
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:330
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::cl::ReallyHidden
@ ReallyHidden
Definition: CommandLine.h:140
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
llvm::SIMachineFunctionInfo::SpilledReg
Definition: SIMachineFunctionInfo.h:454
llvm::SIRegisterInfo::getSubRegClass
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
Definition: SIRegisterInfo.cpp:2709
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
llvm::SIRegisterInfo::buildVGPRSpillLoadStore
void buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const
Definition: SIRegisterInfo.cpp:1636
llvm::SIRegisterInfo::findReachingDef
MachineInstr * findReachingDef(Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
Definition: SIRegisterInfo.cpp:2960
llvm::LiveIntervals::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
Definition: LiveIntervals.h:226
llvm::GCNSubtarget::getInstrInfo
const SIInstrInfo * getInstrInfo() const override
Definition: GCNSubtarget.h:214
llvm::RegScavenger::isRegUsed
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
Definition: RegisterScavenging.cpp:260
llvm::SGPRSpillBuilder::getPerVGPRData
PerVGPRData getPerVGPRData()
Definition: SIRegisterInfo.cpp:144
getAnyVGPRClassForBitWidth
static const TargetRegisterClass * getAnyVGPRClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:2398
llvm::MachineFrameInfo::hasStackObjects
bool hasStackObjects() const
Return true if there are any stack objects in this function.
Definition: MachineFrameInfo.h:349
llvm::SIFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: SIFrameLowering.cpp:1461
llvm::MachineMemOperand::getPointerInfo
const MachinePointerInfo & getPointerInfo() const
Definition: MachineMemOperand.h:200
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:389
llvm::SIRegisterInfo::getCrossCopyRegClass
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
Returns a legal register class to copy a register in the specified class to or from.
Definition: SIRegisterInfo.cpp:931
llvm::SIRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:490
llvm::AMDGPU::OPERAND_REG_INLINE_AC_LAST
@ OPERAND_REG_INLINE_AC_LAST
Definition: SIDefines.h:195
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:502
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
lo16
We lo16(.CPI_X_0)(r2) lis r2
llvm::DXIL::OpCode
OpCode
Definition: DXILConstants.h:18
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:517
llvm::GCNSubtarget::getMaxNumSGPRs
unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const
Definition: GCNSubtarget.h:1111
llvm::MachineOperand::ChangeToRegister
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
Definition: MachineOperand.cpp:239
GCNSubtarget.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:738
llvm::RegScavenger::scavengeRegister
Register scavengeRegister(const TargetRegisterClass *RC, MachineBasicBlock::iterator I, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available and do the appropriate bookkeeping.
Definition: RegisterScavenging.cpp:518
llvm::SGPRSpillBuilder::SGPRSpillBuilder
SGPRSpillBuilder(const SIRegisterInfo &TRI, const SIInstrInfo &TII, bool IsWave32, MachineBasicBlock::iterator MI, Register Reg, bool IsKill, int Index, RegScavenger *RS)
Definition: SIRegisterInfo.cpp:118
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:925
llvm::SGPRSpillBuilder::setMI
void setMI(MachineBasicBlock *NewMBB, MachineBasicBlock::iterator NewMI)
Definition: SIRegisterInfo.cpp:310
llvm::LiveIntervals::InsertMachineInstrInMaps
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
Definition: LiveIntervals.h:266
llvm::SIRegisterInfo::getLargestLegalSuperClass
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:436
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::SIRegisterInfo::getReturnAddressReg
MCRegister getReturnAddressReg(const MachineFunction &MF) const
Definition: SIRegisterInfo.cpp:2897
llvm::SIRegisterInfo::getRegClassForReg
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2814
llvm::SIRegisterInfo::isAGPR
bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2826
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:154
llvm::alignDown
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
Definition: MathExtras.h:780
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::SGPRSpillBuilder::SavedExecReg
Register SavedExecReg
Definition: SIRegisterInfo.cpp:96
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::SIRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
Definition: SIRegisterInfo.cpp:1975
llvm::M0
unsigned M0(unsigned Val)
Definition: VE.h:370
llvm::SIRegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:2855
llvm::SIMachineFunctionInfo::getStackPtrOffsetReg
Register getStackPtrOffsetReg() const
Definition: SIMachineFunctionInfo.h:796
llvm::SIMachineFunctionInfo::usesAGPRs
bool usesAGPRs(const MachineFunction &MF) const
Definition: SIMachineFunctionInfo.cpp:677
llvm::TargetRegisterClass::hasSuperClassEq
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Definition: TargetRegisterInfo.h:139
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
getAlignedAGPRClassForBitWidth
static const TargetRegisterClass * getAlignedAGPRClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:2482
llvm::MachineFrameInfo::getStackID
uint8_t getStackID(int ObjectIdx) const
Definition: MachineFrameInfo.h:723
llvm::SGPRSpillBuilder::IsWave32
bool IsWave32
Definition: SIRegisterInfo.cpp:107
llvm::RegisterBank::getID
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:47
llvm::ThreadPriority::Low
@ Low
Lower the current thread's priority such that it does not affect foreground tasks significantly.
llvm::SIRegisterInfo::getNumChannelsFromSubReg
unsigned getNumChannelsFromSubReg(unsigned SubReg) const
Definition: SIRegisterInfo.h:366
llvm::SIRegisterInfo::getSubRegFromChannel
static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs=1)
Definition: SIRegisterInfo.cpp:529
buildMUBUFOffsetLoadStore
static bool buildMUBUFOffsetLoadStore(const GCNSubtarget &ST, MachineFrameInfo &MFI, MachineBasicBlock::iterator MI, int Index, int64_t Offset)
Definition: SIRegisterInfo.cpp:1194
llvm::SGPRSpillBuilder::ExecReg
Register ExecReg
Definition: SIRegisterInfo.cpp:108
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:518
llvm::SIRegisterInfo::isSGPRClass
static bool isSGPRClass(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:176
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::SIRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: SIRegisterInfo.cpp:415
llvm::SIRegisterInfo::getVCC
MCRegister getVCC() const
Definition: SIRegisterInfo.cpp:2934
llvm::BitVector
Definition: BitVector.h:75
llvm::SGPRSpillBuilder::EltSize
unsigned EltSize
Definition: SIRegisterInfo.cpp:99
getOffenMUBUFLoad
static int getOffenMUBUFLoad(unsigned Opc)
Definition: SIRegisterInfo.cpp:1116
llvm::SIRegisterInfo::getVGPR64Class
const TargetRegisterClass * getVGPR64Class() const
Definition: SIRegisterInfo.cpp:2938
llvm::SGPRSpillBuilder::TmpVGPRIndex
int TmpVGPRIndex
Definition: SIRegisterInfo.cpp:92
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
llvm::SIFrameLowering
Definition: SIFrameLowering.h:16
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:680
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:82
llvm::GCNSubtarget::getMaxNumVGPRs
unsigned getMaxNumVGPRs(unsigned WavesPerEU) const
Definition: GCNSubtarget.h:1181
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:213
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
llvm::AMDGPUSubtarget::getWavefrontSize
unsigned getWavefrontSize() const
Definition: AMDGPUSubtarget.h:200
llvm::SIRegisterInfo::opCanUseLiteralConstant
bool opCanUseLiteralConstant(unsigned OpType) const
Definition: SIRegisterInfo.cpp:2772
llvm::SIRegisterInfo::isFrameOffsetLegal
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:906
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::SIRegisterInfo::getBaseRegister
Register getBaseRegister() const
Definition: SIRegisterInfo.cpp:511
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::AMDGPU::getFlatScratchInstSVfromSVS
LLVM_READONLY int getFlatScratchInstSVfromSVS(uint16_t Opcode)
llvm::cl::opt< bool >
llvm::SIRegisterInfo::getAllVGPRRegMask
const uint32_t * getAllVGPRRegMask() const
Definition: SIRegisterInfo.cpp:513
llvm::AMDGPU::getRegBitWidth
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
Definition: AMDGPUBaseInfo.cpp:1881
llvm::SIMachineFunctionInfo::getVGPRSpillAGPRs
ArrayRef< MCPhysReg > getVGPRSpillAGPRs() const
Definition: SIMachineFunctionInfo.h:568
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
AMDGPURegisterBankInfo.h
llvm::SGPRSpillBuilder::SplitParts
ArrayRef< int16_t > SplitParts
Definition: SIRegisterInfo.cpp:82
AMDGPUMCTargetDesc.h
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:515
llvm::LiveIntervals::ReplaceMachineInstrInMaps
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
Definition: LiveIntervals.h:280
llvm::SIRegisterInfo::shouldRewriteCopySrc
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
Definition: SIRegisterInfo.cpp:2748
llvm::SIRegisterInfo::shouldRealignStack
bool shouldRealignStack(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:725
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::SIRegisterInfo::getRegAsmName
StringRef getRegAsmName(MCRegister Reg) const override
Definition: SIRegisterInfo.cpp:2393
LiveIntervals.h
llvm::MachineInstr::ReloadReuse
@ ReloadReuse
Definition: MachineInstr.h:77
llvm::SIRegisterInfo::isVGPRClass
static bool isVGPRClass(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:188
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::SGPRSpillBuilder::NumSubRegs
unsigned NumSubRegs
Definition: SIRegisterInfo.cpp:83
llvm::LiveRange
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::SIRegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:749
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:63
llvm::SIRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: SIRegisterInfo.cpp:504
llvm::PointerUnion::dyn_cast
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
Definition: PointerUnion.h:162
llvm::LivePhysRegs::available
bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const
Returns true if register Reg and no aliasing register is in the set.
Definition: LivePhysRegs.cpp:141
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::SGPRSpillBuilder::PerVGPRData::VGPRLanes
int64_t VGPRLanes
Definition: SIRegisterInfo.cpp:76
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::SIInstrInfo::isFLATScratch
static bool isFLATScratch(const MachineInstr &MI)
Definition: SIInstrInfo.h:542
llvm::SIRegisterInfo::getAllVectorRegMask
const uint32_t * getAllVectorRegMask() const
Definition: SIRegisterInfo.cpp:521
llvm::AMDGPU::OPERAND_SRC_FIRST
@ OPERAND_SRC_FIRST
Definition: SIDefines.h:197
llvm::GCNSubtarget::hasMFMAInlineLiteralBug
bool hasMFMAInlineLiteralBug() const
Definition: GCNSubtarget.h:930
llvm::SIRegisterInfo::isSGPRReg
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2673
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:483
llvm::AMDGPUMachineFunction::isEntryFunction
bool isEntryFunction() const
Definition: AMDGPUMachineFunction.h:86
llvm::SIRegisterInfo::isVGPR
bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2819
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::SIMachineFunctionInfo::WWMReservedRegs
SmallSetVector< Register, 8 > WWMReservedRegs
Definition: SIMachineFunctionInfo.h:483
AMDGPUInstPrinter.h
llvm::SIRegisterInfo::getBoolRC
const TargetRegisterClass * getBoolRC() const
Definition: SIRegisterInfo.h:320
llvm::MachineRegisterInfo::isAllocatable
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
Definition: MachineRegisterInfo.h:943
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SIMachineFunctionInfo::SpilledReg::Lane
int Lane
Definition: SIMachineFunctionInfo.h:456
llvm::SIRegisterInfo::getRegSplitParts
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
Definition: SIRegisterInfo.cpp:2798
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:656
llvm::SIMachineFunctionInfo::getScavengeFI
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:467
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::GCNSubtarget::hasGFX90AInsts
bool hasGFX90AInsts() const
Definition: GCNSubtarget.h:1012
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::SIMachineFunctionInfo::addToSpilledSGPRs
void addToSpilledSGPRs(unsigned num)
Definition: SIMachineFunctionInfo.h:848
llvm::SIRegisterInfo::getAllAGPRRegMask
const uint32_t * getAllAGPRRegMask() const
Definition: SIRegisterInfo.cpp:517
llvm::RegScavenger::assignRegToScavengingIndex
void assignRegToScavengingIndex(int FI, Register Reg, MachineInstr *Restore=nullptr)
Record that Reg is in use at scavenging index FI.
Definition: RegisterScavenging.h:79
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:114
llvm::MachinePointerInfo::getWithOffset
MachinePointerInfo getWithOffset(int64_t O) const
Definition: MachineMemOperand.h:78
spillVGPRtoAGPR
static MachineInstrBuilder spillVGPRtoAGPR(const GCNSubtarget &ST, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Index, unsigned Lane, unsigned ValueReg, bool IsKill)
Definition: SIRegisterInfo.cpp:1151
llvm::MachineRegisterInfo::getRegClassOrRegBank
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
Definition: MachineRegisterInfo.h:676
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::AMDGPU::getFlatScratchInstSTfromSS
LLVM_READONLY int getFlatScratchInstSTfromSS(uint16_t Opcode)
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1588
llvm::AMDGPU::CPol::SCC
@ SCC
Definition: SIDefines.h:300
llvm::SIRegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: SIRegisterInfo.cpp:431
getDebugLoc
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
Definition: MachineInstrBundle.cpp:110
llvm::SIRegisterInfo::get32BitRegister
MCPhysReg get32BitRegister(MCPhysReg Reg) const
Definition: SIRegisterInfo.cpp:3014
llvm::ArrayRef< int16_t >
llvm::SIRegisterInfo::isVectorSuperClass
bool isVectorSuperClass(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.h:198
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::SGPRSpillBuilder::NotOpc
unsigned NotOpc
Definition: SIRegisterInfo.cpp:110
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
AMDGPU.h
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm::SGPRSpillBuilder::TmpVGPR
Register TmpVGPR
Definition: SIRegisterInfo.cpp:90
llvm::SIRegisterInfo::isProperlyAlignedRC
bool isProperlyAlignedRC(const TargetRegisterClass &RC) const
Definition: SIRegisterInfo.cpp:3031
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::AMDGPUInstPrinter::getRegisterName
static const char * getRegisterName(unsigned RegNo)
getNumSubRegsForSpillOp
static unsigned getNumSubRegsForSpillOp(unsigned Op)
Definition: SIRegisterInfo.cpp:938
llvm::SGPRSpillBuilder::TmpVGPRLive
bool TmpVGPRLive
Definition: SIRegisterInfo.cpp:94
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:868
uint32_t
llvm::SGPRSpillBuilder::prepare
void prepare()
Definition: SIRegisterInfo.cpp:165
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SIMachineFunctionInfo::getVGPRToAGPRSpill
MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const
Definition: SIMachineFunctionInfo.h:572
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
SubRegFromChannelTableWidthMap
static const std::array< unsigned, 17 > SubRegFromChannelTableWidthMap
Definition: SIRegisterInfo.cpp:45
llvm::SIRegisterInfo::getCalleeSavedRegsViaCopy
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
Definition: SIRegisterInfo.cpp:411
llvm::SIMachineFunctionInfo::getScratchRSrcReg
Register getScratchRSrcReg() const
Returns the physical register reserved for use as the resource descriptor for scratch accesses.
Definition: SIMachineFunctionInfo.h:769
llvm::once_flag
std::once_flag once_flag
Definition: Threading.h:57
llvm::SIInstrInfo::isMUBUF
static bool isMUBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:466
llvm::SIRegisterInfo::resolveFrameIndex
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:857
llvm::SIRegisterInfo::buildSpillLoadStore
void buildSpillLoadStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LivePhysRegs *LiveRegs=nullptr) const
Definition: SIRegisterInfo.cpp:1270
llvm::SGPRSpillBuilder::Index
int Index
Definition: SIRegisterInfo.cpp:98
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
llvm::SGPRSpillBuilder
Definition: SIRegisterInfo.cpp:72
llvm::SGPRSpillBuilder::MBB
MachineBasicBlock * MBB
Definition: SIRegisterInfo.cpp:102
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:133
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::PointerUnion
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
Definition: PointerUnion.h:112
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::GCNSubtarget::hasFlatScratchSTMode
bool hasFlatScratchSTMode() const
Definition: GCNSubtarget.h:568
llvm::SIRegisterInfo::getRegPressureSetLimit
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
Definition: SIRegisterInfo.cpp:2874
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:605
llvm::SIInstrInfo::isLegalMUBUFImmOffset
static bool isLegalMUBUFImmOffset(unsigned Imm)
Definition: SIInstrInfo.h:1101
llvm::SIRegisterInfo::getAllSGPR32
ArrayRef< MCPhysReg > getAllSGPR32(const MachineFunction &MF) const
Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:3091
llvm::SIRegisterInfo::getRegClassForTypeOnBank
const TargetRegisterClass * getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const
Definition: SIRegisterInfo.h:312
getRegClass
static const TargetRegisterClass * getRegClass(const MachineInstr &MI, Register Reg)
Definition: AArch64InstrInfo.cpp:3155
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::SGPRSpillBuilder::RS
RegScavenger * RS
Definition: SIRegisterInfo.cpp:101
llvm::commonAlignment
Align commonAlignment(Align A, Align B)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:211
llvm::AMDGPU::OPERAND_SRC_LAST
@ OPERAND_SRC_LAST
Definition: SIDefines.h:198
llvm::MachineRegisterInfo::getMaxLaneMaskForVReg
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Definition: MachineRegisterInfo.cpp:489
llvm::call_once
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:87
llvm::SIInstrFlags::FlatScratch
@ FlatScratch
Definition: SIDefines.h:120
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
llvm::SGPRSpillBuilder::PerVGPRData::NumVGPRs
unsigned NumVGPRs
Definition: SIRegisterInfo.cpp:75
uint16_t
llvm::SGPRSpillBuilder::MI
MachineBasicBlock::iterator MI
Definition: SIRegisterInfo.cpp:81
llvm::SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, LiveIntervals *LIS=nullptr) const
Special case of eliminateFrameIndex.
Definition: SIRegisterInfo.cpp:1942
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:341
AMDGPUGenRegisterInfo
llvm::MachineInstr::setAsmPrinterFlag
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:317
MachineFrameInfo.h
llvm::SIMachineFunctionInfo::SpilledReg::VGPR
Register VGPR
Definition: SIMachineFunctionInfo.h:455
getAnyVectorSuperClassForBitWidth
static const TargetRegisterClass * getAnyVectorSuperClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:2516
llvm::RegScavenger::setRegUsed
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
Definition: RegisterScavenging.cpp:51
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::SIRegisterInfo::spillSGPR
bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false) const
If OnlyToVGPR is true, this will only succeed if this.
Definition: SIRegisterInfo.cpp:1669
llvm::AMDGPUAS::PRIVATE_ADDRESS
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:364
llvm::SGPRSpillBuilder::readWriteTmpVGPR
void readWriteTmpVGPR(unsigned Offset, bool IsLoad)
Definition: SIRegisterInfo.cpp:287
llvm::SIMachineFunctionInfo::getAGPRSpillVGPRs
ArrayRef< MCPhysReg > getAGPRSpillVGPRs() const
Definition: SIMachineFunctionInfo.h:564
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::VNInfo
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
llvm::LiveRange::getVNInfoAt
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:421
llvm::TargetRegisterClass::MC
const MCRegisterClass * MC
Definition: TargetRegisterInfo.h:52
llvm::TargetStackID::SGPRSpill
@ SGPRSpill
Definition: TargetFrameLowering.h:29
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:135
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:432
llvm::RegState::ImplicitKill
@ ImplicitKill
Definition: MachineInstrBuilder.h:64
llvm::SGPRSpillBuilder::SuperReg
Register SuperReg
Definition: SIRegisterInfo.cpp:80
llvm::AMDGPU::OPERAND_REG_IMM_FIRST
@ OPERAND_REG_IMM_FIRST
Definition: SIDefines.h:188
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::SGPRSpillBuilder::MFI
SIMachineFunctionInfo & MFI
Definition: SIRegisterInfo.cpp:104
llvm::SIInstrInfo
Definition: SIInstrInfo.h:43
llvm::GCNSubtarget::enableFlatScratch
bool enableFlatScratch() const
Definition: GCNSubtarget.h:578
llvm::AMDGPU::isInlinableLiteral32
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:2014
llvm::SIRegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
Definition: SIRegisterInfo.cpp:738
llvm::SIRegisterInfo::getConstrainedRegClassForOperand
const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
Definition: SIRegisterInfo.cpp:2922
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:680
llvm::SGPRSpillBuilder::restore
void restore()
Definition: SIRegisterInfo.cpp:246
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::SGPRSpillBuilder::DL
const DebugLoc & DL
Definition: SIRegisterInfo.cpp:85
llvm::GCNSubtarget::getConstantBusLimit
unsigned getConstantBusLimit(unsigned Opcode) const
Definition: AMDGPUSubtarget.cpp:180
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:277
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:740
llvm::SGPRSpillBuilder::PerVGPRData::PerVGPR
unsigned PerVGPR
Definition: SIRegisterInfo.cpp:74
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::Register::isValid
bool isValid() const
Definition: Register.h:126
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:53
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:348
llvm::LiveInterval::hasSubRanges
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:803
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::SIRegisterInfo::findUnusedRegister
MCRegister findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const
Returns a lowest register that is not used at any point in the function.
Definition: SIRegisterInfo.cpp:2782
llvm::SGPRSpillBuilder::MovOpc
unsigned MovOpc
Definition: SIRegisterInfo.cpp:109
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SIRegisterInfo::getCompatibleSubRegClass
const TargetRegisterClass * getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const
Returns a register class which is compatible with SuperRC, such that a subregister exists with class ...
Definition: SIRegisterInfo.cpp:2730
llvm::SIRegisterInfo::getAGPRClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getAGPRClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:2506
llvm::TargetRegisterClass::hasSubClassEq
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition: TargetRegisterInfo.h:127
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FIRST
@ OPERAND_REG_INLINE_AC_FIRST
Definition: SIDefines.h:194
getOffsetMUBUFLoad
static int getOffsetMUBUFLoad(unsigned Opc)
Definition: SIRegisterInfo.cpp:1058
llvm::SIMachineFunctionInfo::addToSpilledVGPRs
void addToSpilledVGPRs(unsigned num)
Definition: SIMachineFunctionInfo.h:852
llvm::SGPRSpillBuilder::MF
MachineFunction & MF
Definition: SIRegisterInfo.cpp:103
getAnyAGPRClassForBitWidth
static const TargetRegisterClass * getAnyAGPRClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:2458
llvm::LiveIntervals::hasInterval
bool hasInterval(Register Reg) const
Definition: LiveIntervals.h:125
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:405
llvm::SIRegisterInfo::opCanUseInlineConstant
bool opCanUseInlineConstant(unsigned OpType) const
Definition: SIRegisterInfo.cpp:2739
llvm::SIRegisterInfo::shouldCoalesce
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
Definition: SIRegisterInfo.cpp:2834
RegisterScavenging.h
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:51
llvm::SGPRSpillBuilder::SGPRSpillBuilder
SGPRSpillBuilder(const SIRegisterInfo &TRI, const SIInstrInfo &TII, bool IsWave32, MachineBasicBlock::iterator MI, int Index, RegScavenger *RS)
Definition: SIRegisterInfo.cpp:112
llvm::AMDGPUSubtarget::getWavefrontSizeLog2
unsigned getWavefrontSizeLog2() const
Definition: AMDGPUSubtarget.h:204
llvm::SIRegisterInfo::spillEmergencySGPR
bool spillEmergencySGPR(MachineBasicBlock::iterator MI, MachineBasicBlock &RestoreMBB, Register SGPR, RegScavenger *RS) const
Definition: SIRegisterInfo.cpp:1870
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::SIMachineFunctionInfo::getSGPRToVGPRSpills
ArrayRef< SpilledReg > getSGPRToVGPRSpills(int FrameIndex) const
Definition: SIMachineFunctionInfo.h:556
getFlatScratchSpillOpcode
static unsigned getFlatScratchSpillOpcode(const SIInstrInfo *TII, unsigned LoadStoreOp, unsigned EltSize)
Definition: SIRegisterInfo.cpp:1232
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:218
llvm::SIRegisterInfo::getEquivalentSGPRClass
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
Definition: SIRegisterInfo.cpp:2700
SIRegisterInfo.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:279
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::SIRegisterInfo::reservedPrivateSegmentBufferReg
MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed.
Definition: SIRegisterInfo.cpp:538
llvm::SIRegisterInfo::getPhysRegClass
const TargetRegisterClass * getPhysRegClass(MCRegister Reg) const
Return the 'base' register class for this register.
Definition: SIRegisterInfo.cpp:2605
llvm::SIRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:545
llvm::SIMachineFunctionInfo::getFrameOffsetReg
Register getFrameOffsetReg() const
Definition: SIMachineFunctionInfo.h:778
llvm::SIRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: SIRegisterInfo.cpp:922
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
EnableSpillSGPRToVGPR
static cl::opt< bool > EnableSpillSGPRToVGPR("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling VGPRs to SGPRs"), cl::ReallyHidden, cl::init(true))
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
llvm::LiveIntervals::getRegUnit
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
Definition: LiveIntervals.h:393
llvm::GCNSubtarget::hasMAIInsts
bool hasMAIInsts() const
Definition: GCNSubtarget.h:712
MachineDominators.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::SIRegisterInfo::getSGPRClassForBitWidth
static const LLVM_READONLY TargetRegisterClass * getSGPRClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:2575
LivePhysRegs.h
llvm::LiveInterval::subranges
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:775