29#define GET_REGINFO_TARGET_DESC
30#include "AMDGPUGenRegisterInfo.inc"
33 "amdgpu-spill-sgpr-to-vgpr",
34 cl::desc(
"Enable spilling SGPRs to VGPRs"),
38std::array<std::vector<int16_t>, 16> SIRegisterInfo::RegSplitParts;
39std::array<std::array<uint16_t, 32>, 9> SIRegisterInfo::SubRegFromChannelTable;
46 0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 9};
116 MI->getOperand(0).isKill(),
Index,
RS) {}
131 MovOpc = AMDGPU::S_MOV_B32;
132 NotOpc = AMDGPU::S_NOT_B32;
135 MovOpc = AMDGPU::S_MOV_B64;
136 NotOpc = AMDGPU::S_NOT_B64;
141 SuperReg != AMDGPU::EXEC &&
"exec should never spill");
172 assert(
RS &&
"Cannot spill SGPR to memory without RegScavenger");
201 IsWave32 ? AMDGPU::SGPR_32RegClass : AMDGPU::SGPR_64RegClass;
222 MI->emitError(
"unhandled SGPR spill to memory");
232 I->getOperand(2).setIsDead();
267 I->getOperand(2).setIsDead();
297 MI->emitError(
"unhandled SGPR spill to memory");
322 ST.getAMDGPUDwarfFlavour()),
325 assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 &&
326 getSubRegIndexLaneMask(AMDGPU::sub31).getAsInteger() == (3ULL << 62) &&
327 (getSubRegIndexLaneMask(AMDGPU::lo16) |
328 getSubRegIndexLaneMask(AMDGPU::hi16)).getAsInteger() ==
329 getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() &&
330 "getNumCoveredRegs() will not work with generated subreg masks!");
332 RegPressureIgnoredUnits.
resize(getNumRegUnits());
334 for (
auto Reg : AMDGPU::VGPR_16RegClass) {
336 RegPressureIgnoredUnits.
set(*regunits(Reg).begin());
342 static auto InitializeRegSplitPartsOnce = [
this]() {
343 for (
unsigned Idx = 1, E = getNumSubRegIndices() - 1;
Idx < E; ++
Idx) {
344 unsigned Size = getSubRegIdxSize(
Idx);
347 std::vector<int16_t> &Vec = RegSplitParts[
Size / 32 - 1];
348 unsigned Pos = getSubRegIdxOffset(
Idx);
353 unsigned MaxNumParts = 1024 /
Size;
354 Vec.resize(MaxNumParts);
362 static auto InitializeSubRegFromChannelTableOnce = [
this]() {
363 for (
auto &Row : SubRegFromChannelTable)
364 Row.fill(AMDGPU::NoSubRegister);
365 for (
unsigned Idx = 1;
Idx < getNumSubRegIndices(); ++
Idx) {
366 unsigned Width = getSubRegIdxSize(
Idx) / 32;
367 unsigned Offset = getSubRegIdxOffset(
Idx) / 32;
372 unsigned TableIdx = Width - 1;
373 assert(TableIdx < SubRegFromChannelTable.size());
375 SubRegFromChannelTable[TableIdx][
Offset] =
Idx;
379 llvm::call_once(InitializeRegSplitPartsFlag, InitializeRegSplitPartsOnce);
381 InitializeSubRegFromChannelTableOnce);
399 : CSR_AMDGPU_SaveList;
401 return ST.
hasGFX90AInsts() ? CSR_AMDGPU_SI_Gfx_GFX90AInsts_SaveList
402 : CSR_AMDGPU_SI_Gfx_SaveList;
404 return CSR_AMDGPU_CS_ChainPreserve_SaveList;
407 static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
408 return &NoCalleeSavedReg;
425 : CSR_AMDGPU_RegMask;
427 return ST.
hasGFX90AInsts() ? CSR_AMDGPU_SI_Gfx_GFX90AInsts_RegMask
428 : CSR_AMDGPU_SI_Gfx_RegMask;
433 return AMDGPU_AllVGPRs_RegMask;
440 return CSR_AMDGPU_NoRegs_RegMask;
444 return VGPR >= AMDGPU::VGPR0 && VGPR < AMDGPU::VGPR8;
455 if (RC == &AMDGPU::VGPR_32RegClass || RC == &AMDGPU::AGPR_32RegClass)
456 return &AMDGPU::AV_32RegClass;
457 if (RC == &AMDGPU::VReg_64RegClass || RC == &AMDGPU::AReg_64RegClass)
458 return &AMDGPU::AV_64RegClass;
459 if (RC == &AMDGPU::VReg_64_Align2RegClass ||
460 RC == &AMDGPU::AReg_64_Align2RegClass)
461 return &AMDGPU::AV_64_Align2RegClass;
462 if (RC == &AMDGPU::VReg_96RegClass || RC == &AMDGPU::AReg_96RegClass)
463 return &AMDGPU::AV_96RegClass;
464 if (RC == &AMDGPU::VReg_96_Align2RegClass ||
465 RC == &AMDGPU::AReg_96_Align2RegClass)
466 return &AMDGPU::AV_96_Align2RegClass;
467 if (RC == &AMDGPU::VReg_128RegClass || RC == &AMDGPU::AReg_128RegClass)
468 return &AMDGPU::AV_128RegClass;
469 if (RC == &AMDGPU::VReg_128_Align2RegClass ||
470 RC == &AMDGPU::AReg_128_Align2RegClass)
471 return &AMDGPU::AV_128_Align2RegClass;
472 if (RC == &AMDGPU::VReg_160RegClass || RC == &AMDGPU::AReg_160RegClass)
473 return &AMDGPU::AV_160RegClass;
474 if (RC == &AMDGPU::VReg_160_Align2RegClass ||
475 RC == &AMDGPU::AReg_160_Align2RegClass)
476 return &AMDGPU::AV_160_Align2RegClass;
477 if (RC == &AMDGPU::VReg_192RegClass || RC == &AMDGPU::AReg_192RegClass)
478 return &AMDGPU::AV_192RegClass;
479 if (RC == &AMDGPU::VReg_192_Align2RegClass ||
480 RC == &AMDGPU::AReg_192_Align2RegClass)
481 return &AMDGPU::AV_192_Align2RegClass;
482 if (RC == &AMDGPU::VReg_256RegClass || RC == &AMDGPU::AReg_256RegClass)
483 return &AMDGPU::AV_256RegClass;
484 if (RC == &AMDGPU::VReg_256_Align2RegClass ||
485 RC == &AMDGPU::AReg_256_Align2RegClass)
486 return &AMDGPU::AV_256_Align2RegClass;
487 if (RC == &AMDGPU::VReg_512RegClass || RC == &AMDGPU::AReg_512RegClass)
488 return &AMDGPU::AV_512RegClass;
489 if (RC == &AMDGPU::VReg_512_Align2RegClass ||
490 RC == &AMDGPU::AReg_512_Align2RegClass)
491 return &AMDGPU::AV_512_Align2RegClass;
492 if (RC == &AMDGPU::VReg_1024RegClass || RC == &AMDGPU::AReg_1024RegClass)
493 return &AMDGPU::AV_1024RegClass;
494 if (RC == &AMDGPU::VReg_1024_Align2RegClass ||
495 RC == &AMDGPU::AReg_1024_Align2RegClass)
496 return &AMDGPU::AV_1024_Align2RegClass;
526 return AMDGPU_AllVGPRs_RegMask;
530 return AMDGPU_AllAGPRs_RegMask;
534 return AMDGPU_AllVectorRegs_RegMask;
538 return AMDGPU_AllAllocatableSRegs_RegMask;
545 assert(NumRegIndex &&
"Not implemented");
546 assert(Channel < SubRegFromChannelTable[NumRegIndex - 1].
size());
547 return SubRegFromChannelTable[NumRegIndex - 1][Channel];
552 const unsigned Align,
555 MCRegister BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx));
556 return getMatchingSuperReg(BaseReg, AMDGPU::sub0, RC);
574 reserveRegisterTuples(
Reserved, AMDGPU::EXEC);
575 reserveRegisterTuples(
Reserved, AMDGPU::FLAT_SCR);
578 reserveRegisterTuples(
Reserved, AMDGPU::M0);
581 reserveRegisterTuples(
Reserved, AMDGPU::SRC_VCCZ);
582 reserveRegisterTuples(
Reserved, AMDGPU::SRC_EXECZ);
583 reserveRegisterTuples(
Reserved, AMDGPU::SRC_SCC);
586 reserveRegisterTuples(
Reserved, AMDGPU::SRC_SHARED_BASE);
587 reserveRegisterTuples(
Reserved, AMDGPU::SRC_SHARED_LIMIT);
588 reserveRegisterTuples(
Reserved, AMDGPU::SRC_PRIVATE_BASE);
589 reserveRegisterTuples(
Reserved, AMDGPU::SRC_PRIVATE_LIMIT);
592 reserveRegisterTuples(
Reserved, AMDGPU::SRC_POPS_EXITING_WAVE_ID);
595 reserveRegisterTuples(
Reserved, AMDGPU::XNACK_MASK);
598 reserveRegisterTuples(
Reserved, AMDGPU::LDS_DIRECT);
601 reserveRegisterTuples(
Reserved, AMDGPU::TBA);
602 reserveRegisterTuples(
Reserved, AMDGPU::TMA);
603 reserveRegisterTuples(
Reserved, AMDGPU::TTMP0_TTMP1);
604 reserveRegisterTuples(
Reserved, AMDGPU::TTMP2_TTMP3);
605 reserveRegisterTuples(
Reserved, AMDGPU::TTMP4_TTMP5);
606 reserveRegisterTuples(
Reserved, AMDGPU::TTMP6_TTMP7);
607 reserveRegisterTuples(
Reserved, AMDGPU::TTMP8_TTMP9);
608 reserveRegisterTuples(
Reserved, AMDGPU::TTMP10_TTMP11);
609 reserveRegisterTuples(
Reserved, AMDGPU::TTMP12_TTMP13);
610 reserveRegisterTuples(
Reserved, AMDGPU::TTMP14_TTMP15);
613 reserveRegisterTuples(
Reserved, AMDGPU::SGPR_NULL64);
618 unsigned TotalNumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
621 unsigned NumRegs =
divideCeil(getRegSizeInBits(*RC), 32);
624 if (
Index + NumRegs > MaxNumSGPRs &&
Index < TotalNumSGPRs)
631 if (ScratchRSrcReg != AMDGPU::NoRegister) {
635 reserveRegisterTuples(
Reserved, ScratchRSrcReg);
639 if (LongBranchReservedReg)
640 reserveRegisterTuples(
Reserved, LongBranchReservedReg);
647 reserveRegisterTuples(
Reserved, StackPtrReg);
648 assert(!isSubRegister(ScratchRSrcReg, StackPtrReg));
653 reserveRegisterTuples(
Reserved, FrameReg);
654 assert(!isSubRegister(ScratchRSrcReg, FrameReg));
659 reserveRegisterTuples(
Reserved, BasePtrReg);
660 assert(!isSubRegister(ScratchRSrcReg, BasePtrReg));
667 reserveRegisterTuples(
Reserved, ExecCopyReg);
672 unsigned MaxNumAGPRs = MaxNumVGPRs;
673 unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs();
686 MaxNumAGPRs = MaxNumVGPRs;
688 if (MaxNumVGPRs > TotalNumVGPRs) {
689 MaxNumAGPRs = MaxNumVGPRs - TotalNumVGPRs;
690 MaxNumVGPRs = TotalNumVGPRs;
698 unsigned NumRegs =
divideCeil(getRegSizeInBits(*RC), 32);
701 if (
Index + NumRegs > MaxNumVGPRs)
712 unsigned NumRegs =
divideCeil(getRegSizeInBits(*RC), 32);
715 if (
Index + NumRegs > MaxNumAGPRs)
728 reserveRegisterTuples(
Reserved, Reg);
732 reserveRegisterTuples(
Reserved, Reg);
735 reserveRegisterTuples(
Reserved, Reg);
752 if (
Info->isBottomOfStack())
760 if (
Info->isEntryFunction()) {
794 AMDGPU::OpName::offset);
795 return MI->getOperand(OffIdx).getImm();
804 AMDGPU::OpName::vaddr) ||
806 AMDGPU::OpName::saddr))) &&
807 "Should never see frame index on non-address operand");
820 return !
TII->isLegalMUBUFImmOffset(FullOffset);
833 DL = Ins->getDebugLoc();
839 : AMDGPU::V_MOV_B32_e32;
843 : &AMDGPU::VGPR_32RegClass);
851 Register OffsetReg =
MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
855 : &AMDGPU::VGPR_32RegClass);
869 TII->getAddNoCarry(*
MBB, Ins,
DL, BaseReg)
880 bool IsFlat =
TII->isFLATScratch(
MI);
896 TII->getNamedOperand(
MI, IsFlat ? AMDGPU::OpName::saddr
897 : AMDGPU::OpName::vaddr);
902 assert(FIOp && FIOp->
isFI() &&
"frame index must be address operand");
908 "offset should be legal");
910 OffsetOp->
setImm(NewOffset);
919 assert(
TII->isLegalMUBUFImmOffset(NewOffset) &&
"offset should be legal");
922 OffsetOp->
setImm(NewOffset);
935 return TII->isLegalMUBUFImmOffset(NewOffset);
946 return &AMDGPU::VGPR_32RegClass;
953 if (RC == &AMDGPU::SCC_CLASSRegClass)
962 case AMDGPU::SI_SPILL_S1024_SAVE:
963 case AMDGPU::SI_SPILL_S1024_RESTORE:
964 case AMDGPU::SI_SPILL_V1024_SAVE:
965 case AMDGPU::SI_SPILL_V1024_RESTORE:
966 case AMDGPU::SI_SPILL_A1024_SAVE:
967 case AMDGPU::SI_SPILL_A1024_RESTORE:
968 case AMDGPU::SI_SPILL_AV1024_SAVE:
969 case AMDGPU::SI_SPILL_AV1024_RESTORE:
971 case AMDGPU::SI_SPILL_S512_SAVE:
972 case AMDGPU::SI_SPILL_S512_RESTORE:
973 case AMDGPU::SI_SPILL_V512_SAVE:
974 case AMDGPU::SI_SPILL_V512_RESTORE:
975 case AMDGPU::SI_SPILL_A512_SAVE:
976 case AMDGPU::SI_SPILL_A512_RESTORE:
977 case AMDGPU::SI_SPILL_AV512_SAVE:
978 case AMDGPU::SI_SPILL_AV512_RESTORE:
980 case AMDGPU::SI_SPILL_S384_SAVE:
981 case AMDGPU::SI_SPILL_S384_RESTORE:
982 case AMDGPU::SI_SPILL_V384_SAVE:
983 case AMDGPU::SI_SPILL_V384_RESTORE:
984 case AMDGPU::SI_SPILL_A384_SAVE:
985 case AMDGPU::SI_SPILL_A384_RESTORE:
986 case AMDGPU::SI_SPILL_AV384_SAVE:
987 case AMDGPU::SI_SPILL_AV384_RESTORE:
989 case AMDGPU::SI_SPILL_S352_SAVE:
990 case AMDGPU::SI_SPILL_S352_RESTORE:
991 case AMDGPU::SI_SPILL_V352_SAVE:
992 case AMDGPU::SI_SPILL_V352_RESTORE:
993 case AMDGPU::SI_SPILL_A352_SAVE:
994 case AMDGPU::SI_SPILL_A352_RESTORE:
995 case AMDGPU::SI_SPILL_AV352_SAVE:
996 case AMDGPU::SI_SPILL_AV352_RESTORE:
998 case AMDGPU::SI_SPILL_S320_SAVE:
999 case AMDGPU::SI_SPILL_S320_RESTORE:
1000 case AMDGPU::SI_SPILL_V320_SAVE:
1001 case AMDGPU::SI_SPILL_V320_RESTORE:
1002 case AMDGPU::SI_SPILL_A320_SAVE:
1003 case AMDGPU::SI_SPILL_A320_RESTORE:
1004 case AMDGPU::SI_SPILL_AV320_SAVE:
1005 case AMDGPU::SI_SPILL_AV320_RESTORE:
1007 case AMDGPU::SI_SPILL_S288_SAVE:
1008 case AMDGPU::SI_SPILL_S288_RESTORE:
1009 case AMDGPU::SI_SPILL_V288_SAVE:
1010 case AMDGPU::SI_SPILL_V288_RESTORE:
1011 case AMDGPU::SI_SPILL_A288_SAVE:
1012 case AMDGPU::SI_SPILL_A288_RESTORE:
1013 case AMDGPU::SI_SPILL_AV288_SAVE:
1014 case AMDGPU::SI_SPILL_AV288_RESTORE:
1016 case AMDGPU::SI_SPILL_S256_SAVE:
1017 case AMDGPU::SI_SPILL_S256_RESTORE:
1018 case AMDGPU::SI_SPILL_V256_SAVE:
1019 case AMDGPU::SI_SPILL_V256_RESTORE:
1020 case AMDGPU::SI_SPILL_A256_SAVE:
1021 case AMDGPU::SI_SPILL_A256_RESTORE:
1022 case AMDGPU::SI_SPILL_AV256_SAVE:
1023 case AMDGPU::SI_SPILL_AV256_RESTORE:
1025 case AMDGPU::SI_SPILL_S224_SAVE:
1026 case AMDGPU::SI_SPILL_S224_RESTORE:
1027 case AMDGPU::SI_SPILL_V224_SAVE:
1028 case AMDGPU::SI_SPILL_V224_RESTORE:
1029 case AMDGPU::SI_SPILL_A224_SAVE:
1030 case AMDGPU::SI_SPILL_A224_RESTORE:
1031 case AMDGPU::SI_SPILL_AV224_SAVE:
1032 case AMDGPU::SI_SPILL_AV224_RESTORE:
1034 case AMDGPU::SI_SPILL_S192_SAVE:
1035 case AMDGPU::SI_SPILL_S192_RESTORE:
1036 case AMDGPU::SI_SPILL_V192_SAVE:
1037 case AMDGPU::SI_SPILL_V192_RESTORE:
1038 case AMDGPU::SI_SPILL_A192_SAVE:
1039 case AMDGPU::SI_SPILL_A192_RESTORE:
1040 case AMDGPU::SI_SPILL_AV192_SAVE:
1041 case AMDGPU::SI_SPILL_AV192_RESTORE:
1043 case AMDGPU::SI_SPILL_S160_SAVE:
1044 case AMDGPU::SI_SPILL_S160_RESTORE:
1045 case AMDGPU::SI_SPILL_V160_SAVE:
1046 case AMDGPU::SI_SPILL_V160_RESTORE:
1047 case AMDGPU::SI_SPILL_A160_SAVE:
1048 case AMDGPU::SI_SPILL_A160_RESTORE:
1049 case AMDGPU::SI_SPILL_AV160_SAVE:
1050 case AMDGPU::SI_SPILL_AV160_RESTORE:
1052 case AMDGPU::SI_SPILL_S128_SAVE:
1053 case AMDGPU::SI_SPILL_S128_RESTORE:
1054 case AMDGPU::SI_SPILL_V128_SAVE:
1055 case AMDGPU::SI_SPILL_V128_RESTORE:
1056 case AMDGPU::SI_SPILL_A128_SAVE:
1057 case AMDGPU::SI_SPILL_A128_RESTORE:
1058 case AMDGPU::SI_SPILL_AV128_SAVE:
1059 case AMDGPU::SI_SPILL_AV128_RESTORE:
1061 case AMDGPU::SI_SPILL_S96_SAVE:
1062 case AMDGPU::SI_SPILL_S96_RESTORE:
1063 case AMDGPU::SI_SPILL_V96_SAVE:
1064 case AMDGPU::SI_SPILL_V96_RESTORE:
1065 case AMDGPU::SI_SPILL_A96_SAVE:
1066 case AMDGPU::SI_SPILL_A96_RESTORE:
1067 case AMDGPU::SI_SPILL_AV96_SAVE:
1068 case AMDGPU::SI_SPILL_AV96_RESTORE:
1070 case AMDGPU::SI_SPILL_S64_SAVE:
1071 case AMDGPU::SI_SPILL_S64_RESTORE:
1072 case AMDGPU::SI_SPILL_V64_SAVE:
1073 case AMDGPU::SI_SPILL_V64_RESTORE:
1074 case AMDGPU::SI_SPILL_A64_SAVE:
1075 case AMDGPU::SI_SPILL_A64_RESTORE:
1076 case AMDGPU::SI_SPILL_AV64_SAVE:
1077 case AMDGPU::SI_SPILL_AV64_RESTORE:
1079 case AMDGPU::SI_SPILL_S32_SAVE:
1080 case AMDGPU::SI_SPILL_S32_RESTORE:
1081 case AMDGPU::SI_SPILL_V32_SAVE:
1082 case AMDGPU::SI_SPILL_V32_RESTORE:
1083 case AMDGPU::SI_SPILL_A32_SAVE:
1084 case AMDGPU::SI_SPILL_A32_RESTORE:
1085 case AMDGPU::SI_SPILL_AV32_SAVE:
1086 case AMDGPU::SI_SPILL_AV32_RESTORE:
1087 case AMDGPU::SI_SPILL_WWM_V32_SAVE:
1088 case AMDGPU::SI_SPILL_WWM_V32_RESTORE:
1089 case AMDGPU::SI_SPILL_WWM_AV32_SAVE:
1090 case AMDGPU::SI_SPILL_WWM_AV32_RESTORE:
1098 case AMDGPU::BUFFER_STORE_DWORD_OFFEN:
1099 return AMDGPU::BUFFER_STORE_DWORD_OFFSET;
1100 case AMDGPU::BUFFER_STORE_BYTE_OFFEN:
1101 return AMDGPU::BUFFER_STORE_BYTE_OFFSET;
1102 case AMDGPU::BUFFER_STORE_SHORT_OFFEN:
1103 return AMDGPU::BUFFER_STORE_SHORT_OFFSET;
1104 case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN:
1105 return AMDGPU::BUFFER_STORE_DWORDX2_OFFSET;
1106 case AMDGPU::BUFFER_STORE_DWORDX3_OFFEN:
1107 return AMDGPU::BUFFER_STORE_DWORDX3_OFFSET;
1108 case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN:
1109 return AMDGPU::BUFFER_STORE_DWORDX4_OFFSET;
1110 case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN:
1111 return AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET;
1112 case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN:
1113 return AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET;
1121 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN:
1122 return AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
1123 case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN:
1124 return AMDGPU::BUFFER_LOAD_UBYTE_OFFSET;
1125 case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN:
1126 return AMDGPU::BUFFER_LOAD_SBYTE_OFFSET;
1127 case AMDGPU::BUFFER_LOAD_USHORT_OFFEN:
1128 return AMDGPU::BUFFER_LOAD_USHORT_OFFSET;
1129 case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN:
1130 return AMDGPU::BUFFER_LOAD_SSHORT_OFFSET;
1131 case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN:
1132 return AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET;
1133 case AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN:
1134 return AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET;
1135 case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN:
1136 return AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET;
1137 case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN:
1138 return AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET;
1139 case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN:
1140 return AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET;
1141 case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN:
1142 return AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET;
1143 case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN:
1144 return AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET;
1145 case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN:
1146 return AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET;
1147 case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN:
1148 return AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET;
1156 case AMDGPU::BUFFER_STORE_DWORD_OFFSET:
1157 return AMDGPU::BUFFER_STORE_DWORD_OFFEN;
1158 case AMDGPU::BUFFER_STORE_BYTE_OFFSET:
1159 return AMDGPU::BUFFER_STORE_BYTE_OFFEN;
1160 case AMDGPU::BUFFER_STORE_SHORT_OFFSET:
1161 return AMDGPU::BUFFER_STORE_SHORT_OFFEN;
1162 case AMDGPU::BUFFER_STORE_DWORDX2_OFFSET:
1163 return AMDGPU::BUFFER_STORE_DWORDX2_OFFEN;
1164 case AMDGPU::BUFFER_STORE_DWORDX3_OFFSET:
1165 return AMDGPU::BUFFER_STORE_DWORDX3_OFFEN;
1166 case AMDGPU::BUFFER_STORE_DWORDX4_OFFSET:
1167 return AMDGPU::BUFFER_STORE_DWORDX4_OFFEN;
1168 case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET:
1169 return AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN;
1170 case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET:
1171 return AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN;
1179 case AMDGPU::BUFFER_LOAD_DWORD_OFFSET:
1180 return AMDGPU::BUFFER_LOAD_DWORD_OFFEN;
1181 case AMDGPU::BUFFER_LOAD_UBYTE_OFFSET:
1182 return AMDGPU::BUFFER_LOAD_UBYTE_OFFEN;
1183 case AMDGPU::BUFFER_LOAD_SBYTE_OFFSET:
1184 return AMDGPU::BUFFER_LOAD_SBYTE_OFFEN;
1185 case AMDGPU::BUFFER_LOAD_USHORT_OFFSET:
1186 return AMDGPU::BUFFER_LOAD_USHORT_OFFEN;
1187 case AMDGPU::BUFFER_LOAD_SSHORT_OFFSET:
1188 return AMDGPU::BUFFER_LOAD_SSHORT_OFFEN;
1189 case AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET:
1190 return AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN;
1191 case AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET:
1192 return AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN;
1193 case AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET:
1194 return AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN;
1195 case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET:
1196 return AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN;
1197 case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET:
1198 return AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN;
1199 case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET:
1200 return AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN;
1201 case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET:
1202 return AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN;
1203 case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET:
1204 return AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN;
1205 case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET:
1206 return AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN;
1215 int Index,
unsigned Lane,
1216 unsigned ValueReg,
bool IsKill) {
1223 if (Reg == AMDGPU::NoRegister)
1226 bool IsStore =
MI->mayStore();
1230 unsigned Dst = IsStore ? Reg : ValueReg;
1231 unsigned Src = IsStore ? ValueReg : Reg;
1232 bool IsVGPR =
TRI->isVGPR(
MRI, Reg);
1234 if (IsVGPR ==
TRI->isVGPR(
MRI, ValueReg)) {
1244 unsigned Opc = (IsStore ^ IsVGPR) ? AMDGPU::V_ACCVGPR_WRITE_B32_e64
1245 : AMDGPU::V_ACCVGPR_READ_B32_e64;
1263 bool IsStore =
MI->mayStore();
1265 unsigned Opc =
MI->getOpcode();
1266 int LoadStoreOp = IsStore ?
1268 if (LoadStoreOp == -1)
1278 .
add(*
TII->getNamedOperand(*
MI, AMDGPU::OpName::srsrc))
1279 .
add(*
TII->getNamedOperand(*
MI, AMDGPU::OpName::soffset))
1286 AMDGPU::OpName::vdata_in);
1288 NewMI.
add(*VDataIn);
1293 unsigned LoadStoreOp,
1295 bool IsStore =
TII->get(LoadStoreOp).mayStore();
1302 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
1303 : AMDGPU::SCRATCH_LOAD_DWORD_SADDR;
1306 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX2_SADDR
1307 : AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR;
1310 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX3_SADDR
1311 : AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR;
1314 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX4_SADDR
1315 : AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR;
1331 unsigned LoadStoreOp,
int Index,
Register ValueReg,
bool IsKill,
1334 assert((!RS || !LiveUnits) &&
"Only RS or LiveUnits can be set but not both");
1342 bool IsStore =
Desc->mayStore();
1343 bool IsFlat =
TII->isFLATScratch(LoadStoreOp);
1345 bool CanClobberSCC =
false;
1346 bool Scavenged =
false;
1356 unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u;
1357 unsigned NumSubRegs = RegWidth / EltSize;
1358 unsigned Size = NumSubRegs * EltSize;
1359 unsigned RemSize = RegWidth -
Size;
1360 unsigned NumRemSubRegs = RemSize ? 1 : 0;
1362 int64_t MaterializedOffset =
Offset;
1364 int64_t MaxOffset =
Offset +
Size + RemSize - EltSize;
1365 int64_t ScratchOffsetRegDelta = 0;
1367 if (IsFlat && EltSize > 4) {
1369 Desc = &
TII->get(LoadStoreOp);
1376 "unexpected VGPR spill offset");
1383 bool UseVGPROffset =
false;
1390 if (IsFlat && SGPRBase) {
1414 bool IsOffsetLegal =
1417 :
TII->isLegalMUBUFImmOffset(MaxOffset);
1429 CanClobberSCC = !RS->
isRegUsed(AMDGPU::SCC);
1430 }
else if (LiveUnits) {
1431 CanClobberSCC = LiveUnits->
available(AMDGPU::SCC);
1432 for (
MCRegister Reg : AMDGPU::SGPR_32RegClass) {
1440 if (ScratchOffsetReg != AMDGPU::NoRegister && !CanClobberSCC)
1444 UseVGPROffset =
true;
1450 for (
MCRegister Reg : AMDGPU::VGPR_32RegClass) {
1452 TmpOffsetVGPR = Reg;
1459 }
else if (!SOffset && CanClobberSCC) {
1470 if (!ScratchOffsetReg)
1472 SOffset = ScratchOffsetReg;
1473 ScratchOffsetRegDelta =
Offset;
1481 if (!IsFlat && !UseVGPROffset)
1484 if (!UseVGPROffset && !SOffset)
1487 if (UseVGPROffset) {
1489 MaterializeVOffset(ScratchOffsetReg, TmpOffsetVGPR,
Offset);
1490 }
else if (ScratchOffsetReg == AMDGPU::NoRegister) {
1495 .
addReg(ScratchOffsetReg)
1497 Add->getOperand(3).setIsDead();
1503 if (IsFlat && SOffset == AMDGPU::NoRegister) {
1505 &&
"Unexpected vaddr for flat scratch with a FI operand");
1507 if (UseVGPROffset) {
1514 Desc = &
TII->get(LoadStoreOp);
1517 for (
unsigned i = 0, e = NumSubRegs + NumRemSubRegs, RegOffset = 0; i != e;
1518 ++i, RegOffset += EltSize) {
1519 if (i == NumSubRegs) {
1523 Desc = &
TII->get(LoadStoreOp);
1525 if (!IsFlat && UseVGPROffset) {
1528 Desc = &
TII->get(NewLoadStoreOp);
1531 if (UseVGPROffset && TmpOffsetVGPR == TmpIntermediateVGPR) {
1538 MaterializeVOffset(ScratchOffsetReg, TmpOffsetVGPR, MaterializedOffset);
1541 unsigned NumRegs = EltSize / 4;
1547 unsigned SOffsetRegState = 0;
1549 const bool IsLastSubReg = i + 1 == e;
1550 const bool IsFirstSubReg = i == 0;
1559 bool NeedSuperRegDef = e > 1 && IsStore && IsFirstSubReg;
1560 bool NeedSuperRegImpOperand = e > 1;
1564 unsigned RemEltSize = EltSize;
1572 for (
int LaneS = (RegOffset + EltSize) / 4 - 1, Lane = LaneS,
1573 LaneE = RegOffset / 4;
1574 Lane >= LaneE; --Lane) {
1575 bool IsSubReg = e > 1 || EltSize > 4;
1580 if (!MIB.getInstr())
1582 if (NeedSuperRegDef || (IsSubReg && IsStore && Lane == LaneS && IsFirstSubReg)) {
1584 NeedSuperRegDef =
false;
1586 if ((IsSubReg || NeedSuperRegImpOperand) && (IsFirstSubReg || IsLastSubReg)) {
1587 NeedSuperRegImpOperand =
true;
1588 unsigned State = SrcDstRegState;
1589 if (!IsLastSubReg || (Lane != LaneE))
1590 State &= ~RegState::Kill;
1591 if (!IsFirstSubReg || (Lane != LaneS))
1592 State &= ~RegState::Define;
1601 if (RemEltSize != EltSize) {
1602 assert(IsFlat && EltSize > 4);
1604 unsigned NumRegs = RemEltSize / 4;
1611 unsigned FinalReg =
SubReg;
1616 if (!TmpIntermediateVGPR) {
1622 TII->get(AMDGPU::V_ACCVGPR_READ_B32_e64),
1623 TmpIntermediateVGPR)
1625 if (NeedSuperRegDef)
1629 SubReg = TmpIntermediateVGPR;
1630 }
else if (UseVGPROffset) {
1631 if (!TmpOffsetVGPR) {
1647 if (UseVGPROffset) {
1656 if (SOffset == AMDGPU::NoRegister) {
1658 if (UseVGPROffset && ScratchOffsetReg) {
1659 MIB.
addReg(ScratchOffsetReg);
1666 MIB.addReg(SOffset, SOffsetRegState);
1669 MIB.addImm(
Offset + RegOffset);
1676 MIB.addMemOperand(NewMMO);
1678 if (!IsAGPR && NeedSuperRegDef)
1681 if (!IsStore && IsAGPR && TmpIntermediateVGPR != AMDGPU::NoRegister) {
1688 if (NeedSuperRegImpOperand && (IsFirstSubReg || IsLastSubReg))
1712 if (!IsStore &&
MI !=
MBB.
end() &&
MI->isReturn() &&
1715 MIB->tieOperands(0, MIB->getNumOperands() - 1);
1719 if (ScratchOffsetRegDelta != 0) {
1723 .
addImm(-ScratchOffsetRegDelta);
1729 bool IsKill)
const {
1747 : AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
1752 : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
1763 bool SpillToPhysVGPRLane)
const {
1769 bool SpillToVGPR = !VGPRSpills.
empty();
1770 if (OnlyToVGPR && !SpillToVGPR)
1779 "Num of VGPR lanes should be equal to num of SGPRs spilled");
1781 for (
unsigned i = 0, e = SB.
NumSubRegs; i < e; ++i) {
1788 bool IsFirstSubreg = i == 0;
1790 bool UseKill = SB.
IsKill && IsLastSubreg;
1796 SB.
TII.get(AMDGPU::SI_SPILL_S32_TO_VGPR), Spill.VGPR)
1813 if (SB.
NumSubRegs > 1 && (IsFirstSubreg || IsLastSubreg))
1833 for (
unsigned i =
Offset * PVD.PerVGPR,
1843 SB.
TII.get(AMDGPU::SI_SPILL_S32_TO_VGPR), SB.
TmpVGPR)
1860 unsigned SuperKillState = 0;
1874 MI->eraseFromParent();
1886 bool SpillToPhysVGPRLane)
const {
1892 bool SpillToVGPR = !VGPRSpills.
empty();
1893 if (OnlyToVGPR && !SpillToVGPR)
1897 for (
unsigned i = 0, e = SB.
NumSubRegs; i < e; ++i) {
1905 SB.
TII.get(AMDGPU::SI_RESTORE_S32_FROM_VGPR),
SubReg)
1928 for (
unsigned i =
Offset * PVD.PerVGPR,
1936 bool LastSubReg = (i + 1 == e);
1938 SB.
TII.get(AMDGPU::SI_RESTORE_S32_FROM_VGPR),
SubReg)
1955 MI->eraseFromParent();
1975 for (
unsigned i =
Offset * PVD.PerVGPR,
1994 unsigned SuperKillState = 0;
2004 MI = RestoreMBB.
end();
2010 for (
unsigned i =
Offset * PVD.PerVGPR,
2017 bool LastSubReg = (i + 1 == e);
2038 switch (
MI->getOpcode()) {
2039 case AMDGPU::SI_SPILL_S1024_SAVE:
2040 case AMDGPU::SI_SPILL_S512_SAVE:
2041 case AMDGPU::SI_SPILL_S384_SAVE:
2042 case AMDGPU::SI_SPILL_S352_SAVE:
2043 case AMDGPU::SI_SPILL_S320_SAVE:
2044 case AMDGPU::SI_SPILL_S288_SAVE:
2045 case AMDGPU::SI_SPILL_S256_SAVE:
2046 case AMDGPU::SI_SPILL_S224_SAVE:
2047 case AMDGPU::SI_SPILL_S192_SAVE:
2048 case AMDGPU::SI_SPILL_S160_SAVE:
2049 case AMDGPU::SI_SPILL_S128_SAVE:
2050 case AMDGPU::SI_SPILL_S96_SAVE:
2051 case AMDGPU::SI_SPILL_S64_SAVE:
2052 case AMDGPU::SI_SPILL_S32_SAVE:
2053 return spillSGPR(
MI, FI, RS, Indexes, LIS,
true, SpillToPhysVGPRLane);
2054 case AMDGPU::SI_SPILL_S1024_RESTORE:
2055 case AMDGPU::SI_SPILL_S512_RESTORE:
2056 case AMDGPU::SI_SPILL_S384_RESTORE:
2057 case AMDGPU::SI_SPILL_S352_RESTORE:
2058 case AMDGPU::SI_SPILL_S320_RESTORE:
2059 case AMDGPU::SI_SPILL_S288_RESTORE:
2060 case AMDGPU::SI_SPILL_S256_RESTORE:
2061 case AMDGPU::SI_SPILL_S224_RESTORE:
2062 case AMDGPU::SI_SPILL_S192_RESTORE:
2063 case AMDGPU::SI_SPILL_S160_RESTORE:
2064 case AMDGPU::SI_SPILL_S128_RESTORE:
2065 case AMDGPU::SI_SPILL_S96_RESTORE:
2066 case AMDGPU::SI_SPILL_S64_RESTORE:
2067 case AMDGPU::SI_SPILL_S32_RESTORE:
2068 return restoreSGPR(
MI, FI, RS, Indexes, LIS,
true, SpillToPhysVGPRLane);
2075 int SPAdj,
unsigned FIOperandNum,
2084 assert(SPAdj == 0 &&
"unhandled SP adjustment in call sequence?");
2087 int Index =
MI->getOperand(FIOperandNum).getIndex();
2093 switch (
MI->getOpcode()) {
2095 case AMDGPU::SI_SPILL_S1024_SAVE:
2096 case AMDGPU::SI_SPILL_S512_SAVE:
2097 case AMDGPU::SI_SPILL_S384_SAVE:
2098 case AMDGPU::SI_SPILL_S352_SAVE:
2099 case AMDGPU::SI_SPILL_S320_SAVE:
2100 case AMDGPU::SI_SPILL_S288_SAVE:
2101 case AMDGPU::SI_SPILL_S256_SAVE:
2102 case AMDGPU::SI_SPILL_S224_SAVE:
2103 case AMDGPU::SI_SPILL_S192_SAVE:
2104 case AMDGPU::SI_SPILL_S160_SAVE:
2105 case AMDGPU::SI_SPILL_S128_SAVE:
2106 case AMDGPU::SI_SPILL_S96_SAVE:
2107 case AMDGPU::SI_SPILL_S64_SAVE:
2108 case AMDGPU::SI_SPILL_S32_SAVE: {
2113 case AMDGPU::SI_SPILL_S1024_RESTORE:
2114 case AMDGPU::SI_SPILL_S512_RESTORE:
2115 case AMDGPU::SI_SPILL_S384_RESTORE:
2116 case AMDGPU::SI_SPILL_S352_RESTORE:
2117 case AMDGPU::SI_SPILL_S320_RESTORE:
2118 case AMDGPU::SI_SPILL_S288_RESTORE:
2119 case AMDGPU::SI_SPILL_S256_RESTORE:
2120 case AMDGPU::SI_SPILL_S224_RESTORE:
2121 case AMDGPU::SI_SPILL_S192_RESTORE:
2122 case AMDGPU::SI_SPILL_S160_RESTORE:
2123 case AMDGPU::SI_SPILL_S128_RESTORE:
2124 case AMDGPU::SI_SPILL_S96_RESTORE:
2125 case AMDGPU::SI_SPILL_S64_RESTORE:
2126 case AMDGPU::SI_SPILL_S32_RESTORE: {
2131 case AMDGPU::SI_SPILL_V1024_SAVE:
2132 case AMDGPU::SI_SPILL_V512_SAVE:
2133 case AMDGPU::SI_SPILL_V384_SAVE:
2134 case AMDGPU::SI_SPILL_V352_SAVE:
2135 case AMDGPU::SI_SPILL_V320_SAVE:
2136 case AMDGPU::SI_SPILL_V288_SAVE:
2137 case AMDGPU::SI_SPILL_V256_SAVE:
2138 case AMDGPU::SI_SPILL_V224_SAVE:
2139 case AMDGPU::SI_SPILL_V192_SAVE:
2140 case AMDGPU::SI_SPILL_V160_SAVE:
2141 case AMDGPU::SI_SPILL_V128_SAVE:
2142 case AMDGPU::SI_SPILL_V96_SAVE:
2143 case AMDGPU::SI_SPILL_V64_SAVE:
2144 case AMDGPU::SI_SPILL_V32_SAVE:
2145 case AMDGPU::SI_SPILL_A1024_SAVE:
2146 case AMDGPU::SI_SPILL_A512_SAVE:
2147 case AMDGPU::SI_SPILL_A384_SAVE:
2148 case AMDGPU::SI_SPILL_A352_SAVE:
2149 case AMDGPU::SI_SPILL_A320_SAVE:
2150 case AMDGPU::SI_SPILL_A288_SAVE:
2151 case AMDGPU::SI_SPILL_A256_SAVE:
2152 case AMDGPU::SI_SPILL_A224_SAVE:
2153 case AMDGPU::SI_SPILL_A192_SAVE:
2154 case AMDGPU::SI_SPILL_A160_SAVE:
2155 case AMDGPU::SI_SPILL_A128_SAVE:
2156 case AMDGPU::SI_SPILL_A96_SAVE:
2157 case AMDGPU::SI_SPILL_A64_SAVE:
2158 case AMDGPU::SI_SPILL_A32_SAVE:
2159 case AMDGPU::SI_SPILL_AV1024_SAVE:
2160 case AMDGPU::SI_SPILL_AV512_SAVE:
2161 case AMDGPU::SI_SPILL_AV384_SAVE:
2162 case AMDGPU::SI_SPILL_AV352_SAVE:
2163 case AMDGPU::SI_SPILL_AV320_SAVE:
2164 case AMDGPU::SI_SPILL_AV288_SAVE:
2165 case AMDGPU::SI_SPILL_AV256_SAVE:
2166 case AMDGPU::SI_SPILL_AV224_SAVE:
2167 case AMDGPU::SI_SPILL_AV192_SAVE:
2168 case AMDGPU::SI_SPILL_AV160_SAVE:
2169 case AMDGPU::SI_SPILL_AV128_SAVE:
2170 case AMDGPU::SI_SPILL_AV96_SAVE:
2171 case AMDGPU::SI_SPILL_AV64_SAVE:
2172 case AMDGPU::SI_SPILL_AV32_SAVE:
2173 case AMDGPU::SI_SPILL_WWM_V32_SAVE:
2174 case AMDGPU::SI_SPILL_WWM_AV32_SAVE: {
2176 AMDGPU::OpName::vdata);
2177 assert(
TII->getNamedOperand(*
MI, AMDGPU::OpName::soffset)->getReg() ==
2181 : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
2182 auto *
MBB =
MI->getParent();
2183 bool IsWWMRegSpill =
TII->isWWMRegSpillOpcode(
MI->getOpcode());
2184 if (IsWWMRegSpill) {
2190 TII->getNamedOperand(*
MI, AMDGPU::OpName::offset)->getImm(),
2191 *
MI->memoperands_begin(), RS);
2196 MI->eraseFromParent();
2199 case AMDGPU::SI_SPILL_V32_RESTORE:
2200 case AMDGPU::SI_SPILL_V64_RESTORE:
2201 case AMDGPU::SI_SPILL_V96_RESTORE:
2202 case AMDGPU::SI_SPILL_V128_RESTORE:
2203 case AMDGPU::SI_SPILL_V160_RESTORE:
2204 case AMDGPU::SI_SPILL_V192_RESTORE:
2205 case AMDGPU::SI_SPILL_V224_RESTORE:
2206 case AMDGPU::SI_SPILL_V256_RESTORE:
2207 case AMDGPU::SI_SPILL_V288_RESTORE:
2208 case AMDGPU::SI_SPILL_V320_RESTORE:
2209 case AMDGPU::SI_SPILL_V352_RESTORE:
2210 case AMDGPU::SI_SPILL_V384_RESTORE:
2211 case AMDGPU::SI_SPILL_V512_RESTORE:
2212 case AMDGPU::SI_SPILL_V1024_RESTORE:
2213 case AMDGPU::SI_SPILL_A32_RESTORE:
2214 case AMDGPU::SI_SPILL_A64_RESTORE:
2215 case AMDGPU::SI_SPILL_A96_RESTORE:
2216 case AMDGPU::SI_SPILL_A128_RESTORE:
2217 case AMDGPU::SI_SPILL_A160_RESTORE:
2218 case AMDGPU::SI_SPILL_A192_RESTORE:
2219 case AMDGPU::SI_SPILL_A224_RESTORE:
2220 case AMDGPU::SI_SPILL_A256_RESTORE:
2221 case AMDGPU::SI_SPILL_A288_RESTORE:
2222 case AMDGPU::SI_SPILL_A320_RESTORE:
2223 case AMDGPU::SI_SPILL_A352_RESTORE:
2224 case AMDGPU::SI_SPILL_A384_RESTORE:
2225 case AMDGPU::SI_SPILL_A512_RESTORE:
2226 case AMDGPU::SI_SPILL_A1024_RESTORE:
2227 case AMDGPU::SI_SPILL_AV32_RESTORE:
2228 case AMDGPU::SI_SPILL_AV64_RESTORE:
2229 case AMDGPU::SI_SPILL_AV96_RESTORE:
2230 case AMDGPU::SI_SPILL_AV128_RESTORE:
2231 case AMDGPU::SI_SPILL_AV160_RESTORE:
2232 case AMDGPU::SI_SPILL_AV192_RESTORE:
2233 case AMDGPU::SI_SPILL_AV224_RESTORE:
2234 case AMDGPU::SI_SPILL_AV256_RESTORE:
2235 case AMDGPU::SI_SPILL_AV288_RESTORE:
2236 case AMDGPU::SI_SPILL_AV320_RESTORE:
2237 case AMDGPU::SI_SPILL_AV352_RESTORE:
2238 case AMDGPU::SI_SPILL_AV384_RESTORE:
2239 case AMDGPU::SI_SPILL_AV512_RESTORE:
2240 case AMDGPU::SI_SPILL_AV1024_RESTORE:
2241 case AMDGPU::SI_SPILL_WWM_V32_RESTORE:
2242 case AMDGPU::SI_SPILL_WWM_AV32_RESTORE: {
2244 AMDGPU::OpName::vdata);
2245 assert(
TII->getNamedOperand(*
MI, AMDGPU::OpName::soffset)->getReg() ==
2249 : AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
2250 auto *
MBB =
MI->getParent();
2251 bool IsWWMRegSpill =
TII->isWWMRegSpillOpcode(
MI->getOpcode());
2252 if (IsWWMRegSpill) {
2259 TII->getNamedOperand(*
MI, AMDGPU::OpName::offset)->getImm(),
2260 *
MI->memoperands_begin(), RS);
2265 MI->eraseFromParent();
2273 int64_t
Offset = FrameInfo.getObjectOffset(
Index);
2275 if (
TII->isFLATScratch(*
MI)) {
2276 assert((int16_t)FIOperandNum ==
2278 AMDGPU::OpName::saddr));
2285 TII->getNamedOperand(*
MI, AMDGPU::OpName::offset);
2289 OffsetOp->
setImm(NewOffset);
2296 unsigned Opc =
MI->getOpcode();
2310 AMDGPU::OpName::vdst_in);
2311 bool TiedVDst = VDstIn != -1 &&
2312 MI->getOperand(VDstIn).isReg() &&
2313 MI->getOperand(VDstIn).isTied();
2315 MI->untieRegOperand(VDstIn);
2325 assert (NewVDst != -1 && NewVDstIn != -1 &&
"Must be tied!");
2326 MI->tieOperands(NewVDst, NewVDstIn);
2328 MI->setDesc(
TII->get(NewOpc));
2336 if (
TII->isImmOperandLegal(*
MI, FIOperandNum, FIOp))
2343 bool UseSGPR =
TII->isOperandLegal(*
MI, FIOperandNum, &FIOp);
2345 if (!
Offset && FrameReg && UseSGPR) {
2351 : &AMDGPU::VGPR_32RegClass;
2358 if ((!FrameReg || !
Offset) && TmpReg) {
2359 unsigned Opc = UseSGPR ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
2362 MIB.addReg(FrameReg);
2370 RS->
isRegUsed(AMDGPU::SCC) && !
MI->definesRegister(AMDGPU::SCC);
2375 MI,
false, 0, !UseSGPR);
2379 if ((!TmpSReg && !FrameReg) || (!TmpReg && !UseSGPR))
2390 assert(!(
Offset & 0x1) &&
"Flat scratch offset must be aligned!");
2410 if (TmpSReg == FrameReg) {
2412 if (NeedSaveSCC && !
MI->registerDefIsDead(AMDGPU::SCC)) {
2436 bool IsMUBUF =
TII->isMUBUF(*
MI);
2443 RS->
isRegUsed(AMDGPU::SCC) && !
MI->definesRegister(AMDGPU::SCC);
2445 ? &AMDGPU::SReg_32RegClass
2446 : &AMDGPU::VGPR_32RegClass;
2447 bool IsCopy =
MI->getOpcode() == AMDGPU::V_MOV_B32_e32 ||
2448 MI->getOpcode() == AMDGPU::V_MOV_B32_e64;
2450 IsCopy ?
MI->getOperand(0).getReg()
2453 int64_t
Offset = FrameInfo.getObjectOffset(
Index);
2455 unsigned OpCode = IsSALU && !LiveSCC ? AMDGPU::S_LSHR_B32
2456 : AMDGPU::V_LSHRREV_B32_e64;
2458 if (OpCode == AMDGPU::V_LSHRREV_B32_e64)
2464 if (IsSALU && !LiveSCC)
2465 Shift.getInstr()->getOperand(3).setIsDead();
2466 if (IsSALU && LiveSCC) {
2468 AMDGPU::SReg_32RegClass, Shift,
false, 0);
2472 ResultReg = NewDest;
2477 if ((MIB =
TII->getAddNoCarry(*
MBB,
MI,
DL, ResultReg, *RS)) !=
2487 const bool IsVOP2 = MIB->
getOpcode() == AMDGPU::V_ADD_U32_e32;
2498 "Need to reuse carry out register");
2503 ConstOffsetReg = getSubReg(MIB.
getReg(1), AMDGPU::sub0);
2505 ConstOffsetReg = MIB.
getReg(1);
2515 if (!MIB || IsSALU) {
2523 AMDGPU::SReg_32_XM0RegClass,
MI,
false, 0,
false);
2524 Register ScaledReg = TmpScaledReg.
isValid() ? TmpScaledReg : FrameReg;
2536 ResultReg = ScaledReg;
2539 if (!TmpScaledReg.
isValid()) {
2552 MI->eraseFromParent();
2561 assert(
static_cast<int>(FIOperandNum) ==
2563 AMDGPU::OpName::vaddr));
2565 auto &SOffset = *
TII->getNamedOperand(*
MI, AMDGPU::OpName::soffset);
2566 assert((SOffset.isImm() && SOffset.getImm() == 0));
2568 if (FrameReg != AMDGPU::NoRegister)
2569 SOffset.ChangeToRegister(FrameReg,
false);
2571 int64_t
Offset = FrameInfo.getObjectOffset(
Index);
2573 =
TII->getNamedOperand(*
MI, AMDGPU::OpName::offset)->getImm();
2574 int64_t NewOffset = OldImm +
Offset;
2576 if (
TII->isLegalMUBUFImmOffset(NewOffset) &&
2578 MI->eraseFromParent();
2587 if (!
TII->isImmOperandLegal(*
MI, FIOperandNum, FIOp)) {
2610 return &AMDGPU::VReg_64RegClass;
2612 return &AMDGPU::VReg_96RegClass;
2614 return &AMDGPU::VReg_128RegClass;
2616 return &AMDGPU::VReg_160RegClass;
2618 return &AMDGPU::VReg_192RegClass;
2620 return &AMDGPU::VReg_224RegClass;
2622 return &AMDGPU::VReg_256RegClass;
2624 return &AMDGPU::VReg_288RegClass;
2626 return &AMDGPU::VReg_320RegClass;
2628 return &AMDGPU::VReg_352RegClass;
2630 return &AMDGPU::VReg_384RegClass;
2632 return &AMDGPU::VReg_512RegClass;
2634 return &AMDGPU::VReg_1024RegClass;
2642 return &AMDGPU::VReg_64_Align2RegClass;
2644 return &AMDGPU::VReg_96_Align2RegClass;
2646 return &AMDGPU::VReg_128_Align2RegClass;
2648 return &AMDGPU::VReg_160_Align2RegClass;
2650 return &AMDGPU::VReg_192_Align2RegClass;
2652 return &AMDGPU::VReg_224_Align2RegClass;
2654 return &AMDGPU::VReg_256_Align2RegClass;
2656 return &AMDGPU::VReg_288_Align2RegClass;
2658 return &AMDGPU::VReg_320_Align2RegClass;
2660 return &AMDGPU::VReg_352_Align2RegClass;
2662 return &AMDGPU::VReg_384_Align2RegClass;
2664 return &AMDGPU::VReg_512_Align2RegClass;
2666 return &AMDGPU::VReg_1024_Align2RegClass;
2674 return &AMDGPU::VReg_1RegClass;
2676 return &AMDGPU::VGPR_16RegClass;
2678 return &AMDGPU::VGPR_32RegClass;
2686 return &AMDGPU::AReg_64RegClass;
2688 return &AMDGPU::AReg_96RegClass;
2690 return &AMDGPU::AReg_128RegClass;
2692 return &AMDGPU::AReg_160RegClass;
2694 return &AMDGPU::AReg_192RegClass;
2696 return &AMDGPU::AReg_224RegClass;
2698 return &AMDGPU::AReg_256RegClass;
2700 return &AMDGPU::AReg_288RegClass;
2702 return &AMDGPU::AReg_320RegClass;
2704 return &AMDGPU::AReg_352RegClass;
2706 return &AMDGPU::AReg_384RegClass;
2708 return &AMDGPU::AReg_512RegClass;
2710 return &AMDGPU::AReg_1024RegClass;
2718 return &AMDGPU::AReg_64_Align2RegClass;
2720 return &AMDGPU::AReg_96_Align2RegClass;
2722 return &AMDGPU::AReg_128_Align2RegClass;
2724 return &AMDGPU::AReg_160_Align2RegClass;
2726 return &AMDGPU::AReg_192_Align2RegClass;
2728 return &AMDGPU::AReg_224_Align2RegClass;
2730 return &AMDGPU::AReg_256_Align2RegClass;
2732 return &AMDGPU::AReg_288_Align2RegClass;
2734 return &AMDGPU::AReg_320_Align2RegClass;
2736 return &AMDGPU::AReg_352_Align2RegClass;
2738 return &AMDGPU::AReg_384_Align2RegClass;
2740 return &AMDGPU::AReg_512_Align2RegClass;
2742 return &AMDGPU::AReg_1024_Align2RegClass;
2750 return &AMDGPU::AGPR_LO16RegClass;
2752 return &AMDGPU::AGPR_32RegClass;
2760 return &AMDGPU::AV_64RegClass;
2762 return &AMDGPU::AV_96RegClass;
2764 return &AMDGPU::AV_128RegClass;
2766 return &AMDGPU::AV_160RegClass;
2768 return &AMDGPU::AV_192RegClass;
2770 return &AMDGPU::AV_224RegClass;
2772 return &AMDGPU::AV_256RegClass;
2774 return &AMDGPU::AV_288RegClass;
2776 return &AMDGPU::AV_320RegClass;
2778 return &AMDGPU::AV_352RegClass;
2780 return &AMDGPU::AV_384RegClass;
2782 return &AMDGPU::AV_512RegClass;
2784 return &AMDGPU::AV_1024RegClass;
2792 return &AMDGPU::AV_64_Align2RegClass;
2794 return &AMDGPU::AV_96_Align2RegClass;
2796 return &AMDGPU::AV_128_Align2RegClass;
2798 return &AMDGPU::AV_160_Align2RegClass;
2800 return &AMDGPU::AV_192_Align2RegClass;
2802 return &AMDGPU::AV_224_Align2RegClass;
2804 return &AMDGPU::AV_256_Align2RegClass;
2806 return &AMDGPU::AV_288_Align2RegClass;
2808 return &AMDGPU::AV_320_Align2RegClass;
2810 return &AMDGPU::AV_352_Align2RegClass;
2812 return &AMDGPU::AV_384_Align2RegClass;
2814 return &AMDGPU::AV_512_Align2RegClass;
2816 return &AMDGPU::AV_1024_Align2RegClass;
2824 return &AMDGPU::AV_32RegClass;
2833 return &AMDGPU::SGPR_LO16RegClass;
2835 return &AMDGPU::SReg_32RegClass;
2837 return &AMDGPU::SReg_64RegClass;
2839 return &AMDGPU::SGPR_96RegClass;
2841 return &AMDGPU::SGPR_128RegClass;
2843 return &AMDGPU::SGPR_160RegClass;
2845 return &AMDGPU::SGPR_192RegClass;
2847 return &AMDGPU::SGPR_224RegClass;
2849 return &AMDGPU::SGPR_256RegClass;
2851 return &AMDGPU::SGPR_288RegClass;
2853 return &AMDGPU::SGPR_320RegClass;
2855 return &AMDGPU::SGPR_352RegClass;
2857 return &AMDGPU::SGPR_384RegClass;
2859 return &AMDGPU::SGPR_512RegClass;
2861 return &AMDGPU::SGPR_1024RegClass;
2869 if (Reg.isVirtual())
2870 RC =
MRI.getRegClass(Reg);
2872 RC = getPhysRegBaseClass(Reg);
2878 unsigned Size = getRegSizeInBits(*SRC);
2880 assert(VRC &&
"Invalid register class size");
2886 unsigned Size = getRegSizeInBits(*SRC);
2888 assert(ARC &&
"Invalid register class size");
2894 unsigned Size = getRegSizeInBits(*VRC);
2896 return &AMDGPU::SGPR_32RegClass;
2898 assert(SRC &&
"Invalid register class size");
2905 unsigned SubIdx)
const {
2908 getMatchingSuperRegClass(SuperRC, SubRC, SubIdx);
2909 return MatchRC && MatchRC->
hasSubClassEq(SuperRC) ? MatchRC :
nullptr;
2925 unsigned SrcSubReg)
const {
2942 return getCommonSubClass(DefRC, SrcRC) !=
nullptr;
2958 if (ReserveHighestRegister) {
2960 if (
MRI.isAllocatable(Reg) && !
MRI.isPhysRegUsed(Reg))
2964 if (
MRI.isAllocatable(Reg) && !
MRI.isPhysRegUsed(Reg))
2981 unsigned EltSize)
const {
2983 assert(RegBitWidth >= 32 && RegBitWidth <= 1024);
2985 const unsigned RegDWORDs = RegBitWidth / 32;
2986 const unsigned EltDWORDs = EltSize / 4;
2987 assert(RegSplitParts.size() + 1 >= EltDWORDs);
2989 const std::vector<int16_t> &Parts = RegSplitParts[EltDWORDs - 1];
2990 const unsigned NumParts = RegDWORDs / EltDWORDs;
2992 return ArrayRef(Parts.data(), NumParts);
2998 return Reg.isVirtual() ?
MRI.getRegClass(Reg) : getPhysRegBaseClass(Reg);
3005 return getSubRegisterClass(SrcRC, MO.
getSubReg());
3030 unsigned SrcSize = getRegSizeInBits(*SrcRC);
3031 unsigned DstSize = getRegSizeInBits(*DstRC);
3032 unsigned NewSize = getRegSizeInBits(*NewRC);
3038 if (SrcSize <= 32 || DstSize <= 32)
3041 return NewSize <= DstSize || NewSize <= SrcSize;
3050 switch (RC->
getID()) {
3052 return AMDGPUGenRegisterInfo::getRegPressureLimit(RC, MF);
3053 case AMDGPU::VGPR_32RegClassID:
3055 case AMDGPU::SGPR_32RegClassID:
3056 case AMDGPU::SGPR_LO16RegClassID:
3062 unsigned Idx)
const {
3063 if (
Idx == AMDGPU::RegisterPressureSets::VGPR_32 ||
3064 Idx == AMDGPU::RegisterPressureSets::AGPR_32)
3068 if (
Idx == AMDGPU::RegisterPressureSets::SReg_32)
3076 static const int Empty[] = { -1 };
3078 if (RegPressureIgnoredUnits[RegUnit])
3081 return AMDGPUGenRegisterInfo::getRegUnitPressureSets(RegUnit);
3086 return AMDGPU::SGPR30_SGPR31;
3092 switch (RB.
getID()) {
3093 case AMDGPU::VGPRRegBankID:
3096 case AMDGPU::VCCRegBankID:
3098 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
3099 : &AMDGPU::SReg_64_XEXECRegClass;
3100 case AMDGPU::SGPRRegBankID:
3102 case AMDGPU::AGPRRegBankID:
3117 return getAllocatableClass(RC);
3123 return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC;
3127 return isWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3133 : &AMDGPU::VReg_64RegClass;
3138 switch ((
int)RCID) {
3139 case AMDGPU::SReg_1RegClassID:
3141 case AMDGPU::SReg_1_XEXECRegClassID:
3142 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
3143 : &AMDGPU::SReg_64_XEXECRegClass;
3147 return AMDGPUGenRegisterInfo::getRegClass(RCID);
3160 if (Reg.isVirtual()) {
3165 :
MRI.getMaxLaneMaskForVReg(Reg);
3169 if ((S.LaneMask & SubLanes) == SubLanes) {
3170 V = S.getVNInfoAt(UseIdx);
3182 for (
MCRegUnit Unit : regunits(Reg.asMCReg())) {
3197 if (!Def || !MDT.dominates(Def, &
Use))
3200 assert(Def->modifiesRegister(Reg,
this));
3206 assert(getRegSizeInBits(*getPhysRegBaseClass(Reg)) <= 32);
3209 AMDGPU::SReg_32RegClass,
3210 AMDGPU::AGPR_32RegClass } ) {
3211 if (
MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::lo16, &RC))
3214 if (
MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::hi16,
3215 &AMDGPU::VGPR_32RegClass)) {
3219 return AMDGPU::NoRegister;
3242 unsigned Size = getRegSizeInBits(*RC);
3276 return std::min(128u, getSubRegIdxSize(
SubReg));
3280 return std::min(32u, getSubRegIdxSize(
SubReg));
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Provides AMDGPU specific target descriptions.
This file declares the targeting of the RegisterBankInfo class for AMDGPU.
static const Function * getParent(const Value *V)
Analysis containing CSE Info
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
AMD GCN specific subclass of TargetSubtarget.
const HexagonInstrInfo * TII
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
unsigned const TargetRegisterInfo * TRI
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static int getOffenMUBUFStore(unsigned Opc)
static const TargetRegisterClass * getAnyAGPRClassForBitWidth(unsigned BitWidth)
static int getOffsetMUBUFLoad(unsigned Opc)
static const std::array< unsigned, 17 > SubRegFromChannelTableWidthMap
static const TargetRegisterClass * getAlignedAGPRClassForBitWidth(unsigned BitWidth)
static bool buildMUBUFOffsetLoadStore(const GCNSubtarget &ST, MachineFrameInfo &MFI, MachineBasicBlock::iterator MI, int Index, int64_t Offset)
static unsigned getFlatScratchSpillOpcode(const SIInstrInfo *TII, unsigned LoadStoreOp, unsigned EltSize)
static const TargetRegisterClass * getAlignedVGPRClassForBitWidth(unsigned BitWidth)
static int getOffsetMUBUFStore(unsigned Opc)
static const TargetRegisterClass * getAnyVGPRClassForBitWidth(unsigned BitWidth)
static cl::opt< bool > EnableSpillSGPRToVGPR("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling SGPRs to VGPRs"), cl::ReallyHidden, cl::init(true))
static unsigned getNumSubRegsForSpillOp(unsigned Op)
static const TargetRegisterClass * getAlignedVectorSuperClassForBitWidth(unsigned BitWidth)
static const TargetRegisterClass * getAnyVectorSuperClassForBitWidth(unsigned BitWidth)
static MachineInstrBuilder spillVGPRtoAGPR(const GCNSubtarget &ST, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Index, unsigned Lane, unsigned ValueReg, bool IsKill)
static int getOffenMUBUFLoad(unsigned Opc)
Interface definition for SIRegisterInfo.
static const char * getRegisterName(MCRegister Reg)
uint32_t getLDSSize() const
bool isBottomOfStack() const
unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const
Inverse of getMaxLocalMemWithWaveCount.
bool useRealTrue16Insts() const
Return true if real (non-fake) variants of True16 instructions using 16-bit registers should be code-...
unsigned getWavefrontSizeLog2() const
unsigned getWavefrontSize() const
bool hasInv2PiInlineImm() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
This class represents an Operation in the Expression.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasGFX90AInsts() const
bool hasMFMAInlineLiteralBug() const
const SIInstrInfo * getInstrInfo() const override
unsigned getConstantBusLimit(unsigned Opcode) const
bool needsAlignedVGPRs() const
Return if operations acting on VGPR tuples require even alignment.
bool enableFlatScratch() const
unsigned getMaxNumVGPRs(unsigned WavesPerEU) const
const SIFrameLowering * getFrameLowering() const override
unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const
bool hasFlatScratchSTMode() const
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
iterator_range< subrange_iterator > subranges()
void removeAllRegUnitsForPhysReg(MCRegister Reg)
Remove associated live ranges for the register units associated with Reg.
bool hasInterval(Register Reg) const
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
LiveInterval & getInterval(Register Reg)
This class represents the liveness of a register, stack slot, etc.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
A set of register units used to track register liveness.
bool available(MCPhysReg Reg) const
Returns true if no part of physical register Reg is live.
Describe properties that are true of each instruction in the target description file.
MCRegAliasIterator enumerates all registers aliasing Reg.
Wrapper class representing physical registers. Should be passed by value.
static MCRegister from(unsigned Val)
Check the provided unsigned value is a valid MCRegister.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasCalls() const
Return true if the current function has any function calls.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
bool hasStackObjects() const
Return true if there are any stack objects in this function.
uint8_t getStackID(int ObjectIdx) const
unsigned getNumFixedObjects() const
Return the number of fixed objects.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
const MachineOperand & getOperand(unsigned i) const
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
const MachinePointerInfo & getPointerInfo() const
Flags getFlags() const
Return the raw flags of the source value,.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
void setImm(int64_t immVal)
void setIsDead(bool Val=true)
void setReg(Register Reg)
Change the register this operand corresponds to.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
void setIsKill(bool Val=true)
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
Register getReg() const
getReg - Returns the register number.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
AnalysisType & getAnalysis() const
getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information ...
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
void assignRegToScavengingIndex(int FI, Register Reg, MachineInstr *Restore=nullptr)
Record that Reg is in use at scavenging index FI.
Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
Holds all the information related to register banks.
virtual bool isDivergentRegBank(const RegisterBank *RB) const
Returns true if the register bank is considered divergent.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
This class implements the register bank concept.
unsigned getID() const
Get the identifier of this register bank.
Wrapper class representing virtual and physical registers.
constexpr bool isValid() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
static bool isFLATScratch(const MachineInstr &MI)
static bool isMUBUF(const MachineInstr &MI)
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
bool usesAGPRs(const MachineFunction &MF) const
ArrayRef< MCPhysReg > getAGPRSpillVGPRs() const
MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const
Register getLongBranchReservedReg() const
Register getStackPtrOffsetReg() const
Register getScratchRSrcReg() const
Returns the physical register reserved for use as the resource descriptor for scratch accesses.
ArrayRef< MCPhysReg > getVGPRSpillAGPRs() const
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToVirtualVGPRLanes(int FrameIndex) const
Register getSGPRForEXECCopy() const
ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToPhysicalVGPRLanes(int FrameIndex) const
Register getVGPRForAGPRCopy() const
Register getFrameOffsetReg() const
void addToSpilledVGPRs(unsigned num)
const ReservedRegSet & getWWMReservedRegs() const
void addToSpilledSGPRs(unsigned num)
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
int64_t getScratchInstrOffset(const MachineInstr *MI) const
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
const TargetRegisterClass * getRegClass(unsigned RCID) const
const TargetRegisterClass * getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const
Returns a register class which is compatible with SuperRC, such that a subregister exists with class ...
ArrayRef< MCPhysReg > getAllSGPR64(const MachineFunction &MF) const
Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
MCRegister findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const
Returns a lowest register that is not used at any point in the function.
static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs=1)
MCPhysReg get32BitRegister(MCPhysReg Reg) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
const TargetRegisterClass * getProperlyAlignedRC(const TargetRegisterClass *RC) const
bool shouldRealignStack(const MachineFunction &MF) const override
bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false, bool SpillToPhysVGPRLane=false) const
bool isProperlyAlignedRC(const TargetRegisterClass &RC) const
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
Register getFrameRegister(const MachineFunction &MF) const override
LLVM_READONLY const TargetRegisterClass * getVectorSuperClassForBitWidth(unsigned BitWidth) const
bool spillEmergencySGPR(MachineBasicBlock::iterator MI, MachineBasicBlock &RestoreMBB, Register SGPR, RegScavenger *RS) const
SIRegisterInfo(const GCNSubtarget &ST)
const uint32_t * getAllVGPRRegMask() const
MCRegister getReturnAddressReg(const MachineFunction &MF) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
bool hasBasePointer(const MachineFunction &MF) const
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
Returns a legal register class to copy a register in the specified class to or from.
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
ArrayRef< MCPhysReg > getAllSGPR32(const MachineFunction &MF) const
Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed.
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool SpillToPhysVGPRLane=false) const
Special case of eliminateFrameIndex.
bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const
void buildSpillLoadStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LiveRegUnits *LiveUnits=nullptr) const
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
LLVM_READONLY const TargetRegisterClass * getAGPRClassForBitWidth(unsigned BitWidth) const
static bool isChainScratchRegister(Register VGPR)
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
bool opCanUseInlineConstant(unsigned OpType) const
const TargetRegisterClass * getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank) const
const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
bool isUniformReg(const MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register Reg) const override
const uint32_t * getNoPreservedMask() const override
StringRef getRegAsmName(MCRegister Reg) const override
const uint32_t * getAllAllocatableSRegMask() const
MCRegister getAlignedHighSGPRForRC(const MachineFunction &MF, const unsigned Align, const TargetRegisterClass *RC) const
Return the largest available SGPR aligned to Align for the register class RC.
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, Register Reg) const
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
const uint32_t * getAllVectorRegMask() const
const TargetRegisterClass * getEquivalentAGPRClass(const TargetRegisterClass *SRC) const
static LLVM_READONLY const TargetRegisterClass * getSGPRClassForBitWidth(unsigned BitWidth)
const TargetRegisterClass * getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const
bool opCanUseLiteralConstant(unsigned OpType) const
Register getBaseRegister() const
LLVM_READONLY const TargetRegisterClass * getVGPRClassForBitWidth(unsigned BitWidth) const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
static bool isVGPRClass(const TargetRegisterClass *RC)
unsigned getHWRegIndex(MCRegister Reg) const
MachineInstr * findReachingDef(Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
ArrayRef< MCPhysReg > getAllSGPR128(const MachineFunction &MF) const
Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
const TargetRegisterClass * getRegClassForOperandReg(const MachineRegisterInfo &MRI, const MachineOperand &MO) const
const uint32_t * getAllAGPRRegMask() const
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
const TargetRegisterClass * getBoolRC() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false, bool SpillToPhysVGPRLane=false) const
If OnlyToVGPR is true, this will only succeed if this manages to find a free VGPR lane to spill.
MCRegister getExec() const
MCRegister getVCC() const
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
bool isVectorSuperClass(const TargetRegisterClass *RC) const
const TargetRegisterClass * getWaveMaskRegClass() const
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC, unsigned SubReg) const
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
const TargetRegisterClass * getVGPR64Class() const
void buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const
static bool isSGPRClass(const TargetRegisterClass *RC)
static bool isAGPRClass(const TargetRegisterClass *RC)
const int * getRegUnitPressureSets(unsigned RegUnit) const override
SlotIndex - An opaque wrapper around machine indexes.
bool isValid() const
Returns true if this is a valid index.
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
SlotIndex replaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
ReplaceMachineInstrInMaps - Replacing a machine instr with a new one in maps used by register allocat...
StringRef - Represent a constant reference to a string, i.e.
const uint8_t TSFlags
Configurable target specific flags.
unsigned getID() const
Return the register class ID number.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
A Use represents the edge between a Value definition and its users.
VNInfo - Value Number Information.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ PRIVATE_ADDRESS
Address space for private memory.
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
LLVM_READONLY int getFlatScratchInstSVfromSS(uint16_t Opcode)
LLVM_READONLY int getFlatScratchInstSTfromSS(uint16_t Opcode)
LLVM_READONLY int getFlatScratchInstSVfromSVS(uint16_t Opcode)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
bool isHi(unsigned Reg, const MCRegisterInfo &MRI)
@ OPERAND_REG_INLINE_AC_FIRST
@ OPERAND_REG_INLINE_AC_LAST
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
@ AMDGPU_Gfx
Used for AMD graphics targets.
@ AMDGPU_CS_ChainPreserve
Used on AMDGPUs to give the middle-end more control over argument placement.
@ AMDGPU_CS_Chain
Used on AMDGPUs to give the middle-end more control over argument placement.
@ Cold
Attempts to make code in the caller as efficient as possible under the assumption that the call is no...
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
auto reverse(ContainerTy &&C)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
unsigned getDefRegState(bool B)
unsigned getKillRegState(bool B)
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
constexpr unsigned BitWidth
static const MachineMemOperand::Flags MOLastUse
Mark the MMO of a load as the last use.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Description of the encoding of one expression Op.
This class contains a discriminated union of information about pointers in memory operands,...
MachinePointerInfo getWithOffset(int64_t O) const
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
void setMI(MachineBasicBlock *NewMBB, MachineBasicBlock::iterator NewMI)
ArrayRef< int16_t > SplitParts
SIMachineFunctionInfo & MFI
SGPRSpillBuilder(const SIRegisterInfo &TRI, const SIInstrInfo &TII, bool IsWave32, MachineBasicBlock::iterator MI, int Index, RegScavenger *RS)
SGPRSpillBuilder(const SIRegisterInfo &TRI, const SIInstrInfo &TII, bool IsWave32, MachineBasicBlock::iterator MI, Register Reg, bool IsKill, int Index, RegScavenger *RS)
PerVGPRData getPerVGPRData()
MachineBasicBlock::iterator MI
void readWriteTmpVGPR(unsigned Offset, bool IsLoad)
const SIRegisterInfo & TRI
The llvm::once_flag structure.