LLVM  14.0.0git
AllocationOrder.cpp
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1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements an allocation order for virtual registers.
10 //
11 // The preferred allocation order for a virtual register depends on allocation
12 // hints and target hooks. The AllocationOrder class encapsulates all of that.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AllocationOrder.h"
21 #include "llvm/Support/Debug.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "regalloc"
27 
28 // Compare VirtRegMap::getRegAllocPref().
29 AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM,
30  const RegisterClassInfo &RegClassInfo,
31  const LiveRegMatrix *Matrix) {
32  const MachineFunction &MF = VRM.getMachineFunction();
33  const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
34  auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
36  bool HardHints =
37  TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
38 
39  LLVM_DEBUG({
40  if (!Hints.empty()) {
41  dbgs() << "hints:";
42  for (unsigned I = 0, E = Hints.size(); I != E; ++I)
43  dbgs() << ' ' << printReg(Hints[I], TRI);
44  dbgs() << '\n';
45  }
46  });
47 #ifndef NDEBUG
48  for (unsigned I = 0, E = Hints.size(); I != E; ++I)
49  assert(is_contained(Order, Hints[I]) &&
50  "Target hint is outside allocation order.");
51 #endif
52  return AllocationOrder(std::move(Hints), Order, HardHints);
53 }
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::RegisterClassInfo::getOrder
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
Definition: RegisterClassInfo.h:99
AllocationOrder.h
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::AllocationOrder::AllocationOrder
AllocationOrder(SmallVector< MCPhysReg, 16 > &&Hints, ArrayRef< MCPhysReg > Order, bool HardHints)
Create an AllocationOrder given the Hits, Order, and HardHits values.
Definition: AllocationOrder.h:90
llvm::VirtRegMap
Definition: VirtRegMap.h:33
RegisterClassInfo.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::VirtRegMap::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: VirtRegMap.h:88
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
MachineRegisterInfo.h
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:644
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::AllocationOrder
Definition: AllocationOrder.h:30
VirtRegMap.h
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetRegisterInfo::getRegAllocationHints
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Definition: TargetRegisterInfo.cpp:421
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1665
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::RegisterClassInfo
Definition: RegisterClassInfo.h:30
llvm::MachineFunction
Definition: MachineFunction.h:234
Matrix
Live Register Matrix
Definition: LiveRegMatrix.cpp:44
llvm::VirtRegMap::getTargetRegInfo
const TargetRegisterInfo & getTargetRegInfo() const
Definition: VirtRegMap.h:94
llvm::AllocationOrder::create
static AllocationOrder create(unsigned VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo, const LiveRegMatrix *Matrix)
Create a new AllocationOrder for VirtReg.
Definition: AllocationOrder.cpp:29
raw_ostream.h
MachineFunction.h
Debug.h
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40