LLVM 19.0.0git
AllocationOrder.cpp
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1//===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements an allocation order for virtual registers.
10//
11// The preferred allocation order for a virtual register depends on allocation
12// hints and target hooks. The AllocationOrder class encapsulates all of that.
13//
14//===----------------------------------------------------------------------===//
15
16#include "AllocationOrder.h"
21#include "llvm/Support/Debug.h"
23
24using namespace llvm;
25
26#define DEBUG_TYPE "regalloc"
27
28// Compare VirtRegMap::getRegAllocPref().
30 const RegisterClassInfo &RegClassInfo,
31 const LiveRegMatrix *Matrix) {
32 const MachineFunction &MF = VRM.getMachineFunction();
34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
36 bool HardHints =
37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
38
40 if (!Hints.empty()) {
41 dbgs() << "hints:";
42 for (unsigned I = 0, E = Hints.size(); I != E; ++I)
43 dbgs() << ' ' << printReg(Hints[I], TRI);
44 dbgs() << '\n';
45 }
46 });
47#ifndef NDEBUG
48 for (unsigned I = 0, E = Hints.size(); I != E; ++I)
49 assert(is_contained(Order, Hints[I]) &&
50 "Target hint is outside allocation order.");
51#endif
52 return AllocationOrder(std::move(Hints), Order, HardHints);
53}
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_DEBUG(X)
Definition: Debug.h:101
Live Register Matrix
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static AllocationOrder create(unsigned VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo, const LiveRegMatrix *Matrix)
Create a new AllocationOrder for VirtReg.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineFunction & getMachineFunction() const
Definition: VirtRegMap.h:87
const TargetRegisterInfo & getTargetRegInfo() const
Definition: VirtRegMap.h:93
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1888