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35 #define DEBUG_TYPE "regalloc"
39 cl::desc(
"Limit all regclasses to N registers"));
55 assert(TRI &&
"no register info set");
59 if (Update || CSR != CalleeSavedRegs) {
62 CalleeSavedAliases.assign(TRI->
getNumRegs(), 0);
65 CalleeSavedAliases[*AI] = *
I;
69 CalleeSavedRegs = CSR;
75 if (Reserved.
size() != RR.
size() || RR != Reserved) {
83 PSetLimits.reset(
new unsigned[NumPSets]);
84 std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
93 assert(RC &&
"no register class given");
94 RCInfo &RCI = RegClass[RC->
getID()];
105 uint8_t MinCost = uint8_t(~0u);
106 uint8_t LastCost = uint8_t(~0u);
107 unsigned LastCostChange = 0;
112 for (
unsigned i = 0;
i != RawOrder.
size(); ++
i) {
113 unsigned PhysReg = RawOrder[
i];
115 if (Reserved.
test(PhysReg))
117 uint8_t Cost = RegCosts[PhysReg];
120 if (CalleeSavedAliases[PhysReg] &&
121 !STI.ignoreCSRForAllocationOrder(*MF, PhysReg))
123 CSRAlias.push_back(PhysReg);
125 if (Cost != LastCost)
127 RCI.Order[
N++] = PhysReg;
131 RCI.NumRegs =
N + CSRAlias.size();
132 assert(RCI.NumRegs <= NumRegs &&
"Allocation order larger than regclass");
135 for (
unsigned i = 0,
e = CSRAlias.size();
i !=
e; ++
i) {
136 unsigned PhysReg = CSRAlias[
i];
137 uint8_t Cost = RegCosts[PhysReg];
138 if (Cost != LastCost)
140 RCI.Order[
N++] = PhysReg;
152 RCI.ProperSubClass =
true;
154 RCI.MinCost = MinCost;
155 RCI.LastCostChange = LastCostChange;
159 for (
unsigned I = 0;
I != RCI.NumRegs; ++
I)
161 dbgs() << (RCI.ProperSubClass ?
" ] (sub-class)\n" :
" ]\n");
173 unsigned NumRCUnits = 0;
176 for (; *PSetID != -1; ++PSetID) {
177 if ((
unsigned)*PSetID == Idx)
186 if (!RC || NUnits > NumRCUnits) {
191 assert(RC &&
"Failed to find register class");
199 if (NAllocatableRegs == 0)
200 return RegPressureSetLimit;
201 unsigned NReserved = RC->
getNumRegs() - NAllocatableRegs;
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
unsigned getID() const
Return the register class ID number.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
ArrayRef< uint8_t > getRegisterCosts(const MachineFunction &MF) const
Get a list of cost values for all registers that correspond to the index returned by RegisterCostTabl...
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
(vector float) vec_cmpeq(*A, *B) C
size_type size() const
size - Returns the number of bits in this bitvector.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const
getNumAllocatableRegs - Returns the number of actually allocatable registers in RC in the current fun...
iterator_range< regclass_iterator > regclasses() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
initializer< Ty > init(const Ty &Val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
bool test(unsigned Idx) const
unsigned getNumRegs() const
Return the number of registers in this class.
unsigned getNumRegClasses() const
unsigned computePSetLimit(unsigned Idx) const
This is not accurate because two overlapping register sets may have some nonoverlapping reserved regi...
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
size_t size() const
size - Get the array size.
static cl::opt< unsigned > StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"), cl::desc("Limit all regclasses to N registers"))
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
MCRegAliasIterator enumerates all registers aliasing Reg.