LLVM  14.0.0git
PPCInstrInfo.cpp
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1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCInstrInfo.h"
15 #include "PPC.h"
16 #include "PPCHazardRecognizers.h"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Statistic.h"
35 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCInst.h"
39 #include "llvm/Support/Debug.h"
43 
44 using namespace llvm;
45 
46 #define DEBUG_TYPE "ppc-instr-info"
47 
48 #define GET_INSTRMAP_INFO
49 #define GET_INSTRINFO_CTOR_DTOR
50 #include "PPCGenInstrInfo.inc"
51 
52 STATISTIC(NumStoreSPILLVSRRCAsVec,
53  "Number of spillvsrrc spilled to stack as vec");
54 STATISTIC(NumStoreSPILLVSRRCAsGpr,
55  "Number of spillvsrrc spilled to stack as gpr");
56 STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc");
57 STATISTIC(CmpIselsConverted,
58  "Number of ISELs that depend on comparison of constants converted");
59 STATISTIC(MissedConvertibleImmediateInstrs,
60  "Number of compare-immediate instructions fed by constants");
61 STATISTIC(NumRcRotatesConvertedToRcAnd,
62  "Number of record-form rotates converted to record-form andi");
63 
64 static cl::
65 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
66  cl::desc("Disable analysis for CTR loops"));
67 
68 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
69 cl::desc("Disable compare instruction optimization"), cl::Hidden);
70 
71 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
72 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
73 cl::Hidden);
74 
75 static cl::opt<bool>
76 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
77  cl::desc("Use the old (incorrect) instruction latency calculation"));
78 
79 static cl::opt<float>
80  FMARPFactor("ppc-fma-rp-factor", cl::Hidden, cl::init(1.5),
81  cl::desc("register pressure factor for the transformations."));
82 
84  "ppc-fma-rp-reduction", cl::Hidden, cl::init(true),
85  cl::desc("enable register pressure reduce in machine combiner pass."));
86 
87 // Pin the vtable to this file.
88 void PPCInstrInfo::anchor() {}
89 
91  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
92  /* CatchRetOpcode */ -1,
93  STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
94  Subtarget(STI), RI(STI.getTargetMachine()) {}
95 
96 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
97 /// this target when scheduling the DAG.
100  const ScheduleDAG *DAG) const {
101  unsigned Directive =
102  static_cast<const PPCSubtarget *>(STI)->getCPUDirective();
105  const InstrItineraryData *II =
106  static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
107  return new ScoreboardHazardRecognizer(II, DAG);
108  }
109 
111 }
112 
113 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
114 /// to use for this target when scheduling the DAG.
117  const ScheduleDAG *DAG) const {
118  unsigned Directive =
119  DAG->MF.getSubtarget<PPCSubtarget>().getCPUDirective();
120 
121  // FIXME: Leaving this as-is until we have POWER9 scheduling info
123  return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
124 
125  // Most subtargets use a PPC970 recognizer.
128  assert(DAG->TII && "No InstrInfo?");
129 
130  return new PPCHazardRecognizer970(*DAG);
131  }
132 
133  return new ScoreboardHazardRecognizer(II, DAG);
134 }
135 
137  const MachineInstr &MI,
138  unsigned *PredCost) const {
139  if (!ItinData || UseOldLatencyCalc)
140  return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
141 
142  // The default implementation of getInstrLatency calls getStageLatency, but
143  // getStageLatency does not do the right thing for us. While we have
144  // itinerary, most cores are fully pipelined, and so the itineraries only
145  // express the first part of the pipeline, not every stage. Instead, we need
146  // to use the listed output operand cycle number (using operand 0 here, which
147  // is an output).
148 
149  unsigned Latency = 1;
150  unsigned DefClass = MI.getDesc().getSchedClass();
151  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
152  const MachineOperand &MO = MI.getOperand(i);
153  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
154  continue;
155 
156  int Cycle = ItinData->getOperandCycle(DefClass, i);
157  if (Cycle < 0)
158  continue;
159 
160  Latency = std::max(Latency, (unsigned) Cycle);
161  }
162 
163  return Latency;
164 }
165 
167  const MachineInstr &DefMI, unsigned DefIdx,
168  const MachineInstr &UseMI,
169  unsigned UseIdx) const {
170  int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
171  UseMI, UseIdx);
172 
173  if (!DefMI.getParent())
174  return Latency;
175 
176  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
177  Register Reg = DefMO.getReg();
178 
179  bool IsRegCR;
181  const MachineRegisterInfo *MRI =
182  &DefMI.getParent()->getParent()->getRegInfo();
183  IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
184  MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
185  } else {
186  IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
187  PPC::CRBITRCRegClass.contains(Reg);
188  }
189 
190  if (UseMI.isBranch() && IsRegCR) {
191  if (Latency < 0)
192  Latency = getInstrLatency(ItinData, DefMI);
193 
194  // On some cores, there is an additional delay between writing to a condition
195  // register, and using it from a branch.
196  unsigned Directive = Subtarget.getCPUDirective();
197  switch (Directive) {
198  default: break;
199  case PPC::DIR_7400:
200  case PPC::DIR_750:
201  case PPC::DIR_970:
202  case PPC::DIR_E5500:
203  case PPC::DIR_PWR4:
204  case PPC::DIR_PWR5:
205  case PPC::DIR_PWR5X:
206  case PPC::DIR_PWR6:
207  case PPC::DIR_PWR6X:
208  case PPC::DIR_PWR7:
209  case PPC::DIR_PWR8:
210  // FIXME: Is this needed for POWER9?
211  Latency += 2;
212  break;
213  }
214  }
215 
216  return Latency;
217 }
218 
219 /// This is an architecture-specific helper function of reassociateOps.
220 /// Set special operand attributes for new instructions after reassociation.
222  MachineInstr &OldMI2,
223  MachineInstr &NewMI1,
224  MachineInstr &NewMI2) const {
225  // Propagate FP flags from the original instructions.
226  // But clear poison-generating flags because those may not be valid now.
227  uint16_t IntersectedFlags = OldMI1.getFlags() & OldMI2.getFlags();
228  NewMI1.setFlags(IntersectedFlags);
229  NewMI1.clearFlag(MachineInstr::MIFlag::NoSWrap);
230  NewMI1.clearFlag(MachineInstr::MIFlag::NoUWrap);
231  NewMI1.clearFlag(MachineInstr::MIFlag::IsExact);
232 
233  NewMI2.setFlags(IntersectedFlags);
234  NewMI2.clearFlag(MachineInstr::MIFlag::NoSWrap);
235  NewMI2.clearFlag(MachineInstr::MIFlag::NoUWrap);
236  NewMI2.clearFlag(MachineInstr::MIFlag::IsExact);
237 }
238 
240  uint16_t Flags) const {
241  MI.setFlags(Flags);
242  MI.clearFlag(MachineInstr::MIFlag::NoSWrap);
243  MI.clearFlag(MachineInstr::MIFlag::NoUWrap);
244  MI.clearFlag(MachineInstr::MIFlag::IsExact);
245 }
246 
247 // This function does not list all associative and commutative operations, but
248 // only those worth feeding through the machine combiner in an attempt to
249 // reduce the critical path. Mostly, this means floating-point operations,
250 // because they have high latencies(>=5) (compared to other operations, such as
251 // and/or, which are also associative and commutative, but have low latencies).
253  switch (Inst.getOpcode()) {
254  // Floating point:
255  // FP Add:
256  case PPC::FADD:
257  case PPC::FADDS:
258  // FP Multiply:
259  case PPC::FMUL:
260  case PPC::FMULS:
261  // Altivec Add:
262  case PPC::VADDFP:
263  // VSX Add:
264  case PPC::XSADDDP:
265  case PPC::XVADDDP:
266  case PPC::XVADDSP:
267  case PPC::XSADDSP:
268  // VSX Multiply:
269  case PPC::XSMULDP:
270  case PPC::XVMULDP:
271  case PPC::XVMULSP:
272  case PPC::XSMULSP:
273  return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
274  Inst.getFlag(MachineInstr::MIFlag::FmNsz);
275  // Fixed point:
276  // Multiply:
277  case PPC::MULHD:
278  case PPC::MULLD:
279  case PPC::MULHW:
280  case PPC::MULLW:
281  return true;
282  default:
283  return false;
284  }
285 }
286 
287 #define InfoArrayIdxFMAInst 0
288 #define InfoArrayIdxFAddInst 1
289 #define InfoArrayIdxFMULInst 2
290 #define InfoArrayIdxAddOpIdx 3
291 #define InfoArrayIdxMULOpIdx 4
292 #define InfoArrayIdxFSubInst 5
293 // Array keeps info for FMA instructions:
294 // Index 0(InfoArrayIdxFMAInst): FMA instruction;
295 // Index 1(InfoArrayIdxFAddInst): ADD instruction associated with FMA;
296 // Index 2(InfoArrayIdxFMULInst): MUL instruction associated with FMA;
297 // Index 3(InfoArrayIdxAddOpIdx): ADD operand index in FMA operands;
298 // Index 4(InfoArrayIdxMULOpIdx): first MUL operand index in FMA operands;
299 // second MUL operand index is plus 1;
300 // Index 5(InfoArrayIdxFSubInst): SUB instruction associated with FMA.
301 static const uint16_t FMAOpIdxInfo[][6] = {
302  // FIXME: Add more FMA instructions like XSNMADDADP and so on.
303  {PPC::XSMADDADP, PPC::XSADDDP, PPC::XSMULDP, 1, 2, PPC::XSSUBDP},
304  {PPC::XSMADDASP, PPC::XSADDSP, PPC::XSMULSP, 1, 2, PPC::XSSUBSP},
305  {PPC::XVMADDADP, PPC::XVADDDP, PPC::XVMULDP, 1, 2, PPC::XVSUBDP},
306  {PPC::XVMADDASP, PPC::XVADDSP, PPC::XVMULSP, 1, 2, PPC::XVSUBSP},
307  {PPC::FMADD, PPC::FADD, PPC::FMUL, 3, 1, PPC::FSUB},
308  {PPC::FMADDS, PPC::FADDS, PPC::FMULS, 3, 1, PPC::FSUBS}};
309 
310 // Check if an opcode is a FMA instruction. If it is, return the index in array
311 // FMAOpIdxInfo. Otherwise, return -1.
312 int16_t PPCInstrInfo::getFMAOpIdxInfo(unsigned Opcode) const {
313  for (unsigned I = 0; I < array_lengthof(FMAOpIdxInfo); I++)
314  if (FMAOpIdxInfo[I][InfoArrayIdxFMAInst] == Opcode)
315  return I;
316  return -1;
317 }
318 
319 // On PowerPC target, we have two kinds of patterns related to FMA:
320 // 1: Improve ILP.
321 // Try to reassociate FMA chains like below:
322 //
323 // Pattern 1:
324 // A = FADD X, Y (Leaf)
325 // B = FMA A, M21, M22 (Prev)
326 // C = FMA B, M31, M32 (Root)
327 // -->
328 // A = FMA X, M21, M22
329 // B = FMA Y, M31, M32
330 // C = FADD A, B
331 //
332 // Pattern 2:
333 // A = FMA X, M11, M12 (Leaf)
334 // B = FMA A, M21, M22 (Prev)
335 // C = FMA B, M31, M32 (Root)
336 // -->
337 // A = FMUL M11, M12
338 // B = FMA X, M21, M22
339 // D = FMA A, M31, M32
340 // C = FADD B, D
341 //
342 // breaking the dependency between A and B, allowing FMA to be executed in
343 // parallel (or back-to-back in a pipeline) instead of depending on each other.
344 //
345 // 2: Reduce register pressure.
346 // Try to reassociate FMA with FSUB and a constant like below:
347 // C is a floating point const.
348 //
349 // Pattern 1:
350 // A = FSUB X, Y (Leaf)
351 // D = FMA B, C, A (Root)
352 // -->
353 // A = FMA B, Y, -C
354 // D = FMA A, X, C
355 //
356 // Pattern 2:
357 // A = FSUB X, Y (Leaf)
358 // D = FMA B, A, C (Root)
359 // -->
360 // A = FMA B, Y, -C
361 // D = FMA A, X, C
362 //
363 // Before the transformation, A must be assigned with different hardware
364 // register with D. After the transformation, A and D must be assigned with
365 // same hardware register due to TIE attribute of FMA instructions.
366 //
369  bool DoRegPressureReduce) const {
370  MachineBasicBlock *MBB = Root.getParent();
373 
374  auto IsAllOpsVirtualReg = [](const MachineInstr &Instr) {
375  for (const auto &MO : Instr.explicit_operands())
376  if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
377  return false;
378  return true;
379  };
380 
381  auto IsReassociableAddOrSub = [&](const MachineInstr &Instr,
382  unsigned OpType) {
383  if (Instr.getOpcode() !=
384  FMAOpIdxInfo[getFMAOpIdxInfo(Root.getOpcode())][OpType])
385  return false;
386 
387  // Instruction can be reassociated.
388  // fast math flags may prohibit reassociation.
389  if (!(Instr.getFlag(MachineInstr::MIFlag::FmReassoc) &&
390  Instr.getFlag(MachineInstr::MIFlag::FmNsz)))
391  return false;
392 
393  // Instruction operands are virtual registers for reassociation.
394  if (!IsAllOpsVirtualReg(Instr))
395  return false;
396 
397  // For register pressure reassociation, the FSub must have only one use as
398  // we want to delete the sub to save its def.
399  if (OpType == InfoArrayIdxFSubInst &&
400  !MRI->hasOneNonDBGUse(Instr.getOperand(0).getReg()))
401  return false;
402 
403  return true;
404  };
405 
406  auto IsReassociableFMA = [&](const MachineInstr &Instr, int16_t &AddOpIdx,
407  int16_t &MulOpIdx, bool IsLeaf) {
408  int16_t Idx = getFMAOpIdxInfo(Instr.getOpcode());
409  if (Idx < 0)
410  return false;
411 
412  // Instruction can be reassociated.
413  // fast math flags may prohibit reassociation.
414  if (!(Instr.getFlag(MachineInstr::MIFlag::FmReassoc) &&
415  Instr.getFlag(MachineInstr::MIFlag::FmNsz)))
416  return false;
417 
418  // Instruction operands are virtual registers for reassociation.
419  if (!IsAllOpsVirtualReg(Instr))
420  return false;
421 
422  MulOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxMULOpIdx];
423  if (IsLeaf)
424  return true;
425 
426  AddOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxAddOpIdx];
427 
428  const MachineOperand &OpAdd = Instr.getOperand(AddOpIdx);
429  MachineInstr *MIAdd = MRI->getUniqueVRegDef(OpAdd.getReg());
430  // If 'add' operand's def is not in current block, don't do ILP related opt.
431  if (!MIAdd || MIAdd->getParent() != MBB)
432  return false;
433 
434  // If this is not Leaf FMA Instr, its 'add' operand should only have one use
435  // as this fma will be changed later.
436  return IsLeaf ? true : MRI->hasOneNonDBGUse(OpAdd.getReg());
437  };
438 
439  int16_t AddOpIdx = -1;
440  int16_t MulOpIdx = -1;
441 
442  bool IsUsedOnceL = false;
443  bool IsUsedOnceR = false;
444  MachineInstr *MULInstrL = nullptr;
445  MachineInstr *MULInstrR = nullptr;
446 
447  auto IsRPReductionCandidate = [&]() {
448  // Currently, we only support float and double.
449  // FIXME: add support for other types.
450  unsigned Opcode = Root.getOpcode();
451  if (Opcode != PPC::XSMADDASP && Opcode != PPC::XSMADDADP)
452  return false;
453 
454  // Root must be a valid FMA like instruction.
455  // Treat it as leaf as we don't care its add operand.
456  if (IsReassociableFMA(Root, AddOpIdx, MulOpIdx, true)) {
457  assert((MulOpIdx >= 0) && "mul operand index not right!");
459  Root.getOperand(MulOpIdx).getReg(), MRI);
461  Root.getOperand(MulOpIdx + 1).getReg(), MRI);
462  if (!MULRegL && !MULRegR)
463  return false;
464 
465  if (MULRegL && !MULRegR) {
466  MULRegR =
467  TRI->lookThruCopyLike(Root.getOperand(MulOpIdx + 1).getReg(), MRI);
468  IsUsedOnceL = true;
469  } else if (!MULRegL && MULRegR) {
470  MULRegL =
471  TRI->lookThruCopyLike(Root.getOperand(MulOpIdx).getReg(), MRI);
472  IsUsedOnceR = true;
473  } else {
474  IsUsedOnceL = true;
475  IsUsedOnceR = true;
476  }
477 
478  if (!Register::isVirtualRegister(MULRegL) ||
479  !Register::isVirtualRegister(MULRegR))
480  return false;
481 
482  MULInstrL = MRI->getVRegDef(MULRegL);
483  MULInstrR = MRI->getVRegDef(MULRegR);
484  return true;
485  }
486  return false;
487  };
488 
489  // Register pressure fma reassociation patterns.
490  if (DoRegPressureReduce && IsRPReductionCandidate()) {
491  assert((MULInstrL && MULInstrR) && "wrong register preduction candidate!");
492  // Register pressure pattern 1
493  if (isLoadFromConstantPool(MULInstrL) && IsUsedOnceR &&
494  IsReassociableAddOrSub(*MULInstrR, InfoArrayIdxFSubInst)) {
495  LLVM_DEBUG(dbgs() << "add pattern REASSOC_XY_BCA\n");
496  Patterns.push_back(MachineCombinerPattern::REASSOC_XY_BCA);
497  return true;
498  }
499 
500  // Register pressure pattern 2
501  if ((isLoadFromConstantPool(MULInstrR) && IsUsedOnceL &&
502  IsReassociableAddOrSub(*MULInstrL, InfoArrayIdxFSubInst))) {
503  LLVM_DEBUG(dbgs() << "add pattern REASSOC_XY_BAC\n");
504  Patterns.push_back(MachineCombinerPattern::REASSOC_XY_BAC);
505  return true;
506  }
507  }
508 
509  // ILP fma reassociation patterns.
510  // Root must be a valid FMA like instruction.
511  AddOpIdx = -1;
512  if (!IsReassociableFMA(Root, AddOpIdx, MulOpIdx, false))
513  return false;
514 
515  assert((AddOpIdx >= 0) && "add operand index not right!");
516 
517  Register RegB = Root.getOperand(AddOpIdx).getReg();
518  MachineInstr *Prev = MRI->getUniqueVRegDef(RegB);
519 
520  // Prev must be a valid FMA like instruction.
521  AddOpIdx = -1;
522  if (!IsReassociableFMA(*Prev, AddOpIdx, MulOpIdx, false))
523  return false;
524 
525  assert((AddOpIdx >= 0) && "add operand index not right!");
526 
527  Register RegA = Prev->getOperand(AddOpIdx).getReg();
528  MachineInstr *Leaf = MRI->getUniqueVRegDef(RegA);
529  AddOpIdx = -1;
530  if (IsReassociableFMA(*Leaf, AddOpIdx, MulOpIdx, true)) {
532  LLVM_DEBUG(dbgs() << "add pattern REASSOC_XMM_AMM_BMM\n");
533  return true;
534  }
535  if (IsReassociableAddOrSub(*Leaf, InfoArrayIdxFAddInst)) {
536  Patterns.push_back(MachineCombinerPattern::REASSOC_XY_AMM_BMM);
537  LLVM_DEBUG(dbgs() << "add pattern REASSOC_XY_AMM_BMM\n");
538  return true;
539  }
540  return false;
541 }
542 
545  SmallVectorImpl<MachineInstr *> &InsInstrs) const {
546  assert(!InsInstrs.empty() && "Instructions set to be inserted is empty!");
547 
548  MachineFunction *MF = Root.getMF();
552 
553  int16_t Idx = getFMAOpIdxInfo(Root.getOpcode());
554  if (Idx < 0)
555  return;
556 
557  uint16_t FirstMulOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxMULOpIdx];
558 
559  // For now we only need to fix up placeholder for register pressure reduce
560  // patterns.
561  Register ConstReg = 0;
562  switch (P) {
564  ConstReg =
565  TRI->lookThruCopyLike(Root.getOperand(FirstMulOpIdx).getReg(), MRI);
566  break;
568  ConstReg =
569  TRI->lookThruCopyLike(Root.getOperand(FirstMulOpIdx + 1).getReg(), MRI);
570  break;
571  default:
572  // Not register pressure reduce patterns.
573  return;
574  }
575 
576  MachineInstr *ConstDefInstr = MRI->getVRegDef(ConstReg);
577  // Get const value from const pool.
578  const Constant *C = getConstantFromConstantPool(ConstDefInstr);
579  assert(isa<llvm::ConstantFP>(C) && "not a valid constant!");
580 
581  // Get negative fp const.
582  APFloat F1((dyn_cast<ConstantFP>(C))->getValueAPF());
583  F1.changeSign();
584  Constant *NegC = ConstantFP::get(dyn_cast<ConstantFP>(C)->getContext(), F1);
585  Align Alignment = MF->getDataLayout().getPrefTypeAlign(C->getType());
586 
587  // Put negative fp const into constant pool.
588  unsigned ConstPoolIdx = MCP->getConstantPoolIndex(NegC, Alignment);
589 
590  MachineOperand *Placeholder = nullptr;
591  // Record the placeholder PPC::ZERO8 we add in reassociateFMA.
592  for (auto *Inst : InsInstrs) {
593  for (MachineOperand &Operand : Inst->explicit_operands()) {
594  assert(Operand.isReg() && "Invalid instruction in InsInstrs!");
595  if (Operand.getReg() == PPC::ZERO8) {
596  Placeholder = &Operand;
597  break;
598  }
599  }
600  }
601 
602  assert(Placeholder && "Placeholder does not exist!");
603 
604  // Generate instructions to load the const fp from constant pool.
605  // We only support PPC64 and medium code model.
606  Register LoadNewConst =
607  generateLoadForNewConst(ConstPoolIdx, &Root, C->getType(), InsInstrs);
608 
609  // Fill the placeholder with the new load from constant pool.
610  Placeholder->setReg(LoadNewConst);
611 }
612 
614  MachineBasicBlock *MBB, RegisterClassInfo *RegClassInfo) const {
615 
617  return false;
618 
619  // Currently, we only enable register pressure reducing in machine combiner
620  // for: 1: PPC64; 2: Code Model is Medium; 3: Power9 which also has vector
621  // support.
622  //
623  // So we need following instructions to access a TOC entry:
624  //
625  // %6:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, %const.0
626  // %7:vssrc = DFLOADf32 target-flags(ppc-toc-lo) %const.0,
627  // killed %6:g8rc_and_g8rc_nox0, implicit $x2 :: (load 4 from constant-pool)
628  //
629  // FIXME: add more supported targets, like Small and Large code model, PPC32,
630  // AIX.
631  if (!(Subtarget.isPPC64() && Subtarget.hasP9Vector() &&
633  return false;
634 
636  MachineFunction *MF = MBB->getParent();
638 
639  auto GetMBBPressure = [&](MachineBasicBlock *MBB) -> std::vector<unsigned> {
640  RegionPressure Pressure;
641  RegPressureTracker RPTracker(Pressure);
642 
643  // Initialize the register pressure tracker.
644  RPTracker.init(MBB->getParent(), RegClassInfo, nullptr, MBB, MBB->end(),
645  /*TrackLaneMasks*/ false, /*TrackUntiedDefs=*/true);
646 
648  MIE = MBB->instr_begin();
649  MII != MIE; --MII) {
650  MachineInstr &MI = *std::prev(MII);
651  if (MI.isDebugValue() || MI.isDebugLabel())
652  continue;
653  RegisterOperands RegOpers;
654  RegOpers.collect(MI, *TRI, *MRI, false, false);
655  RPTracker.recedeSkipDebugValues();
656  assert(&*RPTracker.getPos() == &MI && "RPTracker sync error!");
657  RPTracker.recede(RegOpers);
658  }
659 
660  // Close the RPTracker to finalize live ins.
661  RPTracker.closeRegion();
662 
663  return RPTracker.getPressure().MaxSetPressure;
664  };
665 
666  // For now we only care about float and double type fma.
667  unsigned VSSRCLimit = TRI->getRegPressureSetLimit(
668  *MBB->getParent(), PPC::RegisterPressureSets::VSSRC);
669 
670  // Only reduce register pressure when pressure is high.
671  return GetMBBPressure(MBB)[PPC::RegisterPressureSets::VSSRC] >
672  (float)VSSRCLimit * FMARPFactor;
673 }
674 
675 bool PPCInstrInfo::isLoadFromConstantPool(MachineInstr *I) const {
676  // I has only one memory operand which is load from constant pool.
677  if (!I->hasOneMemOperand())
678  return false;
679 
680  MachineMemOperand *Op = I->memoperands()[0];
681  return Op->isLoad() && Op->getPseudoValue() &&
682  Op->getPseudoValue()->kind() == PseudoSourceValue::ConstantPool;
683 }
684 
685 Register PPCInstrInfo::generateLoadForNewConst(
686  unsigned Idx, MachineInstr *MI, Type *Ty,
687  SmallVectorImpl<MachineInstr *> &InsInstrs) const {
688  // Now we only support PPC64, Medium code model and P9 with vector.
689  // We have immutable pattern to access const pool. See function
690  // shouldReduceRegisterPressure.
691  assert((Subtarget.isPPC64() && Subtarget.hasP9Vector() &&
692  Subtarget.getTargetMachine().getCodeModel() == CodeModel::Medium) &&
693  "Target not supported!\n");
694 
695  MachineFunction *MF = MI->getMF();
697 
698  // Generate ADDIStocHA8
699  Register VReg1 = MRI->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass);
700  MachineInstrBuilder TOCOffset =
701  BuildMI(*MF, MI->getDebugLoc(), get(PPC::ADDIStocHA8), VReg1)
702  .addReg(PPC::X2)
703  .addConstantPoolIndex(Idx);
704 
705  assert((Ty->isFloatTy() || Ty->isDoubleTy()) &&
706  "Only float and double are supported!");
707 
708  unsigned LoadOpcode;
709  // Should be float type or double type.
710  if (Ty->isFloatTy())
711  LoadOpcode = PPC::DFLOADf32;
712  else
713  LoadOpcode = PPC::DFLOADf64;
714 
715  const TargetRegisterClass *RC = MRI->getRegClass(MI->getOperand(0).getReg());
716  Register VReg2 = MRI->createVirtualRegister(RC);
719  Ty->getScalarSizeInBits() / 8, MF->getDataLayout().getPrefTypeAlign(Ty));
720 
721  // Generate Load from constant pool.
723  BuildMI(*MF, MI->getDebugLoc(), get(LoadOpcode), VReg2)
725  .addReg(VReg1, getKillRegState(true))
726  .addMemOperand(MMO);
727 
728  Load->getOperand(1).setTargetFlags(PPCII::MO_TOC_LO);
729 
730  // Insert the toc load instructions into InsInstrs.
731  InsInstrs.insert(InsInstrs.begin(), Load);
732  InsInstrs.insert(InsInstrs.begin(), TOCOffset);
733  return VReg2;
734 }
735 
736 // This function returns the const value in constant pool if the \p I is a load
737 // from constant pool.
738 const Constant *
739 PPCInstrInfo::getConstantFromConstantPool(MachineInstr *I) const {
740  MachineFunction *MF = I->getMF();
743  assert(I->mayLoad() && "Should be a load instruction.\n");
744  for (auto MO : I->uses()) {
745  if (!MO.isReg())
746  continue;
747  Register Reg = MO.getReg();
748  if (Reg == 0 || !Register::isVirtualRegister(Reg))
749  continue;
750  // Find the toc address.
752  for (auto MO2 : DefMI->uses())
753  if (MO2.isCPI())
754  return (MCP->getConstants())[MO2.getIndex()].Val.ConstVal;
755  }
756  return nullptr;
757 }
758 
761  bool DoRegPressureReduce) const {
762  // Using the machine combiner in this way is potentially expensive, so
763  // restrict to when aggressive optimizations are desired.
765  return false;
766 
767  if (getFMAPatterns(Root, Patterns, DoRegPressureReduce))
768  return true;
769 
770  return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns,
771  DoRegPressureReduce);
772 }
773 
778  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
779  switch (Pattern) {
784  reassociateFMA(Root, Pattern, InsInstrs, DelInstrs, InstrIdxForVirtReg);
785  break;
786  default:
787  // Reassociate default patterns.
789  DelInstrs, InstrIdxForVirtReg);
790  break;
791  }
792 }
793 
794 void PPCInstrInfo::reassociateFMA(
798  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
799  MachineFunction *MF = Root.getMF();
802  MachineOperand &OpC = Root.getOperand(0);
803  Register RegC = OpC.getReg();
804  const TargetRegisterClass *RC = MRI.getRegClass(RegC);
805  MRI.constrainRegClass(RegC, RC);
806 
807  unsigned FmaOp = Root.getOpcode();
808  int16_t Idx = getFMAOpIdxInfo(FmaOp);
809  assert(Idx >= 0 && "Root must be a FMA instruction");
810 
811  bool IsILPReassociate =
814 
815  uint16_t AddOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxAddOpIdx];
816  uint16_t FirstMulOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxMULOpIdx];
817 
818  MachineInstr *Prev = nullptr;
819  MachineInstr *Leaf = nullptr;
820  switch (Pattern) {
821  default:
822  llvm_unreachable("not recognized pattern!");
825  Prev = MRI.getUniqueVRegDef(Root.getOperand(AddOpIdx).getReg());
826  Leaf = MRI.getUniqueVRegDef(Prev->getOperand(AddOpIdx).getReg());
827  break;
829  Register MULReg =
830  TRI->lookThruCopyLike(Root.getOperand(FirstMulOpIdx).getReg(), &MRI);
831  Leaf = MRI.getVRegDef(MULReg);
832  break;
833  }
835  Register MULReg = TRI->lookThruCopyLike(
836  Root.getOperand(FirstMulOpIdx + 1).getReg(), &MRI);
837  Leaf = MRI.getVRegDef(MULReg);
838  break;
839  }
840  }
841 
842  uint16_t IntersectedFlags = 0;
843  if (IsILPReassociate)
844  IntersectedFlags = Root.getFlags() & Prev->getFlags() & Leaf->getFlags();
845  else
846  IntersectedFlags = Root.getFlags() & Leaf->getFlags();
847 
848  auto GetOperandInfo = [&](const MachineOperand &Operand, Register &Reg,
849  bool &KillFlag) {
850  Reg = Operand.getReg();
852  KillFlag = Operand.isKill();
853  };
854 
855  auto GetFMAInstrInfo = [&](const MachineInstr &Instr, Register &MulOp1,
856  Register &MulOp2, Register &AddOp,
857  bool &MulOp1KillFlag, bool &MulOp2KillFlag,
858  bool &AddOpKillFlag) {
859  GetOperandInfo(Instr.getOperand(FirstMulOpIdx), MulOp1, MulOp1KillFlag);
860  GetOperandInfo(Instr.getOperand(FirstMulOpIdx + 1), MulOp2, MulOp2KillFlag);
861  GetOperandInfo(Instr.getOperand(AddOpIdx), AddOp, AddOpKillFlag);
862  };
863 
864  Register RegM11, RegM12, RegX, RegY, RegM21, RegM22, RegM31, RegM32, RegA11,
865  RegA21, RegB;
866  bool KillX = false, KillY = false, KillM11 = false, KillM12 = false,
867  KillM21 = false, KillM22 = false, KillM31 = false, KillM32 = false,
868  KillA11 = false, KillA21 = false, KillB = false;
869 
870  GetFMAInstrInfo(Root, RegM31, RegM32, RegB, KillM31, KillM32, KillB);
871 
872  if (IsILPReassociate)
873  GetFMAInstrInfo(*Prev, RegM21, RegM22, RegA21, KillM21, KillM22, KillA21);
874 
876  GetFMAInstrInfo(*Leaf, RegM11, RegM12, RegA11, KillM11, KillM12, KillA11);
877  GetOperandInfo(Leaf->getOperand(AddOpIdx), RegX, KillX);
879  GetOperandInfo(Leaf->getOperand(1), RegX, KillX);
880  GetOperandInfo(Leaf->getOperand(2), RegY, KillY);
881  } else {
882  // Get FSUB instruction info.
883  GetOperandInfo(Leaf->getOperand(1), RegX, KillX);
884  GetOperandInfo(Leaf->getOperand(2), RegY, KillY);
885  }
886 
887  // Create new virtual registers for the new results instead of
888  // recycling legacy ones because the MachineCombiner's computation of the
889  // critical path requires a new register definition rather than an existing
890  // one.
891  // For register pressure reassociation, we only need create one virtual
892  // register for the new fma.
893  Register NewVRA = MRI.createVirtualRegister(RC);
894  InstrIdxForVirtReg.insert(std::make_pair(NewVRA, 0));
895 
896  Register NewVRB = 0;
897  if (IsILPReassociate) {
898  NewVRB = MRI.createVirtualRegister(RC);
899  InstrIdxForVirtReg.insert(std::make_pair(NewVRB, 1));
900  }
901 
902  Register NewVRD = 0;
904  NewVRD = MRI.createVirtualRegister(RC);
905  InstrIdxForVirtReg.insert(std::make_pair(NewVRD, 2));
906  }
907 
908  auto AdjustOperandOrder = [&](MachineInstr *MI, Register RegAdd, bool KillAdd,
909  Register RegMul1, bool KillRegMul1,
910  Register RegMul2, bool KillRegMul2) {
911  MI->getOperand(AddOpIdx).setReg(RegAdd);
912  MI->getOperand(AddOpIdx).setIsKill(KillAdd);
913  MI->getOperand(FirstMulOpIdx).setReg(RegMul1);
914  MI->getOperand(FirstMulOpIdx).setIsKill(KillRegMul1);
915  MI->getOperand(FirstMulOpIdx + 1).setReg(RegMul2);
916  MI->getOperand(FirstMulOpIdx + 1).setIsKill(KillRegMul2);
917  };
918 
919  MachineInstrBuilder NewARegPressure, NewCRegPressure;
920  switch (Pattern) {
921  default:
922  llvm_unreachable("not recognized pattern!");
924  // Create new instructions for insertion.
925  MachineInstrBuilder MINewB =
926  BuildMI(*MF, Prev->getDebugLoc(), get(FmaOp), NewVRB)
927  .addReg(RegX, getKillRegState(KillX))
928  .addReg(RegM21, getKillRegState(KillM21))
929  .addReg(RegM22, getKillRegState(KillM22));
930  MachineInstrBuilder MINewA =
931  BuildMI(*MF, Root.getDebugLoc(), get(FmaOp), NewVRA)
932  .addReg(RegY, getKillRegState(KillY))
933  .addReg(RegM31, getKillRegState(KillM31))
934  .addReg(RegM32, getKillRegState(KillM32));
935  // If AddOpIdx is not 1, adjust the order.
936  if (AddOpIdx != 1) {
937  AdjustOperandOrder(MINewB, RegX, KillX, RegM21, KillM21, RegM22, KillM22);
938  AdjustOperandOrder(MINewA, RegY, KillY, RegM31, KillM31, RegM32, KillM32);
939  }
940 
941  MachineInstrBuilder MINewC =
942  BuildMI(*MF, Root.getDebugLoc(),
944  .addReg(NewVRB, getKillRegState(true))
945  .addReg(NewVRA, getKillRegState(true));
946 
947  // Update flags for newly created instructions.
948  setSpecialOperandAttr(*MINewA, IntersectedFlags);
949  setSpecialOperandAttr(*MINewB, IntersectedFlags);
950  setSpecialOperandAttr(*MINewC, IntersectedFlags);
951 
952  // Record new instructions for insertion.
953  InsInstrs.push_back(MINewA);
954  InsInstrs.push_back(MINewB);
955  InsInstrs.push_back(MINewC);
956  break;
957  }
959  assert(NewVRD && "new FMA register not created!");
960  // Create new instructions for insertion.
961  MachineInstrBuilder MINewA =
962  BuildMI(*MF, Leaf->getDebugLoc(),
963  get(FMAOpIdxInfo[Idx][InfoArrayIdxFMULInst]), NewVRA)
964  .addReg(RegM11, getKillRegState(KillM11))
965  .addReg(RegM12, getKillRegState(KillM12));
966  MachineInstrBuilder MINewB =
967  BuildMI(*MF, Prev->getDebugLoc(), get(FmaOp), NewVRB)
968  .addReg(RegX, getKillRegState(KillX))
969  .addReg(RegM21, getKillRegState(KillM21))
970  .addReg(RegM22, getKillRegState(KillM22));
971  MachineInstrBuilder MINewD =
972  BuildMI(*MF, Root.getDebugLoc(), get(FmaOp), NewVRD)
973  .addReg(NewVRA, getKillRegState(true))
974  .addReg(RegM31, getKillRegState(KillM31))
975  .addReg(RegM32, getKillRegState(KillM32));
976  // If AddOpIdx is not 1, adjust the order.
977  if (AddOpIdx != 1) {
978  AdjustOperandOrder(MINewB, RegX, KillX, RegM21, KillM21, RegM22, KillM22);
979  AdjustOperandOrder(MINewD, NewVRA, true, RegM31, KillM31, RegM32,
980  KillM32);
981  }
982 
983  MachineInstrBuilder MINewC =
984  BuildMI(*MF, Root.getDebugLoc(),
986  .addReg(NewVRB, getKillRegState(true))
987  .addReg(NewVRD, getKillRegState(true));
988 
989  // Update flags for newly created instructions.
990  setSpecialOperandAttr(*MINewA, IntersectedFlags);
991  setSpecialOperandAttr(*MINewB, IntersectedFlags);
992  setSpecialOperandAttr(*MINewD, IntersectedFlags);
993  setSpecialOperandAttr(*MINewC, IntersectedFlags);
994 
995  // Record new instructions for insertion.
996  InsInstrs.push_back(MINewA);
997  InsInstrs.push_back(MINewB);
998  InsInstrs.push_back(MINewD);
999  InsInstrs.push_back(MINewC);
1000  break;
1001  }
1004  Register VarReg;
1005  bool KillVarReg = false;
1007  VarReg = RegM31;
1008  KillVarReg = KillM31;
1009  } else {
1010  VarReg = RegM32;
1011  KillVarReg = KillM32;
1012  }
1013  // We don't want to get negative const from memory pool too early, as the
1014  // created entry will not be deleted even if it has no users. Since all
1015  // operand of Leaf and Root are virtual register, we use zero register
1016  // here as a placeholder. When the InsInstrs is selected in
1017  // MachineCombiner, we call finalizeInsInstrs to replace the zero register
1018  // with a virtual register which is a load from constant pool.
1019  NewARegPressure = BuildMI(*MF, Root.getDebugLoc(), get(FmaOp), NewVRA)
1020  .addReg(RegB, getKillRegState(RegB))
1021  .addReg(RegY, getKillRegState(KillY))
1022  .addReg(PPC::ZERO8);
1023  NewCRegPressure = BuildMI(*MF, Root.getDebugLoc(), get(FmaOp), RegC)
1024  .addReg(NewVRA, getKillRegState(true))
1025  .addReg(RegX, getKillRegState(KillX))
1026  .addReg(VarReg, getKillRegState(KillVarReg));
1027  // For now, we only support xsmaddadp/xsmaddasp, their add operand are
1028  // both at index 1, no need to adjust.
1029  // FIXME: when add more fma instructions support, like fma/fmas, adjust
1030  // the operand index here.
1031  break;
1032  }
1033  }
1034 
1035  if (!IsILPReassociate) {
1036  setSpecialOperandAttr(*NewARegPressure, IntersectedFlags);
1037  setSpecialOperandAttr(*NewCRegPressure, IntersectedFlags);
1038 
1039  InsInstrs.push_back(NewARegPressure);
1040  InsInstrs.push_back(NewCRegPressure);
1041  }
1042 
1043  assert(!InsInstrs.empty() &&
1044  "Insertion instructions set should not be empty!");
1045 
1046  // Record old instructions for deletion.
1047  DelInstrs.push_back(Leaf);
1048  if (IsILPReassociate)
1049  DelInstrs.push_back(Prev);
1050  DelInstrs.push_back(&Root);
1051 }
1052 
1053 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
1055  Register &SrcReg, Register &DstReg,
1056  unsigned &SubIdx) const {
1057  switch (MI.getOpcode()) {
1058  default: return false;
1059  case PPC::EXTSW:
1060  case PPC::EXTSW_32:
1061  case PPC::EXTSW_32_64:
1062  SrcReg = MI.getOperand(1).getReg();
1063  DstReg = MI.getOperand(0).getReg();
1064  SubIdx = PPC::sub_32;
1065  return true;
1066  }
1067 }
1068 
1070  int &FrameIndex) const {
1071  unsigned Opcode = MI.getOpcode();
1072  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1073  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
1074 
1075  if (End != std::find(OpcodesForSpill, End, Opcode)) {
1076  // Check for the operands added by addFrameReference (the immediate is the
1077  // offset which defaults to 0).
1078  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
1079  MI.getOperand(2).isFI()) {
1080  FrameIndex = MI.getOperand(2).getIndex();
1081  return MI.getOperand(0).getReg();
1082  }
1083  }
1084  return 0;
1085 }
1086 
1087 // For opcodes with the ReMaterializable flag set, this function is called to
1088 // verify the instruction is really rematable.
1090  AliasAnalysis *AA) const {
1091  switch (MI.getOpcode()) {
1092  default:
1093  // This function should only be called for opcodes with the ReMaterializable
1094  // flag set.
1095  llvm_unreachable("Unknown rematerializable operation!");
1096  break;
1097  case PPC::LI:
1098  case PPC::LI8:
1099  case PPC::PLI:
1100  case PPC::PLI8:
1101  case PPC::LIS:
1102  case PPC::LIS8:
1103  case PPC::ADDIStocHA:
1104  case PPC::ADDIStocHA8:
1105  case PPC::ADDItocL:
1106  case PPC::LOAD_STACK_GUARD:
1107  case PPC::XXLXORz:
1108  case PPC::XXLXORspz:
1109  case PPC::XXLXORdpz:
1110  case PPC::XXLEQVOnes:
1111  case PPC::XXSPLTI32DX:
1112  case PPC::V_SET0B:
1113  case PPC::V_SET0H:
1114  case PPC::V_SET0:
1115  case PPC::V_SETALLONESB:
1116  case PPC::V_SETALLONESH:
1117  case PPC::V_SETALLONES:
1118  case PPC::CRSET:
1119  case PPC::CRUNSET:
1120  case PPC::XXSETACCZ:
1121  return true;
1122  }
1123  return false;
1124 }
1125 
1127  int &FrameIndex) const {
1128  unsigned Opcode = MI.getOpcode();
1129  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1130  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
1131 
1132  if (End != std::find(OpcodesForSpill, End, Opcode)) {
1133  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
1134  MI.getOperand(2).isFI()) {
1135  FrameIndex = MI.getOperand(2).getIndex();
1136  return MI.getOperand(0).getReg();
1137  }
1138  }
1139  return 0;
1140 }
1141 
1143  unsigned OpIdx1,
1144  unsigned OpIdx2) const {
1145  MachineFunction &MF = *MI.getParent()->getParent();
1146 
1147  // Normal instructions can be commuted the obvious way.
1148  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMI_rec)
1149  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1150  // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
1151  // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
1152  // changing the relative order of the mask operands might change what happens
1153  // to the high-bits of the mask (and, thus, the result).
1154 
1155  // Cannot commute if it has a non-zero rotate count.
1156  if (MI.getOperand(3).getImm() != 0)
1157  return nullptr;
1158 
1159  // If we have a zero rotate count, we have:
1160  // M = mask(MB,ME)
1161  // Op0 = (Op1 & ~M) | (Op2 & M)
1162  // Change this to:
1163  // M = mask((ME+1)&31, (MB-1)&31)
1164  // Op0 = (Op2 & ~M) | (Op1 & M)
1165 
1166  // Swap op1/op2
1167  assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
1168  "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMI_rec.");
1169  Register Reg0 = MI.getOperand(0).getReg();
1170  Register Reg1 = MI.getOperand(1).getReg();
1171  Register Reg2 = MI.getOperand(2).getReg();
1172  unsigned SubReg1 = MI.getOperand(1).getSubReg();
1173  unsigned SubReg2 = MI.getOperand(2).getSubReg();
1174  bool Reg1IsKill = MI.getOperand(1).isKill();
1175  bool Reg2IsKill = MI.getOperand(2).isKill();
1176  bool ChangeReg0 = false;
1177  // If machine instrs are no longer in two-address forms, update
1178  // destination register as well.
1179  if (Reg0 == Reg1) {
1180  // Must be two address instruction!
1181  assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
1182  "Expecting a two-address instruction!");
1183  assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
1184  Reg2IsKill = false;
1185  ChangeReg0 = true;
1186  }
1187 
1188  // Masks.
1189  unsigned MB = MI.getOperand(4).getImm();
1190  unsigned ME = MI.getOperand(5).getImm();
1191 
1192  // We can't commute a trivial mask (there is no way to represent an all-zero
1193  // mask).
1194  if (MB == 0 && ME == 31)
1195  return nullptr;
1196 
1197  if (NewMI) {
1198  // Create a new instruction.
1199  Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
1200  bool Reg0IsDead = MI.getOperand(0).isDead();
1201  return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
1202  .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
1203  .addReg(Reg2, getKillRegState(Reg2IsKill))
1204  .addReg(Reg1, getKillRegState(Reg1IsKill))
1205  .addImm((ME + 1) & 31)
1206  .addImm((MB - 1) & 31);
1207  }
1208 
1209  if (ChangeReg0) {
1210  MI.getOperand(0).setReg(Reg2);
1211  MI.getOperand(0).setSubReg(SubReg2);
1212  }
1213  MI.getOperand(2).setReg(Reg1);
1214  MI.getOperand(1).setReg(Reg2);
1215  MI.getOperand(2).setSubReg(SubReg1);
1216  MI.getOperand(1).setSubReg(SubReg2);
1217  MI.getOperand(2).setIsKill(Reg1IsKill);
1218  MI.getOperand(1).setIsKill(Reg2IsKill);
1219 
1220  // Swap the mask around.
1221  MI.getOperand(4).setImm((ME + 1) & 31);
1222  MI.getOperand(5).setImm((MB - 1) & 31);
1223  return &MI;
1224 }
1225 
1227  unsigned &SrcOpIdx1,
1228  unsigned &SrcOpIdx2) const {
1229  // For VSX A-Type FMA instructions, it is the first two operands that can be
1230  // commuted, however, because the non-encoded tied input operand is listed
1231  // first, the operands to swap are actually the second and third.
1232 
1233  int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
1234  if (AltOpc == -1)
1235  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1236 
1237  // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
1238  // and SrcOpIdx2.
1239  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
1240 }
1241 
1244  // This function is used for scheduling, and the nop wanted here is the type
1245  // that terminates dispatch groups on the POWER cores.
1246  unsigned Directive = Subtarget.getCPUDirective();
1247  unsigned Opcode;
1248  switch (Directive) {
1249  default: Opcode = PPC::NOP; break;
1250  case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
1251  case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
1252  case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
1253  // FIXME: Update when POWER9 scheduling model is ready.
1254  case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
1255  }
1256 
1257  DebugLoc DL;
1258  BuildMI(MBB, MI, DL, get(Opcode));
1259 }
1260 
1261 /// Return the noop instruction to use for a noop.
1263  MCInst Nop;
1264  Nop.setOpcode(PPC::NOP);
1265  return Nop;
1266 }
1267 
1268 // Branch analysis.
1269 // Note: If the condition register is set to CTR or CTR8 then this is a
1270 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
1272  MachineBasicBlock *&TBB,
1273  MachineBasicBlock *&FBB,
1275  bool AllowModify) const {
1276  bool isPPC64 = Subtarget.isPPC64();
1277 
1278  // If the block has no terminators, it just falls into the block after it.
1280  if (I == MBB.end())
1281  return false;
1282 
1283  if (!isUnpredicatedTerminator(*I))
1284  return false;
1285 
1286  if (AllowModify) {
1287  // If the BB ends with an unconditional branch to the fallthrough BB,
1288  // we eliminate the branch instruction.
1289  if (I->getOpcode() == PPC::B &&
1290  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1291  I->eraseFromParent();
1292 
1293  // We update iterator after deleting the last branch.
1295  if (I == MBB.end() || !isUnpredicatedTerminator(*I))
1296  return false;
1297  }
1298  }
1299 
1300  // Get the last instruction in the block.
1301  MachineInstr &LastInst = *I;
1302 
1303  // If there is only one terminator instruction, process it.
1304  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
1305  if (LastInst.getOpcode() == PPC::B) {
1306  if (!LastInst.getOperand(0).isMBB())
1307  return true;
1308  TBB = LastInst.getOperand(0).getMBB();
1309  return false;
1310  } else if (LastInst.getOpcode() == PPC::BCC) {
1311  if (!LastInst.getOperand(2).isMBB())
1312  return true;
1313  // Block ends with fall-through condbranch.
1314  TBB = LastInst.getOperand(2).getMBB();
1315  Cond.push_back(LastInst.getOperand(0));
1316  Cond.push_back(LastInst.getOperand(1));
1317  return false;
1318  } else if (LastInst.getOpcode() == PPC::BC) {
1319  if (!LastInst.getOperand(1).isMBB())
1320  return true;
1321  // Block ends with fall-through condbranch.
1322  TBB = LastInst.getOperand(1).getMBB();
1324  Cond.push_back(LastInst.getOperand(0));
1325  return false;
1326  } else if (LastInst.getOpcode() == PPC::BCn) {
1327  if (!LastInst.getOperand(1).isMBB())
1328  return true;
1329  // Block ends with fall-through condbranch.
1330  TBB = LastInst.getOperand(1).getMBB();
1332  Cond.push_back(LastInst.getOperand(0));
1333  return false;
1334  } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
1335  LastInst.getOpcode() == PPC::BDNZ) {
1336  if (!LastInst.getOperand(0).isMBB())
1337  return true;
1338  if (DisableCTRLoopAnal)
1339  return true;
1340  TBB = LastInst.getOperand(0).getMBB();
1341  Cond.push_back(MachineOperand::CreateImm(1));
1342  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
1343  true));
1344  return false;
1345  } else if (LastInst.getOpcode() == PPC::BDZ8 ||
1346  LastInst.getOpcode() == PPC::BDZ) {
1347  if (!LastInst.getOperand(0).isMBB())
1348  return true;
1349  if (DisableCTRLoopAnal)
1350  return true;
1351  TBB = LastInst.getOperand(0).getMBB();
1352  Cond.push_back(MachineOperand::CreateImm(0));
1353  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
1354  true));
1355  return false;
1356  }
1357 
1358  // Otherwise, don't know what this is.
1359  return true;
1360  }
1361 
1362  // Get the instruction before it if it's a terminator.
1363  MachineInstr &SecondLastInst = *I;
1364 
1365  // If there are three terminators, we don't know what sort of block this is.
1366  if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
1367  return true;
1368 
1369  // If the block ends with PPC::B and PPC:BCC, handle it.
1370  if (SecondLastInst.getOpcode() == PPC::BCC &&
1371  LastInst.getOpcode() == PPC::B) {
1372  if (!SecondLastInst.getOperand(2).isMBB() ||
1373  !LastInst.getOperand(0).isMBB())
1374  return true;
1375  TBB = SecondLastInst.getOperand(2).getMBB();
1376  Cond.push_back(SecondLastInst.getOperand(0));
1377  Cond.push_back(SecondLastInst.getOperand(1));
1378  FBB = LastInst.getOperand(0).getMBB();
1379  return false;
1380  } else if (SecondLastInst.getOpcode() == PPC::BC &&
1381  LastInst.getOpcode() == PPC::B) {
1382  if (!SecondLastInst.getOperand(1).isMBB() ||
1383  !LastInst.getOperand(0).isMBB())
1384  return true;
1385  TBB = SecondLastInst.getOperand(1).getMBB();
1387  Cond.push_back(SecondLastInst.getOperand(0));
1388  FBB = LastInst.getOperand(0).getMBB();
1389  return false;
1390  } else if (SecondLastInst.getOpcode() == PPC::BCn &&
1391  LastInst.getOpcode() == PPC::B) {
1392  if (!SecondLastInst.getOperand(1).isMBB() ||
1393  !LastInst.getOperand(0).isMBB())
1394  return true;
1395  TBB = SecondLastInst.getOperand(1).getMBB();
1397  Cond.push_back(SecondLastInst.getOperand(0));
1398  FBB = LastInst.getOperand(0).getMBB();
1399  return false;
1400  } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
1401  SecondLastInst.getOpcode() == PPC::BDNZ) &&
1402  LastInst.getOpcode() == PPC::B) {
1403  if (!SecondLastInst.getOperand(0).isMBB() ||
1404  !LastInst.getOperand(0).isMBB())
1405  return true;
1406  if (DisableCTRLoopAnal)
1407  return true;
1408  TBB = SecondLastInst.getOperand(0).getMBB();
1409  Cond.push_back(MachineOperand::CreateImm(1));
1410  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
1411  true));
1412  FBB = LastInst.getOperand(0).getMBB();
1413  return false;
1414  } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
1415  SecondLastInst.getOpcode() == PPC::BDZ) &&
1416  LastInst.getOpcode() == PPC::B) {
1417  if (!SecondLastInst.getOperand(0).isMBB() ||
1418  !LastInst.getOperand(0).isMBB())
1419  return true;
1420  if (DisableCTRLoopAnal)
1421  return true;
1422  TBB = SecondLastInst.getOperand(0).getMBB();
1423  Cond.push_back(MachineOperand::CreateImm(0));
1424  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
1425  true));
1426  FBB = LastInst.getOperand(0).getMBB();
1427  return false;
1428  }
1429 
1430  // If the block ends with two PPC:Bs, handle it. The second one is not
1431  // executed, so remove it.
1432  if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
1433  if (!SecondLastInst.getOperand(0).isMBB())
1434  return true;
1435  TBB = SecondLastInst.getOperand(0).getMBB();
1436  I = LastInst;
1437  if (AllowModify)
1438  I->eraseFromParent();
1439  return false;
1440  }
1441 
1442  // Otherwise, can't handle this.
1443  return true;
1444 }
1445 
1447  int *BytesRemoved) const {
1448  assert(!BytesRemoved && "code size not handled");
1449 
1451  if (I == MBB.end())
1452  return 0;
1453 
1454  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
1455  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
1456  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
1457  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
1458  return 0;
1459 
1460  // Remove the branch.
1461  I->eraseFromParent();
1462 
1463  I = MBB.end();
1464 
1465  if (I == MBB.begin()) return 1;
1466  --I;
1467  if (I->getOpcode() != PPC::BCC &&
1468  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
1469  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
1470  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
1471  return 1;
1472 
1473  // Remove the branch.
1474  I->eraseFromParent();
1475  return 2;
1476 }
1477 
1479  MachineBasicBlock *TBB,
1480  MachineBasicBlock *FBB,
1482  const DebugLoc &DL,
1483  int *BytesAdded) const {
1484  // Shouldn't be a fall through.
1485  assert(TBB && "insertBranch must not be told to insert a fallthrough");
1486  assert((Cond.size() == 2 || Cond.size() == 0) &&
1487  "PPC branch conditions have two components!");
1488  assert(!BytesAdded && "code size not handled");
1489 
1490  bool isPPC64 = Subtarget.isPPC64();
1491 
1492  // One-way branch.
1493  if (!FBB) {
1494  if (Cond.empty()) // Unconditional branch
1495  BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
1496  else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
1497  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
1498  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1499  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
1500  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
1501  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
1502  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
1503  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
1504  else // Conditional branch
1505  BuildMI(&MBB, DL, get(PPC::BCC))
1506  .addImm(Cond[0].getImm())
1507  .add(Cond[1])
1508  .addMBB(TBB);
1509  return 1;
1510  }
1511 
1512  // Two-way Conditional Branch.
1513  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
1514  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
1515  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1516  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
1517  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
1518  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
1519  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
1520  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
1521  else
1522  BuildMI(&MBB, DL, get(PPC::BCC))
1523  .addImm(Cond[0].getImm())
1524  .add(Cond[1])
1525  .addMBB(TBB);
1526  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
1527  return 2;
1528 }
1529 
1530 // Select analysis.
1533  Register DstReg, Register TrueReg,
1534  Register FalseReg, int &CondCycles,
1535  int &TrueCycles, int &FalseCycles) const {
1536  if (Cond.size() != 2)
1537  return false;
1538 
1539  // If this is really a bdnz-like condition, then it cannot be turned into a
1540  // select.
1541  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
1542  return false;
1543 
1544  // Check register classes.
1546  const TargetRegisterClass *RC =
1547  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
1548  if (!RC)
1549  return false;
1550 
1551  // isel is for regular integer GPRs only.
1552  if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
1553  !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
1554  !PPC::G8RCRegClass.hasSubClassEq(RC) &&
1555  !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
1556  return false;
1557 
1558  // FIXME: These numbers are for the A2, how well they work for other cores is
1559  // an open question. On the A2, the isel instruction has a 2-cycle latency
1560  // but single-cycle throughput. These numbers are used in combination with
1561  // the MispredictPenalty setting from the active SchedMachineModel.
1562  CondCycles = 1;
1563  TrueCycles = 1;
1564  FalseCycles = 1;
1565 
1566  return true;
1567 }
1568 
1571  const DebugLoc &dl, Register DestReg,
1573  Register FalseReg) const {
1574  assert(Cond.size() == 2 &&
1575  "PPC branch conditions have two components!");
1576 
1577  // Get the register classes.
1579  const TargetRegisterClass *RC =
1580  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
1581  assert(RC && "TrueReg and FalseReg must have overlapping register classes");
1582 
1583  bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
1584  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
1585  assert((Is64Bit ||
1586  PPC::GPRCRegClass.hasSubClassEq(RC) ||
1587  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
1588  "isel is for regular integer GPRs only");
1589 
1590  unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
1591  auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
1592 
1593  unsigned SubIdx = 0;
1594  bool SwapOps = false;
1595  switch (SelectPred) {
1596  case PPC::PRED_EQ:
1597  case PPC::PRED_EQ_MINUS:
1598  case PPC::PRED_EQ_PLUS:
1599  SubIdx = PPC::sub_eq; SwapOps = false; break;
1600  case PPC::PRED_NE:
1601  case PPC::PRED_NE_MINUS:
1602  case PPC::PRED_NE_PLUS:
1603  SubIdx = PPC::sub_eq; SwapOps = true; break;
1604  case PPC::PRED_LT:
1605  case PPC::PRED_LT_MINUS:
1606  case PPC::PRED_LT_PLUS:
1607  SubIdx = PPC::sub_lt; SwapOps = false; break;
1608  case PPC::PRED_GE:
1609  case PPC::PRED_GE_MINUS:
1610  case PPC::PRED_GE_PLUS:
1611  SubIdx = PPC::sub_lt; SwapOps = true; break;
1612  case PPC::PRED_GT:
1613  case PPC::PRED_GT_MINUS:
1614  case PPC::PRED_GT_PLUS:
1615  SubIdx = PPC::sub_gt; SwapOps = false; break;
1616  case PPC::PRED_LE:
1617  case PPC::PRED_LE_MINUS:
1618  case PPC::PRED_LE_PLUS:
1619  SubIdx = PPC::sub_gt; SwapOps = true; break;
1620  case PPC::PRED_UN:
1621  case PPC::PRED_UN_MINUS:
1622  case PPC::PRED_UN_PLUS:
1623  SubIdx = PPC::sub_un; SwapOps = false; break;
1624  case PPC::PRED_NU:
1625  case PPC::PRED_NU_MINUS:
1626  case PPC::PRED_NU_PLUS:
1627  SubIdx = PPC::sub_un; SwapOps = true; break;
1628  case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
1629  case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
1630  }
1631 
1632  Register FirstReg = SwapOps ? FalseReg : TrueReg,
1633  SecondReg = SwapOps ? TrueReg : FalseReg;
1634 
1635  // The first input register of isel cannot be r0. If it is a member
1636  // of a register class that can be r0, then copy it first (the
1637  // register allocator should eliminate the copy).
1638  if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
1639  MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
1640  const TargetRegisterClass *FirstRC =
1641  MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
1642  &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
1643  Register OldFirstReg = FirstReg;
1644  FirstReg = MRI.createVirtualRegister(FirstRC);
1645  BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
1646  .addReg(OldFirstReg);
1647  }
1648 
1649  BuildMI(MBB, MI, dl, get(OpCode), DestReg)
1650  .addReg(FirstReg).addReg(SecondReg)
1651  .addReg(Cond[1].getReg(), 0, SubIdx);
1652 }
1653 
1654 static unsigned getCRBitValue(unsigned CRBit) {
1655  unsigned Ret = 4;
1656  if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
1657  CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
1658  CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
1659  CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
1660  Ret = 3;
1661  if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
1662  CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
1663  CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
1664  CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
1665  Ret = 2;
1666  if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
1667  CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
1668  CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
1669  CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
1670  Ret = 1;
1671  if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
1672  CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
1673  CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
1674  CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
1675  Ret = 0;
1676 
1677  assert(Ret != 4 && "Invalid CR bit register");
1678  return Ret;
1679 }
1680 
1683  const DebugLoc &DL, MCRegister DestReg,
1684  MCRegister SrcReg, bool KillSrc) const {
1685  // We can end up with self copies and similar things as a result of VSX copy
1686  // legalization. Promote them here.
1688  if (PPC::F8RCRegClass.contains(DestReg) &&
1689  PPC::VSRCRegClass.contains(SrcReg)) {
1690  MCRegister SuperReg =
1691  TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
1692 
1693  if (VSXSelfCopyCrash && SrcReg == SuperReg)
1694  llvm_unreachable("nop VSX copy");
1695 
1696  DestReg = SuperReg;
1697  } else if (PPC::F8RCRegClass.contains(SrcReg) &&
1698  PPC::VSRCRegClass.contains(DestReg)) {
1699  MCRegister SuperReg =
1700  TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
1701 
1702  if (VSXSelfCopyCrash && DestReg == SuperReg)
1703  llvm_unreachable("nop VSX copy");
1704 
1705  SrcReg = SuperReg;
1706  }
1707 
1708  // Different class register copy
1709  if (PPC::CRBITRCRegClass.contains(SrcReg) &&
1710  PPC::GPRCRegClass.contains(DestReg)) {
1711  MCRegister CRReg = getCRFromCRBit(SrcReg);
1712  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
1713  getKillRegState(KillSrc);
1714  // Rotate the CR bit in the CR fields to be the least significant bit and
1715  // then mask with 0x1 (MB = ME = 31).
1716  BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
1717  .addReg(DestReg, RegState::Kill)
1718  .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
1719  .addImm(31)
1720  .addImm(31);
1721  return;
1722  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
1723  (PPC::G8RCRegClass.contains(DestReg) ||
1724  PPC::GPRCRegClass.contains(DestReg))) {
1725  bool Is64Bit = PPC::G8RCRegClass.contains(DestReg);
1726  unsigned MvCode = Is64Bit ? PPC::MFOCRF8 : PPC::MFOCRF;
1727  unsigned ShCode = Is64Bit ? PPC::RLWINM8 : PPC::RLWINM;
1728  unsigned CRNum = TRI->getEncodingValue(SrcReg);
1729  BuildMI(MBB, I, DL, get(MvCode), DestReg).addReg(SrcReg);
1730  getKillRegState(KillSrc);
1731  if (CRNum == 7)
1732  return;
1733  // Shift the CR bits to make the CR field in the lowest 4 bits of GRC.
1734  BuildMI(MBB, I, DL, get(ShCode), DestReg)
1735  .addReg(DestReg, RegState::Kill)
1736  .addImm(CRNum * 4 + 4)
1737  .addImm(28)
1738  .addImm(31);
1739  return;
1740  } else if (PPC::G8RCRegClass.contains(SrcReg) &&
1741  PPC::VSFRCRegClass.contains(DestReg)) {
1742  assert(Subtarget.hasDirectMove() &&
1743  "Subtarget doesn't support directmove, don't know how to copy.");
1744  BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
1745  NumGPRtoVSRSpill++;
1746  getKillRegState(KillSrc);
1747  return;
1748  } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
1749  PPC::G8RCRegClass.contains(DestReg)) {
1750  assert(Subtarget.hasDirectMove() &&
1751  "Subtarget doesn't support directmove, don't know how to copy.");
1752  BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
1753  getKillRegState(KillSrc);
1754  return;
1755  } else if (PPC::SPERCRegClass.contains(SrcReg) &&
1756  PPC::GPRCRegClass.contains(DestReg)) {
1757  BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
1758  getKillRegState(KillSrc);
1759  return;
1760  } else if (PPC::GPRCRegClass.contains(SrcReg) &&
1761  PPC::SPERCRegClass.contains(DestReg)) {
1762  BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
1763  getKillRegState(KillSrc);
1764  return;
1765  }
1766 
1767  unsigned Opc;
1768  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
1769  Opc = PPC::OR;
1770  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
1771  Opc = PPC::OR8;
1772  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
1773  Opc = PPC::FMR;
1774  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
1775  Opc = PPC::MCRF;
1776  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
1777  Opc = PPC::VOR;
1778  else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
1779  // There are two different ways this can be done:
1780  // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
1781  // issue in VSU pipeline 0.
1782  // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
1783  // can go to either pipeline.
1784  // We'll always use xxlor here, because in practically all cases where
1785  // copies are generated, they are close enough to some use that the
1786  // lower-latency form is preferable.
1787  Opc = PPC::XXLOR;
1788  else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
1789  PPC::VSSRCRegClass.contains(DestReg, SrcReg))
1790  Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf;
1791  else if (Subtarget.pairedVectorMemops() &&
1792  PPC::VSRpRCRegClass.contains(DestReg, SrcReg)) {
1793  if (SrcReg > PPC::VSRp15)
1794  SrcReg = PPC::V0 + (SrcReg - PPC::VSRp16) * 2;
1795  else
1796  SrcReg = PPC::VSL0 + (SrcReg - PPC::VSRp0) * 2;
1797  if (DestReg > PPC::VSRp15)
1798  DestReg = PPC::V0 + (DestReg - PPC::VSRp16) * 2;
1799  else
1800  DestReg = PPC::VSL0 + (DestReg - PPC::VSRp0) * 2;
1801  BuildMI(MBB, I, DL, get(PPC::XXLOR), DestReg).
1802  addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1803  BuildMI(MBB, I, DL, get(PPC::XXLOR), DestReg + 1).
1804  addReg(SrcReg + 1).addReg(SrcReg + 1, getKillRegState(KillSrc));
1805  return;
1806  }
1807  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
1808  Opc = PPC::CROR;
1809  else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
1810  Opc = PPC::EVOR;
1811  else if ((PPC::ACCRCRegClass.contains(DestReg) ||
1812  PPC::UACCRCRegClass.contains(DestReg)) &&
1813  (PPC::ACCRCRegClass.contains(SrcReg) ||
1814  PPC::UACCRCRegClass.contains(SrcReg))) {
1815  // If primed, de-prime the source register, copy the individual registers
1816  // and prime the destination if needed. The vector subregisters are
1817  // vs[(u)acc * 4] - vs[(u)acc * 4 + 3]. If the copy is not a kill and the
1818  // source is primed, we need to re-prime it after the copy as well.
1819  PPCRegisterInfo::emitAccCopyInfo(MBB, DestReg, SrcReg);
1820  bool DestPrimed = PPC::ACCRCRegClass.contains(DestReg);
1821  bool SrcPrimed = PPC::ACCRCRegClass.contains(SrcReg);
1822  MCRegister VSLSrcReg =
1823  PPC::VSL0 + (SrcReg - (SrcPrimed ? PPC::ACC0 : PPC::UACC0)) * 4;
1824  MCRegister VSLDestReg =
1825  PPC::VSL0 + (DestReg - (DestPrimed ? PPC::ACC0 : PPC::UACC0)) * 4;
1826  if (SrcPrimed)
1827  BuildMI(MBB, I, DL, get(PPC::XXMFACC), SrcReg).addReg(SrcReg);
1828  for (unsigned Idx = 0; Idx < 4; Idx++)
1829  BuildMI(MBB, I, DL, get(PPC::XXLOR), VSLDestReg + Idx)
1830  .addReg(VSLSrcReg + Idx)
1831  .addReg(VSLSrcReg + Idx, getKillRegState(KillSrc));
1832  if (DestPrimed)
1833  BuildMI(MBB, I, DL, get(PPC::XXMTACC), DestReg).addReg(DestReg);
1834  if (SrcPrimed && !KillSrc)
1835  BuildMI(MBB, I, DL, get(PPC::XXMTACC), SrcReg).addReg(SrcReg);
1836  return;
1837  } else if (PPC::G8pRCRegClass.contains(DestReg) &&
1838  PPC::G8pRCRegClass.contains(SrcReg)) {
1839  // TODO: Handle G8RC to G8pRC (and vice versa) copy.
1840  unsigned DestRegIdx = DestReg - PPC::G8p0;
1841  MCRegister DestRegSub0 = PPC::X0 + 2 * DestRegIdx;
1842  MCRegister DestRegSub1 = PPC::X0 + 2 * DestRegIdx + 1;
1843  unsigned SrcRegIdx = SrcReg - PPC::G8p0;
1844  MCRegister SrcRegSub0 = PPC::X0 + 2 * SrcRegIdx;
1845  MCRegister SrcRegSub1 = PPC::X0 + 2 * SrcRegIdx + 1;
1846  BuildMI(MBB, I, DL, get(PPC::OR8), DestRegSub0)
1847  .addReg(SrcRegSub0)
1848  .addReg(SrcRegSub0, getKillRegState(KillSrc));
1849  BuildMI(MBB, I, DL, get(PPC::OR8), DestRegSub1)
1850  .addReg(SrcRegSub1)
1851  .addReg(SrcRegSub1, getKillRegState(KillSrc));
1852  return;
1853  } else
1854  llvm_unreachable("Impossible reg-to-reg copy");
1855 
1856  const MCInstrDesc &MCID = get(Opc);
1857  if (MCID.getNumOperands() == 3)
1858  BuildMI(MBB, I, DL, MCID, DestReg)
1859  .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1860  else
1861  BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1862 }
1863 
1864 unsigned PPCInstrInfo::getSpillIndex(const TargetRegisterClass *RC) const {
1865  int OpcodeIndex = 0;
1866 
1867  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1868  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1870  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1871  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1873  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1875  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1877  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1879  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1881  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1883  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1885  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1887  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1889  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1891  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1893  } else if (PPC::ACCRCRegClass.hasSubClassEq(RC)) {
1894  assert(Subtarget.pairedVectorMemops() &&
1895  "Register unexpected when paired memops are disabled.");
1897  } else if (PPC::UACCRCRegClass.hasSubClassEq(RC)) {
1898  assert(Subtarget.pairedVectorMemops() &&
1899  "Register unexpected when paired memops are disabled.");
1901  } else if (PPC::VSRpRCRegClass.hasSubClassEq(RC)) {
1902  assert(Subtarget.pairedVectorMemops() &&
1903  "Register unexpected when paired memops are disabled.");
1905  } else if (PPC::G8pRCRegClass.hasSubClassEq(RC)) {
1907  } else {
1908  llvm_unreachable("Unknown regclass!");
1909  }
1910  return OpcodeIndex;
1911 }
1912 
1913 unsigned
1915  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1916  return OpcodesForSpill[getSpillIndex(RC)];
1917 }
1918 
1919 unsigned
1921  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1922  return OpcodesForSpill[getSpillIndex(RC)];
1923 }
1924 
1925 void PPCInstrInfo::StoreRegToStackSlot(
1926  MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
1927  const TargetRegisterClass *RC,
1928  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1929  unsigned Opcode = getStoreOpcodeForSpill(RC);
1930  DebugLoc DL;
1931 
1932  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1933  FuncInfo->setHasSpills();
1934 
1935  NewMIs.push_back(addFrameReference(
1936  BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1937  FrameIdx));
1938 
1939  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1940  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1941  FuncInfo->setSpillsCR();
1942 
1943  if (isXFormMemOp(Opcode))
1944  FuncInfo->setHasNonRISpills();
1945 }
1946 
1949  bool isKill, int FrameIdx, const TargetRegisterClass *RC,
1950  const TargetRegisterInfo *TRI) const {
1951  MachineFunction &MF = *MBB.getParent();
1953 
1954  StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1955 
1956  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1957  MBB.insert(MI, NewMIs[i]);
1958 
1959  const MachineFrameInfo &MFI = MF.getFrameInfo();
1961  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1963  MFI.getObjectAlign(FrameIdx));
1964  NewMIs.back()->addMemOperand(MF, MMO);
1965 }
1966 
1969  Register SrcReg, bool isKill,
1970  int FrameIdx,
1971  const TargetRegisterClass *RC,
1972  const TargetRegisterInfo *TRI) const {
1973  // We need to avoid a situation in which the value from a VRRC register is
1974  // spilled using an Altivec instruction and reloaded into a VSRC register
1975  // using a VSX instruction. The issue with this is that the VSX
1976  // load/store instructions swap the doublewords in the vector and the Altivec
1977  // ones don't. The register classes on the spill/reload may be different if
1978  // the register is defined using an Altivec instruction and is then used by a
1979  // VSX instruction.
1980  RC = updatedRC(RC);
1981  storeRegToStackSlotNoUpd(MBB, MI, SrcReg, isKill, FrameIdx, RC, TRI);
1982 }
1983 
1984 void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1985  unsigned DestReg, int FrameIdx,
1986  const TargetRegisterClass *RC,
1988  const {
1989  unsigned Opcode = getLoadOpcodeForSpill(RC);
1990  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
1991  FrameIdx));
1992  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1993 
1994  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1995  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1996  FuncInfo->setSpillsCR();
1997 
1998  if (isXFormMemOp(Opcode))
1999  FuncInfo->setHasNonRISpills();
2000 }
2001 
2004  int FrameIdx, const TargetRegisterClass *RC,
2005  const TargetRegisterInfo *TRI) const {
2006  MachineFunction &MF = *MBB.getParent();
2008  DebugLoc DL;
2009  if (MI != MBB.end()) DL = MI->getDebugLoc();
2010 
2011  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2012  FuncInfo->setHasSpills();
2013 
2014  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
2015 
2016  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
2017  MBB.insert(MI, NewMIs[i]);
2018 
2019  const MachineFrameInfo &MFI = MF.getFrameInfo();
2021  MachinePointerInfo::getFixedStack(MF, FrameIdx),
2023  MFI.getObjectAlign(FrameIdx));
2024  NewMIs.back()->addMemOperand(MF, MMO);
2025 }
2026 
2029  Register DestReg, int FrameIdx,
2030  const TargetRegisterClass *RC,
2031  const TargetRegisterInfo *TRI) const {
2032  // We need to avoid a situation in which the value from a VRRC register is
2033  // spilled using an Altivec instruction and reloaded into a VSRC register
2034  // using a VSX instruction. The issue with this is that the VSX
2035  // load/store instructions swap the doublewords in the vector and the Altivec
2036  // ones don't. The register classes on the spill/reload may be different if
2037  // the register is defined using an Altivec instruction and is then used by a
2038  // VSX instruction.
2039  RC = updatedRC(RC);
2040 
2041  loadRegFromStackSlotNoUpd(MBB, MI, DestReg, FrameIdx, RC, TRI);
2042 }
2043 
2044 bool PPCInstrInfo::
2046  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
2047  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
2048  Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
2049  else
2050  // Leave the CR# the same, but invert the condition.
2051  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
2052  return false;
2053 }
2054 
2055 // For some instructions, it is legal to fold ZERO into the RA register field.
2056 // This function performs that fold by replacing the operand with PPC::ZERO,
2057 // it does not consider whether the load immediate zero is no longer in use.
2059  Register Reg) const {
2060  // A zero immediate should always be loaded with a single li.
2061  unsigned DefOpc = DefMI.getOpcode();
2062  if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
2063  return false;
2064  if (!DefMI.getOperand(1).isImm())
2065  return false;
2066  if (DefMI.getOperand(1).getImm() != 0)
2067  return false;
2068 
2069  // Note that we cannot here invert the arguments of an isel in order to fold
2070  // a ZERO into what is presented as the second argument. All we have here
2071  // is the condition bit, and that might come from a CR-logical bit operation.
2072 
2073  const MCInstrDesc &UseMCID = UseMI.getDesc();
2074 
2075  // Only fold into real machine instructions.
2076  if (UseMCID.isPseudo())
2077  return false;
2078 
2079  // We need to find which of the User's operands is to be folded, that will be
2080  // the operand that matches the given register ID.
2081  unsigned UseIdx;
2082  for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
2083  if (UseMI.getOperand(UseIdx).isReg() &&
2084  UseMI.getOperand(UseIdx).getReg() == Reg)
2085  break;
2086 
2087  assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
2088  assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
2089 
2090  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
2091 
2092  // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
2093  // register (which might also be specified as a pointer class kind).
2094  if (UseInfo->isLookupPtrRegClass()) {
2095  if (UseInfo->RegClass /* Kind */ != 1)
2096  return false;
2097  } else {
2098  if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
2099  UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
2100  return false;
2101  }
2102 
2103  // Make sure this is not tied to an output register (or otherwise
2104  // constrained). This is true for ST?UX registers, for example, which
2105  // are tied to their output registers.
2106  if (UseInfo->Constraints != 0)
2107  return false;
2108 
2109  MCRegister ZeroReg;
2110  if (UseInfo->isLookupPtrRegClass()) {
2111  bool isPPC64 = Subtarget.isPPC64();
2112  ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
2113  } else {
2114  ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
2115  PPC::ZERO8 : PPC::ZERO;
2116  }
2117 
2118  UseMI.getOperand(UseIdx).setReg(ZeroReg);
2119  return true;
2120 }
2121 
2122 // Folds zero into instructions which have a load immediate zero as an operand
2123 // but also recognize zero as immediate zero. If the definition of the load
2124 // has no more users it is deleted.
2126  Register Reg, MachineRegisterInfo *MRI) const {
2127  bool Changed = onlyFoldImmediate(UseMI, DefMI, Reg);
2128  if (MRI->use_nodbg_empty(Reg))
2129  DefMI.eraseFromParent();
2130  return Changed;
2131 }
2132 
2135  I != IE; ++I)
2136  if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
2137  return true;
2138  return false;
2139 }
2140 
2141 // We should make sure that, if we're going to predicate both sides of a
2142 // condition (a diamond), that both sides don't define the counter register. We
2143 // can predicate counter-decrement-based branches, but while that predicates
2144 // the branching, it does not predicate the counter decrement. If we tried to
2145 // merge the triangle into one predicated block, we'd decrement the counter
2146 // twice.
2148  unsigned NumT, unsigned ExtraT,
2149  MachineBasicBlock &FMBB,
2150  unsigned NumF, unsigned ExtraF,
2151  BranchProbability Probability) const {
2152  return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
2153 }
2154 
2155 
2157  // The predicated branches are identified by their type, not really by the
2158  // explicit presence of a predicate. Furthermore, some of them can be
2159  // predicated more than once. Because if conversion won't try to predicate
2160  // any instruction which already claims to be predicated (by returning true
2161  // here), always return false. In doing so, we let isPredicable() be the
2162  // final word on whether not the instruction can be (further) predicated.
2163 
2164  return false;
2165 }
2166 
2168  const MachineBasicBlock *MBB,
2169  const MachineFunction &MF) const {
2170  // Set MFFS and MTFSF as scheduling boundary to avoid unexpected code motion
2171  // across them, since some FP operations may change content of FPSCR.
2172  // TODO: Model FPSCR in PPC instruction definitions and remove the workaround
2173  if (MI.getOpcode() == PPC::MFFS || MI.getOpcode() == PPC::MTFSF)
2174  return true;
2176 }
2177 
2179  ArrayRef<MachineOperand> Pred) const {
2180  unsigned OpC = MI.getOpcode();
2181  if (OpC == PPC::BLR || OpC == PPC::BLR8) {
2182  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
2183  bool isPPC64 = Subtarget.isPPC64();
2184  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
2185  : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
2186  // Need add Def and Use for CTR implicit operand.
2187  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2188  .addReg(Pred[1].getReg(), RegState::Implicit)
2189  .addReg(Pred[1].getReg(), RegState::ImplicitDefine);
2190  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
2191  MI.setDesc(get(PPC::BCLR));
2192  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
2193  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
2194  MI.setDesc(get(PPC::BCLRn));
2195  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
2196  } else {
2197  MI.setDesc(get(PPC::BCCLR));
2198  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2199  .addImm(Pred[0].getImm())
2200  .add(Pred[1]);
2201  }
2202 
2203  return true;
2204  } else if (OpC == PPC::B) {
2205  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
2206  bool isPPC64 = Subtarget.isPPC64();
2207  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
2208  : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
2209  // Need add Def and Use for CTR implicit operand.
2210  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2211  .addReg(Pred[1].getReg(), RegState::Implicit)
2212  .addReg(Pred[1].getReg(), RegState::ImplicitDefine);
2213  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
2214  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
2215  MI.RemoveOperand(0);
2216 
2217  MI.setDesc(get(PPC::BC));
2218  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2219  .add(Pred[1])
2220  .addMBB(MBB);
2221  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
2222  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
2223  MI.RemoveOperand(0);
2224 
2225  MI.setDesc(get(PPC::BCn));
2226  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2227  .add(Pred[1])
2228  .addMBB(MBB);
2229  } else {
2230  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
2231  MI.RemoveOperand(0);
2232 
2233  MI.setDesc(get(PPC::BCC));
2234  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2235  .addImm(Pred[0].getImm())
2236  .add(Pred[1])
2237  .addMBB(MBB);
2238  }
2239 
2240  return true;
2241  } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL ||
2242  OpC == PPC::BCTRL8) {
2243  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
2244  llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
2245 
2246  bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
2247  bool isPPC64 = Subtarget.isPPC64();
2248 
2249  if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
2250  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
2251  : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
2252  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
2253  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
2254  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
2255  : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
2256  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
2257  } else {
2258  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
2259  : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
2260  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2261  .addImm(Pred[0].getImm())
2262  .add(Pred[1]);
2263  }
2264 
2265  // Need add Def and Use for LR implicit operand.
2266  if (setLR)
2267  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2268  .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::Implicit)
2269  .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::ImplicitDefine);
2270 
2271  return true;
2272  }
2273 
2274  return false;
2275 }
2276 
2278  ArrayRef<MachineOperand> Pred2) const {
2279  assert(Pred1.size() == 2 && "Invalid PPC first predicate");
2280  assert(Pred2.size() == 2 && "Invalid PPC second predicate");
2281 
2282  if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
2283  return false;
2284  if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
2285  return false;
2286 
2287  // P1 can only subsume P2 if they test the same condition register.
2288  if (Pred1[1].getReg() != Pred2[1].getReg())
2289  return false;
2290 
2291  PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
2292  PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
2293 
2294  if (P1 == P2)
2295  return true;
2296 
2297  // Does P1 subsume P2, e.g. GE subsumes GT.
2298  if (P1 == PPC::PRED_LE &&
2299  (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
2300  return true;
2301  if (P1 == PPC::PRED_GE &&
2302  (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
2303  return true;
2304 
2305  return false;
2306 }
2307 
2309  std::vector<MachineOperand> &Pred,
2310  bool SkipDead) const {
2311  // Note: At the present time, the contents of Pred from this function is
2312  // unused by IfConversion. This implementation follows ARM by pushing the
2313  // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
2314  // predicate, instructions defining CTR or CTR8 are also included as
2315  // predicate-defining instructions.
2316 
2317  const TargetRegisterClass *RCs[] =
2318  { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
2319  &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
2320 
2321  bool Found = false;
2322  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
2323  const MachineOperand &MO = MI.getOperand(i);
2324  for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
2325  const TargetRegisterClass *RC = RCs[c];
2326  if (MO.isReg()) {
2327  if (MO.isDef() && RC->contains(MO.getReg())) {
2328  Pred.push_back(MO);
2329  Found = true;
2330  }
2331  } else if (MO.isRegMask()) {
2332  for (TargetRegisterClass::iterator I = RC->begin(),
2333  IE = RC->end(); I != IE; ++I)
2334  if (MO.clobbersPhysReg(*I)) {
2335  Pred.push_back(MO);
2336  Found = true;
2337  }
2338  }
2339  }
2340  }
2341 
2342  return Found;
2343 }
2344 
2346  Register &SrcReg2, int &Mask,
2347  int &Value) const {
2348  unsigned Opc = MI.getOpcode();
2349 
2350  switch (Opc) {
2351  default: return false;
2352  case PPC::CMPWI:
2353  case PPC::CMPLWI:
2354  case PPC::CMPDI:
2355  case PPC::CMPLDI:
2356  SrcReg = MI.getOperand(1).getReg();
2357  SrcReg2 = 0;
2358  Value = MI.getOperand(2).getImm();
2359  Mask = 0xFFFF;
2360  return true;
2361  case PPC::CMPW:
2362  case PPC::CMPLW:
2363  case PPC::CMPD:
2364  case PPC::CMPLD:
2365  case PPC::FCMPUS:
2366  case PPC::FCMPUD:
2367  SrcReg = MI.getOperand(1).getReg();
2368  SrcReg2 = MI.getOperand(2).getReg();
2369  Value = 0;
2370  Mask = 0;
2371  return true;
2372  }
2373 }
2374 
2376  Register SrcReg2, int Mask, int Value,
2377  const MachineRegisterInfo *MRI) const {
2378  if (DisableCmpOpt)
2379  return false;
2380 
2381  int OpC = CmpInstr.getOpcode();
2382  Register CRReg = CmpInstr.getOperand(0).getReg();
2383 
2384  // FP record forms set CR1 based on the exception status bits, not a
2385  // comparison with zero.
2386  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
2387  return false;
2388 
2390  // The record forms set the condition register based on a signed comparison
2391  // with zero (so says the ISA manual). This is not as straightforward as it
2392  // seems, however, because this is always a 64-bit comparison on PPC64, even
2393  // for instructions that are 32-bit in nature (like slw for example).
2394  // So, on PPC32, for unsigned comparisons, we can use the record forms only
2395  // for equality checks (as those don't depend on the sign). On PPC64,
2396  // we are restricted to equality for unsigned 64-bit comparisons and for
2397  // signed 32-bit comparisons the applicability is more restricted.
2398  bool isPPC64 = Subtarget.isPPC64();
2399  bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
2400  bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
2401  bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
2402 
2403  // Look through copies unless that gets us to a physical register.
2404  Register ActualSrc = TRI->lookThruCopyLike(SrcReg, MRI);
2405  if (ActualSrc.isVirtual())
2406  SrcReg = ActualSrc;
2407 
2408  // Get the unique definition of SrcReg.
2409  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2410  if (!MI) return false;
2411 
2412  bool equalityOnly = false;
2413  bool noSub = false;
2414  if (isPPC64) {
2415  if (is32BitSignedCompare) {
2416  // We can perform this optimization only if MI is sign-extending.
2417  if (isSignExtended(*MI))
2418  noSub = true;
2419  else
2420  return false;
2421  } else if (is32BitUnsignedCompare) {
2422  // We can perform this optimization, equality only, if MI is
2423  // zero-extending.
2424  if (isZeroExtended(*MI)) {
2425  noSub = true;
2426  equalityOnly = true;
2427  } else
2428  return false;
2429  } else
2430  equalityOnly = is64BitUnsignedCompare;
2431  } else
2432  equalityOnly = is32BitUnsignedCompare;
2433 
2434  if (equalityOnly) {
2435  // We need to check the uses of the condition register in order to reject
2436  // non-equality comparisons.
2438  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
2439  I != IE; ++I) {
2440  MachineInstr *UseMI = &*I;
2441  if (UseMI->getOpcode() == PPC::BCC) {
2443  unsigned PredCond = PPC::getPredicateCondition(Pred);
2444  // We ignore hint bits when checking for non-equality comparisons.
2445  if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
2446  return false;
2447  } else if (UseMI->getOpcode() == PPC::ISEL ||
2448  UseMI->getOpcode() == PPC::ISEL8) {
2449  unsigned SubIdx = UseMI->getOperand(3).getSubReg();
2450  if (SubIdx != PPC::sub_eq)
2451  return false;
2452  } else
2453  return false;
2454  }
2455  }
2456 
2457  MachineBasicBlock::iterator I = CmpInstr;
2458 
2459  // Scan forward to find the first use of the compare.
2460  for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
2461  ++I) {
2462  bool FoundUse = false;
2464  J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
2465  J != JE; ++J)
2466  if (&*J == &*I) {
2467  FoundUse = true;
2468  break;
2469  }
2470 
2471  if (FoundUse)
2472  break;
2473  }
2474 
2477 
2478  // There are two possible candidates which can be changed to set CR[01].
2479  // One is MI, the other is a SUB instruction.
2480  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2481  MachineInstr *Sub = nullptr;
2482  if (SrcReg2 != 0)
2483  // MI is not a candidate for CMPrr.
2484  MI = nullptr;
2485  // FIXME: Conservatively refuse to convert an instruction which isn't in the
2486  // same BB as the comparison. This is to allow the check below to avoid calls
2487  // (and other explicit clobbers); instead we should really check for these
2488  // more explicitly (in at least a few predecessors).
2489  else if (MI->getParent() != CmpInstr.getParent())
2490  return false;
2491  else if (Value != 0) {
2492  // The record-form instructions set CR bit based on signed comparison
2493  // against 0. We try to convert a compare against 1 or -1 into a compare
2494  // against 0 to exploit record-form instructions. For example, we change
2495  // the condition "greater than -1" into "greater than or equal to 0"
2496  // and "less than 1" into "less than or equal to 0".
2497 
2498  // Since we optimize comparison based on a specific branch condition,
2499  // we don't optimize if condition code is used by more than once.
2500  if (equalityOnly || !MRI->hasOneUse(CRReg))
2501  return false;
2502 
2503  MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
2504  if (UseMI->getOpcode() != PPC::BCC)
2505  return false;
2506 
2508  unsigned PredCond = PPC::getPredicateCondition(Pred);
2509  unsigned PredHint = PPC::getPredicateHint(Pred);
2510  int16_t Immed = (int16_t)Value;
2511 
2512  // When modifying the condition in the predicate, we propagate hint bits
2513  // from the original predicate to the new one.
2514  if (Immed == -1 && PredCond == PPC::PRED_GT)
2515  // We convert "greater than -1" into "greater than or equal to 0",
2516  // since we are assuming signed comparison by !equalityOnly
2517  Pred = PPC::getPredicate(PPC::PRED_GE, PredHint);
2518  else if (Immed == -1 && PredCond == PPC::PRED_LE)
2519  // We convert "less than or equal to -1" into "less than 0".
2520  Pred = PPC::getPredicate(PPC::PRED_LT, PredHint);
2521  else if (Immed == 1 && PredCond == PPC::PRED_LT)
2522  // We convert "less than 1" into "less than or equal to 0".
2523  Pred = PPC::getPredicate(PPC::PRED_LE, PredHint);
2524  else if (Immed == 1 && PredCond == PPC::PRED_GE)
2525  // We convert "greater than or equal to 1" into "greater than 0".
2526  Pred = PPC::getPredicate(PPC::PRED_GT, PredHint);
2527  else
2528  return false;
2529 
2530  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)), Pred));
2531  }
2532 
2533  // Search for Sub.
2534  --I;
2535 
2536  // Get ready to iterate backward from CmpInstr.
2537  MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
2538 
2539  for (; I != E && !noSub; --I) {
2540  const MachineInstr &Instr = *I;
2541  unsigned IOpC = Instr.getOpcode();
2542 
2543  if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
2544  Instr.readsRegister(PPC::CR0, TRI)))
2545  // This instruction modifies or uses the record condition register after
2546  // the one we want to change. While we could do this transformation, it
2547  // would likely not be profitable. This transformation removes one
2548  // instruction, and so even forcing RA to generate one move probably
2549  // makes it unprofitable.
2550  return false;
2551 
2552  // Check whether CmpInstr can be made redundant by the current instruction.
2553  if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
2554  OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
2555  (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
2556  ((Instr.getOperand(1).getReg() == SrcReg &&
2557  Instr.getOperand(2).getReg() == SrcReg2) ||
2558  (Instr.getOperand(1).getReg() == SrcReg2 &&
2559  Instr.getOperand(2).getReg() == SrcReg))) {
2560  Sub = &*I;
2561  break;
2562  }
2563 
2564  if (I == B)
2565  // The 'and' is below the comparison instruction.
2566  return false;
2567  }
2568 
2569  // Return false if no candidates exist.
2570  if (!MI && !Sub)
2571  return false;
2572 
2573  // The single candidate is called MI.
2574  if (!MI) MI = Sub;
2575 
2576  int NewOpC = -1;
2577  int MIOpC = MI->getOpcode();
2578  if (MIOpC == PPC::ANDI_rec || MIOpC == PPC::ANDI8_rec ||
2579  MIOpC == PPC::ANDIS_rec || MIOpC == PPC::ANDIS8_rec)
2580  NewOpC = MIOpC;
2581  else {
2582  NewOpC = PPC::getRecordFormOpcode(MIOpC);
2583  if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
2584  NewOpC = MIOpC;
2585  }
2586 
2587  // FIXME: On the non-embedded POWER architectures, only some of the record
2588  // forms are fast, and we should use only the fast ones.
2589 
2590  // The defining instruction has a record form (or is already a record
2591  // form). It is possible, however, that we'll need to reverse the condition
2592  // code of the users.
2593  if (NewOpC == -1)
2594  return false;
2595 
2596  // This transformation should not be performed if `nsw` is missing and is not
2597  // `equalityOnly` comparison. Since if there is overflow, sub_lt, sub_gt in
2598  // CRReg do not reflect correct order. If `equalityOnly` is true, sub_eq in
2599  // CRReg can reflect if compared values are equal, this optz is still valid.
2600  if (!equalityOnly && (NewOpC == PPC::SUBF_rec || NewOpC == PPC::SUBF8_rec) &&
2601  Sub && !Sub->getFlag(MachineInstr::NoSWrap))
2602  return false;
2603 
2604  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
2605  // needs to be updated to be based on SUB. Push the condition code
2606  // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
2607  // condition code of these operands will be modified.
2608  // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
2609  // comparison against 0, which may modify predicate.
2610  bool ShouldSwap = false;
2611  if (Sub && Value == 0) {
2612  ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2613  Sub->getOperand(2).getReg() == SrcReg;
2614 
2615  // The operands to subf are the opposite of sub, so only in the fixed-point
2616  // case, invert the order.
2617  ShouldSwap = !ShouldSwap;
2618  }
2619 
2620  if (ShouldSwap)
2622  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
2623  I != IE; ++I) {
2624  MachineInstr *UseMI = &*I;
2625  if (UseMI->getOpcode() == PPC::BCC) {
2627  unsigned PredCond = PPC::getPredicateCondition(Pred);
2628  assert((!equalityOnly ||
2629  PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) &&
2630  "Invalid predicate for equality-only optimization");
2631  (void)PredCond; // To suppress warning in release build.
2632  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
2633  PPC::getSwappedPredicate(Pred)));
2634  } else if (UseMI->getOpcode() == PPC::ISEL ||
2635  UseMI->getOpcode() == PPC::ISEL8) {
2636  unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
2637  assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
2638  "Invalid CR bit for equality-only optimization");
2639 
2640  if (NewSubReg == PPC::sub_lt)
2641  NewSubReg = PPC::sub_gt;
2642  else if (NewSubReg == PPC::sub_gt)
2643  NewSubReg = PPC::sub_lt;
2644 
2645  SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
2646  NewSubReg));
2647  } else // We need to abort on a user we don't understand.
2648  return false;
2649  }
2650  assert(!(Value != 0 && ShouldSwap) &&
2651  "Non-zero immediate support and ShouldSwap"
2652  "may conflict in updating predicate");
2653 
2654  // Create a new virtual register to hold the value of the CR set by the
2655  // record-form instruction. If the instruction was not previously in
2656  // record form, then set the kill flag on the CR.
2657  CmpInstr.eraseFromParent();
2658 
2660  BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
2661  get(TargetOpcode::COPY), CRReg)
2662  .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
2663 
2664  // Even if CR0 register were dead before, it is alive now since the
2665  // instruction we just built uses it.
2666  MI->clearRegisterDeads(PPC::CR0);
2667 
2668  if (MIOpC != NewOpC) {
2669  // We need to be careful here: we're replacing one instruction with
2670  // another, and we need to make sure that we get all of the right
2671  // implicit uses and defs. On the other hand, the caller may be holding
2672  // an iterator to this instruction, and so we can't delete it (this is
2673  // specifically the case if this is the instruction directly after the
2674  // compare).
2675 
2676  // Rotates are expensive instructions. If we're emitting a record-form
2677  // rotate that can just be an andi/andis, we should just emit that.
2678  if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) {
2679  Register GPRRes = MI->getOperand(0).getReg();
2680  int64_t SH = MI->getOperand(2).getImm();
2681  int64_t MB = MI->getOperand(3).getImm();
2682  int64_t ME = MI->getOperand(4).getImm();
2683  // We can only do this if both the start and end of the mask are in the
2684  // same halfword.
2685  bool MBInLoHWord = MB >= 16;
2686  bool MEInLoHWord = ME >= 16;
2687  uint64_t Mask = ~0LLU;
2688 
2689  if (MB <= ME && MBInLoHWord == MEInLoHWord && SH == 0) {
2690  Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2691  // The mask value needs to shift right 16 if we're emitting andis.
2692  Mask >>= MBInLoHWord ? 0 : 16;
2693  NewOpC = MIOpC == PPC::RLWINM
2694  ? (MBInLoHWord ? PPC::ANDI_rec : PPC::ANDIS_rec)
2695  : (MBInLoHWord ? PPC::ANDI8_rec : PPC::ANDIS8_rec);
2696  } else if (MRI->use_empty(GPRRes) && (ME == 31) &&
2697  (ME - MB + 1 == SH) && (MB >= 16)) {
2698  // If we are rotating by the exact number of bits as are in the mask
2699  // and the mask is in the least significant bits of the register,
2700  // that's just an andis. (as long as the GPR result has no uses).
2701  Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
2702  Mask >>= 16;
2703  NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDIS_rec : PPC::ANDIS8_rec;
2704  }
2705  // If we've set the mask, we can transform.
2706  if (Mask != ~0LLU) {
2707  MI->RemoveOperand(4);
2708  MI->RemoveOperand(3);
2709  MI->getOperand(2).setImm(Mask);
2710  NumRcRotatesConvertedToRcAnd++;
2711  }
2712  } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
2713  int64_t MB = MI->getOperand(3).getImm();
2714  if (MB >= 48) {
2715  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2716  NewOpC = PPC::ANDI8_rec;
2717  MI->RemoveOperand(3);
2718  MI->getOperand(2).setImm(Mask);
2719  NumRcRotatesConvertedToRcAnd++;
2720  }
2721  }
2722 
2723  const MCInstrDesc &NewDesc = get(NewOpC);
2724  MI->setDesc(NewDesc);
2725 
2726  if (NewDesc.ImplicitDefs)
2727  for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
2728  *ImpDefs; ++ImpDefs)
2729  if (!MI->definesRegister(*ImpDefs))
2730  MI->addOperand(*MI->getParent()->getParent(),
2731  MachineOperand::CreateReg(*ImpDefs, true, true));
2732  if (NewDesc.ImplicitUses)
2733  for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
2734  *ImpUses; ++ImpUses)
2735  if (!MI->readsRegister(*ImpUses))
2736  MI->addOperand(*MI->getParent()->getParent(),
2737  MachineOperand::CreateReg(*ImpUses, false, true));
2738  }
2739  assert(MI->definesRegister(PPC::CR0) &&
2740  "Record-form instruction does not define cr0?");
2741 
2742  // Modify the condition code of operands in OperandsToUpdate.
2743  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2744  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2745  for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
2746  PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
2747 
2748  for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
2749  SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
2750 
2751  return true;
2752 }
2753 
2756  int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
2757  const TargetRegisterInfo *TRI) const {
2758  const MachineOperand *BaseOp;
2759  OffsetIsScalable = false;
2760  if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI))
2761  return false;
2762  BaseOps.push_back(BaseOp);
2763  return true;
2764 }
2765 
2766 static bool isLdStSafeToCluster(const MachineInstr &LdSt,
2767  const TargetRegisterInfo *TRI) {
2768  // If this is a volatile load/store, don't mess with it.
2769  if (LdSt.hasOrderedMemoryRef() || LdSt.getNumExplicitOperands() != 3)
2770  return false;
2771 
2772  if (LdSt.getOperand(2).isFI())
2773  return true;
2774 
2775  assert(LdSt.getOperand(2).isReg() && "Expected a reg operand.");
2776  // Can't cluster if the instruction modifies the base register
2777  // or it is update form. e.g. ld r2,3(r2)
2778  if (LdSt.modifiesRegister(LdSt.getOperand(2).getReg(), TRI))
2779  return false;
2780 
2781  return true;
2782 }
2783 
2784 // Only cluster instruction pair that have the same opcode, and they are
2785 // clusterable according to PowerPC specification.
2786 static bool isClusterableLdStOpcPair(unsigned FirstOpc, unsigned SecondOpc,
2787  const PPCSubtarget &Subtarget) {
2788  switch (FirstOpc) {
2789  default:
2790  return false;
2791  case PPC::STD:
2792  case PPC::STFD:
2793  case PPC::STXSD:
2794  case PPC::DFSTOREf64:
2795  return FirstOpc == SecondOpc;
2796  // PowerPC backend has opcode STW/STW8 for instruction "stw" to deal with
2797  // 32bit and 64bit instruction selection. They are clusterable pair though
2798  // they are different opcode.
2799  case PPC::STW:
2800  case PPC::STW8:
2801  return SecondOpc == PPC::STW || SecondOpc == PPC::STW8;
2802  }
2803 }
2804 
2807  ArrayRef<const MachineOperand *> BaseOps2, unsigned NumLoads,
2808  unsigned NumBytes) const {
2809 
2810  assert(BaseOps1.size() == 1 && BaseOps2.size() == 1);
2811  const MachineOperand &BaseOp1 = *BaseOps1.front();
2812  const MachineOperand &BaseOp2 = *BaseOps2.front();
2813  assert((BaseOp1.isReg() || BaseOp1.isFI()) &&
2814  "Only base registers and frame indices are supported.");
2815 
2816  // The NumLoads means the number of loads that has been clustered.
2817  // Don't cluster memory op if there are already two ops clustered at least.
2818  if (NumLoads > 2)
2819  return false;
2820 
2821  // Cluster the load/store only when they have the same base
2822  // register or FI.
2823  if ((BaseOp1.isReg() != BaseOp2.isReg()) ||
2824  (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) ||
2825  (BaseOp1.isFI() && BaseOp1.getIndex() != BaseOp2.getIndex()))
2826  return false;
2827 
2828  // Check if the load/store are clusterable according to the PowerPC
2829  // specification.
2830  const MachineInstr &FirstLdSt = *BaseOp1.getParent();
2831  const MachineInstr &SecondLdSt = *BaseOp2.getParent();
2832  unsigned FirstOpc = FirstLdSt.getOpcode();
2833  unsigned SecondOpc = SecondLdSt.getOpcode();
2835  // Cluster the load/store only when they have the same opcode, and they are
2836  // clusterable opcode according to PowerPC specification.
2837  if (!isClusterableLdStOpcPair(FirstOpc, SecondOpc, Subtarget))
2838  return false;
2839 
2840  // Can't cluster load/store that have ordered or volatile memory reference.
2841  if (!isLdStSafeToCluster(FirstLdSt, TRI) ||
2842  !isLdStSafeToCluster(SecondLdSt, TRI))
2843  return false;
2844 
2845  int64_t Offset1 = 0, Offset2 = 0;
2846  unsigned Width1 = 0, Width2 = 0;
2847  const MachineOperand *Base1 = nullptr, *Base2 = nullptr;
2848  if (!getMemOperandWithOffsetWidth(FirstLdSt, Base1, Offset1, Width1, TRI) ||
2849  !getMemOperandWithOffsetWidth(SecondLdSt, Base2, Offset2, Width2, TRI) ||
2850  Width1 != Width2)
2851  return false;
2852 
2853  assert(Base1 == &BaseOp1 && Base2 == &BaseOp2 &&
2854  "getMemOperandWithOffsetWidth return incorrect base op");
2855  // The caller should already have ordered FirstMemOp/SecondMemOp by offset.
2856  assert(Offset1 <= Offset2 && "Caller should have ordered offsets.");
2857  return Offset1 + Width1 == Offset2;
2858 }
2859 
2860 /// GetInstSize - Return the number of bytes of code the specified
2861 /// instruction may be. This returns the maximum number of bytes.
2862 ///
2864  unsigned Opcode = MI.getOpcode();
2865 
2866  if (Opcode == PPC::INLINEASM || Opcode == PPC::INLINEASM_BR) {
2867  const MachineFunction *MF = MI.getParent()->getParent();
2868  const char *AsmStr = MI.getOperand(0).getSymbolName();
2869  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
2870  } else if (Opcode == TargetOpcode::STACKMAP) {
2871  StackMapOpers Opers(&MI);
2872  return Opers.getNumPatchBytes();
2873  } else if (Opcode == TargetOpcode::PATCHPOINT) {
2874  PatchPointOpers Opers(&MI);
2875  return Opers.getNumPatchBytes();
2876  } else {
2877  return get(Opcode).getSize();
2878  }
2879 }
2880 
2881 std::pair<unsigned, unsigned>
2883  const unsigned Mask = PPCII::MO_ACCESS_MASK;
2884  return std::make_pair(TF & Mask, TF & ~Mask);
2885 }
2886 
2889  using namespace PPCII;
2890  static const std::pair<unsigned, const char *> TargetFlags[] = {
2891  {MO_LO, "ppc-lo"},
2892  {MO_HA, "ppc-ha"},
2893  {MO_TPREL_LO, "ppc-tprel-lo"},
2894  {MO_TPREL_HA, "ppc-tprel-ha"},
2895  {MO_DTPREL_LO, "ppc-dtprel-lo"},
2896  {MO_TLSLD_LO, "ppc-tlsld-lo"},
2897  {MO_TOC_LO, "ppc-toc-lo"},
2898  {MO_TLS, "ppc-tls"}};
2899  return makeArrayRef(TargetFlags);
2900 }
2901 
2904  using namespace PPCII;
2905  static const std::pair<unsigned, const char *> TargetFlags[] = {
2906  {MO_PLT, "ppc-plt"},
2907  {MO_PIC_FLAG, "ppc-pic"},
2908  {MO_PCREL_FLAG, "ppc-pcrel"},
2909  {MO_GOT_FLAG, "ppc-got"},
2910  {MO_PCREL_OPT_FLAG, "ppc-opt-pcrel"},
2911  {MO_TLSGD_FLAG, "ppc-tlsgd"},
2912  {MO_TLSLD_FLAG, "ppc-tlsld"},
2913  {MO_TPREL_FLAG, "ppc-tprel"},
2914  {MO_TLSGDM_FLAG, "ppc-tlsgdm"},
2915  {MO_GOT_TLSGD_PCREL_FLAG, "ppc-got-tlsgd-pcrel"},
2916  {MO_GOT_TLSLD_PCREL_FLAG, "ppc-got-tlsld-pcrel"},
2917  {MO_GOT_TPREL_PCREL_FLAG, "ppc-got-tprel-pcrel"}};
2918  return makeArrayRef(TargetFlags);
2919 }
2920 
2921 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
2922 // The VSX versions have the advantage of a full 64-register target whereas
2923 // the FP ones have the advantage of lower latency and higher throughput. So
2924 // what we are after is using the faster instructions in low register pressure
2925 // situations and using the larger register file in high register pressure
2926 // situations.
2928  unsigned UpperOpcode, LowerOpcode;
2929  switch (MI.getOpcode()) {
2930  case PPC::DFLOADf32:
2931  UpperOpcode = PPC::LXSSP;
2932  LowerOpcode = PPC::LFS;
2933  break;
2934  case PPC::DFLOADf64:
2935  UpperOpcode = PPC::LXSD;
2936  LowerOpcode = PPC::LFD;
2937  break;
2938  case PPC::DFSTOREf32:
2939  UpperOpcode = PPC::STXSSP;
2940  LowerOpcode = PPC::STFS;
2941  break;
2942  case PPC::DFSTOREf64:
2943  UpperOpcode = PPC::STXSD;
2944  LowerOpcode = PPC::STFD;
2945  break;
2946  case PPC::XFLOADf32:
2947  UpperOpcode = PPC::LXSSPX;
2948  LowerOpcode = PPC::LFSX;
2949  break;
2950  case PPC::XFLOADf64:
2951  UpperOpcode = PPC::LXSDX;
2952  LowerOpcode = PPC::LFDX;
2953  break;
2954  case PPC::XFSTOREf32:
2955  UpperOpcode = PPC::STXSSPX;
2956  LowerOpcode = PPC::STFSX;
2957  break;
2958  case PPC::XFSTOREf64:
2959  UpperOpcode = PPC::STXSDX;
2960  LowerOpcode = PPC::STFDX;
2961  break;
2962  case PPC::LIWAX:
2963  UpperOpcode = PPC::LXSIWAX;
2964  LowerOpcode = PPC::LFIWAX;
2965  break;
2966  case PPC::LIWZX:
2967  UpperOpcode = PPC::LXSIWZX;
2968  LowerOpcode = PPC::LFIWZX;
2969  break;
2970  case PPC::STIWX:
2971  UpperOpcode = PPC::STXSIWX;
2972  LowerOpcode = PPC::STFIWX;
2973  break;
2974  default:
2975  llvm_unreachable("Unknown Operation!");
2976  }
2977 
2978  Register TargetReg = MI.getOperand(0).getReg();
2979  unsigned Opcode;
2980  if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
2981  (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2982  Opcode = LowerOpcode;
2983  else
2984  Opcode = UpperOpcode;
2985  MI.setDesc(get(Opcode));
2986  return true;
2987 }
2988 
2989 static bool isAnImmediateOperand(const MachineOperand &MO) {
2990  return MO.isCPI() || MO.isGlobal() || MO.isImm();
2991 }
2992 
2994  auto &MBB = *MI.getParent();
2995  auto DL = MI.getDebugLoc();
2996 
2997  switch (MI.getOpcode()) {
2998  case PPC::BUILD_UACC: {
2999  MCRegister ACC = MI.getOperand(0).getReg();
3000  MCRegister UACC = MI.getOperand(1).getReg();
3001  if (ACC - PPC::ACC0 != UACC - PPC::UACC0) {
3002  MCRegister SrcVSR = PPC::VSL0 + (UACC - PPC::UACC0) * 4;
3003  MCRegister DstVSR = PPC::VSL0 + (ACC - PPC::ACC0) * 4;
3004  // FIXME: This can easily be improved to look up to the top of the MBB
3005  // to see if the inputs are XXLOR's. If they are and SrcReg is killed,
3006  // we can just re-target any such XXLOR's to DstVSR + offset.
3007  for (int VecNo = 0; VecNo < 4; VecNo++)
3008  BuildMI(MBB, MI, DL, get(PPC::XXLOR), DstVSR + VecNo)
3009  .addReg(SrcVSR + VecNo)
3010  .addReg(SrcVSR + VecNo);
3011  }
3012  // BUILD_UACC is expanded to 4 copies of the underlying vsx regisers.
3013  // So after building the 4 copies, we can replace the BUILD_UACC instruction
3014  // with a NOP.
3016  }
3017  case PPC::KILL_PAIR: {
3018  MI.setDesc(get(PPC::UNENCODED_NOP));
3019  MI.RemoveOperand(1);
3020  MI.RemoveOperand(0);
3021  return true;
3022  }
3023  case TargetOpcode::LOAD_STACK_GUARD: {
3024  assert(Subtarget.isTargetLinux() &&
3025  "Only Linux target is expected to contain LOAD_STACK_GUARD");
3026  const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
3027  const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
3028  MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
3029  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
3030  .addImm(Offset)
3031  .addReg(Reg);
3032  return true;
3033  }
3034  case PPC::DFLOADf32:
3035  case PPC::DFLOADf64:
3036  case PPC::DFSTOREf32:
3037  case PPC::DFSTOREf64: {
3038  assert(Subtarget.hasP9Vector() &&
3039  "Invalid D-Form Pseudo-ops on Pre-P9 target.");
3040  assert(MI.getOperand(2).isReg() &&
3041  isAnImmediateOperand(MI.getOperand(1)) &&
3042  "D-form op must have register and immediate operands");
3043  return expandVSXMemPseudo(MI);
3044  }
3045  case PPC::XFLOADf32:
3046  case PPC::XFSTOREf32:
3047  case PPC::LIWAX:
3048  case PPC::LIWZX:
3049  case PPC::STIWX: {
3050  assert(Subtarget.hasP8Vector() &&
3051  "Invalid X-Form Pseudo-ops on Pre-P8 target.");
3052  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
3053  "X-form op must have register and register operands");
3054  return expandVSXMemPseudo(MI);
3055  }
3056  case PPC::XFLOADf64:
3057  case PPC::XFSTOREf64: {
3058  assert(Subtarget.hasVSX() &&
3059  "Invalid X-Form Pseudo-ops on target that has no VSX.");
3060  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
3061  "X-form op must have register and register operands");
3062  return expandVSXMemPseudo(MI);
3063  }
3064  case PPC::SPILLTOVSR_LD: {
3065  Register TargetReg = MI.getOperand(0).getReg();
3066  if (PPC::VSFRCRegClass.contains(TargetReg)) {
3067  MI.setDesc(get(PPC::DFLOADf64));
3068  return expandPostRAPseudo(MI);
3069  }
3070  else
3071  MI.setDesc(get(PPC::LD));
3072  return true;
3073  }
3074  case PPC::SPILLTOVSR_ST: {
3075  Register SrcReg = MI.getOperand(0).getReg();
3076  if (PPC::VSFRCRegClass.contains(SrcReg)) {
3077  NumStoreSPILLVSRRCAsVec++;
3078  MI.setDesc(get(PPC::DFSTOREf64));
3079  return expandPostRAPseudo(MI);
3080  } else {
3081  NumStoreSPILLVSRRCAsGpr++;
3082  MI.setDesc(get(PPC::STD));
3083  }
3084  return true;
3085  }
3086  case PPC::SPILLTOVSR_LDX: {
3087  Register TargetReg = MI.getOperand(0).getReg();
3088  if (PPC::VSFRCRegClass.contains(TargetReg))
3089  MI.setDesc(get(PPC::LXSDX));
3090  else
3091  MI.setDesc(get(PPC::LDX));
3092  return true;
3093  }
3094  case PPC::SPILLTOVSR_STX: {
3095  Register SrcReg = MI.getOperand(0).getReg();
3096  if (PPC::VSFRCRegClass.contains(SrcReg)) {
3097  NumStoreSPILLVSRRCAsVec++;
3098  MI.setDesc(get(PPC::STXSDX));
3099  } else {
3100  NumStoreSPILLVSRRCAsGpr++;
3101  MI.setDesc(get(PPC::STDX));
3102  }
3103  return true;
3104  }
3105 
3106  case PPC::CFENCE8: {
3107  auto Val = MI.getOperand(0).getReg();
3108  BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
3109  BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
3111  .addReg(PPC::CR7)
3112  .addImm(1);
3113  MI.setDesc(get(PPC::ISYNC));
3114  MI.RemoveOperand(0);
3115  return true;
3116  }
3117  }
3118  return false;
3119 }
3120 
3121 // Essentially a compile-time implementation of a compare->isel sequence.
3122 // It takes two constants to compare, along with the true/false registers
3123 // and the comparison type (as a subreg to a CR field) and returns one
3124 // of the true/false registers, depending on the comparison results.
3125 static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc,
3126  unsigned TrueReg, unsigned FalseReg,
3127  unsigned CRSubReg) {
3128  // Signed comparisons. The immediates are assumed to be sign-extended.
3129  if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
3130  switch (CRSubReg) {
3131  default: llvm_unreachable("Unknown integer comparison type.");
3132  case PPC::sub_lt:
3133  return Imm1 < Imm2 ? TrueReg : FalseReg;
3134  case PPC::sub_gt:
3135  return Imm1 > Imm2 ? TrueReg : FalseReg;
3136  case PPC::sub_eq:
3137  return Imm1 == Imm2 ? TrueReg : FalseReg;
3138  }
3139  }
3140  // Unsigned comparisons.
3141  else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
3142  switch (CRSubReg) {
3143  default: llvm_unreachable("Unknown integer comparison type.");
3144  case PPC::sub_lt:
3145  return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;
3146  case PPC::sub_gt:
3147  return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;
3148  case PPC::sub_eq:
3149  return Imm1 == Imm2 ? TrueReg : FalseReg;
3150  }
3151  }
3152  return PPC::NoRegister;
3153 }
3154 
3156  unsigned OpNo,
3157  int64_t Imm) const {
3158  assert(MI.getOperand(OpNo).isReg() && "Operand must be a REG");
3159  // Replace the REG with the Immediate.
3160  Register InUseReg = MI.getOperand(OpNo).getReg();
3161  MI.getOperand(OpNo).ChangeToImmediate(Imm);
3162 
3163  // We need to make sure that the MI didn't have any implicit use
3164  // of this REG any more. We don't call MI.implicit_operands().empty() to
3165  // return early, since MI's MCID might be changed in calling context, as a
3166  // result its number of explicit operands may be changed, thus the begin of
3167  // implicit operand is changed.
3169  int UseOpIdx = MI.findRegisterUseOperandIdx(InUseReg, false, TRI);
3170  if (UseOpIdx >= 0) {
3171  MachineOperand &MO = MI.getOperand(UseOpIdx);
3172  if (MO.isImplicit())
3173  // The operands must always be in the following order:
3174  // - explicit reg defs,
3175  // - other explicit operands (reg uses, immediates, etc.),
3176  // - implicit reg defs
3177  // - implicit reg uses
3178  // Therefore, removing the implicit operand won't change the explicit
3179  // operands layout.
3180  MI.RemoveOperand(UseOpIdx);
3181  }
3182 }
3183 
3184 // Replace an instruction with one that materializes a constant (and sets
3185 // CR0 if the original instruction was a record-form instruction).
3187  const LoadImmediateInfo &LII) const {
3188  // Remove existing operands.
3189  int OperandToKeep = LII.SetCR ? 1 : 0;
3190  for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
3191  MI.RemoveOperand(i);
3192 
3193  // Replace the instruction.
3194  if (LII.SetCR) {
3195  MI.setDesc(get(LII.Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec));
3196  // Set the immediate.
3197  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
3198  .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
3199  return;
3200  }
3201  else
3202  MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
3203 
3204  // Set the immediate.
3205  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
3206  .addImm(LII.Imm);
3207 }
3208 
3210  bool &SeenIntermediateUse) const {
3211  assert(!MI.getParent()->getParent()->getRegInfo().isSSA() &&
3212  "Should be called after register allocation.");
3214  MachineBasicBlock::reverse_iterator E = MI.getParent()->rend(), It = MI;
3215  It++;
3216  SeenIntermediateUse = false;
3217  for (; It != E; ++It) {
3218  if (It->modifiesRegister(Reg, TRI))
3219  return &*It;
3220  if (It->readsRegister(Reg, TRI))
3221  SeenIntermediateUse = true;
3222  }
3223  return nullptr;
3224 }
3225 
3226 MachineInstr *PPCInstrInfo::getForwardingDefMI(
3227  MachineInstr &MI,
3228  unsigned &OpNoForForwarding,
3229  bool &SeenIntermediateUse) const {
3230  OpNoForForwarding = ~0U;
3231  MachineInstr *DefMI = nullptr;
3232  MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
3234  // If we're in SSA, get the defs through the MRI. Otherwise, only look
3235  // within the basic block to see if the register is defined using an
3236  // LI/LI8/ADDI/ADDI8.
3237  if (MRI->isSSA()) {
3238  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
3239  if (!MI.getOperand(i).isReg())
3240  continue;
3241  Register Reg = MI.getOperand(i).getReg();
3243  continue;
3244  unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI);
3245  if (Register::isVirtualRegister(TrueReg)) {
3246  DefMI = MRI->getVRegDef(TrueReg);
3247  if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8 ||
3248  DefMI->getOpcode() == PPC::ADDI ||
3249  DefMI->getOpcode() == PPC::ADDI8) {
3250  OpNoForForwarding = i;
3251  // The ADDI and LI operand maybe exist in one instruction at same
3252  // time. we prefer to fold LI operand as LI only has one Imm operand
3253  // and is more possible to be converted. So if current DefMI is
3254  // ADDI/ADDI8, we continue to find possible LI/LI8.
3255  if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8)
3256  break;
3257  }
3258  }
3259  }
3260  } else {
3261  // Looking back through the definition for each operand could be expensive,
3262  // so exit early if this isn't an instruction that either has an immediate
3263  // form or is already an immediate form that we can handle.
3264  ImmInstrInfo III;
3265  unsigned Opc = MI.getOpcode();
3266  bool ConvertibleImmForm =
3267  Opc == PPC::CMPWI || Opc == PPC::CMPLWI || Opc == PPC::CMPDI ||
3268  Opc == PPC::CMPLDI || Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
3269  Opc == PPC::ORI || Opc == PPC::ORI8 || Opc == PPC::XORI ||
3270  Opc == PPC::XORI8 || Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec ||
3271  Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
3272  Opc == PPC::RLWINM || Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8 ||
3273  Opc == PPC::RLWINM8_rec;
3274  bool IsVFReg = (MI.getNumOperands() && MI.getOperand(0).isReg())
3275  ? isVFRegister(MI.getOperand(0).getReg())
3276  : false;
3277  if (!ConvertibleImmForm && !instrHasImmForm(Opc, IsVFReg, III, true))
3278  return nullptr;
3279 
3280  // Don't convert or %X, %Y, %Y since that's just a register move.
3281  if ((Opc == PPC::OR || Opc == PPC::OR8) &&
3282  MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
3283  return nullptr;
3284  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
3285  MachineOperand &MO = MI.getOperand(i);
3286  SeenIntermediateUse = false;
3287  if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
3288  Register Reg = MI.getOperand(i).getReg();
3289  // If we see another use of this reg between the def and the MI,
3290  // we want to flat it so the def isn't deleted.
3291  MachineInstr *DefMI = getDefMIPostRA(Reg, MI, SeenIntermediateUse);
3292  if (DefMI) {
3293  // Is this register defined by some form of add-immediate (including
3294  // load-immediate) within this basic block?
3295  switch (DefMI->getOpcode()) {
3296  default:
3297  break;
3298  case PPC::LI:
3299  case PPC::LI8:
3300  case PPC::ADDItocL:
3301  case PPC::ADDI:
3302  case PPC::ADDI8:
3303  OpNoForForwarding = i;
3304  return DefMI;
3305  }
3306  }
3307  }
3308  }
3309  }
3310  return OpNoForForwarding == ~0U ? nullptr : DefMI;
3311 }
3312 
3313 unsigned PPCInstrInfo::getSpillTarget() const {
3314  // With P10, we may need to spill paired vector registers or accumulator
3315  // registers. MMA implies paired vectors, so we can just check that.
3316  bool IsP10Variant = Subtarget.isISA3_1() || Subtarget.pairedVectorMemops();
3317  return IsP10Variant ? 2 : Subtarget.hasP9Vector() ? 1 : 0;
3318 }
3319 
3320 const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
3321  return StoreSpillOpcodesArray[getSpillTarget()];
3322 }
3323 
3324 const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
3325  return LoadSpillOpcodesArray[getSpillTarget()];
3326 }
3327 
3329  unsigned RegNo) const {
3330  // Conservatively clear kill flag for the register if the instructions are in
3331  // different basic blocks and in SSA form, because the kill flag may no longer
3332  // be right. There is no need to bother with dead flags since defs with no
3333  // uses will be handled by DCE.
3335  if (MRI.isSSA() && (StartMI->getParent() != EndMI->getParent())) {
3336  MRI.clearKillFlags(RegNo);
3337  return;
3338  }
3339 
3340  // Instructions between [StartMI, EndMI] should be in same basic block.
3341  assert((StartMI->getParent() == EndMI->getParent()) &&
3342  "Instructions are not in same basic block");
3343 
3344  // If before RA, StartMI may be def through COPY, we need to adjust it to the
3345  // real def. See function getForwardingDefMI.
3346  if (MRI.isSSA()) {
3347  bool Reads, Writes;
3348  std::tie(Reads, Writes) = StartMI->readsWritesVirtualRegister(RegNo);
3349  if (!Reads && !Writes) {
3351  "Must be a virtual register");
3352  // Get real def and ignore copies.
3353  StartMI = MRI.getVRegDef(RegNo);
3354  }
3355  }
3356 
3357  bool IsKillSet = false;
3358 
3359  auto clearOperandKillInfo = [=] (MachineInstr &MI, unsigned Index) {
3360  MachineOperand &MO = MI.getOperand(Index);
3361  if (MO.isReg() && MO.isUse() && MO.isKill() &&
3362  getRegisterInfo().regsOverlap(MO.getReg(), RegNo))
3363  MO.setIsKill(false);
3364  };
3365 
3366  // Set killed flag for EndMI.
3367  // No need to do anything if EndMI defines RegNo.
3368  int UseIndex =
3369  EndMI->findRegisterUseOperandIdx(RegNo, false, &getRegisterInfo());
3370  if (UseIndex != -1) {
3371  EndMI->getOperand(UseIndex).setIsKill(true);
3372  IsKillSet = true;
3373  // Clear killed flag for other EndMI operands related to RegNo. In some
3374  // upexpected cases, killed may be set multiple times for same register
3375  // operand in same MI.
3376  for (int i = 0, e = EndMI->getNumOperands(); i != e; ++i)
3377  if (i != UseIndex)
3378  clearOperandKillInfo(*EndMI, i);
3379  }
3380 
3381  // Walking the inst in reverse order (EndMI -> StartMI].
3384  // EndMI has been handled above, skip it here.
3385  It++;
3386  MachineOperand *MO = nullptr;
3387  for (; It != E; ++It) {
3388  // Skip insturctions which could not be a def/use of RegNo.
3389  if (It->isDebugInstr() || It->isPosition())
3390  continue;
3391 
3392  // Clear killed flag for all It operands related to RegNo. In some
3393  // upexpected cases, killed may be set multiple times for same register
3394  // operand in same MI.
3395  for (int i = 0, e = It->getNumOperands(); i != e; ++i)
3396  clearOperandKillInfo(*It, i);
3397 
3398  // If killed is not set, set killed for its last use or set dead for its def
3399  // if no use found.
3400  if (!IsKillSet) {
3401  if ((MO = It->findRegisterUseOperand(RegNo, false, &getRegisterInfo()))) {
3402  // Use found, set it killed.
3403  IsKillSet = true;
3404  MO->setIsKill(true);
3405  continue;
3406  } else if ((MO = It->findRegisterDefOperand(RegNo, false, true,
3407  &getRegisterInfo()))) {
3408  // No use found, set dead for its def.
3409  assert(&*It == StartMI && "No new def between StartMI and EndMI.");
3410  MO->setIsDead(true);
3411  break;
3412  }
3413  }
3414 
3415  if ((&*It) == StartMI)
3416  break;
3417  }
3418  // Ensure RegMo liveness is killed after EndMI.
3419  assert((IsKillSet || (MO && MO->isDead())) &&
3420  "RegNo should be killed or dead");
3421 }
3422 
3423 // This opt tries to convert the following imm form to an index form to save an
3424 // add for stack variables.
3425 // Return false if no such pattern found.
3426 //
3427 // ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, OffsetAddi
3428 // ADD instr: ToBeDeletedReg = ADD ToBeChangedReg(killed), ScaleReg
3429 // Imm instr: Reg = op OffsetImm, ToBeDeletedReg(killed)
3430 //
3431 // can be converted to:
3432 //
3433 // new ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, (OffsetAddi + OffsetImm)
3434 // Index instr: Reg = opx ScaleReg, ToBeChangedReg(killed)
3435 //
3436 // In order to eliminate ADD instr, make sure that:
3437 // 1: (OffsetAddi + OffsetImm) must be int16 since this offset will be used in
3438 // new ADDI instr and ADDI can only take int16 Imm.
3439 // 2: ToBeChangedReg must be killed in ADD instr and there is no other use
3440 // between ADDI and ADD instr since its original def in ADDI will be changed
3441 // in new ADDI instr. And also there should be no new def for it between
3442 // ADD and Imm instr as ToBeChangedReg will be used in Index instr.
3443 // 3: ToBeDeletedReg must be killed in Imm instr and there is no other use
3444 // between ADD and Imm instr since ADD instr will be eliminated.
3445 // 4: ScaleReg must not be redefined between ADD and Imm instr since it will be
3446 // moved to Index instr.
3448  MachineFunction *MF = MI.getParent()->getParent();
3450  bool PostRA = !MRI->isSSA();
3451  // Do this opt after PEI which is after RA. The reason is stack slot expansion
3452  // in PEI may expose such opportunities since in PEI, stack slot offsets to
3453  // frame base(OffsetAddi) are determined.
3454  if (!PostRA)
3455  return false;
3456  unsigned ToBeDeletedReg = 0;
3457  int64_t OffsetImm = 0;
3458  unsigned XFormOpcode = 0;
3459  ImmInstrInfo III;
3460 
3461  // Check if Imm instr meets requirement.
3462  if (!isImmInstrEligibleForFolding(MI, ToBeDeletedReg, XFormOpcode, OffsetImm,
3463  III))
3464  return false;
3465 
3466  bool OtherIntermediateUse = false;
3467  MachineInstr *ADDMI = getDefMIPostRA(ToBeDeletedReg, MI, OtherIntermediateUse);
3468 
3469  // Exit if there is other use between ADD and Imm instr or no def found.
3470  if (OtherIntermediateUse || !ADDMI)
3471  return false;
3472 
3473  // Check if ADD instr meets requirement.
3474  if (!isADDInstrEligibleForFolding(*ADDMI))
3475  return false;
3476 
3477  unsigned ScaleRegIdx = 0;
3478  int64_t OffsetAddi = 0;
3479  MachineInstr *ADDIMI = nullptr;
3480 
3481  // Check if there is a valid ToBeChangedReg in ADDMI.
3482  // 1: It must be killed.
3483  // 2: Its definition must be a valid ADDIMI.
3484  // 3: It must satify int16 offset requirement.
3485  if (isValidToBeChangedReg(ADDMI, 1, ADDIMI, OffsetAddi, OffsetImm))
3486  ScaleRegIdx = 2;
3487  else if (isValidToBeChangedReg(ADDMI, 2, ADDIMI, OffsetAddi, OffsetImm))
3488  ScaleRegIdx = 1;
3489  else
3490  return false;
3491 
3492  assert(ADDIMI && "There should be ADDIMI for valid ToBeChangedReg.");
3493  unsigned ToBeChangedReg = ADDIMI->getOperand(0).getReg();
3494  unsigned ScaleReg = ADDMI->getOperand(ScaleRegIdx).getReg();
3495  auto NewDefFor = [&](unsigned Reg, MachineBasicBlock::iterator Start,
3497  for (auto It = ++Start; It != End; It++)
3498  if (It->modifiesRegister(Reg, &getRegisterInfo()))
3499  return true;
3500  return false;
3501  };
3502 
3503  // We are trying to replace the ImmOpNo with ScaleReg. Give up if it is
3504  // treated as special zero when ScaleReg is R0/X0 register.
3505  if (III.ZeroIsSpecialOrig == III.ImmOpNo &&
3506  (ScaleReg == PPC::R0 || ScaleReg == PPC::X0))
3507  return false;
3508 
3509  // Make sure no other def for ToBeChangedReg and ScaleReg between ADD Instr
3510  // and Imm Instr.
3511  if (NewDefFor(ToBeChangedReg, *ADDMI, MI) || NewDefFor(ScaleReg, *ADDMI, MI))
3512  return false;
3513 
3514  // Now start to do the transformation.
3515  LLVM_DEBUG(dbgs() << "Replace instruction: "
3516  << "\n");
3517  LLVM_DEBUG(ADDIMI->dump());
3518  LLVM_DEBUG(ADDMI->dump());
3519  LLVM_DEBUG(MI.dump());
3520  LLVM_DEBUG(dbgs() << "with: "
3521  << "\n");
3522 
3523  // Update ADDI instr.
3524  ADDIMI->getOperand(2).setImm(OffsetAddi + OffsetImm);
3525 
3526  // Update Imm instr.
3527  MI.setDesc(get(XFormOpcode));
3528  MI.getOperand(III.ImmOpNo)
3529  .ChangeToRegister(ScaleReg, false, false,
3530  ADDMI->getOperand(ScaleRegIdx).isKill());
3531 
3532  MI.getOperand(III.OpNoForForwarding)
3533  .ChangeToRegister(ToBeChangedReg, false, false, true);
3534 
3535  // Eliminate ADD instr.
3536  ADDMI->eraseFromParent();
3537 
3538  LLVM_DEBUG(ADDIMI->dump());
3539  LLVM_DEBUG(MI.dump());
3540 
3541  return true;
3542 }
3543 
3545  int64_t &Imm) const {
3546  unsigned Opc = ADDIMI.getOpcode();
3547 
3548  // Exit if the instruction is not ADDI.
3549  if (Opc != PPC::ADDI && Opc != PPC::ADDI8)
3550  return false;
3551 
3552  // The operand may not necessarily be an immediate - it could be a relocation.
3553  if (!ADDIMI.getOperand(2).isImm())
3554  return false;
3555 
3556  Imm = ADDIMI.getOperand(2).getImm();
3557 
3558  return true;
3559 }
3560 
3562  unsigned Opc = ADDMI.getOpcode();
3563 
3564  // Exit if the instruction is not ADD.
3565  return Opc == PPC::ADD4 || Opc == PPC::ADD8;
3566 }
3567 
3569  unsigned &ToBeDeletedReg,
3570  unsigned &XFormOpcode,
3571  int64_t &OffsetImm,
3572  ImmInstrInfo &III) const {
3573  // Only handle load/store.
3574  if (!MI.mayLoadOrStore())
3575  return false;
3576 
3577  unsigned Opc = MI.getOpcode();
3578 
3579  XFormOpcode = RI.getMappedIdxOpcForImmOpc(Opc);
3580 
3581  // Exit if instruction has no index form.
3582  if (XFormOpcode == PPC::INSTRUCTION_LIST_END)
3583  return false;
3584 
3585  // TODO: sync the logic between instrHasImmForm() and ImmToIdxMap.
3586  if (!instrHasImmForm(XFormOpcode, isVFRegister(MI.getOperand(0).getReg()),
3587  III, true))
3588  return false;
3589 
3590  if (!III.IsSummingOperands)
3591  return false;
3592 
3593  MachineOperand ImmOperand = MI.getOperand(III.ImmOpNo);
3594  MachineOperand RegOperand = MI.getOperand(III.OpNoForForwarding);
3595  // Only support imm operands, not relocation slots or others.
3596  if (!ImmOperand.isImm())
3597  return false;
3598 
3599  assert(RegOperand.isReg() && "Instruction format is not right");
3600 
3601  // There are other use for ToBeDeletedReg after Imm instr, can not delete it.
3602  if (!RegOperand.isKill())
3603  return false;
3604 
3605  ToBeDeletedReg = RegOperand.getReg();
3606  OffsetImm = ImmOperand.getImm();
3607 
3608  return true;
3609 }
3610 
3612  MachineInstr *&ADDIMI,
3613  int64_t &OffsetAddi,
3614  int64_t OffsetImm) const {
3615  assert((Index == 1 || Index == 2) && "Invalid operand index for add.");
3616  MachineOperand &MO = ADDMI->getOperand(Index);
3617 
3618  if (!MO.isKill())
3619  return false;
3620 
3621  bool OtherIntermediateUse = false;
3622 
3623  ADDIMI = getDefMIPostRA(MO.getReg(), *ADDMI, OtherIntermediateUse);
3624  // Currently handle only one "add + Imminstr" pair case, exit if other
3625  // intermediate use for ToBeChangedReg found.
3626  // TODO: handle the cases where there are other "add + Imminstr" pairs
3627  // with same offset in Imminstr which is like:
3628  //
3629  // ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, OffsetAddi
3630  // ADD instr1: ToBeDeletedReg1 = ADD ToBeChangedReg, ScaleReg1
3631  // Imm instr1: Reg1 = op1 OffsetImm, ToBeDeletedReg1(killed)
3632  // ADD instr2: ToBeDeletedReg2 = ADD ToBeChangedReg(killed), ScaleReg2
3633  // Imm instr2: Reg2 = op2 OffsetImm, ToBeDeletedReg2(killed)
3634  //
3635  // can be converted to:
3636  //
3637  // new ADDI instr: ToBeChangedReg = ADDI FrameBaseReg,
3638  // (OffsetAddi + OffsetImm)
3639  // Index instr1: Reg1 = opx1 ScaleReg1, ToBeChangedReg
3640  // Index instr2: Reg2 = opx2 ScaleReg2, ToBeChangedReg(killed)
3641 
3642  if (OtherIntermediateUse || !ADDIMI)
3643  return false;
3644  // Check if ADDI instr meets requirement.
3645  if (!isADDIInstrEligibleForFolding(*ADDIMI, OffsetAddi))
3646  return false;
3647 
3648  if (isInt<16>(OffsetAddi + OffsetImm))
3649  return true;
3650  return false;
3651 }
3652 
3653 // If this instruction has an immediate form and one of its operands is a
3654 // result of a load-immediate or an add-immediate, convert it to
3655 // the immediate form if the constant is in range.
3657  MachineInstr **KilledDef) const {
3658  MachineFunction *MF = MI.getParent()->getParent();
3660  bool PostRA = !MRI->isSSA();
3661  bool SeenIntermediateUse = true;
3662  unsigned ForwardingOperand = ~0U;
3663  MachineInstr *DefMI = getForwardingDefMI(MI, ForwardingOperand,
3664  SeenIntermediateUse);
3665  if (!DefMI)
3666  return false;
3667  assert(ForwardingOperand < MI.getNumOperands() &&
3668  "The forwarding operand needs to be valid at this point");
3669  bool IsForwardingOperandKilled = MI.getOperand(ForwardingOperand).isKill();
3670  bool KillFwdDefMI = !SeenIntermediateUse && IsForwardingOperandKilled;
3671  if (KilledDef && KillFwdDefMI)
3672  *KilledDef = DefMI;
3673 
3674  // If this is a imm instruction and its register operands is produced by ADDI,
3675  // put the imm into imm inst directly.
3676  if (RI.getMappedIdxOpcForImmOpc(MI.getOpcode()) !=
3677  PPC::INSTRUCTION_LIST_END &&
3678  transformToNewImmFormFedByAdd(MI, *DefMI, ForwardingOperand))
3679  return true;
3680 
3681  ImmInstrInfo III;
3682  bool IsVFReg = MI.getOperand(0).isReg()
3683  ? isVFRegister(MI.getOperand(0).getReg())
3684  : false;
3685  bool HasImmForm = instrHasImmForm(MI.getOpcode(), IsVFReg, III, PostRA);
3686  // If this is a reg+reg instruction that has a reg+imm form,
3687  // and one of the operands is produced by an add-immediate,
3688  // try to convert it.
3689  if (HasImmForm &&
3690  transformToImmFormFedByAdd(MI, III, ForwardingOperand, *DefMI,
3691  KillFwdDefMI))
3692  return true;
3693 
3694  // If this is a reg+reg instruction that has a reg+imm form,
3695  // and one of the operands is produced by LI, convert it now.
3696  if (HasImmForm &&
3697  transformToImmFormFedByLI(MI, III, ForwardingOperand, *DefMI))
3698  return true;
3699 
3700  // If this is not a reg+reg, but the DefMI is LI/LI8, check if its user MI
3701  // can be simpified to LI.
3702  if (!HasImmForm && simplifyToLI(MI, *DefMI, ForwardingOperand, KilledDef))
3703  return true;
3704 
3705  return false;
3706 }
3707 
3709  MachineInstr **ToErase) const {
3710  MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
3711  unsigned FoldingReg = MI.getOperand(1).getReg();
3712  if (!Register::isVirtualRegister(FoldingReg))
3713  return false;
3714  MachineInstr *SrcMI = MRI->getVRegDef(FoldingReg);
3715  if (SrcMI->getOpcode() != PPC::RLWINM &&
3716  SrcMI->getOpcode() != PPC::RLWINM_rec &&
3717  SrcMI->getOpcode() != PPC::RLWINM8 &&
3718  SrcMI->getOpcode() != PPC::RLWINM8_rec)
3719  return false;
3720  assert((MI.getOperand(2).isImm() && MI.getOperand(3).isImm() &&
3721  MI.getOperand(4).isImm() && SrcMI->getOperand(2).isImm() &&
3722  SrcMI->getOperand(3).isImm() && SrcMI->getOperand(4).isImm()) &&
3723  "Invalid PPC::RLWINM Instruction!");
3724  uint64_t SHSrc = SrcMI->getOperand(2).getImm();
3725  uint64_t SHMI = MI.getOperand(2).getImm();
3726  uint64_t MBSrc = SrcMI->getOperand(3).getImm();
3727  uint64_t MBMI = MI.getOperand(3).getImm();
3728  uint64_t MESrc = SrcMI->getOperand(4).getImm();
3729  uint64_t MEMI = MI.getOperand(4).getImm();
3730 
3731  assert((MEMI < 32 && MESrc < 32 && MBMI < 32 && MBSrc < 32) &&
3732  "Invalid PPC::RLWINM Instruction!");
3733  // If MBMI is bigger than MEMI, we always can not get run of ones.
3734  // RotatedSrcMask non-wrap:
3735  // 0........31|32........63
3736  // RotatedSrcMask: B---E B---E
3737  // MaskMI: -----------|--E B------
3738  // Result: ----- --- (Bad candidate)
3739  //
3740  // RotatedSrcMask wrap:
3741  // 0........31|32........63
3742  // RotatedSrcMask: --E B----|--E B----
3743  // MaskMI: -----------|--E B------
3744  // Result: --- -----|--- ----- (Bad candidate)
3745  //
3746  // One special case is RotatedSrcMask is a full set mask.
3747  // RotatedSrcMask full:
3748  // 0........31|32........63
3749  // RotatedSrcMask: ------EB---|-------EB---
3750  // MaskMI: -----------|--E B------
3751  // Result: -----------|--- ------- (Good candidate)
3752 
3753  // Mark special case.
3754  bool SrcMaskFull = (MBSrc - MESrc == 1) || (MBSrc == 0 && MESrc == 31);
3755 
3756  // For other MBMI > MEMI cases, just return.
3757  if ((MBMI > MEMI) && !SrcMaskFull)
3758  return false;
3759 
3760  // Handle MBMI <= MEMI cases.
3761  APInt MaskMI = APInt::getBitsSetWithWrap(32, 32 - MEMI - 1, 32 - MBMI);
3762  // In MI, we only need low 32 bits of SrcMI, just consider about low 32
3763  // bit of SrcMI mask. Note that in APInt, lowerest bit is at index 0,
3764  // while in PowerPC ISA, lowerest bit is at index 63.
3765  APInt MaskSrc = APInt::getBitsSetWithWrap(32, 32 - MESrc - 1, 32 - MBSrc);
3766 
3767  APInt RotatedSrcMask = MaskSrc.rotl(SHMI);
3768  APInt FinalMask = RotatedSrcMask & MaskMI;
3769  uint32_t NewMB, NewME;
3770  bool Simplified = false;
3771 
3772  // If final mask is 0, MI result should be 0 too.
3773  if (FinalMask.isNullValue()) {
3774  bool Is64Bit =
3775  (MI.getOpcode() == PPC::RLWINM8 || MI.getOpcode() == PPC::RLWINM8_rec);
3776  Simplified = true;
3777  LLVM_DEBUG(dbgs() << "Replace Instr: ");
3778  LLVM_DEBUG(MI.dump());
3779 
3780  if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM8) {
3781  // Replace MI with "LI 0"
3782  MI.RemoveOperand(4);
3783  MI.RemoveOperand(3);
3784  MI.RemoveOperand(2);
3785  MI.getOperand(1).ChangeToImmediate(0);
3786  MI.setDesc(get(Is64Bit ? PPC::LI8 : PPC::LI));
3787  } else {
3788  // Replace MI with "ANDI_rec reg, 0"
3789  MI.RemoveOperand(4);
3790  MI.RemoveOperand(3);
3791  MI.getOperand(2).setImm(0);
3792  MI.setDesc(get(Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec));
3793  MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
3794  if (SrcMI->getOperand(1).isKill()) {
3795  MI.getOperand(1).setIsKill(true);
3796  SrcMI->getOperand(1).setIsKill(false);
3797  } else
3798  // About to replace MI.getOperand(1), clear its kill flag.
3799  MI.getOperand(1).setIsKill(false);
3800  }
3801 
3802  LLVM_DEBUG(dbgs() << "With: ");
3803  LLVM_DEBUG(MI.dump());
3804 
3805  } else if ((isRunOfOnes((unsigned)(FinalMask.getZExtValue()), NewMB, NewME) &&
3806  NewMB <= NewME) ||
3807  SrcMaskFull) {
3808  // Here we only handle MBMI <= MEMI case, so NewMB must be no bigger
3809  // than NewME. Otherwise we get a 64 bit value after folding, but MI
3810  // return a 32 bit value.
3811  Simplified = true;
3812  LLVM_DEBUG(dbgs() << "Converting Instr: ");
3813  LLVM_DEBUG(MI.dump());
3814 
3815  uint16_t NewSH = (SHSrc + SHMI) % 32;
3816  MI.getOperand(2).setImm(NewSH);
3817  // If SrcMI mask is full, no need to update MBMI and MEMI.
3818  if (!SrcMaskFull) {
3819  MI.getOperand(3).setImm(NewMB);
3820  MI.getOperand(4).setImm(NewME);
3821  }
3822  MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
3823  if (SrcMI->getOperand(1).isKill()) {
3824  MI.getOperand(1).setIsKill(true);
3825  SrcMI->getOperand(1).setIsKill(false);
3826  } else
3827  // About to replace MI.getOperand(1), clear its kill flag.
3828  MI.getOperand(1).setIsKill(false);
3829 
3830  LLVM_DEBUG(dbgs() << "To: ");
3831  LLVM_DEBUG(MI.dump());
3832  }
3833  if (Simplified & MRI->use_nodbg_empty(FoldingReg) &&
3834  !SrcMI->hasImplicitDef()) {
3835  // If FoldingReg has no non-debug use and it has no implicit def (it
3836  // is not RLWINMO or RLWINM8o), it's safe to delete its def SrcMI.
3837  // Otherwise keep it.
3838  *ToErase = SrcMI;
3839  LLVM_DEBUG(dbgs() << "Delete dead instruction: ");
3840  LLVM_DEBUG(SrcMI->dump());
3841  }
3842  return Simplified;
3843 }
3844 
3845 bool PPCInstrInfo::instrHasImmForm(unsigned Opc, bool IsVFReg,
3846  ImmInstrInfo &III, bool PostRA) const {
3847  // The vast majority of the instructions would need their operand 2 replaced
3848  // with an immediate when switching to the reg+imm form. A marked exception
3849  // are the update form loads/stores for which a constant operand 2 would need
3850  // to turn into a displacement and move operand 1 to the operand 2 position.
3851  III.ImmOpNo = 2;
3852  III.OpNoForForwarding = 2;
3853  III.ImmWidth = 16;
3854  III.ImmMustBeMultipleOf = 1;
3855  III.TruncateImmTo = 0;
3856  III.IsSummingOperands = false;
3857  switch (Opc) {
3858  default: return false;
3859  case PPC::ADD4:
3860  case PPC::ADD8:
3861  III.SignedImm = true;
3862  III.ZeroIsSpecialOrig = 0;
3863  III.ZeroIsSpecialNew = 1;
3864  III.IsCommutative = true;
3865  III.IsSummingOperands = true;
3866  III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
3867  break;
3868  case PPC::ADDC:
3869  case PPC::ADDC8:
3870  III.SignedImm = true;
3871  III.ZeroIsSpecialOrig = 0;
3872  III.ZeroIsSpecialNew = 0;
3873  III.IsCommutative = true;
3874  III.IsSummingOperands = true;
3875  III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
3876  break;
3877  case PPC::ADDC_rec:
3878  III.SignedImm = true;
3879  III.ZeroIsSpecialOrig = 0;
3880  III.ZeroIsSpecialNew = 0;
3881  III.IsCommutative = true;
3882  III.IsSummingOperands = true;
3883  III.ImmOpcode = PPC::ADDIC_rec;
3884  break;
3885  case PPC::SUBFC:
3886  case PPC::SUBFC8:
3887  III.SignedImm = true;
3888  III.ZeroIsSpecialOrig = 0;
3889  III.ZeroIsSpecialNew = 0;
3890  III.IsCommutative = false;
3891  III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
3892  break;
3893  case PPC::CMPW:
3894  case PPC::CMPD:
3895  III.SignedImm = true;
3896  III.ZeroIsSpecialOrig = 0;
3897  III.ZeroIsSpecialNew = 0;
3898  III.IsCommutative = false;
3899  III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
3900  break;
3901  case PPC::CMPLW:
3902  case PPC::CMPLD:
3903  III.SignedImm = false;
3904  III.ZeroIsSpecialOrig = 0;
3905  III.ZeroIsSpecialNew = 0;
3906  III.IsCommutative = false;
3907  III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
3908  break;
3909  case PPC::AND_rec:
3910  case PPC::AND8_rec:
3911  case PPC::OR:
3912  case PPC::OR8:
3913  case PPC::XOR:
3914  case PPC::XOR8:
3915  III.SignedImm = false;
3916  III.ZeroIsSpecialOrig = 0;
3917  III.ZeroIsSpecialNew = 0;
3918  III.IsCommutative = true;
3919  switch(Opc) {
3920  default: llvm_unreachable("Unknown opcode");
3921  case PPC::AND_rec:
3922  III.ImmOpcode = PPC::ANDI_rec;
3923  break;
3924  case PPC::AND8_rec:
3925  III.ImmOpcode = PPC::ANDI8_rec;
3926  break;
3927  case PPC::OR: III.ImmOpcode = PPC::ORI; break;
3928  case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
3929  case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
3930  case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
3931  }
3932  break;
3933  case PPC::RLWNM:
3934  case PPC::RLWNM8:
3935  case PPC::RLWNM_rec:
3936  case PPC::RLWNM8_rec:
3937  case PPC::SLW:
3938  case PPC::SLW8:
3939  case PPC::SLW_rec:
3940  case PPC::SLW8_rec:
3941  case PPC::SRW:
3942  case PPC::SRW8:
3943  case PPC::SRW_rec:
3944  case PPC::SRW8_rec:
3945  case PPC::SRAW:
3946  case PPC::SRAW_rec:
3947  III.SignedImm = false;
3948  III.ZeroIsSpecialOrig = 0;
3949  III.ZeroIsSpecialNew = 0;
3950  III.IsCommutative = false;
3951  // This isn't actually true, but the instructions ignore any of the
3952  // upper bits, so any immediate loaded with an LI is acceptable.
3953  // This does not apply to shift right algebraic because a value
3954  // out of range will produce a -1/0.
3955  III.ImmWidth = 16;
3956  if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 || Opc == PPC::RLWNM_rec ||
3957  Opc == PPC::RLWNM8_rec)
3958  III.TruncateImmTo = 5;
3959  else
3960  III.TruncateImmTo = 6;
3961  switch(Opc) {
3962  default: llvm_unreachable("Unknown opcode");
3963  case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
3964  case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
3965  case PPC::RLWNM_rec:
3966  III.ImmOpcode = PPC::RLWINM_rec;
3967  break;
3968  case PPC::RLWNM8_rec:
3969  III.ImmOpcode = PPC::RLWINM8_rec;
3970  break;
3971  case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
3972  case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
3973  case PPC::SLW_rec:
3974  III.ImmOpcode = PPC::RLWINM_rec;
3975  break;
3976  case PPC::SLW8_rec:
3977  III.ImmOpcode = PPC::RLWINM8_rec;
3978  break;
3979  case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
3980  case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
3981  case PPC::SRW_rec:
3982  III.ImmOpcode = PPC::RLWINM_rec;
3983  break;
3984  case PPC::SRW8_rec:
3985  III.ImmOpcode = PPC::RLWINM8_rec;
3986  break;
3987  case PPC::SRAW:
3988  III.ImmWidth = 5;
3989  III.TruncateImmTo = 0;
3990  III.ImmOpcode = PPC::SRAWI;
3991  break;
3992  case PPC::SRAW_rec:
3993  III.ImmWidth = 5;
3994  III.TruncateImmTo = 0;
3995  III.ImmOpcode = PPC::SRAWI_rec;
3996  break;
3997  }
3998  break;
3999  case PPC::RLDCL:
4000  case PPC::RLDCL_rec:
4001  case PPC::RLDCR:
4002  case PPC::RLDCR_rec:
4003  case PPC::SLD:
4004  case PPC::SLD_rec:
4005  case PPC::SRD:
4006  case PPC::SRD_rec:
4007  case PPC::SRAD:
4008  case PPC::SRAD_rec:
4009  III.SignedImm = false;
4010  III.ZeroIsSpecialOrig = 0;
4011  III.ZeroIsSpecialNew = 0;
4012  III.IsCommutative = false;
4013  // This isn't actually true, but the instructions ignore any of the
4014  // upper bits, so any immediate loaded with an LI is acceptable.
4015  // This does not apply to shift right algebraic because a value
4016  // out of range will produce a -1/0.
4017  III.ImmWidth = 16;
4018  if (Opc == PPC::RLDCL || Opc == PPC::RLDCL_rec || Opc == PPC::RLDCR ||
4019  Opc == PPC::RLDCR_rec)
4020  III.TruncateImmTo = 6;
4021  else
4022  III.TruncateImmTo = 7;
4023  switch(Opc) {
4024  default: llvm_unreachable("Unknown opcode");
4025  case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
4026  case PPC::RLDCL_rec:
4027  III.ImmOpcode = PPC::RLDICL_rec;
4028  break;
4029  case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
4030  case PPC::RLDCR_rec:
4031  III.ImmOpcode = PPC::RLDICR_rec;
4032  break;
4033  case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
4034  case PPC::SLD_rec:
4035  III.ImmOpcode = PPC::RLDICR_rec;
4036  break;
4037  case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
4038  case PPC::SRD_rec:
4039  III.ImmOpcode = PPC::RLDICL_rec;
4040  break;
4041  case PPC::SRAD:
4042  III.ImmWidth = 6;
4043  III.TruncateImmTo = 0;
4044  III.ImmOpcode = PPC::SRADI;
4045  break;
4046  case PPC::SRAD_rec:
4047  III.ImmWidth = 6;
4048  III.TruncateImmTo = 0;
4049  III.ImmOpcode = PPC::SRADI_rec;
4050  break;
4051  }
4052  break;
4053  // Loads and stores:
4054  case PPC::LBZX:
4055  case PPC::LBZX8:
4056  case PPC::LHZX:
4057  case PPC::LHZX8:
4058  case PPC::LHAX:
4059  case PPC::LHAX8:
4060  case PPC::LWZX:
4061  case PPC::LWZX8:
4062  case PPC::LWAX:
4063  case PPC::LDX:
4064  case PPC::LFSX:
4065  case PPC::LFDX:
4066  case PPC::STBX:
4067  case PPC::STBX8:
4068  case PPC::STHX:
4069  case PPC::STHX8:
4070  case PPC::STWX:
4071  case PPC::STWX8:
4072  case PPC::STDX:
4073  case PPC::STFSX:
4074  case PPC::STFDX:
4075  III.SignedImm = true;
4076  III.ZeroIsSpecialOrig = 1;
4077  III.ZeroIsSpecialNew = 2;
4078  III.IsCommutative = true;
4079  III.IsSummingOperands = true;
4080  III.ImmOpNo = 1;
4081  III.OpNoForForwarding = 2;
4082  switch(Opc) {
4083  default: llvm_unreachable("Unknown opcode");
4084  case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break;
4085  case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break;
4086  case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break;
4087  case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break;
4088  case PPC::LHAX: III.ImmOpcode = PPC::LHA; break;
4089  case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break;
4090  case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break;
4091  case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break;
4092  case PPC::LWAX:
4093  III.ImmOpcode = PPC::LWA;
4094  III.ImmMustBeMultipleOf = 4;
4095  break;
4096  case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break;
4097  case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
4098  case PPC::LFDX: III.ImmOpcode = PPC::LFD; break;
4099  case PPC::STBX: III.ImmOpcode = PPC::STB; break;
4100  case PPC::STBX8: III.ImmOpcode = PPC::STB8; break;
4101  case PPC::STHX: III.ImmOpcode = PPC::STH; break;
4102  case PPC::STHX8: III.ImmOpcode = PPC::STH8; break;
4103  case PPC::STWX: III.ImmOpcode = PPC::STW; break;
4104  case PPC::STWX8: III.ImmOpcode = PPC::STW8; break;
4105  case PPC::STDX:
4106  III.ImmOpcode = PPC::STD;
4107  III.ImmMustBeMultipleOf = 4;
4108  break;
4109  case PPC::STFSX: III.ImmOpcode = PPC::STFS; break;
4110  case PPC::STFDX: III.ImmOpcode = PPC::STFD; break;
4111  }
4112  break;
4113  case PPC::LBZUX:
4114  case PPC::LBZUX8:
4115  case PPC::LHZUX:
4116  case PPC::LHZUX8:
4117  case PPC::LHAUX:
4118  case PPC::LHAUX8:
4119  case PPC::LWZUX:
4120  case PPC::LWZUX8:
4121  case PPC::LDUX:
4122  case PPC::LFSUX:
4123  case PPC::LFDUX:
4124  case PPC::STBUX:
4125  case PPC::STBUX8:
4126  case PPC::STHUX:
4127  case PPC::STHUX8:
4128  case PPC::STWUX:
4129  case PPC::STWUX8:
4130  case PPC::STDUX:
4131  case PPC::STFSUX:
4132  case PPC::STFDUX:
4133  III.SignedImm = true;
4134  III.ZeroIsSpecialOrig = 2;
4135  III.ZeroIsSpecialNew = 3;
4136  III.IsCommutative = false;
4137  III.IsSummingOperands = true;
4138  III.ImmOpNo = 2;
4139  III.OpNoForForwarding = 3;
4140  switch(Opc) {
4141  default: llvm_unreachable("Unknown opcode");
4142  case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break;
4143  case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break;
4144  case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break;
4145  case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break;
4146  case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break;
4147  case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break;
4148  case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break;
4149  case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break;
4150  case PPC::LDUX:
4151  III.ImmOpcode = PPC::LDU;
4152  III.ImmMustBeMultipleOf = 4;
4153  break;
4154  case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break;
4155  case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break;
4156  case PPC::STBUX: III.ImmOpcode = PPC::STBU; break;
4157  case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break;
4158  case PPC::STHUX: III.ImmOpcode = PPC::STHU; break;
4159  case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break;
4160  case PPC::STWUX: III.ImmOpcode = PPC::STWU; break;
4161  case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break;
4162  case PPC::STDUX:
4163  III.ImmOpcode = PPC::STDU;
4164  III.ImmMustBeMultipleOf = 4;
4165  break;
4166  case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break;
4167  case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break;
4168  }
4169  break;
4170  // Power9 and up only. For some of these, the X-Form version has access to all
4171  // 64 VSR's whereas the D-Form only has access to the VR's. We replace those
4172  // with pseudo-ops pre-ra and for post-ra, we check that the register loaded
4173  // into or stored from is one of the VR registers.
4174  case PPC::LXVX:
4175  case PPC::LXSSPX:
4176  case PPC::LXSDX:
4177  case PPC::STXVX:
4178  case PPC::STXSSPX:
4179  case PPC::STXSDX:
4180  case PPC::XFLOADf32:
4181  case PPC::XFLOADf64:
4182  case PPC::XFSTOREf32:
4183  case PPC::XFSTOREf64:
4184  if (!Subtarget.hasP9Vector())
4185  return false;
4186  III.SignedImm = true;
4187  III.ZeroIsSpecialOrig = 1;
4188  III.ZeroIsSpecialNew = 2;
4189  III.IsCommutative = true;
4190  III.IsSummingOperands = true;
4191  III.ImmOpNo = 1;
4192  III.OpNoForForwarding = 2;
4193  III.ImmMustBeMultipleOf = 4;
4194  switch(Opc) {
4195  default: llvm_unreachable("Unknown opcode");
4196  case PPC::LXVX:
4197  III.ImmOpcode = PPC::LXV;
4198  III.ImmMustBeMultipleOf = 16;
4199  break;
4200  case PPC::LXSSPX:
4201  if (PostRA) {
4202  if (IsVFReg)
4203  III.ImmOpcode = PPC::LXSSP;
4204  else {
4205  III.ImmOpcode = PPC::LFS;
4206  III.ImmMustBeMultipleOf = 1;
4207  }
4208  break;
4209  }
4211  case PPC::XFLOADf32:
4212  III.ImmOpcode = PPC::DFLOADf32;
4213  break;
4214  case PPC::LXSDX:
4215  if (PostRA) {
4216  if (IsVFReg)
4217  III.ImmOpcode = PPC::LXSD;
4218  else {
4219  III.ImmOpcode = PPC::LFD;
4220  III.ImmMustBeMultipleOf = 1;
4221  }
4222  break;
4223  }
4225  case PPC::XFLOADf64:
4226  III.ImmOpcode = PPC::DFLOADf64;
4227  break;
4228  case PPC::STXVX:
4229  III.ImmOpcode = PPC::STXV;
4230  III.ImmMustBeMultipleOf = 16;
4231  break;
4232  case PPC::STXSSPX:
4233  if (PostRA) {
4234  if (IsVFReg)
4235  III.ImmOpcode = PPC::STXSSP;
4236  else {
4237  III.ImmOpcode = PPC::STFS;
4238  III.ImmMustBeMultipleOf = 1;
4239  }
4240  break;
4241  }
4243  case PPC::XFSTOREf32:
4244  III.ImmOpcode = PPC::DFSTOREf32;
4245  break;
4246  case PPC::STXSDX:
4247  if (PostRA) {
4248  if (IsVFReg)
4249  III.ImmOpcode = PPC::STXSD;
4250  else {
4251  III.ImmOpcode = PPC::STFD;
4252  III.ImmMustBeMultipleOf = 1;
4253  }
4254  break;
4255  }
4257  case PPC::XFSTOREf64:
4258  III.ImmOpcode = PPC::DFSTOREf64;
4259  break;
4260  }
4261  break;
4262  }
4263  return true;
4264 }
4265 
4266 // Utility function for swaping two arbitrary operands of an instruction.
4267 static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
4268  assert(Op1 != Op2 && "Cannot swap operand with itself.");
4269 
4270  unsigned MaxOp = std::max(Op1, Op2);
4271  unsigned MinOp = std::min(Op1, Op2);
4272  MachineOperand MOp1 = MI.getOperand(MinOp);
4273  MachineOperand MOp2 = MI.getOperand(MaxOp);
4274  MI.RemoveOperand(std::max(Op1, Op2));
4275  MI.RemoveOperand(std::min(Op1, Op2));
4276 
4277  // If the operands we are swapping are the two at the end (the common case)
4278  // we can just remove both and add them in the opposite order.
4279  if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) {
4280  MI.addOperand(MOp2);
4281  MI.addOperand(MOp1);
4282  } else {
4283  // Store all operands in a temporary vector, remove them and re-add in the
4284  // right order.
4286  unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
4287  for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
4288  MOps.push_back(MI.getOperand(i));
4289  MI.RemoveOperand(i);
4290  }
4291  // MOp2 needs to be added next.
4292  MI.addOperand(MOp2);
4293  // Now add the rest.
4294  for (unsigned i = MI.getNumOperands(); i < TotalOps; i++) {
4295  if (i == MaxOp)
4296  MI.addOperand(MOp1);
4297  else {
4298  MI.addOperand(MOps.back());
4299  MOps.pop_back();
4300  }
4301  }
4302  }
4303 }
4304 
4305 // Check if the 'MI' that has the index OpNoForForwarding
4306 // meets the requirement described in the ImmInstrInfo.
4307 bool PPCInstrInfo::isUseMIElgibleForForwarding(MachineInstr &MI,
4308  const ImmInstrInfo &III,
4309  unsigned OpNoForForwarding
4310  ) const {
4311  // As the algorithm of checking for PPC::ZERO/PPC::ZERO8
4312  // would not work pre-RA, we can only do the check post RA.
4313  MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4314  if (MRI.isSSA())
4315  return false;
4316 
4317  // Cannot do the transform if MI isn't summing the operands.
4318  if (!III.IsSummingOperands)
4319  return false;
4320 
4321  // The instruction we are trying to replace must have the ZeroIsSpecialOrig set.
4322  if (!III.ZeroIsSpecialOrig)
4323  return false;
4324 
4325  // We cannot do the transform if the operand we are trying to replace
4326  // isn't the same as the operand the instruction allows.
4327  if (OpNoForForwarding != III.OpNoForForwarding)
4328  return false;
4329 
4330  // Check if the instruction we are trying to transform really has
4331  // the special zero register as its operand.
4332  if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO &&
4333  MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8)
4334  return false;
4335 
4336  // This machine instruction is convertible if it is,
4337  // 1. summing the operands.
4338  // 2. one of the operands is special zero register.
4339  // 3. the operand we are trying to replace is allowed by the MI.
4340  return true;
4341 }
4342 
4343 // Check if the DefMI is the add inst and set the ImmMO and RegMO
4344 // accordingly.
4345 bool PPCInstrInfo::isDefMIElgibleForForwarding(MachineInstr &DefMI,
4346  const ImmInstrInfo &III,
4347  MachineOperand *&ImmMO,
4348  MachineOperand *&RegMO) const {
4349  unsigned Opc = DefMI.getOpcode();
4350  if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8)
4351  return false;
4352 
4353  assert(DefMI.getNumOperands() >= 3 &&
4354  "Add inst must have at least three operands");
4355  RegMO = &DefMI.getOperand(1);
4356  ImmMO = &DefMI.getOperand(2);
4357 
4358  // Before RA, ADDI first operand could be a frame index.
4359  if (!RegMO->isReg())
4360  return false;
4361 
4362  // This DefMI is elgible for forwarding if it is:
4363  // 1. add inst
4364  // 2. one of the operands is Imm/CPI/Global.
4365  return isAnImmediateOperand(*ImmMO);
4366 }
4367 
4368 bool PPCInstrInfo::isRegElgibleForForwarding(
4369  const MachineOperand &RegMO, const MachineInstr &DefMI,
4370  const MachineInstr &MI, bool KillDefMI,
4371  bool &IsFwdFeederRegKilled) const {
4372  // x = addi y, imm
4373  // ...
4374  // z = lfdx 0, x -> z = lfd imm(y)
4375  // The Reg "y" can be forwarded to the MI(z) only when there is no DEF
4376  // of "y" between the DEF of "x" and "z".
4377  // The query is only valid post RA.
4378  const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4379  if (MRI.isSSA())
4380  return false;
4381 
4382  Register Reg = RegMO.getReg();
4383 
4384  // Walking the inst in reverse(MI-->DefMI) to get the last DEF of the Reg.
4386  MachineBasicBlock::const_reverse_iterator E = MI.getParent()->rend();
4387  It++;
4388  for (; It != E; ++It) {
4389  if (It->modifiesRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
4390  return false;
4391  else if (It->killsRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
4392  IsFwdFeederRegKilled = true;
4393  // Made it to DefMI without encountering a clobber.
4394  if ((&*It) == &DefMI)
4395  break;
4396  }
4397  assert((&*It) == &DefMI && "DefMI is missing");
4398 
4399  // If DefMI also defines the register to be forwarded, we can only forward it
4400  // if DefMI is being erased.
4401  if (DefMI.modifiesRegister(Reg, &getRegisterInfo()))
4402  return KillDefMI;
4403 
4404  return true;
4405 }
4406 
4407 bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
4408  const MachineInstr &DefMI,
4409  const ImmInstrInfo &III,
4410  int64_t &Imm,
4411  int64_t BaseImm) const {
4412  assert(isAnImmediateOperand(ImmMO) && "ImmMO is NOT an immediate");
4413  if (DefMI.getOpcode() == PPC::ADDItocL) {
4414  // The operand for ADDItocL is CPI, which isn't imm at compiling time,
4415  // However, we know that, it is 16-bit width, and has the alignment of 4.
4416  // Check if the instruction met the requirement.
4417  if (III.ImmMustBeMultipleOf > 4 ||
4418  III.TruncateImmTo || III.ImmWidth != 16)
4419  return false;
4420 
4421  // Going from XForm to DForm loads means that the displacement needs to be
4422  // not just an immediate but also a multiple of 4, or 16 depending on the
4423  // load. A DForm load cannot be represented if it is a multiple of say 2.
4424  // XForm loads do not have this restriction.
4425  if (ImmMO.isGlobal()) {
4426  const DataLayout &DL = ImmMO.getGlobal()->getParent()->getDataLayout();
4428  return false;
4429  }
4430 
4431  return true;
4432  }
4433 
4434  if (ImmMO.isImm()) {
4435  // It is Imm, we need to check if the Imm fit the range.
4436  // Sign-extend to 64-bits.
4437  // DefMI may be folded with another imm form instruction, the result Imm is
4438  // the sum of Imm of DefMI and BaseImm which is from imm form instruction.
4439  APInt ActualValue(64, ImmMO.getImm() + BaseImm, true);
4440  if (III.SignedImm && !ActualValue.isSignedIntN(III.ImmWidth))
4441  return false;
4442  if (!III.SignedImm && !ActualValue.isIntN(III.ImmWidth))
4443  return false;
4444  Imm = SignExtend64<16>(ImmMO.getImm() + BaseImm);
4445 
4446  if (Imm % III.ImmMustBeMultipleOf)
4447  return false;
4448  if (III.TruncateImmTo)
4449  Imm &= ((1 << III.TruncateImmTo) - 1);
4450  }
4451  else
4452  return false;
4453 
4454  // This ImmMO is forwarded if it meets the requriement describle
4455  // in ImmInstrInfo
4456  return true;
4457 }
4458 
4459 bool PPCInstrInfo::simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
4460  unsigned OpNoForForwarding,
4461  MachineInstr **KilledDef) const {
4462  if ((DefMI.getOpcode() != PPC::LI && DefMI.getOpcode() != PPC::LI8) ||
4463  !DefMI.getOperand(1).isImm())
4464  return false;
4465 
4466  MachineFunction *MF = MI.getParent()->getParent();
4468  bool PostRA = !MRI->isSSA();
4469 
4470  int64_t Immediate = DefMI.getOperand(1).getImm();
4471  // Sign-extend to 64-bits.
4472  int64_t SExtImm = SignExtend64<16>(Immediate);
4473 
4474  bool IsForwardingOperandKilled = MI.getOperand(OpNoForForwarding).isKill();
4475  Register ForwardingOperandReg = MI.getOperand(OpNoForForwarding).getReg();
4476 
4477  bool ReplaceWithLI = false;
4478  bool Is64BitLI = false;
4479  int64_t NewImm = 0;
4480  bool SetCR = false;
4481  unsigned Opc = MI.getOpcode();
4482  switch (Opc) {
4483  default:
4484  return false;
4485 
4486  // FIXME: Any branches conditional on such a comparison can be made
4487  // unconditional. At this time, this happens too infrequently to be worth
4488  // the implementation effort, but if that ever changes, we could convert
4489  // such a pattern here.
4490  case PPC::CMPWI:
4491  case PPC::CMPLWI:
4492  case PPC::CMPDI:
4493  case PPC::CMPLDI: {
4494  // Doing this post-RA would require dataflow analysis to reliably find uses
4495  // of the CR register set by the compare.
4496  // No need to fixup killed/dead flag since this transformation is only valid
4497  // before RA.
4498  if (PostRA)
4499  return false;
4500  // If a compare-immediate is fed by an immediate and is itself an input of
4501  // an ISEL (the most common case) into a COPY of the correct register.
4502  bool Changed = false;
4503  Register DefReg = MI.getOperand(0).getReg();
4504  int64_t Comparand = MI.getOperand(2).getImm();
4505  int64_t SExtComparand = ((uint64_t)Comparand & ~0x7FFFuLL) != 0
4506  ? (Comparand | 0xFFFFFFFFFFFF0000)
4507  : Comparand;
4508 
4509  for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
4510  unsigned UseOpc = CompareUseMI.getOpcode();
4511  if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
4512  continue;
4513  unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
4514  Register TrueReg = CompareUseMI.getOperand(1).getReg();
4515  Register FalseReg = CompareUseMI.getOperand(2).getReg();
4516  unsigned RegToCopy =
4517  selectReg(SExtImm, SExtComparand, Opc, TrueReg, FalseReg, CRSubReg);
4518  if (RegToCopy == PPC::NoRegister)
4519  continue;
4520  // Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0.
4521  if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
4522  CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
4523  replaceInstrOperandWithImm(CompareUseMI, 1, 0);
4524  CompareUseMI.RemoveOperand(3);
4525  CompareUseMI.RemoveOperand(2);
4526  continue;
4527  }
4528  LLVM_DEBUG(
4529  dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n");
4530  LLVM_DEBUG(DefMI.dump(); MI.dump(); CompareUseMI.dump());
4531  LLVM_DEBUG(dbgs() << "Is converted to:\n");
4532  // Convert to copy and remove unneeded operands.
4533  CompareUseMI.setDesc(get(PPC::COPY));
4534  CompareUseMI.RemoveOperand(3);
4535  CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
4536  CmpIselsConverted++;
4537  Changed = true;
4538  LLVM_DEBUG(CompareUseMI.dump());
4539  }
4540  if (Changed)
4541  return true;
4542  // This may end up incremented multiple times since this function is called
4543  // during a fixed-point transformation, but it is only meant to indicate the
4544  // presence of this opportunity.
4545  MissedConvertibleImmediateInstrs++;
4546  return false;
4547  }
4548 
4549  // Immediate forms - may simply be convertable to an LI.
4550  case PPC::ADDI:
4551  case PPC::ADDI8: {
4552  // Does the sum fit in a 16-bit signed field?
4553  int64_t Addend = MI.getOperand(2).getImm();
4554  if (isInt<16>(Addend + SExtImm)) {
4555  ReplaceWithLI = true;
4556  Is64BitLI = Opc == PPC::ADDI8;
4557  NewImm = Addend + SExtImm;
4558  break;
4559  }
4560  return false;
4561  }
4562  case PPC::SUBFIC:
4563  case PPC::SUBFIC8: {
4564  // Only transform this if the CARRY implicit operand is dead.
4565  if (MI.getNumOperands() > 3 && !MI.getOperand(3).isDead())
4566  return false;
4567  int64_t Minuend = MI.getOperand(2).getImm();
4568  if (isInt<16>(Minuend - SExtImm)) {
4569  ReplaceWithLI = true;
4570  Is64BitLI = Opc == PPC::SUBFIC8;
4571  NewImm = Minuend - SExtImm;
4572  break;
4573  }
4574  return false;
4575  }
4576  case PPC::RLDICL:
4577  case PPC::RLDICL_rec:
4578  case PPC::RLDICL_32:
4579  case PPC::RLDICL_32_64: {
4580  // Use APInt's rotate function.
4581  int64_t SH = MI.getOperand(2).getImm();
4582  int64_t MB = MI.getOperand(3).getImm();
4583  APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec) ? 64 : 32,
4584  SExtImm, true);
4585  InVal = InVal.rotl(SH);
4586  uint64_t Mask = MB == 0 ? -1LLU : (1LLU << (63 - MB + 1)) - 1;
4587  InVal &= Mask;
4588  // Can't replace negative values with an LI as that will sign-extend
4589  // and not clear the left bits. If we're setting the CR bit, we will use
4590  // ANDI_rec which won't sign extend, so that's safe.
4591  if (isUInt<15>(InVal.getSExtValue()) ||
4592  (Opc == PPC::RLDICL_rec && isUInt<16>(InVal.getSExtValue()))) {
4593  ReplaceWithLI = true;
4594  Is64BitLI = Opc != PPC::RLDICL_32;
4595  NewImm = InVal.getSExtValue();
4596  SetCR = Opc == PPC::RLDICL_rec;
4597  break;
4598  }
4599  return false;
4600  }
4601  case PPC::RLWINM:
4602  case PPC::RLWINM8:
4603  case PPC::RLWINM_rec:
4604  case PPC::RLWINM8_rec: {
4605  int64_t SH = MI.getOperand(2).getImm();
4606  int64_t MB = MI.getOperand(3).getImm();
4607  int64_t ME = MI.getOperand(4).getImm();
4608  APInt InVal(32, SExtImm, true);
4609  InVal = InVal.rotl(SH);
4610  APInt Mask = APInt::getBitsSetWithWrap(32, 32 - ME - 1, 32 - MB);
4611  InVal &= Mask;
4612  // Can't replace negative values with an LI as that will sign-extend
4613  // and not clear the left bits. If we're setting the CR bit, we will use
4614  // ANDI_rec which won't sign extend, so that's safe.
4615  bool ValueFits = isUInt<15>(InVal.getSExtValue());
4616  ValueFits |= ((Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec) &&
4617  isUInt<16>(InVal.getSExtValue()));
4618  if (ValueFits) {
4619  ReplaceWithLI = true;
4620  Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8_rec;
4621  NewImm = InVal.getSExtValue();
4622  SetCR = Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec;
4623  break;
4624  }
4625  return false;
4626  }
4627  case PPC::ORI:
4628  case PPC::ORI8:
4629  case PPC::XORI:
4630  case PPC::XORI8: {
4631  int64_t LogicalImm = MI.getOperand(2).getImm();
4632  int64_t Result = 0;
4633  if (Opc == PPC::ORI || Opc == PPC::ORI8)
4634  Result = LogicalImm | SExtImm;
4635  else
4636  Result = LogicalImm ^ SExtImm;
4637  if (isInt<16>(Result)) {
4638  ReplaceWithLI = true;
4639  Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
4640  NewImm = Result;
4641  break;
4642  }
4643  return false;
4644  }
4645  }
4646 
4647  if (ReplaceWithLI) {
4648  // We need to be careful with CR-setting instructions we're replacing.
4649  if (SetCR) {
4650  // We don't know anything about uses when we're out of SSA, so only
4651  // replace if the new immediate will be reproduced.
4652  bool ImmChanged = (SExtImm & NewImm) != NewImm;
4653  if (PostRA && ImmChanged)
4654  return false;
4655 
4656  if (!PostRA) {
4657  // If the defining load-immediate has no other uses, we can just replace
4658  // the immediate with the new immediate.
4659  if (MRI->hasOneUse(DefMI.getOperand(0).getReg()))
4660  DefMI.getOperand(1).setImm(NewImm);
4661 
4662  // If we're not using the GPR result of the CR-setting instruction, we
4663  // just need to and with zero/non-zero depending on the new immediate.
4664  else if (MRI->use_empty(MI.getOperand(0).getReg())) {
4665  if (NewImm) {
4666  assert(Immediate && "Transformation converted zero to non-zero?");
4667  NewImm = Immediate;
4668  }
4669  } else if (ImmChanged)
4670  return false;
4671  }
4672  }
4673 
4674  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
4675  LLVM_DEBUG(MI.dump());
4676  LLVM_DEBUG(dbgs() << "Fed by:\n");
4677  LLVM_DEBUG(DefMI.dump());
4678  LoadImmediateInfo LII;
4679  LII.Imm = NewImm;
4680  LII.Is64Bit = Is64BitLI;
4681  LII.SetCR = SetCR;
4682  // If we're setting the CR, the original load-immediate must be kept (as an
4683  // operand to ANDI_rec/ANDI8_rec).
4684  if (KilledDef && SetCR)
4685  *KilledDef = nullptr;
4686  replaceInstrWithLI(MI, LII);
4687 
4688  // Fixup killed/dead flag after transformation.
4689  // Pattern:
4690  // ForwardingOperandReg = LI imm1
4691  // y = op2 imm2, ForwardingOperandReg(killed)
4692  if (IsForwardingOperandKilled)
4693  fixupIsDeadOrKill(&DefMI, &MI, ForwardingOperandReg);
4694 
4695  LLVM_DEBUG(dbgs() << "With:\n");
4696  LLVM_DEBUG(MI.dump());
4697  return true;
4698  }
4699  return false;
4700 }
4701 
4702 bool PPCInstrInfo::transformToNewImmFormFedByAdd(
4703  MachineInstr &MI, MachineInstr &DefMI, unsigned OpNoForForwarding) const {
4704  MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
4705  bool PostRA = !MRI->isSSA();
4706  // FIXME: extend this to post-ra. Need to do some change in getForwardingDefMI
4707  // for post-ra.
4708  if (PostRA)
4709  return false;
4710 
4711  // Only handle load/store.
4712  if (!MI.mayLoadOrStore())
4713  return false;
4714 
4715  unsigned XFormOpcode = RI.getMappedIdxOpcForImmOpc(MI.getOpcode());
4716 
4717  assert((XFormOpcode != PPC::INSTRUCTION_LIST_END) &&
4718  "MI must have x-form opcode");
4719 
4720  // get Imm Form info.
4721  ImmInstrInfo III;
4722  bool IsVFReg = MI.getOperand(0).isReg()
4723  ? isVFRegister(MI.getOperand(0).getReg())
4724  : false;
4725 
4726  if (!instrHasImmForm(XFormOpcode, IsVFReg, III, PostRA))
4727  return false;
4728 
4729  if (!III.IsSummingOperands)
4730  return false;
4731 
4732  if (OpNoForForwarding != III.OpNoForForwarding)
4733  return false;
4734 
4735  MachineOperand ImmOperandMI = MI.getOperand(III.ImmOpNo);
4736  if (!ImmOperandMI.isImm())
4737  return false;
4738 
4739  // Check DefMI.
4740  MachineOperand *ImmMO = nullptr;
4741  MachineOperand *RegMO = nullptr;
4742  if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
4743  return false;
4744  assert(ImmMO && RegMO && "Imm and Reg operand must have been set");
4745 
4746  // Check Imm.
4747  // Set ImmBase from imm instruction as base and get new Imm inside
4748  // isImmElgibleForForwarding.
4749  int64_t ImmBase = ImmOperandMI.getImm();
4750  int64_t Imm = 0;
4751  if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm, ImmBase))
4752  return false;
4753 
4754  // Get killed info in case fixup needed after transformation.
4755  unsigned ForwardKilledOperandReg = ~0U;
4756  if (MI.getOperand(III.OpNoForForwarding).isKill())
4757  ForwardKilledOperandReg = MI.getOperand(III.OpNoForForwarding).getReg();
4758 
4759  // Do the transform
4760  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
4761  LLVM_DEBUG(MI.dump());
4762  LLVM_DEBUG(dbgs() << "Fed by:\n");
4763  LLVM_DEBUG(DefMI.dump());
4764 
4765  MI.getOperand(III.OpNoForForwarding).setReg(RegMO->getReg());
4766  if (RegMO->isKill()) {
4767  MI.getOperand(III.OpNoForForwarding).setIsKill(true);
4768  // Clear the killed flag in RegMO. Doing this here can handle some cases
4769  // that DefMI and MI are not in same basic block.
4770  RegMO->setIsKill(false);
4771  }
4772  MI.getOperand(III.ImmOpNo).setImm(Imm);
4773 
4774  // FIXME: fix kill/dead flag if MI and DefMI are not in same basic block.
4775  if (DefMI.getParent() == MI.getParent()) {
4776  // Check if reg is killed between MI and DefMI.
4777  auto IsKilledFor = [&](unsigned Reg) {
4780  It++;
4781  for (; It != E; ++It) {
4782  if (It->killsRegister(Reg))
4783  return true;
4784  }
4785  return false;
4786  };
4787 
4788  // Update kill flag
4789  if (RegMO->isKill() || IsKilledFor(RegMO->getReg()))
4790  fixupIsDeadOrKill(&DefMI, &MI, RegMO->getReg());
4791  if (ForwardKilledOperandReg != ~0U)
4792  fixupIsDeadOrKill(&DefMI, &MI, ForwardKilledOperandReg);
4793  }
4794 
4795  LLVM_DEBUG(dbgs() << "With:\n");
4796  LLVM_DEBUG(MI.dump());
4797  return true;
4798 }
4799 
4800 // If an X-Form instruction is fed by an add-immediate and one of its operands
4801 // is the literal zero, attempt to forward the source of the add-immediate to
4802 // the corresponding D-Form instruction with the displacement coming from
4803 // the immediate being added.
4804 bool PPCInstrInfo::transformToImmFormFedByAdd(
4805  MachineInstr &MI, const ImmInstrInfo &III, unsigned OpNoForForwarding,
4806  MachineInstr &DefMI, bool KillDefMI) const {
4807  // RegMO ImmMO
4808  // | |
4809  // x = addi reg, imm <----- DefMI
4810  // y = op 0 , x <----- MI
4811  // |
4812  // OpNoForForwarding
4813  // Check if the MI meet the requirement described in the III.
4814  if (!isUseMIElgibleForForwarding(MI, III, OpNoForForwarding))
4815  return false;
4816 
4817  // Check if the DefMI meet the requirement
4818  // described in the III. If yes, set the ImmMO and RegMO accordingly.
4819  MachineOperand *ImmMO = nullptr;
4820  MachineOperand *RegMO = nullptr;
4821  if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
4822  return false;
4823  assert(ImmMO && RegMO && "Imm and Reg operand must have been set");
4824 
4825  // As we get the Imm operand now, we need to check if the ImmMO meet
4826  // the requirement described in the III. If yes set the Imm.
4827  int64_t Imm = 0;
4828  if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm))
4829  return false;
4830 
4831  bool IsFwdFeederRegKilled = false;
4832  // Check if the RegMO can be forwarded to MI.
4833  if (!isRegElgibleForForwarding(*RegMO, DefMI, MI, KillDefMI,
4834  IsFwdFeederRegKilled))
4835  return false;
4836 
4837  // Get killed info in case fixup needed after transformation.
4838  unsigned ForwardKilledOperandReg = ~0U;
4839  MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4840  bool PostRA = !MRI.isSSA();
4841  if (PostRA && MI.getOperand(OpNoForForwarding).isKill())
4842  ForwardKilledOperandReg = MI.getOperand(OpNoForForwarding).getReg();
4843 
4844  // We know that, the MI and DefMI both meet the pattern, and
4845  // the Imm also meet the requirement with the new Imm-form.
4846  // It is safe to do the transformation now.
4847  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
4848  LLVM_DEBUG(MI.dump());
4849  LLVM_DEBUG(dbgs() << "Fed by:\n");
4850  LLVM_DEBUG(DefMI.dump());
4851 
4852  // Update the base reg first.
4853  MI.getOperand(III.OpNoForForwarding).ChangeToRegister(RegMO->getReg(),
4854  false, false,
4855  RegMO->isKill());
4856 
4857  // Then, update the imm.
4858  if (ImmMO->isImm()) {
4859  // If the ImmMO is Imm, change the operand that has ZERO to that Imm
4860  // directly.
4862  }
4863  else {
4864  // Otherwise, it is Constant Pool Index(CPI) or Global,
4865  // which is relocation in fact. We need to replace the special zero
4866  // register with ImmMO.
4867  // Before that, we need to fixup the target flags for imm.
4868  // For some reason, we miss to set the flag for the ImmMO if it is CPI.
4869  if (DefMI.getOpcode() == PPC::ADDItocL)
4871 
4872  // MI didn't have the interface such as MI.setOperand(i) though
4873  // it has MI.getOperand(i). To repalce the ZERO MachineOperand with
4874  // ImmMO, we need to remove ZERO operand and all the operands behind it,
4875  // and, add the ImmMO, then, move back all the operands behind ZERO.
4877  for (unsigned i = MI.getNumOperands() - 1; i >= III.ZeroIsSpecialOrig; i--) {
4878  MOps.push_back(MI.getOperand(i));
4879  MI.RemoveOperand(i);
4880  }
4881 
4882  // Remove the last MO in the list, which is ZERO operand in fact.
4883  MOps.pop_back();
4884  // Add the imm operand.
4885  MI.addOperand(*ImmMO);
4886  // Now add the rest back.
4887  for (auto &MO : MOps)
4888  MI.addOperand(MO);
4889  }
4890 
4891  // Update the opcode.
4892  MI.setDesc(get(III.ImmOpcode));
4893 
4894  // Fix up killed/dead flag after transformation.
4895  // Pattern 1:
4896  // x = ADD KilledFwdFeederReg, imm
4897  // n = opn KilledFwdFeederReg(killed), regn
4898  // y = XOP 0, x
4899  // Pattern 2:
4900  // x = ADD reg(killed), imm
4901  // y = XOP 0, x
4902  if (IsFwdFeederRegKilled || RegMO->isKill())
4903  fixupIsDeadOrKill(&DefMI, &MI, RegMO->getReg());
4904  // Pattern 3:
4905  // ForwardKilledOperandReg = ADD reg, imm
4906  // y = XOP 0, ForwardKilledOperandReg(killed)
4907  if (ForwardKilledOperandReg != ~0U)
4908  fixupIsDeadOrKill(&DefMI, &MI, ForwardKilledOperandReg);
4909 
4910  LLVM_DEBUG(dbgs() << "With:\n");
4911  LLVM_DEBUG(MI.dump());
4912 
4913  return true;
4914 }
4915 
4916 bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
4917  const ImmInstrInfo &III,
4918  unsigned ConstantOpNo,
4919  MachineInstr &DefMI) const {
4920  // DefMI must be LI or LI8.
4921  if ((DefMI.getOpcode() != PPC::LI && DefMI.getOpcode() != PPC::LI8) ||
4922  !DefMI.getOperand(1).isImm())
4923  return false;
4924 
4925  // Get Imm operand and Sign-extend to 64-bits.
4926  int64_t Imm = SignExtend64<16>(DefMI.getOperand(1).getImm());
4927