LLVM  13.0.0git
PPCInstrInfo.cpp
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1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCInstrInfo.h"
15 #include "PPC.h"
16 #include "PPCHazardRecognizers.h"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Statistic.h"
35 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCInst.h"
39 #include "llvm/Support/Debug.h"
43 
44 using namespace llvm;
45 
46 #define DEBUG_TYPE "ppc-instr-info"
47 
48 #define GET_INSTRMAP_INFO
49 #define GET_INSTRINFO_CTOR_DTOR
50 #include "PPCGenInstrInfo.inc"
51 
52 STATISTIC(NumStoreSPILLVSRRCAsVec,
53  "Number of spillvsrrc spilled to stack as vec");
54 STATISTIC(NumStoreSPILLVSRRCAsGpr,
55  "Number of spillvsrrc spilled to stack as gpr");
56 STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc");
57 STATISTIC(CmpIselsConverted,
58  "Number of ISELs that depend on comparison of constants converted");
59 STATISTIC(MissedConvertibleImmediateInstrs,
60  "Number of compare-immediate instructions fed by constants");
61 STATISTIC(NumRcRotatesConvertedToRcAnd,
62  "Number of record-form rotates converted to record-form andi");
63 
64 static cl::
65 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
66  cl::desc("Disable analysis for CTR loops"));
67 
68 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
69 cl::desc("Disable compare instruction optimization"), cl::Hidden);
70 
71 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
72 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
73 cl::Hidden);
74 
75 static cl::opt<bool>
76 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
77  cl::desc("Use the old (incorrect) instruction latency calculation"));
78 
79 static cl::opt<float>
80  FMARPFactor("ppc-fma-rp-factor", cl::Hidden, cl::init(1.5),
81  cl::desc("register pressure factor for the transformations."));
82 
84  "ppc-fma-rp-reduction", cl::Hidden, cl::init(true),
85  cl::desc("enable register pressure reduce in machine combiner pass."));
86 
87 // Pin the vtable to this file.
88 void PPCInstrInfo::anchor() {}
89 
91  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
92  /* CatchRetOpcode */ -1,
93  STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
94  Subtarget(STI), RI(STI.getTargetMachine()) {}
95 
96 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
97 /// this target when scheduling the DAG.
100  const ScheduleDAG *DAG) const {
101  unsigned Directive =
102  static_cast<const PPCSubtarget *>(STI)->getCPUDirective();
105  const InstrItineraryData *II =
106  static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
107  return new ScoreboardHazardRecognizer(II, DAG);
108  }
109 
111 }
112 
113 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
114 /// to use for this target when scheduling the DAG.
117  const ScheduleDAG *DAG) const {
118  unsigned Directive =
119  DAG->MF.getSubtarget<PPCSubtarget>().getCPUDirective();
120 
121  // FIXME: Leaving this as-is until we have POWER9 scheduling info
123  return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
124 
125  // Most subtargets use a PPC970 recognizer.
128  assert(DAG->TII && "No InstrInfo?");
129 
130  return new PPCHazardRecognizer970(*DAG);
131  }
132 
133  return new ScoreboardHazardRecognizer(II, DAG);
134 }
135 
137  const MachineInstr &MI,
138  unsigned *PredCost) const {
139  if (!ItinData || UseOldLatencyCalc)
140  return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
141 
142  // The default implementation of getInstrLatency calls getStageLatency, but
143  // getStageLatency does not do the right thing for us. While we have
144  // itinerary, most cores are fully pipelined, and so the itineraries only
145  // express the first part of the pipeline, not every stage. Instead, we need
146  // to use the listed output operand cycle number (using operand 0 here, which
147  // is an output).
148 
149  unsigned Latency = 1;
150  unsigned DefClass = MI.getDesc().getSchedClass();
151  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
152  const MachineOperand &MO = MI.getOperand(i);
153  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
154  continue;
155 
156  int Cycle = ItinData->getOperandCycle(DefClass, i);
157  if (Cycle < 0)
158  continue;
159 
160  Latency = std::max(Latency, (unsigned) Cycle);
161  }
162 
163  return Latency;
164 }
165 
167  const MachineInstr &DefMI, unsigned DefIdx,
168  const MachineInstr &UseMI,
169  unsigned UseIdx) const {
170  int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
171  UseMI, UseIdx);
172 
173  if (!DefMI.getParent())
174  return Latency;
175 
176  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
177  Register Reg = DefMO.getReg();
178 
179  bool IsRegCR;
181  const MachineRegisterInfo *MRI =
182  &DefMI.getParent()->getParent()->getRegInfo();
183  IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
184  MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
185  } else {
186  IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
187  PPC::CRBITRCRegClass.contains(Reg);
188  }
189 
190  if (UseMI.isBranch() && IsRegCR) {
191  if (Latency < 0)
192  Latency = getInstrLatency(ItinData, DefMI);
193 
194  // On some cores, there is an additional delay between writing to a condition
195  // register, and using it from a branch.
196  unsigned Directive = Subtarget.getCPUDirective();
197  switch (Directive) {
198  default: break;
199  case PPC::DIR_7400:
200  case PPC::DIR_750:
201  case PPC::DIR_970:
202  case PPC::DIR_E5500:
203  case PPC::DIR_PWR4:
204  case PPC::DIR_PWR5:
205  case PPC::DIR_PWR5X:
206  case PPC::DIR_PWR6:
207  case PPC::DIR_PWR6X:
208  case PPC::DIR_PWR7:
209  case PPC::DIR_PWR8:
210  // FIXME: Is this needed for POWER9?
211  Latency += 2;
212  break;
213  }
214  }
215 
216  return Latency;
217 }
218 
219 /// This is an architecture-specific helper function of reassociateOps.
220 /// Set special operand attributes for new instructions after reassociation.
222  MachineInstr &OldMI2,
223  MachineInstr &NewMI1,
224  MachineInstr &NewMI2) const {
225  // Propagate FP flags from the original instructions.
226  // But clear poison-generating flags because those may not be valid now.
227  uint16_t IntersectedFlags = OldMI1.getFlags() & OldMI2.getFlags();
228  NewMI1.setFlags(IntersectedFlags);
229  NewMI1.clearFlag(MachineInstr::MIFlag::NoSWrap);
230  NewMI1.clearFlag(MachineInstr::MIFlag::NoUWrap);
231  NewMI1.clearFlag(MachineInstr::MIFlag::IsExact);
232 
233  NewMI2.setFlags(IntersectedFlags);
234  NewMI2.clearFlag(MachineInstr::MIFlag::NoSWrap);
235  NewMI2.clearFlag(MachineInstr::MIFlag::NoUWrap);
236  NewMI2.clearFlag(MachineInstr::MIFlag::IsExact);
237 }
238 
240  uint16_t Flags) const {
241  MI.setFlags(Flags);
242  MI.clearFlag(MachineInstr::MIFlag::NoSWrap);
243  MI.clearFlag(MachineInstr::MIFlag::NoUWrap);
244  MI.clearFlag(MachineInstr::MIFlag::IsExact);
245 }
246 
247 // This function does not list all associative and commutative operations, but
248 // only those worth feeding through the machine combiner in an attempt to
249 // reduce the critical path. Mostly, this means floating-point operations,
250 // because they have high latencies(>=5) (compared to other operations, such as
251 // and/or, which are also associative and commutative, but have low latencies).
253  switch (Inst.getOpcode()) {
254  // Floating point:
255  // FP Add:
256  case PPC::FADD:
257  case PPC::FADDS:
258  // FP Multiply:
259  case PPC::FMUL:
260  case PPC::FMULS:
261  // Altivec Add:
262  case PPC::VADDFP:
263  // VSX Add:
264  case PPC::XSADDDP:
265  case PPC::XVADDDP:
266  case PPC::XVADDSP:
267  case PPC::XSADDSP:
268  // VSX Multiply:
269  case PPC::XSMULDP:
270  case PPC::XVMULDP:
271  case PPC::XVMULSP:
272  case PPC::XSMULSP:
273  return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
274  Inst.getFlag(MachineInstr::MIFlag::FmNsz);
275  // Fixed point:
276  // Multiply:
277  case PPC::MULHD:
278  case PPC::MULLD:
279  case PPC::MULHW:
280  case PPC::MULLW:
281  return true;
282  default:
283  return false;
284  }
285 }
286 
287 #define InfoArrayIdxFMAInst 0
288 #define InfoArrayIdxFAddInst 1
289 #define InfoArrayIdxFMULInst 2
290 #define InfoArrayIdxAddOpIdx 3
291 #define InfoArrayIdxMULOpIdx 4
292 #define InfoArrayIdxFSubInst 5
293 // Array keeps info for FMA instructions:
294 // Index 0(InfoArrayIdxFMAInst): FMA instruction;
295 // Index 1(InfoArrayIdxFAddInst): ADD instruction associated with FMA;
296 // Index 2(InfoArrayIdxFMULInst): MUL instruction associated with FMA;
297 // Index 3(InfoArrayIdxAddOpIdx): ADD operand index in FMA operands;
298 // Index 4(InfoArrayIdxMULOpIdx): first MUL operand index in FMA operands;
299 // second MUL operand index is plus 1;
300 // Index 5(InfoArrayIdxFSubInst): SUB instruction associated with FMA.
301 static const uint16_t FMAOpIdxInfo[][6] = {
302  // FIXME: Add more FMA instructions like XSNMADDADP and so on.
303  {PPC::XSMADDADP, PPC::XSADDDP, PPC::XSMULDP, 1, 2, PPC::XSSUBDP},
304  {PPC::XSMADDASP, PPC::XSADDSP, PPC::XSMULSP, 1, 2, PPC::XSSUBSP},
305  {PPC::XVMADDADP, PPC::XVADDDP, PPC::XVMULDP, 1, 2, PPC::XVSUBDP},
306  {PPC::XVMADDASP, PPC::XVADDSP, PPC::XVMULSP, 1, 2, PPC::XVSUBSP},
307  {PPC::FMADD, PPC::FADD, PPC::FMUL, 3, 1, PPC::FSUB},
308  {PPC::FMADDS, PPC::FADDS, PPC::FMULS, 3, 1, PPC::FSUBS}};
309 
310 // Check if an opcode is a FMA instruction. If it is, return the index in array
311 // FMAOpIdxInfo. Otherwise, return -1.
312 int16_t PPCInstrInfo::getFMAOpIdxInfo(unsigned Opcode) const {
313  for (unsigned I = 0; I < array_lengthof(FMAOpIdxInfo); I++)
314  if (FMAOpIdxInfo[I][InfoArrayIdxFMAInst] == Opcode)
315  return I;
316  return -1;
317 }
318 
319 // On PowerPC target, we have two kinds of patterns related to FMA:
320 // 1: Improve ILP.
321 // Try to reassociate FMA chains like below:
322 //
323 // Pattern 1:
324 // A = FADD X, Y (Leaf)
325 // B = FMA A, M21, M22 (Prev)
326 // C = FMA B, M31, M32 (Root)
327 // -->
328 // A = FMA X, M21, M22
329 // B = FMA Y, M31, M32
330 // C = FADD A, B
331 //
332 // Pattern 2:
333 // A = FMA X, M11, M12 (Leaf)
334 // B = FMA A, M21, M22 (Prev)
335 // C = FMA B, M31, M32 (Root)
336 // -->
337 // A = FMUL M11, M12
338 // B = FMA X, M21, M22
339 // D = FMA A, M31, M32
340 // C = FADD B, D
341 //
342 // breaking the dependency between A and B, allowing FMA to be executed in
343 // parallel (or back-to-back in a pipeline) instead of depending on each other.
344 //
345 // 2: Reduce register pressure.
346 // Try to reassociate FMA with FSUB and a constant like below:
347 // C is a floating point const.
348 //
349 // Pattern 1:
350 // A = FSUB X, Y (Leaf)
351 // D = FMA B, C, A (Root)
352 // -->
353 // A = FMA B, Y, -C
354 // D = FMA A, X, C
355 //
356 // Pattern 2:
357 // A = FSUB X, Y (Leaf)
358 // D = FMA B, A, C (Root)
359 // -->
360 // A = FMA B, Y, -C
361 // D = FMA A, X, C
362 //
363 // Before the transformation, A must be assigned with different hardware
364 // register with D. After the transformation, A and D must be assigned with
365 // same hardware register due to TIE attribute of FMA instructions.
366 //
369  bool DoRegPressureReduce) const {
370  MachineBasicBlock *MBB = Root.getParent();
373 
374  auto IsAllOpsVirtualReg = [](const MachineInstr &Instr) {
375  for (const auto &MO : Instr.explicit_operands())
376  if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
377  return false;
378  return true;
379  };
380 
381  auto IsReassociableAddOrSub = [&](const MachineInstr &Instr,
382  unsigned OpType) {
383  if (Instr.getOpcode() !=
384  FMAOpIdxInfo[getFMAOpIdxInfo(Root.getOpcode())][OpType])
385  return false;
386 
387  // Instruction can be reassociated.
388  // fast math flags may prohibit reassociation.
389  if (!(Instr.getFlag(MachineInstr::MIFlag::FmReassoc) &&
390  Instr.getFlag(MachineInstr::MIFlag::FmNsz)))
391  return false;
392 
393  // Instruction operands are virtual registers for reassociation.
394  if (!IsAllOpsVirtualReg(Instr))
395  return false;
396 
397  // For register pressure reassociation, the FSub must have only one use as
398  // we want to delete the sub to save its def.
399  if (OpType == InfoArrayIdxFSubInst &&
400  !MRI->hasOneNonDBGUse(Instr.getOperand(0).getReg()))
401  return false;
402 
403  return true;
404  };
405 
406  auto IsReassociableFMA = [&](const MachineInstr &Instr, int16_t &AddOpIdx,
407  int16_t &MulOpIdx, bool IsLeaf) {
408  int16_t Idx = getFMAOpIdxInfo(Instr.getOpcode());
409  if (Idx < 0)
410  return false;
411 
412  // Instruction can be reassociated.
413  // fast math flags may prohibit reassociation.
414  if (!(Instr.getFlag(MachineInstr::MIFlag::FmReassoc) &&
415  Instr.getFlag(MachineInstr::MIFlag::FmNsz)))
416  return false;
417 
418  // Instruction operands are virtual registers for reassociation.
419  if (!IsAllOpsVirtualReg(Instr))
420  return false;
421 
422  MulOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxMULOpIdx];
423  if (IsLeaf)
424  return true;
425 
426  AddOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxAddOpIdx];
427 
428  const MachineOperand &OpAdd = Instr.getOperand(AddOpIdx);
429  MachineInstr *MIAdd = MRI->getUniqueVRegDef(OpAdd.getReg());
430  // If 'add' operand's def is not in current block, don't do ILP related opt.
431  if (!MIAdd || MIAdd->getParent() != MBB)
432  return false;
433 
434  // If this is not Leaf FMA Instr, its 'add' operand should only have one use
435  // as this fma will be changed later.
436  return IsLeaf ? true : MRI->hasOneNonDBGUse(OpAdd.getReg());
437  };
438 
439  int16_t AddOpIdx = -1;
440  int16_t MulOpIdx = -1;
441 
442  bool IsUsedOnceL = false;
443  bool IsUsedOnceR = false;
444  MachineInstr *MULInstrL = nullptr;
445  MachineInstr *MULInstrR = nullptr;
446 
447  auto IsRPReductionCandidate = [&]() {
448  // Currently, we only support float and double.
449  // FIXME: add support for other types.
450  unsigned Opcode = Root.getOpcode();
451  if (Opcode != PPC::XSMADDASP && Opcode != PPC::XSMADDADP)
452  return false;
453 
454  // Root must be a valid FMA like instruction.
455  // Treat it as leaf as we don't care its add operand.
456  if (IsReassociableFMA(Root, AddOpIdx, MulOpIdx, true)) {
457  assert((MulOpIdx >= 0) && "mul operand index not right!");
459  Root.getOperand(MulOpIdx).getReg(), MRI);
461  Root.getOperand(MulOpIdx + 1).getReg(), MRI);
462  if (!MULRegL && !MULRegR)
463  return false;
464 
465  if (MULRegL && !MULRegR) {
466  MULRegR =
467  TRI->lookThruCopyLike(Root.getOperand(MulOpIdx + 1).getReg(), MRI);
468  IsUsedOnceL = true;
469  } else if (!MULRegL && MULRegR) {
470  MULRegL =
471  TRI->lookThruCopyLike(Root.getOperand(MulOpIdx).getReg(), MRI);
472  IsUsedOnceR = true;
473  } else {
474  IsUsedOnceL = true;
475  IsUsedOnceR = true;
476  }
477 
478  if (!Register::isVirtualRegister(MULRegL) ||
479  !Register::isVirtualRegister(MULRegR))
480  return false;
481 
482  MULInstrL = MRI->getVRegDef(MULRegL);
483  MULInstrR = MRI->getVRegDef(MULRegR);
484  return true;
485  }
486  return false;
487  };
488 
489  // Register pressure fma reassociation patterns.
490  if (DoRegPressureReduce && IsRPReductionCandidate()) {
491  assert((MULInstrL && MULInstrR) && "wrong register preduction candidate!");
492  // Register pressure pattern 1
493  if (isLoadFromConstantPool(MULInstrL) && IsUsedOnceR &&
494  IsReassociableAddOrSub(*MULInstrR, InfoArrayIdxFSubInst)) {
495  LLVM_DEBUG(dbgs() << "add pattern REASSOC_XY_BCA\n");
496  Patterns.push_back(MachineCombinerPattern::REASSOC_XY_BCA);
497  return true;
498  }
499 
500  // Register pressure pattern 2
501  if ((isLoadFromConstantPool(MULInstrR) && IsUsedOnceL &&
502  IsReassociableAddOrSub(*MULInstrL, InfoArrayIdxFSubInst))) {
503  LLVM_DEBUG(dbgs() << "add pattern REASSOC_XY_BAC\n");
504  Patterns.push_back(MachineCombinerPattern::REASSOC_XY_BAC);
505  return true;
506  }
507  }
508 
509  // ILP fma reassociation patterns.
510  // Root must be a valid FMA like instruction.
511  AddOpIdx = -1;
512  if (!IsReassociableFMA(Root, AddOpIdx, MulOpIdx, false))
513  return false;
514 
515  assert((AddOpIdx >= 0) && "add operand index not right!");
516 
517  Register RegB = Root.getOperand(AddOpIdx).getReg();
518  MachineInstr *Prev = MRI->getUniqueVRegDef(RegB);
519 
520  // Prev must be a valid FMA like instruction.
521  AddOpIdx = -1;
522  if (!IsReassociableFMA(*Prev, AddOpIdx, MulOpIdx, false))
523  return false;
524 
525  assert((AddOpIdx >= 0) && "add operand index not right!");
526 
527  Register RegA = Prev->getOperand(AddOpIdx).getReg();
528  MachineInstr *Leaf = MRI->getUniqueVRegDef(RegA);
529  AddOpIdx = -1;
530  if (IsReassociableFMA(*Leaf, AddOpIdx, MulOpIdx, true)) {
532  LLVM_DEBUG(dbgs() << "add pattern REASSOC_XMM_AMM_BMM\n");
533  return true;
534  }
535  if (IsReassociableAddOrSub(*Leaf, InfoArrayIdxFAddInst)) {
536  Patterns.push_back(MachineCombinerPattern::REASSOC_XY_AMM_BMM);
537  LLVM_DEBUG(dbgs() << "add pattern REASSOC_XY_AMM_BMM\n");
538  return true;
539  }
540  return false;
541 }
542 
545  SmallVectorImpl<MachineInstr *> &InsInstrs) const {
546  assert(!InsInstrs.empty() && "Instructions set to be inserted is empty!");
547 
548  MachineFunction *MF = Root.getMF();
552 
553  int16_t Idx = getFMAOpIdxInfo(Root.getOpcode());
554  if (Idx < 0)
555  return;
556 
557  uint16_t FirstMulOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxMULOpIdx];
558 
559  // For now we only need to fix up placeholder for register pressure reduce
560  // patterns.
561  Register ConstReg = 0;
562  switch (P) {
564  ConstReg =
565  TRI->lookThruCopyLike(Root.getOperand(FirstMulOpIdx).getReg(), MRI);
566  break;
568  ConstReg =
569  TRI->lookThruCopyLike(Root.getOperand(FirstMulOpIdx + 1).getReg(), MRI);
570  break;
571  default:
572  // Not register pressure reduce patterns.
573  return;
574  }
575 
576  MachineInstr *ConstDefInstr = MRI->getVRegDef(ConstReg);
577  // Get const value from const pool.
578  const Constant *C = getConstantFromConstantPool(ConstDefInstr);
579  assert(isa<llvm::ConstantFP>(C) && "not a valid constant!");
580 
581  // Get negative fp const.
582  APFloat F1((dyn_cast<ConstantFP>(C))->getValueAPF());
583  F1.changeSign();
584  Constant *NegC = ConstantFP::get(dyn_cast<ConstantFP>(C)->getContext(), F1);
585  Align Alignment = MF->getDataLayout().getPrefTypeAlign(C->getType());
586 
587  // Put negative fp const into constant pool.
588  unsigned ConstPoolIdx = MCP->getConstantPoolIndex(NegC, Alignment);
589 
590  MachineOperand *Placeholder = nullptr;
591  // Record the placeholder PPC::ZERO8 we add in reassociateFMA.
592  for (auto *Inst : InsInstrs) {
593  for (MachineOperand &Operand : Inst->explicit_operands()) {
594  assert(Operand.isReg() && "Invalid instruction in InsInstrs!");
595  if (Operand.getReg() == PPC::ZERO8) {
596  Placeholder = &Operand;
597  break;
598  }
599  }
600  }
601 
602  assert(Placeholder && "Placeholder does not exist!");
603 
604  // Generate instructions to load the const fp from constant pool.
605  // We only support PPC64 and medium code model.
606  Register LoadNewConst =
607  generateLoadForNewConst(ConstPoolIdx, &Root, C->getType(), InsInstrs);
608 
609  // Fill the placeholder with the new load from constant pool.
610  Placeholder->setReg(LoadNewConst);
611 }
612 
614  MachineBasicBlock *MBB, RegisterClassInfo *RegClassInfo) const {
615 
617  return false;
618 
619  // Currently, we only enable register pressure reducing in machine combiner
620  // for: 1: PPC64; 2: Code Model is Medium; 3: Power9 which also has vector
621  // support.
622  //
623  // So we need following instructions to access a TOC entry:
624  //
625  // %6:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, %const.0
626  // %7:vssrc = DFLOADf32 target-flags(ppc-toc-lo) %const.0,
627  // killed %6:g8rc_and_g8rc_nox0, implicit $x2 :: (load 4 from constant-pool)
628  //
629  // FIXME: add more supported targets, like Small and Large code model, PPC32,
630  // AIX.
631  if (!(Subtarget.isPPC64() && Subtarget.hasP9Vector() &&
633  return false;
634 
636  MachineFunction *MF = MBB->getParent();
638 
639  auto GetMBBPressure = [&](MachineBasicBlock *MBB) -> std::vector<unsigned> {
640  RegionPressure Pressure;
641  RegPressureTracker RPTracker(Pressure);
642 
643  // Initialize the register pressure tracker.
644  RPTracker.init(MBB->getParent(), RegClassInfo, nullptr, MBB, MBB->end(),
645  /*TrackLaneMasks*/ false, /*TrackUntiedDefs=*/true);
646 
648  MIE = MBB->instr_begin();
649  MII != MIE; --MII) {
650  MachineInstr &MI = *std::prev(MII);
651  if (MI.isDebugValue() || MI.isDebugLabel())
652  continue;
653  RegisterOperands RegOpers;
654  RegOpers.collect(MI, *TRI, *MRI, false, false);
655  RPTracker.recedeSkipDebugValues();
656  assert(&*RPTracker.getPos() == &MI && "RPTracker sync error!");
657  RPTracker.recede(RegOpers);
658  }
659 
660  // Close the RPTracker to finalize live ins.
661  RPTracker.closeRegion();
662 
663  return RPTracker.getPressure().MaxSetPressure;
664  };
665 
666  // For now we only care about float and double type fma.
667  unsigned VSSRCLimit = TRI->getRegPressureSetLimit(
668  *MBB->getParent(), PPC::RegisterPressureSets::VSSRC);
669 
670  // Only reduce register pressure when pressure is high.
671  return GetMBBPressure(MBB)[PPC::RegisterPressureSets::VSSRC] >
672  (float)VSSRCLimit * FMARPFactor;
673 }
674 
675 bool PPCInstrInfo::isLoadFromConstantPool(MachineInstr *I) const {
676  // I has only one memory operand which is load from constant pool.
677  if (!I->hasOneMemOperand())
678  return false;
679 
680  MachineMemOperand *Op = I->memoperands()[0];
681  return Op->isLoad() && Op->getPseudoValue() &&
682  Op->getPseudoValue()->kind() == PseudoSourceValue::ConstantPool;
683 }
684 
685 Register PPCInstrInfo::generateLoadForNewConst(
686  unsigned Idx, MachineInstr *MI, Type *Ty,
687  SmallVectorImpl<MachineInstr *> &InsInstrs) const {
688  // Now we only support PPC64, Medium code model and P9 with vector.
689  // We have immutable pattern to access const pool. See function
690  // shouldReduceRegisterPressure.
691  assert((Subtarget.isPPC64() && Subtarget.hasP9Vector() &&
692  Subtarget.getTargetMachine().getCodeModel() == CodeModel::Medium) &&
693  "Target not supported!\n");
694 
695  MachineFunction *MF = MI->getMF();
697 
698  // Generate ADDIStocHA8
699  Register VReg1 = MRI->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass);
700  MachineInstrBuilder TOCOffset =
701  BuildMI(*MF, MI->getDebugLoc(), get(PPC::ADDIStocHA8), VReg1)
702  .addReg(PPC::X2)
703  .addConstantPoolIndex(Idx);
704 
705  assert((Ty->isFloatTy() || Ty->isDoubleTy()) &&
706  "Only float and double are supported!");
707 
708  unsigned LoadOpcode;
709  // Should be float type or double type.
710  if (Ty->isFloatTy())
711  LoadOpcode = PPC::DFLOADf32;
712  else
713  LoadOpcode = PPC::DFLOADf64;
714 
715  const TargetRegisterClass *RC = MRI->getRegClass(MI->getOperand(0).getReg());
716  Register VReg2 = MRI->createVirtualRegister(RC);
719  Ty->getScalarSizeInBits() / 8, MF->getDataLayout().getPrefTypeAlign(Ty));
720 
721  // Generate Load from constant pool.
723  BuildMI(*MF, MI->getDebugLoc(), get(LoadOpcode), VReg2)
725  .addReg(VReg1, getKillRegState(true))
726  .addMemOperand(MMO);
727 
728  Load->getOperand(1).setTargetFlags(PPCII::MO_TOC_LO);
729 
730  // Insert the toc load instructions into InsInstrs.
731  InsInstrs.insert(InsInstrs.begin(), Load);
732  InsInstrs.insert(InsInstrs.begin(), TOCOffset);
733  return VReg2;
734 }
735 
736 // This function returns the const value in constant pool if the \p I is a load
737 // from constant pool.
738 const Constant *
739 PPCInstrInfo::getConstantFromConstantPool(MachineInstr *I) const {
740  MachineFunction *MF = I->getMF();
743  assert(I->mayLoad() && "Should be a load instruction.\n");
744  for (auto MO : I->uses()) {
745  if (!MO.isReg())
746  continue;
747  Register Reg = MO.getReg();
748  if (Reg == 0 || !Register::isVirtualRegister(Reg))
749  continue;
750  // Find the toc address.
752  for (auto MO2 : DefMI->uses())
753  if (MO2.isCPI())
754  return (MCP->getConstants())[MO2.getIndex()].Val.ConstVal;
755  }
756  return nullptr;
757 }
758 
761  bool DoRegPressureReduce) const {
762  // Using the machine combiner in this way is potentially expensive, so
763  // restrict to when aggressive optimizations are desired.
765  return false;
766 
767  if (getFMAPatterns(Root, Patterns, DoRegPressureReduce))
768  return true;
769 
770  return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns,
771  DoRegPressureReduce);
772 }
773 
778  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
779  switch (Pattern) {
784  reassociateFMA(Root, Pattern, InsInstrs, DelInstrs, InstrIdxForVirtReg);
785  break;
786  default:
787  // Reassociate default patterns.
789  DelInstrs, InstrIdxForVirtReg);
790  break;
791  }
792 }
793 
794 void PPCInstrInfo::reassociateFMA(
798  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
799  MachineFunction *MF = Root.getMF();
802  MachineOperand &OpC = Root.getOperand(0);
803  Register RegC = OpC.getReg();
804  const TargetRegisterClass *RC = MRI.getRegClass(RegC);
805  MRI.constrainRegClass(RegC, RC);
806 
807  unsigned FmaOp = Root.getOpcode();
808  int16_t Idx = getFMAOpIdxInfo(FmaOp);
809  assert(Idx >= 0 && "Root must be a FMA instruction");
810 
811  bool IsILPReassociate =
814 
815  uint16_t AddOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxAddOpIdx];
816  uint16_t FirstMulOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxMULOpIdx];
817 
818  MachineInstr *Prev = nullptr;
819  MachineInstr *Leaf = nullptr;
820  switch (Pattern) {
821  default:
822  llvm_unreachable("not recognized pattern!");
825  Prev = MRI.getUniqueVRegDef(Root.getOperand(AddOpIdx).getReg());
826  Leaf = MRI.getUniqueVRegDef(Prev->getOperand(AddOpIdx).getReg());
827  break;
829  Register MULReg =
830  TRI->lookThruCopyLike(Root.getOperand(FirstMulOpIdx).getReg(), &MRI);
831  Leaf = MRI.getVRegDef(MULReg);
832  break;
833  }
835  Register MULReg = TRI->lookThruCopyLike(
836  Root.getOperand(FirstMulOpIdx + 1).getReg(), &MRI);
837  Leaf = MRI.getVRegDef(MULReg);
838  break;
839  }
840  }
841 
842  uint16_t IntersectedFlags = 0;
843  if (IsILPReassociate)
844  IntersectedFlags = Root.getFlags() & Prev->getFlags() & Leaf->getFlags();
845  else
846  IntersectedFlags = Root.getFlags() & Leaf->getFlags();
847 
848  auto GetOperandInfo = [&](const MachineOperand &Operand, Register &Reg,
849  bool &KillFlag) {
850  Reg = Operand.getReg();
852  KillFlag = Operand.isKill();
853  };
854 
855  auto GetFMAInstrInfo = [&](const MachineInstr &Instr, Register &MulOp1,
856  Register &MulOp2, Register &AddOp,
857  bool &MulOp1KillFlag, bool &MulOp2KillFlag,
858  bool &AddOpKillFlag) {
859  GetOperandInfo(Instr.getOperand(FirstMulOpIdx), MulOp1, MulOp1KillFlag);
860  GetOperandInfo(Instr.getOperand(FirstMulOpIdx + 1), MulOp2, MulOp2KillFlag);
861  GetOperandInfo(Instr.getOperand(AddOpIdx), AddOp, AddOpKillFlag);
862  };
863 
864  Register RegM11, RegM12, RegX, RegY, RegM21, RegM22, RegM31, RegM32, RegA11,
865  RegA21, RegB;
866  bool KillX = false, KillY = false, KillM11 = false, KillM12 = false,
867  KillM21 = false, KillM22 = false, KillM31 = false, KillM32 = false,
868  KillA11 = false, KillA21 = false, KillB = false;
869 
870  GetFMAInstrInfo(Root, RegM31, RegM32, RegB, KillM31, KillM32, KillB);
871 
872  if (IsILPReassociate)
873  GetFMAInstrInfo(*Prev, RegM21, RegM22, RegA21, KillM21, KillM22, KillA21);
874 
876  GetFMAInstrInfo(*Leaf, RegM11, RegM12, RegA11, KillM11, KillM12, KillA11);
877  GetOperandInfo(Leaf->getOperand(AddOpIdx), RegX, KillX);
879  GetOperandInfo(Leaf->getOperand(1), RegX, KillX);
880  GetOperandInfo(Leaf->getOperand(2), RegY, KillY);
881  } else {
882  // Get FSUB instruction info.
883  GetOperandInfo(Leaf->getOperand(1), RegX, KillX);
884  GetOperandInfo(Leaf->getOperand(2), RegY, KillY);
885  }
886 
887  // Create new virtual registers for the new results instead of
888  // recycling legacy ones because the MachineCombiner's computation of the
889  // critical path requires a new register definition rather than an existing
890  // one.
891  // For register pressure reassociation, we only need create one virtual
892  // register for the new fma.
893  Register NewVRA = MRI.createVirtualRegister(RC);
894  InstrIdxForVirtReg.insert(std::make_pair(NewVRA, 0));
895 
896  Register NewVRB = 0;
897  if (IsILPReassociate) {
898  NewVRB = MRI.createVirtualRegister(RC);
899  InstrIdxForVirtReg.insert(std::make_pair(NewVRB, 1));
900  }
901 
902  Register NewVRD = 0;
904  NewVRD = MRI.createVirtualRegister(RC);
905  InstrIdxForVirtReg.insert(std::make_pair(NewVRD, 2));
906  }
907 
908  auto AdjustOperandOrder = [&](MachineInstr *MI, Register RegAdd, bool KillAdd,
909  Register RegMul1, bool KillRegMul1,
910  Register RegMul2, bool KillRegMul2) {
911  MI->getOperand(AddOpIdx).setReg(RegAdd);
912  MI->getOperand(AddOpIdx).setIsKill(KillAdd);
913  MI->getOperand(FirstMulOpIdx).setReg(RegMul1);
914  MI->getOperand(FirstMulOpIdx).setIsKill(KillRegMul1);
915  MI->getOperand(FirstMulOpIdx + 1).setReg(RegMul2);
916  MI->getOperand(FirstMulOpIdx + 1).setIsKill(KillRegMul2);
917  };
918 
919  MachineInstrBuilder NewARegPressure, NewCRegPressure;
920  switch (Pattern) {
921  default:
922  llvm_unreachable("not recognized pattern!");
924  // Create new instructions for insertion.
925  MachineInstrBuilder MINewB =
926  BuildMI(*MF, Prev->getDebugLoc(), get(FmaOp), NewVRB)
927  .addReg(RegX, getKillRegState(KillX))
928  .addReg(RegM21, getKillRegState(KillM21))
929  .addReg(RegM22, getKillRegState(KillM22));
930  MachineInstrBuilder MINewA =
931  BuildMI(*MF, Root.getDebugLoc(), get(FmaOp), NewVRA)
932  .addReg(RegY, getKillRegState(KillY))
933  .addReg(RegM31, getKillRegState(KillM31))
934  .addReg(RegM32, getKillRegState(KillM32));
935  // If AddOpIdx is not 1, adjust the order.
936  if (AddOpIdx != 1) {
937  AdjustOperandOrder(MINewB, RegX, KillX, RegM21, KillM21, RegM22, KillM22);
938  AdjustOperandOrder(MINewA, RegY, KillY, RegM31, KillM31, RegM32, KillM32);
939  }
940 
941  MachineInstrBuilder MINewC =
942  BuildMI(*MF, Root.getDebugLoc(),
944  .addReg(NewVRB, getKillRegState(true))
945  .addReg(NewVRA, getKillRegState(true));
946 
947  // Update flags for newly created instructions.
948  setSpecialOperandAttr(*MINewA, IntersectedFlags);
949  setSpecialOperandAttr(*MINewB, IntersectedFlags);
950  setSpecialOperandAttr(*MINewC, IntersectedFlags);
951 
952  // Record new instructions for insertion.
953  InsInstrs.push_back(MINewA);
954  InsInstrs.push_back(MINewB);
955  InsInstrs.push_back(MINewC);
956  break;
957  }
959  assert(NewVRD && "new FMA register not created!");
960  // Create new instructions for insertion.
961  MachineInstrBuilder MINewA =
962  BuildMI(*MF, Leaf->getDebugLoc(),
963  get(FMAOpIdxInfo[Idx][InfoArrayIdxFMULInst]), NewVRA)
964  .addReg(RegM11, getKillRegState(KillM11))
965  .addReg(RegM12, getKillRegState(KillM12));
966  MachineInstrBuilder MINewB =
967  BuildMI(*MF, Prev->getDebugLoc(), get(FmaOp), NewVRB)
968  .addReg(RegX, getKillRegState(KillX))
969  .addReg(RegM21, getKillRegState(KillM21))
970  .addReg(RegM22, getKillRegState(KillM22));
971  MachineInstrBuilder MINewD =
972  BuildMI(*MF, Root.getDebugLoc(), get(FmaOp), NewVRD)
973  .addReg(NewVRA, getKillRegState(true))
974  .addReg(RegM31, getKillRegState(KillM31))
975  .addReg(RegM32, getKillRegState(KillM32));
976  // If AddOpIdx is not 1, adjust the order.
977  if (AddOpIdx != 1) {
978  AdjustOperandOrder(MINewB, RegX, KillX, RegM21, KillM21, RegM22, KillM22);
979  AdjustOperandOrder(MINewD, NewVRA, true, RegM31, KillM31, RegM32,
980  KillM32);
981  }
982 
983  MachineInstrBuilder MINewC =
984  BuildMI(*MF, Root.getDebugLoc(),
986  .addReg(NewVRB, getKillRegState(true))
987  .addReg(NewVRD, getKillRegState(true));
988 
989  // Update flags for newly created instructions.
990  setSpecialOperandAttr(*MINewA, IntersectedFlags);
991  setSpecialOperandAttr(*MINewB, IntersectedFlags);
992  setSpecialOperandAttr(*MINewD, IntersectedFlags);
993  setSpecialOperandAttr(*MINewC, IntersectedFlags);
994 
995  // Record new instructions for insertion.
996  InsInstrs.push_back(MINewA);
997  InsInstrs.push_back(MINewB);
998  InsInstrs.push_back(MINewD);
999  InsInstrs.push_back(MINewC);
1000  break;
1001  }
1004  Register VarReg;
1005  bool KillVarReg = false;
1007  VarReg = RegM31;
1008  KillVarReg = KillM31;
1009  } else {
1010  VarReg = RegM32;
1011  KillVarReg = KillM32;
1012  }
1013  // We don't want to get negative const from memory pool too early, as the
1014  // created entry will not be deleted even if it has no users. Since all
1015  // operand of Leaf and Root are virtual register, we use zero register
1016  // here as a placeholder. When the InsInstrs is selected in
1017  // MachineCombiner, we call finalizeInsInstrs to replace the zero register
1018  // with a virtual register which is a load from constant pool.
1019  NewARegPressure = BuildMI(*MF, Root.getDebugLoc(), get(FmaOp), NewVRA)
1020  .addReg(RegB, getKillRegState(RegB))
1021  .addReg(RegY, getKillRegState(KillY))
1022  .addReg(PPC::ZERO8);
1023  NewCRegPressure = BuildMI(*MF, Root.getDebugLoc(), get(FmaOp), RegC)
1024  .addReg(NewVRA, getKillRegState(true))
1025  .addReg(RegX, getKillRegState(KillX))
1026  .addReg(VarReg, getKillRegState(KillVarReg));
1027  // For now, we only support xsmaddadp/xsmaddasp, their add operand are
1028  // both at index 1, no need to adjust.
1029  // FIXME: when add more fma instructions support, like fma/fmas, adjust
1030  // the operand index here.
1031  break;
1032  }
1033  }
1034 
1035  if (!IsILPReassociate) {
1036  setSpecialOperandAttr(*NewARegPressure, IntersectedFlags);
1037  setSpecialOperandAttr(*NewCRegPressure, IntersectedFlags);
1038 
1039  InsInstrs.push_back(NewARegPressure);
1040  InsInstrs.push_back(NewCRegPressure);
1041  }
1042 
1043  assert(!InsInstrs.empty() &&
1044  "Insertion instructions set should not be empty!");
1045 
1046  // Record old instructions for deletion.
1047  DelInstrs.push_back(Leaf);
1048  if (IsILPReassociate)
1049  DelInstrs.push_back(Prev);
1050  DelInstrs.push_back(&Root);
1051 }
1052 
1053 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
1055  Register &SrcReg, Register &DstReg,
1056  unsigned &SubIdx) const {
1057  switch (MI.getOpcode()) {
1058  default: return false;
1059  case PPC::EXTSW:
1060  case PPC::EXTSW_32:
1061  case PPC::EXTSW_32_64:
1062  SrcReg = MI.getOperand(1).getReg();
1063  DstReg = MI.getOperand(0).getReg();
1064  SubIdx = PPC::sub_32;
1065  return true;
1066  }
1067 }
1068 
1070  int &FrameIndex) const {
1071  unsigned Opcode = MI.getOpcode();
1072  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1073  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
1074 
1075  if (End != std::find(OpcodesForSpill, End, Opcode)) {
1076  // Check for the operands added by addFrameReference (the immediate is the
1077  // offset which defaults to 0).
1078  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
1079  MI.getOperand(2).isFI()) {
1080  FrameIndex = MI.getOperand(2).getIndex();
1081  return MI.getOperand(0).getReg();
1082  }
1083  }
1084  return 0;
1085 }
1086 
1087 // For opcodes with the ReMaterializable flag set, this function is called to
1088 // verify the instruction is really rematable.
1090  AliasAnalysis *AA) const {
1091  switch (MI.getOpcode()) {
1092  default:
1093  // This function should only be called for opcodes with the ReMaterializable
1094  // flag set.
1095  llvm_unreachable("Unknown rematerializable operation!");
1096  break;
1097  case PPC::LI:
1098  case PPC::LI8:
1099  case PPC::PLI:
1100  case PPC::PLI8:
1101  case PPC::LIS:
1102  case PPC::LIS8:
1103  case PPC::ADDIStocHA:
1104  case PPC::ADDIStocHA8:
1105  case PPC::ADDItocL:
1106  case PPC::LOAD_STACK_GUARD:
1107  case PPC::XXLXORz:
1108  case PPC::XXLXORspz:
1109  case PPC::XXLXORdpz:
1110  case PPC::XXLEQVOnes:
1111  case PPC::XXSPLTI32DX:
1112  case PPC::V_SET0B:
1113  case PPC::V_SET0H:
1114  case PPC::V_SET0:
1115  case PPC::V_SETALLONESB:
1116  case PPC::V_SETALLONESH:
1117  case PPC::V_SETALLONES:
1118  case PPC::CRSET:
1119  case PPC::CRUNSET:
1120  case PPC::XXSETACCZ:
1121  return true;
1122  }
1123  return false;
1124 }
1125 
1127  int &FrameIndex) const {
1128  unsigned Opcode = MI.getOpcode();
1129  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1130  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
1131 
1132  if (End != std::find(OpcodesForSpill, End, Opcode)) {
1133  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
1134  MI.getOperand(2).isFI()) {
1135  FrameIndex = MI.getOperand(2).getIndex();
1136  return MI.getOperand(0).getReg();
1137  }
1138  }
1139  return 0;
1140 }
1141 
1143  unsigned OpIdx1,
1144  unsigned OpIdx2) const {
1145  MachineFunction &MF = *MI.getParent()->getParent();
1146 
1147  // Normal instructions can be commuted the obvious way.
1148  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMI_rec)
1149  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1150  // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
1151  // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
1152  // changing the relative order of the mask operands might change what happens
1153  // to the high-bits of the mask (and, thus, the result).
1154 
1155  // Cannot commute if it has a non-zero rotate count.
1156  if (MI.getOperand(3).getImm() != 0)
1157  return nullptr;
1158 
1159  // If we have a zero rotate count, we have:
1160  // M = mask(MB,ME)
1161  // Op0 = (Op1 & ~M) | (Op2 & M)
1162  // Change this to:
1163  // M = mask((ME+1)&31, (MB-1)&31)
1164  // Op0 = (Op2 & ~M) | (Op1 & M)
1165 
1166  // Swap op1/op2
1167  assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
1168  "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMI_rec.");
1169  Register Reg0 = MI.getOperand(0).getReg();
1170  Register Reg1 = MI.getOperand(1).getReg();
1171  Register Reg2 = MI.getOperand(2).getReg();
1172  unsigned SubReg1 = MI.getOperand(1).getSubReg();
1173  unsigned SubReg2 = MI.getOperand(2).getSubReg();
1174  bool Reg1IsKill = MI.getOperand(1).isKill();
1175  bool Reg2IsKill = MI.getOperand(2).isKill();
1176  bool ChangeReg0 = false;
1177  // If machine instrs are no longer in two-address forms, update
1178  // destination register as well.
1179  if (Reg0 == Reg1) {
1180  // Must be two address instruction!
1181  assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
1182  "Expecting a two-address instruction!");
1183  assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
1184  Reg2IsKill = false;
1185  ChangeReg0 = true;
1186  }
1187 
1188  // Masks.
1189  unsigned MB = MI.getOperand(4).getImm();
1190  unsigned ME = MI.getOperand(5).getImm();
1191 
1192  // We can't commute a trivial mask (there is no way to represent an all-zero
1193  // mask).
1194  if (MB == 0 && ME == 31)
1195  return nullptr;
1196 
1197  if (NewMI) {
1198  // Create a new instruction.
1199  Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
1200  bool Reg0IsDead = MI.getOperand(0).isDead();
1201  return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
1202  .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
1203  .addReg(Reg2, getKillRegState(Reg2IsKill))
1204  .addReg(Reg1, getKillRegState(Reg1IsKill))
1205  .addImm((ME + 1) & 31)
1206  .addImm((MB - 1) & 31);
1207  }
1208 
1209  if (ChangeReg0) {
1210  MI.getOperand(0).setReg(Reg2);
1211  MI.getOperand(0).setSubReg(SubReg2);
1212  }
1213  MI.getOperand(2).setReg(Reg1);
1214  MI.getOperand(1).setReg(Reg2);
1215  MI.getOperand(2).setSubReg(SubReg1);
1216  MI.getOperand(1).setSubReg(SubReg2);
1217  MI.getOperand(2).setIsKill(Reg1IsKill);
1218  MI.getOperand(1).setIsKill(Reg2IsKill);
1219 
1220  // Swap the mask around.
1221  MI.getOperand(4).setImm((ME + 1) & 31);
1222  MI.getOperand(5).setImm((MB - 1) & 31);
1223  return &MI;
1224 }
1225 
1227  unsigned &SrcOpIdx1,
1228  unsigned &SrcOpIdx2) const {
1229  // For VSX A-Type FMA instructions, it is the first two operands that can be
1230  // commuted, however, because the non-encoded tied input operand is listed
1231  // first, the operands to swap are actually the second and third.
1232 
1233  int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
1234  if (AltOpc == -1)
1235  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1236 
1237  // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
1238  // and SrcOpIdx2.
1239  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
1240 }
1241 
1244  // This function is used for scheduling, and the nop wanted here is the type
1245  // that terminates dispatch groups on the POWER cores.
1246  unsigned Directive = Subtarget.getCPUDirective();
1247  unsigned Opcode;
1248  switch (Directive) {
1249  default: Opcode = PPC::NOP; break;
1250  case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
1251  case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
1252  case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
1253  // FIXME: Update when POWER9 scheduling model is ready.
1254  case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
1255  }
1256 
1257  DebugLoc DL;
1258  BuildMI(MBB, MI, DL, get(Opcode));
1259 }
1260 
1261 /// Return the noop instruction to use for a noop.
1263  MCInst Nop;
1264  Nop.setOpcode(PPC::NOP);
1265  return Nop;
1266 }
1267 
1268 // Branch analysis.
1269 // Note: If the condition register is set to CTR or CTR8 then this is a
1270 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
1272  MachineBasicBlock *&TBB,
1273  MachineBasicBlock *&FBB,
1275  bool AllowModify) const {
1276  bool isPPC64 = Subtarget.isPPC64();
1277 
1278  // If the block has no terminators, it just falls into the block after it.
1280  if (I == MBB.end())
1281  return false;
1282 
1283  if (!isUnpredicatedTerminator(*I))
1284  return false;
1285 
1286  if (AllowModify) {
1287  // If the BB ends with an unconditional branch to the fallthrough BB,
1288  // we eliminate the branch instruction.
1289  if (I->getOpcode() == PPC::B &&
1290  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1291  I->eraseFromParent();
1292 
1293  // We update iterator after deleting the last branch.
1295  if (I == MBB.end() || !isUnpredicatedTerminator(*I))
1296  return false;
1297  }
1298  }
1299 
1300  // Get the last instruction in the block.
1301  MachineInstr &LastInst = *I;
1302 
1303  // If there is only one terminator instruction, process it.
1304  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
1305  if (LastInst.getOpcode() == PPC::B) {
1306  if (!LastInst.getOperand(0).isMBB())
1307  return true;
1308  TBB = LastInst.getOperand(0).getMBB();
1309  return false;
1310  } else if (LastInst.getOpcode() == PPC::BCC) {
1311  if (!LastInst.getOperand(2).isMBB())
1312  return true;
1313  // Block ends with fall-through condbranch.
1314  TBB = LastInst.getOperand(2).getMBB();
1315  Cond.push_back(LastInst.getOperand(0));
1316  Cond.push_back(LastInst.getOperand(1));
1317  return false;
1318  } else if (LastInst.getOpcode() == PPC::BC) {
1319  if (!LastInst.getOperand(1).isMBB())
1320  return true;
1321  // Block ends with fall-through condbranch.
1322  TBB = LastInst.getOperand(1).getMBB();
1324  Cond.push_back(LastInst.getOperand(0));
1325  return false;
1326  } else if (LastInst.getOpcode() == PPC::BCn) {
1327  if (!LastInst.getOperand(1).isMBB())
1328  return true;
1329  // Block ends with fall-through condbranch.
1330  TBB = LastInst.getOperand(1).getMBB();
1332  Cond.push_back(LastInst.getOperand(0));
1333  return false;
1334  } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
1335  LastInst.getOpcode() == PPC::BDNZ) {
1336  if (!LastInst.getOperand(0).isMBB())
1337  return true;
1338  if (DisableCTRLoopAnal)
1339  return true;
1340  TBB = LastInst.getOperand(0).getMBB();
1341  Cond.push_back(MachineOperand::CreateImm(1));
1342  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
1343  true));
1344  return false;
1345  } else if (LastInst.getOpcode() == PPC::BDZ8 ||
1346  LastInst.getOpcode() == PPC::BDZ) {
1347  if (!LastInst.getOperand(0).isMBB())
1348  return true;
1349  if (DisableCTRLoopAnal)
1350  return true;
1351  TBB = LastInst.getOperand(0).getMBB();
1352  Cond.push_back(MachineOperand::CreateImm(0));
1353  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
1354  true));
1355  return false;
1356  }
1357 
1358  // Otherwise, don't know what this is.
1359  return true;
1360  }
1361 
1362  // Get the instruction before it if it's a terminator.
1363  MachineInstr &SecondLastInst = *I;
1364 
1365  // If there are three terminators, we don't know what sort of block this is.
1366  if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
1367  return true;
1368 
1369  // If the block ends with PPC::B and PPC:BCC, handle it.
1370  if (SecondLastInst.getOpcode() == PPC::BCC &&
1371  LastInst.getOpcode() == PPC::B) {
1372  if (!SecondLastInst.getOperand(2).isMBB() ||
1373  !LastInst.getOperand(0).isMBB())
1374  return true;
1375  TBB = SecondLastInst.getOperand(2).getMBB();
1376  Cond.push_back(SecondLastInst.getOperand(0));
1377  Cond.push_back(SecondLastInst.getOperand(1));
1378  FBB = LastInst.getOperand(0).getMBB();
1379  return false;
1380  } else if (SecondLastInst.getOpcode() == PPC::BC &&
1381  LastInst.getOpcode() == PPC::B) {
1382  if (!SecondLastInst.getOperand(1).isMBB() ||
1383  !LastInst.getOperand(0).isMBB())
1384  return true;
1385  TBB = SecondLastInst.getOperand(1).getMBB();
1387  Cond.push_back(SecondLastInst.getOperand(0));
1388  FBB = LastInst.getOperand(0).getMBB();
1389  return false;
1390  } else if (SecondLastInst.getOpcode() == PPC::BCn &&
1391  LastInst.getOpcode() == PPC::B) {
1392  if (!SecondLastInst.getOperand(1).isMBB() ||
1393  !LastInst.getOperand(0).isMBB())
1394  return true;
1395  TBB = SecondLastInst.getOperand(1).getMBB();
1397  Cond.push_back(SecondLastInst.getOperand(0));
1398  FBB = LastInst.getOperand(0).getMBB();
1399  return false;
1400  } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
1401  SecondLastInst.getOpcode() == PPC::BDNZ) &&
1402  LastInst.getOpcode() == PPC::B) {
1403  if (!SecondLastInst.getOperand(0).isMBB() ||
1404  !LastInst.getOperand(0).isMBB())
1405  return true;
1406  if (DisableCTRLoopAnal)
1407  return true;
1408  TBB = SecondLastInst.getOperand(0).getMBB();
1409  Cond.push_back(MachineOperand::CreateImm(1));
1410  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
1411  true));
1412  FBB = LastInst.getOperand(0).getMBB();
1413  return false;
1414  } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
1415  SecondLastInst.getOpcode() == PPC::BDZ) &&
1416  LastInst.getOpcode() == PPC::B) {
1417  if (!SecondLastInst.getOperand(0).isMBB() ||
1418  !LastInst.getOperand(0).isMBB())
1419  return true;
1420  if (DisableCTRLoopAnal)
1421  return true;
1422  TBB = SecondLastInst.getOperand(0).getMBB();
1423  Cond.push_back(MachineOperand::CreateImm(0));
1424  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
1425  true));
1426  FBB = LastInst.getOperand(0).getMBB();
1427  return false;
1428  }
1429 
1430  // If the block ends with two PPC:Bs, handle it. The second one is not
1431  // executed, so remove it.
1432  if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
1433  if (!SecondLastInst.getOperand(0).isMBB())
1434  return true;
1435  TBB = SecondLastInst.getOperand(0).getMBB();
1436  I = LastInst;
1437  if (AllowModify)
1438  I->eraseFromParent();
1439  return false;
1440  }
1441 
1442  // Otherwise, can't handle this.
1443  return true;
1444 }
1445 
1447  int *BytesRemoved) const {
1448  assert(!BytesRemoved && "code size not handled");
1449 
1451  if (I == MBB.end())
1452  return 0;
1453 
1454  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
1455  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
1456  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
1457  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
1458  return 0;
1459 
1460  // Remove the branch.
1461  I->eraseFromParent();
1462 
1463  I = MBB.end();
1464 
1465  if (I == MBB.begin()) return 1;
1466  --I;
1467  if (I->getOpcode() != PPC::BCC &&
1468  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
1469  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
1470  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
1471  return 1;
1472 
1473  // Remove the branch.
1474  I->eraseFromParent();
1475  return 2;
1476 }
1477 
1479  MachineBasicBlock *TBB,
1480  MachineBasicBlock *FBB,
1482  const DebugLoc &DL,
1483  int *BytesAdded) const {
1484  // Shouldn't be a fall through.
1485  assert(TBB && "insertBranch must not be told to insert a fallthrough");
1486  assert((Cond.size() == 2 || Cond.size() == 0) &&
1487  "PPC branch conditions have two components!");
1488  assert(!BytesAdded && "code size not handled");
1489 
1490  bool isPPC64 = Subtarget.isPPC64();
1491 
1492  // One-way branch.
1493  if (!FBB) {
1494  if (Cond.empty()) // Unconditional branch
1495  BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
1496  else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
1497  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
1498  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1499  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
1500  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
1501  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
1502  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
1503  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
1504  else // Conditional branch
1505  BuildMI(&MBB, DL, get(PPC::BCC))
1506  .addImm(Cond[0].getImm())
1507  .add(Cond[1])
1508  .addMBB(TBB);
1509  return 1;
1510  }
1511 
1512  // Two-way Conditional Branch.
1513  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
1514  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
1515  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1516  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
1517  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
1518  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
1519  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
1520  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
1521  else
1522  BuildMI(&MBB, DL, get(PPC::BCC))
1523  .addImm(Cond[0].getImm())
1524  .add(Cond[1])
1525  .addMBB(TBB);
1526  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
1527  return 2;
1528 }
1529 
1530 // Select analysis.
1533  Register DstReg, Register TrueReg,
1534  Register FalseReg, int &CondCycles,
1535  int &TrueCycles, int &FalseCycles) const {
1536  if (Cond.size() != 2)
1537  return false;
1538 
1539  // If this is really a bdnz-like condition, then it cannot be turned into a
1540  // select.
1541  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
1542  return false;
1543 
1544  // Check register classes.
1546  const TargetRegisterClass *RC =
1547  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
1548  if (!RC)
1549  return false;
1550 
1551  // isel is for regular integer GPRs only.
1552  if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
1553  !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
1554  !PPC::G8RCRegClass.hasSubClassEq(RC) &&
1555  !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
1556  return false;
1557 
1558  // FIXME: These numbers are for the A2, how well they work for other cores is
1559  // an open question. On the A2, the isel instruction has a 2-cycle latency
1560  // but single-cycle throughput. These numbers are used in combination with
1561  // the MispredictPenalty setting from the active SchedMachineModel.
1562  CondCycles = 1;
1563  TrueCycles = 1;
1564  FalseCycles = 1;
1565 
1566  return true;
1567 }
1568 
1571  const DebugLoc &dl, Register DestReg,
1573  Register FalseReg) const {
1574  assert(Cond.size() == 2 &&
1575  "PPC branch conditions have two components!");
1576 
1577  // Get the register classes.
1579  const TargetRegisterClass *RC =
1580  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
1581  assert(RC && "TrueReg and FalseReg must have overlapping register classes");
1582 
1583  bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
1584  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
1585  assert((Is64Bit ||
1586  PPC::GPRCRegClass.hasSubClassEq(RC) ||
1587  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
1588  "isel is for regular integer GPRs only");
1589 
1590  unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
1591  auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
1592 
1593  unsigned SubIdx = 0;
1594  bool SwapOps = false;
1595  switch (SelectPred) {
1596  case PPC::PRED_EQ:
1597  case PPC::PRED_EQ_MINUS:
1598  case PPC::PRED_EQ_PLUS:
1599  SubIdx = PPC::sub_eq; SwapOps = false; break;
1600  case PPC::PRED_NE:
1601  case PPC::PRED_NE_MINUS:
1602  case PPC::PRED_NE_PLUS:
1603  SubIdx = PPC::sub_eq; SwapOps = true; break;
1604  case PPC::PRED_LT:
1605  case PPC::PRED_LT_MINUS:
1606  case PPC::PRED_LT_PLUS:
1607  SubIdx = PPC::sub_lt; SwapOps = false; break;
1608  case PPC::PRED_GE:
1609  case PPC::PRED_GE_MINUS:
1610  case PPC::PRED_GE_PLUS:
1611  SubIdx = PPC::sub_lt; SwapOps = true; break;
1612  case PPC::PRED_GT:
1613  case PPC::PRED_GT_MINUS:
1614  case PPC::PRED_GT_PLUS:
1615  SubIdx = PPC::sub_gt; SwapOps = false; break;
1616  case PPC::PRED_LE:
1617  case PPC::PRED_LE_MINUS:
1618  case PPC::PRED_LE_PLUS:
1619  SubIdx = PPC::sub_gt; SwapOps = true; break;
1620  case PPC::PRED_UN:
1621  case PPC::PRED_UN_MINUS:
1622  case PPC::PRED_UN_PLUS:
1623  SubIdx = PPC::sub_un; SwapOps = false; break;
1624  case PPC::PRED_NU:
1625  case PPC::PRED_NU_MINUS:
1626  case PPC::PRED_NU_PLUS:
1627  SubIdx = PPC::sub_un; SwapOps = true; break;
1628  case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
1629  case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
1630  }
1631 
1632  Register FirstReg = SwapOps ? FalseReg : TrueReg,
1633  SecondReg = SwapOps ? TrueReg : FalseReg;
1634 
1635  // The first input register of isel cannot be r0. If it is a member
1636  // of a register class that can be r0, then copy it first (the
1637  // register allocator should eliminate the copy).
1638  if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
1639  MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
1640  const TargetRegisterClass *FirstRC =
1641  MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
1642  &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
1643  Register OldFirstReg = FirstReg;
1644  FirstReg = MRI.createVirtualRegister(FirstRC);
1645  BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
1646  .addReg(OldFirstReg);
1647  }
1648 
1649  BuildMI(MBB, MI, dl, get(OpCode), DestReg)
1650  .addReg(FirstReg).addReg(SecondReg)
1651  .addReg(Cond[1].getReg(), 0, SubIdx);
1652 }
1653 
1654 static unsigned getCRBitValue(unsigned CRBit) {
1655  unsigned Ret = 4;
1656  if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
1657  CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
1658  CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
1659  CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
1660  Ret = 3;
1661  if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
1662  CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
1663  CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
1664  CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
1665  Ret = 2;
1666  if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
1667  CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
1668  CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
1669  CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
1670  Ret = 1;
1671  if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
1672  CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
1673  CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
1674  CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
1675  Ret = 0;
1676 
1677  assert(Ret != 4 && "Invalid CR bit register");
1678  return Ret;
1679 }
1680 
1683  const DebugLoc &DL, MCRegister DestReg,
1684  MCRegister SrcReg, bool KillSrc) const {
1685  // We can end up with self copies and similar things as a result of VSX copy
1686  // legalization. Promote them here.
1688  if (PPC::F8RCRegClass.contains(DestReg) &&
1689  PPC::VSRCRegClass.contains(SrcReg)) {
1690  MCRegister SuperReg =
1691  TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
1692 
1693  if (VSXSelfCopyCrash && SrcReg == SuperReg)
1694  llvm_unreachable("nop VSX copy");
1695 
1696  DestReg = SuperReg;
1697  } else if (PPC::F8RCRegClass.contains(SrcReg) &&
1698  PPC::VSRCRegClass.contains(DestReg)) {
1699  MCRegister SuperReg =
1700  TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
1701 
1702  if (VSXSelfCopyCrash && DestReg == SuperReg)
1703  llvm_unreachable("nop VSX copy");
1704 
1705  SrcReg = SuperReg;
1706  }
1707 
1708  // Different class register copy
1709  if (PPC::CRBITRCRegClass.contains(SrcReg) &&
1710  PPC::GPRCRegClass.contains(DestReg)) {
1711  MCRegister CRReg = getCRFromCRBit(SrcReg);
1712  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
1713  getKillRegState(KillSrc);
1714  // Rotate the CR bit in the CR fields to be the least significant bit and
1715  // then mask with 0x1 (MB = ME = 31).
1716  BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
1717  .addReg(DestReg, RegState::Kill)
1718  .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
1719  .addImm(31)
1720  .addImm(31);
1721  return;
1722  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
1723  (PPC::G8RCRegClass.contains(DestReg) ||
1724  PPC::GPRCRegClass.contains(DestReg))) {
1725  bool Is64Bit = PPC::G8RCRegClass.contains(DestReg);
1726  unsigned MvCode = Is64Bit ? PPC::MFOCRF8 : PPC::MFOCRF;
1727  unsigned ShCode = Is64Bit ? PPC::RLWINM8 : PPC::RLWINM;
1728  unsigned CRNum = TRI->getEncodingValue(SrcReg);
1729  BuildMI(MBB, I, DL, get(MvCode), DestReg).addReg(SrcReg);
1730  getKillRegState(KillSrc);
1731  if (CRNum == 7)
1732  return;
1733  // Shift the CR bits to make the CR field in the lowest 4 bits of GRC.
1734  BuildMI(MBB, I, DL, get(ShCode), DestReg)
1735  .addReg(DestReg, RegState::Kill)
1736  .addImm(CRNum * 4 + 4)
1737  .addImm(28)
1738  .addImm(31);
1739  return;
1740  } else if (PPC::G8RCRegClass.contains(SrcReg) &&
1741  PPC::VSFRCRegClass.contains(DestReg)) {
1742  assert(Subtarget.hasDirectMove() &&
1743  "Subtarget doesn't support directmove, don't know how to copy.");
1744  BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
1745  NumGPRtoVSRSpill++;
1746  getKillRegState(KillSrc);
1747  return;
1748  } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
1749  PPC::G8RCRegClass.contains(DestReg)) {
1750  assert(Subtarget.hasDirectMove() &&
1751  "Subtarget doesn't support directmove, don't know how to copy.");
1752  BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
1753  getKillRegState(KillSrc);
1754  return;
1755  } else if (PPC::SPERCRegClass.contains(SrcReg) &&
1756  PPC::GPRCRegClass.contains(DestReg)) {
1757  BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
1758  getKillRegState(KillSrc);
1759  return;
1760  } else if (PPC::GPRCRegClass.contains(SrcReg) &&
1761  PPC::SPERCRegClass.contains(DestReg)) {
1762  BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
1763  getKillRegState(KillSrc);
1764  return;
1765  }
1766 
1767  unsigned Opc;
1768  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
1769  Opc = PPC::OR;
1770  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
1771  Opc = PPC::OR8;
1772  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
1773  Opc = PPC::FMR;
1774  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
1775  Opc = PPC::MCRF;
1776  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
1777  Opc = PPC::VOR;
1778  else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
1779  // There are two different ways this can be done:
1780  // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
1781  // issue in VSU pipeline 0.
1782  // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
1783  // can go to either pipeline.
1784  // We'll always use xxlor here, because in practically all cases where
1785  // copies are generated, they are close enough to some use that the
1786  // lower-latency form is preferable.
1787  Opc = PPC::XXLOR;
1788  else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
1789  PPC::VSSRCRegClass.contains(DestReg, SrcReg))
1790  Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf;
1791  else if (Subtarget.pairedVectorMemops() &&
1792  PPC::VSRpRCRegClass.contains(DestReg, SrcReg)) {
1793  if (SrcReg > PPC::VSRp15)
1794  SrcReg = PPC::V0 + (SrcReg - PPC::VSRp16) * 2;
1795  else
1796  SrcReg = PPC::VSL0 + (SrcReg - PPC::VSRp0) * 2;
1797  if (DestReg > PPC::VSRp15)
1798  DestReg = PPC::V0 + (DestReg - PPC::VSRp16) * 2;
1799  else
1800  DestReg = PPC::VSL0 + (DestReg - PPC::VSRp0) * 2;
1801  BuildMI(MBB, I, DL, get(PPC::XXLOR), DestReg).
1802  addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1803  BuildMI(MBB, I, DL, get(PPC::XXLOR), DestReg + 1).
1804  addReg(SrcReg + 1).addReg(SrcReg + 1, getKillRegState(KillSrc));
1805  return;
1806  }
1807  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
1808  Opc = PPC::CROR;
1809  else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
1810  Opc = PPC::EVOR;
1811  else if ((PPC::ACCRCRegClass.contains(DestReg) ||
1812  PPC::UACCRCRegClass.contains(DestReg)) &&
1813  (PPC::ACCRCRegClass.contains(SrcReg) ||
1814  PPC::UACCRCRegClass.contains(SrcReg))) {
1815  // If primed, de-prime the source register, copy the individual registers
1816  // and prime the destination if needed. The vector subregisters are
1817  // vs[(u)acc * 4] - vs[(u)acc * 4 + 3]. If the copy is not a kill and the
1818  // source is primed, we need to re-prime it after the copy as well.
1819  PPCRegisterInfo::emitAccCopyInfo(MBB, DestReg, SrcReg);
1820  bool DestPrimed = PPC::ACCRCRegClass.contains(DestReg);
1821  bool SrcPrimed = PPC::ACCRCRegClass.contains(SrcReg);
1822  MCRegister VSLSrcReg =
1823  PPC::VSL0 + (SrcReg - (SrcPrimed ? PPC::ACC0 : PPC::UACC0)) * 4;
1824  MCRegister VSLDestReg =
1825  PPC::VSL0 + (DestReg - (DestPrimed ? PPC::ACC0 : PPC::UACC0)) * 4;
1826  if (SrcPrimed)
1827  BuildMI(MBB, I, DL, get(PPC::XXMFACC), SrcReg).addReg(SrcReg);
1828  for (unsigned Idx = 0; Idx < 4; Idx++)
1829  BuildMI(MBB, I, DL, get(PPC::XXLOR), VSLDestReg + Idx)
1830  .addReg(VSLSrcReg + Idx)
1831  .addReg(VSLSrcReg + Idx, getKillRegState(KillSrc));
1832  if (DestPrimed)
1833  BuildMI(MBB, I, DL, get(PPC::XXMTACC), DestReg).addReg(DestReg);
1834  if (SrcPrimed && !KillSrc)
1835  BuildMI(MBB, I, DL, get(PPC::XXMTACC), SrcReg).addReg(SrcReg);
1836  return;
1837  } else
1838  llvm_unreachable("Impossible reg-to-reg copy");
1839 
1840  const MCInstrDesc &MCID = get(Opc);
1841  if (MCID.getNumOperands() == 3)
1842  BuildMI(MBB, I, DL, MCID, DestReg)
1843  .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1844  else
1845  BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1846 }
1847 
1848 unsigned PPCInstrInfo::getSpillIndex(const TargetRegisterClass *RC) const {
1849  int OpcodeIndex = 0;
1850 
1851  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1852  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1854  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1855  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1857  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1859  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1861  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1863  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1865  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1867  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1869  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1871  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1873  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1875  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1877  } else if (PPC::ACCRCRegClass.hasSubClassEq(RC)) {
1878  assert(Subtarget.pairedVectorMemops() &&
1879  "Register unexpected when paired memops are disabled.");
1881  } else if (PPC::UACCRCRegClass.hasSubClassEq(RC)) {
1882  assert(Subtarget.pairedVectorMemops() &&
1883  "Register unexpected when paired memops are disabled.");
1885  } else if (PPC::VSRpRCRegClass.hasSubClassEq(RC)) {
1886  assert(Subtarget.pairedVectorMemops() &&
1887  "Register unexpected when paired memops are disabled.");
1889  } else {
1890  llvm_unreachable("Unknown regclass!");
1891  }
1892  return OpcodeIndex;
1893 }
1894 
1895 unsigned
1897  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1898  return OpcodesForSpill[getSpillIndex(RC)];
1899 }
1900 
1901 unsigned
1903  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1904  return OpcodesForSpill[getSpillIndex(RC)];
1905 }
1906 
1907 void PPCInstrInfo::StoreRegToStackSlot(
1908  MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
1909  const TargetRegisterClass *RC,
1910  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1911  unsigned Opcode = getStoreOpcodeForSpill(RC);
1912  DebugLoc DL;
1913 
1914  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1915  FuncInfo->setHasSpills();
1916 
1917  NewMIs.push_back(addFrameReference(
1918  BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1919  FrameIdx));
1920 
1921  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1922  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1923  FuncInfo->setSpillsCR();
1924 
1925  if (isXFormMemOp(Opcode))
1926  FuncInfo->setHasNonRISpills();
1927 }
1928 
1931  bool isKill, int FrameIdx, const TargetRegisterClass *RC,
1932  const TargetRegisterInfo *TRI) const {
1933  MachineFunction &MF = *MBB.getParent();
1935 
1936  StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1937 
1938  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1939  MBB.insert(MI, NewMIs[i]);
1940 
1941  const MachineFrameInfo &MFI = MF.getFrameInfo();
1943  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1945  MFI.getObjectAlign(FrameIdx));
1946  NewMIs.back()->addMemOperand(MF, MMO);
1947 }
1948 
1951  Register SrcReg, bool isKill,
1952  int FrameIdx,
1953  const TargetRegisterClass *RC,
1954  const TargetRegisterInfo *TRI) const {
1955  // We need to avoid a situation in which the value from a VRRC register is
1956  // spilled using an Altivec instruction and reloaded into a VSRC register
1957  // using a VSX instruction. The issue with this is that the VSX
1958  // load/store instructions swap the doublewords in the vector and the Altivec
1959  // ones don't. The register classes on the spill/reload may be different if
1960  // the register is defined using an Altivec instruction and is then used by a
1961  // VSX instruction.
1962  RC = updatedRC(RC);
1963  storeRegToStackSlotNoUpd(MBB, MI, SrcReg, isKill, FrameIdx, RC, TRI);
1964 }
1965 
1966 void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1967  unsigned DestReg, int FrameIdx,
1968  const TargetRegisterClass *RC,
1970  const {
1971  unsigned Opcode = getLoadOpcodeForSpill(RC);
1972  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
1973  FrameIdx));
1974  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1975 
1976  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1977  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1978  FuncInfo->setSpillsCR();
1979 
1980  if (isXFormMemOp(Opcode))
1981  FuncInfo->setHasNonRISpills();
1982 }
1983 
1986  int FrameIdx, const TargetRegisterClass *RC,
1987  const TargetRegisterInfo *TRI) const {
1988  MachineFunction &MF = *MBB.getParent();
1990  DebugLoc DL;
1991  if (MI != MBB.end()) DL = MI->getDebugLoc();
1992 
1993  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1994  FuncInfo->setHasSpills();
1995 
1996  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
1997 
1998  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1999  MBB.insert(MI, NewMIs[i]);
2000 
2001  const MachineFrameInfo &MFI = MF.getFrameInfo();
2003  MachinePointerInfo::getFixedStack(MF, FrameIdx),
2005  MFI.getObjectAlign(FrameIdx));
2006  NewMIs.back()->addMemOperand(MF, MMO);
2007 }
2008 
2011  Register DestReg, int FrameIdx,
2012  const TargetRegisterClass *RC,
2013  const TargetRegisterInfo *TRI) const {
2014  // We need to avoid a situation in which the value from a VRRC register is
2015  // spilled using an Altivec instruction and reloaded into a VSRC register
2016  // using a VSX instruction. The issue with this is that the VSX
2017  // load/store instructions swap the doublewords in the vector and the Altivec
2018  // ones don't. The register classes on the spill/reload may be different if
2019  // the register is defined using an Altivec instruction and is then used by a
2020  // VSX instruction.
2021  RC = updatedRC(RC);
2022 
2023  loadRegFromStackSlotNoUpd(MBB, MI, DestReg, FrameIdx, RC, TRI);
2024 }
2025 
2026 bool PPCInstrInfo::
2028  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
2029  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
2030  Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
2031  else
2032  // Leave the CR# the same, but invert the condition.
2033  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
2034  return false;
2035 }
2036 
2037 // For some instructions, it is legal to fold ZERO into the RA register field.
2038 // This function performs that fold by replacing the operand with PPC::ZERO,
2039 // it does not consider whether the load immediate zero is no longer in use.
2041  Register Reg) const {
2042  // A zero immediate should always be loaded with a single li.
2043  unsigned DefOpc = DefMI.getOpcode();
2044  if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
2045  return false;
2046  if (!DefMI.getOperand(1).isImm())
2047  return false;
2048  if (DefMI.getOperand(1).getImm() != 0)
2049  return false;
2050 
2051  // Note that we cannot here invert the arguments of an isel in order to fold
2052  // a ZERO into what is presented as the second argument. All we have here
2053  // is the condition bit, and that might come from a CR-logical bit operation.
2054 
2055  const MCInstrDesc &UseMCID = UseMI.getDesc();
2056 
2057  // Only fold into real machine instructions.
2058  if (UseMCID.isPseudo())
2059  return false;
2060 
2061  // We need to find which of the User's operands is to be folded, that will be
2062  // the operand that matches the given register ID.
2063  unsigned UseIdx;
2064  for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
2065  if (UseMI.getOperand(UseIdx).isReg() &&
2066  UseMI.getOperand(UseIdx).getReg() == Reg)
2067  break;
2068 
2069  assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
2070  assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
2071 
2072  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
2073 
2074  // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
2075  // register (which might also be specified as a pointer class kind).
2076  if (UseInfo->isLookupPtrRegClass()) {
2077  if (UseInfo->RegClass /* Kind */ != 1)
2078  return false;
2079  } else {
2080  if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
2081  UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
2082  return false;
2083  }
2084 
2085  // Make sure this is not tied to an output register (or otherwise
2086  // constrained). This is true for ST?UX registers, for example, which
2087  // are tied to their output registers.
2088  if (UseInfo->Constraints != 0)
2089  return false;
2090 
2091  MCRegister ZeroReg;
2092  if (UseInfo->isLookupPtrRegClass()) {
2093  bool isPPC64 = Subtarget.isPPC64();
2094  ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
2095  } else {
2096  ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
2097  PPC::ZERO8 : PPC::ZERO;
2098  }
2099 
2100  UseMI.getOperand(UseIdx).setReg(ZeroReg);
2101  return true;
2102 }
2103 
2104 // Folds zero into instructions which have a load immediate zero as an operand
2105 // but also recognize zero as immediate zero. If the definition of the load
2106 // has no more users it is deleted.
2108  Register Reg, MachineRegisterInfo *MRI) const {
2109  bool Changed = onlyFoldImmediate(UseMI, DefMI, Reg);
2110  if (MRI->use_nodbg_empty(Reg))
2111  DefMI.eraseFromParent();
2112  return Changed;
2113 }
2114 
2117  I != IE; ++I)
2118  if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
2119  return true;
2120  return false;
2121 }
2122 
2123 // We should make sure that, if we're going to predicate both sides of a
2124 // condition (a diamond), that both sides don't define the counter register. We
2125 // can predicate counter-decrement-based branches, but while that predicates
2126 // the branching, it does not predicate the counter decrement. If we tried to
2127 // merge the triangle into one predicated block, we'd decrement the counter
2128 // twice.
2130  unsigned NumT, unsigned ExtraT,
2131  MachineBasicBlock &FMBB,
2132  unsigned NumF, unsigned ExtraF,
2133  BranchProbability Probability) const {
2134  return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
2135 }
2136 
2137 
2139  // The predicated branches are identified by their type, not really by the
2140  // explicit presence of a predicate. Furthermore, some of them can be
2141  // predicated more than once. Because if conversion won't try to predicate
2142  // any instruction which already claims to be predicated (by returning true
2143  // here), always return false. In doing so, we let isPredicable() be the
2144  // final word on whether not the instruction can be (further) predicated.
2145 
2146  return false;
2147 }
2148 
2150  const MachineBasicBlock *MBB,
2151  const MachineFunction &MF) const {
2152  // Set MFFS and MTFSF as scheduling boundary to avoid unexpected code motion
2153  // across them, since some FP operations may change content of FPSCR.
2154  // TODO: Model FPSCR in PPC instruction definitions and remove the workaround
2155  if (MI.getOpcode() == PPC::MFFS || MI.getOpcode() == PPC::MTFSF)
2156  return true;
2158 }
2159 
2161  ArrayRef<MachineOperand> Pred) const {
2162  unsigned OpC = MI.getOpcode();
2163  if (OpC == PPC::BLR || OpC == PPC::BLR8) {
2164  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
2165  bool isPPC64 = Subtarget.isPPC64();
2166  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
2167  : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
2168  // Need add Def and Use for CTR implicit operand.
2169  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2170  .addReg(Pred[1].getReg(), RegState::Implicit)
2171  .addReg(Pred[1].getReg(), RegState::ImplicitDefine);
2172  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
2173  MI.setDesc(get(PPC::BCLR));
2174  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
2175  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
2176  MI.setDesc(get(PPC::BCLRn));
2177  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
2178  } else {
2179  MI.setDesc(get(PPC::BCCLR));
2180  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2181  .addImm(Pred[0].getImm())
2182  .add(Pred[1]);
2183  }
2184 
2185  return true;
2186  } else if (OpC == PPC::B) {
2187  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
2188  bool isPPC64 = Subtarget.isPPC64();
2189  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
2190  : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
2191  // Need add Def and Use for CTR implicit operand.
2192  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2193  .addReg(Pred[1].getReg(), RegState::Implicit)
2194  .addReg(Pred[1].getReg(), RegState::ImplicitDefine);
2195  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
2196  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
2197  MI.RemoveOperand(0);
2198 
2199  MI.setDesc(get(PPC::BC));
2200  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2201  .add(Pred[1])
2202  .addMBB(MBB);
2203  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
2204  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
2205  MI.RemoveOperand(0);
2206 
2207  MI.setDesc(get(PPC::BCn));
2208  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2209  .add(Pred[1])
2210  .addMBB(MBB);
2211  } else {
2212  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
2213  MI.RemoveOperand(0);
2214 
2215  MI.setDesc(get(PPC::BCC));
2216  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2217  .addImm(Pred[0].getImm())
2218  .add(Pred[1])
2219  .addMBB(MBB);
2220  }
2221 
2222  return true;
2223  } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL ||
2224  OpC == PPC::BCTRL8) {
2225  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
2226  llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
2227 
2228  bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
2229  bool isPPC64 = Subtarget.isPPC64();
2230 
2231  if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
2232  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
2233  : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
2234  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
2235  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
2236  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
2237  : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
2238  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
2239  } else {
2240  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
2241  : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
2242  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2243  .addImm(Pred[0].getImm())
2244  .add(Pred[1]);
2245  }
2246 
2247  // Need add Def and Use for LR implicit operand.
2248  if (setLR)
2249  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2250  .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::Implicit)
2251  .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::ImplicitDefine);
2252 
2253  return true;
2254  }
2255 
2256  return false;
2257 }
2258 
2260  ArrayRef<MachineOperand> Pred2) const {
2261  assert(Pred1.size() == 2 && "Invalid PPC first predicate");
2262  assert(Pred2.size() == 2 && "Invalid PPC second predicate");
2263 
2264  if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
2265  return false;
2266  if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
2267  return false;
2268 
2269  // P1 can only subsume P2 if they test the same condition register.
2270  if (Pred1[1].getReg() != Pred2[1].getReg())
2271  return false;
2272 
2273  PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
2274  PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
2275 
2276  if (P1 == P2)
2277  return true;
2278 
2279  // Does P1 subsume P2, e.g. GE subsumes GT.
2280  if (P1 == PPC::PRED_LE &&
2281  (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
2282  return true;
2283  if (P1 == PPC::PRED_GE &&
2284  (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
2285  return true;
2286 
2287  return false;
2288 }
2289 
2291  std::vector<MachineOperand> &Pred,
2292  bool SkipDead) const {
2293  // Note: At the present time, the contents of Pred from this function is
2294  // unused by IfConversion. This implementation follows ARM by pushing the
2295  // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
2296  // predicate, instructions defining CTR or CTR8 are also included as
2297  // predicate-defining instructions.
2298 
2299  const TargetRegisterClass *RCs[] =
2300  { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
2301  &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
2302 
2303  bool Found = false;
2304  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
2305  const MachineOperand &MO = MI.getOperand(i);
2306  for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
2307  const TargetRegisterClass *RC = RCs[c];
2308  if (MO.isReg()) {
2309  if (MO.isDef() && RC->contains(MO.getReg())) {
2310  Pred.push_back(MO);
2311  Found = true;
2312  }
2313  } else if (MO.isRegMask()) {
2314  for (TargetRegisterClass::iterator I = RC->begin(),
2315  IE = RC->end(); I != IE; ++I)
2316  if (MO.clobbersPhysReg(*I)) {
2317  Pred.push_back(MO);
2318  Found = true;
2319  }
2320  }
2321  }
2322  }
2323 
2324  return Found;
2325 }
2326 
2328  Register &SrcReg2, int &Mask,
2329  int &Value) const {
2330  unsigned Opc = MI.getOpcode();
2331 
2332  switch (Opc) {
2333  default: return false;
2334  case PPC::CMPWI:
2335  case PPC::CMPLWI:
2336  case PPC::CMPDI:
2337  case PPC::CMPLDI:
2338  SrcReg = MI.getOperand(1).getReg();
2339  SrcReg2 = 0;
2340  Value = MI.getOperand(2).getImm();
2341  Mask = 0xFFFF;
2342  return true;
2343  case PPC::CMPW:
2344  case PPC::CMPLW:
2345  case PPC::CMPD:
2346  case PPC::CMPLD:
2347  case PPC::FCMPUS:
2348  case PPC::FCMPUD:
2349  SrcReg = MI.getOperand(1).getReg();
2350  SrcReg2 = MI.getOperand(2).getReg();
2351  Value = 0;
2352  Mask = 0;
2353  return true;
2354  }
2355 }
2356 
2358  Register SrcReg2, int Mask, int Value,
2359  const MachineRegisterInfo *MRI) const {
2360  if (DisableCmpOpt)
2361  return false;
2362 
2363  int OpC = CmpInstr.getOpcode();
2364  Register CRReg = CmpInstr.getOperand(0).getReg();
2365 
2366  // FP record forms set CR1 based on the exception status bits, not a
2367  // comparison with zero.
2368  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
2369  return false;
2370 
2372  // The record forms set the condition register based on a signed comparison
2373  // with zero (so says the ISA manual). This is not as straightforward as it
2374  // seems, however, because this is always a 64-bit comparison on PPC64, even
2375  // for instructions that are 32-bit in nature (like slw for example).
2376  // So, on PPC32, for unsigned comparisons, we can use the record forms only
2377  // for equality checks (as those don't depend on the sign). On PPC64,
2378  // we are restricted to equality for unsigned 64-bit comparisons and for
2379  // signed 32-bit comparisons the applicability is more restricted.
2380  bool isPPC64 = Subtarget.isPPC64();
2381  bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
2382  bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
2383  bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
2384 
2385  // Look through copies unless that gets us to a physical register.
2386  Register ActualSrc = TRI->lookThruCopyLike(SrcReg, MRI);
2387  if (ActualSrc.isVirtual())
2388  SrcReg = ActualSrc;
2389 
2390  // Get the unique definition of SrcReg.
2391  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2392  if (!MI) return false;
2393 
2394  bool equalityOnly = false;
2395  bool noSub = false;
2396  if (isPPC64) {
2397  if (is32BitSignedCompare) {
2398  // We can perform this optimization only if MI is sign-extending.
2399  if (isSignExtended(*MI))
2400  noSub = true;
2401  else
2402  return false;
2403  } else if (is32BitUnsignedCompare) {
2404  // We can perform this optimization, equality only, if MI is
2405  // zero-extending.
2406  if (isZeroExtended(*MI)) {
2407  noSub = true;
2408  equalityOnly = true;
2409  } else
2410  return false;
2411  } else
2412  equalityOnly = is64BitUnsignedCompare;
2413  } else
2414  equalityOnly = is32BitUnsignedCompare;
2415 
2416  if (equalityOnly) {
2417  // We need to check the uses of the condition register in order to reject
2418  // non-equality comparisons.
2420  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
2421  I != IE; ++I) {
2422  MachineInstr *UseMI = &*I;
2423  if (UseMI->getOpcode() == PPC::BCC) {
2425  unsigned PredCond = PPC::getPredicateCondition(Pred);
2426  // We ignore hint bits when checking for non-equality comparisons.
2427  if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
2428  return false;
2429  } else if (UseMI->getOpcode() == PPC::ISEL ||
2430  UseMI->getOpcode() == PPC::ISEL8) {
2431  unsigned SubIdx = UseMI->getOperand(3).getSubReg();
2432  if (SubIdx != PPC::sub_eq)
2433  return false;
2434  } else
2435  return false;
2436  }
2437  }
2438 
2439  MachineBasicBlock::iterator I = CmpInstr;
2440 
2441  // Scan forward to find the first use of the compare.
2442  for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
2443  ++I) {
2444  bool FoundUse = false;
2446  J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
2447  J != JE; ++J)
2448  if (&*J == &*I) {
2449  FoundUse = true;
2450  break;
2451  }
2452 
2453  if (FoundUse)
2454  break;
2455  }
2456 
2459 
2460  // There are two possible candidates which can be changed to set CR[01].
2461  // One is MI, the other is a SUB instruction.
2462  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2463  MachineInstr *Sub = nullptr;
2464  if (SrcReg2 != 0)
2465  // MI is not a candidate for CMPrr.
2466  MI = nullptr;
2467  // FIXME: Conservatively refuse to convert an instruction which isn't in the
2468  // same BB as the comparison. This is to allow the check below to avoid calls
2469  // (and other explicit clobbers); instead we should really check for these
2470  // more explicitly (in at least a few predecessors).
2471  else if (MI->getParent() != CmpInstr.getParent())
2472  return false;
2473  else if (Value != 0) {
2474  // The record-form instructions set CR bit based on signed comparison
2475  // against 0. We try to convert a compare against 1 or -1 into a compare
2476  // against 0 to exploit record-form instructions. For example, we change
2477  // the condition "greater than -1" into "greater than or equal to 0"
2478  // and "less than 1" into "less than or equal to 0".
2479 
2480  // Since we optimize comparison based on a specific branch condition,
2481  // we don't optimize if condition code is used by more than once.
2482  if (equalityOnly || !MRI->hasOneUse(CRReg))
2483  return false;
2484 
2485  MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
2486  if (UseMI->getOpcode() != PPC::BCC)
2487  return false;
2488 
2490  unsigned PredCond = PPC::getPredicateCondition(Pred);
2491  unsigned PredHint = PPC::getPredicateHint(Pred);
2492  int16_t Immed = (int16_t)Value;
2493 
2494  // When modifying the condition in the predicate, we propagate hint bits
2495  // from the original predicate to the new one.
2496  if (Immed == -1 && PredCond == PPC::PRED_GT)
2497  // We convert "greater than -1" into "greater than or equal to 0",
2498  // since we are assuming signed comparison by !equalityOnly
2499  Pred = PPC::getPredicate(PPC::PRED_GE, PredHint);
2500  else if (Immed == -1 && PredCond == PPC::PRED_LE)
2501  // We convert "less than or equal to -1" into "less than 0".
2502  Pred = PPC::getPredicate(PPC::PRED_LT, PredHint);
2503  else if (Immed == 1 && PredCond == PPC::PRED_LT)
2504  // We convert "less than 1" into "less than or equal to 0".
2505  Pred = PPC::getPredicate(PPC::PRED_LE, PredHint);
2506  else if (Immed == 1 && PredCond == PPC::PRED_GE)
2507  // We convert "greater than or equal to 1" into "greater than 0".
2508  Pred = PPC::getPredicate(PPC::PRED_GT, PredHint);
2509  else
2510  return false;
2511 
2512  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)), Pred));
2513  }
2514 
2515  // Search for Sub.
2516  --I;
2517 
2518  // Get ready to iterate backward from CmpInstr.
2519  MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
2520 
2521  for (; I != E && !noSub; --I) {
2522  const MachineInstr &Instr = *I;
2523  unsigned IOpC = Instr.getOpcode();
2524 
2525  if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
2526  Instr.readsRegister(PPC::CR0, TRI)))
2527  // This instruction modifies or uses the record condition register after
2528  // the one we want to change. While we could do this transformation, it
2529  // would likely not be profitable. This transformation removes one
2530  // instruction, and so even forcing RA to generate one move probably
2531  // makes it unprofitable.
2532  return false;
2533 
2534  // Check whether CmpInstr can be made redundant by the current instruction.
2535  if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
2536  OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
2537  (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
2538  ((Instr.getOperand(1).getReg() == SrcReg &&
2539  Instr.getOperand(2).getReg() == SrcReg2) ||
2540  (Instr.getOperand(1).getReg() == SrcReg2 &&
2541  Instr.getOperand(2).getReg() == SrcReg))) {
2542  Sub = &*I;
2543  break;
2544  }
2545 
2546  if (I == B)
2547  // The 'and' is below the comparison instruction.
2548  return false;
2549  }
2550 
2551  // Return false if no candidates exist.
2552  if (!MI && !Sub)
2553  return false;
2554 
2555  // The single candidate is called MI.
2556  if (!MI) MI = Sub;
2557 
2558  int NewOpC = -1;
2559  int MIOpC = MI->getOpcode();
2560  if (MIOpC == PPC::ANDI_rec || MIOpC == PPC::ANDI8_rec ||
2561  MIOpC == PPC::ANDIS_rec || MIOpC == PPC::ANDIS8_rec)
2562  NewOpC = MIOpC;
2563  else {
2564  NewOpC = PPC::getRecordFormOpcode(MIOpC);
2565  if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
2566  NewOpC = MIOpC;
2567  }
2568 
2569  // FIXME: On the non-embedded POWER architectures, only some of the record
2570  // forms are fast, and we should use only the fast ones.
2571 
2572  // The defining instruction has a record form (or is already a record
2573  // form). It is possible, however, that we'll need to reverse the condition
2574  // code of the users.
2575  if (NewOpC == -1)
2576  return false;
2577 
2578  // This transformation should not be performed if `nsw` is missing and is not
2579  // `equalityOnly` comparison. Since if there is overflow, sub_lt, sub_gt in
2580  // CRReg do not reflect correct order. If `equalityOnly` is true, sub_eq in
2581  // CRReg can reflect if compared values are equal, this optz is still valid.
2582  if (!equalityOnly && (NewOpC == PPC::SUBF_rec || NewOpC == PPC::SUBF8_rec) &&
2583  Sub && !Sub->getFlag(MachineInstr::NoSWrap))
2584  return false;
2585 
2586  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
2587  // needs to be updated to be based on SUB. Push the condition code
2588  // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
2589  // condition code of these operands will be modified.
2590  // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
2591  // comparison against 0, which may modify predicate.
2592  bool ShouldSwap = false;
2593  if (Sub && Value == 0) {
2594  ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2595  Sub->getOperand(2).getReg() == SrcReg;
2596 
2597  // The operands to subf are the opposite of sub, so only in the fixed-point
2598  // case, invert the order.
2599  ShouldSwap = !ShouldSwap;
2600  }
2601 
2602  if (ShouldSwap)
2604  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
2605  I != IE; ++I) {
2606  MachineInstr *UseMI = &*I;
2607  if (UseMI->getOpcode() == PPC::BCC) {
2609  unsigned PredCond = PPC::getPredicateCondition(Pred);
2610  assert((!equalityOnly ||
2611  PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) &&
2612  "Invalid predicate for equality-only optimization");
2613  (void)PredCond; // To suppress warning in release build.
2614  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
2615  PPC::getSwappedPredicate(Pred)));
2616  } else if (UseMI->getOpcode() == PPC::ISEL ||
2617  UseMI->getOpcode() == PPC::ISEL8) {
2618  unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
2619  assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
2620  "Invalid CR bit for equality-only optimization");
2621 
2622  if (NewSubReg == PPC::sub_lt)
2623  NewSubReg = PPC::sub_gt;
2624  else if (NewSubReg == PPC::sub_gt)
2625  NewSubReg = PPC::sub_lt;
2626 
2627  SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
2628  NewSubReg));
2629  } else // We need to abort on a user we don't understand.
2630  return false;
2631  }
2632  assert(!(Value != 0 && ShouldSwap) &&
2633  "Non-zero immediate support and ShouldSwap"
2634  "may conflict in updating predicate");
2635 
2636  // Create a new virtual register to hold the value of the CR set by the
2637  // record-form instruction. If the instruction was not previously in
2638  // record form, then set the kill flag on the CR.
2639  CmpInstr.eraseFromParent();
2640 
2642  BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
2643  get(TargetOpcode::COPY), CRReg)
2644  .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
2645 
2646  // Even if CR0 register were dead before, it is alive now since the
2647  // instruction we just built uses it.
2648  MI->clearRegisterDeads(PPC::CR0);
2649 
2650  if (MIOpC != NewOpC) {
2651  // We need to be careful here: we're replacing one instruction with
2652  // another, and we need to make sure that we get all of the right
2653  // implicit uses and defs. On the other hand, the caller may be holding
2654  // an iterator to this instruction, and so we can't delete it (this is
2655  // specifically the case if this is the instruction directly after the
2656  // compare).
2657 
2658  // Rotates are expensive instructions. If we're emitting a record-form
2659  // rotate that can just be an andi/andis, we should just emit that.
2660  if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) {
2661  Register GPRRes = MI->getOperand(0).getReg();
2662  int64_t SH = MI->getOperand(2).getImm();
2663  int64_t MB = MI->getOperand(3).getImm();
2664  int64_t ME = MI->getOperand(4).getImm();
2665  // We can only do this if both the start and end of the mask are in the
2666  // same halfword.
2667  bool MBInLoHWord = MB >= 16;
2668  bool MEInLoHWord = ME >= 16;
2669  uint64_t Mask = ~0LLU;
2670 
2671  if (MB <= ME && MBInLoHWord == MEInLoHWord && SH == 0) {
2672  Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2673  // The mask value needs to shift right 16 if we're emitting andis.
2674  Mask >>= MBInLoHWord ? 0 : 16;
2675  NewOpC = MIOpC == PPC::RLWINM
2676  ? (MBInLoHWord ? PPC::ANDI_rec : PPC::ANDIS_rec)
2677  : (MBInLoHWord ? PPC::ANDI8_rec : PPC::ANDIS8_rec);
2678  } else if (MRI->use_empty(GPRRes) && (ME == 31) &&
2679  (ME - MB + 1 == SH) && (MB >= 16)) {
2680  // If we are rotating by the exact number of bits as are in the mask
2681  // and the mask is in the least significant bits of the register,
2682  // that's just an andis. (as long as the GPR result has no uses).
2683  Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
2684  Mask >>= 16;
2685  NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDIS_rec : PPC::ANDIS8_rec;
2686  }
2687  // If we've set the mask, we can transform.
2688  if (Mask != ~0LLU) {
2689  MI->RemoveOperand(4);
2690  MI->RemoveOperand(3);
2691  MI->getOperand(2).setImm(Mask);
2692  NumRcRotatesConvertedToRcAnd++;
2693  }
2694  } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
2695  int64_t MB = MI->getOperand(3).getImm();
2696  if (MB >= 48) {
2697  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2698  NewOpC = PPC::ANDI8_rec;
2699  MI->RemoveOperand(3);
2700  MI->getOperand(2).setImm(Mask);
2701  NumRcRotatesConvertedToRcAnd++;
2702  }
2703  }
2704 
2705  const MCInstrDesc &NewDesc = get(NewOpC);
2706  MI->setDesc(NewDesc);
2707 
2708  if (NewDesc.ImplicitDefs)
2709  for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
2710  *ImpDefs; ++ImpDefs)
2711  if (!MI->definesRegister(*ImpDefs))
2712  MI->addOperand(*MI->getParent()->getParent(),
2713  MachineOperand::CreateReg(*ImpDefs, true, true));
2714  if (NewDesc.ImplicitUses)
2715  for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
2716  *ImpUses; ++ImpUses)
2717  if (!MI->readsRegister(*ImpUses))
2718  MI->addOperand(*MI->getParent()->getParent(),
2719  MachineOperand::CreateReg(*ImpUses, false, true));
2720  }
2721  assert(MI->definesRegister(PPC::CR0) &&
2722  "Record-form instruction does not define cr0?");
2723 
2724  // Modify the condition code of operands in OperandsToUpdate.
2725  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2726  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2727  for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
2728  PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
2729 
2730  for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
2731  SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
2732 
2733  return true;
2734 }
2735 
2738  int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
2739  const TargetRegisterInfo *TRI) const {
2740  const MachineOperand *BaseOp;
2741  OffsetIsScalable = false;
2742  if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI))
2743  return false;
2744  BaseOps.push_back(BaseOp);
2745  return true;
2746 }
2747 
2748 static bool isLdStSafeToCluster(const MachineInstr &LdSt,
2749  const TargetRegisterInfo *TRI) {
2750  // If this is a volatile load/store, don't mess with it.
2751  if (LdSt.hasOrderedMemoryRef() || LdSt.getNumExplicitOperands() != 3)
2752  return false;
2753 
2754  if (LdSt.getOperand(2).isFI())
2755  return true;
2756 
2757  assert(LdSt.getOperand(2).isReg() && "Expected a reg operand.");
2758  // Can't cluster if the instruction modifies the base register
2759  // or it is update form. e.g. ld r2,3(r2)
2760  if (LdSt.modifiesRegister(LdSt.getOperand(2).getReg(), TRI))
2761  return false;
2762 
2763  return true;
2764 }
2765 
2766 // Only cluster instruction pair that have the same opcode, and they are
2767 // clusterable according to PowerPC specification.
2768 static bool isClusterableLdStOpcPair(unsigned FirstOpc, unsigned SecondOpc,
2769  const PPCSubtarget &Subtarget) {
2770  switch (FirstOpc) {
2771  default:
2772  return false;
2773  case PPC::STD:
2774  case PPC::STFD:
2775  case PPC::STXSD:
2776  case PPC::DFSTOREf64:
2777  return FirstOpc == SecondOpc;
2778  // PowerPC backend has opcode STW/STW8 for instruction "stw" to deal with
2779  // 32bit and 64bit instruction selection. They are clusterable pair though
2780  // they are different opcode.
2781  case PPC::STW:
2782  case PPC::STW8:
2783  return SecondOpc == PPC::STW || SecondOpc == PPC::STW8;
2784  }
2785 }
2786 
2789  ArrayRef<const MachineOperand *> BaseOps2, unsigned NumLoads,
2790  unsigned NumBytes) const {
2791 
2792  assert(BaseOps1.size() == 1 && BaseOps2.size() == 1);
2793  const MachineOperand &BaseOp1 = *BaseOps1.front();
2794  const MachineOperand &BaseOp2 = *BaseOps2.front();
2795  assert((BaseOp1.isReg() || BaseOp1.isFI()) &&
2796  "Only base registers and frame indices are supported.");
2797 
2798  // The NumLoads means the number of loads that has been clustered.
2799  // Don't cluster memory op if there are already two ops clustered at least.
2800  if (NumLoads > 2)
2801  return false;
2802 
2803  // Cluster the load/store only when they have the same base
2804  // register or FI.
2805  if ((BaseOp1.isReg() != BaseOp2.isReg()) ||
2806  (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) ||
2807  (BaseOp1.isFI() && BaseOp1.getIndex() != BaseOp2.getIndex()))
2808  return false;
2809 
2810  // Check if the load/store are clusterable according to the PowerPC
2811  // specification.
2812  const MachineInstr &FirstLdSt = *BaseOp1.getParent();
2813  const MachineInstr &SecondLdSt = *BaseOp2.getParent();
2814  unsigned FirstOpc = FirstLdSt.getOpcode();
2815  unsigned SecondOpc = SecondLdSt.getOpcode();
2817  // Cluster the load/store only when they have the same opcode, and they are
2818  // clusterable opcode according to PowerPC specification.
2819  if (!isClusterableLdStOpcPair(FirstOpc, SecondOpc, Subtarget))
2820  return false;
2821 
2822  // Can't cluster load/store that have ordered or volatile memory reference.
2823  if (!isLdStSafeToCluster(FirstLdSt, TRI) ||
2824  !isLdStSafeToCluster(SecondLdSt, TRI))
2825  return false;
2826 
2827  int64_t Offset1 = 0, Offset2 = 0;
2828  unsigned Width1 = 0, Width2 = 0;
2829  const MachineOperand *Base1 = nullptr, *Base2 = nullptr;
2830  if (!getMemOperandWithOffsetWidth(FirstLdSt, Base1, Offset1, Width1, TRI) ||
2831  !getMemOperandWithOffsetWidth(SecondLdSt, Base2, Offset2, Width2, TRI) ||
2832  Width1 != Width2)
2833  return false;
2834 
2835  assert(Base1 == &BaseOp1 && Base2 == &BaseOp2 &&
2836  "getMemOperandWithOffsetWidth return incorrect base op");
2837  // The caller should already have ordered FirstMemOp/SecondMemOp by offset.
2838  assert(Offset1 <= Offset2 && "Caller should have ordered offsets.");
2839  return Offset1 + Width1 == Offset2;
2840 }
2841 
2842 /// GetInstSize - Return the number of bytes of code the specified
2843 /// instruction may be. This returns the maximum number of bytes.
2844 ///
2846  unsigned Opcode = MI.getOpcode();
2847 
2848  if (Opcode == PPC::INLINEASM || Opcode == PPC::INLINEASM_BR) {
2849  const MachineFunction *MF = MI.getParent()->getParent();
2850  const char *AsmStr = MI.getOperand(0).getSymbolName();
2851  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
2852  } else if (Opcode == TargetOpcode::STACKMAP) {
2853  StackMapOpers Opers(&MI);
2854  return Opers.getNumPatchBytes();
2855  } else if (Opcode == TargetOpcode::PATCHPOINT) {
2856  PatchPointOpers Opers(&MI);
2857  return Opers.getNumPatchBytes();
2858  } else {
2859  return get(Opcode).getSize();
2860  }
2861 }
2862 
2863 std::pair<unsigned, unsigned>
2865  const unsigned Mask = PPCII::MO_ACCESS_MASK;
2866  return std::make_pair(TF & Mask, TF & ~Mask);
2867 }
2868 
2871  using namespace PPCII;
2872  static const std::pair<unsigned, const char *> TargetFlags[] = {
2873  {MO_LO, "ppc-lo"},
2874  {MO_HA, "ppc-ha"},
2875  {MO_TPREL_LO, "ppc-tprel-lo"},
2876  {MO_TPREL_HA, "ppc-tprel-ha"},
2877  {MO_DTPREL_LO, "ppc-dtprel-lo"},
2878  {MO_TLSLD_LO, "ppc-tlsld-lo"},
2879  {MO_TOC_LO, "ppc-toc-lo"},
2880  {MO_TLS, "ppc-tls"}};
2881  return makeArrayRef(TargetFlags);
2882 }
2883 
2886  using namespace PPCII;
2887  static const std::pair<unsigned, const char *> TargetFlags[] = {
2888  {MO_PLT, "ppc-plt"},
2889  {MO_PIC_FLAG, "ppc-pic"},
2890  {MO_PCREL_FLAG, "ppc-pcrel"},
2891  {MO_GOT_FLAG, "ppc-got"},
2892  {MO_PCREL_OPT_FLAG, "ppc-opt-pcrel"},
2893  {MO_TLSGD_FLAG, "ppc-tlsgd"},
2894  {MO_TLSLD_FLAG, "ppc-tlsld"},
2895  {MO_TPREL_FLAG, "ppc-tprel"},
2896  {MO_GOT_TLSGD_PCREL_FLAG, "ppc-got-tlsgd-pcrel"},
2897  {MO_GOT_TLSLD_PCREL_FLAG, "ppc-got-tlsld-pcrel"},
2898  {MO_GOT_TPREL_PCREL_FLAG, "ppc-got-tprel-pcrel"}};
2899  return makeArrayRef(TargetFlags);
2900 }
2901 
2902 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
2903 // The VSX versions have the advantage of a full 64-register target whereas
2904 // the FP ones have the advantage of lower latency and higher throughput. So
2905 // what we are after is using the faster instructions in low register pressure
2906 // situations and using the larger register file in high register pressure
2907 // situations.
2909  unsigned UpperOpcode, LowerOpcode;
2910  switch (MI.getOpcode()) {
2911  case PPC::DFLOADf32:
2912  UpperOpcode = PPC::LXSSP;
2913  LowerOpcode = PPC::LFS;
2914  break;
2915  case PPC::DFLOADf64:
2916  UpperOpcode = PPC::LXSD;
2917  LowerOpcode = PPC::LFD;
2918  break;
2919  case PPC::DFSTOREf32:
2920  UpperOpcode = PPC::STXSSP;
2921  LowerOpcode = PPC::STFS;
2922  break;
2923  case PPC::DFSTOREf64:
2924  UpperOpcode = PPC::STXSD;
2925  LowerOpcode = PPC::STFD;
2926  break;
2927  case PPC::XFLOADf32:
2928  UpperOpcode = PPC::LXSSPX;
2929  LowerOpcode = PPC::LFSX;
2930  break;
2931  case PPC::XFLOADf64:
2932  UpperOpcode = PPC::LXSDX;
2933  LowerOpcode = PPC::LFDX;
2934  break;
2935  case PPC::XFSTOREf32:
2936  UpperOpcode = PPC::STXSSPX;
2937  LowerOpcode = PPC::STFSX;
2938  break;
2939  case PPC::XFSTOREf64:
2940  UpperOpcode = PPC::STXSDX;
2941  LowerOpcode = PPC::STFDX;
2942  break;
2943  case PPC::LIWAX:
2944  UpperOpcode = PPC::LXSIWAX;
2945  LowerOpcode = PPC::LFIWAX;
2946  break;
2947  case PPC::LIWZX:
2948  UpperOpcode = PPC::LXSIWZX;
2949  LowerOpcode = PPC::LFIWZX;
2950  break;
2951  case PPC::STIWX:
2952  UpperOpcode = PPC::STXSIWX;
2953  LowerOpcode = PPC::STFIWX;
2954  break;
2955  default:
2956  llvm_unreachable("Unknown Operation!");
2957  }
2958 
2959  Register TargetReg = MI.getOperand(0).getReg();
2960  unsigned Opcode;
2961  if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
2962  (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2963  Opcode = LowerOpcode;
2964  else
2965  Opcode = UpperOpcode;
2966  MI.setDesc(get(Opcode));
2967  return true;
2968 }
2969 
2970 static bool isAnImmediateOperand(const MachineOperand &MO) {
2971  return MO.isCPI() || MO.isGlobal() || MO.isImm();
2972 }
2973 
2975  auto &MBB = *MI.getParent();
2976  auto DL = MI.getDebugLoc();
2977 
2978  switch (MI.getOpcode()) {
2979  case PPC::BUILD_UACC: {
2980  MCRegister ACC = MI.getOperand(0).getReg();
2981  MCRegister UACC = MI.getOperand(1).getReg();
2982  if (ACC - PPC::ACC0 != UACC - PPC::UACC0) {
2983  MCRegister SrcVSR = PPC::VSL0 + (UACC - PPC::UACC0) * 4;
2984  MCRegister DstVSR = PPC::VSL0 + (ACC - PPC::ACC0) * 4;
2985  // FIXME: This can easily be improved to look up to the top of the MBB
2986  // to see if the inputs are XXLOR's. If they are and SrcReg is killed,
2987  // we can just re-target any such XXLOR's to DstVSR + offset.
2988  for (int VecNo = 0; VecNo < 4; VecNo++)
2989  BuildMI(MBB, MI, DL, get(PPC::XXLOR), DstVSR + VecNo)
2990  .addReg(SrcVSR + VecNo)
2991  .addReg(SrcVSR + VecNo);
2992  }
2993  // BUILD_UACC is expanded to 4 copies of the underlying vsx regisers.
2994  // So after building the 4 copies, we can replace the BUILD_UACC instruction
2995  // with a NOP.
2997  }
2998  case PPC::KILL_PAIR: {
2999  MI.setDesc(get(PPC::UNENCODED_NOP));
3000  MI.RemoveOperand(1);
3001  MI.RemoveOperand(0);
3002  return true;
3003  }
3004  case TargetOpcode::LOAD_STACK_GUARD: {
3005  assert(Subtarget.isTargetLinux() &&
3006  "Only Linux target is expected to contain LOAD_STACK_GUARD");
3007  const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
3008  const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
3009  MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
3010  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
3011  .addImm(Offset)
3012  .addReg(Reg);
3013  return true;
3014  }
3015  case PPC::DFLOADf32:
3016  case PPC::DFLOADf64:
3017  case PPC::DFSTOREf32:
3018  case PPC::DFSTOREf64: {
3019  assert(Subtarget.hasP9Vector() &&
3020  "Invalid D-Form Pseudo-ops on Pre-P9 target.");
3021  assert(MI.getOperand(2).isReg() &&
3022  isAnImmediateOperand(MI.getOperand(1)) &&
3023  "D-form op must have register and immediate operands");
3024  return expandVSXMemPseudo(MI);
3025  }
3026  case PPC::XFLOADf32:
3027  case PPC::XFSTOREf32:
3028  case PPC::LIWAX:
3029  case PPC::LIWZX:
3030  case PPC::STIWX: {
3031  assert(Subtarget.hasP8Vector() &&
3032  "Invalid X-Form Pseudo-ops on Pre-P8 target.");
3033  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
3034  "X-form op must have register and register operands");
3035  return expandVSXMemPseudo(MI);
3036  }
3037  case PPC::XFLOADf64:
3038  case PPC::XFSTOREf64: {
3039  assert(Subtarget.hasVSX() &&
3040  "Invalid X-Form Pseudo-ops on target that has no VSX.");
3041  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
3042  "X-form op must have register and register operands");
3043  return expandVSXMemPseudo(MI);
3044  }
3045  case PPC::SPILLTOVSR_LD: {
3046  Register TargetReg = MI.getOperand(0).getReg();
3047  if (PPC::VSFRCRegClass.contains(TargetReg)) {
3048  MI.setDesc(get(PPC::DFLOADf64));
3049  return expandPostRAPseudo(MI);
3050  }
3051  else
3052  MI.setDesc(get(PPC::LD));
3053  return true;
3054  }
3055  case PPC::SPILLTOVSR_ST: {
3056  Register SrcReg = MI.getOperand(0).getReg();
3057  if (PPC::VSFRCRegClass.contains(SrcReg)) {
3058  NumStoreSPILLVSRRCAsVec++;
3059  MI.setDesc(get(PPC::DFSTOREf64));
3060  return expandPostRAPseudo(MI);
3061  } else {
3062  NumStoreSPILLVSRRCAsGpr++;
3063  MI.setDesc(get(PPC::STD));
3064  }
3065  return true;
3066  }
3067  case PPC::SPILLTOVSR_LDX: {
3068  Register TargetReg = MI.getOperand(0).getReg();
3069  if (PPC::VSFRCRegClass.contains(TargetReg))
3070  MI.setDesc(get(PPC::LXSDX));
3071  else
3072  MI.setDesc(get(PPC::LDX));
3073  return true;
3074  }
3075  case PPC::SPILLTOVSR_STX: {
3076  Register SrcReg = MI.getOperand(0).getReg();
3077  if (PPC::VSFRCRegClass.contains(SrcReg)) {
3078  NumStoreSPILLVSRRCAsVec++;
3079  MI.setDesc(get(PPC::STXSDX));
3080  } else {
3081  NumStoreSPILLVSRRCAsGpr++;
3082  MI.setDesc(get(PPC::STDX));
3083  }
3084  return true;
3085  }
3086 
3087  case PPC::CFENCE8: {
3088  auto Val = MI.getOperand(0).getReg();
3089  BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
3090  BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
3092  .addReg(PPC::CR7)
3093  .addImm(1);
3094  MI.setDesc(get(PPC::ISYNC));
3095  MI.RemoveOperand(0);
3096  return true;
3097  }
3098  }
3099  return false;
3100 }
3101 
3102 // Essentially a compile-time implementation of a compare->isel sequence.
3103 // It takes two constants to compare, along with the true/false registers
3104 // and the comparison type (as a subreg to a CR field) and returns one
3105 // of the true/false registers, depending on the comparison results.
3106 static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc,
3107  unsigned TrueReg, unsigned FalseReg,
3108  unsigned CRSubReg) {
3109  // Signed comparisons. The immediates are assumed to be sign-extended.
3110  if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
3111  switch (CRSubReg) {
3112  default: llvm_unreachable("Unknown integer comparison type.");
3113  case PPC::sub_lt:
3114  return Imm1 < Imm2 ? TrueReg : FalseReg;
3115  case PPC::sub_gt:
3116  return Imm1 > Imm2 ? TrueReg : FalseReg;
3117  case PPC::sub_eq:
3118  return Imm1 == Imm2 ? TrueReg : FalseReg;
3119  }
3120  }
3121  // Unsigned comparisons.
3122  else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
3123  switch (CRSubReg) {
3124  default: llvm_unreachable("Unknown integer comparison type.");
3125  case PPC::sub_lt:
3126  return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;
3127  case PPC::sub_gt:
3128  return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;
3129  case PPC::sub_eq:
3130  return Imm1 == Imm2 ? TrueReg : FalseReg;
3131  }
3132  }
3133  return PPC::NoRegister;
3134 }
3135 
3137  unsigned OpNo,
3138  int64_t Imm) const {
3139  assert(MI.getOperand(OpNo).isReg() && "Operand must be a REG");
3140  // Replace the REG with the Immediate.
3141  Register InUseReg = MI.getOperand(OpNo).getReg();
3142  MI.getOperand(OpNo).ChangeToImmediate(Imm);
3143 
3144  if (MI.implicit_operands().empty())
3145  return;
3146 
3147  // We need to make sure that the MI didn't have any implicit use
3148  // of this REG any more.
3150  int UseOpIdx = MI.findRegisterUseOperandIdx(InUseReg, false, TRI);
3151  if (UseOpIdx >= 0) {
3152  MachineOperand &MO = MI.getOperand(UseOpIdx);
3153  if (MO.isImplicit())
3154  // The operands must always be in the following order:
3155  // - explicit reg defs,
3156  // - other explicit operands (reg uses, immediates, etc.),
3157  // - implicit reg defs
3158  // - implicit reg uses
3159  // Therefore, removing the implicit operand won't change the explicit
3160  // operands layout.
3161  MI.RemoveOperand(UseOpIdx);
3162  }
3163 }
3164 
3165 // Replace an instruction with one that materializes a constant (and sets
3166 // CR0 if the original instruction was a record-form instruction).
3168  const LoadImmediateInfo &LII) const {
3169  // Remove existing operands.
3170  int OperandToKeep = LII.SetCR ? 1 : 0;
3171  for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
3172  MI.RemoveOperand(i);
3173 
3174  // Replace the instruction.
3175  if (LII.SetCR) {
3176  MI.setDesc(get(LII.Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec));
3177  // Set the immediate.
3178  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
3179  .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
3180  return;
3181  }
3182  else
3183  MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
3184 
3185  // Set the immediate.
3186  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
3187  .addImm(LII.Imm);
3188 }
3189 
3191  bool &SeenIntermediateUse) const {
3192  assert(!MI.getParent()->getParent()->getRegInfo().isSSA() &&
3193  "Should be called after register allocation.");
3195  MachineBasicBlock::reverse_iterator E = MI.getParent()->rend(), It = MI;
3196  It++;
3197  SeenIntermediateUse = false;
3198  for (; It != E; ++It) {
3199  if (It->modifiesRegister(Reg, TRI))
3200  return &*It;
3201  if (It->readsRegister(Reg, TRI))
3202  SeenIntermediateUse = true;
3203  }
3204  return nullptr;
3205 }
3206 
3207 MachineInstr *PPCInstrInfo::getForwardingDefMI(
3208  MachineInstr &MI,
3209  unsigned &OpNoForForwarding,
3210  bool &SeenIntermediateUse) const {
3211  OpNoForForwarding = ~0U;
3212  MachineInstr *DefMI = nullptr;
3213  MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
3215  // If we're in SSA, get the defs through the MRI. Otherwise, only look
3216  // within the basic block to see if the register is defined using an
3217  // LI/LI8/ADDI/ADDI8.
3218  if (MRI->isSSA()) {
3219  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
3220  if (!MI.getOperand(i).isReg())
3221  continue;
3222  Register Reg = MI.getOperand(i).getReg();
3224  continue;
3225  unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI);
3226  if (Register::isVirtualRegister(TrueReg)) {
3227  DefMI = MRI->getVRegDef(TrueReg);
3228  if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8 ||
3229  DefMI->getOpcode() == PPC::ADDI ||
3230  DefMI->getOpcode() == PPC::ADDI8) {
3231  OpNoForForwarding = i;
3232  // The ADDI and LI operand maybe exist in one instruction at same
3233  // time. we prefer to fold LI operand as LI only has one Imm operand
3234  // and is more possible to be converted. So if current DefMI is
3235  // ADDI/ADDI8, we continue to find possible LI/LI8.
3236  if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8)
3237  break;
3238  }
3239  }
3240  }
3241  } else {
3242  // Looking back through the definition for each operand could be expensive,
3243  // so exit early if this isn't an instruction that either has an immediate
3244  // form or is already an immediate form that we can handle.
3245  ImmInstrInfo III;
3246  unsigned Opc = MI.getOpcode();
3247  bool ConvertibleImmForm =
3248  Opc == PPC::CMPWI || Opc == PPC::CMPLWI || Opc == PPC::CMPDI ||
3249  Opc == PPC::CMPLDI || Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
3250  Opc == PPC::ORI || Opc == PPC::ORI8 || Opc == PPC::XORI ||
3251  Opc == PPC::XORI8 || Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec ||
3252  Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
3253  Opc == PPC::RLWINM || Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8 ||
3254  Opc == PPC::RLWINM8_rec;
3255  bool IsVFReg = (MI.getNumOperands() && MI.getOperand(0).isReg())
3256  ? isVFRegister(MI.getOperand(0).getReg())
3257  : false;
3258  if (!ConvertibleImmForm && !instrHasImmForm(Opc, IsVFReg, III, true))
3259  return nullptr;
3260 
3261  // Don't convert or %X, %Y, %Y since that's just a register move.
3262  if ((Opc == PPC::OR || Opc == PPC::OR8) &&
3263  MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
3264  return nullptr;
3265  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
3266  MachineOperand &MO = MI.getOperand(i);
3267  SeenIntermediateUse = false;
3268  if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
3269  Register Reg = MI.getOperand(i).getReg();
3270  // If we see another use of this reg between the def and the MI,
3271  // we want to flat it so the def isn't deleted.
3272  MachineInstr *DefMI = getDefMIPostRA(Reg, MI, SeenIntermediateUse);
3273  if (DefMI) {
3274  // Is this register defined by some form of add-immediate (including
3275  // load-immediate) within this basic block?
3276  switch (DefMI->getOpcode()) {
3277  default:
3278  break;
3279  case PPC::LI:
3280  case PPC::LI8:
3281  case PPC::ADDItocL:
3282  case PPC::ADDI:
3283  case PPC::ADDI8:
3284  OpNoForForwarding = i;
3285  return DefMI;
3286  }
3287  }
3288  }
3289  }
3290  }
3291  return OpNoForForwarding == ~0U ? nullptr : DefMI;
3292 }
3293 
3294 unsigned PPCInstrInfo::getSpillTarget() const {
3295  // With P10, we may need to spill paired vector registers or accumulator
3296  // registers. MMA implies paired vectors, so we can just check that.
3297  bool IsP10Variant = Subtarget.isISA3_1() || Subtarget.pairedVectorMemops();
3298  return IsP10Variant ? 2 : Subtarget.hasP9Vector() ? 1 : 0;
3299 }
3300 
3301 const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
3302  return StoreSpillOpcodesArray[getSpillTarget()];
3303 }
3304 
3305 const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
3306  return LoadSpillOpcodesArray[getSpillTarget()];
3307 }
3308 
3310  unsigned RegNo) const {
3311  // Conservatively clear kill flag for the register if the instructions are in
3312  // different basic blocks and in SSA form, because the kill flag may no longer
3313  // be right. There is no need to bother with dead flags since defs with no
3314  // uses will be handled by DCE.
3316  if (MRI.isSSA() && (StartMI->getParent() != EndMI->getParent())) {
3317  MRI.clearKillFlags(RegNo);
3318  return;
3319  }
3320 
3321  // Instructions between [StartMI, EndMI] should be in same basic block.
3322  assert((StartMI->getParent() == EndMI->getParent()) &&
3323  "Instructions are not in same basic block");
3324 
3325  // If before RA, StartMI may be def through COPY, we need to adjust it to the
3326  // real def. See function getForwardingDefMI.
3327  if (MRI.isSSA()) {
3328  bool Reads, Writes;
3329  std::tie(Reads, Writes) = StartMI->readsWritesVirtualRegister(RegNo);
3330  if (!Reads && !Writes) {
3332  "Must be a virtual register");
3333  // Get real def and ignore copies.
3334  StartMI = MRI.getVRegDef(RegNo);
3335  }
3336  }
3337 
3338  bool IsKillSet = false;
3339 
3340  auto clearOperandKillInfo = [=] (MachineInstr &MI, unsigned Index) {
3341  MachineOperand &MO = MI.getOperand(Index);
3342  if (MO.isReg() && MO.isUse() && MO.isKill() &&
3343  getRegisterInfo().regsOverlap(MO.getReg(), RegNo))
3344  MO.setIsKill(false);
3345  };
3346 
3347  // Set killed flag for EndMI.
3348  // No need to do anything if EndMI defines RegNo.
3349  int UseIndex =
3350  EndMI->findRegisterUseOperandIdx(RegNo, false, &getRegisterInfo());
3351  if (UseIndex != -1) {
3352  EndMI->getOperand(UseIndex).setIsKill(true);
3353  IsKillSet = true;
3354  // Clear killed flag for other EndMI operands related to RegNo. In some
3355  // upexpected cases, killed may be set multiple times for same register
3356  // operand in same MI.
3357  for (int i = 0, e = EndMI->getNumOperands(); i != e; ++i)
3358  if (i != UseIndex)
3359  clearOperandKillInfo(*EndMI, i);
3360  }
3361 
3362  // Walking the inst in reverse order (EndMI -> StartMI].
3365  // EndMI has been handled above, skip it here.
3366  It++;
3367  MachineOperand *MO = nullptr;
3368  for (; It != E; ++It) {
3369  // Skip insturctions which could not be a def/use of RegNo.
3370  if (It->isDebugInstr() || It->isPosition())
3371  continue;
3372 
3373  // Clear killed flag for all It operands related to RegNo. In some
3374  // upexpected cases, killed may be set multiple times for same register
3375  // operand in same MI.
3376  for (int i = 0, e = It->getNumOperands(); i != e; ++i)
3377  clearOperandKillInfo(*It, i);
3378 
3379  // If killed is not set, set killed for its last use or set dead for its def
3380  // if no use found.
3381  if (!IsKillSet) {
3382  if ((MO = It->findRegisterUseOperand(RegNo, false, &getRegisterInfo()))) {
3383  // Use found, set it killed.
3384  IsKillSet = true;
3385  MO->setIsKill(true);
3386  continue;
3387  } else if ((MO = It->findRegisterDefOperand(RegNo, false, true,
3388  &getRegisterInfo()))) {
3389  // No use found, set dead for its def.
3390  assert(&*It == StartMI && "No new def between StartMI and EndMI.");
3391  MO->setIsDead(true);
3392  break;
3393  }
3394  }
3395 
3396  if ((&*It) == StartMI)
3397  break;
3398  }
3399  // Ensure RegMo liveness is killed after EndMI.
3400  assert((IsKillSet || (MO && MO->isDead())) &&
3401  "RegNo should be killed or dead");
3402 }
3403 
3404 // This opt tries to convert the following imm form to an index form to save an
3405 // add for stack variables.
3406 // Return false if no such pattern found.
3407 //
3408 // ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, OffsetAddi
3409 // ADD instr: ToBeDeletedReg = ADD ToBeChangedReg(killed), ScaleReg
3410 // Imm instr: Reg = op OffsetImm, ToBeDeletedReg(killed)
3411 //
3412 // can be converted to:
3413 //
3414 // new ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, (OffsetAddi + OffsetImm)
3415 // Index instr: Reg = opx ScaleReg, ToBeChangedReg(killed)
3416 //
3417 // In order to eliminate ADD instr, make sure that:
3418 // 1: (OffsetAddi + OffsetImm) must be int16 since this offset will be used in
3419 // new ADDI instr and ADDI can only take int16 Imm.
3420 // 2: ToBeChangedReg must be killed in ADD instr and there is no other use
3421 // between ADDI and ADD instr since its original def in ADDI will be changed
3422 // in new ADDI instr. And also there should be no new def for it between
3423 // ADD and Imm instr as ToBeChangedReg will be used in Index instr.
3424 // 3: ToBeDeletedReg must be killed in Imm instr and there is no other use
3425 // between ADD and Imm instr since ADD instr will be eliminated.
3426 // 4: ScaleReg must not be redefined between ADD and Imm instr since it will be
3427 // moved to Index instr.
3429  MachineFunction *MF = MI.getParent()->getParent();
3431  bool PostRA = !MRI->isSSA();
3432  // Do this opt after PEI which is after RA. The reason is stack slot expansion
3433  // in PEI may expose such opportunities since in PEI, stack slot offsets to
3434  // frame base(OffsetAddi) are determined.
3435  if (!PostRA)
3436  return false;
3437  unsigned ToBeDeletedReg = 0;
3438  int64_t OffsetImm = 0;
3439  unsigned XFormOpcode = 0;
3440  ImmInstrInfo III;
3441 
3442  // Check if Imm instr meets requirement.
3443  if (!isImmInstrEligibleForFolding(MI, ToBeDeletedReg, XFormOpcode, OffsetImm,
3444  III))
3445  return false;
3446 
3447  bool OtherIntermediateUse = false;
3448  MachineInstr *ADDMI = getDefMIPostRA(ToBeDeletedReg, MI, OtherIntermediateUse);
3449 
3450  // Exit if there is other use between ADD and Imm instr or no def found.
3451  if (OtherIntermediateUse || !ADDMI)
3452  return false;
3453 
3454  // Check if ADD instr meets requirement.
3455  if (!isADDInstrEligibleForFolding(*ADDMI))
3456  return false;
3457 
3458  unsigned ScaleRegIdx = 0;
3459  int64_t OffsetAddi = 0;
3460  MachineInstr *ADDIMI = nullptr;
3461 
3462  // Check if there is a valid ToBeChangedReg in ADDMI.
3463  // 1: It must be killed.
3464  // 2: Its definition must be a valid ADDIMI.
3465  // 3: It must satify int16 offset requirement.
3466  if (isValidToBeChangedReg(ADDMI, 1, ADDIMI, OffsetAddi, OffsetImm))
3467  ScaleRegIdx = 2;
3468  else if (isValidToBeChangedReg(ADDMI, 2, ADDIMI, OffsetAddi, OffsetImm))
3469  ScaleRegIdx = 1;
3470  else
3471  return false;
3472 
3473  assert(ADDIMI && "There should be ADDIMI for valid ToBeChangedReg.");
3474  unsigned ToBeChangedReg = ADDIMI->getOperand(0).getReg();
3475  unsigned ScaleReg = ADDMI->getOperand(ScaleRegIdx).getReg();
3476  auto NewDefFor = [&](unsigned Reg, MachineBasicBlock::iterator Start,
3478  for (auto It = ++Start; It != End; It++)
3479  if (It->modifiesRegister(Reg, &getRegisterInfo()))
3480  return true;
3481  return false;
3482  };
3483 
3484  // We are trying to replace the ImmOpNo with ScaleReg. Give up if it is
3485  // treated as special zero when ScaleReg is R0/X0 register.
3486  if (III.ZeroIsSpecialOrig == III.ImmOpNo &&
3487  (ScaleReg == PPC::R0 || ScaleReg == PPC::X0))
3488  return false;
3489 
3490  // Make sure no other def for ToBeChangedReg and ScaleReg between ADD Instr
3491  // and Imm Instr.
3492  if (NewDefFor(ToBeChangedReg, *ADDMI, MI) || NewDefFor(ScaleReg, *ADDMI, MI))
3493  return false;
3494 
3495  // Now start to do the transformation.
3496  LLVM_DEBUG(dbgs() << "Replace instruction: "
3497  << "\n");
3498  LLVM_DEBUG(ADDIMI->dump());
3499  LLVM_DEBUG(ADDMI->dump());
3500  LLVM_DEBUG(MI.dump());
3501  LLVM_DEBUG(dbgs() << "with: "
3502  << "\n");
3503 
3504  // Update ADDI instr.
3505  ADDIMI->getOperand(2).setImm(OffsetAddi + OffsetImm);
3506 
3507  // Update Imm instr.
3508  MI.setDesc(get(XFormOpcode));
3509  MI.getOperand(III.ImmOpNo)
3510  .ChangeToRegister(ScaleReg, false, false,
3511  ADDMI->getOperand(ScaleRegIdx).isKill());
3512 
3513  MI.getOperand(III.OpNoForForwarding)
3514  .ChangeToRegister(ToBeChangedReg, false, false, true);
3515 
3516  // Eliminate ADD instr.
3517  ADDMI->eraseFromParent();
3518 
3519  LLVM_DEBUG(ADDIMI->dump());
3520  LLVM_DEBUG(MI.dump());
3521 
3522  return true;
3523 }
3524 
3526  int64_t &Imm) const {
3527  unsigned Opc = ADDIMI.getOpcode();
3528 
3529  // Exit if the instruction is not ADDI.
3530  if (Opc != PPC::ADDI && Opc != PPC::ADDI8)
3531  return false;
3532 
3533  // The operand may not necessarily be an immediate - it could be a relocation.
3534  if (!ADDIMI.getOperand(2).isImm())
3535  return false;
3536 
3537  Imm = ADDIMI.getOperand(2).getImm();
3538 
3539  return true;
3540 }
3541 
3543  unsigned Opc = ADDMI.getOpcode();
3544 
3545  // Exit if the instruction is not ADD.
3546  return Opc == PPC::ADD4 || Opc == PPC::ADD8;
3547 }
3548 
3550  unsigned &ToBeDeletedReg,
3551  unsigned &XFormOpcode,
3552  int64_t &OffsetImm,
3553  ImmInstrInfo &III) const {
3554  // Only handle load/store.
3555  if (!MI.mayLoadOrStore())
3556  return false;
3557 
3558  unsigned Opc = MI.getOpcode();
3559 
3560  XFormOpcode = RI.getMappedIdxOpcForImmOpc(Opc);
3561 
3562  // Exit if instruction has no index form.
3563  if (XFormOpcode == PPC::INSTRUCTION_LIST_END)
3564  return false;
3565 
3566  // TODO: sync the logic between instrHasImmForm() and ImmToIdxMap.
3567  if (!instrHasImmForm(XFormOpcode, isVFRegister(MI.getOperand(0).getReg()),
3568  III, true))
3569  return false;
3570 
3571  if (!III.IsSummingOperands)
3572  return false;
3573 
3574  MachineOperand ImmOperand = MI.getOperand(III.ImmOpNo);
3575  MachineOperand RegOperand = MI.getOperand(III.OpNoForForwarding);
3576  // Only support imm operands, not relocation slots or others.
3577  if (!ImmOperand.isImm())
3578  return false;
3579 
3580  assert(RegOperand.isReg() && "Instruction format is not right");
3581 
3582  // There are other use for ToBeDeletedReg after Imm instr, can not delete it.
3583  if (!RegOperand.isKill())
3584  return false;
3585 
3586  ToBeDeletedReg = RegOperand.getReg();
3587  OffsetImm = ImmOperand.getImm();
3588 
3589  return true;
3590 }
3591 
3593  MachineInstr *&ADDIMI,
3594  int64_t &OffsetAddi,
3595  int64_t OffsetImm) const {
3596  assert((Index == 1 || Index == 2) && "Invalid operand index for add.");
3597  MachineOperand &MO = ADDMI->getOperand(Index);
3598 
3599  if (!MO.isKill())
3600  return false;
3601 
3602  bool OtherIntermediateUse = false;
3603 
3604  ADDIMI = getDefMIPostRA(MO.getReg(), *ADDMI, OtherIntermediateUse);
3605  // Currently handle only one "add + Imminstr" pair case, exit if other
3606  // intermediate use for ToBeChangedReg found.
3607  // TODO: handle the cases where there are other "add + Imminstr" pairs
3608  // with same offset in Imminstr which is like:
3609  //
3610  // ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, OffsetAddi
3611  // ADD instr1: ToBeDeletedReg1 = ADD ToBeChangedReg, ScaleReg1
3612  // Imm instr1: Reg1 = op1 OffsetImm, ToBeDeletedReg1(killed)
3613  // ADD instr2: ToBeDeletedReg2 = ADD ToBeChangedReg(killed), ScaleReg2
3614  // Imm instr2: Reg2 = op2 OffsetImm, ToBeDeletedReg2(killed)
3615  //
3616  // can be converted to:
3617  //
3618  // new ADDI instr: ToBeChangedReg = ADDI FrameBaseReg,
3619  // (OffsetAddi + OffsetImm)
3620  // Index instr1: Reg1 = opx1 ScaleReg1, ToBeChangedReg
3621  // Index instr2: Reg2 = opx2 ScaleReg2, ToBeChangedReg(killed)
3622 
3623  if (OtherIntermediateUse || !ADDIMI)
3624  return false;
3625  // Check if ADDI instr meets requirement.
3626  if (!isADDIInstrEligibleForFolding(*ADDIMI, OffsetAddi))
3627  return false;
3628 
3629  if (isInt<16>(OffsetAddi + OffsetImm))
3630  return true;
3631  return false;
3632 }
3633 
3634 // If this instruction has an immediate form and one of its operands is a
3635 // result of a load-immediate or an add-immediate, convert it to
3636 // the immediate form if the constant is in range.
3638  MachineInstr **KilledDef) const {
3639  MachineFunction *MF = MI.getParent()->getParent();
3641  bool PostRA = !MRI->isSSA();
3642  bool SeenIntermediateUse = true;
3643  unsigned ForwardingOperand = ~0U;
3644  MachineInstr *DefMI = getForwardingDefMI(MI, ForwardingOperand,
3645  SeenIntermediateUse);
3646  if (!DefMI)
3647  return false;
3648  assert(ForwardingOperand < MI.getNumOperands() &&
3649  "The forwarding operand needs to be valid at this point");
3650  bool IsForwardingOperandKilled = MI.getOperand(ForwardingOperand).isKill();
3651  bool KillFwdDefMI = !SeenIntermediateUse && IsForwardingOperandKilled;
3652  if (KilledDef && KillFwdDefMI)
3653  *KilledDef = DefMI;
3654 
3655  // If this is a imm instruction and its register operands is produced by ADDI,
3656  // put the imm into imm inst directly.
3657  if (RI.getMappedIdxOpcForImmOpc(MI.getOpcode()) !=
3658  PPC::INSTRUCTION_LIST_END &&
3659  transformToNewImmFormFedByAdd(MI, *DefMI, ForwardingOperand))
3660  return true;
3661 
3662  ImmInstrInfo III;
3663  bool IsVFReg = MI.getOperand(0).isReg()
3664  ? isVFRegister(MI.getOperand(0).getReg())
3665  : false;
3666  bool HasImmForm = instrHasImmForm(MI.getOpcode(), IsVFReg, III, PostRA);
3667  // If this is a reg+reg instruction that has a reg+imm form,
3668  // and one of the operands is produced by an add-immediate,
3669  // try to convert it.
3670  if (HasImmForm &&
3671  transformToImmFormFedByAdd(MI, III, ForwardingOperand, *DefMI,
3672  KillFwdDefMI))
3673  return true;
3674 
3675  // If this is a reg+reg instruction that has a reg+imm form,
3676  // and one of the operands is produced by LI, convert it now.
3677  if (HasImmForm &&
3678  transformToImmFormFedByLI(MI, III, ForwardingOperand, *DefMI))
3679  return true;
3680 
3681  // If this is not a reg+reg, but the DefMI is LI/LI8, check if its user MI
3682  // can be simpified to LI.
3683  if (!HasImmForm && simplifyToLI(MI, *DefMI, ForwardingOperand, KilledDef))
3684  return true;
3685 
3686  return false;
3687 }
3688 
3690  MachineInstr **ToErase) const {
3691  MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
3692  unsigned FoldingReg = MI.getOperand(1).getReg();
3693  if (!Register::isVirtualRegister(FoldingReg))
3694  return false;
3695  MachineInstr *SrcMI = MRI->getVRegDef(FoldingReg);
3696  if (SrcMI->getOpcode() != PPC::RLWINM &&
3697  SrcMI->getOpcode() != PPC::RLWINM_rec &&
3698  SrcMI->getOpcode() != PPC::RLWINM8 &&
3699  SrcMI->getOpcode() != PPC::RLWINM8_rec)
3700  return false;
3701  assert((MI.getOperand(2).isImm() && MI.getOperand(3).isImm() &&
3702  MI.getOperand(4).isImm() && SrcMI->getOperand(2).isImm() &&
3703  SrcMI->getOperand(3).isImm() && SrcMI->getOperand(4).isImm()) &&
3704  "Invalid PPC::RLWINM Instruction!");
3705  uint64_t SHSrc = SrcMI->getOperand(2).getImm();
3706  uint64_t SHMI = MI.getOperand(2).getImm();
3707  uint64_t MBSrc = SrcMI->getOperand(3).getImm();
3708  uint64_t MBMI = MI.getOperand(3).getImm();
3709  uint64_t MESrc = SrcMI->getOperand(4).getImm();
3710  uint64_t MEMI = MI.getOperand(4).getImm();
3711 
3712  assert((MEMI < 32 && MESrc < 32 && MBMI < 32 && MBSrc < 32) &&
3713  "Invalid PPC::RLWINM Instruction!");
3714  // If MBMI is bigger than MEMI, we always can not get run of ones.
3715  // RotatedSrcMask non-wrap:
3716  // 0........31|32........63
3717  // RotatedSrcMask: B---E B---E
3718  // MaskMI: -----------|--E B------
3719  // Result: ----- --- (Bad candidate)
3720  //
3721  // RotatedSrcMask wrap:
3722  // 0........31|32........63
3723  // RotatedSrcMask: --E B----|--E B----
3724  // MaskMI: -----------|--E B------
3725  // Result: --- -----|--- ----- (Bad candidate)
3726  //
3727  // One special case is RotatedSrcMask is a full set mask.
3728  // RotatedSrcMask full:
3729  // 0........31|32........63
3730  // RotatedSrcMask: ------EB---|-------EB---
3731  // MaskMI: -----------|--E B------
3732  // Result: -----------|--- ------- (Good candidate)
3733 
3734  // Mark special case.
3735  bool SrcMaskFull = (MBSrc - MESrc == 1) || (MBSrc == 0 && MESrc == 31);
3736 
3737  // For other MBMI > MEMI cases, just return.
3738  if ((MBMI > MEMI) && !SrcMaskFull)
3739  return false;
3740 
3741  // Handle MBMI <= MEMI cases.
3742  APInt MaskMI = APInt::getBitsSetWithWrap(32, 32 - MEMI - 1, 32 - MBMI);
3743  // In MI, we only need low 32 bits of SrcMI, just consider about low 32
3744  // bit of SrcMI mask. Note that in APInt, lowerest bit is at index 0,
3745  // while in PowerPC ISA, lowerest bit is at index 63.
3746  APInt MaskSrc = APInt::getBitsSetWithWrap(32, 32 - MESrc - 1, 32 - MBSrc);
3747 
3748  APInt RotatedSrcMask = MaskSrc.rotl(SHMI);
3749  APInt FinalMask = RotatedSrcMask & MaskMI;
3750  uint32_t NewMB, NewME;
3751  bool Simplified = false;
3752 
3753  // If final mask is 0, MI result should be 0 too.
3754  if (FinalMask.isNullValue()) {
3755  bool Is64Bit =
3756  (MI.getOpcode() == PPC::RLWINM8 || MI.getOpcode() == PPC::RLWINM8_rec);
3757  Simplified = true;
3758  LLVM_DEBUG(dbgs() << "Replace Instr: ");
3759  LLVM_DEBUG(MI.dump());
3760 
3761  if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM8) {
3762  // Replace MI with "LI 0"
3763  MI.RemoveOperand(4);
3764  MI.RemoveOperand(3);
3765  MI.RemoveOperand(2);
3766  MI.getOperand(1).ChangeToImmediate(0);
3767  MI.setDesc(get(Is64Bit ? PPC::LI8 : PPC::LI));
3768  } else {
3769  // Replace MI with "ANDI_rec reg, 0"
3770  MI.RemoveOperand(4);
3771  MI.RemoveOperand(3);
3772  MI.getOperand(2).setImm(0);
3773  MI.setDesc(get(Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec));
3774  MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
3775  if (SrcMI->getOperand(1).isKill()) {
3776  MI.getOperand(1).setIsKill(true);
3777  SrcMI->getOperand(1).setIsKill(false);
3778  } else
3779  // About to replace MI.getOperand(1), clear its kill flag.
3780  MI.getOperand(1).setIsKill(false);
3781  }
3782 
3783  LLVM_DEBUG(dbgs() << "With: ");
3784  LLVM_DEBUG(MI.dump());
3785 
3786  } else if ((isRunOfOnes((unsigned)(FinalMask.getZExtValue()), NewMB, NewME) &&
3787  NewMB <= NewME) ||
3788  SrcMaskFull) {
3789  // Here we only handle MBMI <= MEMI case, so NewMB must be no bigger
3790  // than NewME. Otherwise we get a 64 bit value after folding, but MI
3791  // return a 32 bit value.
3792  Simplified = true;
3793  LLVM_DEBUG(dbgs() << "Converting Instr: ");
3794  LLVM_DEBUG(MI.dump());
3795 
3796  uint16_t NewSH = (SHSrc + SHMI) % 32;
3797  MI.getOperand(2).setImm(NewSH);
3798  // If SrcMI mask is full, no need to update MBMI and MEMI.
3799  if (!SrcMaskFull) {
3800  MI.getOperand(3).setImm(NewMB);
3801  MI.getOperand(4).setImm(NewME);
3802  }
3803  MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
3804  if (SrcMI->getOperand(1).isKill()) {
3805  MI.getOperand(1).setIsKill(true);
3806  SrcMI->getOperand(1).setIsKill(false);
3807  } else
3808  // About to replace MI.getOperand(1), clear its kill flag.
3809  MI.getOperand(1).setIsKill(false);
3810 
3811  LLVM_DEBUG(dbgs() << "To: ");
3812  LLVM_DEBUG(MI.dump());
3813  }
3814  if (Simplified & MRI->use_nodbg_empty(FoldingReg) &&
3815  !SrcMI->hasImplicitDef()) {
3816  // If FoldingReg has no non-debug use and it has no implicit def (it
3817  // is not RLWINMO or RLWINM8o), it's safe to delete its def SrcMI.
3818  // Otherwise keep it.
3819  *ToErase = SrcMI;
3820  LLVM_DEBUG(dbgs() << "Delete dead instruction: ");
3821  LLVM_DEBUG(SrcMI->dump());
3822  }
3823  return Simplified;
3824 }
3825 
3826 bool PPCInstrInfo::instrHasImmForm(unsigned Opc, bool IsVFReg,
3827  ImmInstrInfo &III, bool PostRA) const {
3828  // The vast majority of the instructions would need their operand 2 replaced
3829  // with an immediate when switching to the reg+imm form. A marked exception
3830  // are the update form loads/stores for which a constant operand 2 would need
3831  // to turn into a displacement and move operand 1 to the operand 2 position.
3832  III.ImmOpNo = 2;
3833  III.OpNoForForwarding = 2;
3834  III.ImmWidth = 16;
3835  III.ImmMustBeMultipleOf = 1;
3836  III.TruncateImmTo = 0;
3837  III.IsSummingOperands = false;
3838  switch (Opc) {
3839  default: return false;
3840  case PPC::ADD4:
3841  case PPC::ADD8:
3842  III.SignedImm = true;
3843  III.ZeroIsSpecialOrig = 0;
3844  III.ZeroIsSpecialNew = 1;
3845  III.IsCommutative = true;
3846  III.IsSummingOperands = true;
3847  III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
3848  break;
3849  case PPC::ADDC:
3850  case PPC::ADDC8:
3851  III.SignedImm = true;
3852  III.ZeroIsSpecialOrig = 0;
3853  III.ZeroIsSpecialNew = 0;
3854  III.IsCommutative = true;
3855  III.IsSummingOperands = true;
3856  III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
3857  break;
3858  case PPC::ADDC_rec:
3859  III.SignedImm = true;
3860  III.ZeroIsSpecialOrig = 0;
3861  III.ZeroIsSpecialNew = 0;
3862  III.IsCommutative = true;
3863  III.IsSummingOperands = true;
3864  III.ImmOpcode = PPC::ADDIC_rec;
3865  break;
3866  case PPC::SUBFC:
3867  case PPC::SUBFC8:
3868  III.SignedImm = true;
3869  III.ZeroIsSpecialOrig = 0;
3870  III.ZeroIsSpecialNew = 0;
3871  III.IsCommutative = false;
3872  III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
3873  break;
3874  case PPC::CMPW:
3875  case PPC::CMPD:
3876  III.SignedImm = true;
3877  III.ZeroIsSpecialOrig = 0;
3878  III.ZeroIsSpecialNew = 0;
3879  III.IsCommutative = false;
3880  III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
3881  break;
3882  case PPC::CMPLW:
3883  case PPC::CMPLD:
3884  III.SignedImm = false;
3885  III.ZeroIsSpecialOrig = 0;
3886  III.ZeroIsSpecialNew = 0;
3887  III.IsCommutative = false;
3888  III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
3889  break;
3890  case PPC::AND_rec:
3891  case PPC::AND8_rec:
3892  case PPC::OR:
3893  case PPC::OR8:
3894  case PPC::XOR:
3895  case PPC::XOR8:
3896  III.SignedImm = false;
3897  III.ZeroIsSpecialOrig = 0;
3898  III.ZeroIsSpecialNew = 0;
3899  III.IsCommutative = true;
3900  switch(Opc) {
3901  default: llvm_unreachable("Unknown opcode");
3902  case PPC::AND_rec:
3903  III.ImmOpcode = PPC::ANDI_rec;
3904  break;
3905  case PPC::AND8_rec:
3906  III.ImmOpcode = PPC::ANDI8_rec;
3907  break;
3908  case PPC::OR: III.ImmOpcode = PPC::ORI; break;
3909  case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
3910  case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
3911  case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
3912  }
3913  break;
3914  case PPC::RLWNM:
3915  case PPC::RLWNM8:
3916  case PPC::RLWNM_rec:
3917  case PPC::RLWNM8_rec:
3918  case PPC::SLW:
3919  case PPC::SLW8:
3920  case PPC::SLW_rec:
3921  case PPC::SLW8_rec:
3922  case PPC::SRW:
3923  case PPC::SRW8:
3924  case PPC::SRW_rec:
3925  case PPC::SRW8_rec:
3926  case PPC::SRAW:
3927  case PPC::SRAW_rec:
3928  III.SignedImm = false;
3929  III.ZeroIsSpecialOrig = 0;
3930  III.ZeroIsSpecialNew = 0;
3931  III.IsCommutative = false;
3932  // This isn't actually true, but the instructions ignore any of the
3933  // upper bits, so any immediate loaded with an LI is acceptable.
3934  // This does not apply to shift right algebraic because a value
3935  // out of range will produce a -1/0.
3936  III.ImmWidth = 16;
3937  if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 || Opc == PPC::RLWNM_rec ||
3938  Opc == PPC::RLWNM8_rec)
3939  III.TruncateImmTo = 5;
3940  else
3941  III.TruncateImmTo = 6;
3942  switch(Opc) {
3943  default: llvm_unreachable("Unknown opcode");
3944  case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
3945  case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
3946  case PPC::RLWNM_rec:
3947  III.ImmOpcode = PPC::RLWINM_rec;
3948  break;
3949  case PPC::RLWNM8_rec:
3950  III.ImmOpcode = PPC::RLWINM8_rec;
3951  break;
3952  case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
3953  case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
3954  case PPC::SLW_rec:
3955  III.ImmOpcode = PPC::RLWINM_rec;
3956  break;
3957  case PPC::SLW8_rec:
3958  III.ImmOpcode = PPC::RLWINM8_rec;
3959  break;
3960  case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
3961  case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
3962  case PPC::SRW_rec:
3963  III.ImmOpcode = PPC::RLWINM_rec;
3964  break;
3965  case PPC::SRW8_rec:
3966  III.ImmOpcode = PPC::RLWINM8_rec;
3967  break;
3968  case PPC::SRAW:
3969  III.ImmWidth = 5;
3970  III.TruncateImmTo = 0;
3971  III.ImmOpcode = PPC::SRAWI;
3972  break;
3973  case PPC::SRAW_rec:
3974  III.ImmWidth = 5;
3975  III.TruncateImmTo = 0;
3976  III.ImmOpcode = PPC::SRAWI_rec;
3977  break;
3978  }
3979  break;
3980  case PPC::RLDCL:
3981  case PPC::RLDCL_rec:
3982  case PPC::RLDCR:
3983  case PPC::RLDCR_rec:
3984  case PPC::SLD:
3985  case PPC::SLD_rec:
3986  case PPC::SRD:
3987  case PPC::SRD_rec:
3988  case PPC::SRAD:
3989  case PPC::SRAD_rec:
3990  III.SignedImm = false;
3991  III.ZeroIsSpecialOrig = 0;
3992  III.ZeroIsSpecialNew = 0;
3993  III.IsCommutative = false;
3994  // This isn't actually true, but the instructions ignore any of the
3995  // upper bits, so any immediate loaded with an LI is acceptable.
3996  // This does not apply to shift right algebraic because a value
3997  // out of range will produce a -1/0.
3998  III.ImmWidth = 16;
3999  if (Opc == PPC::RLDCL || Opc == PPC::RLDCL_rec || Opc == PPC::RLDCR ||
4000  Opc == PPC::RLDCR_rec)
4001  III.TruncateImmTo = 6;
4002  else
4003  III.TruncateImmTo = 7;
4004  switch(Opc) {
4005  default: llvm_unreachable("Unknown opcode");
4006  case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
4007  case PPC::RLDCL_rec:
4008  III.ImmOpcode = PPC::RLDICL_rec;
4009  break;
4010  case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
4011  case PPC::RLDCR_rec:
4012  III.ImmOpcode = PPC::RLDICR_rec;
4013  break;
4014  case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
4015  case PPC::SLD_rec:
4016  III.ImmOpcode = PPC::RLDICR_rec;
4017  break;
4018  case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
4019  case PPC::SRD_rec:
4020  III.ImmOpcode = PPC::RLDICL_rec;
4021  break;
4022  case PPC::SRAD:
4023  III.ImmWidth = 6;
4024  III.TruncateImmTo = 0;
4025  III.ImmOpcode = PPC::SRADI;
4026  break;
4027  case PPC::SRAD_rec:
4028  III.ImmWidth = 6;
4029  III.TruncateImmTo = 0;
4030  III.ImmOpcode = PPC::SRADI_rec;
4031  break;
4032  }
4033  break;
4034  // Loads and stores:
4035  case PPC::LBZX:
4036  case PPC::LBZX8:
4037  case PPC::LHZX:
4038  case PPC::LHZX8:
4039  case PPC::LHAX:
4040  case PPC::LHAX8:
4041  case PPC::LWZX:
4042  case PPC::LWZX8:
4043  case PPC::LWAX:
4044  case PPC::LDX:
4045  case PPC::LFSX:
4046  case PPC::LFDX:
4047  case PPC::STBX:
4048  case PPC::STBX8:
4049  case PPC::STHX:
4050  case PPC::STHX8:
4051  case PPC::STWX:
4052  case PPC::STWX8:
4053  case PPC::STDX:
4054  case PPC::STFSX:
4055  case PPC::STFDX:
4056  III.SignedImm = true;
4057  III.ZeroIsSpecialOrig = 1;
4058  III.ZeroIsSpecialNew = 2;
4059  III.IsCommutative = true;
4060  III.IsSummingOperands = true;
4061  III.ImmOpNo = 1;
4062  III.OpNoForForwarding = 2;
4063  switch(Opc) {
4064  default: llvm_unreachable("Unknown opcode");
4065  case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break;
4066  case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break;
4067  case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break;
4068  case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break;
4069  case PPC::LHAX: III.ImmOpcode = PPC::LHA; break;
4070  case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break;
4071  case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break;
4072  case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break;
4073  case PPC::LWAX:
4074  III.ImmOpcode = PPC::LWA;
4075  III.ImmMustBeMultipleOf = 4;
4076  break;
4077  case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break;
4078  case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
4079  case PPC::LFDX: III.ImmOpcode = PPC::LFD; break;
4080  case PPC::STBX: III.ImmOpcode = PPC::STB; break;
4081  case PPC::STBX8: III.ImmOpcode = PPC::STB8; break;
4082  case PPC::STHX: III.ImmOpcode = PPC::STH; break;
4083  case PPC::STHX8: III.ImmOpcode = PPC::STH8; break;
4084  case PPC::STWX: III.ImmOpcode = PPC::STW; break;
4085  case PPC::STWX8: III.ImmOpcode = PPC::STW8; break;
4086  case PPC::STDX:
4087  III.ImmOpcode = PPC::STD;
4088  III.ImmMustBeMultipleOf = 4;
4089  break;
4090  case PPC::STFSX: III.ImmOpcode = PPC::STFS; break;
4091  case PPC::STFDX: III.ImmOpcode = PPC::STFD; break;
4092  }
4093  break;
4094  case PPC::LBZUX:
4095  case PPC::LBZUX8:
4096  case PPC::LHZUX:
4097  case PPC::LHZUX8:
4098  case PPC::LHAUX:
4099  case PPC::LHAUX8:
4100  case PPC::LWZUX:
4101  case PPC::LWZUX8:
4102  case PPC::LDUX:
4103  case PPC::LFSUX:
4104  case PPC::LFDUX:
4105  case PPC::STBUX:
4106  case PPC::STBUX8:
4107  case PPC::STHUX:
4108  case PPC::STHUX8:
4109  case PPC::STWUX:
4110  case PPC::STWUX8:
4111  case PPC::STDUX:
4112  case PPC::STFSUX:
4113  case PPC::STFDUX:
4114  III.SignedImm = true;
4115  III.ZeroIsSpecialOrig = 2;
4116  III.ZeroIsSpecialNew = 3;
4117  III.IsCommutative = false;
4118  III.IsSummingOperands = true;
4119  III.ImmOpNo = 2;
4120  III.OpNoForForwarding = 3;
4121  switch(Opc) {
4122  default: llvm_unreachable("Unknown opcode");
4123  case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break;
4124  case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break;
4125  case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break;
4126  case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break;
4127  case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break;
4128  case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break;
4129  case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break;
4130  case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break;
4131  case PPC::LDUX:
4132  III.ImmOpcode = PPC::LDU;
4133  III.ImmMustBeMultipleOf = 4;
4134  break;
4135  case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break;
4136  case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break;
4137  case PPC::STBUX: III.ImmOpcode = PPC::STBU; break;
4138  case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break;
4139  case PPC::STHUX: III.ImmOpcode = PPC::STHU; break;
4140  case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break;
4141  case PPC::STWUX: III.ImmOpcode = PPC::STWU; break;
4142  case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break;
4143  case PPC::STDUX:
4144  III.ImmOpcode = PPC::STDU;
4145  III.ImmMustBeMultipleOf = 4;
4146  break;
4147  case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break;
4148  case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break;
4149  }
4150  break;
4151  // Power9 and up only. For some of these, the X-Form version has access to all
4152  // 64 VSR's whereas the D-Form only has access to the VR's. We replace those
4153  // with pseudo-ops pre-ra and for post-ra, we check that the register loaded
4154  // into or stored from is one of the VR registers.
4155  case PPC::LXVX:
4156  case PPC::LXSSPX:
4157  case PPC::LXSDX:
4158  case PPC::STXVX:
4159  case PPC::STXSSPX:
4160  case PPC::STXSDX:
4161  case PPC::XFLOADf32:
4162  case PPC::XFLOADf64:
4163  case PPC::XFSTOREf32:
4164  case PPC::XFSTOREf64:
4165  if (!Subtarget.hasP9Vector())
4166  return false;
4167  III.SignedImm = true;
4168  III.ZeroIsSpecialOrig = 1;
4169  III.ZeroIsSpecialNew = 2;
4170  III.IsCommutative = true;
4171  III.IsSummingOperands = true;
4172  III.ImmOpNo = 1;
4173  III.OpNoForForwarding = 2;
4174  III.ImmMustBeMultipleOf = 4;
4175  switch(Opc) {
4176  default: llvm_unreachable("Unknown opcode");
4177  case PPC::LXVX:
4178  III.ImmOpcode = PPC::LXV;
4179  III.ImmMustBeMultipleOf = 16;
4180  break;
4181  case PPC::LXSSPX:
4182  if (PostRA) {
4183  if (IsVFReg)
4184  III.ImmOpcode = PPC::LXSSP;
4185  else {
4186  III.ImmOpcode = PPC::LFS;
4187  III.ImmMustBeMultipleOf = 1;
4188  }
4189  break;
4190  }
4192  case PPC::XFLOADf32:
4193  III.ImmOpcode = PPC::DFLOADf32;
4194  break;
4195  case PPC::LXSDX:
4196  if (PostRA) {
4197  if (IsVFReg)
4198  III.ImmOpcode = PPC::LXSD;
4199  else {
4200  III.ImmOpcode = PPC::LFD;
4201  III.ImmMustBeMultipleOf = 1;
4202  }
4203  break;
4204  }
4206  case PPC::XFLOADf64:
4207  III.ImmOpcode = PPC::DFLOADf64;
4208  break;
4209  case PPC::STXVX:
4210  III.ImmOpcode = PPC::STXV;
4211  III.ImmMustBeMultipleOf = 16;
4212  break;
4213  case PPC::STXSSPX:
4214  if (PostRA) {
4215  if (IsVFReg)
4216  III.ImmOpcode = PPC::STXSSP;
4217  else {
4218  III.ImmOpcode = PPC::STFS;
4219  III.ImmMustBeMultipleOf = 1;
4220  }
4221  break;
4222  }
4224  case PPC::XFSTOREf32:
4225  III.ImmOpcode = PPC::DFSTOREf32;
4226  break;
4227  case PPC::STXSDX:
4228  if (PostRA) {
4229  if (IsVFReg)
4230  III.ImmOpcode = PPC::STXSD;
4231  else {
4232  III.ImmOpcode = PPC::STFD;
4233  III.ImmMustBeMultipleOf = 1;
4234  }
4235  break;
4236  }
4238  case PPC::XFSTOREf64:
4239  III.ImmOpcode = PPC::DFSTOREf64;
4240  break;
4241  }
4242  break;
4243  }
4244  return true;
4245 }
4246 
4247 // Utility function for swaping two arbitrary operands of an instruction.
4248 static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
4249  assert(Op1 != Op2 && "Cannot swap operand with itself.");
4250 
4251  unsigned MaxOp = std::max(Op1, Op2);
4252  unsigned MinOp = std::min(Op1, Op2);
4253  MachineOperand MOp1 = MI.getOperand(MinOp);
4254  MachineOperand MOp2 = MI.getOperand(MaxOp);
4255  MI.RemoveOperand(std::max(Op1, Op2));
4256  MI.RemoveOperand(std::min(Op1, Op2));
4257 
4258  // If the operands we are swapping are the two at the end (the common case)
4259  // we can just remove both and add them in the opposite order.
4260  if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) {
4261  MI.addOperand(MOp2);
4262  MI.addOperand(MOp1);
4263  } else {
4264  // Store all operands in a temporary vector, remove them and re-add in the
4265  // right order.
4267  unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
4268  for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
4269  MOps.push_back(MI.getOperand(i));
4270  MI.RemoveOperand(i);
4271  }
4272  // MOp2 needs to be added next.
4273  MI.addOperand(MOp2);
4274  // Now add the rest.
4275  for (unsigned i = MI.getNumOperands(); i < TotalOps; i++) {
4276  if (i == MaxOp)
4277  MI.addOperand(MOp1);
4278  else {
4279  MI.addOperand(MOps.back());
4280  MOps.pop_back();
4281  }
4282  }
4283  }
4284 }
4285 
4286 // Check if the 'MI' that has the index OpNoForForwarding
4287 // meets the requirement described in the ImmInstrInfo.
4288 bool PPCInstrInfo::isUseMIElgibleForForwarding(MachineInstr &MI,
4289  const ImmInstrInfo &III,
4290  unsigned OpNoForForwarding
4291  ) const {
4292  // As the algorithm of checking for PPC::ZERO/PPC::ZERO8
4293  // would not work pre-RA, we can only do the check post RA.
4294  MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4295  if (MRI.isSSA())
4296  return false;
4297 
4298  // Cannot do the transform if MI isn't summing the operands.
4299  if (!III.IsSummingOperands)
4300  return false;
4301 
4302  // The instruction we are trying to replace must have the ZeroIsSpecialOrig set.
4303  if (!III.ZeroIsSpecialOrig)
4304  return false;
4305 
4306  // We cannot do the transform if the operand we are trying to replace
4307  // isn't the same as the operand the instruction allows.
4308  if (OpNoForForwarding != III.OpNoForForwarding)
4309  return false;
4310 
4311  // Check if the instruction we are trying to transform really has
4312  // the special zero register as its operand.
4313  if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO &&
4314  MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8)
4315  return false;
4316 
4317  // This machine instruction is convertible if it is,
4318  // 1. summing the operands.
4319  // 2. one of the operands is special zero register.
4320  // 3. the operand we are trying to replace is allowed by the MI.
4321  return true;
4322 }
4323 
4324 // Check if the DefMI is the add inst and set the ImmMO and RegMO
4325 // accordingly.
4326 bool PPCInstrInfo::isDefMIElgibleForForwarding(MachineInstr &DefMI,
4327  const ImmInstrInfo &III,
4328  MachineOperand *&ImmMO,
4329  MachineOperand *&RegMO) const {
4330  unsigned Opc = DefMI.getOpcode();
4331  if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8)
4332  return false;
4333 
4334  assert(DefMI.getNumOperands() >= 3 &&
4335  "Add inst must have at least three operands");
4336  RegMO = &DefMI.getOperand(1);
4337  ImmMO = &DefMI.getOperand(2);
4338 
4339  // Before RA, ADDI first operand could be a frame index.
4340  if (!RegMO->isReg())
4341  return false;
4342 
4343  // This DefMI is elgible for forwarding if it is:
4344  // 1. add inst
4345  // 2. one of the operands is Imm/CPI/Global.
4346  return isAnImmediateOperand(*ImmMO);
4347 }
4348 
4349 bool PPCInstrInfo::isRegElgibleForForwarding(
4350  const MachineOperand &RegMO, const MachineInstr &DefMI,
4351  const MachineInstr &MI, bool KillDefMI,
4352  bool &IsFwdFeederRegKilled) const {
4353  // x = addi y, imm
4354  // ...
4355  // z = lfdx 0, x -> z = lfd imm(y)
4356  // The Reg "y" can be forwarded to the MI(z) only when there is no DEF
4357  // of "y" between the DEF of "x" and "z".
4358  // The query is only valid post RA.
4359  const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4360  if (MRI.isSSA())
4361  return false;
4362 
4363  Register Reg = RegMO.getReg();
4364 
4365  // Walking the inst in reverse(MI-->DefMI) to get the last DEF of the Reg.
4367  MachineBasicBlock::const_reverse_iterator E = MI.getParent()->rend();
4368  It++;
4369  for (; It != E; ++It) {
4370  if (It->modifiesRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
4371  return false;
4372  else if (It->killsRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
4373  IsFwdFeederRegKilled = true;
4374  // Made it to DefMI without encountering a clobber.
4375  if ((&*It) == &DefMI)
4376  break;
4377  }
4378  assert((&*It) == &DefMI && "DefMI is missing");
4379 
4380  // If DefMI also defines the register to be forwarded, we can only forward it
4381  // if DefMI is being erased.
4382  if (DefMI.modifiesRegister(Reg, &getRegisterInfo()))
4383  return KillDefMI;
4384 
4385  return true;
4386 }
4387 
4388 bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
4389  const MachineInstr &DefMI,
4390  const ImmInstrInfo &III,
4391  int64_t &Imm,
4392  int64_t BaseImm) const {
4393  assert(isAnImmediateOperand(ImmMO) && "ImmMO is NOT an immediate");
4394  if (DefMI.getOpcode() == PPC::ADDItocL) {
4395  // The operand for ADDItocL is CPI, which isn't imm at compiling time,
4396  // However, we know that, it is 16-bit width, and has the alignment of 4.
4397  // Check if the instruction met the requirement.
4398  if (III.ImmMustBeMultipleOf > 4 ||
4399  III.TruncateImmTo || III.ImmWidth != 16)
4400  return false;
4401 
4402  // Going from XForm to DForm loads means that the displacement needs to be
4403  // not just an immediate but also a multiple of 4, or 16 depending on the
4404  // load. A DForm load cannot be represented if it is a multiple of say 2.
4405  // XForm loads do not have this restriction.
4406  if (ImmMO.isGlobal()) {
4407  const DataLayout &DL = ImmMO.getGlobal()->getParent()->getDataLayout();
4409  return false;
4410  }
4411 
4412  return true;
4413  }
4414 
4415  if (ImmMO.isImm()) {
4416  // It is Imm, we need to check if the Imm fit the range.
4417  // Sign-extend to 64-bits.
4418  // DefMI may be folded with another imm form instruction, the result Imm is
4419  // the sum of Imm of DefMI and BaseImm which is from imm form instruction.
4420  APInt ActualValue(64, ImmMO.getImm() + BaseImm, true);
4421  if (III.SignedImm && !ActualValue.isSignedIntN(III.ImmWidth))
4422  return false;
4423  if (!III.SignedImm && !ActualValue.isIntN(III.ImmWidth))
4424  return false;
4425  Imm = SignExtend64<16>(ImmMO.getImm() + BaseImm);
4426 
4427  if (Imm % III.ImmMustBeMultipleOf)
4428  return false;
4429  if (III.TruncateImmTo)
4430  Imm &= ((1 << III.TruncateImmTo) - 1);
4431  }
4432  else
4433  return false;
4434 
4435  // This ImmMO is forwarded if it meets the requriement describle
4436  // in ImmInstrInfo
4437  return true;
4438 }
4439 
4440 bool PPCInstrInfo::simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
4441  unsigned OpNoForForwarding,
4442  MachineInstr **KilledDef) const {
4443  if ((DefMI.getOpcode() != PPC::LI && DefMI.getOpcode() != PPC::LI8) ||
4444  !DefMI.getOperand(1).isImm())
4445  return false;
4446 
4447  MachineFunction *MF = MI.getParent()->getParent();
4449  bool PostRA = !MRI->isSSA();
4450 
4451  int64_t Immediate = DefMI.getOperand(1).getImm();
4452  // Sign-extend to 64-bits.
4453  int64_t SExtImm = SignExtend64<16>(Immediate);
4454 
4455  bool IsForwardingOperandKilled = MI.getOperand(OpNoForForwarding).isKill();
4456  Register ForwardingOperandReg = MI.getOperand(OpNoForForwarding).getReg();
4457 
4458  bool ReplaceWithLI = false;
4459  bool Is64BitLI = false;
4460  int64_t NewImm = 0;
4461  bool SetCR = false;
4462  unsigned Opc = MI.getOpcode();
4463  switch (Opc) {
4464  default:
4465  return false;
4466 
4467  // FIXME: Any branches conditional on such a comparison can be made
4468  // unconditional. At this time, this happens too infrequently to be worth
4469  // the implementation effort, but if that ever changes, we could convert
4470  // such a pattern here.
4471  case PPC::CMPWI:
4472  case PPC::CMPLWI:
4473  case PPC::CMPDI:
4474  case PPC::CMPLDI: {
4475  // Doing this post-RA would require dataflow analysis to reliably find uses
4476  // of the CR register set by the compare.
4477  // No need to fixup killed/dead flag since this transformation is only valid
4478  // before RA.
4479  if (PostRA)
4480  return false;
4481  // If a compare-immediate is fed by an immediate and is itself an input of
4482  // an ISEL (the most common case) into a COPY of the correct register.
4483  bool Changed = false;
4484  Register DefReg = MI.getOperand(0).getReg();
4485  int64_t Comparand = MI.getOperand(2).getImm();
4486  int64_t SExtComparand = ((uint64_t)Comparand & ~0x7FFFuLL) != 0
4487  ? (Comparand | 0xFFFFFFFFFFFF0000)
4488  : Comparand;
4489 
4490  for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
4491  unsigned UseOpc = CompareUseMI.getOpcode();
4492  if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
4493  continue;
4494  unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
4495  Register TrueReg = CompareUseMI.getOperand(1).getReg();
4496  Register FalseReg = CompareUseMI.getOperand(2).getReg();
4497  unsigned RegToCopy =
4498  selectReg(SExtImm, SExtComparand, Opc, TrueReg, FalseReg, CRSubReg);
4499  if (RegToCopy == PPC::NoRegister)
4500  continue;
4501  // Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0.
4502  if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
4503  CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
4504  replaceInstrOperandWithImm(CompareUseMI, 1, 0);
4505  CompareUseMI.RemoveOperand(3);
4506  CompareUseMI.RemoveOperand(2);
4507  continue;
4508  }
4509  LLVM_DEBUG(
4510  dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n");
4511  LLVM_DEBUG(DefMI.dump(); MI.dump(); CompareUseMI.dump());
4512  LLVM_DEBUG(dbgs() << "Is converted to:\n");
4513  // Convert to copy and remove unneeded operands.
4514  CompareUseMI.setDesc(get(PPC::COPY));
4515  CompareUseMI.RemoveOperand(3);
4516  CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
4517  CmpIselsConverted++;
4518  Changed = true;
4519  LLVM_DEBUG(CompareUseMI.dump());
4520  }
4521  if (Changed)
4522  return true;
4523  // This may end up incremented multiple times since this function is called
4524  // during a fixed-point transformation, but it is only meant to indicate the
4525  // presence of this opportunity.
4526  MissedConvertibleImmediateInstrs++;
4527  return false;
4528  }
4529 
4530  // Immediate forms - may simply be convertable to an LI.
4531  case PPC::ADDI:
4532  case PPC::ADDI8: {
4533  // Does the sum fit in a 16-bit signed field?
4534  int64_t Addend = MI.getOperand(2).getImm();
4535  if (isInt<16>(Addend + SExtImm)) {
4536  ReplaceWithLI = true;
4537  Is64BitLI = Opc == PPC::ADDI8;
4538  NewImm = Addend + SExtImm;
4539  break;
4540  }
4541  return false;
4542  }
4543  case PPC::SUBFIC:
4544  case PPC::SUBFIC8: {
4545  // Only transform this if the CARRY implicit operand is dead.
4546  if (MI.getNumOperands() > 3 && !MI.getOperand(3).isDead())
4547  return false;
4548  int64_t Minuend = MI.getOperand(2).getImm();
4549  if (isInt<16>(Minuend - SExtImm)) {
4550  ReplaceWithLI = true;
4551  Is64BitLI = Opc == PPC::SUBFIC8;
4552  NewImm = Minuend - SExtImm;
4553  break;
4554  }
4555  return false;
4556  }
4557  case PPC::RLDICL:
4558  case PPC::RLDICL_rec:
4559  case PPC::RLDICL_32:
4560  case PPC::RLDICL_32_64: {
4561  // Use APInt's rotate function.
4562  int64_t SH = MI.getOperand(2).getImm();
4563  int64_t MB = MI.getOperand(3).getImm();
4564  APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec) ? 64 : 32,
4565  SExtImm, true);
4566  InVal = InVal.rotl(SH);
4567  uint64_t Mask = MB == 0 ? -1LLU : (1LLU << (63 - MB + 1)) - 1;
4568  InVal &= Mask;
4569  // Can't replace negative values with an LI as that will sign-extend
4570  // and not clear the left bits. If we're setting the CR bit, we will use
4571  // ANDI_rec which won't sign extend, so that's safe.
4572  if (isUInt<15>(InVal.getSExtValue()) ||
4573  (Opc == PPC::RLDICL_rec && isUInt<16>(InVal.getSExtValue()))) {
4574  ReplaceWithLI = true;
4575  Is64BitLI = Opc != PPC::RLDICL_32;
4576  NewImm = InVal.getSExtValue();
4577  SetCR = Opc == PPC::RLDICL_rec;
4578  break;
4579  }
4580  return false;
4581  }
4582  case PPC::RLWINM:
4583  case PPC::RLWINM8:
4584  case PPC::RLWINM_rec:
4585  case PPC::RLWINM8_rec: {
4586  int64_t SH = MI.getOperand(2).getImm();
4587  int64_t MB = MI.getOperand(3).getImm();
4588  int64_t ME = MI.getOperand(4).getImm();
4589  APInt InVal(32, SExtImm, true);
4590  InVal = InVal.rotl(SH);
4591  APInt Mask = APInt::getBitsSetWithWrap(32, 32 - ME - 1, 32 - MB);
4592  InVal &= Mask;
4593  // Can't replace negative values with an LI as that will sign-extend
4594  // and not clear the left bits. If we're setting the CR bit, we will use
4595  // ANDI_rec which won't sign extend, so that's safe.
4596  bool ValueFits = isUInt<15>(InVal.getSExtValue());
4597  ValueFits |= ((Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec) &&
4598  isUInt<16>(InVal.getSExtValue()));
4599  if (ValueFits) {
4600  ReplaceWithLI = true;
4601  Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8_rec;
4602  NewImm = InVal.getSExtValue();
4603  SetCR = Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec;
4604  break;
4605  }
4606  return false;
4607  }
4608  case PPC::ORI:
4609  case PPC::ORI8:
4610  case PPC::XORI:
4611  case PPC::XORI8: {
4612  int64_t LogicalImm = MI.getOperand(2).getImm();
4613  int64_t Result = 0;
4614  if (Opc == PPC::ORI || Opc == PPC::ORI8)
4615  Result = LogicalImm | SExtImm;
4616  else
4617  Result = LogicalImm ^ SExtImm;
4618  if (isInt<16>(Result)) {
4619  ReplaceWithLI = true;
4620  Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
4621  NewImm = Result;
4622  break;
4623  }
4624  return false;
4625  }
4626  }
4627 
4628  if (ReplaceWithLI) {
4629  // We need to be careful with CR-setting instructions we're replacing.
4630  if (SetCR) {
4631  // We don't know anything about uses when we're out of SSA, so only
4632  // replace if the new immediate will be reproduced.
4633  bool ImmChanged = (SExtImm & NewImm) != NewImm;
4634  if (PostRA && ImmChanged)
4635  return false;
4636 
4637  if (!PostRA) {
4638  // If the defining load-immediate has no other uses, we can just replace
4639  // the immediate with the new immediate.
4640  if (MRI->hasOneUse(DefMI.getOperand(0).getReg()))
4641  DefMI.getOperand(1).setImm(NewImm);
4642 
4643  // If we're not using the GPR result of the CR-setting instruction, we
4644  // just need to and with zero/non-zero depending on the new immediate.
4645  else if (MRI->use_empty(MI.getOperand(0).getReg())) {
4646  if (NewImm) {
4647  assert(Immediate && "Transformation converted zero to non-zero?");
4648  NewImm = Immediate;
4649  }
4650  } else if (ImmChanged)
4651  return false;
4652  }
4653  }
4654 
4655  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
4656  LLVM_DEBUG(MI.dump());
4657  LLVM_DEBUG(dbgs() << "Fed by:\n");
4658  LLVM_DEBUG(DefMI.dump());
4659  LoadImmediateInfo LII;
4660  LII.Imm = NewImm;
4661  LII.Is64Bit = Is64BitLI;
4662  LII.SetCR = SetCR;
4663  // If we're setting the CR, the original load-immediate must be kept (as an
4664  // operand to ANDI_rec/ANDI8_rec).
4665  if (KilledDef && SetCR)
4666  *KilledDef = nullptr;
4667  replaceInstrWithLI(MI, LII);
4668 
4669  // Fixup killed/dead flag after transformation.
4670  // Pattern:
4671  // ForwardingOperandReg = LI imm1
4672  // y = op2 imm2, ForwardingOperandReg(killed)
4673  if (IsForwardingOperandKilled)
4674  fixupIsDeadOrKill(&DefMI, &MI, ForwardingOperandReg);
4675 
4676  LLVM_DEBUG(dbgs() << "With:\n");
4677  LLVM_DEBUG(MI.dump());
4678  return true;
4679  }
4680  return false;
4681 }
4682 
4683 bool PPCInstrInfo::transformToNewImmFormFedByAdd(
4684  MachineInstr &MI, MachineInstr &DefMI, unsigned OpNoForForwarding) const {
4685  MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
4686  bool PostRA = !MRI->isSSA();
4687  // FIXME: extend this to post-ra. Need to do some change in getForwardingDefMI
4688  // for post-ra.
4689  if (PostRA)
4690  return false;
4691 
4692  // Only handle load/store.
4693  if (!MI.mayLoadOrStore())
4694  return false;
4695 
4696  unsigned XFormOpcode = RI.getMappedIdxOpcForImmOpc(MI.getOpcode());
4697 
4698  assert((XFormOpcode != PPC::INSTRUCTION_LIST_END) &&
4699  "MI must have x-form opcode");
4700 
4701  // get Imm Form info.
4702  ImmInstrInfo III;
4703  bool IsVFReg = MI.getOperand(0).isReg()
4704  ? isVFRegister(MI.getOperand(0).getReg())
4705  : false;
4706 
4707  if (!instrHasImmForm(XFormOpcode, IsVFReg, III, PostRA))
4708  return false;
4709 
4710  if (!III.IsSummingOperands)
4711  return false;
4712 
4713  if (OpNoForForwarding != III.OpNoForForwarding)
4714  return false;
4715 
4716  MachineOperand ImmOperandMI = MI.getOperand(III.ImmOpNo);
4717  if (!ImmOperandMI.isImm())
4718  return false;
4719 
4720  // Check DefMI.
4721  MachineOperand *ImmMO = nullptr;
4722  MachineOperand *RegMO = nullptr;
4723  if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
4724  return false;
4725  assert(ImmMO && RegMO && "Imm and Reg operand must have been set");
4726 
4727  // Check Imm.
4728  // Set ImmBase from imm instruction as base and get new Imm inside
4729  // isImmElgibleForForwarding.
4730  int64_t ImmBase = ImmOperandMI.getImm();
4731  int64_t Imm = 0;
4732  if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm, ImmBase))
4733  return false;
4734 
4735  // Get killed info in case fixup needed after transformation.
4736  unsigned ForwardKilledOperandReg = ~0U;
4737  if (MI.getOperand(III.OpNoForForwarding).isKill())
4738  ForwardKilledOperandReg = MI.getOperand(III.OpNoForForwarding).getReg();
4739 
4740  // Do the transform
4741  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
4742  LLVM_DEBUG(MI.dump());
4743  LLVM_DEBUG(dbgs() << "Fed by:\n");
4744  LLVM_DEBUG(DefMI.dump());
4745 
4746  MI.getOperand(III.OpNoForForwarding).setReg(RegMO->getReg());
4747  if (RegMO->isKill()) {
4748  MI.getOperand(III.OpNoForForwarding).setIsKill(true);
4749  // Clear the killed flag in RegMO. Doing this here can handle some cases
4750  // that DefMI and MI are not in same basic block.
4751  RegMO->setIsKill(false);
4752  }
4753  MI.getOperand(III.ImmOpNo).setImm(Imm);
4754 
4755  // FIXME: fix kill/dead flag if MI and DefMI are not in same basic block.
4756  if (DefMI.getParent() == MI.getParent()) {
4757  // Check if reg is killed between MI and DefMI.
4758  auto IsKilledFor = [&](unsigned Reg) {
4761  It++;
4762  for (; It != E; ++It) {
4763  if (It->killsRegister(Reg))
4764  return true;
4765  }
4766  return false;
4767  };
4768 
4769  // Update kill flag
4770  if (RegMO->isKill() || IsKilledFor(RegMO->getReg()))
4771  fixupIsDeadOrKill(&DefMI, &MI, RegMO->getReg());
4772  if (ForwardKilledOperandReg != ~0U)
4773  fixupIsDeadOrKill(&DefMI, &MI, ForwardKilledOperandReg);
4774  }
4775 
4776  LLVM_DEBUG(dbgs() << "With:\n");
4777  LLVM_DEBUG(MI.dump());
4778  return true;
4779 }
4780 
4781 // If an X-Form instruction is fed by an add-immediate and one of its operands
4782 // is the literal zero, attempt to forward the source of the add-immediate to
4783 // the corresponding D-Form instruction with the displacement coming from
4784 // the immediate being added.
4785 bool PPCInstrInfo::transformToImmFormFedByAdd(
4786  MachineInstr &MI, const ImmInstrInfo &III, unsigned OpNoForForwarding,
4787  MachineInstr &DefMI, bool KillDefMI) const {
4788  // RegMO ImmMO
4789  // | |
4790  // x = addi reg, imm <----- DefMI
4791  // y = op 0 , x <----- MI
4792  // |
4793  // OpNoForForwarding
4794  // Check if the MI meet the requirement described in the III.
4795  if (!isUseMIElgibleForForwarding(MI, III, OpNoForForwarding))
4796  return false;
4797 
4798  // Check if the DefMI meet the requirement
4799  // described in the III. If yes, set the ImmMO and RegMO accordingly.
4800  MachineOperand *ImmMO = nullptr;
4801  MachineOperand *RegMO = nullptr;
4802  if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
4803  return false;
4804  assert(ImmMO && RegMO && "Imm and Reg operand must have been set");
4805 
4806  // As we get the Imm operand now, we need to check if the ImmMO meet
4807  // the requirement described in the III. If yes set the Imm.
4808  int64_t Imm = 0;
4809  if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm))
4810  return false;
4811 
4812  bool IsFwdFeederRegKilled = false;
4813  // Check if the RegMO can be forwarded to MI.
4814  if (!isRegElgibleForForwarding(*RegMO, DefMI, MI, KillDefMI,
4815  IsFwdFeederRegKilled))
4816  return false;
4817 
4818  // Get killed info in case fixup needed after transformation.
4819  unsigned ForwardKilledOperandReg = ~0U;
4820  MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4821  bool PostRA = !MRI.isSSA();
4822  if (PostRA && MI.getOperand(OpNoForForwarding).isKill())
4823  ForwardKilledOperandReg = MI.getOperand(OpNoForForwarding).getReg();
4824 
4825  // We know that, the MI and DefMI both meet the pattern, and
4826  // the Imm also meet the requirement with the new Imm-form.
4827  // It is safe to do the transformation now.
4828  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
4829  LLVM_DEBUG(MI.dump());
4830  LLVM_DEBUG(dbgs() << "Fed by:\n");
4831  LLVM_DEBUG(DefMI.dump());
4832 
4833  // Update the base reg first.
4834  MI.getOperand(III.OpNoForForwarding).ChangeToRegister(RegMO->getReg(),
4835  false, false,
4836  RegMO->isKill());
4837 
4838  // Then, update the imm.
4839  if (ImmMO->isImm()) {
4840  // If the ImmMO is Imm, change the operand that has ZERO to that Imm
4841  // directly.
4843  }
4844  else {
4845  // Otherwise, it is Constant Pool Index(CPI) or Global,
4846  // which is relocation in fact. We need to replace the special zero
4847  // register with ImmMO.
4848  // Before that, we need to fixup the target flags for imm.
4849  // For some reason, we miss to set the flag for the ImmMO if it is CPI.
4850  if (DefMI.getOpcode() == PPC::ADDItocL)
4852 
4853  // MI didn't have the interface such as MI.setOperand(i) though
4854  // it has MI.getOperand(i). To repalce the ZERO MachineOperand with
4855  // ImmMO, we need to remove ZERO operand and all the operands behind it,
4856  // and, add the ImmMO, then, move back all the operands behind ZERO.
4858  for (unsigned i = MI.getNumOperands() - 1; i >= III.ZeroIsSpecialOrig; i--) {
4859  MOps.push_back(MI.getOperand(i));
4860  MI.RemoveOperand(i);
4861  }
4862 
4863  // Remove the last MO in the list, which is ZERO operand in fact.
4864  MOps.pop_back();
4865  // Add the imm operand.
4866  MI.addOperand(*ImmMO);
4867  // Now add the rest back.
4868  for (auto &MO : MOps)
4869  MI.addOperand(MO);
4870  }
4871 
4872  // Update the opcode.
4873  MI.setDesc(get(III.ImmOpcode));
4874 
4875  // Fix up killed/dead flag after transformation.
4876  // Pattern 1:
4877  // x = ADD KilledFwdFeederReg, imm
4878  // n = opn KilledFwdFeederReg(killed), regn
4879  // y = XOP 0, x
4880  // Pattern 2:
4881  // x = ADD reg(killed), imm
4882  // y = XOP 0, x
4883  if (IsFwdFeederRegKilled || RegMO->isKill())
4884  fixupIsDeadOrKill(&DefMI, &MI, RegMO->getReg());
4885  // Pattern 3:
4886  // ForwardKilledOperandReg = ADD reg, imm
4887  // y = XOP 0, ForwardKilledOperandReg(killed)
4888  if (ForwardKilledOperandReg != ~0U)
4889  fixupIsDeadOrKill(&DefMI, &MI, ForwardKilledOperandReg);
4890 
4891  LLVM_DEBUG(dbgs() << "With:\n");
4892  LLVM_DEBUG(MI.dump());
4893 
4894  return true;
4895 }
4896 
4897 bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
4898  const ImmInstrInfo &III,
4899  unsigned ConstantOpNo,
4900  MachineInstr &DefMI) const {
4901  // DefMI must be LI or LI8.
4902  if ((DefMI.getOpcode() != PPC::LI && DefMI.getOpcode() != PPC::LI8) ||
4903  !DefMI.getOperand(1).isImm())
4904  return false;
4905 
4906  // Get Imm operand and Sign-extend to 64-bits.
4907  int64_t Imm = SignExtend64<16>(DefMI.getOperand(1).getImm());
4908 
4909  MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4910  bool PostRA = !MRI.isSSA();
4911  // Exit early if we can't convert this.
4912  if ((ConstantOpNo != III.OpNoForForwarding) && !III.IsCommutative)
4913  return false;
4914  if (Imm % III.ImmMustBeMultipleOf)
4915  return false;
4916  if (III.TruncateImmTo)
4917  Imm &= ((1 << III.TruncateImmTo) - 1);
4918  if (III.SignedImm) {
4919  APInt ActualValue(64, Imm, true);
4920  if (!ActualValue.isSignedIntN(III.ImmWidth))
4921  return false;
4922  } else {
4923  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
4924  if ((uint64_t)Imm > UnsignedMax)
4925  return false;
4926  }
4927 
4928  // If we're post-RA, the instructions don't agree on whether register zero is
4929  // special, we can transform this as long as the register operand that will
4930  // end up in the location where zero is special isn't R0.
4931  if (PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
4932  unsigned PosForOrigZero = III.ZeroIsSpecialOrig ? III.