49#define DEBUG_TYPE "ppc-instr-info"
51#define GET_INSTRMAP_INFO
52#define GET_INSTRINFO_CTOR_DTOR
53#include "PPCGenInstrInfo.inc"
56 "Number of spillvsrrc spilled to stack as vec");
58 "Number of spillvsrrc spilled to stack as gpr");
59STATISTIC(NumGPRtoVSRSpill,
"Number of gpr spills to spillvsrrc");
61 "Number of ISELs that depend on comparison of constants converted");
63 "Number of compare-immediate instructions fed by constants");
65 "Number of record-form rotates converted to record-form andi");
69 cl::desc(
"Disable analysis for CTR loops"));
75cl::desc(
"Causes the backend to crash instead of generating a nop VSX copy"),
80 cl::desc(
"Use the old (incorrect) instruction latency calculation"));
84 cl::desc(
"register pressure factor for the transformations."));
88 cl::desc(
"enable register pressure reduce in machine combiner pass."));
91void PPCInstrInfo::anchor() {}
96 STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
97 Subtarget(STI), RI(STI.getTargetMachine()) {}
105 static_cast<const PPCSubtarget *
>(STI)->getCPUDirective();
109 static_cast<const PPCSubtarget *
>(STI)->getInstrItineraryData();
141 unsigned *PredCost)
const {
143 return PPCGenInstrInfo::getInstrLatency(ItinData,
MI, PredCost);
153 unsigned DefClass =
MI.getDesc().getSchedClass();
154 for (
unsigned i = 0, e =
MI.getNumOperands(); i != e; ++i) {
172 unsigned UseIdx)
const {
173 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData,
DefMI, DefIdx,
176 if (!
DefMI.getParent())
183 if (Reg.isVirtual()) {
186 IsRegCR =
MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
187 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
189 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
190 PPC::CRBITRCRegClass.contains(Reg);
193 if (
UseMI.isBranch() && IsRegCR) {
293#define InfoArrayIdxFMAInst 0
294#define InfoArrayIdxFAddInst 1
295#define InfoArrayIdxFMULInst 2
296#define InfoArrayIdxAddOpIdx 3
297#define InfoArrayIdxMULOpIdx 4
298#define InfoArrayIdxFSubInst 5
309 {PPC::XSMADDADP, PPC::XSADDDP, PPC::XSMULDP, 1, 2, PPC::XSSUBDP},
310 {PPC::XSMADDASP, PPC::XSADDSP, PPC::XSMULSP, 1, 2, PPC::XSSUBSP},
311 {PPC::XVMADDADP, PPC::XVADDDP, PPC::XVMULDP, 1, 2, PPC::XVSUBDP},
312 {PPC::XVMADDASP, PPC::XVADDSP, PPC::XVMULSP, 1, 2, PPC::XVSUBSP},
313 {PPC::FMADD, PPC::FADD, PPC::FMUL, 3, 1, PPC::FSUB},
314 {PPC::FMADDS, PPC::FADDS, PPC::FMULS, 3, 1, PPC::FSUBS}};
318int16_t PPCInstrInfo::getFMAOpIdxInfo(
unsigned Opcode)
const {
375 bool DoRegPressureReduce)
const {
380 auto IsAllOpsVirtualReg = [](
const MachineInstr &Instr) {
381 for (
const auto &MO : Instr.explicit_operands())
382 if (!(MO.isReg() && MO.getReg().isVirtual()))
387 auto IsReassociableAddOrSub = [&](
const MachineInstr &Instr,
389 if (Instr.getOpcode() !=
400 if (!IsAllOpsVirtualReg(Instr))
406 !
MRI->hasOneNonDBGUse(Instr.getOperand(0).getReg()))
412 auto IsReassociableFMA = [&](
const MachineInstr &Instr, int16_t &AddOpIdx,
413 int16_t &MulOpIdx,
bool IsLeaf) {
414 int16_t
Idx = getFMAOpIdxInfo(Instr.getOpcode());
425 if (!IsAllOpsVirtualReg(Instr))
445 int16_t AddOpIdx = -1;
446 int16_t MulOpIdx = -1;
448 bool IsUsedOnceL =
false;
449 bool IsUsedOnceR =
false;
453 auto IsRPReductionCandidate = [&]() {
457 if (Opcode != PPC::XSMADDASP && Opcode != PPC::XSMADDADP)
462 if (IsReassociableFMA(Root, AddOpIdx, MulOpIdx,
true)) {
463 assert((MulOpIdx >= 0) &&
"mul operand index not right!");
464 Register MULRegL =
TRI->lookThruSingleUseCopyChain(
466 Register MULRegR =
TRI->lookThruSingleUseCopyChain(
468 if (!MULRegL && !MULRegR)
471 if (MULRegL && !MULRegR) {
475 }
else if (!MULRegL && MULRegR) {
487 MULInstrL =
MRI->getVRegDef(MULRegL);
488 MULInstrR =
MRI->getVRegDef(MULRegR);
495 if (DoRegPressureReduce && IsRPReductionCandidate()) {
496 assert((MULInstrL && MULInstrR) &&
"wrong register preduction candidate!");
517 if (!IsReassociableFMA(Root, AddOpIdx, MulOpIdx,
false))
520 assert((AddOpIdx >= 0) &&
"add operand index not right!");
527 if (!IsReassociableFMA(*Prev, AddOpIdx, MulOpIdx,
false))
530 assert((AddOpIdx >= 0) &&
"add operand index not right!");
535 if (IsReassociableFMA(*Leaf, AddOpIdx, MulOpIdx,
true)) {
551 assert(!InsInstrs.
empty() &&
"Instructions set to be inserted is empty!");
584 assert(isa<llvm::ConstantFP>(
C) &&
"not a valid constant!");
587 APFloat F1((dyn_cast<ConstantFP>(
C))->getValueAPF());
597 for (
auto *Inst : InsInstrs) {
599 assert(Operand.isReg() &&
"Invalid instruction in InsInstrs!");
600 if (Operand.getReg() == PPC::ZERO8) {
601 Placeholder = &Operand;
607 assert(Placeholder &&
"Placeholder does not exist!");
612 generateLoadForNewConst(ConstPoolIdx, &Root,
C->getType(), InsInstrs);
615 Placeholder->setReg(LoadNewConst);
636 if (!(Subtarget.
isPPC64() && Subtarget.hasP9Vector() &&
644 auto GetMBBPressure =
654 if (
MI.isDebugValue() ||
MI.isDebugLabel())
660 RPTracker.
recede(RegOpers);
670 unsigned VSSRCLimit =
TRI->getRegPressureSetLimit(
674 return GetMBBPressure(
MBB)[PPC::RegisterPressureSets::VSSRC] >
680 if (!
I->hasOneMemOperand())
684 return Op->isLoad() &&
Op->getPseudoValue() &&
688Register PPCInstrInfo::generateLoadForNewConst(
696 "Target not supported!\n");
702 Register VReg1 =
MRI->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass);
704 BuildMI(*MF,
MI->getDebugLoc(),
get(PPC::ADDIStocHA8), VReg1)
709 "Only float and double are supported!");
714 LoadOpcode = PPC::DFLOADf32;
716 LoadOpcode = PPC::DFLOADf64;
746 assert(
I->mayLoad() &&
"Should be a load instruction.\n");
747 for (
auto MO :
I->uses()) {
751 if (Reg == 0 || !Reg.isVirtual())
757 return (MCP->
getConstants())[MO2.getIndex()].Val.ConstVal;
764 bool DoRegPressureReduce)
const {
774 DoRegPressureReduce);
787 reassociateFMA(Root,
Pattern, InsInstrs, DelInstrs, InstrIdxForVirtReg);
792 DelInstrs, InstrIdxForVirtReg);
797void PPCInstrInfo::reassociateFMA(
808 MRI.constrainRegClass(RegC, RC);
811 int16_t
Idx = getFMAOpIdxInfo(FmaOp);
812 assert(
Idx >= 0 &&
"Root must be a FMA instruction");
814 bool IsILPReassociate =
834 Leaf =
MRI.getVRegDef(MULReg);
840 Leaf =
MRI.getVRegDef(MULReg);
846 if (IsILPReassociate)
854 MRI.constrainRegClass(Reg, RC);
855 KillFlag = Operand.
isKill();
860 bool &MulOp1KillFlag,
bool &MulOp2KillFlag,
861 bool &AddOpKillFlag) {
862 GetOperandInfo(
Instr.getOperand(FirstMulOpIdx), MulOp1, MulOp1KillFlag);
863 GetOperandInfo(
Instr.getOperand(FirstMulOpIdx + 1), MulOp2, MulOp2KillFlag);
864 GetOperandInfo(
Instr.getOperand(AddOpIdx), AddOp, AddOpKillFlag);
867 Register RegM11, RegM12, RegX, RegY, RegM21, RegM22, RegM31, RegM32, RegA11,
869 bool KillX =
false, KillY =
false, KillM11 =
false, KillM12 =
false,
870 KillM21 =
false, KillM22 =
false, KillM31 =
false, KillM32 =
false,
871 KillA11 =
false, KillA21 =
false, KillB =
false;
873 GetFMAInstrInfo(Root, RegM31, RegM32, RegB, KillM31, KillM32, KillB);
875 if (IsILPReassociate)
876 GetFMAInstrInfo(*Prev, RegM21, RegM22, RegA21, KillM21, KillM22, KillA21);
879 GetFMAInstrInfo(*Leaf, RegM11, RegM12, RegA11, KillM11, KillM12, KillA11);
880 GetOperandInfo(Leaf->
getOperand(AddOpIdx), RegX, KillX);
882 GetOperandInfo(Leaf->
getOperand(1), RegX, KillX);
883 GetOperandInfo(Leaf->
getOperand(2), RegY, KillY);
886 GetOperandInfo(Leaf->
getOperand(1), RegX, KillX);
887 GetOperandInfo(Leaf->
getOperand(2), RegY, KillY);
897 InstrIdxForVirtReg.
insert(std::make_pair(NewVRA, 0));
900 if (IsILPReassociate) {
901 NewVRB =
MRI.createVirtualRegister(RC);
902 InstrIdxForVirtReg.
insert(std::make_pair(NewVRB, 1));
907 NewVRD =
MRI.createVirtualRegister(RC);
908 InstrIdxForVirtReg.
insert(std::make_pair(NewVRD, 2));
913 Register RegMul2,
bool KillRegMul2) {
914 MI->getOperand(AddOpIdx).setReg(RegAdd);
915 MI->getOperand(AddOpIdx).setIsKill(KillAdd);
916 MI->getOperand(FirstMulOpIdx).setReg(RegMul1);
917 MI->getOperand(FirstMulOpIdx).setIsKill(KillRegMul1);
918 MI->getOperand(FirstMulOpIdx + 1).setReg(RegMul2);
919 MI->getOperand(FirstMulOpIdx + 1).setIsKill(KillRegMul2);
940 AdjustOperandOrder(MINewB, RegX, KillX, RegM21, KillM21, RegM22, KillM22);
941 AdjustOperandOrder(MINewA, RegY, KillY, RegM31, KillM31, RegM32, KillM32);
962 assert(NewVRD &&
"new FMA register not created!");
981 AdjustOperandOrder(MINewB, RegX, KillX, RegM21, KillM21, RegM22, KillM22);
982 AdjustOperandOrder(MINewD, NewVRA,
true, RegM31, KillM31, RegM32,
1008 bool KillVarReg =
false;
1011 KillVarReg = KillM31;
1014 KillVarReg = KillM32;
1038 if (!IsILPReassociate) {
1047 "Insertion instructions set should not be empty!");
1051 if (IsILPReassociate)
1059 unsigned &SubIdx)
const {
1060 switch (
MI.getOpcode()) {
1061 default:
return false;
1064 case PPC::EXTSW_32_64:
1065 SrcReg =
MI.getOperand(1).getReg();
1066 DstReg =
MI.getOperand(0).getReg();
1067 SubIdx = PPC::sub_32;
1073 int &FrameIndex)
const {
1077 if (
MI.getOperand(1).isImm() && !
MI.getOperand(1).getImm() &&
1078 MI.getOperand(2).isFI()) {
1079 FrameIndex =
MI.getOperand(2).getIndex();
1080 return MI.getOperand(0).getReg();
1090 switch (
MI.getOpcode()) {
1102 case PPC::ADDIStocHA:
1103 case PPC::ADDIStocHA8:
1105 case PPC::LOAD_STACK_GUARD:
1107 case PPC::XXLXORspz:
1108 case PPC::XXLXORdpz:
1109 case PPC::XXLEQVOnes:
1110 case PPC::XXSPLTI32DX:
1112 case PPC::XXSPLTIDP:
1116 case PPC::V_SETALLONESB:
1117 case PPC::V_SETALLONESH:
1118 case PPC::V_SETALLONES:
1121 case PPC::XXSETACCZ:
1122 case PPC::XXSETACCZW:
1129 int &FrameIndex)
const {
1131 if (
MI.getOperand(1).isImm() && !
MI.getOperand(1).getImm() &&
1132 MI.getOperand(2).isFI()) {
1133 FrameIndex =
MI.getOperand(2).getIndex();
1134 return MI.getOperand(0).getReg();
1142 unsigned OpIdx2)
const {
1146 if (
MI.getOpcode() != PPC::RLWIMI &&
MI.getOpcode() != PPC::RLWIMI_rec)
1154 if (
MI.getOperand(3).getImm() != 0)
1165 assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
1166 "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMI_rec.");
1170 unsigned SubReg1 =
MI.getOperand(1).getSubReg();
1171 unsigned SubReg2 =
MI.getOperand(2).getSubReg();
1172 bool Reg1IsKill =
MI.getOperand(1).isKill();
1173 bool Reg2IsKill =
MI.getOperand(2).isKill();
1174 bool ChangeReg0 =
false;
1180 "Expecting a two-address instruction!");
1181 assert(
MI.getOperand(0).getSubReg() == SubReg1 &&
"Tied subreg mismatch");
1187 unsigned MB =
MI.getOperand(4).getImm();
1188 unsigned ME =
MI.getOperand(5).getImm();
1192 if (MB == 0 && ME == 31)
1197 Register Reg0 = ChangeReg0 ? Reg2 :
MI.getOperand(0).getReg();
1198 bool Reg0IsDead =
MI.getOperand(0).isDead();
1199 return BuildMI(MF,
MI.getDebugLoc(),
MI.getDesc())
1208 MI.getOperand(0).setReg(Reg2);
1209 MI.getOperand(0).setSubReg(SubReg2);
1211 MI.getOperand(2).setReg(Reg1);
1212 MI.getOperand(1).setReg(Reg2);
1213 MI.getOperand(2).setSubReg(SubReg1);
1214 MI.getOperand(1).setSubReg(SubReg2);
1215 MI.getOperand(2).setIsKill(Reg1IsKill);
1216 MI.getOperand(1).setIsKill(Reg2IsKill);
1219 MI.getOperand(4).setImm((ME + 1) & 31);
1220 MI.getOperand(5).setImm((MB - 1) & 31);
1225 unsigned &SrcOpIdx1,
1226 unsigned &SrcOpIdx2)
const {
1237 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
1247 default: Opcode = PPC::NOP;
break;
1273 bool AllowModify)
const {
1274 bool isPPC64 = Subtarget.
isPPC64();
1281 if (!isUnpredicatedTerminator(*
I))
1287 if (
I->getOpcode() == PPC::B &&
1289 I->eraseFromParent();
1293 if (
I ==
MBB.
end() || !isUnpredicatedTerminator(*
I))
1302 if (
I ==
MBB.
begin() || !isUnpredicatedTerminator(*--
I)) {
1308 }
else if (LastInst.
getOpcode() == PPC::BCC) {
1316 }
else if (LastInst.
getOpcode() == PPC::BC) {
1324 }
else if (LastInst.
getOpcode() == PPC::BCn) {
1332 }
else if (LastInst.
getOpcode() == PPC::BDNZ8 ||
1343 }
else if (LastInst.
getOpcode() == PPC::BDZ8 ||
1364 if (
I !=
MBB.
begin() && isUnpredicatedTerminator(*--
I))
1368 if (SecondLastInst.
getOpcode() == PPC::BCC &&
1378 }
else if (SecondLastInst.
getOpcode() == PPC::BC &&
1388 }
else if (SecondLastInst.
getOpcode() == PPC::BCn &&
1398 }
else if ((SecondLastInst.
getOpcode() == PPC::BDNZ8 ||
1399 SecondLastInst.
getOpcode() == PPC::BDNZ) &&
1412 }
else if ((SecondLastInst.
getOpcode() == PPC::BDZ8 ||
1413 SecondLastInst.
getOpcode() == PPC::BDZ) &&
1436 I->eraseFromParent();
1445 int *BytesRemoved)
const {
1446 assert(!BytesRemoved &&
"code size not handled");
1452 if (
I->getOpcode() != PPC::B &&
I->getOpcode() != PPC::BCC &&
1453 I->getOpcode() != PPC::BC &&
I->getOpcode() != PPC::BCn &&
1454 I->getOpcode() != PPC::BDNZ8 &&
I->getOpcode() != PPC::BDNZ &&
1455 I->getOpcode() != PPC::BDZ8 &&
I->getOpcode() != PPC::BDZ)
1459 I->eraseFromParent();
1465 if (
I->getOpcode() != PPC::BCC &&
1466 I->getOpcode() != PPC::BC &&
I->getOpcode() != PPC::BCn &&
1467 I->getOpcode() != PPC::BDNZ8 &&
I->getOpcode() != PPC::BDNZ &&
1468 I->getOpcode() != PPC::BDZ8 &&
I->getOpcode() != PPC::BDZ)
1472 I->eraseFromParent();
1481 int *BytesAdded)
const {
1483 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
1485 "PPC branch conditions have two components!");
1486 assert(!BytesAdded &&
"code size not handled");
1488 bool isPPC64 = Subtarget.
isPPC64();
1496 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1497 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).
addMBB(
TBB);
1513 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1514 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).
addMBB(
TBB);
1532 Register FalseReg,
int &CondCycles,
1533 int &TrueCycles,
int &FalseCycles)
const {
1534 if (
Cond.size() != 2)
1550 RI.getCommonSubClass(
MRI.getRegClass(TrueReg),
MRI.getRegClass(FalseReg));
1555 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
1556 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
1557 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
1558 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
1578 "PPC branch conditions have two components!");
1583 RI.getCommonSubClass(
MRI.getRegClass(TrueReg),
MRI.getRegClass(FalseReg));
1584 assert(RC &&
"TrueReg and FalseReg must have overlapping register classes");
1586 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
1587 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
1589 PPC::GPRCRegClass.hasSubClassEq(RC) ||
1590 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
1591 "isel is for regular integer GPRs only");
1593 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
1596 unsigned SubIdx = 0;
1597 bool SwapOps =
false;
1598 switch (SelectPred) {
1602 SubIdx = PPC::sub_eq; SwapOps =
false;
break;
1606 SubIdx = PPC::sub_eq; SwapOps =
true;
break;
1610 SubIdx = PPC::sub_lt; SwapOps =
false;
break;
1614 SubIdx = PPC::sub_lt; SwapOps =
true;
break;
1618 SubIdx = PPC::sub_gt; SwapOps =
false;
break;
1622 SubIdx = PPC::sub_gt; SwapOps =
true;
break;
1626 SubIdx = PPC::sub_un; SwapOps =
false;
break;
1630 SubIdx = PPC::sub_un; SwapOps =
true;
break;
1635 Register FirstReg = SwapOps ? FalseReg : TrueReg,
1636 SecondReg = SwapOps ? TrueReg : FalseReg;
1641 if (
MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
1642 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
1644 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
1645 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
1647 FirstReg =
MRI.createVirtualRegister(FirstRC);
1659 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
1660 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
1661 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
1662 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
1664 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
1665 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
1666 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
1667 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
1669 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
1670 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
1671 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
1672 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
1674 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
1675 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
1676 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
1677 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
1680 assert(Ret != 4 &&
"Invalid CR bit register");
1691 if (PPC::F8RCRegClass.
contains(DestReg) &&
1692 PPC::VSRCRegClass.
contains(SrcReg)) {
1694 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
1700 }
else if (PPC::F8RCRegClass.
contains(SrcReg) &&
1701 PPC::VSRCRegClass.
contains(DestReg)) {
1703 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
1712 if (PPC::CRBITRCRegClass.
contains(SrcReg) &&
1713 PPC::GPRCRegClass.
contains(DestReg)) {
1725 }
else if (PPC::CRRCRegClass.
contains(SrcReg) &&
1726 (PPC::G8RCRegClass.
contains(DestReg) ||
1727 PPC::GPRCRegClass.
contains(DestReg))) {
1728 bool Is64Bit = PPC::G8RCRegClass.contains(DestReg);
1729 unsigned MvCode = Is64Bit ? PPC::MFOCRF8 : PPC::MFOCRF;
1730 unsigned ShCode = Is64Bit ? PPC::RLWINM8 : PPC::RLWINM;
1731 unsigned CRNum =
TRI->getEncodingValue(SrcReg);
1743 }
else if (PPC::G8RCRegClass.
contains(SrcReg) &&
1744 PPC::VSFRCRegClass.
contains(DestReg)) {
1745 assert(Subtarget.hasDirectMove() &&
1746 "Subtarget doesn't support directmove, don't know how to copy.");
1751 }
else if (PPC::VSFRCRegClass.
contains(SrcReg) &&
1752 PPC::G8RCRegClass.
contains(DestReg)) {
1753 assert(Subtarget.hasDirectMove() &&
1754 "Subtarget doesn't support directmove, don't know how to copy.");
1758 }
else if (PPC::SPERCRegClass.
contains(SrcReg) &&
1759 PPC::GPRCRegClass.
contains(DestReg)) {
1763 }
else if (PPC::GPRCRegClass.
contains(SrcReg) &&
1764 PPC::SPERCRegClass.
contains(DestReg)) {
1771 if (PPC::GPRCRegClass.
contains(DestReg, SrcReg))
1773 else if (PPC::G8RCRegClass.
contains(DestReg, SrcReg))
1775 else if (PPC::F4RCRegClass.
contains(DestReg, SrcReg))
1777 else if (PPC::CRRCRegClass.
contains(DestReg, SrcReg))
1779 else if (PPC::VRRCRegClass.
contains(DestReg, SrcReg))
1781 else if (PPC::VSRCRegClass.
contains(DestReg, SrcReg))
1791 else if (PPC::VSFRCRegClass.
contains(DestReg, SrcReg) ||
1792 PPC::VSSRCRegClass.
contains(DestReg, SrcReg))
1793 Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf;
1794 else if (Subtarget.pairedVectorMemops() &&
1795 PPC::VSRpRCRegClass.contains(DestReg, SrcReg)) {
1796 if (SrcReg > PPC::VSRp15)
1797 SrcReg = PPC::V0 + (SrcReg - PPC::VSRp16) * 2;
1799 SrcReg = PPC::VSL0 + (SrcReg - PPC::VSRp0) * 2;
1800 if (DestReg > PPC::VSRp15)
1801 DestReg = PPC::V0 + (DestReg - PPC::VSRp16) * 2;
1803 DestReg = PPC::VSL0 + (DestReg - PPC::VSRp0) * 2;
1810 else if (PPC::CRBITRCRegClass.
contains(DestReg, SrcReg))
1812 else if (PPC::SPERCRegClass.
contains(DestReg, SrcReg))
1814 else if ((PPC::ACCRCRegClass.
contains(DestReg) ||
1815 PPC::UACCRCRegClass.
contains(DestReg)) &&
1816 (PPC::ACCRCRegClass.
contains(SrcReg) ||
1817 PPC::UACCRCRegClass.
contains(SrcReg))) {
1823 bool DestPrimed = PPC::ACCRCRegClass.contains(DestReg);
1824 bool SrcPrimed = PPC::ACCRCRegClass.contains(SrcReg);
1826 PPC::VSL0 + (SrcReg - (SrcPrimed ? PPC::ACC0 : PPC::UACC0)) * 4;
1828 PPC::VSL0 + (DestReg - (DestPrimed ? PPC::ACC0 : PPC::UACC0)) * 4;
1837 if (SrcPrimed && !KillSrc)
1840 }
else if (PPC::G8pRCRegClass.
contains(DestReg) &&
1841 PPC::G8pRCRegClass.
contains(SrcReg)) {
1843 unsigned DestRegIdx = DestReg - PPC::G8p0;
1844 MCRegister DestRegSub0 = PPC::X0 + 2 * DestRegIdx;
1845 MCRegister DestRegSub1 = PPC::X0 + 2 * DestRegIdx + 1;
1846 unsigned SrcRegIdx = SrcReg - PPC::G8p0;
1847 MCRegister SrcRegSub0 = PPC::X0 + 2 * SrcRegIdx;
1848 MCRegister SrcRegSub1 = PPC::X0 + 2 * SrcRegIdx + 1;
1870 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1871 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1873 }
else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1874 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1876 }
else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1878 }
else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1880 }
else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1882 }
else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1884 }
else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1886 }
else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1888 }
else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1890 }
else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1892 }
else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1894 }
else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1896 }
else if (PPC::ACCRCRegClass.hasSubClassEq(RC)) {
1897 assert(Subtarget.pairedVectorMemops() &&
1898 "Register unexpected when paired memops are disabled.");
1900 }
else if (PPC::UACCRCRegClass.hasSubClassEq(RC)) {
1901 assert(Subtarget.pairedVectorMemops() &&
1902 "Register unexpected when paired memops are disabled.");
1904 }
else if (PPC::WACCRCRegClass.hasSubClassEq(RC)) {
1905 assert(Subtarget.pairedVectorMemops() &&
1906 "Register unexpected when paired memops are disabled.");
1908 }
else if (PPC::VSRpRCRegClass.hasSubClassEq(RC)) {
1909 assert(Subtarget.pairedVectorMemops() &&
1910 "Register unexpected when paired memops are disabled.");
1912 }
else if (PPC::G8pRCRegClass.hasSubClassEq(RC)) {
1923 return OpcodesForSpill[getSpillIndex(RC)];
1929 return OpcodesForSpill[getSpillIndex(RC)];
1932void PPCInstrInfo::StoreRegToStackSlot(
1946 if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1947 PPC::CRBITRCRegClass.hasSubClassEq(RC))
1961 StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1963 for (
unsigned i = 0, e = NewMIs.
size(); i != e; ++i)
1971 NewMIs.
back()->addMemOperand(MF, MMO);
1990 unsigned DestReg,
int FrameIdx,
1999 if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
2000 PPC::CRBITRCRegClass.hasSubClassEq(RC))
2019 LoadRegFromStackSlot(MF,
DL, DestReg, FrameIdx, RC, NewMIs);
2021 for (
unsigned i = 0, e = NewMIs.
size(); i != e; ++i)
2029 NewMIs.
back()->addMemOperand(MF, MMO);
2052 assert(
Cond.size() == 2 &&
"Invalid PPC branch opcode!");
2054 Cond[0].setImm(
Cond[0].getImm() == 0 ? 1 : 0);
2067 unsigned DefOpc =
DefMI.getOpcode();
2068 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
2070 if (!
DefMI.getOperand(1).isImm())
2072 if (
DefMI.getOperand(1).getImm() != 0)
2088 for (UseIdx = 0; UseIdx <
UseMI.getNumOperands(); ++UseIdx)
2089 if (
UseMI.getOperand(UseIdx).isReg() &&
2093 assert(UseIdx <
UseMI.getNumOperands() &&
"Cannot find Reg in UseMI");
2104 if (UseInfo->
RegClass != PPC::GPRC_NOR0RegClassID &&
2105 UseInfo->
RegClass != PPC::G8RC_NOX0RegClassID)
2117 bool isPPC64 = Subtarget.
isPPC64();
2118 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
2120 ZeroReg = UseInfo->
RegClass == PPC::G8RC_NOX0RegClassID ?
2121 PPC::ZERO8 : PPC::ZERO;
2126 UseMI.getOperand(UseIdx).setReg(ZeroReg);
2138 if (
MRI->use_nodbg_empty(Reg))
2139 DefMI.eraseFromParent();
2145 if (
MI.definesRegister(PPC::CTR) ||
MI.definesRegister(PPC::CTR8))
2157 unsigned NumT,
unsigned ExtraT,
2159 unsigned NumF,
unsigned ExtraF,
2182 if (
MI.getOpcode() == PPC::MFFS ||
MI.getOpcode() == PPC::MTFSF)
2189 unsigned OpC =
MI.getOpcode();
2190 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
2191 if (Pred[1].
getReg() == PPC::CTR8 || Pred[1].
getReg() == PPC::CTR) {
2192 bool isPPC64 = Subtarget.
isPPC64();
2193 MI.setDesc(
get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
2194 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
2200 MI.setDesc(
get(PPC::BCLR));
2203 MI.setDesc(
get(PPC::BCLRn));
2206 MI.setDesc(
get(PPC::BCCLR));
2208 .
addImm(Pred[0].getImm())
2213 }
else if (OpC == PPC::B) {
2214 if (Pred[1].
getReg() == PPC::CTR8 || Pred[1].
getReg() == PPC::CTR) {
2215 bool isPPC64 = Subtarget.
isPPC64();
2216 MI.setDesc(
get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
2217 : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
2224 MI.removeOperand(0);
2226 MI.setDesc(
get(PPC::BC));
2232 MI.removeOperand(0);
2234 MI.setDesc(
get(PPC::BCn));
2240 MI.removeOperand(0);
2242 MI.setDesc(
get(PPC::BCC));
2244 .
addImm(Pred[0].getImm())
2250 }
else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL ||
2251 OpC == PPC::BCTRL8 || OpC == PPC::BCTRL_RM ||
2252 OpC == PPC::BCTRL8_RM) {
2253 if (Pred[1].
getReg() == PPC::CTR8 || Pred[1].
getReg() == PPC::CTR)
2256 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8 ||
2257 OpC == PPC::BCTRL_RM || OpC == PPC::BCTRL8_RM;
2258 bool isPPC64 = Subtarget.
isPPC64();
2261 MI.setDesc(
get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
2262 : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
2265 MI.setDesc(
get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
2266 : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
2269 MI.setDesc(
get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
2270 : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
2272 .
addImm(Pred[0].getImm())
2281 if (OpC == PPC::BCTRL_RM || OpC == PPC::BCTRL8_RM)
2293 assert(Pred1.
size() == 2 &&
"Invalid PPC first predicate");
2294 assert(Pred2.
size() == 2 &&
"Invalid PPC second predicate");
2296 if (Pred1[1].
getReg() == PPC::CTR8 || Pred1[1].
getReg() == PPC::CTR)
2298 if (Pred2[1].
getReg() == PPC::CTR8 || Pred2[1].
getReg() == PPC::CTR)
2323 std::vector<MachineOperand> &Pred,
2324 bool SkipDead)
const {
2332 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
2333 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
2337 for (
unsigned c = 0; c < std::size(RCs) && !Found; ++c) {
2340 if (MO.isDef() && RC->
contains(MO.getReg())) {
2344 }
else if (MO.isRegMask()) {
2346 if (MO.clobbersPhysReg(R)) {
2359 int64_t &
Value)
const {
2360 unsigned Opc =
MI.getOpcode();
2363 default:
return false;
2368 SrcReg =
MI.getOperand(1).getReg();
2370 Value =
MI.getOperand(2).getImm();
2379 SrcReg =
MI.getOperand(1).getReg();
2380 SrcReg2 =
MI.getOperand(2).getReg();
2399 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
2411 bool isPPC64 = Subtarget.
isPPC64();
2412 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
2413 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
2414 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
2423 if (!
MI)
return false;
2425 bool equalityOnly =
false;
2428 if (is32BitSignedCompare) {
2434 }
else if (is32BitUnsignedCompare) {
2439 equalityOnly =
true;
2443 equalityOnly = is64BitUnsignedCompare;
2445 equalityOnly = is32BitUnsignedCompare;
2451 I =
MRI->use_instr_begin(CRReg), IE =
MRI->use_instr_end();
2463 if (SubIdx != PPC::sub_eq)
2475 bool FoundUse =
false;
2477 J =
MRI->use_instr_begin(CRReg), JE =
MRI->use_instr_end();
2504 else if (
Value != 0) {
2513 if (equalityOnly || !
MRI->hasOneUse(CRReg))
2523 int16_t Immed = (int16_t)
Value;
2557 for (;
I !=
E && !noSub; --
I) {
2559 unsigned IOpC = Instr.getOpcode();
2561 if (&*
I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0,
TRI) ||
2562 Instr.readsRegister(PPC::CR0,
TRI)))
2571 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
2572 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
2573 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
2574 ((Instr.getOperand(1).getReg() == SrcReg &&
2575 Instr.getOperand(2).getReg() == SrcReg2) ||
2576 (Instr.getOperand(1).getReg() == SrcReg2 &&
2577 Instr.getOperand(2).getReg() == SrcReg))) {
2595 int MIOpC =
MI->getOpcode();
2596 if (MIOpC == PPC::ANDI_rec || MIOpC == PPC::ANDI8_rec ||
2597 MIOpC == PPC::ANDIS_rec || MIOpC == PPC::ANDIS8_rec)
2600 NewOpC = PPC::getRecordFormOpcode(MIOpC);
2618 if (!equalityOnly && (NewOpC == PPC::SUBF_rec || NewOpC == PPC::SUBF8_rec) &&
2628 bool ShouldSwap =
false;
2629 if (Sub &&
Value == 0) {
2635 ShouldSwap = !ShouldSwap;
2640 I =
MRI->use_instr_begin(CRReg), IE =
MRI->use_instr_end();
2648 "Invalid predicate for equality-only optimization");
2655 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
2656 "Invalid CR bit for equality-only optimization");
2658 if (NewSubReg == PPC::sub_lt)
2659 NewSubReg = PPC::sub_gt;
2660 else if (NewSubReg == PPC::sub_gt)
2661 NewSubReg = PPC::sub_lt;
2669 "Non-zero immediate support and ShouldSwap"
2670 "may conflict in updating predicate");
2678 BuildMI(*
MI->getParent(), std::next(MII),
MI->getDebugLoc(),
2679 get(TargetOpcode::COPY), CRReg)
2684 MI->clearRegisterDeads(PPC::CR0);
2686 if (MIOpC != NewOpC) {
2696 if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) {
2697 Register GPRRes =
MI->getOperand(0).getReg();
2698 int64_t SH =
MI->getOperand(2).getImm();
2699 int64_t MB =
MI->getOperand(3).getImm();
2700 int64_t ME =
MI->getOperand(4).getImm();
2703 bool MBInLoHWord = MB >= 16;
2704 bool MEInLoHWord = ME >= 16;
2707 if (MB <= ME && MBInLoHWord == MEInLoHWord && SH == 0) {
2708 Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2710 Mask >>= MBInLoHWord ? 0 : 16;
2711 NewOpC = MIOpC == PPC::RLWINM
2712 ? (MBInLoHWord ? PPC::ANDI_rec : PPC::ANDIS_rec)
2713 : (MBInLoHWord ? PPC::ANDI8_rec : PPC::ANDIS8_rec);
2714 }
else if (
MRI->use_empty(GPRRes) && (ME == 31) &&
2715 (ME - MB + 1 == SH) && (MB >= 16)) {
2719 Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
2721 NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDIS_rec : PPC::ANDIS8_rec;
2724 if (Mask != ~0LLU) {
2725 MI->removeOperand(4);
2726 MI->removeOperand(3);
2727 MI->getOperand(2).setImm(Mask);
2728 NumRcRotatesConvertedToRcAnd++;
2730 }
else if (MIOpC == PPC::RLDICL &&
MI->getOperand(2).getImm() == 0) {
2731 int64_t MB =
MI->getOperand(3).getImm();
2733 uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2734 NewOpC = PPC::ANDI8_rec;
2735 MI->removeOperand(3);
2736 MI->getOperand(2).setImm(Mask);
2737 NumRcRotatesConvertedToRcAnd++;
2742 MI->setDesc(NewDesc);
2745 if (!
MI->definesRegister(ImpDef)) {
2746 MI->addOperand(*
MI->getParent()->getParent(),
2751 if (!
MI->readsRegister(ImpUse)) {
2752 MI->addOperand(*
MI->getParent()->getParent(),
2757 assert(
MI->definesRegister(PPC::CR0) &&
2758 "Record-form instruction does not define cr0?");
2763 for (
unsigned i = 0, e = PredsToUpdate.
size(); i < e; i++)
2764 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
2766 for (
unsigned i = 0, e = SubRegsToUpdate.
size(); i < e; i++)
2767 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
2778 int64_t CmpMask, CmpValue;
2783 if (CmpValue || !CmpMask || SrcReg2)
2791 if (Opc == PPC::CMPLWI || Opc == PPC::CMPLDI)
2798 if (Subtarget.
isPPC64() && Opc == PPC::CMPWI)
2805 bool SrcRegHasOtherUse =
false;
2812 if (CRReg != PPC::CR0)
2816 bool SeenUseOfCRReg =
false;
2817 bool IsCRRegKilled =
false;
2818 if (!isRegElgibleForForwarding(RegMO, *SrcMI, CmpMI,
false, IsCRRegKilled,
2824 int NewOpC = PPC::getRecordFormOpcode(SrcMIOpc);
2838 "Record-form instruction does not define cr0?");
2849 int64_t &
Offset,
bool &OffsetIsScalable,
unsigned &Width,
2852 OffsetIsScalable =
false;
2887 case PPC::DFSTOREf64:
2888 return FirstOpc == SecondOpc;
2894 return SecondOpc == PPC::STW || SecondOpc == PPC::STW8;
2901 unsigned NumBytes)
const {
2907 "Only base registers and frame indices are supported.");
2925 unsigned FirstOpc = FirstLdSt.
getOpcode();
2926 unsigned SecondOpc = SecondLdSt.
getOpcode();
2938 int64_t Offset1 = 0, Offset2 = 0;
2939 unsigned Width1 = 0, Width2 = 0;
2946 assert(Base1 == &BaseOp1 && Base2 == &BaseOp2 &&
2947 "getMemOperandWithOffsetWidth return incorrect base op");
2949 assert(Offset1 <= Offset2 &&
"Caller should have ordered offsets.");
2950 return Offset1 + Width1 == Offset2;
2957 unsigned Opcode =
MI.getOpcode();
2959 if (Opcode == PPC::INLINEASM || Opcode == PPC::INLINEASM_BR) {
2961 const char *AsmStr =
MI.getOperand(0).getSymbolName();
2963 }
else if (Opcode == TargetOpcode::STACKMAP) {
2966 }
else if (Opcode == TargetOpcode::PATCHPOINT) {
2970 return get(Opcode).getSize();
2974std::pair<unsigned, unsigned>
2977 return std::make_pair(TF & Mask, TF & ~Mask);
2982 using namespace PPCII;
2983 static const std::pair<unsigned, const char *> TargetFlags[] = {
2986 {MO_TPREL_LO,
"ppc-tprel-lo"},
2987 {MO_TPREL_HA,
"ppc-tprel-ha"},
2988 {MO_DTPREL_LO,
"ppc-dtprel-lo"},
2989 {MO_TLSLD_LO,
"ppc-tlsld-lo"},
2990 {MO_TOC_LO,
"ppc-toc-lo"},
2991 {MO_TLS,
"ppc-tls"}};
2997 using namespace PPCII;
2998 static const std::pair<unsigned, const char *> TargetFlags[] = {
2999 {MO_PLT,
"ppc-plt"},
3000 {MO_PIC_FLAG,
"ppc-pic"},
3001 {MO_PCREL_FLAG,
"ppc-pcrel"},
3002 {MO_GOT_FLAG,
"ppc-got"},
3003 {MO_PCREL_OPT_FLAG,
"ppc-opt-pcrel"},
3004 {MO_TLSGD_FLAG,
"ppc-tlsgd"},
3005 {MO_TLSLD_FLAG,
"ppc-tlsld"},
3006 {MO_TPREL_FLAG,
"ppc-tprel"},
3007 {MO_TLSGDM_FLAG,
"ppc-tlsgdm"},
3008 {MO_GOT_TLSGD_PCREL_FLAG,
"ppc-got-tlsgd-pcrel"},
3009 {MO_GOT_TLSLD_PCREL_FLAG,
"ppc-got-tlsld-pcrel"},
3010 {MO_GOT_TPREL_PCREL_FLAG,
"ppc-got-tprel-pcrel"}};
3021 unsigned UpperOpcode, LowerOpcode;
3022 switch (
MI.getOpcode()) {
3023 case PPC::DFLOADf32:
3024 UpperOpcode = PPC::LXSSP;
3025 LowerOpcode = PPC::LFS;
3027 case PPC::DFLOADf64:
3028 UpperOpcode = PPC::LXSD;
3029 LowerOpcode = PPC::LFD;
3031 case PPC::DFSTOREf32:
3032 UpperOpcode = PPC::STXSSP;
3033 LowerOpcode = PPC::STFS;
3035 case PPC::DFSTOREf64:
3036 UpperOpcode = PPC::STXSD;
3037 LowerOpcode = PPC::STFD;
3039 case PPC::XFLOADf32:
3040 UpperOpcode = PPC::LXSSPX;
3041 LowerOpcode = PPC::LFSX;
3043 case PPC::XFLOADf64:
3044 UpperOpcode = PPC::LXSDX;
3045 LowerOpcode = PPC::LFDX;
3047 case PPC::XFSTOREf32:
3048 UpperOpcode = PPC::STXSSPX;
3049 LowerOpcode = PPC::STFSX;
3051 case PPC::XFSTOREf64:
3052 UpperOpcode = PPC::STXSDX;
3053 LowerOpcode = PPC::STFDX;
3056 UpperOpcode = PPC::LXSIWAX;
3057 LowerOpcode = PPC::LFIWAX;
3060 UpperOpcode = PPC::LXSIWZX;
3061 LowerOpcode = PPC::LFIWZX;
3064 UpperOpcode = PPC::STXSIWX;
3065 LowerOpcode = PPC::STFIWX;
3071 Register TargetReg =
MI.getOperand(0).getReg();
3073 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
3074 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
3075 Opcode = LowerOpcode;
3077 Opcode = UpperOpcode;
3078 MI.setDesc(
get(Opcode));
3087 auto &
MBB = *
MI.getParent();
3088 auto DL =
MI.getDebugLoc();
3090 switch (
MI.getOpcode()) {
3091 case PPC::BUILD_UACC: {
3094 if (ACC - PPC::ACC0 != UACC - PPC::UACC0) {
3095 MCRegister SrcVSR = PPC::VSL0 + (UACC - PPC::UACC0) * 4;
3096 MCRegister DstVSR = PPC::VSL0 + (ACC - PPC::ACC0) * 4;
3100 for (
int VecNo = 0; VecNo < 4; VecNo++)
3102 .addReg(SrcVSR + VecNo)
3110 case PPC::KILL_PAIR: {
3111 MI.setDesc(
get(PPC::UNENCODED_NOP));
3112 MI.removeOperand(1);
3113 MI.removeOperand(0);
3116 case TargetOpcode::LOAD_STACK_GUARD: {
3118 "Only Linux target is expected to contain LOAD_STACK_GUARD");
3119 const int64_t
Offset = Subtarget.
isPPC64() ? -0x7010 : -0x7008;
3120 const unsigned Reg = Subtarget.
isPPC64() ? PPC::X13 : PPC::R2;
3121 MI.setDesc(
get(Subtarget.
isPPC64() ? PPC::LD : PPC::LWZ));
3127 case PPC::DFLOADf32:
3128 case PPC::DFLOADf64:
3129 case PPC::DFSTOREf32:
3130 case PPC::DFSTOREf64: {
3131 assert(Subtarget.hasP9Vector() &&
3132 "Invalid D-Form Pseudo-ops on Pre-P9 target.");
3135 "D-form op must have register and immediate operands");
3138 case PPC::XFLOADf32:
3139 case PPC::XFSTOREf32:
3143 assert(Subtarget.hasP8Vector() &&
3144 "Invalid X-Form Pseudo-ops on Pre-P8 target.");
3145 assert(
MI.getOperand(2).isReg() &&
MI.getOperand(1).isReg() &&
3146 "X-form op must have register and register operands");
3149 case PPC::XFLOADf64:
3150 case PPC::XFSTOREf64: {
3151 assert(Subtarget.hasVSX() &&
3152 "Invalid X-Form Pseudo-ops on target that has no VSX.");
3153 assert(
MI.getOperand(2).isReg() &&
MI.getOperand(1).isReg() &&
3154 "X-form op must have register and register operands");
3157 case PPC::SPILLTOVSR_LD: {
3158 Register TargetReg =
MI.getOperand(0).getReg();
3159 if (PPC::VSFRCRegClass.
contains(TargetReg)) {
3160 MI.setDesc(
get(PPC::DFLOADf64));
3164 MI.setDesc(
get(PPC::LD));
3167 case PPC::SPILLTOVSR_ST: {
3169 if (PPC::VSFRCRegClass.
contains(SrcReg)) {
3170 NumStoreSPILLVSRRCAsVec++;
3171 MI.setDesc(
get(PPC::DFSTOREf64));
3174 NumStoreSPILLVSRRCAsGpr++;
3175 MI.setDesc(
get(PPC::STD));
3179 case PPC::SPILLTOVSR_LDX: {
3180 Register TargetReg =
MI.getOperand(0).getReg();
3181 if (PPC::VSFRCRegClass.
contains(TargetReg))
3182 MI.setDesc(
get(PPC::LXSDX));
3184 MI.setDesc(
get(PPC::LDX));
3187 case PPC::SPILLTOVSR_STX: {
3189 if (PPC::VSFRCRegClass.
contains(SrcReg)) {
3190 NumStoreSPILLVSRRCAsVec++;
3191 MI.setDesc(
get(PPC::STXSDX));
3193 NumStoreSPILLVSRRCAsGpr++;
3194 MI.setDesc(
get(PPC::STDX));
3200 case PPC::CFENCE8: {
3201 auto Val =
MI.getOperand(0).getReg();
3207 MI.setDesc(
get(PPC::ISYNC));
3208 MI.removeOperand(0);
3219static unsigned selectReg(int64_t Imm1, int64_t Imm2,
unsigned CompareOpc,
3220 unsigned TrueReg,
unsigned FalseReg,
3221 unsigned CRSubReg) {
3223 if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
3227 return Imm1 < Imm2 ? TrueReg : FalseReg;
3229 return Imm1 > Imm2 ? TrueReg : FalseReg;
3231 return Imm1 == Imm2 ? TrueReg : FalseReg;
3235 else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
3243 return Imm1 == Imm2 ? TrueReg : FalseReg;
3246 return PPC::NoRegister;
3251 int64_t Imm)
const {
3252 assert(
MI.getOperand(OpNo).isReg() &&
"Operand must be a REG");
3254 Register InUseReg =
MI.getOperand(OpNo).getReg();
3255 MI.getOperand(OpNo).ChangeToImmediate(Imm);
3263 int UseOpIdx =
MI.findRegisterUseOperandIdx(InUseReg,
false,
TRI);
3264 if (UseOpIdx >= 0) {
3274 MI.removeOperand(UseOpIdx);
3283 int OperandToKeep = LII.
SetCR ? 1 : 0;
3284 for (
int i =
MI.getNumOperands() - 1; i > OperandToKeep; i--)
3285 MI.removeOperand(i);
3289 MI.setDesc(
get(LII.
Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec));
3304 bool &SeenIntermediateUse)
const {
3305 assert(!
MI.getParent()->getParent()->getRegInfo().isSSA() &&
3306 "Should be called after register allocation.");
3310 SeenIntermediateUse =
false;
3311 for (; It !=
E; ++It) {
3312 if (It->modifiesRegister(Reg,
TRI))
3314 if (It->readsRegister(Reg,
TRI))
3315 SeenIntermediateUse =
true;
3323 int64_t Imm)
const {
3325 "Register should be in non-SSA form after RA");
3326 bool isPPC64 = Subtarget.
isPPC64();
3330 if (isInt<16>(Imm)) {
3332 }
else if (isInt<32>(Imm)) {
3340 assert(isPPC64 &&
"Materializing 64-bit immediate to single register is "
3341 "only supported in PPC64");
3343 if ((Imm >> 32) & 0xFFFF)
3346 .
addImm((Imm >> 32) & 0xFFFF);
3353 .
addImm((Imm >> 16) & 0xFFFF);
3363 unsigned &OpNoForForwarding,
3364 bool &SeenIntermediateUse)
const {
3365 OpNoForForwarding = ~0U;
3373 for (
int i = 1, e =
MI.getNumOperands(); i < e; i++) {
3374 if (!
MI.getOperand(i).isReg())
3377 if (!Reg.isVirtual())
3382 if (DefMIForTrueReg->
getOpcode() == PPC::LI ||
3383 DefMIForTrueReg->
getOpcode() == PPC::LI8 ||
3384 DefMIForTrueReg->
getOpcode() == PPC::ADDI ||
3385 DefMIForTrueReg->
getOpcode() == PPC::ADDI8) {
3386 OpNoForForwarding = i;
3387 DefMI = DefMIForTrueReg;
3402 unsigned Opc =
MI.getOpcode();
3403 bool ConvertibleImmForm =
3404 Opc == PPC::CMPWI || Opc == PPC::CMPLWI || Opc == PPC::CMPDI ||
3405 Opc == PPC::CMPLDI || Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
3406 Opc == PPC::ORI || Opc == PPC::ORI8 || Opc == PPC::XORI ||
3407 Opc == PPC::XORI8 || Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec ||
3408 Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
3409 Opc == PPC::RLWINM || Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8 ||
3410 Opc == PPC::RLWINM8_rec;
3411 bool IsVFReg = (
MI.getNumOperands() &&
MI.getOperand(0).isReg())
3418 if ((Opc == PPC::OR || Opc == PPC::OR8) &&
3419 MI.getOperand(1).getReg() ==
MI.getOperand(2).getReg())
3421 for (
int i = 1, e =
MI.getNumOperands(); i <
e; i++) {
3423 SeenIntermediateUse =
false;
3440 OpNoForForwarding = i;
3447 return OpNoForForwarding == ~0
U ? nullptr :
DefMI;
3450unsigned PPCInstrInfo::getSpillTarget()
const {
3453 bool IsP10Variant = Subtarget.isISA3_1() || Subtarget.pairedVectorMemops();
3454 return Subtarget.isISAFuture() ? 3 : IsP10Variant ?
3455 2 : Subtarget.hasP9Vector() ?
3494 bool PostRA = !
MRI->isSSA();
3500 unsigned ToBeDeletedReg = 0;
3501 int64_t OffsetImm = 0;
3502 unsigned XFormOpcode = 0;
3510 bool OtherIntermediateUse =
false;
3514 if (OtherIntermediateUse || !ADDMI)
3521 unsigned ScaleRegIdx = 0;
3522 int64_t OffsetAddi = 0;
3536 assert(ADDIMI &&
"There should be ADDIMI for valid ToBeChangedReg.");
3541 for (
auto It = ++Start; It !=
End; It++)
3550 (ScaleReg == PPC::R0 || ScaleReg == PPC::X0))
3555 if (NewDefFor(ToBeChangedReg, *ADDMI,
MI) || NewDefFor(ScaleReg, *ADDMI,
MI))
3571 MI.setDesc(
get(XFormOpcode));
3573 .ChangeToRegister(ScaleReg,
false,
false,
3577 .ChangeToRegister(ToBeChangedReg,
false,
false,
true);
3589 int64_t &Imm)
const {
3593 if (Opc != PPC::ADDI && Opc != PPC::ADDI8)
3609 return Opc == PPC::ADD4 || Opc == PPC::ADD8;
3613 unsigned &ToBeDeletedReg,
3614 unsigned &XFormOpcode,
3618 if (!
MI.mayLoadOrStore())
3621 unsigned Opc =
MI.getOpcode();
3626 if (XFormOpcode == PPC::INSTRUCTION_LIST_END)
3640 if (!ImmOperand.
isImm())
3643 assert(RegOperand.
isReg() &&
"Instruction format is not right");
3646 if (!RegOperand.
isKill())
3649 ToBeDeletedReg = RegOperand.
getReg();
3650 OffsetImm = ImmOperand.
getImm();
3657 int64_t &OffsetAddi,
3658 int64_t OffsetImm)
const {
3665 bool OtherIntermediateUse =
false;
3686 if (OtherIntermediateUse || !ADDIMI)
3692 if (isInt<16>(OffsetAddi + OffsetImm))
3705 bool PostRA = !
MRI->isSSA();
3706 bool SeenIntermediateUse =
true;
3707 unsigned ForwardingOperand = ~0U;
3709 SeenIntermediateUse);
3712 assert(ForwardingOperand <
MI.getNumOperands() &&
3713 "The forwarding operand needs to be valid at this point");
3714 bool IsForwardingOperandKilled =
MI.getOperand(ForwardingOperand).isKill();
3715 bool KillFwdDefMI = !SeenIntermediateUse && IsForwardingOperandKilled;
3716 if (KilledDef && KillFwdDefMI)
3731 PPC::INSTRUCTION_LIST_END &&
3732 transformToNewImmFormFedByAdd(
MI, *
DefMI, ForwardingOperand))
3736 bool IsVFReg =
MI.getOperand(0).isReg()
3744 transformToImmFormFedByAdd(
MI, III, ForwardingOperand, *
DefMI,
3751 transformToImmFormFedByLI(
MI, III, ForwardingOperand, *
DefMI))
3756 if (!HasImmForm && simplifyToLI(
MI, *
DefMI, ForwardingOperand, KilledDef))
3765 Register FoldingReg =
MI.getOperand(1).getReg();
3769 if (SrcMI->
getOpcode() != PPC::RLWINM &&
3770 SrcMI->
getOpcode() != PPC::RLWINM_rec &&
3774 assert((
MI.getOperand(2).isImm() &&
MI.getOperand(3).isImm() &&
3777 "Invalid PPC::RLWINM Instruction!");
3785 assert((MEMI < 32 && MESrc < 32 && MBMI < 32 && MBSrc < 32) &&
3786 "Invalid PPC::RLWINM Instruction!");
3808 bool SrcMaskFull = (MBSrc - MESrc == 1) || (MBSrc == 0 && MESrc == 31);
3811 if ((MBMI > MEMI) && !SrcMaskFull)
3821 APInt RotatedSrcMask = MaskSrc.
rotl(SHMI);
3822 APInt FinalMask = RotatedSrcMask & MaskMI;
3824 bool Simplified =
false;
3827 if (FinalMask.
isZero()) {
3829 (
MI.getOpcode() == PPC::RLWINM8 ||
MI.getOpcode() == PPC::RLWINM8_rec);
3834 if (
MI.getOpcode() == PPC::RLWINM ||
MI.getOpcode() == PPC::RLWINM8) {
3836 MI.removeOperand(4);
3837 MI.removeOperand(3);
3838 MI.removeOperand(2);
3839 MI.getOperand(1).ChangeToImmediate(0);
3840 MI.setDesc(
get(Is64Bit ? PPC::LI8 : PPC::LI));
3843 MI.removeOperand(4);
3844 MI.removeOperand(3);
3845 MI.getOperand(2).setImm(0);
3846 MI.setDesc(
get(Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec));
3849 MI.getOperand(1).setIsKill(
true);
3853 MI.getOperand(1).setIsKill(
false);
3869 uint16_t NewSH = (SHSrc + SHMI) % 32;
3870 MI.getOperand(2).setImm(NewSH);
3873 MI.getOperand(3).setImm(NewMB);
3874 MI.getOperand(4).setImm(NewME);
3878 MI.getOperand(1).setIsKill(
true);
3882 MI.getOperand(1).setIsKill(
false);
3887 if (Simplified &
MRI->use_nodbg_empty(FoldingReg) &&
3912 default:
return false;
3920 III.
ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
3929 III.
ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
3945 III.
ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
3953 III.
ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
3961 III.
ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
3981 case PPC::OR: III.
ImmOpcode = PPC::ORI;
break;
3982 case PPC::OR8: III.
ImmOpcode = PPC::ORI8;
break;
3983 case PPC::XOR: III.
ImmOpcode = PPC::XORI;
break;
3984 case PPC::XOR8: III.
ImmOpcode = PPC::XORI8;
break;
3989 case PPC::RLWNM_rec:
3990 case PPC::RLWNM8_rec:
4010 if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 || Opc == PPC::RLWNM_rec ||
4011 Opc == PPC::RLWNM8_rec)
4017 case PPC::RLWNM: III.
ImmOpcode = PPC::RLWINM;
break;
4018 case PPC::RLWNM8: III.
ImmOpcode = PPC::RLWINM8;
break;
4019 case PPC::RLWNM_rec:
4022 case PPC::RLWNM8_rec:
4025 case PPC::SLW: III.
ImmOpcode = PPC::RLWINM;
break;
4026 case PPC::SLW8: III.
ImmOpcode = PPC::RLWINM8;
break;
4033 case PPC::SRW: III.
ImmOpcode = PPC::RLWINM;
break;
4034 case PPC::SRW8: III.
ImmOpcode = PPC::RLWINM8;
break;
4054 case PPC::RLDCL_rec:
4056 case PPC::RLDCR_rec:
4072 if (Opc == PPC::RLDCL || Opc == PPC::RLDCL_rec || Opc == PPC::RLDCR ||
4073 Opc == PPC::RLDCR_rec)
4079 case PPC::RLDCL: III.
ImmOpcode = PPC::RLDICL;
break;
4080 case PPC::RLDCL_rec:
4083 case PPC::RLDCR: III.
ImmOpcode = PPC::RLDICR;
break;
4084 case PPC::RLDCR_rec:
4087 case PPC::SLD: III.
ImmOpcode = PPC::RLDICR;
break;
4091 case PPC::SRD: III.
ImmOpcode = PPC::RLDICL;
break;
4138 case PPC::LBZX: III.
ImmOpcode = PPC::LBZ;
break;
4139 case PPC::LBZX8: III.
ImmOpcode = PPC::LBZ8;
break;
4140 case PPC::LHZX: III.
ImmOpcode = PPC::LHZ;
break;
4141 case PPC::LHZX8: III.
ImmOpcode = PPC::LHZ8;
break;
4142 case PPC::LHAX: III.
ImmOpcode = PPC::LHA;
break;
4143 case PPC::LHAX8: III.
ImmOpcode = PPC::LHA8;
break;
4144 case PPC::LWZX: III.
ImmOpcode = PPC::LWZ;
break;
4145 case PPC::LWZX8: III.
ImmOpcode = PPC::LWZ8;
break;
4151 case PPC::LFSX: III.
ImmOpcode = PPC::LFS;
break;
4152 case PPC::LFDX: III.
ImmOpcode = PPC::LFD;
break;
4153 case PPC::STBX: III.
ImmOpcode = PPC::STB;
break;
4154 case PPC::STBX8: III.
ImmOpcode = PPC::STB8;
break;
4155 case PPC::STHX: III.
ImmOpcode = PPC::STH;
break;
4156 case PPC::STHX8: III.
ImmOpcode = PPC::STH8;
break;
4157 case PPC::STWX: III.
ImmOpcode = PPC::STW;
break;
4158 case PPC::STWX8: III.
ImmOpcode = PPC::STW8;
break;
4163 case PPC::STFSX: III.
ImmOpcode = PPC::STFS;
break;
4164 case PPC::STFDX: III.
ImmOpcode = PPC::STFD;
break;
4196 case PPC::LBZUX: III.
ImmOpcode = PPC::LBZU;
break;
4197 case PPC::LBZUX8: III.
ImmOpcode = PPC::LBZU8;
break;
4198 case PPC::LHZUX: III.
ImmOpcode = PPC::LHZU;
break;
4199 case PPC::LHZUX8: III.
ImmOpcode = PPC::LHZU8;
break;
4200 case PPC::LHAUX: III.
ImmOpcode = PPC::LHAU;
break;
4201 case PPC::LHAUX8: III.
ImmOpcode = PPC::LHAU8;
break;
4202 case PPC::LWZUX: III.
ImmOpcode = PPC::LWZU;
break;
4203 case PPC::LWZUX8: III.
ImmOpcode = PPC::LWZU8;
break;
4208 case PPC::LFSUX: III.
ImmOpcode = PPC::LFSU;
break;
4209 case PPC::LFDUX: III.
ImmOpcode = PPC::LFDU;
break;
4210 case PPC::STBUX: III.
ImmOpcode = PPC::STBU;
break;
4211 case PPC::STBUX8: III.
ImmOpcode = PPC::STBU8;
break;
4212 case PPC::STHUX: III.
ImmOpcode = PPC::STHU;
break;
4213 case PPC::STHUX8: III.
ImmOpcode = PPC::STHU8;
break;
4214 case PPC::STWUX: III.
ImmOpcode = PPC::STWU;
break;
4215 case PPC::STWUX8: III.
ImmOpcode = PPC::STWU8;
break;
4220 case PPC::STFSUX: III.
ImmOpcode = PPC::STFSU;
break;
4221 case PPC::STFDUX: III.
ImmOpcode = PPC::STFDU;
break;
4234 case PPC::XFLOADf32:
4235 case PPC::XFLOADf64:
4236 case PPC::XFSTOREf32:
4237 case PPC::XFSTOREf64:
4238 if (!Subtarget.hasP9Vector())
4265 case PPC::XFLOADf32:
4279 case PPC::XFLOADf64:
4297 case PPC::XFSTOREf32:
4311 case PPC::XFSTOREf64:
4322 assert(Op1 != Op2 &&
"Cannot swap operand with itself.");
4324 unsigned MaxOp = std::max(Op1, Op2);
4325 unsigned MinOp = std::min(Op1, Op2);
4328 MI.removeOperand(std::max(Op1, Op2));
4329 MI.removeOperand(std::min(Op1, Op2));
4333 if (MaxOp - MinOp == 1 &&
MI.getNumOperands() == MinOp) {
4334 MI.addOperand(MOp2);
4335 MI.addOperand(MOp1);
4340 unsigned TotalOps =
MI.getNumOperands() + 2;
4341 for (
unsigned i =
MI.getNumOperands() - 1; i >= MinOp; i--) {
4343 MI.removeOperand(i);
4346 MI.addOperand(MOp2);
4348 for (
unsigned i =
MI.getNumOperands(); i < TotalOps; i++) {
4350 MI.addOperand(MOp1);
4352 MI.addOperand(MOps.
back());
4363 unsigned OpNoForForwarding
4403 unsigned Opc =
DefMI.getOpcode();
4404 if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8)
4408 "Add inst must have at least three operands");
4409 RegMO = &
DefMI.getOperand(1);
4410 ImmMO = &
DefMI.getOperand(2);
4413 if (!RegMO->
isReg())
4422bool PPCInstrInfo::isRegElgibleForForwarding(
4425 bool &IsFwdFeederRegKilled,
bool &SeenIntermediateUse)
const {
4442 for (; It !=
E; ++It) {
4446 IsFwdFeederRegKilled =
true;
4448 SeenIntermediateUse =
true;
4450 if ((&*It) == &
DefMI)
4463bool PPCInstrInfo::isImmElgibleForForwarding(
const MachineOperand &ImmMO,
4467 int64_t BaseImm)
const {
4469 if (
DefMI.getOpcode() == PPC::ADDItocL) {
4490 if (ImmMO.
isImm()) {
4495 APInt ActualValue(64, ImmMO.
getImm() + BaseImm,
true);
4500 Imm = SignExtend64<16>(ImmMO.
getImm() + BaseImm);
4516 unsigned OpNoForForwarding,
4518 if ((
DefMI.getOpcode() != PPC::LI &&
DefMI.getOpcode() != PPC::LI8) ||
4519 !
DefMI.getOperand(1).isImm())
4524 bool PostRA = !
MRI->isSSA();
4526 int64_t Immediate =
DefMI.getOperand(1).getImm();
4528 int64_t SExtImm = SignExtend64<16>(Immediate);
4530 bool ReplaceWithLI =
false;
4531 bool Is64BitLI =
false;
4534 unsigned Opc =
MI.getOpcode();
4555 bool Changed =
false;
4557 int64_t Comparand =
MI.getOperand(2).getImm();
4558 int64_t SExtComparand = ((
uint64_t)Comparand & ~0x7FFFuLL) != 0
4559 ? (Comparand | 0xFFFFFFFFFFFF0000)
4562 for (
auto &CompareUseMI :
MRI->use_instructions(DefReg)) {
4563 unsigned UseOpc = CompareUseMI.getOpcode();
4564 if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
4566 unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
4567 Register TrueReg = CompareUseMI.getOperand(1).getReg();
4568 Register FalseReg = CompareUseMI.getOperand(2).getReg();
4569 unsigned RegToCopy =
4570 selectReg(SExtImm, SExtComparand, Opc, TrueReg, FalseReg, CRSubReg);
4571 if (RegToCopy == PPC::NoRegister)
4574 if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
4575 CompareUseMI.setDesc(
get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
4577 CompareUseMI.removeOperand(3);
4578 CompareUseMI.removeOperand(2);
4582 dbgs() <<
"Found LI -> CMPI -> ISEL, replacing with a copy.\n");
4586 CompareUseMI.setDesc(
get(PPC::COPY));
4587 CompareUseMI.removeOperand(3);
4588 CompareUseMI.removeOperand(RegToCopy == TrueReg ? 2 : 1);
4589 CmpIselsConverted++;
4598 MissedConvertibleImmediateInstrs++;
4606 int64_t Addend =
MI.getOperand(2).getImm();
4607 if (isInt<16>(Addend + SExtImm)) {
4608 ReplaceWithLI =
true;
4609 Is64BitLI = Opc == PPC::ADDI8;
4610 NewImm = Addend + SExtImm;
4616 case PPC::SUBFIC8: {
4618 if (
MI.getNumOperands() > 3 && !
MI.getOperand(3).isDead())
4620 int64_t Minuend =
MI.getOperand(2).getImm();
4621 if (isInt<16>(Minuend - SExtImm)) {
4622 ReplaceWithLI =
true;
4623 Is64BitLI = Opc == PPC::SUBFIC8;
4624 NewImm = Minuend - SExtImm;
4630 case PPC::RLDICL_rec:
4631 case PPC::RLDICL_32:
4632 case PPC::RLDICL_32_64: {
4634 int64_t SH =
MI.getOperand(2).getImm();
4635 int64_t MB =
MI.getOperand(3).getImm();
4636 APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec) ? 64 : 32,
4638 InVal = InVal.rotl(SH);
4644 if (isUInt<15>(InVal.getSExtValue()) ||
4645 (Opc == PPC::RLDICL_rec && isUInt<16>(InVal.getSExtValue()))) {
4646 ReplaceWithLI =
true;
4647 Is64BitLI = Opc != PPC::RLDICL_32;
4648 NewImm = InVal.getSExtValue();
4649 SetCR = Opc == PPC::RLDICL_rec;
4656 case PPC::RLWINM_rec:
4657 case PPC::RLWINM8_rec: {
4658 int64_t SH =
MI.getOperand(2).getImm();
4659 int64_t MB =
MI.getOperand(3).getImm();
4660 int64_t ME =
MI.getOperand(4).getImm();
4661 APInt InVal(32, SExtImm,
true);
4662 InVal = InVal.rotl(SH);
4668 bool ValueFits = isUInt<15>(InVal.getSExtValue());
4669 ValueFits |= ((Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec) &&
4670 isUInt<16>(InVal.getSExtValue()));
4672 ReplaceWithLI =
true;
4673 Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8_rec;
4674 NewImm = InVal.getSExtValue();
4675 SetCR = Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec;
4684 int64_t LogicalImm =
MI.getOperand(2).getImm();
4686 if (Opc == PPC::ORI || Opc == PPC::ORI8)
4687 Result = LogicalImm | SExtImm;
4689 Result = LogicalImm ^ SExtImm;
4690 if (isInt<16>(Result)) {
4691 ReplaceWithLI =
true;
4692 Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
4700 if (ReplaceWithLI) {
4705 bool ImmChanged = (SExtImm & NewImm) != NewImm;
4706 if (PostRA && ImmChanged)
4713 DefMI.getOperand(1).setImm(NewImm);
4717 else if (
MRI->use_empty(