LLVM  16.0.0git
RegisterClassInfo.h
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1 //===- RegisterClassInfo.h - Dynamic Register Class Info --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RegisterClassInfo class which provides dynamic
10 // information about target register classes. Callee saved and reserved
11 // registers depends on calling conventions and other dynamic information, so
12 // some things cannot be determined statically.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
17 #define LLVM_CODEGEN_REGISTERCLASSINFO_H
18 
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/MC/MCRegister.h"
24 #include <cstdint>
25 #include <memory>
26 
27 namespace llvm {
28 
30  struct RCInfo {
31  unsigned Tag = 0;
32  unsigned NumRegs = 0;
33  bool ProperSubClass = false;
34  uint8_t MinCost = 0;
35  uint16_t LastCostChange = 0;
36  std::unique_ptr<MCPhysReg[]> Order;
37 
38  RCInfo() = default;
39 
40  operator ArrayRef<MCPhysReg>() const {
41  return makeArrayRef(Order.get(), NumRegs);
42  }
43  };
44 
45  // Brief cached information for each register class.
46  std::unique_ptr<RCInfo[]> RegClass;
47 
48  // Tag changes whenever cached information needs to be recomputed. An RCInfo
49  // entry is valid when its tag matches.
50  unsigned Tag = 0;
51 
52  const MachineFunction *MF = nullptr;
53  const TargetRegisterInfo *TRI = nullptr;
54 
55  // Callee saved registers of last MF.
56  // Used only to determine if an update for CalleeSavedAliases is necessary.
57  SmallVector<MCPhysReg, 16> LastCalleeSavedRegs;
58 
59  // Map register alias to the callee saved Register.
60  SmallVector<MCPhysReg, 4> CalleeSavedAliases;
61 
62  // Indicate if a specified callee saved register be in the allocation order
63  // exactly as written in the tablegen descriptions or listed later.
64  BitVector IgnoreCSRForAllocOrder;
65 
66  // Reserved registers in the current MF.
67  BitVector Reserved;
68 
69  std::unique_ptr<unsigned[]> PSetLimits;
70 
71  // The register cost values.
72  ArrayRef<uint8_t> RegCosts;
73 
74  // Compute all information about RC.
75  void compute(const TargetRegisterClass *RC) const;
76 
77  // Return an up-to-date RCInfo for RC.
78  const RCInfo &get(const TargetRegisterClass *RC) const {
79  const RCInfo &RCI = RegClass[RC->getID()];
80  if (Tag != RCI.Tag)
81  compute(RC);
82  return RCI;
83  }
84 
85 public:
87 
88  /// runOnFunction - Prepare to answer questions about MF. This must be called
89  /// before any other methods are used.
90  void runOnMachineFunction(const MachineFunction &MF);
91 
92  /// getNumAllocatableRegs - Returns the number of actually allocatable
93  /// registers in RC in the current function.
94  unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
95  return get(RC).NumRegs;
96  }
97 
98  /// getOrder - Returns the preferred allocation order for RC. The order
99  /// contains no reserved registers, and registers that alias callee saved
100  /// registers come last.
102  return get(RC);
103  }
104 
105  /// isProperSubClass - Returns true if RC has a legal super-class with more
106  /// allocatable registers.
107  ///
108  /// Register classes like GR32_NOSP are not proper sub-classes because %esp
109  /// is not allocatable. Similarly, tGPR is not a proper sub-class in Thumb
110  /// mode because the GPR super-class is not legal.
111  bool isProperSubClass(const TargetRegisterClass *RC) const {
112  return get(RC).ProperSubClass;
113  }
114 
115  /// getLastCalleeSavedAlias - Returns the last callee saved register that
116  /// overlaps PhysReg, or NoRegister if Reg doesn't overlap a
117  /// CalleeSavedAliases.
119  if (PhysReg.id() < CalleeSavedAliases.size())
120  return CalleeSavedAliases[PhysReg];
121  return MCRegister::NoRegister;
122  }
123 
124  /// Get the minimum register cost in RC's allocation order.
125  /// This is the smallest value in RegCosts[Reg] for all
126  /// the registers in getOrder(RC).
127  uint8_t getMinCost(const TargetRegisterClass *RC) const {
128  return get(RC).MinCost;
129  }
130 
131  /// Get the position of the last cost change in getOrder(RC).
132  ///
133  /// All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the
134  /// same cost according to RegCosts[Reg].
135  unsigned getLastCostChange(const TargetRegisterClass *RC) const {
136  return get(RC).LastCostChange;
137  }
138 
139  /// Get the register unit limit for the given pressure set index.
140  ///
141  /// RegisterClassInfo adjusts this limit for reserved registers.
142  unsigned getRegPressureSetLimit(unsigned Idx) const {
143  if (!PSetLimits[Idx])
144  PSetLimits[Idx] = computePSetLimit(Idx);
145  return PSetLimits[Idx];
146  }
147 
148 protected:
149  unsigned computePSetLimit(unsigned Idx) const;
150 };
151 
152 } // end namespace llvm
153 
154 #endif // LLVM_CODEGEN_REGISTERCLASSINFO_H
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:75
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::RegisterClassInfo::getOrder
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
Definition: RegisterClassInfo.h:101
llvm::RegisterClassInfo::getLastCostChange
unsigned getLastCostChange(const TargetRegisterClass *RC) const
Get the position of the last cost change in getOrder(RC).
Definition: RegisterClassInfo.h:135
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::MCRegister::NoRegister
static constexpr unsigned NoRegister
Definition: MCRegister.h:43
llvm::dwarf::Tag
Tag
Definition: Dwarf.h:105
llvm::RegisterClassInfo::RegisterClassInfo
RegisterClassInfo()
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
BitVector.h
llvm::BitVector
Definition: BitVector.h:75
llvm::RegisterClassInfo::getMinCost
uint8_t getMinCost(const TargetRegisterClass *RC) const
Get the minimum register cost in RC's allocation order.
Definition: RegisterClassInfo.h:127
MCRegister.h
llvm::RegisterClassInfo::isProperSubClass
bool isProperSubClass(const TargetRegisterClass *RC) const
isProperSubClass - Returns true if RC has a legal super-class with more allocatable registers.
Definition: RegisterClassInfo.h:111
llvm::RegisterClassInfo::getNumAllocatableRegs
unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const
getNumAllocatableRegs - Returns the number of actually allocatable registers in RC in the current fun...
Definition: RegisterClassInfo.h:94
llvm::RegisterClassInfo::runOnMachineFunction
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
Definition: RegisterClassInfo.cpp:42
ArrayRef.h
llvm::RegisterClassInfo
Definition: RegisterClassInfo.h:29
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MCRegister::id
unsigned id() const
Definition: MCRegister.h:72
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::RegisterClassInfo::getRegPressureSetLimit
unsigned getRegPressureSetLimit(unsigned Idx) const
Get the register unit limit for the given pressure set index.
Definition: RegisterClassInfo.h:142
uint16_t
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::RegisterClassInfo::getLastCalleeSavedAlias
MCRegister getLastCalleeSavedAlias(MCRegister PhysReg) const
getLastCalleeSavedAlias - Returns the last callee saved register that overlaps PhysReg,...
Definition: RegisterClassInfo.h:118
llvm::RegisterClassInfo::computePSetLimit
unsigned computePSetLimit(unsigned Idx) const
This is not accurate because two overlapping register sets may have some nonoverlapping reserved regi...
Definition: RegisterClassInfo.cpp:204
SmallVector.h
TargetRegisterInfo.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24