LLVM  14.0.0git
AMDGPUBaseInfo.cpp
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1 //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AMDGPUBaseInfo.h"
10 #include "AMDGPU.h"
11 #include "AMDGPUAsmUtils.h"
12 #include "AMDKernelCodeT.h"
13 #include "GCNSubtarget.h"
15 #include "llvm/BinaryFormat/ELF.h"
16 #include "llvm/IR/Attributes.h"
17 #include "llvm/IR/Function.h"
18 #include "llvm/IR/GlobalValue.h"
19 #include "llvm/IR/IntrinsicsAMDGPU.h"
20 #include "llvm/IR/IntrinsicsR600.h"
21 #include "llvm/IR/LLVMContext.h"
26 
27 #define GET_INSTRINFO_NAMED_OPS
28 #define GET_INSTRMAP_INFO
29 #include "AMDGPUGenInstrInfo.inc"
30 
32  "amdhsa-code-object-version", llvm::cl::Hidden,
33  llvm::cl::desc("AMDHSA Code Object Version"), llvm::cl::init(4),
35 
36 namespace {
37 
38 /// \returns Bit mask for given bit \p Shift and bit \p Width.
39 unsigned getBitMask(unsigned Shift, unsigned Width) {
40  return ((1 << Width) - 1) << Shift;
41 }
42 
43 /// Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
44 ///
45 /// \returns Packed \p Dst.
46 unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
47  Dst &= ~(1 << Shift) & ~getBitMask(Shift, Width);
48  Dst |= (Src << Shift) & getBitMask(Shift, Width);
49  return Dst;
50 }
51 
52 /// Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
53 ///
54 /// \returns Unpacked bits.
55 unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
56  return (Src & getBitMask(Shift, Width)) >> Shift;
57 }
58 
59 /// \returns Vmcnt bit shift (lower bits).
60 unsigned getVmcntBitShiftLo() { return 0; }
61 
62 /// \returns Vmcnt bit width (lower bits).
63 unsigned getVmcntBitWidthLo() { return 4; }
64 
65 /// \returns Expcnt bit shift.
66 unsigned getExpcntBitShift() { return 4; }
67 
68 /// \returns Expcnt bit width.
69 unsigned getExpcntBitWidth() { return 3; }
70 
71 /// \returns Lgkmcnt bit shift.
72 unsigned getLgkmcntBitShift() { return 8; }
73 
74 /// \returns Lgkmcnt bit width.
75 unsigned getLgkmcntBitWidth(unsigned VersionMajor) {
76  return (VersionMajor >= 10) ? 6 : 4;
77 }
78 
79 /// \returns Vmcnt bit shift (higher bits).
80 unsigned getVmcntBitShiftHi() { return 14; }
81 
82 /// \returns Vmcnt bit width (higher bits).
83 unsigned getVmcntBitWidthHi() { return 2; }
84 
85 } // end namespace anonymous
86 
87 namespace llvm {
88 
89 namespace AMDGPU {
90 
92  if (STI && STI->getTargetTriple().getOS() != Triple::AMDHSA)
93  return None;
94 
95  switch (AmdhsaCodeObjectVersion) {
96  case 2:
98  case 3:
100  case 4:
102  default:
103  report_fatal_error(Twine("Unsupported AMDHSA Code Object Version ") +
105  }
106 }
107 
109  if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI))
110  return *HsaAbiVer == ELF::ELFABIVERSION_AMDGPU_HSA_V2;
111  return false;
112 }
113 
115  if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI))
116  return *HsaAbiVer == ELF::ELFABIVERSION_AMDGPU_HSA_V3;
117  return false;
118 }
119 
121  if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI))
122  return *HsaAbiVer == ELF::ELFABIVERSION_AMDGPU_HSA_V4;
123  return false;
124 }
125 
127  return isHsaAbiVersion3(STI) || isHsaAbiVersion4(STI);
128 }
129 
130 #define GET_MIMGBaseOpcodesTable_IMPL
131 #define GET_MIMGDimInfoTable_IMPL
132 #define GET_MIMGInfoTable_IMPL
133 #define GET_MIMGLZMappingTable_IMPL
134 #define GET_MIMGMIPMappingTable_IMPL
135 #define GET_MIMGG16MappingTable_IMPL
136 #include "AMDGPUGenSearchableTables.inc"
137 
138 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
139  unsigned VDataDwords, unsigned VAddrDwords) {
140  const MIMGInfo *Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding,
141  VDataDwords, VAddrDwords);
142  return Info ? Info->Opcode : -1;
143 }
144 
145 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc) {
146  const MIMGInfo *Info = getMIMGInfo(Opc);
147  return Info ? getMIMGBaseOpcodeInfo(Info->BaseOpcode) : nullptr;
148 }
149 
150 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels) {
151  const MIMGInfo *OrigInfo = getMIMGInfo(Opc);
152  const MIMGInfo *NewInfo =
153  getMIMGOpcodeHelper(OrigInfo->BaseOpcode, OrigInfo->MIMGEncoding,
154  NewChannels, OrigInfo->VAddrDwords);
155  return NewInfo ? NewInfo->Opcode : -1;
156 }
157 
158 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
159  const MIMGDimInfo *Dim, bool IsA16,
160  bool IsG16Supported) {
161  unsigned AddrWords = BaseOpcode->NumExtraArgs;
162  unsigned AddrComponents = (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
163  (BaseOpcode->LodOrClampOrMip ? 1 : 0);
164  if (IsA16)
165  AddrWords += divideCeil(AddrComponents, 2);
166  else
167  AddrWords += AddrComponents;
168 
169  // Note: For subtargets that support A16 but not G16, enabling A16 also
170  // enables 16 bit gradients.
171  // For subtargets that support A16 (operand) and G16 (done with a different
172  // instruction encoding), they are independent.
173 
174  if (BaseOpcode->Gradients) {
175  if ((IsA16 && !IsG16Supported) || BaseOpcode->G16)
176  // There are two gradients per coordinate, we pack them separately.
177  // For the 3d case,
178  // we get (dy/du, dx/du) (-, dz/du) (dy/dv, dx/dv) (-, dz/dv)
179  AddrWords += alignTo<2>(Dim->NumGradients / 2);
180  else
181  AddrWords += Dim->NumGradients;
182  }
183  return AddrWords;
184 }
185 
186 struct MUBUFInfo {
189  uint8_t elements;
190  bool has_vaddr;
191  bool has_srsrc;
194 };
195 
196 struct MTBUFInfo {
199  uint8_t elements;
200  bool has_vaddr;
201  bool has_srsrc;
203 };
204 
205 struct SMInfo {
207  bool IsBuffer;
208 };
209 
210 struct VOPInfo {
212  bool IsSingle;
213 };
214 
215 #define GET_MTBUFInfoTable_DECL
216 #define GET_MTBUFInfoTable_IMPL
217 #define GET_MUBUFInfoTable_DECL
218 #define GET_MUBUFInfoTable_IMPL
219 #define GET_SMInfoTable_DECL
220 #define GET_SMInfoTable_IMPL
221 #define GET_VOP1InfoTable_DECL
222 #define GET_VOP1InfoTable_IMPL
223 #define GET_VOP2InfoTable_DECL
224 #define GET_VOP2InfoTable_IMPL
225 #define GET_VOP3InfoTable_DECL
226 #define GET_VOP3InfoTable_IMPL
227 #include "AMDGPUGenSearchableTables.inc"
228 
229 int getMTBUFBaseOpcode(unsigned Opc) {
230  const MTBUFInfo *Info = getMTBUFInfoFromOpcode(Opc);
231  return Info ? Info->BaseOpcode : -1;
232 }
233 
234 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements) {
235  const MTBUFInfo *Info = getMTBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
236  return Info ? Info->Opcode : -1;
237 }
238 
239 int getMTBUFElements(unsigned Opc) {
240  const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
241  return Info ? Info->elements : 0;
242 }
243 
244 bool getMTBUFHasVAddr(unsigned Opc) {
245  const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
246  return Info ? Info->has_vaddr : false;
247 }
248 
249 bool getMTBUFHasSrsrc(unsigned Opc) {
250  const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
251  return Info ? Info->has_srsrc : false;
252 }
253 
254 bool getMTBUFHasSoffset(unsigned Opc) {
255  const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
256  return Info ? Info->has_soffset : false;
257 }
258 
259 int getMUBUFBaseOpcode(unsigned Opc) {
260  const MUBUFInfo *Info = getMUBUFInfoFromOpcode(Opc);
261  return Info ? Info->BaseOpcode : -1;
262 }
263 
264 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements) {
265  const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
266  return Info ? Info->Opcode : -1;
267 }
268 
269 int getMUBUFElements(unsigned Opc) {
270  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
271  return Info ? Info->elements : 0;
272 }
273 
274 bool getMUBUFHasVAddr(unsigned Opc) {
275  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
276  return Info ? Info->has_vaddr : false;
277 }
278 
279 bool getMUBUFHasSrsrc(unsigned Opc) {
280  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
281  return Info ? Info->has_srsrc : false;
282 }
283 
284 bool getMUBUFHasSoffset(unsigned Opc) {
285  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
286  return Info ? Info->has_soffset : false;
287 }
288 
289 bool getMUBUFIsBufferInv(unsigned Opc) {
290  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
291  return Info ? Info->IsBufferInv : false;
292 }
293 
294 bool getSMEMIsBuffer(unsigned Opc) {
295  const SMInfo *Info = getSMEMOpcodeHelper(Opc);
296  return Info ? Info->IsBuffer : false;
297 }
298 
299 bool getVOP1IsSingle(unsigned Opc) {
300  const VOPInfo *Info = getVOP1OpcodeHelper(Opc);
301  return Info ? Info->IsSingle : false;
302 }
303 
304 bool getVOP2IsSingle(unsigned Opc) {
305  const VOPInfo *Info = getVOP2OpcodeHelper(Opc);
306  return Info ? Info->IsSingle : false;
307 }
308 
309 bool getVOP3IsSingle(unsigned Opc) {
310  const VOPInfo *Info = getVOP3OpcodeHelper(Opc);
311  return Info ? Info->IsSingle : false;
312 }
313 
314 // Wrapper for Tablegen'd function. enum Subtarget is not defined in any
315 // header files, so we need to wrap it in a function that takes unsigned
316 // instead.
317 int getMCOpcode(uint16_t Opcode, unsigned Gen) {
318  return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
319 }
320 
321 namespace IsaInfo {
322 
324  : STI(STI), XnackSetting(TargetIDSetting::Any),
325  SramEccSetting(TargetIDSetting::Any) {
326  if (!STI.getFeatureBits().test(FeatureSupportsXNACK))
327  XnackSetting = TargetIDSetting::Unsupported;
328  if (!STI.getFeatureBits().test(FeatureSupportsSRAMECC))
329  SramEccSetting = TargetIDSetting::Unsupported;
330 }
331 
333  // Check if xnack or sramecc is explicitly enabled or disabled. In the
334  // absence of the target features we assume we must generate code that can run
335  // in any environment.
336  SubtargetFeatures Features(FS);
337  Optional<bool> XnackRequested;
338  Optional<bool> SramEccRequested;
339 
340  for (const std::string &Feature : Features.getFeatures()) {
341  if (Feature == "+xnack")
342  XnackRequested = true;
343  else if (Feature == "-xnack")
344  XnackRequested = false;
345  else if (Feature == "+sramecc")
346  SramEccRequested = true;
347  else if (Feature == "-sramecc")
348  SramEccRequested = false;
349  }
350 
351  bool XnackSupported = isXnackSupported();
352  bool SramEccSupported = isSramEccSupported();
353 
354  if (XnackRequested) {
355  if (XnackSupported) {
356  XnackSetting =
357  *XnackRequested ? TargetIDSetting::On : TargetIDSetting::Off;
358  } else {
359  // If a specific xnack setting was requested and this GPU does not support
360  // xnack emit a warning. Setting will remain set to "Unsupported".
361  if (*XnackRequested) {
362  errs() << "warning: xnack 'On' was requested for a processor that does "
363  "not support it!\n";
364  } else {
365  errs() << "warning: xnack 'Off' was requested for a processor that "
366  "does not support it!\n";
367  }
368  }
369  }
370 
371  if (SramEccRequested) {
372  if (SramEccSupported) {
373  SramEccSetting =
374  *SramEccRequested ? TargetIDSetting::On : TargetIDSetting::Off;
375  } else {
376  // If a specific sramecc setting was requested and this GPU does not
377  // support sramecc emit a warning. Setting will remain set to
378  // "Unsupported".
379  if (*SramEccRequested) {
380  errs() << "warning: sramecc 'On' was requested for a processor that "
381  "does not support it!\n";
382  } else {
383  errs() << "warning: sramecc 'Off' was requested for a processor that "
384  "does not support it!\n";
385  }
386  }
387  }
388 }
389 
390 static TargetIDSetting
392  if (FeatureString.endswith("-"))
393  return TargetIDSetting::Off;
394  if (FeatureString.endswith("+"))
395  return TargetIDSetting::On;
396 
397  llvm_unreachable("Malformed feature string");
398 }
399 
401  SmallVector<StringRef, 3> TargetIDSplit;
402  TargetID.split(TargetIDSplit, ':');
403 
404  for (const auto &FeatureString : TargetIDSplit) {
405  if (FeatureString.startswith("xnack"))
406  XnackSetting = getTargetIDSettingFromFeatureString(FeatureString);
407  if (FeatureString.startswith("sramecc"))
408  SramEccSetting = getTargetIDSettingFromFeatureString(FeatureString);
409  }
410 }
411 
412 std::string AMDGPUTargetID::toString() const {
413  std::string StringRep = "";
414  raw_string_ostream StreamRep(StringRep);
415 
416  auto TargetTriple = STI.getTargetTriple();
417  auto Version = getIsaVersion(STI.getCPU());
418 
419  StreamRep << TargetTriple.getArchName() << '-'
420  << TargetTriple.getVendorName() << '-'
421  << TargetTriple.getOSName() << '-'
422  << TargetTriple.getEnvironmentName() << '-';
423 
424  std::string Processor = "";
425  // TODO: Following else statement is present here because we used various
426  // alias names for GPUs up until GFX9 (e.g. 'fiji' is same as 'gfx803').
427  // Remove once all aliases are removed from GCNProcessors.td.
428  if (Version.Major >= 9)
429  Processor = STI.getCPU().str();
430  else
431  Processor = (Twine("gfx") + Twine(Version.Major) + Twine(Version.Minor) +
432  Twine(Version.Stepping))
433  .str();
434 
435  std::string Features = "";
436  if (Optional<uint8_t> HsaAbiVersion = getHsaAbiVersion(&STI)) {
437  switch (*HsaAbiVersion) {
439  // Code object V2 only supported specific processors and had fixed
440  // settings for the XNACK.
441  if (Processor == "gfx600") {
442  } else if (Processor == "gfx601") {
443  } else if (Processor == "gfx602") {
444  } else if (Processor == "gfx700") {
445  } else if (Processor == "gfx701") {
446  } else if (Processor == "gfx702") {
447  } else if (Processor == "gfx703") {
448  } else if (Processor == "gfx704") {
449  } else if (Processor == "gfx705") {
450  } else if (Processor == "gfx801") {
451  if (!isXnackOnOrAny())
453  "AMD GPU code object V2 does not support processor " +
454  Twine(Processor) + " without XNACK");
455  } else if (Processor == "gfx802") {
456  } else if (Processor == "gfx803") {
457  } else if (Processor == "gfx805") {
458  } else if (Processor == "gfx810") {
459  if (!isXnackOnOrAny())
461  "AMD GPU code object V2 does not support processor " +
462  Twine(Processor) + " without XNACK");
463  } else if (Processor == "gfx900") {
464  if (isXnackOnOrAny())
465  Processor = "gfx901";
466  } else if (Processor == "gfx902") {
467  if (isXnackOnOrAny())
468  Processor = "gfx903";
469  } else if (Processor == "gfx904") {
470  if (isXnackOnOrAny())
471  Processor = "gfx905";
472  } else if (Processor == "gfx906") {
473  if (isXnackOnOrAny())
474  Processor = "gfx907";
475  } else if (Processor == "gfx90c") {
476  if (isXnackOnOrAny())
478  "AMD GPU code object V2 does not support processor " +
479  Twine(Processor) + " with XNACK being ON or ANY");
480  } else {
482  "AMD GPU code object V2 does not support processor " +
483  Twine(Processor));
484  }
485  break;
487  // xnack.
488  if (isXnackOnOrAny())
489  Features += "+xnack";
490  // In code object v2 and v3, "sramecc" feature was spelled with a
491  // hyphen ("sram-ecc").
492  if (isSramEccOnOrAny())
493  Features += "+sram-ecc";
494  break;
496  // sramecc.
498  Features += ":sramecc-";
500  Features += ":sramecc+";
501  // xnack.
503  Features += ":xnack-";
504  else if (getXnackSetting() == TargetIDSetting::On)
505  Features += ":xnack+";
506  break;
507  default:
508  break;
509  }
510  }
511 
512  StreamRep << Processor << Features;
513 
514  StreamRep.flush();
515  return StringRep;
516 }
517 
518 unsigned getWavefrontSize(const MCSubtargetInfo *STI) {
519  if (STI->getFeatureBits().test(FeatureWavefrontSize16))
520  return 16;
521  if (STI->getFeatureBits().test(FeatureWavefrontSize32))
522  return 32;
523 
524  return 64;
525 }
526 
527 unsigned getLocalMemorySize(const MCSubtargetInfo *STI) {
528  if (STI->getFeatureBits().test(FeatureLocalMemorySize32768))
529  return 32768;
530  if (STI->getFeatureBits().test(FeatureLocalMemorySize65536))
531  return 65536;
532 
533  return 0;
534 }
535 
536 unsigned getEUsPerCU(const MCSubtargetInfo *STI) {
537  // "Per CU" really means "per whatever functional block the waves of a
538  // workgroup must share". For gfx10 in CU mode this is the CU, which contains
539  // two SIMDs.
540  if (isGFX10Plus(*STI) && STI->getFeatureBits().test(FeatureCuMode))
541  return 2;
542  // Pre-gfx10 a CU contains four SIMDs. For gfx10 in WGP mode the WGP contains
543  // two CUs, so a total of four SIMDs.
544  return 4;
545 }
546 
548  unsigned FlatWorkGroupSize) {
549  assert(FlatWorkGroupSize != 0);
550  if (STI->getTargetTriple().getArch() != Triple::amdgcn)
551  return 8;
552  unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize);
553  if (N == 1)
554  return 40;
555  N = 40 / N;
556  return std::min(N, 16u);
557 }
558 
559 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI) {
560  return 1;
561 }
562 
563 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI) {
564  // FIXME: Need to take scratch memory into account.
565  if (isGFX90A(*STI))
566  return 8;
567  if (!isGFX10Plus(*STI))
568  return 10;
569  return hasGFX10_3Insts(*STI) ? 16 : 20;
570 }
571 
573  unsigned FlatWorkGroupSize) {
574  return divideCeil(getWavesPerWorkGroup(STI, FlatWorkGroupSize),
575  getEUsPerCU(STI));
576 }
577 
579  return 1;
580 }
581 
583  // Some subtargets allow encoding 2048, but this isn't tested or supported.
584  return 1024;
585 }
586 
588  unsigned FlatWorkGroupSize) {
589  return divideCeil(FlatWorkGroupSize, getWavefrontSize(STI));
590 }
591 
592 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI) {
594  if (Version.Major >= 10)
595  return getAddressableNumSGPRs(STI);
596  if (Version.Major >= 8)
597  return 16;
598  return 8;
599 }
600 
602  return 8;
603 }
604 
605 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI) {
607  if (Version.Major >= 8)
608  return 800;
609  return 512;
610 }
611 
613  if (STI->getFeatureBits().test(FeatureSGPRInitBug))
615 
617  if (Version.Major >= 10)
618  return 106;
619  if (Version.Major >= 8)
620  return 102;
621  return 104;
622 }
623 
624 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
625  assert(WavesPerEU != 0);
626 
628  if (Version.Major >= 10)
629  return 0;
630 
631  if (WavesPerEU >= getMaxWavesPerEU(STI))
632  return 0;
633 
634  unsigned MinNumSGPRs = getTotalNumSGPRs(STI) / (WavesPerEU + 1);
635  if (STI->getFeatureBits().test(FeatureTrapHandler))
636  MinNumSGPRs -= std::min(MinNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
637  MinNumSGPRs = alignDown(MinNumSGPRs, getSGPRAllocGranule(STI)) + 1;
638  return std::min(MinNumSGPRs, getAddressableNumSGPRs(STI));
639 }
640 
641 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
642  bool Addressable) {
643  assert(WavesPerEU != 0);
644 
645  unsigned AddressableNumSGPRs = getAddressableNumSGPRs(STI);
647  if (Version.Major >= 10)
648  return Addressable ? AddressableNumSGPRs : 108;
649  if (Version.Major >= 8 && !Addressable)
650  AddressableNumSGPRs = 112;
651  unsigned MaxNumSGPRs = getTotalNumSGPRs(STI) / WavesPerEU;
652  if (STI->getFeatureBits().test(FeatureTrapHandler))
653  MaxNumSGPRs -= std::min(MaxNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
654  MaxNumSGPRs = alignDown(MaxNumSGPRs, getSGPRAllocGranule(STI));
655  return std::min(MaxNumSGPRs, AddressableNumSGPRs);
656 }
657 
658 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
659  bool FlatScrUsed, bool XNACKUsed) {
660  unsigned ExtraSGPRs = 0;
661  if (VCCUsed)
662  ExtraSGPRs = 2;
663 
665  if (Version.Major >= 10)
666  return ExtraSGPRs;
667 
668  if (Version.Major < 8) {
669  if (FlatScrUsed)
670  ExtraSGPRs = 4;
671  } else {
672  if (XNACKUsed)
673  ExtraSGPRs = 4;
674 
675  if (FlatScrUsed ||
676  STI->getFeatureBits().test(AMDGPU::FeatureArchitectedFlatScratch))
677  ExtraSGPRs = 6;
678  }
679 
680  return ExtraSGPRs;
681 }
682 
683 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
684  bool FlatScrUsed) {
685  return getNumExtraSGPRs(STI, VCCUsed, FlatScrUsed,
686  STI->getFeatureBits().test(AMDGPU::FeatureXNACK));
687 }
688 
689 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs) {
691  // SGPRBlocks is actual number of SGPR blocks minus 1.
692  return NumSGPRs / getSGPREncodingGranule(STI) - 1;
693 }
694 
696  Optional<bool> EnableWavefrontSize32) {
697  if (STI->getFeatureBits().test(FeatureGFX90AInsts))
698  return 8;
699 
700  bool IsWave32 = EnableWavefrontSize32 ?
701  *EnableWavefrontSize32 :
702  STI->getFeatureBits().test(FeatureWavefrontSize32);
703 
704  if (hasGFX10_3Insts(*STI))
705  return IsWave32 ? 16 : 8;
706 
707  return IsWave32 ? 8 : 4;
708 }
709 
711  Optional<bool> EnableWavefrontSize32) {
712  if (STI->getFeatureBits().test(FeatureGFX90AInsts))
713  return 8;
714 
715  bool IsWave32 = EnableWavefrontSize32 ?
716  *EnableWavefrontSize32 :
717  STI->getFeatureBits().test(FeatureWavefrontSize32);
718 
719  return IsWave32 ? 8 : 4;
720 }
721 
722 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {
723  if (STI->getFeatureBits().test(FeatureGFX90AInsts))
724  return 512;
725  if (!isGFX10Plus(*STI))
726  return 256;
727  return STI->getFeatureBits().test(FeatureWavefrontSize32) ? 1024 : 512;
728 }
729 
731  if (STI->getFeatureBits().test(FeatureGFX90AInsts))
732  return 512;
733  return 256;
734 }
735 
736 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
737  assert(WavesPerEU != 0);
738 
739  if (WavesPerEU >= getMaxWavesPerEU(STI))
740  return 0;
741  unsigned MinNumVGPRs =
742  alignDown(getTotalNumVGPRs(STI) / (WavesPerEU + 1),
743  getVGPRAllocGranule(STI)) + 1;
744  return std::min(MinNumVGPRs, getAddressableNumVGPRs(STI));
745 }
746 
747 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
748  assert(WavesPerEU != 0);
749 
750  unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(STI) / WavesPerEU,
751  getVGPRAllocGranule(STI));
752  unsigned AddressableNumVGPRs = getAddressableNumVGPRs(STI);
753  return std::min(MaxNumVGPRs, AddressableNumVGPRs);
754 }
755 
756 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs,
757  Optional<bool> EnableWavefrontSize32) {
759  getVGPREncodingGranule(STI, EnableWavefrontSize32));
760  // VGPRBlocks is actual number of VGPR blocks minus 1.
761  return NumVGPRs / getVGPREncodingGranule(STI, EnableWavefrontSize32) - 1;
762 }
763 
764 } // end namespace IsaInfo
765 
767  const MCSubtargetInfo *STI) {
769 
770  memset(&Header, 0, sizeof(Header));
771 
774  Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
775  Header.amd_machine_version_major = Version.Major;
776  Header.amd_machine_version_minor = Version.Minor;
777  Header.amd_machine_version_stepping = Version.Stepping;
778  Header.kernel_code_entry_byte_offset = sizeof(Header);
779  Header.wavefront_size = 6;
780 
781  // If the code object does not support indirect functions, then the value must
782  // be 0xffffffff.
783  Header.call_convention = -1;
784 
785  // These alignment values are specified in powers of two, so alignment =
786  // 2^n. The minimum alignment is 2^4 = 16.
787  Header.kernarg_segment_alignment = 4;
788  Header.group_segment_alignment = 4;
789  Header.private_segment_alignment = 4;
790 
791  if (Version.Major >= 10) {
792  if (STI->getFeatureBits().test(FeatureWavefrontSize32)) {
793  Header.wavefront_size = 5;
795  }
797  S_00B848_WGP_MODE(STI->getFeatureBits().test(FeatureCuMode) ? 0 : 1) |
799  }
800 }
801 
803  const MCSubtargetInfo *STI) {
805 
807  memset(&KD, 0, sizeof(KD));
808 
810  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64,
813  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, 1);
815  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE, 1);
817  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, 1);
818  if (Version.Major >= 10) {
820  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
821  STI->getFeatureBits().test(FeatureWavefrontSize32) ? 1 : 0);
823  amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE,
824  STI->getFeatureBits().test(FeatureCuMode) ? 0 : 1);
826  amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED, 1);
827  }
828  if (AMDGPU::isGFX90A(*STI)) {
830  amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT,
831  STI->getFeatureBits().test(FeatureTgSplit) ? 1 : 0);
832  }
833  return KD;
834 }
835 
836 bool isGroupSegment(const GlobalValue *GV) {
838 }
839 
840 bool isGlobalSegment(const GlobalValue *GV) {
842 }
843 
845  unsigned AS = GV->getAddressSpace();
846  return AS == AMDGPUAS::CONSTANT_ADDRESS ||
848 }
849 
851  return TT.getArch() == Triple::r600;
852 }
853 
854 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
855  Attribute A = F.getFnAttribute(Name);
856  int Result = Default;
857 
858  if (A.isStringAttribute()) {
859  StringRef Str = A.getValueAsString();
860  if (Str.getAsInteger(0, Result)) {
861  LLVMContext &Ctx = F.getContext();
862  Ctx.emitError("can't parse integer attribute " + Name);
863  }
864  }
865 
866  return Result;
867 }
868 
869 std::pair<int, int> getIntegerPairAttribute(const Function &F,
870  StringRef Name,
871  std::pair<int, int> Default,
872  bool OnlyFirstRequired) {
873  Attribute A = F.getFnAttribute(Name);
874  if (!A.isStringAttribute())
875  return Default;
876 
877  LLVMContext &Ctx = F.getContext();
878  std::pair<int, int> Ints = Default;
879  std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
880  if (Strs.first.trim().getAsInteger(0, Ints.first)) {
881  Ctx.emitError("can't parse first integer attribute " + Name);
882  return Default;
883  }
884  if (Strs.second.trim().getAsInteger(0, Ints.second)) {
885  if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
886  Ctx.emitError("can't parse second integer attribute " + Name);
887  return Default;
888  }
889  }
890 
891  return Ints;
892 }
893 
895  unsigned VmcntLo = (1 << getVmcntBitWidthLo()) - 1;
896  if (Version.Major < 9)
897  return VmcntLo;
898 
899  unsigned VmcntHi = ((1 << getVmcntBitWidthHi()) - 1) << getVmcntBitWidthLo();
900  return VmcntLo | VmcntHi;
901 }
902 
904  return (1 << getExpcntBitWidth()) - 1;
905 }
906 
908  return (1 << getLgkmcntBitWidth(Version.Major)) - 1;
909 }
910 
912  unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(), getVmcntBitWidthLo());
913  unsigned Expcnt = getBitMask(getExpcntBitShift(), getExpcntBitWidth());
914  unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(),
915  getLgkmcntBitWidth(Version.Major));
916  unsigned Waitcnt = VmcntLo | Expcnt | Lgkmcnt;
917  if (Version.Major < 9)
918  return Waitcnt;
919 
920  unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(), getVmcntBitWidthHi());
921  return Waitcnt | VmcntHi;
922 }
923 
924 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt) {
925  unsigned VmcntLo =
926  unpackBits(Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
927  if (Version.Major < 9)
928  return VmcntLo;
929 
930  unsigned VmcntHi =
931  unpackBits(Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
932  VmcntHi <<= getVmcntBitWidthLo();
933  return VmcntLo | VmcntHi;
934 }
935 
936 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt) {
937  return unpackBits(Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
938 }
939 
940 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt) {
941  return unpackBits(Waitcnt, getLgkmcntBitShift(),
942  getLgkmcntBitWidth(Version.Major));
943 }
944 
945 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
946  unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
947  Vmcnt = decodeVmcnt(Version, Waitcnt);
948  Expcnt = decodeExpcnt(Version, Waitcnt);
949  Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
950 }
951 
952 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded) {
953  Waitcnt Decoded;
954  Decoded.VmCnt = decodeVmcnt(Version, Encoded);
955  Decoded.ExpCnt = decodeExpcnt(Version, Encoded);
956  Decoded.LgkmCnt = decodeLgkmcnt(Version, Encoded);
957  return Decoded;
958 }
959 
960 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
961  unsigned Vmcnt) {
962  Waitcnt =
963  packBits(Vmcnt, Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
964  if (Version.Major < 9)
965  return Waitcnt;
966 
967  Vmcnt >>= getVmcntBitWidthLo();
968  return packBits(Vmcnt, Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
969 }
970 
971 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
972  unsigned Expcnt) {
973  return packBits(Expcnt, Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
974 }
975 
976 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
977  unsigned Lgkmcnt) {
978  return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(),
979  getLgkmcntBitWidth(Version.Major));
980 }
981 
983  unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
984  unsigned Waitcnt = getWaitcntBitMask(Version);
985  Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
986  Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
987  Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
988  return Waitcnt;
989 }
990 
991 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded) {
992  return encodeWaitcnt(Version, Decoded.VmCnt, Decoded.ExpCnt, Decoded.LgkmCnt);
993 }
994 
995 //===----------------------------------------------------------------------===//
996 // hwreg
997 //===----------------------------------------------------------------------===//
998 
999 namespace Hwreg {
1000 
1001 int64_t getHwregId(const StringRef Name) {
1002  for (int Id = ID_SYMBOLIC_FIRST_; Id < ID_SYMBOLIC_LAST_; ++Id) {
1003  if (IdSymbolic[Id] && Name == IdSymbolic[Id])
1004  return Id;
1005  }
1006  return ID_UNKNOWN_;
1007 }
1008 
1009 static unsigned getLastSymbolicHwreg(const MCSubtargetInfo &STI) {
1010  if (isSI(STI) || isCI(STI) || isVI(STI))
1011  return ID_SYMBOLIC_FIRST_GFX9_;
1012  else if (isGFX9(STI))
1013  return ID_SYMBOLIC_FIRST_GFX10_;
1014  else if (isGFX10(STI) && !isGFX10_BEncoding(STI))
1016  else
1017  return ID_SYMBOLIC_LAST_;
1018 }
1019 
1020 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI) {
1021  return
1024 }
1025 
1026 bool isValidHwreg(int64_t Id) {
1027  return 0 <= Id && isUInt<ID_WIDTH_>(Id);
1028 }
1029 
1031  return 0 <= Offset && isUInt<OFFSET_WIDTH_>(Offset);
1032 }
1033 
1034 bool isValidHwregWidth(int64_t Width) {
1035  return 0 <= (Width - 1) && isUInt<WIDTH_M1_WIDTH_>(Width - 1);
1036 }
1037 
1039  return (Id << ID_SHIFT_) |
1040  (Offset << OFFSET_SHIFT_) |
1041  ((Width - 1) << WIDTH_M1_SHIFT_);
1042 }
1043 
1044 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI) {
1045  return isValidHwreg(Id, STI) ? IdSymbolic[Id] : "";
1046 }
1047 
1048 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width) {
1049  Id = (Val & ID_MASK_) >> ID_SHIFT_;
1050  Offset = (Val & OFFSET_MASK_) >> OFFSET_SHIFT_;
1051  Width = ((Val & WIDTH_M1_MASK_) >> WIDTH_M1_SHIFT_) + 1;
1052 }
1053 
1054 } // namespace Hwreg
1055 
1056 //===----------------------------------------------------------------------===//
1057 // exp tgt
1058 //===----------------------------------------------------------------------===//
1059 
1060 namespace Exp {
1061 
1062 struct ExpTgt {
1064  unsigned Tgt;
1065  unsigned MaxIndex;
1066 };
1067 
1068 static constexpr ExpTgt ExpTgtInfo[] = {
1069  {{"null"}, ET_NULL, ET_NULL_MAX_IDX},
1070  {{"mrtz"}, ET_MRTZ, ET_MRTZ_MAX_IDX},
1071  {{"prim"}, ET_PRIM, ET_PRIM_MAX_IDX},
1072  {{"mrt"}, ET_MRT0, ET_MRT_MAX_IDX},
1073  {{"pos"}, ET_POS0, ET_POS_MAX_IDX},
1074  {{"param"}, ET_PARAM0, ET_PARAM_MAX_IDX},
1075 };
1076 
1077 bool getTgtName(unsigned Id, StringRef &Name, int &Index) {
1078  for (const ExpTgt &Val : ExpTgtInfo) {
1079  if (Val.Tgt <= Id && Id <= Val.Tgt + Val.MaxIndex) {
1080  Index = (Val.MaxIndex == 0) ? -1 : (Id - Val.Tgt);
1081  Name = Val.Name;
1082  return true;
1083  }
1084  }
1085  return false;
1086 }
1087 
1088 unsigned getTgtId(const StringRef Name) {
1089 
1090  for (const ExpTgt &Val : ExpTgtInfo) {
1091  if (Val.MaxIndex == 0 && Name == Val.Name)
1092  return Val.Tgt;
1093 
1094  if (Val.MaxIndex > 0 && Name.startswith(Val.Name)) {
1095  StringRef Suffix = Name.drop_front(Val.Name.size());
1096 
1097  unsigned Id;
1098  if (Suffix.getAsInteger(10, Id) || Id > Val.MaxIndex)
1099  return ET_INVALID;
1100 
1101  // Disable leading zeroes
1102  if (Suffix.size() > 1 && Suffix[0] == '0')
1103  return ET_INVALID;
1104 
1105  return Val.Tgt + Id;
1106  }
1107  }
1108  return ET_INVALID;
1109 }
1110 
1111 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI) {
1112  return (Id != ET_POS4 && Id != ET_PRIM) || isGFX10Plus(STI);
1113 }
1114 
1115 } // namespace Exp
1116 
1117 //===----------------------------------------------------------------------===//
1118 // MTBUF Format
1119 //===----------------------------------------------------------------------===//
1120 
1121 namespace MTBUFFormat {
1122 
1123 int64_t getDfmt(const StringRef Name) {
1124  for (int Id = DFMT_MIN; Id <= DFMT_MAX; ++Id) {
1125  if (Name == DfmtSymbolic[Id])
1126  return Id;
1127  }
1128  return DFMT_UNDEF;
1129 }
1130 
1132  assert(Id <= DFMT_MAX);
1133  return DfmtSymbolic[Id];
1134 }
1135 
1137  if (isSI(STI) || isCI(STI))
1138  return NfmtSymbolicSICI;
1139  if (isVI(STI) || isGFX9(STI))
1140  return NfmtSymbolicVI;
1141  return NfmtSymbolicGFX10;
1142 }
1143 
1144 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI) {
1145  auto lookupTable = getNfmtLookupTable(STI);
1146  for (int Id = NFMT_MIN; Id <= NFMT_MAX; ++Id) {
1147  if (Name == lookupTable[Id])
1148  return Id;
1149  }
1150  return NFMT_UNDEF;
1151 }
1152 
1153 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI) {
1154  assert(Id <= NFMT_MAX);
1155  return getNfmtLookupTable(STI)[Id];
1156 }
1157 
1158 bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI) {
1159  unsigned Dfmt;
1160  unsigned Nfmt;
1161  decodeDfmtNfmt(Id, Dfmt, Nfmt);
1162  return isValidNfmt(Nfmt, STI);
1163 }
1164 
1165 bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI) {
1166  return !getNfmtName(Id, STI).empty();
1167 }
1168 
1169 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt) {
1170  return (Dfmt << DFMT_SHIFT) | (Nfmt << NFMT_SHIFT);
1171 }
1172 
1173 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt) {
1174  Dfmt = (Format >> DFMT_SHIFT) & DFMT_MASK;
1175  Nfmt = (Format >> NFMT_SHIFT) & NFMT_MASK;
1176 }
1177 
1179  for (int Id = UFMT_FIRST; Id <= UFMT_LAST; ++Id) {
1180  if (Name == UfmtSymbolic[Id])
1181  return Id;
1182  }
1183  return UFMT_UNDEF;
1184 }
1185 
1187  return isValidUnifiedFormat(Id) ? UfmtSymbolic[Id] : "";
1188 }
1189 
1190 bool isValidUnifiedFormat(unsigned Id) {
1191  return Id <= UFMT_LAST;
1192 }
1193 
1194 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt) {
1195  int64_t Fmt = encodeDfmtNfmt(Dfmt, Nfmt);
1196  for (int Id = UFMT_FIRST; Id <= UFMT_LAST; ++Id) {
1197  if (Fmt == DfmtNfmt2UFmt[Id])
1198  return Id;
1199  }
1200  return UFMT_UNDEF;
1201 }
1202 
1203 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI) {
1204  return isGFX10Plus(STI) ? (Val <= UFMT_MAX) : (Val <= DFMT_NFMT_MAX);
1205 }
1206 
1208  if (isGFX10Plus(STI))
1209  return UFMT_DEFAULT;
1210  return DFMT_NFMT_DEFAULT;
1211 }
1212 
1213 } // namespace MTBUFFormat
1214 
1215 //===----------------------------------------------------------------------===//
1216 // SendMsg
1217 //===----------------------------------------------------------------------===//
1218 
1219 namespace SendMsg {
1220 
1221 int64_t getMsgId(const StringRef Name) {
1222  for (int i = ID_GAPS_FIRST_; i < ID_GAPS_LAST_; ++i) {
1223  if (IdSymbolic[i] && Name == IdSymbolic[i])
1224  return i;
1225  }
1226  return ID_UNKNOWN_;
1227 }
1228 
1229 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict) {
1230  if (Strict) {
1231  switch (MsgId) {
1232  case ID_SAVEWAVE:
1233  return isVI(STI) || isGFX9Plus(STI);
1234  case ID_STALL_WAVE_GEN:
1235  case ID_HALT_WAVES:
1236  case ID_ORDERED_PS_DONE:
1237  case ID_GS_ALLOC_REQ:
1238  case ID_GET_DOORBELL:
1239  return isGFX9Plus(STI);
1240  case ID_EARLY_PRIM_DEALLOC:
1241  return isGFX9(STI);
1242  case ID_GET_DDID:
1243  return isGFX10Plus(STI);
1244  default:
1245  return 0 <= MsgId && MsgId < ID_GAPS_LAST_ && IdSymbolic[MsgId];
1246  }
1247  } else {
1248  return 0 <= MsgId && isUInt<ID_WIDTH_>(MsgId);
1249  }
1250 }
1251 
1252 StringRef getMsgName(int64_t MsgId) {
1253  assert(0 <= MsgId && MsgId < ID_GAPS_LAST_);
1254  return IdSymbolic[MsgId];
1255 }
1256 
1257 int64_t getMsgOpId(int64_t MsgId, const StringRef Name) {
1258  const char* const *S = (MsgId == ID_SYSMSG) ? OpSysSymbolic : OpGsSymbolic;
1259  const int F = (MsgId == ID_SYSMSG) ? OP_SYS_FIRST_ : OP_GS_FIRST_;
1260  const int L = (MsgId == ID_SYSMSG) ? OP_SYS_LAST_ : OP_GS_LAST_;
1261  for (int i = F; i < L; ++i) {
1262  if (Name == S[i]) {
1263  return i;
1264  }
1265  }
1266  return OP_UNKNOWN_;
1267 }
1268 
1269 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1270  bool Strict) {
1271  assert(isValidMsgId(MsgId, STI, Strict));
1272 
1273  if (!Strict)
1274  return 0 <= OpId && isUInt<OP_WIDTH_>(OpId);
1275 
1276  switch(MsgId)
1277  {
1278  case ID_GS:
1279  return (OP_GS_FIRST_ <= OpId && OpId < OP_GS_LAST_) && OpId != OP_GS_NOP;
1280  case ID_GS_DONE:
1281  return OP_GS_FIRST_ <= OpId && OpId < OP_GS_LAST_;
1282  case ID_SYSMSG:
1283  return OP_SYS_FIRST_ <= OpId && OpId < OP_SYS_LAST_;
1284  default:
1285  return OpId == OP_NONE_;
1286  }
1287 }
1288 
1289 StringRef getMsgOpName(int64_t MsgId, int64_t OpId) {
1290  assert(msgRequiresOp(MsgId));
1291  return (MsgId == ID_SYSMSG)? OpSysSymbolic[OpId] : OpGsSymbolic[OpId];
1292 }
1293 
1294 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
1295  const MCSubtargetInfo &STI, bool Strict) {
1296  assert(isValidMsgOp(MsgId, OpId, STI, Strict));
1297 
1298  if (!Strict)
1299  return 0 <= StreamId && isUInt<STREAM_ID_WIDTH_>(StreamId);
1300 
1301  switch(MsgId)
1302  {
1303  case ID_GS:
1305  case ID_GS_DONE:
1306  return (OpId == OP_GS_NOP)?
1307  (StreamId == STREAM_ID_NONE_) :
1309  default:
1310  return StreamId == STREAM_ID_NONE_;
1311  }
1312 }
1313 
1314 bool msgRequiresOp(int64_t MsgId) {
1315  return MsgId == ID_GS || MsgId == ID_GS_DONE || MsgId == ID_SYSMSG;
1316 }
1317 
1318 bool msgSupportsStream(int64_t MsgId, int64_t OpId) {
1319  return (MsgId == ID_GS || MsgId == ID_GS_DONE) && OpId != OP_GS_NOP;
1320 }
1321 
1322 void decodeMsg(unsigned Val,
1323  uint16_t &MsgId,
1324  uint16_t &OpId,
1325  uint16_t &StreamId) {
1326  MsgId = Val & ID_MASK_;
1327  OpId = (Val & OP_MASK_) >> OP_SHIFT_;
1329 }
1330 
1332  uint64_t OpId,
1333  uint64_t StreamId) {
1334  return (MsgId << ID_SHIFT_) |
1335  (OpId << OP_SHIFT_) |
1337 }
1338 
1339 } // namespace SendMsg
1340 
1341 //===----------------------------------------------------------------------===//
1342 //
1343 //===----------------------------------------------------------------------===//
1344 
1346  return getIntegerAttribute(F, "InitialPSInputAddr", 0);
1347 }
1348 
1350  // As a safe default always respond as if PS has color exports.
1351  return getIntegerAttribute(
1352  F, "amdgpu-color-export",
1353  F.getCallingConv() == CallingConv::AMDGPU_PS ? 1 : 0) != 0;
1354 }
1355 
1357  return getIntegerAttribute(F, "amdgpu-depth-export", 0) != 0;
1358 }
1359 
1361  switch(cc) {
1369  return true;
1370  default:
1371  return false;
1372  }
1373 }
1374 
1376  return isShader(cc) || cc == CallingConv::AMDGPU_Gfx;
1377 }
1378 
1380  return !isGraphics(cc) || cc == CallingConv::AMDGPU_CS;
1381 }
1382 
1384  switch (CC) {
1394  return true;
1395  default:
1396  return false;
1397  }
1398 }
1399 
1401  switch (CC) {
1403  return true;
1404  default:
1405  return isEntryFunctionCC(CC);
1406  }
1407 }
1408 
1409 bool hasXNACK(const MCSubtargetInfo &STI) {
1410  return STI.getFeatureBits()[AMDGPU::FeatureXNACK];
1411 }
1412 
1413 bool hasSRAMECC(const MCSubtargetInfo &STI) {
1414  return STI.getFeatureBits()[AMDGPU::FeatureSRAMECC];
1415 }
1416 
1417 bool hasMIMG_R128(const MCSubtargetInfo &STI) {
1418  return STI.getFeatureBits()[AMDGPU::FeatureMIMG_R128] && !STI.getFeatureBits()[AMDGPU::FeatureR128A16];
1419 }
1420 
1421 bool hasGFX10A16(const MCSubtargetInfo &STI) {
1422  return STI.getFeatureBits()[AMDGPU::FeatureGFX10A16];
1423 }
1424 
1425 bool hasG16(const MCSubtargetInfo &STI) {
1426  return STI.getFeatureBits()[AMDGPU::FeatureG16];
1427 }
1428 
1429 bool hasPackedD16(const MCSubtargetInfo &STI) {
1430  return !STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem];
1431 }
1432 
1433 bool isSI(const MCSubtargetInfo &STI) {
1434  return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
1435 }
1436 
1437 bool isCI(const MCSubtargetInfo &STI) {
1438  return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
1439 }
1440 
1441 bool isVI(const MCSubtargetInfo &STI) {
1442  return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1443 }
1444 
1445 bool isGFX9(const MCSubtargetInfo &STI) {
1446  return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
1447 }
1448 
1449 bool isGFX9Plus(const MCSubtargetInfo &STI) {
1450  return isGFX9(STI) || isGFX10Plus(STI);
1451 }
1452 
1453 bool isGFX10(const MCSubtargetInfo &STI) {
1454  return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
1455 }
1456 
1457 bool isGFX10Plus(const MCSubtargetInfo &STI) { return isGFX10(STI); }
1458 
1460  return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding];
1461 }
1462 
1464  return STI.getFeatureBits()[AMDGPU::FeatureGFX10_AEncoding];
1465 }
1466 
1468  return STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding];
1469 }
1470 
1472  return STI.getFeatureBits()[AMDGPU::FeatureGFX10_3Insts];
1473 }
1474 
1475 bool isGFX90A(const MCSubtargetInfo &STI) {
1476  return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts];
1477 }
1478 
1480  return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch];
1481 }
1482 
1483 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
1484  const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
1485  const unsigned FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0);
1486  return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
1487  Reg == AMDGPU::SCC;
1488 }
1489 
1490 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
1491  for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) {
1492  if (*R == Reg1) return true;
1493  }
1494  return false;
1495 }
1496 
1497 #define MAP_REG2REG \
1498  using namespace AMDGPU; \
1499  switch(Reg) { \
1500  default: return Reg; \
1501  CASE_CI_VI(FLAT_SCR) \
1502  CASE_CI_VI(FLAT_SCR_LO) \
1503  CASE_CI_VI(FLAT_SCR_HI) \
1504  CASE_VI_GFX9PLUS(TTMP0) \
1505  CASE_VI_GFX9PLUS(TTMP1) \
1506  CASE_VI_GFX9PLUS(TTMP2) \
1507  CASE_VI_GFX9PLUS(TTMP3) \
1508  CASE_VI_GFX9PLUS(TTMP4) \
1509  CASE_VI_GFX9PLUS(TTMP5) \
1510  CASE_VI_GFX9PLUS(TTMP6) \
1511  CASE_VI_GFX9PLUS(TTMP7) \
1512  CASE_VI_GFX9PLUS(TTMP8) \
1513  CASE_VI_GFX9PLUS(TTMP9) \
1514  CASE_VI_GFX9PLUS(TTMP10) \
1515  CASE_VI_GFX9PLUS(TTMP11) \
1516  CASE_VI_GFX9PLUS(TTMP12) \
1517  CASE_VI_GFX9PLUS(TTMP13) \
1518  CASE_VI_GFX9PLUS(TTMP14) \
1519  CASE_VI_GFX9PLUS(TTMP15) \
1520  CASE_VI_GFX9PLUS(TTMP0_TTMP1) \
1521  CASE_VI_GFX9PLUS(TTMP2_TTMP3) \
1522  CASE_VI_GFX9PLUS(TTMP4_TTMP5) \
1523  CASE_VI_GFX9PLUS(TTMP6_TTMP7) \
1524  CASE_VI_GFX9PLUS(TTMP8_TTMP9) \
1525  CASE_VI_GFX9PLUS(TTMP10_TTMP11) \
1526  CASE_VI_GFX9PLUS(TTMP12_TTMP13) \
1527  CASE_VI_GFX9PLUS(TTMP14_TTMP15) \
1528  CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3) \
1529  CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7) \
1530  CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11) \
1531  CASE_VI_GFX9PLUS(TTMP12_TTMP13_TTMP14_TTMP15) \
1532  CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
1533  CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
1534  CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
1535  CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
1536  }
1537 
1538 #define CASE_CI_VI(node) \
1539  assert(!isSI(STI)); \
1540  case node: return isCI(STI) ? node##_ci : node##_vi;
1541 
1542 #define CASE_VI_GFX9PLUS(node) \
1543  case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;
1544 
1545 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
1546  if (STI.getTargetTriple().getArch() == Triple::r600)
1547  return Reg;
1548  MAP_REG2REG
1549 }
1550 
1551 #undef CASE_CI_VI
1552 #undef CASE_VI_GFX9PLUS
1553 
1554 #define CASE_CI_VI(node) case node##_ci: case node##_vi: return node;
1555 #define CASE_VI_GFX9PLUS(node) case node##_vi: case node##_gfx9plus: return node;
1556 
1557 unsigned mc2PseudoReg(unsigned Reg) {
1558  MAP_REG2REG
1559 }
1560 
1561 #undef CASE_CI_VI
1562 #undef CASE_VI_GFX9PLUS
1563 #undef MAP_REG2REG
1564 
1565 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
1566  assert(OpNo < Desc.NumOperands);
1567  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
1568  return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
1569  OpType <= AMDGPU::OPERAND_SRC_LAST;
1570 }
1571 
1572 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
1573  assert(OpNo < Desc.NumOperands);
1574  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
1575  switch (OpType) {
1595  return true;
1596  default:
1597  return false;
1598  }
1599 }
1600 
1601 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
1602  assert(OpNo < Desc.NumOperands);
1603  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
1604  return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
1606 }
1607 
1608 // Avoid using MCRegisterClass::getSize, since that function will go away
1609 // (move from MC* level to Target* level). Return size in bits.
1610 unsigned getRegBitWidth(unsigned RCID) {
1611  switch (RCID) {
1612  case AMDGPU::VGPR_LO16RegClassID:
1613  case AMDGPU::VGPR_HI16RegClassID:
1614  case AMDGPU::SGPR_LO16RegClassID:
1615  case AMDGPU::AGPR_LO16RegClassID:
1616  return 16;
1617  case AMDGPU::SGPR_32RegClassID:
1618  case AMDGPU::VGPR_32RegClassID:
1619  case AMDGPU::VRegOrLds_32RegClassID:
1620  case AMDGPU::AGPR_32RegClassID:
1621  case AMDGPU::VS_32RegClassID:
1622  case AMDGPU::AV_32RegClassID:
1623  case AMDGPU::SReg_32RegClassID:
1624  case AMDGPU::SReg_32_XM0RegClassID:
1625  case AMDGPU::SRegOrLds_32RegClassID:
1626  return 32;
1627  case AMDGPU::SGPR_64RegClassID:
1628  case AMDGPU::VS_64RegClassID:
1629  case AMDGPU::AV_64RegClassID:
1630  case AMDGPU::SReg_64RegClassID:
1631  case AMDGPU::VReg_64RegClassID:
1632  case AMDGPU::AReg_64RegClassID:
1633  case AMDGPU::SReg_64_XEXECRegClassID:
1634  case AMDGPU::VReg_64_Align2RegClassID:
1635  case AMDGPU::AReg_64_Align2RegClassID:
1636  return 64;
1637  case AMDGPU::SGPR_96RegClassID:
1638  case AMDGPU::SReg_96RegClassID:
1639  case AMDGPU::VReg_96RegClassID:
1640  case AMDGPU::AReg_96RegClassID:
1641  case AMDGPU::VReg_96_Align2RegClassID:
1642  case AMDGPU::AReg_96_Align2RegClassID:
1643  case AMDGPU::AV_96RegClassID:
1644  return 96;
1645  case AMDGPU::SGPR_128RegClassID:
1646  case AMDGPU::SReg_128RegClassID:
1647  case AMDGPU::VReg_128RegClassID:
1648  case AMDGPU::AReg_128RegClassID:
1649  case AMDGPU::VReg_128_Align2RegClassID:
1650  case AMDGPU::AReg_128_Align2RegClassID:
1651  case AMDGPU::AV_128RegClassID:
1652  return 128;
1653  case AMDGPU::SGPR_160RegClassID:
1654  case AMDGPU::SReg_160RegClassID:
1655  case AMDGPU::VReg_160RegClassID:
1656  case AMDGPU::AReg_160RegClassID:
1657  case AMDGPU::VReg_160_Align2RegClassID:
1658  case AMDGPU::AReg_160_Align2RegClassID:
1659  case AMDGPU::AV_160RegClassID:
1660  return 160;
1661  case AMDGPU::SGPR_192RegClassID:
1662  case AMDGPU::SReg_192RegClassID:
1663  case AMDGPU::VReg_192RegClassID:
1664  case AMDGPU::AReg_192RegClassID:
1665  case AMDGPU::VReg_192_Align2RegClassID:
1666  case AMDGPU::AReg_192_Align2RegClassID:
1667  return 192;
1668  case AMDGPU::SGPR_224RegClassID:
1669  case AMDGPU::SReg_224RegClassID:
1670  case AMDGPU::VReg_224RegClassID:
1671  case AMDGPU::AReg_224RegClassID:
1672  case AMDGPU::VReg_224_Align2RegClassID:
1673  case AMDGPU::AReg_224_Align2RegClassID:
1674  return 224;
1675  case AMDGPU::SGPR_256RegClassID:
1676  case AMDGPU::SReg_256RegClassID:
1677  case AMDGPU::VReg_256RegClassID:
1678  case AMDGPU::AReg_256RegClassID:
1679  case AMDGPU::VReg_256_Align2RegClassID:
1680  case AMDGPU::AReg_256_Align2RegClassID:
1681  return 256;
1682  case AMDGPU::SGPR_512RegClassID:
1683  case AMDGPU::SReg_512RegClassID:
1684  case AMDGPU::VReg_512RegClassID:
1685  case AMDGPU::AReg_512RegClassID:
1686  case AMDGPU::VReg_512_Align2RegClassID:
1687  case AMDGPU::AReg_512_Align2RegClassID:
1688  return 512;
1689  case AMDGPU::SGPR_1024RegClassID:
1690  case AMDGPU::SReg_1024RegClassID:
1691  case AMDGPU::VReg_1024RegClassID:
1692  case AMDGPU::AReg_1024RegClassID:
1693  case AMDGPU::VReg_1024_Align2RegClassID:
1694  case AMDGPU::AReg_1024_Align2RegClassID:
1695  return 1024;
1696  default:
1697  llvm_unreachable("Unexpected register class");
1698  }
1699 }
1700 
1701 unsigned getRegBitWidth(const MCRegisterClass &RC) {
1702  return getRegBitWidth(RC.getID());
1703 }
1704 
1705 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
1706  unsigned OpNo) {
1707  assert(OpNo < Desc.NumOperands);
1708  unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1709  return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
1710 }
1711 
1712 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
1714  return true;
1715 
1716  uint64_t Val = static_cast<uint64_t>(Literal);
1717  return (Val == DoubleToBits(0.0)) ||
1718  (Val == DoubleToBits(1.0)) ||
1719  (Val == DoubleToBits(-1.0)) ||
1720  (Val == DoubleToBits(0.5)) ||
1721  (Val == DoubleToBits(-0.5)) ||
1722  (Val == DoubleToBits(2.0)) ||
1723  (Val == DoubleToBits(-2.0)) ||
1724  (Val == DoubleToBits(4.0)) ||
1725  (Val == DoubleToBits(-4.0)) ||
1726  (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
1727 }
1728 
1729 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
1731  return true;
1732 
1733  // The actual type of the operand does not seem to matter as long
1734  // as the bits match one of the inline immediate values. For example:
1735  //
1736  // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
1737  // so it is a legal inline immediate.
1738  //
1739  // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
1740  // floating-point, so it is a legal inline immediate.
1741 
1742  uint32_t Val = static_cast<uint32_t>(Literal);
1743  return (Val == FloatToBits(0.0f)) ||
1744  (Val == FloatToBits(1.0f)) ||
1745  (Val == FloatToBits(-1.0f)) ||
1746  (Val == FloatToBits(0.5f)) ||
1747  (Val == FloatToBits(-0.5f)) ||
1748  (Val == FloatToBits(2.0f)) ||
1749  (Val == FloatToBits(-2.0f)) ||
1750  (Val == FloatToBits(4.0f)) ||
1751  (Val == FloatToBits(-4.0f)) ||
1752  (Val == 0x3e22f983 && HasInv2Pi);
1753 }
1754 
1755 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) {
1756  if (!HasInv2Pi)
1757  return false;
1758 
1760  return true;
1761 
1762  uint16_t Val = static_cast<uint16_t>(Literal);
1763  return Val == 0x3C00 || // 1.0
1764  Val == 0xBC00 || // -1.0
1765  Val == 0x3800 || // 0.5
1766  Val == 0xB800 || // -0.5
1767  Val == 0x4000 || // 2.0
1768  Val == 0xC000 || // -2.0
1769  Val == 0x4400 || // 4.0
1770  Val == 0xC400 || // -4.0
1771  Val == 0x3118; // 1/2pi
1772 }
1773 
1774 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi) {
1775  assert(HasInv2Pi);
1776 
1777  if (isInt<16>(Literal) || isUInt<16>(Literal)) {
1778  int16_t Trunc = static_cast<int16_t>(Literal);
1779  return AMDGPU::isInlinableLiteral16(Trunc, HasInv2Pi);
1780  }
1781  if (!(Literal & 0xffff))
1782  return AMDGPU::isInlinableLiteral16(Literal >> 16, HasInv2Pi);
1783 
1784  int16_t Lo16 = static_cast<int16_t>(Literal);
1785  int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
1786  return Lo16 == Hi16 && isInlinableLiteral16(Lo16, HasInv2Pi);
1787 }
1788 
1789 bool isInlinableIntLiteralV216(int32_t Literal) {
1790  int16_t Lo16 = static_cast<int16_t>(Literal);
1792  return isInlinableIntLiteral(Lo16);
1793 
1794  int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
1795  if (!(Literal & 0xffff))
1796  return isInlinableIntLiteral(Hi16);
1797  return Lo16 == Hi16 && isInlinableIntLiteral(Lo16);
1798 }
1799 
1800 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi) {
1801  assert(HasInv2Pi);
1802 
1803  int16_t Lo16 = static_cast<int16_t>(Literal);
1805  return true;
1806 
1807  int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
1808  if (!(Literal & 0xffff))
1809  return true;
1810  return Lo16 == Hi16;
1811 }
1812 
1813 bool isArgPassedInSGPR(const Argument *A) {
1814  const Function *F = A->getParent();
1815 
1816  // Arguments to compute shaders are never a source of divergence.
1817  CallingConv::ID CC = F->getCallingConv();
1818  switch (CC) {
1821  return true;
1830  // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
1831  // Everything else is in VGPRs.
1832  return F->getAttributes().hasParamAttr(A->getArgNo(), Attribute::InReg) ||
1833  F->getAttributes().hasParamAttr(A->getArgNo(), Attribute::ByVal);
1834  default:
1835  // TODO: Should calls support inreg for SGPR inputs?
1836  return false;
1837  }
1838 }
1839 
1840 static bool hasSMEMByteOffset(const MCSubtargetInfo &ST) {
1841  return isGCN3Encoding(ST) || isGFX10Plus(ST);
1842 }
1843 
1845  return isGFX9Plus(ST);
1846 }
1847 
1849  int64_t EncodedOffset) {
1850  return hasSMEMByteOffset(ST) ? isUInt<20>(EncodedOffset)
1851  : isUInt<8>(EncodedOffset);
1852 }
1853 
1855  int64_t EncodedOffset,
1856  bool IsBuffer) {
1857  return !IsBuffer &&
1859  isInt<21>(EncodedOffset);
1860 }
1861 
1862 static bool isDwordAligned(uint64_t ByteOffset) {
1863  return (ByteOffset & 3) == 0;
1864 }
1865 
1867  uint64_t ByteOffset) {
1868  if (hasSMEMByteOffset(ST))
1869  return ByteOffset;
1870 
1871  assert(isDwordAligned(ByteOffset));
1872  return ByteOffset >> 2;
1873 }
1874 
1876  int64_t ByteOffset, bool IsBuffer) {
1877  // The signed version is always a byte offset.
1878  if (!IsBuffer && hasSMRDSignedImmOffset(ST)) {
1880  return isInt<20>(ByteOffset) ? Optional<int64_t>(ByteOffset) : None;
1881  }
1882 
1883  if (!isDwordAligned(ByteOffset) && !hasSMEMByteOffset(ST))
1884  return None;
1885 
1886  int64_t EncodedOffset = convertSMRDOffsetUnits(ST, ByteOffset);
1887  return isLegalSMRDEncodedUnsignedOffset(ST, EncodedOffset)
1888  ? Optional<int64_t>(EncodedOffset)
1889  : None;
1890 }
1891 
1893  int64_t ByteOffset) {
1894  if (!isCI(ST) || !isDwordAligned(ByteOffset))
1895  return None;
1896 
1897  int64_t EncodedOffset = convertSMRDOffsetUnits(ST, ByteOffset);
1898  return isUInt<32>(EncodedOffset) ? Optional<int64_t>(EncodedOffset) : None;
1899 }
1900 
1902  // Address offset is 12-bit signed for GFX10, 13-bit for GFX9.
1903  if (AMDGPU::isGFX10(ST))
1904  return Signed ? 12 : 11;
1905 
1906  return Signed ? 13 : 12;
1907 }
1908 
1909 // Given Imm, split it into the values to put into the SOffset and ImmOffset
1910 // fields in an MUBUF instruction. Return false if it is not possible (due to a
1911 // hardware bug needing a workaround).
1912 //
1913 // The required alignment ensures that individual address components remain
1914 // aligned if they are aligned to begin with. It also ensures that additional
1915 // offsets within the given alignment can be added to the resulting ImmOffset.
1916 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
1917  const GCNSubtarget *Subtarget, Align Alignment) {
1918  const uint32_t MaxImm = alignDown(4095, Alignment.value());
1919  uint32_t Overflow = 0;
1920 
1921  if (Imm > MaxImm) {
1922  if (Imm <= MaxImm + 64) {
1923  // Use an SOffset inline constant for 4..64
1924  Overflow = Imm - MaxImm;
1925  Imm = MaxImm;
1926  } else {
1927  // Try to keep the same value in SOffset for adjacent loads, so that
1928  // the corresponding register contents can be re-used.
1929  //
1930  // Load values with all low-bits (except for alignment bits) set into
1931  // SOffset, so that a larger range of values can be covered using
1932  // s_movk_i32.
1933  //
1934  // Atomic operations fail to work correctly when individual address
1935  // components are unaligned, even if their sum is aligned.
1936  uint32_t High = (Imm + Alignment.value()) & ~4095;
1937  uint32_t Low = (Imm + Alignment.value()) & 4095;
1938  Imm = Low;
1939  Overflow = High - Alignment.value();
1940  }
1941  }
1942 
1943  // There is a hardware bug in SI and CI which prevents address clamping in
1944  // MUBUF instructions from working correctly with SOffsets. The immediate
1945  // offset is unaffected.
1946  if (Overflow > 0 &&
1948  return false;
1949 
1950  ImmOffset = Imm;
1951  SOffset = Overflow;
1952  return true;
1953 }
1954 
1956  *this = getDefaultForCallingConv(F.getCallingConv());
1957 
1958  StringRef IEEEAttr = F.getFnAttribute("amdgpu-ieee").getValueAsString();
1959  if (!IEEEAttr.empty())
1960  IEEE = IEEEAttr == "true";
1961 
1962  StringRef DX10ClampAttr
1963  = F.getFnAttribute("amdgpu-dx10-clamp").getValueAsString();
1964  if (!DX10ClampAttr.empty())
1965  DX10Clamp = DX10ClampAttr == "true";
1966 
1967  StringRef DenormF32Attr = F.getFnAttribute("denormal-fp-math-f32").getValueAsString();
1968  if (!DenormF32Attr.empty()) {
1969  DenormalMode DenormMode = parseDenormalFPAttribute(DenormF32Attr);
1972  }
1973 
1974  StringRef DenormAttr = F.getFnAttribute("denormal-fp-math").getValueAsString();
1975  if (!DenormAttr.empty()) {
1976  DenormalMode DenormMode = parseDenormalFPAttribute(DenormAttr);
1977 
1978  if (DenormF32Attr.empty()) {
1981  }
1982 
1985  }
1986 }
1987 
1988 namespace {
1989 
1990 struct SourceOfDivergence {
1991  unsigned Intr;
1992 };
1993 const SourceOfDivergence *lookupSourceOfDivergence(unsigned Intr);
1994 
1995 #define GET_SourcesOfDivergence_IMPL
1996 #define GET_Gfx9BufferFormat_IMPL
1997 #define GET_Gfx10PlusBufferFormat_IMPL
1998 #include "AMDGPUGenSearchableTables.inc"
1999 
2000 } // end anonymous namespace
2001 
2002 bool isIntrinsicSourceOfDivergence(unsigned IntrID) {
2003  return lookupSourceOfDivergence(IntrID);
2004 }
2005 
2006 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
2007  uint8_t NumComponents,
2008  uint8_t NumFormat,
2009  const MCSubtargetInfo &STI) {
2010  return isGFX10Plus(STI)
2011  ? getGfx10PlusBufferFormatInfo(BitsPerComp, NumComponents,
2012  NumFormat)
2013  : getGfx9BufferFormatInfo(BitsPerComp, NumComponents, NumFormat);
2014 }
2015 
2017  const MCSubtargetInfo &STI) {
2018  return isGFX10Plus(STI) ? getGfx10PlusBufferFormatInfo(Format)
2019  : getGfx9BufferFormatInfo(Format);
2020 }
2021 
2022 } // namespace AMDGPU
2023 
2026  switch (S) {
2028  OS << "Unsupported";
2029  break;
2031  OS << "Any";
2032  break;
2034  OS << "Off";
2035  break;
2037  OS << "On";
2038  break;
2039  }
2040  return OS;
2041 }
2042 
2043 } // namespace llvm
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:163
llvm::AMDGPU::Hwreg::encodeHwreg
uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width)
Definition: AMDGPUBaseInfo.cpp:1038
llvm::CallingConv::AMDGPU_Gfx
@ AMDGPU_Gfx
Calling convention used for AMD graphics targets.
Definition: CallingConv.h:250
i
i
Definition: README.txt:29
llvm::AMDGPU::SendMsg::getMsgName
StringRef getMsgName(int64_t MsgId)
Definition: AMDGPUBaseInfo.cpp:1252
llvm::AMDGPU::MUBUFInfo::elements
uint8_t elements
Definition: AMDGPUBaseInfo.cpp:189
llvm::AMDGPU::getMUBUFIsBufferInv
bool getMUBUFIsBufferInv(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:289
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::AMDGPU::getMCReg
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
Definition: AMDGPUBaseInfo.cpp:1545
llvm::AMDGPU::isHsaAbiVersion3
bool isHsaAbiVersion3(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:114
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::AMDGPUTargetID
AMDGPUTargetID(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:323
llvm::AMDGPU::mc2PseudoReg
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
Definition: AMDGPUBaseInfo.cpp:1557
llvm::AMDGPU::VOPInfo::IsSingle
bool IsSingle
Definition: AMDGPUBaseInfo.cpp:212
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4636
llvm::AMDGPU::MTBUFFormat::UFMT_MAX
@ UFMT_MAX
Definition: SIDefines.h:599
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::AMDGPU::IsaInfo::getSGPRAllocGranule
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:592
llvm::AMDGPU::getMUBUFHasSoffset
bool getMUBUFHasSoffset(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:284
llvm::LLVMContext::emitError
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Definition: LLVMContext.cpp:251
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::AMDGPU::MTBUFFormat::NumFormat
NumFormat
Definition: SIDefines.h:471
llvm::AMDGPU::Hwreg::getHwreg
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1044
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1207
llvm::AMDGPU::MIMGBaseOpcodeInfo::Gradients
bool Gradients
Definition: AMDGPUBaseInfo.h:289
llvm::AMDGPU::SendMsg::IdSymbolic
const char *const IdSymbolic[ID_GAPS_LAST_]
Definition: AMDGPUAsmUtils.cpp:18
llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumSGPRs
constexpr char NumSGPRs[]
Key for Kernel::CodeProps::Metadata::mNumSGPRs.
Definition: AMDGPUMetadata.h:253
llvm::AMDGPU::MIMGBaseOpcodeInfo::LodOrClampOrMip
bool LodOrClampOrMip
Definition: AMDGPUBaseInfo.h:292
llvm::AMDGPU::MTBUFFormat::getDfmtName
StringRef getDfmtName(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1131
llvm::AMDGPU::SendMsg::encodeMsg
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
Definition: AMDGPUBaseInfo.cpp:1331
llvm::AMDGPU::getIsaVersion
IsaVersion getIsaVersion(StringRef GPU)
Definition: TargetParser.cpp:189
llvm::AMDGPU::decodeLgkmcnt
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:940
llvm::AMDGPU::Hwreg::ID_SHIFT_
@ ID_SHIFT_
Definition: SIDefines.h:385
llvm::StringRef::endswith
LLVM_NODISCARD bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:297
llvm::AMDGPU::SendMsg::OpGsSymbolic
const char *const OpGsSymbolic[OP_GS_LAST_]
Definition: AMDGPUAsmUtils.cpp:46
llvm::Function
Definition: Function.h:62
llvm::AMDGPU::getMUBUFBaseOpcode
int getMUBUFBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:259
llvm::Attribute
Definition: Attributes.h:52
llvm::AMDGPU::SIModeRegisterDefaults::FP32OutputDenormals
bool FP32OutputDenormals
Definition: AMDGPUBaseInfo.h:929
llvm::AMDGPU::getSMRDEncodedOffset
Optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
Definition: AMDGPUBaseInfo.cpp:1875
llvm::AMDGPU::MTBUFFormat::DFMT_MASK
@ DFMT_MASK
Definition: SIDefines.h:468
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isSramEccOnOrAny
bool isSramEccOnOrAny() const
Definition: AMDGPUBaseInfo.h:130
llvm::AMDGPU::getMCOpcode
int getMCOpcode(uint16_t Opcode, unsigned Gen)
Definition: AMDGPUBaseInfo.cpp:317
llvm::AMDGPU::decodeVmcnt
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:924
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:625
llvm::AMDGPU::hasSRAMECC
bool hasSRAMECC(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1413
llvm::AMDGPU::SIModeRegisterDefaults::IEEE
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
Definition: AMDGPUBaseInfo.h:920
llvm::AMDGPU::hasXNACK
bool hasXNACK(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1409
llvm::AMDGPU::IsaInfo::TargetIDSetting::Unsupported
@ Unsupported
llvm::AMDGPU::OPERAND_REG_IMM_V2FP16
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:152
High
uint64_t High
Definition: NVVMIntrRange.cpp:61
cc
src override malloc cc
Definition: CMakeLists.txt:93
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::AMDGPU::SendMsg::ID_STALL_WAVE_GEN
@ ID_STALL_WAVE_GEN
Definition: SIDefines.h:309
llvm::AMDGPU::IsaInfo::TargetIDSetting::On
@ On
llvm::AMDGPU::isGFX10_BEncoding
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1467
llvm::Triple::amdgcn
@ amdgcn
Definition: Triple.h:72
llvm::AMDGPU::isGFX10_AEncoding
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1463
amd_kernel_code_t::compute_pgm_resource_registers
uint64_t compute_pgm_resource_registers
Shader program settings for CS.
Definition: AMDKernelCodeT.h:558
llvm::AMDGPU::getVOP2IsSingle
bool getVOP2IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:304
llvm::AMDGPU::MIMGDimInfo
Definition: AMDGPUBaseInfo.h:304
llvm::AMDGPU::hasArchitectedFlatScratch
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1479
llvm::AMDGPU::MTBUFFormat::encodeDfmtNfmt
int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt)
Definition: AMDGPUBaseInfo.cpp:1169
llvm::AMDGPU::getHsaAbiVersion
Optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:91
llvm::AMDGPU::MTBUFFormat::NFMT_UNDEF
@ NFMT_UNDEF
Definition: SIDefines.h:485
llvm::AMDGPUSubtarget::SEA_ISLANDS
@ SEA_ISLANDS
Definition: AMDGPUSubtarget.h:38
llvm::AMDGPU::Exp::ET_NULL
@ ET_NULL
Definition: SIDefines.h:746
llvm::AMDGPU::SendMsg::STREAM_ID_MASK_
@ STREAM_ID_MASK_
Definition: SIDefines.h:354
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::AMDGPU::SendMsg::OpSysSymbolic
const char *const OpSysSymbolic[OP_SYS_LAST_]
Definition: AMDGPUAsmUtils.cpp:38
llvm::AMDGPU::getSMRDEncodedLiteralOffset32
Optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
Definition: AMDGPUBaseInfo.cpp:1892
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::AMDGPU::MTBUFInfo::has_vaddr
bool has_vaddr
Definition: AMDGPUBaseInfo.cpp:200
llvm::AMDGPU::SendMsg::OP_GS_LAST_
@ OP_GS_LAST_
Definition: SIDefines.h:336
llvm::AMDGPU::MTBUFFormat::isValidNfmt
bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1165
Shift
bool Shift
Definition: README.txt:468
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_GFX1030_
@ ID_SYMBOLIC_FIRST_GFX1030_
Definition: SIDefines.h:383
llvm::AMDGPU::Hwreg::ID_MASK_
@ ID_MASK_
Definition: SIDefines.h:387
llvm::AMDGPU::Exp::ET_POS0
@ ET_POS0
Definition: SIDefines.h:747
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_MAX
@ DFMT_NFMT_MAX
Definition: SIDefines.h:500
llvm::FloatToBits
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:663
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:210
llvm::AMDGPU::IsaInfo::getNumExtraSGPRs
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
Definition: AMDGPUBaseInfo.cpp:658
llvm::AMDGPU::isGFX10
bool isGFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1453
llvm::AMDGPU::IsaInfo::getTotalNumVGPRs
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:722
llvm::AMDGPU::SendMsg::ID_EARLY_PRIM_DEALLOC
@ ID_EARLY_PRIM_DEALLOC
Definition: SIDefines.h:312
llvm::AMDGPU::MTBUFFormat::getUnifiedFormat
int64_t getUnifiedFormat(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1178
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setTargetIDFromTargetIDStream
void setTargetIDFromTargetIDStream(StringRef TargetID)
Definition: AMDGPUBaseInfo.cpp:400
llvm::AMDGPU::IsaInfo::getMinWavesPerEU
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:559
llvm::Optional< uint8_t >
llvm::AMDGPU::SIModeRegisterDefaults::getDefaultForCallingConv
static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.h:946
llvm::AMDGPU::MUBUFInfo::has_soffset
bool has_soffset
Definition: AMDGPUBaseInfo.cpp:192
llvm::MCRegisterClass::contains
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
Definition: MCRegisterInfo.h:68
llvm::AMDGPU::SIModeRegisterDefaults::FP32InputDenormals
bool FP32InputDenormals
If this is set, neither input or output denormals are flushed for most f32 instructions.
Definition: AMDGPUBaseInfo.h:928
llvm::AMDGPU::IsaInfo::TargetIDSetting::Any
@ Any
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
AMDGPUAsmUtils.h
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:893
llvm::CallingConv::AMDGPU_ES
@ AMDGPU_ES
Calling convention used for AMDPAL shader stage before geometry shader if geometry is in use.
Definition: CallingConv.h:236
llvm::AMDGPU::getVmcntBitMask
unsigned getVmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:894
llvm::AMDGPU::isGlobalSegment
bool isGlobalSegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:840
llvm::AMDGPU::SendMsg::getMsgId
int64_t getMsgId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1221
llvm::AMDGPU::hasGFX10_3Insts
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1471
TargetParser.h
llvm::AMDGPU::SendMsg::ID_GAPS_LAST_
@ ID_GAPS_LAST_
Definition: SIDefines.h:317
llvm::AMDGPU::IsaInfo::getMaxNumVGPRs
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:747
llvm::AMDGPU::Exp::ET_PARAM0
@ ET_PARAM0
Definition: SIDefines.h:752
llvm::AMDGPU::getWaitcntBitMask
unsigned getWaitcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:911
llvm::AMDGPU::isIntrinsicSourceOfDivergence
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
Definition: AMDGPUBaseInfo.cpp:2002
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc2
uint32_t compute_pgm_rsrc2
Definition: AMDHSAKernelDescriptor.h:174
llvm::AMDGPU::SendMsg::getMsgOpName
StringRef getMsgOpName(int64_t MsgId, int64_t OpId)
Definition: AMDGPUBaseInfo.cpp:1289
llvm::AMDGPU::MIMGDimInfo::NumGradients
uint8_t NumGradients
Definition: AMDGPUBaseInfo.h:307
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::AMDGPU::getMTBUFOpcode
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
Definition: AMDGPUBaseInfo.cpp:234
llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable
static const StringLiteral * getNfmtLookupTable(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1136
llvm::AMDGPU::MUBUFInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:187
llvm::AMDGPU::SendMsg::ID_SAVEWAVE
@ ID_SAVEWAVE
Definition: SIDefines.h:308
llvm::AMDGPU::MIMGInfo::VAddrDwords
uint8_t VAddrDwords
Definition: AMDGPUBaseInfo.h:364
llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:547
llvm::AMDGPUAS::CONSTANT_ADDRESS
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:362
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::AMDGPU::MTBUFFormat::isValidDfmtNfmt
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1158
AMDHSAKernelDescriptor.h
llvm::AMDGPU::HSAMD::V3::VersionMajor
constexpr uint32_t VersionMajor
HSA metadata major version.
Definition: AMDGPUMetadata.h:454
llvm::AMDGPU::SendMsg::ID_MASK_
@ ID_MASK_
Definition: SIDefines.h:321
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
llvm::AMDGPU::IsaInfo::TargetIDSetting
TargetIDSetting
Definition: AMDGPUBaseInfo.h:78
llvm::parseDenormalFPAttribute
DenormalMode parseDenormalFPAttribute(StringRef Str)
Returns the denormal mode to use for inputs and outputs.
Definition: FloatingPointMode.h:174
llvm::AMDGPU::Hwreg::decodeHwreg
void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)
Definition: AMDGPUBaseInfo.cpp:1048
llvm::AMDGPU::Hwreg::ID_UNKNOWN_
@ ID_UNKNOWN_
Definition: SIDefines.h:362
llvm::AMDGPU::IsaVersion
Instruction set architecture version.
Definition: TargetParser.h:105
llvm::AMDGPU::IsaInfo::getSGPREncodingGranule
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:601
CommandLine.h
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicVI
const StringLiteral NfmtSymbolicVI[]
Definition: AMDGPUAsmUtils.cpp:136
llvm::AMDGPU::isGFX90A
bool isGFX90A(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1475
llvm::AMDGPU::SendMsg::OP_GS_FIRST_
@ OP_GS_FIRST_
Definition: SIDefines.h:337
llvm::AMDGPU::OPERAND_REG_IMM_FP32
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:147
llvm::AMDGPU::SendMsg::ID_GET_DOORBELL
@ ID_GET_DOORBELL
Definition: SIDefines.h:314
llvm::AMDGPU::MUBUFInfo::has_srsrc
bool has_srsrc
Definition: AMDGPUBaseInfo.cpp:191
llvm::StringLiteral
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:891
llvm::AMDGPU::getMTBUFHasSrsrc
bool getMTBUFHasSrsrc(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:249
GlobalValue.h
ELF.h
llvm::DenormalMode::Input
DenormalModeKind Input
Denormal treatment kind for floating point instruction inputs in the default floating-point environme...
Definition: FloatingPointMode.h:90
llvm::AMDGPU::isShader
bool isShader(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1360
llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:587
llvm::AMDGPU::MTBUFInfo::has_soffset
bool has_soffset
Definition: AMDGPUBaseInfo.cpp:202
amd_kernel_code_t::amd_kernel_code_version_major
uint32_t amd_kernel_code_version_major
Definition: AMDKernelCodeT.h:527
llvm::AMDGPU::Exp::ET_INVALID
@ ET_INVALID
Definition: SIDefines.h:762
llvm::AMDGPU::Exp::ET_MRTZ_MAX_IDX
@ ET_MRTZ_MAX_IDX
Definition: SIDefines.h:756
GCNSubtarget.h
llvm::AMDGPU::hasSMEMByteOffset
static bool hasSMEMByteOffset(const MCSubtargetInfo &ST)
Definition: AMDGPUBaseInfo.cpp:1840
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::AMDGPU::getRegOperandSize
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
Definition: AMDGPUBaseInfo.cpp:1705
llvm::AMDGPU::SendMsg::OP_SYS_LAST_
@ OP_SYS_LAST_
Definition: SIDefines.h:343
llvm::ReplacementType::Literal
@ Literal
llvm::AMDGPU::Hwreg::isValidHwreg
bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1020
llvm::AMDGPU::getMIMGBaseOpcode
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:145
llvm::AMDGPU::SendMsg::ID_GS_ALLOC_REQ
@ ID_GS_ALLOC_REQ
Definition: SIDefines.h:313
llvm::AMDGPU::MTBUFFormat::UFMT_DEFAULT
@ UFMT_DEFAULT
Definition: SIDefines.h:602
llvm::StringRef::split
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:749
llvm::AMDGPU::MIMGBaseOpcodeInfo
Definition: AMDGPUBaseInfo.h:280
llvm::AMDGPU::isInlinableIntLiteralV216
bool isInlinableIntLiteralV216(int32_t Literal)
Definition: AMDGPUBaseInfo.cpp:1789
Intr
unsigned Intr
Definition: AMDGPUBaseInfo.cpp:1991
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:176
llvm::AMDGPU::MTBUFFormat::DfmtSymbolic
const StringLiteral DfmtSymbolic[]
Definition: AMDGPUAsmUtils.cpp:95
llvm::AMDGPU::getMUBUFOpcode
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
Definition: AMDGPUBaseInfo.cpp:264
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:107
llvm::AMDGPU::getSMEMIsBuffer
bool getSMEMIsBuffer(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:294
llvm::AMDGPU::IsaInfo::getMaxNumSGPRs
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
Definition: AMDGPUBaseInfo.cpp:641
llvm::AMDGPU::isSGPR
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
Definition: AMDGPUBaseInfo.cpp:1483
llvm::AMDGPUAS::LOCAL_ADDRESS
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:363
llvm::AMDGPU::IsaInfo::getTargetIDSettingFromFeatureString
static TargetIDSetting getTargetIDSettingFromFeatureString(StringRef FeatureString)
Definition: AMDGPUBaseInfo.cpp:391
llvm::AMDGPU::SendMsg::STREAM_ID_LAST_
@ STREAM_ID_LAST_
Definition: SIDefines.h:350
llvm::SubtargetFeatures::getFeatures
const std::vector< std::string > & getFeatures() const
Returns the vector of individual subtarget features.
Definition: SubtargetFeature.h:196
llvm::DoubleToBits
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:653
llvm::SubtargetFeatures
Manages the enabling and disabling of subtarget specific features.
Definition: SubtargetFeature.h:183
llvm::AMDGPU::MTBUFFormat::UfmtSymbolic
const StringLiteral UfmtSymbolic[]
Definition: AMDGPUAsmUtils.cpp:147
llvm::AMDGPU::SendMsg::ID_SYSMSG
@ ID_SYSMSG
Definition: SIDefines.h:316
llvm::AMDGPU::Hwreg::Id
Id
Definition: SIDefines.h:361
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackOnOrAny
bool isXnackOnOrAny() const
Definition: AMDGPUBaseInfo.h:101
llvm::AMDGPU::decodeExpcnt
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:936
llvm::AMDGPU::SendMsg::ID_SHIFT_
@ ID_SHIFT_
Definition: SIDefines.h:319
llvm::AMDGPU::MTBUFInfo::BaseOpcode
uint16_t BaseOpcode
Definition: AMDGPUBaseInfo.cpp:198
llvm::AMDGPUAS::GLOBAL_ADDRESS
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:359
llvm::alignDown
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
Definition: MathExtras.h:753
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
S_00B848_MEM_ORDERED
#define S_00B848_MEM_ORDERED(x)
Definition: SIDefines.h:880
llvm::AMDGPU::hasGFX10A16
bool hasGFX10A16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1421
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::AMDGPU::Exp::ET_PRIM
@ ET_PRIM
Definition: SIDefines.h:751
llvm::AMDGPU::SendMsg::OP_GS_NOP
@ OP_GS_NOP
Definition: SIDefines.h:332
llvm::AMDGPU::OPERAND_REG_IMM_FP64
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:148
llvm::AMDGPU::getMTBUFBaseOpcode
int getMTBUFBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:229
llvm::AMDGPU::getInitialPSInputAddr
unsigned getInitialPSInputAddr(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1345
llvm::AMDGPU::SendMsg::OP_SHIFT_
@ OP_SHIFT_
Definition: SIDefines.h:326
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_GFX9_
@ ID_SYMBOLIC_FIRST_GFX9_
Definition: SIDefines.h:372
llvm::Triple::r600
@ r600
Definition: Triple.h:71
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::AMDGPU::Exp::ExpTgt::Name
StringLiteral Name
Definition: AMDGPUBaseInfo.cpp:1063
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::AMDGPU::getMTBUFHasSoffset
bool getMTBUFHasSoffset(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:254
llvm::raw_ostream::flush
void flush()
Definition: raw_ostream.h:186
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:230
llvm::AMDGPU::MTBUFFormat::DFMT_UNDEF
@ DFMT_UNDEF
Definition: SIDefines.h:464
llvm::AMDGPU::decodeWaitcnt
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
Definition: AMDGPUBaseInfo.cpp:945
amd_kernel_code_t::wavefront_size
uint8_t wavefront_size
Wavefront size expressed as a power of two.
Definition: AMDKernelCodeT.h:643
llvm::AMDGPU::MTBUFInfo
Definition: AMDGPUBaseInfo.cpp:196
llvm::AMDGPU::OPERAND_REG_IMM_V2FP32
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:155
llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:578
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::getSramEccSetting
TargetIDSetting getSramEccSetting() const
Definition: AMDGPUBaseInfo.h:144
llvm::amdhsa::kernel_descriptor_t::kernel_code_properties
uint16_t kernel_code_properties
Definition: AMDHSAKernelDescriptor.h:175
llvm::IndexedInstrProf::Version
const uint64_t Version
Definition: InstrProf.h:991
llvm::AMDGPU::getMUBUFHasSrsrc
bool getMUBUFHasSrsrc(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:279
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::AMDGPU::convertSMRDOffsetUnits
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
Definition: AMDGPUBaseInfo.cpp:1866
llvm::AMDGPU::MTBUFFormat::UFMT_FIRST
@ UFMT_FIRST
Definition: SIDefines.h:596
llvm::AMDGPU::IsaInfo::getEUsPerCU
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:536
llvm::AMDGPU::MIMGInfo::MIMGEncoding
uint8_t MIMGEncoding
Definition: AMDGPUBaseInfo.h:362
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:89
llvm::AMDGPU::MTBUFInfo::elements
uint8_t elements
Definition: AMDGPUBaseInfo.cpp:199
llvm::AMDGPU::IsaInfo::getLocalMemorySize
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:527
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AMDGPU::getMIMGOpcode
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
Definition: AMDGPUBaseInfo.cpp:138
llvm::Triple::getArch
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:310
llvm::AMDGPU::MTBUFFormat::UFMT_UNDEF
@ UFMT_UNDEF
Definition: SIDefines.h:601
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:245
llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat
bool isValidUnifiedFormat(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1190
llvm::AMDGPU::isCI
bool isCI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1437
llvm::StringRef::getAsInteger
std::enable_if_t< std::numeric_limits< T >::is_signed, bool > getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:510
llvm::None
const NoneType None
Definition: None.h:23
llvm::AMDGPU::SendMsg::StreamId
StreamId
Definition: SIDefines.h:347
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::CallingConv::AMDGPU_GS
@ AMDGPU_GS
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:207
llvm::AMDGPU::SendMsg::ID_GAPS_FIRST_
@ ID_GAPS_FIRST_
Definition: SIDefines.h:318
llvm::AMDGPU::isGFX10Plus
bool isGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1457
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc3
uint32_t compute_pgm_rsrc3
Definition: AMDHSAKernelDescriptor.h:172
llvm::AMDGPU::isEntryFunctionCC
bool isEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1383
amd_kernel_code_t::amd_machine_version_minor
uint16_t amd_machine_version_minor
Definition: AMDKernelCodeT.h:531
llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1203
llvm::AMDGPU::isHsaAbiVersion2
bool isHsaAbiVersion2(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:108
llvm::AMDGPU::hasPackedD16
bool hasPackedD16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1429
llvm::AMDGPU::Hwreg::getLastSymbolicHwreg
static unsigned getLastSymbolicHwreg(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1009
llvm::AMDGPU::SendMsg::ID_ORDERED_PS_DONE
@ ID_ORDERED_PS_DONE
Definition: SIDefines.h:311
llvm::AMDGPU::MTBUFFormat::NFMT_MIN
@ NFMT_MIN
Definition: SIDefines.h:482
llvm::CallingConv::AMDGPU_CS
@ AMDGPU_CS
Calling convention used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:213
llvm::AMDGPU::SMInfo::IsBuffer
bool IsBuffer
Definition: AMDGPUBaseInfo.cpp:207
llvm::AMDGPU::Hwreg::OFFSET_MASK_
@ OFFSET_MASK_
Definition: SIDefines.h:394
llvm::AMDGPU::Hwreg::isValidHwregWidth
bool isValidHwregWidth(int64_t Width)
Definition: AMDGPUBaseInfo.cpp:1034
llvm::AMDGPU::shouldEmitConstantsToTextSection
bool shouldEmitConstantsToTextSection(const Triple &TT)
Definition: AMDGPUBaseInfo.cpp:850
llvm::AMDGPU::Hwreg::WIDTH_M1_SHIFT_
@ WIDTH_M1_SHIFT_
Definition: SIDefines.h:404
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:120
llvm::Triple::AMDHSA
@ AMDHSA
Definition: Triple.h:193
llvm::AMDGPU::isVI
bool isVI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1441
llvm::AMDGPU::MUBUFInfo::BaseOpcode
uint16_t BaseOpcode
Definition: AMDGPUBaseInfo.cpp:188
llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:150
llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE
@ FLOAT_DENORM_MODE_FLUSH_NONE
Definition: AMDHSAKernelDescriptor.h:63
llvm::AMDGPU::isInlinableLiteralV216
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:1774
llvm::cl::opt
Definition: CommandLine.h:1432
llvm::AMDGPU::Exp::ET_PARAM_MAX_IDX
@ ET_PARAM_MAX_IDX
Definition: SIDefines.h:760
llvm::AMDGPU::getRegBitWidth
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
Definition: AMDGPUBaseInfo.cpp:1610
llvm::AMDGPU::MTBUFFormat::NFMT_MAX
@ NFMT_MAX
Definition: SIDefines.h:483
llvm::AMDGPU::getExpcntBitMask
unsigned getExpcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:903
llvm::MCInstrDesc::NumOperands
unsigned short NumOperands
Definition: MCInstrDesc.h:198
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::divideCeil
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:742
llvm::AMDGPU::isHsaAbiVersion4
bool isHsaAbiVersion4(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:120
llvm::AMDGPU::IsaInfo::getMinNumSGPRs
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:624
llvm::AMDGPU::isInlinableIntLiteral
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
Definition: AMDGPUBaseInfo.h:840
llvm::AMDGPU::hasG16
bool hasG16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1425
AMDGPUMCTargetDesc.h
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:390
llvm::isUInt< 16 >
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:408
llvm::AMDGPU::SMInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:206
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
uint64_t
llvm::AMDGPU::MTBUFFormat::NFMT_MASK
@ NFMT_MASK
Definition: SIDefines.h:489
llvm::Triple::getOS
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:319
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:162
llvm::AMDGPU::isGFX9
bool isGFX9(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1445
llvm::AMDGPU::MTBUFFormat::DFMT_SHIFT
@ DFMT_SHIFT
Definition: SIDefines.h:467
llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V2
@ ELFABIVERSION_AMDGPU_HSA_V2
Definition: ELF.h:374
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:95
llvm::AMDGPU::initDefaultAMDKernelCodeT
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:766
llvm::AMDGPU::getIntegerAttribute
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
Definition: AMDGPUBaseInfo.cpp:854
llvm::CallingConv::SPIR_KERNEL
@ SPIR_KERNEL
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:152
llvm::AMDGPU::VOPInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:211
llvm::AMDGPU::OPERAND_SRC_FIRST
@ OPERAND_SRC_FIRST
Definition: SIDefines.h:193
amd_kernel_code_t::call_convention
int32_t call_convention
Definition: AMDKernelCodeT.h:645
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition: MCSubtargetInfo.h:108
llvm::AMDGPU::MUBUFInfo::IsBufferInv
bool IsBufferInv
Definition: AMDGPUBaseInfo.cpp:193
llvm::DenormalMode
Represent subnormal handling kind for floating point instruction inputs and outputs.
Definition: FloatingPointMode.h:67
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4
@ ELFABIVERSION_AMDGPU_HSA_V4
Definition: ELF.h:376
llvm::AMDGPU::getGcnBufferFormatInfo
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2006
llvm::AMDGPU::SendMsg::OP_UNKNOWN_
@ OP_UNKNOWN_
Definition: SIDefines.h:325
llvm::AMDGPU::IsaInfo::getWavefrontSize
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:518
llvm::isUInt< 32 >
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:411
llvm::AMDGPU::isSISrcInlinableOperand
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this opearnd support only inlinable literals?
Definition: AMDGPUBaseInfo.cpp:1601
llvm::AMDGPU::Hwreg::isValidHwregOffset
bool isValidHwregOffset(int64_t Offset)
Definition: AMDGPUBaseInfo.cpp:1030
llvm::AMDGPU::SIModeRegisterDefaults::DX10Clamp
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
Definition: AMDGPUBaseInfo.h:924
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AMDGPU::encodeVmcnt
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
Definition: AMDGPUBaseInfo.cpp:960
llvm::isUInt< 8 >
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:405
llvm::AMDGPU::getAddrSizeMIMGOp
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
Definition: AMDGPUBaseInfo.cpp:158
llvm::AMDGPU::SendMsg::msgRequiresOp
bool msgRequiresOp(int64_t MsgId)
Definition: AMDGPUBaseInfo.cpp:1314
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::getXnackSetting
TargetIDSetting getXnackSetting() const
Definition: AMDGPUBaseInfo.h:115
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16InputDenormals
bool FP64FP16InputDenormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
Definition: AMDGPUBaseInfo.h:933
amd_kernel_code_t::amd_machine_version_stepping
uint16_t amd_machine_version_stepping
Definition: AMDKernelCodeT.h:532
amd_kernel_code_t::group_segment_alignment
uint8_t group_segment_alignment
Definition: AMDKernelCodeT.h:635
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
llvm::AMDGPU::Waitcnt::LgkmCnt
unsigned LgkmCnt
Definition: AMDGPUBaseInfo.h:476
llvm::AMDGPU::Exp::isSupportedTgtId
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1111
llvm::AMDGPU::IsaInfo::getTotalNumSGPRs
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:605
llvm::AMDGPU::getMIMGInfo
const LLVM_READONLY MIMGInfo * getMIMGInfo(unsigned Opc)
llvm::AMDGPU::VOPInfo
Definition: AMDGPUBaseInfo.cpp:210
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:164
llvm::AMDGPU::Exp::ET_MRT0
@ ET_MRT0
Definition: SIDefines.h:743
llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:612
llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:151
AmdhsaCodeObjectVersion
static llvm::cl::opt< unsigned > AmdhsaCodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden, llvm::cl::desc("AMDHSA Code Object Version"), llvm::cl::init(4), llvm::cl::ZeroOrMore)
llvm::DenormalMode::IEEE
@ IEEE
IEEE-754 denormal numbers preserved.
Definition: FloatingPointMode.h:74
llvm::AMDGPU::IsaInfo::getNumSGPRBlocks
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
Definition: AMDGPUBaseInfo.cpp:689
amd_kernel_code_t::kernarg_segment_alignment
uint8_t kernarg_segment_alignment
The maximum byte alignment of variables used by the kernel in the specified memory segment.
Definition: AMDKernelCodeT.h:634
amd_kernel_code_t::amd_kernel_code_version_minor
uint32_t amd_kernel_code_version_minor
Definition: AMDKernelCodeT.h:528
llvm::AMDGPU::Exp::ExpTgtInfo
static constexpr ExpTgt ExpTgtInfo[]
Definition: AMDGPUBaseInfo.cpp:1068
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:177
llvm::AMDGPU::IsaInfo::TargetIDSetting::Off
@ Off
llvm::AMDGPU::MTBUFFormat::DFMT_MIN
@ DFMT_MIN
Definition: SIDefines.h:461
llvm::AMDGPU::MIMGInfo::BaseOpcode
uint16_t BaseOpcode
Definition: AMDGPUBaseInfo.h:361
llvm::AMDGPU::isInlinableLiteral16
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:1755
llvm::AMDGPU::getMIMGBaseOpcodeInfo
const LLVM_READONLY MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
llvm::AMDGPU::CPol::SCC
@ SCC
Definition: SIDefines.h:295
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicGFX10
const StringLiteral NfmtSymbolicGFX10[]
Definition: AMDGPUAsmUtils.cpp:114
llvm::AMDGPU::isDwordAligned
static bool isDwordAligned(uint64_t ByteOffset)
Definition: AMDGPUBaseInfo.cpp:1862
llvm::AMDGPU::SendMsg::msgSupportsStream
bool msgSupportsStream(int64_t MsgId, int64_t OpId)
Definition: AMDGPUBaseInfo.cpp:1318
llvm::AMDGPU::Exp::ExpTgt::Tgt
unsigned Tgt
Definition: AMDGPUBaseInfo.cpp:1064
llvm::AMDGPU::hasSMRDSignedImmOffset
static bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST)
Definition: AMDGPUBaseInfo.cpp:1844
llvm::AMDGPU::Exp::ET_MRTZ
@ ET_MRTZ
Definition: SIDefines.h:745
llvm::AMDGPU::Hwreg::ID_XNACK_MASK
@ ID_XNACK_MASK
Definition: SIDefines.h:380
llvm::AMDGPU::Exp::ExpTgt::MaxIndex
unsigned MaxIndex
Definition: AMDGPUBaseInfo.cpp:1065
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
AMDGPU.h
MAP_REG2REG
#define MAP_REG2REG
Definition: AMDGPUBaseInfo.cpp:1497
llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V3
@ ELFABIVERSION_AMDGPU_HSA_V3
Definition: ELF.h:375
llvm::AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
Definition: AMDGPUBaseInfo.h:74
llvm::AMDGPU::getVOP3IsSingle
bool getVOP3IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:309
llvm::AMDGPU::Hwreg::OFFSET_SHIFT_
@ OFFSET_SHIFT_
Definition: SIDefines.h:392
llvm::AMDGPU::isModuleEntryFunctionCC
bool isModuleEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1400
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::AMDGPU::isCompute
bool isCompute(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1379
llvm::AMDGPU::IsaInfo::getVGPREncodingGranule
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:710
llvm::MCRegisterClass::getID
unsigned getID() const
getID() - Return the register class ID number.
Definition: MCRegisterInfo.h:48
uint32_t
llvm::AMDGPU::IsaInfo::getNumVGPRBlocks
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:756
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::AMDGPU::MIMGBaseOpcodeInfo::Coordinates
bool Coordinates
Definition: AMDGPUBaseInfo.h:291
llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
Definition: AMDGPUBaseInfo.cpp:1848
llvm::AMDGPU::isSISrcOperand
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
Definition: AMDGPUBaseInfo.cpp:1565
llvm::AMDGPU::isGraphics
bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1375
amd_kernel_code_t
AMD Kernel Code Object (amd_kernel_code_t).
Definition: AMDKernelCodeT.h:526
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackSupported
bool isXnackSupported() const
Definition: AMDGPUBaseInfo.h:96
llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:582
llvm::AMDGPU::Exp::getTgtName
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
Definition: AMDGPUBaseInfo.cpp:1077
llvm::AMDGPU::Waitcnt::VmCnt
unsigned VmCnt
Definition: AMDGPUBaseInfo.h:474
llvm::AMDGPU::getMTBUFHasVAddr
bool getMTBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:244
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
AMDHSA_BITS_SET
#define AMDHSA_BITS_SET(DST, MSK, VAL)
Definition: AMDHSAKernelDescriptor.h:42
llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt)
Definition: AMDGPUBaseInfo.cpp:1194
amd_kernel_code_t::kernel_code_entry_byte_offset
int64_t kernel_code_entry_byte_offset
Byte offset (possibly negative) from start of amd_kernel_code_t object to kernel's entry point instru...
Definition: AMDKernelCodeT.h:544
llvm::AMDGPU::MTBUFFormat::DfmtNfmt2UFmt
const unsigned DfmtNfmt2UFmt[]
Definition: AMDGPUAsmUtils.cpp:241
llvm::AMDGPU::GcnBufferFormatInfo
Definition: AMDGPUBaseInfo.h:54
llvm::AMDGPU::SendMsg::ID_GS
@ ID_GS
Definition: SIDefines.h:306
llvm::AMDGPU::isGFX9Plus
bool isGFX9Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1449
llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:802
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPU::SendMsg::ID_GS_DONE
@ ID_GS_DONE
Definition: SIDefines.h:307
amd_kernel_code_t::amd_machine_kind
uint16_t amd_machine_kind
Definition: AMDKernelCodeT.h:529
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: AMDGPUBaseInfo.h:934
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:216
llvm::AMDGPU::isGroupSegment
bool isGroupSegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:836
llvm::AMDGPU::SendMsg::STREAM_ID_FIRST_
@ STREAM_ID_FIRST_
Definition: SIDefines.h:351
llvm::AMDGPU::SMInfo
Definition: AMDGPUBaseInfo.cpp:205
llvm::AMDGPU::MTBUFFormat::UFMT_LAST
@ UFMT_LAST
Definition: SIDefines.h:597
llvm::AMDGPU::Hwreg::IdSymbolic
const char *const IdSymbolic[]
Definition: AMDGPUAsmUtils.cpp:58
llvm::AMDGPU::encodeWaitcnt
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
Definition: AMDGPUBaseInfo.cpp:982
llvm::AMDGPU::SendMsg::isValidMsgOp
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1269
llvm::AMDGPU::SendMsg::OP_SYS_FIRST_
@ OP_SYS_FIRST_
Definition: SIDefines.h:344
Attributes.h
llvm::isInt< 16 >
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:370
llvm::AMDGPU::isSI
bool isSI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1433
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:178
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString
std::string toString() const
Definition: AMDGPUBaseInfo.cpp:412
amd_kernel_code_t::amd_machine_version_major
uint16_t amd_machine_version_major
Definition: AMDKernelCodeT.h:530
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::Any
Definition: Any.h:26
llvm::AMDGPU::IsaInfo::TRAP_NUM_SGPRS
@ TRAP_NUM_SGPRS
Definition: AMDGPUBaseInfo.h:75
llvm::AMDGPU::OPERAND_SRC_LAST
@ OPERAND_SRC_LAST
Definition: SIDefines.h:194
llvm::AMDGPU::isArgPassedInSGPR
bool isArgPassedInSGPR(const Argument *A)
Definition: AMDGPUBaseInfo.cpp:1813
llvm::AMDGPU::Waitcnt
Represents the counter values to wait for in an s_waitcnt instruction.
Definition: AMDGPUBaseInfo.h:473
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
amd_kernel_code_t::private_segment_alignment
uint8_t private_segment_alignment
Definition: AMDKernelCodeT.h:636
llvm::AMDGPU::SIModeRegisterDefaults::SIModeRegisterDefaults
SIModeRegisterDefaults()
Definition: AMDGPUBaseInfo.h:936
llvm::AMDGPU::getMUBUFHasVAddr
bool getMUBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:274
llvm::AMDGPU::isInlinableLiteral64
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
Definition: AMDGPUBaseInfo.cpp:1712
llvm::AMDGPU::OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:153
uint16_t
llvm::AMDGPU::getMUBUFElements
int getMUBUFElements(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:269
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_DEFAULT
@ DFMT_NFMT_DEFAULT
Definition: SIDefines.h:494
llvm::AMDGPU::SendMsg::getMsgOpId
int64_t getMsgOpId(int64_t MsgId, const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1257
llvm::AMDGPU::Exp::ET_POS4
@ ET_POS4
Definition: SIDefines.h:749
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::FPOpFusion::Strict
@ Strict
Definition: TargetOptions.h:39
amd_kernel_code_t::code_properties
uint32_t code_properties
Code properties.
Definition: AMDKernelCodeT.h:562
llvm::AMDGPU::SendMsg::ID_GET_DDID
@ ID_GET_DDID
Definition: SIDefines.h:315
llvm::AMDGPU::isFoldableLiteralV216
bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:1800
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:165
llvm::AMDGPU::MIMGInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.h:360
Function.h
llvm::AMDGPU::MUBUFInfo::has_vaddr
bool has_vaddr
Definition: AMDGPUBaseInfo.cpp:190
llvm::AMDGPU::OPERAND_REG_INLINE_C_FIRST
@ OPERAND_REG_INLINE_C_FIRST
Definition: SIDefines.h:187
llvm::amdhsa::kernel_descriptor_t
Definition: AMDHSAKernelDescriptor.h:165
llvm::AMDGPU::getVOP1IsSingle
bool getVOP1IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:299
llvm::AMDGPU::SendMsg::ID_UNKNOWN_
@ ID_UNKNOWN_
Definition: SIDefines.h:304
llvm::CallingConv::AMDGPU_VS
@ AMDGPU_VS
Calling convention used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (ve...
Definition: CallingConv.h:204
llvm::AMDGPU::splitMUBUFOffset
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, Align Alignment)
Definition: AMDGPUBaseInfo.cpp:1916
llvm::AMDGPU::SendMsg::STREAM_ID_NONE_
@ STREAM_ID_NONE_
Definition: SIDefines.h:348
llvm::CallingConv::AMDGPU_HS
@ AMDGPU_HS
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:223
llvm::AMDGPU::MIMGInfo
Definition: AMDGPUBaseInfo.h:359
llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
Definition: AMDGPUBaseInfo.cpp:1173
llvm::AMDGPU::Exp::getTgtId
unsigned getTgtId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1088
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicSICI
const StringLiteral NfmtSymbolicSICI[]
Definition: AMDGPUAsmUtils.cpp:125
llvm::CallingConv::AMDGPU_LS
@ AMDGPU_LS
Calling convention used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:231
llvm::AMDGPU::MTBUFFormat::NFMT_SHIFT
@ NFMT_SHIFT
Definition: SIDefines.h:488
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:167
llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:730
llvm::AMDGPU::SendMsg::decodeMsg
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId)
Definition: AMDGPUBaseInfo.cpp:1322
llvm::AMDGPU::SendMsg::isValidMsgStream
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1294
llvm::AMDGPU::MTBUFFormat::getNfmtName
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1153
AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32
@ AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32
Definition: AMDKernelCodeT.h:127
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_
@ ID_SYMBOLIC_FIRST_
Definition: SIDefines.h:363
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc1
uint32_t compute_pgm_rsrc1
Definition: AMDHSAKernelDescriptor.h:173
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:413
llvm::AMDGPU::SendMsg::STREAM_ID_SHIFT_
@ STREAM_ID_SHIFT_
Definition: SIDefines.h:352
llvm::AMDGPU::getLgkmcntBitMask
unsigned getLgkmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:907
llvm::GlobalValue::getAddressSpace
unsigned getAddressSpace() const
Definition: Globals.cpp:112
llvm::GCNSubtarget::getGeneration
Generation getGeneration() const
Definition: GCNSubtarget.h:258
llvm::AMDGPU::Hwreg::WIDTH_M1_MASK_
@ WIDTH_M1_MASK_
Definition: SIDefines.h:406
llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs
uint8_t NumExtraArgs
Definition: AMDGPUBaseInfo.h:288
llvm::AMDGPU::isInlinableLiteral32
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:1729
llvm::AMDGPU::isSISrcFPOperand
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
Definition: AMDGPUBaseInfo.cpp:1572
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constexpr bool test(unsigned I) const
Definition: SubtargetFeature.h:90
llvm::AMDGPU::encodeExpcnt
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
Definition: AMDGPUBaseInfo.cpp:971
llvm::AMDGPU::isRegIntersect
bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
Is there any intersection between registers.
Definition: AMDGPUBaseInfo.cpp:1490
llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName
StringRef getUnifiedFormatName(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1186
llvm::AMDGPU::Exp::ET_POS_MAX_IDX
@ ET_POS_MAX_IDX
Definition: SIDefines.h:759
llvm::AMDGPU::isGCN3Encoding
bool isGCN3Encoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1459
llvm::AMDGPU::MTBUFFormat::getNfmt
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1144
llvm::AMDGPU::Exp::ExpTgt
Definition: AMDGPUBaseInfo.cpp:1062
llvm::AMDGPU::Exp::ET_PRIM_MAX_IDX
@ ET_PRIM_MAX_IDX
Definition: SIDefines.h:757
llvm::AMDGPU::getNumFlatOffsetBits
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed)
For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
Definition: AMDGPUBaseInfo.cpp:1901
N
#define N
AMDKernelCodeT.h
llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:572
llvm::AMDGPU::IsaInfo::getMaxWavesPerEU
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:563
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::AMDGPU::IsaInfo::getMinNumVGPRs
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:736
llvm::AMDGPU::Hwreg::getHwregId
int64_t getHwregId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1001
llvm::AMDGPU::hasMIMG_R128
bool hasMIMG_R128(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1417
llvm::AMDGPU::MIMGBaseOpcodeInfo::G16
bool G16
Definition: AMDGPUBaseInfo.h:290
llvm::AMDGPU::Exp::ET_NULL_MAX_IDX
@ ET_NULL_MAX_IDX
Definition: SIDefines.h:755
llvm::DenormalMode::Output
DenormalModeKind Output
Denormal flushing mode for floating point instruction results in the default floating point environme...
Definition: FloatingPointMode.h:85
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:161
llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumVGPRs
constexpr char NumVGPRs[]
Key for Kernel::CodeProps::Metadata::mNumVGPRs.
Definition: AMDGPUMetadata.h:255
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setTargetIDFromFeaturesString
void setTargetIDFromFeaturesString(StringRef FS)
Definition: AMDGPUBaseInfo.cpp:332
llvm::AMDGPU::isReadOnlySegment
bool isReadOnlySegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:844
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_LAST_
@ ID_SYMBOLIC_LAST_
Definition: SIDefines.h:384
llvm::AMDGPU::SendMsg::OP_NONE_
@ OP_NONE_
Definition: SIDefines.h:327
llvm::AMDGPU::isLegalSMRDEncodedSignedOffset
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
Definition: AMDGPUBaseInfo.cpp:1854
llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
Definition: AMDGPU.h:366
llvm::AMDGPU::OPERAND_REG_IMM_FP16
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:149
S_00B848_WGP_MODE
#define S_00B848_WGP_MODE(x)
Definition: SIDefines.h:877
LLVMContext.h
llvm::AMDGPU::encodeLgkmcnt
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
Definition: AMDGPUBaseInfo.cpp:976
llvm::cl::desc
Definition: CommandLine.h:412
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:179
llvm::AMDGPU::MTBUFFormat::getDfmt
int64_t getDfmt(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1123
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:231
llvm::AMDGPU::isHsaAbiVersion3Or4
bool isHsaAbiVersion3Or4(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:126
llvm::AMDGPU::Waitcnt::ExpCnt
unsigned ExpCnt
Definition: AMDGPUBaseInfo.h:475
llvm::AMDGPU::getIntegerPairAttribute
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
Definition: AMDGPUBaseInfo.cpp:869
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isSramEccSupported
bool isSramEccSupported() const
Definition: AMDGPUBaseInfo.h:125
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
llvm::AMDGPU::MTBUFInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:197
llvm::AMDGPU::MTBUFInfo::has_srsrc
bool has_srsrc
Definition: AMDGPUBaseInfo.cpp:201
llvm::AMDGPU::SendMsg::isValidMsgId
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1229
llvm::AMDGPU::SendMsg::OP_MASK_
@ OP_MASK_
Definition: SIDefines.h:330
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::AMDGPU::MUBUFInfo
Definition: AMDGPUBaseInfo.cpp:186
llvm::AMDGPU::Exp::ET_MRT_MAX_IDX
@ ET_MRT_MAX_IDX
Definition: SIDefines.h:758
llvm::AMDGPU::SendMsg::ID_HALT_WAVES
@ ID_HALT_WAVES
Definition: SIDefines.h:310
llvm::AMDGPU::getHasColorExport
bool getHasColorExport(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1349
llvm::AMDGPU::getHasDepthExport
bool getHasDepthExport(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1356
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_GFX10_
@ ID_SYMBOLIC_FIRST_GFX10_
Definition: SIDefines.h:374
llvm::AMDGPU::IsaInfo::getVGPRAllocGranule
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:695
llvm::AMDGPU::getMaskedMIMGOp
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
Definition: AMDGPUBaseInfo.cpp:150
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
llvm::AMDGPU::getMTBUFElements
int getMTBUFElements(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:239
llvm::AMDGPU::OPERAND_REG_INLINE_C_LAST
@ OPERAND_REG_INLINE_C_LAST
Definition: SIDefines.h:188
AMDGPUBaseInfo.h
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:180
llvm::AMDGPU::MTBUFFormat::DFMT_MAX
@ DFMT_MAX
Definition: SIDefines.h:462
llvm::AMDGPU::MIMGDimInfo::NumCoords
uint8_t NumCoords
Definition: AMDGPUBaseInfo.h:306