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AMDGPUBaseInfo.cpp
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1 //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AMDGPUBaseInfo.h"
10 #include "AMDGPU.h"
11 #include "AMDGPUAsmUtils.h"
12 #include "AMDKernelCodeT.h"
13 #include "GCNSubtarget.h"
15 #include "llvm/BinaryFormat/ELF.h"
16 #include "llvm/IR/Attributes.h"
17 #include "llvm/IR/Function.h"
18 #include "llvm/IR/GlobalValue.h"
19 #include "llvm/IR/IntrinsicsAMDGPU.h"
20 #include "llvm/IR/IntrinsicsR600.h"
21 #include "llvm/IR/LLVMContext.h"
26 
27 #define GET_INSTRINFO_NAMED_OPS
28 #define GET_INSTRMAP_INFO
29 #include "AMDGPUGenInstrInfo.inc"
30 
32  AmdhsaCodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden,
33  llvm::cl::desc("AMDHSA Code Object Version"),
34  llvm::cl::init(4));
35 
36 namespace {
37 
38 /// \returns Bit mask for given bit \p Shift and bit \p Width.
39 unsigned getBitMask(unsigned Shift, unsigned Width) {
40  return ((1 << Width) - 1) << Shift;
41 }
42 
43 /// Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
44 ///
45 /// \returns Packed \p Dst.
46 unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
47  unsigned Mask = getBitMask(Shift, Width);
48  return ((Src << Shift) & Mask) | (Dst & ~Mask);
49 }
50 
51 /// Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
52 ///
53 /// \returns Unpacked bits.
54 unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
55  return (Src & getBitMask(Shift, Width)) >> Shift;
56 }
57 
58 /// \returns Vmcnt bit shift (lower bits).
59 unsigned getVmcntBitShiftLo(unsigned VersionMajor) {
60  return VersionMajor >= 11 ? 10 : 0;
61 }
62 
63 /// \returns Vmcnt bit width (lower bits).
64 unsigned getVmcntBitWidthLo(unsigned VersionMajor) {
65  return VersionMajor >= 11 ? 6 : 4;
66 }
67 
68 /// \returns Expcnt bit shift.
69 unsigned getExpcntBitShift(unsigned VersionMajor) {
70  return VersionMajor >= 11 ? 0 : 4;
71 }
72 
73 /// \returns Expcnt bit width.
74 unsigned getExpcntBitWidth(unsigned VersionMajor) { return 3; }
75 
76 /// \returns Lgkmcnt bit shift.
77 unsigned getLgkmcntBitShift(unsigned VersionMajor) {
78  return VersionMajor >= 11 ? 4 : 8;
79 }
80 
81 /// \returns Lgkmcnt bit width.
82 unsigned getLgkmcntBitWidth(unsigned VersionMajor) {
83  return VersionMajor >= 10 ? 6 : 4;
84 }
85 
86 /// \returns Vmcnt bit shift (higher bits).
87 unsigned getVmcntBitShiftHi(unsigned VersionMajor) { return 14; }
88 
89 /// \returns Vmcnt bit width (higher bits).
90 unsigned getVmcntBitWidthHi(unsigned VersionMajor) {
91  return (VersionMajor == 9 || VersionMajor == 10) ? 2 : 0;
92 }
93 
94 } // end namespace anonymous
95 
96 namespace llvm {
97 
98 namespace AMDGPU {
99 
101  if (STI && STI->getTargetTriple().getOS() != Triple::AMDHSA)
102  return None;
103 
104  switch (AmdhsaCodeObjectVersion) {
105  case 2:
107  case 3:
109  case 4:
111  case 5:
113  default:
114  report_fatal_error(Twine("Unsupported AMDHSA Code Object Version ") +
116  }
117 }
118 
120  if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI))
121  return *HsaAbiVer == ELF::ELFABIVERSION_AMDGPU_HSA_V2;
122  return false;
123 }
124 
126  if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI))
127  return *HsaAbiVer == ELF::ELFABIVERSION_AMDGPU_HSA_V3;
128  return false;
129 }
130 
132  if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI))
133  return *HsaAbiVer == ELF::ELFABIVERSION_AMDGPU_HSA_V4;
134  return false;
135 }
136 
138  if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI))
139  return *HsaAbiVer == ELF::ELFABIVERSION_AMDGPU_HSA_V5;
140  return false;
141 }
142 
144  return isHsaAbiVersion3(STI) || isHsaAbiVersion4(STI) ||
145  isHsaAbiVersion5(STI);
146 }
147 
150 }
151 
153  switch (AmdhsaCodeObjectVersion) {
154  case 2:
155  case 3:
156  case 4:
157  return 48;
158  case 5:
160  default:
161  llvm_unreachable("Unexpected code object version");
162  return 0;
163  }
164 }
165 
166 
167 // FIXME: All such magic numbers about the ABI should be in a
168 // central TD file.
170  switch (AmdhsaCodeObjectVersion) {
171  case 2:
172  case 3:
173  case 4:
174  return 24;
175  case 5:
177  default:
178  llvm_unreachable("Unexpected code object version");
179  return 0;
180  }
181 }
182 
183 #define GET_MIMGBaseOpcodesTable_IMPL
184 #define GET_MIMGDimInfoTable_IMPL
185 #define GET_MIMGInfoTable_IMPL
186 #define GET_MIMGLZMappingTable_IMPL
187 #define GET_MIMGMIPMappingTable_IMPL
188 #define GET_MIMGBiasMappingTable_IMPL
189 #define GET_MIMGOffsetMappingTable_IMPL
190 #define GET_MIMGG16MappingTable_IMPL
191 #define GET_MAIInstInfoTable_IMPL
192 #include "AMDGPUGenSearchableTables.inc"
193 
194 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
195  unsigned VDataDwords, unsigned VAddrDwords) {
196  const MIMGInfo *Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding,
197  VDataDwords, VAddrDwords);
198  return Info ? Info->Opcode : -1;
199 }
200 
201 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc) {
202  const MIMGInfo *Info = getMIMGInfo(Opc);
203  return Info ? getMIMGBaseOpcodeInfo(Info->BaseOpcode) : nullptr;
204 }
205 
206 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels) {
207  const MIMGInfo *OrigInfo = getMIMGInfo(Opc);
208  const MIMGInfo *NewInfo =
209  getMIMGOpcodeHelper(OrigInfo->BaseOpcode, OrigInfo->MIMGEncoding,
210  NewChannels, OrigInfo->VAddrDwords);
211  return NewInfo ? NewInfo->Opcode : -1;
212 }
213 
214 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
215  const MIMGDimInfo *Dim, bool IsA16,
216  bool IsG16Supported) {
217  unsigned AddrWords = BaseOpcode->NumExtraArgs;
218  unsigned AddrComponents = (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
219  (BaseOpcode->LodOrClampOrMip ? 1 : 0);
220  if (IsA16)
221  AddrWords += divideCeil(AddrComponents, 2);
222  else
223  AddrWords += AddrComponents;
224 
225  // Note: For subtargets that support A16 but not G16, enabling A16 also
226  // enables 16 bit gradients.
227  // For subtargets that support A16 (operand) and G16 (done with a different
228  // instruction encoding), they are independent.
229 
230  if (BaseOpcode->Gradients) {
231  if ((IsA16 && !IsG16Supported) || BaseOpcode->G16)
232  // There are two gradients per coordinate, we pack them separately.
233  // For the 3d case,
234  // we get (dy/du, dx/du) (-, dz/du) (dy/dv, dx/dv) (-, dz/dv)
235  AddrWords += alignTo<2>(Dim->NumGradients / 2);
236  else
237  AddrWords += Dim->NumGradients;
238  }
239  return AddrWords;
240 }
241 
242 struct MUBUFInfo {
245  uint8_t elements;
246  bool has_vaddr;
247  bool has_srsrc;
250 };
251 
252 struct MTBUFInfo {
255  uint8_t elements;
256  bool has_vaddr;
257  bool has_srsrc;
259 };
260 
261 struct SMInfo {
263  bool IsBuffer;
264 };
265 
266 struct VOPInfo {
268  bool IsSingle;
269 };
270 
273 };
274 
279 };
280 
281 struct VOPDInfo {
285 };
286 
289  bool IsTrue16;
290 };
291 
292 #define GET_MTBUFInfoTable_DECL
293 #define GET_MTBUFInfoTable_IMPL
294 #define GET_MUBUFInfoTable_DECL
295 #define GET_MUBUFInfoTable_IMPL
296 #define GET_SMInfoTable_DECL
297 #define GET_SMInfoTable_IMPL
298 #define GET_VOP1InfoTable_DECL
299 #define GET_VOP1InfoTable_IMPL
300 #define GET_VOP2InfoTable_DECL
301 #define GET_VOP2InfoTable_IMPL
302 #define GET_VOP3InfoTable_DECL
303 #define GET_VOP3InfoTable_IMPL
304 #define GET_VOPC64DPPTable_DECL
305 #define GET_VOPC64DPPTable_IMPL
306 #define GET_VOPC64DPP8Table_DECL
307 #define GET_VOPC64DPP8Table_IMPL
308 #define GET_VOPDComponentTable_DECL
309 #define GET_VOPDComponentTable_IMPL
310 #define GET_VOPDPairs_DECL
311 #define GET_VOPDPairs_IMPL
312 #define GET_VOPTrue16Table_DECL
313 #define GET_VOPTrue16Table_IMPL
314 #define GET_WMMAOpcode2AddrMappingTable_DECL
315 #define GET_WMMAOpcode2AddrMappingTable_IMPL
316 #define GET_WMMAOpcode3AddrMappingTable_DECL
317 #define GET_WMMAOpcode3AddrMappingTable_IMPL
318 #include "AMDGPUGenSearchableTables.inc"
319 
320 int getMTBUFBaseOpcode(unsigned Opc) {
321  const MTBUFInfo *Info = getMTBUFInfoFromOpcode(Opc);
322  return Info ? Info->BaseOpcode : -1;
323 }
324 
325 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements) {
326  const MTBUFInfo *Info = getMTBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
327  return Info ? Info->Opcode : -1;
328 }
329 
330 int getMTBUFElements(unsigned Opc) {
331  const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
332  return Info ? Info->elements : 0;
333 }
334 
335 bool getMTBUFHasVAddr(unsigned Opc) {
336  const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
337  return Info ? Info->has_vaddr : false;
338 }
339 
340 bool getMTBUFHasSrsrc(unsigned Opc) {
341  const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
342  return Info ? Info->has_srsrc : false;
343 }
344 
345 bool getMTBUFHasSoffset(unsigned Opc) {
346  const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
347  return Info ? Info->has_soffset : false;
348 }
349 
350 int getMUBUFBaseOpcode(unsigned Opc) {
351  const MUBUFInfo *Info = getMUBUFInfoFromOpcode(Opc);
352  return Info ? Info->BaseOpcode : -1;
353 }
354 
355 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements) {
356  const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
357  return Info ? Info->Opcode : -1;
358 }
359 
360 int getMUBUFElements(unsigned Opc) {
361  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
362  return Info ? Info->elements : 0;
363 }
364 
365 bool getMUBUFHasVAddr(unsigned Opc) {
366  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
367  return Info ? Info->has_vaddr : false;
368 }
369 
370 bool getMUBUFHasSrsrc(unsigned Opc) {
371  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
372  return Info ? Info->has_srsrc : false;
373 }
374 
375 bool getMUBUFHasSoffset(unsigned Opc) {
376  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
377  return Info ? Info->has_soffset : false;
378 }
379 
380 bool getMUBUFIsBufferInv(unsigned Opc) {
381  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
382  return Info ? Info->IsBufferInv : false;
383 }
384 
385 bool getSMEMIsBuffer(unsigned Opc) {
386  const SMInfo *Info = getSMEMOpcodeHelper(Opc);
387  return Info ? Info->IsBuffer : false;
388 }
389 
390 bool getVOP1IsSingle(unsigned Opc) {
391  const VOPInfo *Info = getVOP1OpcodeHelper(Opc);
392  return Info ? Info->IsSingle : false;
393 }
394 
395 bool getVOP2IsSingle(unsigned Opc) {
396  const VOPInfo *Info = getVOP2OpcodeHelper(Opc);
397  return Info ? Info->IsSingle : false;
398 }
399 
400 bool getVOP3IsSingle(unsigned Opc) {
401  const VOPInfo *Info = getVOP3OpcodeHelper(Opc);
402  return Info ? Info->IsSingle : false;
403 }
404 
405 bool isVOPC64DPP(unsigned Opc) {
406  return isVOPC64DPPOpcodeHelper(Opc) || isVOPC64DPP8OpcodeHelper(Opc);
407 }
408 
409 bool getMAIIsDGEMM(unsigned Opc) {
410  const MAIInstInfo *Info = getMAIInstInfoHelper(Opc);
411  return Info ? Info->is_dgemm : false;
412 }
413 
414 bool getMAIIsGFX940XDL(unsigned Opc) {
415  const MAIInstInfo *Info = getMAIInstInfoHelper(Opc);
416  return Info ? Info->is_gfx940_xdl : false;
417 }
418 
419 CanBeVOPD getCanBeVOPD(unsigned Opc) {
420  const VOPDComponentInfo *Info = getVOPDComponentHelper(Opc);
421  if (Info)
422  return {Info->CanBeVOPDX, true};
423  else
424  return {false, false};
425 }
426 
427 unsigned getVOPDOpcode(unsigned Opc) {
428  const VOPDComponentInfo *Info = getVOPDComponentHelper(Opc);
429  return Info ? Info->VOPDOp : ~0u;
430 }
431 
432 bool isVOPD(unsigned Opc) {
433  return AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0X) != -1;
434 }
435 
436 bool isTrue16Inst(unsigned Opc) {
437  const VOPTrue16Info *Info = getTrue16OpcodeHelper(Opc);
438  return Info ? Info->IsTrue16 : false;
439 }
440 
441 unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc) {
442  const WMMAOpcodeMappingInfo *Info = getWMMAMappingInfoFrom2AddrOpcode(Opc);
443  return Info ? Info->Opcode3Addr : ~0u;
444 }
445 
446 unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc) {
447  const WMMAOpcodeMappingInfo *Info = getWMMAMappingInfoFrom3AddrOpcode(Opc);
448  return Info ? Info->Opcode2Addr : ~0u;
449 }
450 
451 // Wrapper for Tablegen'd function. enum Subtarget is not defined in any
452 // header files, so we need to wrap it in a function that takes unsigned
453 // instead.
454 int getMCOpcode(uint16_t Opcode, unsigned Gen) {
455  return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
456 }
457 
458 int getVOPDFull(unsigned OpX, unsigned OpY) {
459  const VOPDInfo *Info = getVOPDInfoFromComponentOpcodes(OpX, OpY);
460  return Info ? Info->Opcode : -1;
461 }
462 
463 namespace IsaInfo {
464 
466  : STI(STI), XnackSetting(TargetIDSetting::Any),
467  SramEccSetting(TargetIDSetting::Any) {
468  if (!STI.getFeatureBits().test(FeatureSupportsXNACK))
469  XnackSetting = TargetIDSetting::Unsupported;
470  if (!STI.getFeatureBits().test(FeatureSupportsSRAMECC))
471  SramEccSetting = TargetIDSetting::Unsupported;
472 }
473 
475  // Check if xnack or sramecc is explicitly enabled or disabled. In the
476  // absence of the target features we assume we must generate code that can run
477  // in any environment.
478  SubtargetFeatures Features(FS);
479  Optional<bool> XnackRequested;
480  Optional<bool> SramEccRequested;
481 
482  for (const std::string &Feature : Features.getFeatures()) {
483  if (Feature == "+xnack")
484  XnackRequested = true;
485  else if (Feature == "-xnack")
486  XnackRequested = false;
487  else if (Feature == "+sramecc")
488  SramEccRequested = true;
489  else if (Feature == "-sramecc")
490  SramEccRequested = false;
491  }
492 
493  bool XnackSupported = isXnackSupported();
494  bool SramEccSupported = isSramEccSupported();
495 
496  if (XnackRequested) {
497  if (XnackSupported) {
498  XnackSetting =
499  *XnackRequested ? TargetIDSetting::On : TargetIDSetting::Off;
500  } else {
501  // If a specific xnack setting was requested and this GPU does not support
502  // xnack emit a warning. Setting will remain set to "Unsupported".
503  if (*XnackRequested) {
504  errs() << "warning: xnack 'On' was requested for a processor that does "
505  "not support it!\n";
506  } else {
507  errs() << "warning: xnack 'Off' was requested for a processor that "
508  "does not support it!\n";
509  }
510  }
511  }
512 
513  if (SramEccRequested) {
514  if (SramEccSupported) {
515  SramEccSetting =
516  *SramEccRequested ? TargetIDSetting::On : TargetIDSetting::Off;
517  } else {
518  // If a specific sramecc setting was requested and this GPU does not
519  // support sramecc emit a warning. Setting will remain set to
520  // "Unsupported".
521  if (*SramEccRequested) {
522  errs() << "warning: sramecc 'On' was requested for a processor that "
523  "does not support it!\n";
524  } else {
525  errs() << "warning: sramecc 'Off' was requested for a processor that "
526  "does not support it!\n";
527  }
528  }
529  }
530 }
531 
532 static TargetIDSetting
534  if (FeatureString.endswith("-"))
535  return TargetIDSetting::Off;
536  if (FeatureString.endswith("+"))
537  return TargetIDSetting::On;
538 
539  llvm_unreachable("Malformed feature string");
540 }
541 
543  SmallVector<StringRef, 3> TargetIDSplit;
544  TargetID.split(TargetIDSplit, ':');
545 
546  for (const auto &FeatureString : TargetIDSplit) {
547  if (FeatureString.startswith("xnack"))
548  XnackSetting = getTargetIDSettingFromFeatureString(FeatureString);
549  if (FeatureString.startswith("sramecc"))
550  SramEccSetting = getTargetIDSettingFromFeatureString(FeatureString);
551  }
552 }
553 
554 std::string AMDGPUTargetID::toString() const {
555  std::string StringRep;
556  raw_string_ostream StreamRep(StringRep);
557 
558  auto TargetTriple = STI.getTargetTriple();
559  auto Version = getIsaVersion(STI.getCPU());
560 
561  StreamRep << TargetTriple.getArchName() << '-'
562  << TargetTriple.getVendorName() << '-'
563  << TargetTriple.getOSName() << '-'
564  << TargetTriple.getEnvironmentName() << '-';
565 
566  std::string Processor;
567  // TODO: Following else statement is present here because we used various
568  // alias names for GPUs up until GFX9 (e.g. 'fiji' is same as 'gfx803').
569  // Remove once all aliases are removed from GCNProcessors.td.
570  if (Version.Major >= 9)
571  Processor = STI.getCPU().str();
572  else
573  Processor = (Twine("gfx") + Twine(Version.Major) + Twine(Version.Minor) +
574  Twine(Version.Stepping))
575  .str();
576 
577  std::string Features;
578  if (Optional<uint8_t> HsaAbiVersion = getHsaAbiVersion(&STI)) {
579  switch (*HsaAbiVersion) {
581  // Code object V2 only supported specific processors and had fixed
582  // settings for the XNACK.
583  if (Processor == "gfx600") {
584  } else if (Processor == "gfx601") {
585  } else if (Processor == "gfx602") {
586  } else if (Processor == "gfx700") {
587  } else if (Processor == "gfx701") {
588  } else if (Processor == "gfx702") {
589  } else if (Processor == "gfx703") {
590  } else if (Processor == "gfx704") {
591  } else if (Processor == "gfx705") {
592  } else if (Processor == "gfx801") {
593  if (!isXnackOnOrAny())
595  "AMD GPU code object V2 does not support processor " +
596  Twine(Processor) + " without XNACK");
597  } else if (Processor == "gfx802") {
598  } else if (Processor == "gfx803") {
599  } else if (Processor == "gfx805") {
600  } else if (Processor == "gfx810") {
601  if (!isXnackOnOrAny())
603  "AMD GPU code object V2 does not support processor " +
604  Twine(Processor) + " without XNACK");
605  } else if (Processor == "gfx900") {
606  if (isXnackOnOrAny())
607  Processor = "gfx901";
608  } else if (Processor == "gfx902") {
609  if (isXnackOnOrAny())
610  Processor = "gfx903";
611  } else if (Processor == "gfx904") {
612  if (isXnackOnOrAny())
613  Processor = "gfx905";
614  } else if (Processor == "gfx906") {
615  if (isXnackOnOrAny())
616  Processor = "gfx907";
617  } else if (Processor == "gfx90c") {
618  if (isXnackOnOrAny())
620  "AMD GPU code object V2 does not support processor " +
621  Twine(Processor) + " with XNACK being ON or ANY");
622  } else {
624  "AMD GPU code object V2 does not support processor " +
625  Twine(Processor));
626  }
627  break;
629  // xnack.
630  if (isXnackOnOrAny())
631  Features += "+xnack";
632  // In code object v2 and v3, "sramecc" feature was spelled with a
633  // hyphen ("sram-ecc").
634  if (isSramEccOnOrAny())
635  Features += "+sram-ecc";
636  break;
639  // sramecc.
641  Features += ":sramecc-";
643  Features += ":sramecc+";
644  // xnack.
646  Features += ":xnack-";
647  else if (getXnackSetting() == TargetIDSetting::On)
648  Features += ":xnack+";
649  break;
650  default:
651  break;
652  }
653  }
654 
655  StreamRep << Processor << Features;
656 
657  StreamRep.flush();
658  return StringRep;
659 }
660 
661 unsigned getWavefrontSize(const MCSubtargetInfo *STI) {
662  if (STI->getFeatureBits().test(FeatureWavefrontSize16))
663  return 16;
664  if (STI->getFeatureBits().test(FeatureWavefrontSize32))
665  return 32;
666 
667  return 64;
668 }
669 
670 unsigned getLocalMemorySize(const MCSubtargetInfo *STI) {
671  if (STI->getFeatureBits().test(FeatureLocalMemorySize32768))
672  return 32768;
673  if (STI->getFeatureBits().test(FeatureLocalMemorySize65536))
674  return 65536;
675 
676  return 0;
677 }
678 
679 unsigned getEUsPerCU(const MCSubtargetInfo *STI) {
680  // "Per CU" really means "per whatever functional block the waves of a
681  // workgroup must share". For gfx10 in CU mode this is the CU, which contains
682  // two SIMDs.
683  if (isGFX10Plus(*STI) && STI->getFeatureBits().test(FeatureCuMode))
684  return 2;
685  // Pre-gfx10 a CU contains four SIMDs. For gfx10 in WGP mode the WGP contains
686  // two CUs, so a total of four SIMDs.
687  return 4;
688 }
689 
691  unsigned FlatWorkGroupSize) {
692  assert(FlatWorkGroupSize != 0);
693  if (STI->getTargetTriple().getArch() != Triple::amdgcn)
694  return 8;
695  unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize);
696  if (N == 1)
697  return 40;
698  N = 40 / N;
699  return std::min(N, 16u);
700 }
701 
702 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI) {
703  return 1;
704 }
705 
706 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI) {
707  // FIXME: Need to take scratch memory into account.
708  if (isGFX90A(*STI))
709  return 8;
710  if (!isGFX10Plus(*STI))
711  return 10;
712  return hasGFX10_3Insts(*STI) ? 16 : 20;
713 }
714 
716  unsigned FlatWorkGroupSize) {
717  return divideCeil(getWavesPerWorkGroup(STI, FlatWorkGroupSize),
718  getEUsPerCU(STI));
719 }
720 
722  return 1;
723 }
724 
726  // Some subtargets allow encoding 2048, but this isn't tested or supported.
727  return 1024;
728 }
729 
731  unsigned FlatWorkGroupSize) {
732  return divideCeil(FlatWorkGroupSize, getWavefrontSize(STI));
733 }
734 
735 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI) {
737  if (Version.Major >= 10)
738  return getAddressableNumSGPRs(STI);
739  if (Version.Major >= 8)
740  return 16;
741  return 8;
742 }
743 
745  return 8;
746 }
747 
748 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI) {
750  if (Version.Major >= 8)
751  return 800;
752  return 512;
753 }
754 
756  if (STI->getFeatureBits().test(FeatureSGPRInitBug))
758 
760  if (Version.Major >= 10)
761  return 106;
762  if (Version.Major >= 8)
763  return 102;
764  return 104;
765 }
766 
767 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
768  assert(WavesPerEU != 0);
769 
771  if (Version.Major >= 10)
772  return 0;
773 
774  if (WavesPerEU >= getMaxWavesPerEU(STI))
775  return 0;
776 
777  unsigned MinNumSGPRs = getTotalNumSGPRs(STI) / (WavesPerEU + 1);
778  if (STI->getFeatureBits().test(FeatureTrapHandler))
779  MinNumSGPRs -= std::min(MinNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
780  MinNumSGPRs = alignDown(MinNumSGPRs, getSGPRAllocGranule(STI)) + 1;
781  return std::min(MinNumSGPRs, getAddressableNumSGPRs(STI));
782 }
783 
784 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
785  bool Addressable) {
786  assert(WavesPerEU != 0);
787 
788  unsigned AddressableNumSGPRs = getAddressableNumSGPRs(STI);
790  if (Version.Major >= 10)
791  return Addressable ? AddressableNumSGPRs : 108;
792  if (Version.Major >= 8 && !Addressable)
793  AddressableNumSGPRs = 112;
794  unsigned MaxNumSGPRs = getTotalNumSGPRs(STI) / WavesPerEU;
795  if (STI->getFeatureBits().test(FeatureTrapHandler))
796  MaxNumSGPRs -= std::min(MaxNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
797  MaxNumSGPRs = alignDown(MaxNumSGPRs, getSGPRAllocGranule(STI));
798  return std::min(MaxNumSGPRs, AddressableNumSGPRs);
799 }
800 
801 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
802  bool FlatScrUsed, bool XNACKUsed) {
803  unsigned ExtraSGPRs = 0;
804  if (VCCUsed)
805  ExtraSGPRs = 2;
806 
808  if (Version.Major >= 10)
809  return ExtraSGPRs;
810 
811  if (Version.Major < 8) {
812  if (FlatScrUsed)
813  ExtraSGPRs = 4;
814  } else {
815  if (XNACKUsed)
816  ExtraSGPRs = 4;
817 
818  if (FlatScrUsed ||
819  STI->getFeatureBits().test(AMDGPU::FeatureArchitectedFlatScratch))
820  ExtraSGPRs = 6;
821  }
822 
823  return ExtraSGPRs;
824 }
825 
826 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
827  bool FlatScrUsed) {
828  return getNumExtraSGPRs(STI, VCCUsed, FlatScrUsed,
829  STI->getFeatureBits().test(AMDGPU::FeatureXNACK));
830 }
831 
832 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs) {
834  // SGPRBlocks is actual number of SGPR blocks minus 1.
835  return NumSGPRs / getSGPREncodingGranule(STI) - 1;
836 }
837 
839  Optional<bool> EnableWavefrontSize32) {
840  if (STI->getFeatureBits().test(FeatureGFX90AInsts))
841  return 8;
842 
843  bool IsWave32 = EnableWavefrontSize32 ?
844  *EnableWavefrontSize32 :
845  STI->getFeatureBits().test(FeatureWavefrontSize32);
846 
847  if (STI->getFeatureBits().test(FeatureGFX11FullVGPRs))
848  return IsWave32 ? 24 : 12;
849 
850  if (hasGFX10_3Insts(*STI))
851  return IsWave32 ? 16 : 8;
852 
853  return IsWave32 ? 8 : 4;
854 }
855 
857  Optional<bool> EnableWavefrontSize32) {
858  if (STI->getFeatureBits().test(FeatureGFX90AInsts))
859  return 8;
860 
861  bool IsWave32 = EnableWavefrontSize32 ?
862  *EnableWavefrontSize32 :
863  STI->getFeatureBits().test(FeatureWavefrontSize32);
864 
865  return IsWave32 ? 8 : 4;
866 }
867 
868 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {
869  if (STI->getFeatureBits().test(FeatureGFX90AInsts))
870  return 512;
871  if (!isGFX10Plus(*STI))
872  return 256;
873  bool IsWave32 = STI->getFeatureBits().test(FeatureWavefrontSize32);
874  if (STI->getFeatureBits().test(FeatureGFX11FullVGPRs))
875  return IsWave32 ? 1536 : 768;
876  return IsWave32 ? 1024 : 512;
877 }
878 
880  if (STI->getFeatureBits().test(FeatureGFX90AInsts))
881  return 512;
882  return 256;
883 }
884 
885 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
886  assert(WavesPerEU != 0);
887 
888  if (WavesPerEU >= getMaxWavesPerEU(STI))
889  return 0;
890  unsigned MinNumVGPRs =
891  alignDown(getTotalNumVGPRs(STI) / (WavesPerEU + 1),
892  getVGPRAllocGranule(STI)) + 1;
893  return std::min(MinNumVGPRs, getAddressableNumVGPRs(STI));
894 }
895 
896 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
897  assert(WavesPerEU != 0);
898 
899  unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(STI) / WavesPerEU,
900  getVGPRAllocGranule(STI));
901  unsigned AddressableNumVGPRs = getAddressableNumVGPRs(STI);
902  return std::min(MaxNumVGPRs, AddressableNumVGPRs);
903 }
904 
905 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs,
906  Optional<bool> EnableWavefrontSize32) {
908  getVGPREncodingGranule(STI, EnableWavefrontSize32));
909  // VGPRBlocks is actual number of VGPR blocks minus 1.
910  return NumVGPRs / getVGPREncodingGranule(STI, EnableWavefrontSize32) - 1;
911 }
912 
913 } // end namespace IsaInfo
914 
916  const MCSubtargetInfo *STI) {
918 
919  memset(&Header, 0, sizeof(Header));
920 
923  Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
924  Header.amd_machine_version_major = Version.Major;
925  Header.amd_machine_version_minor = Version.Minor;
926  Header.amd_machine_version_stepping = Version.Stepping;
927  Header.kernel_code_entry_byte_offset = sizeof(Header);
928  Header.wavefront_size = 6;
929 
930  // If the code object does not support indirect functions, then the value must
931  // be 0xffffffff.
932  Header.call_convention = -1;
933 
934  // These alignment values are specified in powers of two, so alignment =
935  // 2^n. The minimum alignment is 2^4 = 16.
936  Header.kernarg_segment_alignment = 4;
937  Header.group_segment_alignment = 4;
938  Header.private_segment_alignment = 4;
939 
940  if (Version.Major >= 10) {
941  if (STI->getFeatureBits().test(FeatureWavefrontSize32)) {
942  Header.wavefront_size = 5;
944  }
946  S_00B848_WGP_MODE(STI->getFeatureBits().test(FeatureCuMode) ? 0 : 1) |
948  }
949 }
950 
952  const MCSubtargetInfo *STI) {
954 
956  memset(&KD, 0, sizeof(KD));
957 
959  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64,
962  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, 1);
964  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE, 1);
966  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, 1);
967  if (Version.Major >= 10) {
969  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
970  STI->getFeatureBits().test(FeatureWavefrontSize32) ? 1 : 0);
972  amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE,
973  STI->getFeatureBits().test(FeatureCuMode) ? 0 : 1);
975  amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED, 1);
976  }
977  if (AMDGPU::isGFX90A(*STI)) {
979  amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT,
980  STI->getFeatureBits().test(FeatureTgSplit) ? 1 : 0);
981  }
982  return KD;
983 }
984 
985 bool isGroupSegment(const GlobalValue *GV) {
987 }
988 
989 bool isGlobalSegment(const GlobalValue *GV) {
991 }
992 
994  unsigned AS = GV->getAddressSpace();
995  return AS == AMDGPUAS::CONSTANT_ADDRESS ||
997 }
998 
1000  return TT.getArch() == Triple::r600;
1001 }
1002 
1003 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
1004  Attribute A = F.getFnAttribute(Name);
1005  int Result = Default;
1006 
1007  if (A.isStringAttribute()) {
1008  StringRef Str = A.getValueAsString();
1009  if (Str.getAsInteger(0, Result)) {
1010  LLVMContext &Ctx = F.getContext();
1011  Ctx.emitError("can't parse integer attribute " + Name);
1012  }
1013  }
1014 
1015  return Result;
1016 }
1017 
1018 std::pair<int, int> getIntegerPairAttribute(const Function &F,
1019  StringRef Name,
1020  std::pair<int, int> Default,
1021  bool OnlyFirstRequired) {
1022  Attribute A = F.getFnAttribute(Name);
1023  if (!A.isStringAttribute())
1024  return Default;
1025 
1026  LLVMContext &Ctx = F.getContext();
1027  std::pair<int, int> Ints = Default;
1028  std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
1029  if (Strs.first.trim().getAsInteger(0, Ints.first)) {
1030  Ctx.emitError("can't parse first integer attribute " + Name);
1031  return Default;
1032  }
1033  if (Strs.second.trim().getAsInteger(0, Ints.second)) {
1034  if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
1035  Ctx.emitError("can't parse second integer attribute " + Name);
1036  return Default;
1037  }
1038  }
1039 
1040  return Ints;
1041 }
1042 
1044  return (1 << (getVmcntBitWidthLo(Version.Major) +
1045  getVmcntBitWidthHi(Version.Major))) -
1046  1;
1047 }
1048 
1050  return (1 << getExpcntBitWidth(Version.Major)) - 1;
1051 }
1052 
1054  return (1 << getLgkmcntBitWidth(Version.Major)) - 1;
1055 }
1056 
1058  unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(Version.Major),
1059  getVmcntBitWidthLo(Version.Major));
1060  unsigned Expcnt = getBitMask(getExpcntBitShift(Version.Major),
1061  getExpcntBitWidth(Version.Major));
1062  unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(Version.Major),
1063  getLgkmcntBitWidth(Version.Major));
1064  unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(Version.Major),
1065  getVmcntBitWidthHi(Version.Major));
1066  return VmcntLo | Expcnt | Lgkmcnt | VmcntHi;
1067 }
1068 
1069 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt) {
1070  unsigned VmcntLo = unpackBits(Waitcnt, getVmcntBitShiftLo(Version.Major),
1071  getVmcntBitWidthLo(Version.Major));
1072  unsigned VmcntHi = unpackBits(Waitcnt, getVmcntBitShiftHi(Version.Major),
1073  getVmcntBitWidthHi(Version.Major));
1074  return VmcntLo | VmcntHi << getVmcntBitWidthLo(Version.Major);
1075 }
1076 
1077 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt) {
1078  return unpackBits(Waitcnt, getExpcntBitShift(Version.Major),
1079  getExpcntBitWidth(Version.Major));
1080 }
1081 
1082 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt) {
1083  return unpackBits(Waitcnt, getLgkmcntBitShift(Version.Major),
1084  getLgkmcntBitWidth(Version.Major));
1085 }
1086 
1087 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
1088  unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
1089  Vmcnt = decodeVmcnt(Version, Waitcnt);
1090  Expcnt = decodeExpcnt(Version, Waitcnt);
1091  Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
1092 }
1093 
1094 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded) {
1095  Waitcnt Decoded;
1096  Decoded.VmCnt = decodeVmcnt(Version, Encoded);
1097  Decoded.ExpCnt = decodeExpcnt(Version, Encoded);
1098  Decoded.LgkmCnt = decodeLgkmcnt(Version, Encoded);
1099  return Decoded;
1100 }
1101 
1102 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
1103  unsigned Vmcnt) {
1104  Waitcnt = packBits(Vmcnt, Waitcnt, getVmcntBitShiftLo(Version.Major),
1105  getVmcntBitWidthLo(Version.Major));
1106  return packBits(Vmcnt >> getVmcntBitWidthLo(Version.Major), Waitcnt,
1107  getVmcntBitShiftHi(Version.Major),
1108  getVmcntBitWidthHi(Version.Major));
1109 }
1110 
1111 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
1112  unsigned Expcnt) {
1113  return packBits(Expcnt, Waitcnt, getExpcntBitShift(Version.Major),
1114  getExpcntBitWidth(Version.Major));
1115 }
1116 
1117 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
1118  unsigned Lgkmcnt) {
1119  return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(Version.Major),
1120  getLgkmcntBitWidth(Version.Major));
1121 }
1122 
1124  unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
1125  unsigned Waitcnt = getWaitcntBitMask(Version);
1126  Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
1127  Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
1128  Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
1129  return Waitcnt;
1130 }
1131 
1132 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded) {
1133  return encodeWaitcnt(Version, Decoded.VmCnt, Decoded.ExpCnt, Decoded.LgkmCnt);
1134 }
1135 
1136 //===----------------------------------------------------------------------===//
1137 // Custom Operands.
1138 //
1139 // A table of custom operands shall describe "primary" operand names
1140 // first followed by aliases if any. It is not required but recommended
1141 // to arrange operands so that operand encoding match operand position
1142 // in the table. This will make disassembly a bit more efficient.
1143 // Unused slots in the table shall have an empty name.
1144 //
1145 //===----------------------------------------------------------------------===//
1146 
1147 template <class T>
1148 static bool isValidOpr(int Idx, const CustomOperand<T> OpInfo[], int OpInfoSize,
1149  T Context) {
1150  return 0 <= Idx && Idx < OpInfoSize && !OpInfo[Idx].Name.empty() &&
1151  (!OpInfo[Idx].Cond || OpInfo[Idx].Cond(Context));
1152 }
1153 
1154 template <class T>
1155 static int getOprIdx(std::function<bool(const CustomOperand<T> &)> Test,
1156  const CustomOperand<T> OpInfo[], int OpInfoSize,
1157  T Context) {
1158  int InvalidIdx = OPR_ID_UNKNOWN;
1159  for (int Idx = 0; Idx < OpInfoSize; ++Idx) {
1160  if (Test(OpInfo[Idx])) {
1161  if (!OpInfo[Idx].Cond || OpInfo[Idx].Cond(Context))
1162  return Idx;
1164  }
1165  }
1166  return InvalidIdx;
1167 }
1168 
1169 template <class T>
1170 static int getOprIdx(const StringRef Name, const CustomOperand<T> OpInfo[],
1171  int OpInfoSize, T Context) {
1172  auto Test = [=](const CustomOperand<T> &Op) { return Op.Name == Name; };
1173  return getOprIdx<T>(Test, OpInfo, OpInfoSize, Context);
1174 }
1175 
1176 template <class T>
1177 static int getOprIdx(int Id, const CustomOperand<T> OpInfo[], int OpInfoSize,
1178  T Context, bool QuickCheck = true) {
1179  auto Test = [=](const CustomOperand<T> &Op) {
1180  return Op.Encoding == Id && !Op.Name.empty();
1181  };
1182  // This is an optimization that should work in most cases.
1183  // As a side effect, it may cause selection of an alias
1184  // instead of a primary operand name in case of sparse tables.
1185  if (QuickCheck && isValidOpr<T>(Id, OpInfo, OpInfoSize, Context) &&
1186  OpInfo[Id].Encoding == Id) {
1187  return Id;
1188  }
1189  return getOprIdx<T>(Test, OpInfo, OpInfoSize, Context);
1190 }
1191 
1192 //===----------------------------------------------------------------------===//
1193 // Custom Operand Values
1194 //===----------------------------------------------------------------------===//
1195 
1197  int Size,
1198  const MCSubtargetInfo &STI) {
1199  unsigned Enc = 0;
1200  for (int Idx = 0; Idx < Size; ++Idx) {
1201  const auto &Op = Opr[Idx];
1202  if (Op.isSupported(STI))
1203  Enc |= Op.encode(Op.Default);
1204  }
1205  return Enc;
1206 }
1207 
1209  int Size, unsigned Code,
1210  bool &HasNonDefaultVal,
1211  const MCSubtargetInfo &STI) {
1212  unsigned UsedOprMask = 0;
1213  HasNonDefaultVal = false;
1214  for (int Idx = 0; Idx < Size; ++Idx) {
1215  const auto &Op = Opr[Idx];
1216  if (!Op.isSupported(STI))
1217  continue;
1218  UsedOprMask |= Op.getMask();
1219  unsigned Val = Op.decode(Code);
1220  if (!Op.isValid(Val))
1221  return false;
1222  HasNonDefaultVal |= (Val != Op.Default);
1223  }
1224  return (Code & ~UsedOprMask) == 0;
1225 }
1226 
1227 static bool decodeCustomOperand(const CustomOperandVal *Opr, int Size,
1228  unsigned Code, int &Idx, StringRef &Name,
1229  unsigned &Val, bool &IsDefault,
1230  const MCSubtargetInfo &STI) {
1231  while (Idx < Size) {
1232  const auto &Op = Opr[Idx++];
1233  if (Op.isSupported(STI)) {
1234  Name = Op.Name;
1235  Val = Op.decode(Code);
1236  IsDefault = (Val == Op.Default);
1237  return true;
1238  }
1239  }
1240 
1241  return false;
1242 }
1243 
1245  int64_t InputVal) {
1246  if (InputVal < 0 || InputVal > Op.Max)
1247  return OPR_VAL_INVALID;
1248  return Op.encode(InputVal);
1249 }
1250 
1251 static int encodeCustomOperand(const CustomOperandVal *Opr, int Size,
1252  const StringRef Name, int64_t InputVal,
1253  unsigned &UsedOprMask,
1254  const MCSubtargetInfo &STI) {
1255  int InvalidId = OPR_ID_UNKNOWN;
1256  for (int Idx = 0; Idx < Size; ++Idx) {
1257  const auto &Op = Opr[Idx];
1258  if (Op.Name == Name) {
1259  if (!Op.isSupported(STI)) {
1260  InvalidId = OPR_ID_UNSUPPORTED;
1261  continue;
1262  }
1263  auto OprMask = Op.getMask();
1264  if (OprMask & UsedOprMask)
1265  return OPR_ID_DUPLICATE;
1266  UsedOprMask |= OprMask;
1267  return encodeCustomOperandVal(Op, InputVal);
1268  }
1269  }
1270  return InvalidId;
1271 }
1272 
1273 //===----------------------------------------------------------------------===//
1274 // DepCtr
1275 //===----------------------------------------------------------------------===//
1276 
1277 namespace DepCtr {
1278 
1280  static int Default = -1;
1281  if (Default == -1)
1283  return Default;
1284 }
1285 
1286 bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
1287  const MCSubtargetInfo &STI) {
1289  HasNonDefaultVal, STI);
1290 }
1291 
1292 bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
1293  bool &IsDefault, const MCSubtargetInfo &STI) {
1294  return decodeCustomOperand(DepCtrInfo, DEP_CTR_SIZE, Code, Id, Name, Val,
1295  IsDefault, STI);
1296 }
1297 
1298 int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
1299  const MCSubtargetInfo &STI) {
1300  return encodeCustomOperand(DepCtrInfo, DEP_CTR_SIZE, Name, Val, UsedOprMask,
1301  STI);
1302 }
1303 
1304 } // namespace DepCtr
1305 
1306 //===----------------------------------------------------------------------===//
1307 // hwreg
1308 //===----------------------------------------------------------------------===//
1309 
1310 namespace Hwreg {
1311 
1312 int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI) {
1313  int Idx = getOprIdx<const MCSubtargetInfo &>(Name, Opr, OPR_SIZE, STI);
1314  return (Idx < 0) ? Idx : Opr[Idx].Encoding;
1315 }
1316 
1317 bool isValidHwreg(int64_t Id) {
1318  return 0 <= Id && isUInt<ID_WIDTH_>(Id);
1319 }
1320 
1322  return 0 <= Offset && isUInt<OFFSET_WIDTH_>(Offset);
1323 }
1324 
1325 bool isValidHwregWidth(int64_t Width) {
1326  return 0 <= (Width - 1) && isUInt<WIDTH_M1_WIDTH_>(Width - 1);
1327 }
1328 
1330  return (Id << ID_SHIFT_) |
1331  (Offset << OFFSET_SHIFT_) |
1332  ((Width - 1) << WIDTH_M1_SHIFT_);
1333 }
1334 
1335 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI) {
1336  int Idx = getOprIdx<const MCSubtargetInfo &>(Id, Opr, OPR_SIZE, STI);
1337  return (Idx < 0) ? "" : Opr[Idx].Name;
1338 }
1339 
1340 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width) {
1341  Id = (Val & ID_MASK_) >> ID_SHIFT_;
1342  Offset = (Val & OFFSET_MASK_) >> OFFSET_SHIFT_;
1343  Width = ((Val & WIDTH_M1_MASK_) >> WIDTH_M1_SHIFT_) + 1;
1344 }
1345 
1346 } // namespace Hwreg
1347 
1348 //===----------------------------------------------------------------------===//
1349 // exp tgt
1350 //===----------------------------------------------------------------------===//
1351 
1352 namespace Exp {
1353 
1354 struct ExpTgt {
1356  unsigned Tgt;
1357  unsigned MaxIndex;
1358 };
1359 
1360 static constexpr ExpTgt ExpTgtInfo[] = {
1361  {{"null"}, ET_NULL, ET_NULL_MAX_IDX},
1362  {{"mrtz"}, ET_MRTZ, ET_MRTZ_MAX_IDX},
1363  {{"prim"}, ET_PRIM, ET_PRIM_MAX_IDX},
1364  {{"mrt"}, ET_MRT0, ET_MRT_MAX_IDX},
1365  {{"pos"}, ET_POS0, ET_POS_MAX_IDX},
1366  {{"dual_src_blend"}, ET_DUAL_SRC_BLEND0, ET_DUAL_SRC_BLEND_MAX_IDX},
1367  {{"param"}, ET_PARAM0, ET_PARAM_MAX_IDX},
1368 };
1369 
1370 bool getTgtName(unsigned Id, StringRef &Name, int &Index) {
1371  for (const ExpTgt &Val : ExpTgtInfo) {
1372  if (Val.Tgt <= Id && Id <= Val.Tgt + Val.MaxIndex) {
1373  Index = (Val.MaxIndex == 0) ? -1 : (Id - Val.Tgt);
1374  Name = Val.Name;
1375  return true;
1376  }
1377  }
1378  return false;
1379 }
1380 
1381 unsigned getTgtId(const StringRef Name) {
1382 
1383  for (const ExpTgt &Val : ExpTgtInfo) {
1384  if (Val.MaxIndex == 0 && Name == Val.Name)
1385  return Val.Tgt;
1386 
1387  if (Val.MaxIndex > 0 && Name.startswith(Val.Name)) {
1388  StringRef Suffix = Name.drop_front(Val.Name.size());
1389 
1390  unsigned Id;
1391  if (Suffix.getAsInteger(10, Id) || Id > Val.MaxIndex)
1392  return ET_INVALID;
1393 
1394  // Disable leading zeroes
1395  if (Suffix.size() > 1 && Suffix[0] == '0')
1396  return ET_INVALID;
1397 
1398  return Val.Tgt + Id;
1399  }
1400  }
1401  return ET_INVALID;
1402 }
1403 
1404 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI) {
1405  switch (Id) {
1406  case ET_NULL:
1407  return !isGFX11Plus(STI);
1408  case ET_POS4:
1409  case ET_PRIM:
1410  return isGFX10Plus(STI);
1411  case ET_DUAL_SRC_BLEND0:
1412  case ET_DUAL_SRC_BLEND1:
1413  return isGFX11Plus(STI);
1414  default:
1415  if (Id >= ET_PARAM0 && Id <= ET_PARAM31)
1416  return !isGFX11Plus(STI);
1417  return true;
1418  }
1419 }
1420 
1421 } // namespace Exp
1422 
1423 //===----------------------------------------------------------------------===//
1424 // MTBUF Format
1425 //===----------------------------------------------------------------------===//
1426 
1427 namespace MTBUFFormat {
1428 
1429 int64_t getDfmt(const StringRef Name) {
1430  for (int Id = DFMT_MIN; Id <= DFMT_MAX; ++Id) {
1431  if (Name == DfmtSymbolic[Id])
1432  return Id;
1433  }
1434  return DFMT_UNDEF;
1435 }
1436 
1438  assert(Id <= DFMT_MAX);
1439  return DfmtSymbolic[Id];
1440 }
1441 
1443  if (isSI(STI) || isCI(STI))
1444  return NfmtSymbolicSICI;
1445  if (isVI(STI) || isGFX9(STI))
1446  return NfmtSymbolicVI;
1447  return NfmtSymbolicGFX10;
1448 }
1449 
1450 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI) {
1451  auto lookupTable = getNfmtLookupTable(STI);
1452  for (int Id = NFMT_MIN; Id <= NFMT_MAX; ++Id) {
1453  if (Name == lookupTable[Id])
1454  return Id;
1455  }
1456  return NFMT_UNDEF;
1457 }
1458 
1459 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI) {
1460  assert(Id <= NFMT_MAX);
1461  return getNfmtLookupTable(STI)[Id];
1462 }
1463 
1464 bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI) {
1465  unsigned Dfmt;
1466  unsigned Nfmt;
1467  decodeDfmtNfmt(Id, Dfmt, Nfmt);
1468  return isValidNfmt(Nfmt, STI);
1469 }
1470 
1471 bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI) {
1472  return !getNfmtName(Id, STI).empty();
1473 }
1474 
1475 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt) {
1476  return (Dfmt << DFMT_SHIFT) | (Nfmt << NFMT_SHIFT);
1477 }
1478 
1479 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt) {
1480  Dfmt = (Format >> DFMT_SHIFT) & DFMT_MASK;
1481  Nfmt = (Format >> NFMT_SHIFT) & NFMT_MASK;
1482 }
1483 
1484 int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI) {
1485  if (isGFX11Plus(STI)) {
1486  for (int Id = UfmtGFX11::UFMT_FIRST; Id <= UfmtGFX11::UFMT_LAST; ++Id) {
1487  if (Name == UfmtSymbolicGFX11[Id])
1488  return Id;
1489  }
1490  } else {
1491  for (int Id = UfmtGFX10::UFMT_FIRST; Id <= UfmtGFX10::UFMT_LAST; ++Id) {
1492  if (Name == UfmtSymbolicGFX10[Id])
1493  return Id;
1494  }
1495  }
1496  return UFMT_UNDEF;
1497 }
1498 
1500  if(isValidUnifiedFormat(Id, STI))
1501  return isGFX10(STI) ? UfmtSymbolicGFX10[Id] : UfmtSymbolicGFX11[Id];
1502  return "";
1503 }
1504 
1505 bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI) {
1506  return isGFX10(STI) ? Id <= UfmtGFX10::UFMT_LAST : Id <= UfmtGFX11::UFMT_LAST;
1507 }
1508 
1509 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
1510  const MCSubtargetInfo &STI) {
1511  int64_t Fmt = encodeDfmtNfmt(Dfmt, Nfmt);
1512  if (isGFX11Plus(STI)) {
1513  for (int Id = UfmtGFX11::UFMT_FIRST; Id <= UfmtGFX11::UFMT_LAST; ++Id) {
1514  if (Fmt == DfmtNfmt2UFmtGFX11[Id])
1515  return Id;
1516  }
1517  } else {
1518  for (int Id = UfmtGFX10::UFMT_FIRST; Id <= UfmtGFX10::UFMT_LAST; ++Id) {
1519  if (Fmt == DfmtNfmt2UFmtGFX10[Id])
1520  return Id;
1521  }
1522  }
1523  return UFMT_UNDEF;
1524 }
1525 
1526 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI) {
1527  return isGFX10Plus(STI) ? (Val <= UFMT_MAX) : (Val <= DFMT_NFMT_MAX);
1528 }
1529 
1531  if (isGFX10Plus(STI))
1532  return UFMT_DEFAULT;
1533  return DFMT_NFMT_DEFAULT;
1534 }
1535 
1536 } // namespace MTBUFFormat
1537 
1538 //===----------------------------------------------------------------------===//
1539 // SendMsg
1540 //===----------------------------------------------------------------------===//
1541 
1542 namespace SendMsg {
1543 
1546 }
1547 
1548 int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI) {
1549  int Idx = getOprIdx<const MCSubtargetInfo &>(Name, Msg, MSG_SIZE, STI);
1550  return (Idx < 0) ? Idx : Msg[Idx].Encoding;
1551 }
1552 
1553 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI) {
1554  return (MsgId & ~(getMsgIdMask(STI))) == 0;
1555 }
1556 
1557 StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI) {
1558  int Idx = getOprIdx<const MCSubtargetInfo &>(MsgId, Msg, MSG_SIZE, STI);
1559  return (Idx < 0) ? "" : Msg[Idx].Name;
1560 }
1561 
1562 int64_t getMsgOpId(int64_t MsgId, const StringRef Name) {
1563  const char* const *S = (MsgId == ID_SYSMSG) ? OpSysSymbolic : OpGsSymbolic;
1564  const int F = (MsgId == ID_SYSMSG) ? OP_SYS_FIRST_ : OP_GS_FIRST_;
1565  const int L = (MsgId == ID_SYSMSG) ? OP_SYS_LAST_ : OP_GS_LAST_;
1566  for (int i = F; i < L; ++i) {
1567  if (Name == S[i]) {
1568  return i;
1569  }
1570  }
1571  return OP_UNKNOWN_;
1572 }
1573 
1574 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1575  bool Strict) {
1576  assert(isValidMsgId(MsgId, STI));
1577 
1578  if (!Strict)
1579  return 0 <= OpId && isUInt<OP_WIDTH_>(OpId);
1580 
1581  if (MsgId == ID_SYSMSG)
1582  return OP_SYS_FIRST_ <= OpId && OpId < OP_SYS_LAST_;
1583  if (!isGFX11Plus(STI)) {
1584  switch (MsgId) {
1585  case ID_GS_PreGFX11:
1586  return (OP_GS_FIRST_ <= OpId && OpId < OP_GS_LAST_) && OpId != OP_GS_NOP;
1587  case ID_GS_DONE_PreGFX11:
1588  return OP_GS_FIRST_ <= OpId && OpId < OP_GS_LAST_;
1589  }
1590  }
1591  return OpId == OP_NONE_;
1592 }
1593 
1594 StringRef getMsgOpName(int64_t MsgId, int64_t OpId,
1595  const MCSubtargetInfo &STI) {
1596  assert(msgRequiresOp(MsgId, STI));
1597  return (MsgId == ID_SYSMSG)? OpSysSymbolic[OpId] : OpGsSymbolic[OpId];
1598 }
1599 
1600 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
1601  const MCSubtargetInfo &STI, bool Strict) {
1602  assert(isValidMsgOp(MsgId, OpId, STI, Strict));
1603 
1604  if (!Strict)
1605  return 0 <= StreamId && isUInt<STREAM_ID_WIDTH_>(StreamId);
1606 
1607  if (!isGFX11Plus(STI)) {
1608  switch (MsgId) {
1609  case ID_GS_PreGFX11:
1611  case ID_GS_DONE_PreGFX11:
1612  return (OpId == OP_GS_NOP) ?
1613  (StreamId == STREAM_ID_NONE_) :
1615  }
1616  }
1617  return StreamId == STREAM_ID_NONE_;
1618 }
1619 
1620 bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI) {
1621  return MsgId == ID_SYSMSG ||
1622  (!isGFX11Plus(STI) &&
1623  (MsgId == ID_GS_PreGFX11 || MsgId == ID_GS_DONE_PreGFX11));
1624 }
1625 
1626 bool msgSupportsStream(int64_t MsgId, int64_t OpId,
1627  const MCSubtargetInfo &STI) {
1628  return !isGFX11Plus(STI) &&
1629  (MsgId == ID_GS_PreGFX11 || MsgId == ID_GS_DONE_PreGFX11) &&
1630  OpId != OP_GS_NOP;
1631 }
1632 
1633 void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
1634  uint16_t &StreamId, const MCSubtargetInfo &STI) {
1635  MsgId = Val & getMsgIdMask(STI);
1636  if (isGFX11Plus(STI)) {
1637  OpId = 0;
1638  StreamId = 0;
1639  } else {
1640  OpId = (Val & OP_MASK_) >> OP_SHIFT_;
1642  }
1643 }
1644 
1646  uint64_t OpId,
1647  uint64_t StreamId) {
1648  return MsgId | (OpId << OP_SHIFT_) | (StreamId << STREAM_ID_SHIFT_);
1649 }
1650 
1651 } // namespace SendMsg
1652 
1653 //===----------------------------------------------------------------------===//
1654 //
1655 //===----------------------------------------------------------------------===//
1656 
1658  return getIntegerAttribute(F, "InitialPSInputAddr", 0);
1659 }
1660 
1662  // As a safe default always respond as if PS has color exports.
1663  return getIntegerAttribute(
1664  F, "amdgpu-color-export",
1665  F.getCallingConv() == CallingConv::AMDGPU_PS ? 1 : 0) != 0;
1666 }
1667 
1669  return getIntegerAttribute(F, "amdgpu-depth-export", 0) != 0;
1670 }
1671 
1673  switch(cc) {
1681  return true;
1682  default:
1683  return false;
1684  }
1685 }
1686 
1688  return isShader(cc) || cc == CallingConv::AMDGPU_Gfx;
1689 }
1690 
1692  return !isGraphics(cc) || cc == CallingConv::AMDGPU_CS;
1693 }
1694 
1696  switch (CC) {
1706  return true;
1707  default:
1708  return false;
1709  }
1710 }
1711 
1713  switch (CC) {
1715  return true;
1716  default:
1717  return isEntryFunctionCC(CC);
1718  }
1719 }
1720 
1721 bool isKernelCC(const Function *Func) {
1722  return AMDGPU::isModuleEntryFunctionCC(Func->getCallingConv());
1723 }
1724 
1725 bool hasXNACK(const MCSubtargetInfo &STI) {
1726  return STI.getFeatureBits()[AMDGPU::FeatureXNACK];
1727 }
1728 
1729 bool hasSRAMECC(const MCSubtargetInfo &STI) {
1730  return STI.getFeatureBits()[AMDGPU::FeatureSRAMECC];
1731 }
1732 
1733 bool hasMIMG_R128(const MCSubtargetInfo &STI) {
1734  return STI.getFeatureBits()[AMDGPU::FeatureMIMG_R128] && !STI.getFeatureBits()[AMDGPU::FeatureR128A16];
1735 }
1736 
1737 bool hasGFX10A16(const MCSubtargetInfo &STI) {
1738  return STI.getFeatureBits()[AMDGPU::FeatureGFX10A16];
1739 }
1740 
1741 bool hasG16(const MCSubtargetInfo &STI) {
1742  return STI.getFeatureBits()[AMDGPU::FeatureG16];
1743 }
1744 
1745 bool hasPackedD16(const MCSubtargetInfo &STI) {
1746  return !STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem] && !isCI(STI) &&
1747  !isSI(STI);
1748 }
1749 
1750 bool isSI(const MCSubtargetInfo &STI) {
1751  return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
1752 }
1753 
1754 bool isCI(const MCSubtargetInfo &STI) {
1755  return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
1756 }
1757 
1758 bool isVI(const MCSubtargetInfo &STI) {
1759  return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1760 }
1761 
1762 bool isGFX9(const MCSubtargetInfo &STI) {
1763  return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
1764 }
1765 
1766 bool isGFX9_GFX10(const MCSubtargetInfo &STI) {
1767  return isGFX9(STI) || isGFX10(STI);
1768 }
1769 
1771  return isVI(STI) || isGFX9(STI) || isGFX10(STI);
1772 }
1773 
1774 bool isGFX8Plus(const MCSubtargetInfo &STI) {
1775  return isVI(STI) || isGFX9Plus(STI);
1776 }
1777 
1778 bool isGFX9Plus(const MCSubtargetInfo &STI) {
1779  return isGFX9(STI) || isGFX10Plus(STI);
1780 }
1781 
1782 bool isGFX10(const MCSubtargetInfo &STI) {
1783  return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
1784 }
1785 
1786 bool isGFX10Plus(const MCSubtargetInfo &STI) {
1787  return isGFX10(STI) || isGFX11Plus(STI);
1788 }
1789 
1790 bool isGFX11(const MCSubtargetInfo &STI) {
1791  return STI.getFeatureBits()[AMDGPU::FeatureGFX11];
1792 }
1793 
1794 bool isGFX11Plus(const MCSubtargetInfo &STI) {
1795  return isGFX11(STI);
1796 }
1797 
1799  return !isGFX11Plus(STI);
1800 }
1801 
1803  return isSI(STI) || isCI(STI) || isVI(STI) || isGFX9(STI);
1804 }
1805 
1807  return isGFX10(STI) && !AMDGPU::isGFX10_BEncoding(STI);
1808 }
1809 
1811  return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding];
1812 }
1813 
1815  return STI.getFeatureBits()[AMDGPU::FeatureGFX10_AEncoding];
1816 }
1817 
1819  return STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding];
1820 }
1821 
1823  return STI.getFeatureBits()[AMDGPU::FeatureGFX10_3Insts];
1824 }
1825 
1826 bool isGFX90A(const MCSubtargetInfo &STI) {
1827  return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts];
1828 }
1829 
1830 bool isGFX940(const MCSubtargetInfo &STI) {
1831  return STI.getFeatureBits()[AMDGPU::FeatureGFX940Insts];
1832 }
1833 
1835  return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch];
1836 }
1837 
1838 bool hasMAIInsts(const MCSubtargetInfo &STI) {
1839  return STI.getFeatureBits()[AMDGPU::FeatureMAIInsts];
1840 }
1841 
1842 bool hasVOPD(const MCSubtargetInfo &STI) {
1843  return STI.getFeatureBits()[AMDGPU::FeatureVOPD];
1844 }
1845 
1846 int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR,
1847  int32_t ArgNumVGPR) {
1848  if (has90AInsts && ArgNumAGPR)
1849  return alignTo(ArgNumVGPR, 4) + ArgNumAGPR;
1850  return std::max(ArgNumVGPR, ArgNumAGPR);
1851 }
1852 
1853 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
1854  const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
1855  const unsigned FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0);
1856  return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
1857  Reg == AMDGPU::SCC;
1858 }
1859 
1860 #define MAP_REG2REG \
1861  using namespace AMDGPU; \
1862  switch(Reg) { \
1863  default: return Reg; \
1864  CASE_CI_VI(FLAT_SCR) \
1865  CASE_CI_VI(FLAT_SCR_LO) \
1866  CASE_CI_VI(FLAT_SCR_HI) \
1867  CASE_VI_GFX9PLUS(TTMP0) \
1868  CASE_VI_GFX9PLUS(TTMP1) \
1869  CASE_VI_GFX9PLUS(TTMP2) \
1870  CASE_VI_GFX9PLUS(TTMP3) \
1871  CASE_VI_GFX9PLUS(TTMP4) \
1872  CASE_VI_GFX9PLUS(TTMP5) \
1873  CASE_VI_GFX9PLUS(TTMP6) \
1874  CASE_VI_GFX9PLUS(TTMP7) \
1875  CASE_VI_GFX9PLUS(TTMP8) \
1876  CASE_VI_GFX9PLUS(TTMP9) \
1877  CASE_VI_GFX9PLUS(TTMP10) \
1878  CASE_VI_GFX9PLUS(TTMP11) \
1879  CASE_VI_GFX9PLUS(TTMP12) \
1880  CASE_VI_GFX9PLUS(TTMP13) \
1881  CASE_VI_GFX9PLUS(TTMP14) \
1882  CASE_VI_GFX9PLUS(TTMP15) \
1883  CASE_VI_GFX9PLUS(TTMP0_TTMP1) \
1884  CASE_VI_GFX9PLUS(TTMP2_TTMP3) \
1885  CASE_VI_GFX9PLUS(TTMP4_TTMP5) \
1886  CASE_VI_GFX9PLUS(TTMP6_TTMP7) \
1887  CASE_VI_GFX9PLUS(TTMP8_TTMP9) \
1888  CASE_VI_GFX9PLUS(TTMP10_TTMP11) \
1889  CASE_VI_GFX9PLUS(TTMP12_TTMP13) \
1890  CASE_VI_GFX9PLUS(TTMP14_TTMP15) \
1891  CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3) \
1892  CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7) \
1893  CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11) \
1894  CASE_VI_GFX9PLUS(TTMP12_TTMP13_TTMP14_TTMP15) \
1895  CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
1896  CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
1897  CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
1898  CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
1899  CASE_GFXPRE11_GFX11PLUS(M0) \
1900  CASE_GFXPRE11_GFX11PLUS(SGPR_NULL) \
1901  CASE_GFXPRE11_GFX11PLUS_TO(SGPR_NULL64, SGPR_NULL) \
1902  }
1903 
1904 #define CASE_CI_VI(node) \
1905  assert(!isSI(STI)); \
1906  case node: return isCI(STI) ? node##_ci : node##_vi;
1907 
1908 #define CASE_VI_GFX9PLUS(node) \
1909  case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;
1910 
1911 #define CASE_GFXPRE11_GFX11PLUS(node) \
1912  case node: return isGFX11Plus(STI) ? node##_gfx11plus : node##_gfxpre11;
1913 
1914 #define CASE_GFXPRE11_GFX11PLUS_TO(node, result) \
1915  case node: return isGFX11Plus(STI) ? result##_gfx11plus : result##_gfxpre11;
1916 
1917 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
1918  if (STI.getTargetTriple().getArch() == Triple::r600)
1919  return Reg;
1920  MAP_REG2REG
1921 }
1922 
1923 #undef CASE_CI_VI
1924 #undef CASE_VI_GFX9PLUS
1925 #undef CASE_GFXPRE11_GFX11PLUS
1926 #undef CASE_GFXPRE11_GFX11PLUS_TO
1927 
1928 #define CASE_CI_VI(node) case node##_ci: case node##_vi: return node;
1929 #define CASE_VI_GFX9PLUS(node) case node##_vi: case node##_gfx9plus: return node;
1930 #define CASE_GFXPRE11_GFX11PLUS(node) case node##_gfx11plus: case node##_gfxpre11: return node;
1931 #define CASE_GFXPRE11_GFX11PLUS_TO(node, result)
1932 
1933 unsigned mc2PseudoReg(unsigned Reg) {
1934  MAP_REG2REG
1935 }
1936 
1937 #undef CASE_CI_VI
1938 #undef CASE_VI_GFX9PLUS
1939 #undef CASE_GFXPRE11_GFX11PLUS
1940 #undef CASE_GFXPRE11_GFX11PLUS_TO
1941 #undef MAP_REG2REG
1942 
1943 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
1944  assert(OpNo < Desc.NumOperands);
1945  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
1946  return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
1947  OpType <= AMDGPU::OPERAND_SRC_LAST;
1948 }
1949 
1950 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
1951  assert(OpNo < Desc.NumOperands);
1952  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
1953  switch (OpType) {
1973  return true;
1974  default:
1975  return false;
1976  }
1977 }
1978 
1979 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
1980  assert(OpNo < Desc.NumOperands);
1981  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
1982  return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
1984 }
1985 
1986 // Avoid using MCRegisterClass::getSize, since that function will go away
1987 // (move from MC* level to Target* level). Return size in bits.
1988 unsigned getRegBitWidth(unsigned RCID) {
1989  switch (RCID) {
1990  case AMDGPU::VGPR_LO16RegClassID:
1991  case AMDGPU::VGPR_HI16RegClassID:
1992  case AMDGPU::SGPR_LO16RegClassID:
1993  case AMDGPU::AGPR_LO16RegClassID:
1994  return 16;
1995  case AMDGPU::SGPR_32RegClassID:
1996  case AMDGPU::VGPR_32RegClassID:
1997  case AMDGPU::VRegOrLds_32RegClassID:
1998  case AMDGPU::AGPR_32RegClassID:
1999  case AMDGPU::VS_32RegClassID:
2000  case AMDGPU::AV_32RegClassID:
2001  case AMDGPU::SReg_32RegClassID:
2002  case AMDGPU::SReg_32_XM0RegClassID:
2003  case AMDGPU::SRegOrLds_32RegClassID:
2004  return 32;
2005  case AMDGPU::SGPR_64RegClassID:
2006  case AMDGPU::VS_64RegClassID:
2007  case AMDGPU::SReg_64RegClassID:
2008  case AMDGPU::VReg_64RegClassID:
2009  case AMDGPU::AReg_64RegClassID:
2010  case AMDGPU::SReg_64_XEXECRegClassID:
2011  case AMDGPU::VReg_64_Align2RegClassID:
2012  case AMDGPU::AReg_64_Align2RegClassID:
2013  case AMDGPU::AV_64RegClassID:
2014  case AMDGPU::AV_64_Align2RegClassID:
2015  return 64;
2016  case AMDGPU::SGPR_96RegClassID:
2017  case AMDGPU::SReg_96RegClassID:
2018  case AMDGPU::VReg_96RegClassID:
2019  case AMDGPU::AReg_96RegClassID:
2020  case AMDGPU::VReg_96_Align2RegClassID:
2021  case AMDGPU::AReg_96_Align2RegClassID:
2022  case AMDGPU::AV_96RegClassID:
2023  case AMDGPU::AV_96_Align2RegClassID:
2024  return 96;
2025  case AMDGPU::SGPR_128RegClassID:
2026  case AMDGPU::SReg_128RegClassID:
2027  case AMDGPU::VReg_128RegClassID:
2028  case AMDGPU::AReg_128RegClassID:
2029  case AMDGPU::VReg_128_Align2RegClassID:
2030  case AMDGPU::AReg_128_Align2RegClassID:
2031  case AMDGPU::AV_128RegClassID:
2032  case AMDGPU::AV_128_Align2RegClassID:
2033  return 128;
2034  case AMDGPU::SGPR_160RegClassID:
2035  case AMDGPU::SReg_160RegClassID:
2036  case AMDGPU::VReg_160RegClassID:
2037  case AMDGPU::AReg_160RegClassID:
2038  case AMDGPU::VReg_160_Align2RegClassID:
2039  case AMDGPU::AReg_160_Align2RegClassID:
2040  case AMDGPU::AV_160RegClassID:
2041  case AMDGPU::AV_160_Align2RegClassID:
2042  return 160;
2043  case AMDGPU::SGPR_192RegClassID:
2044  case AMDGPU::SReg_192RegClassID:
2045  case AMDGPU::VReg_192RegClassID:
2046  case AMDGPU::AReg_192RegClassID:
2047  case AMDGPU::VReg_192_Align2RegClassID:
2048  case AMDGPU::AReg_192_Align2RegClassID:
2049  case AMDGPU::AV_192RegClassID:
2050  case AMDGPU::AV_192_Align2RegClassID:
2051  return 192;
2052  case AMDGPU::SGPR_224RegClassID:
2053  case AMDGPU::SReg_224RegClassID:
2054  case AMDGPU::VReg_224RegClassID:
2055  case AMDGPU::AReg_224RegClassID:
2056  case AMDGPU::VReg_224_Align2RegClassID:
2057  case AMDGPU::AReg_224_Align2RegClassID:
2058  case AMDGPU::AV_224RegClassID:
2059  case AMDGPU::AV_224_Align2RegClassID:
2060  return 224;
2061  case AMDGPU::SGPR_256RegClassID:
2062  case AMDGPU::SReg_256RegClassID:
2063  case AMDGPU::VReg_256RegClassID:
2064  case AMDGPU::AReg_256RegClassID:
2065  case AMDGPU::VReg_256_Align2RegClassID:
2066  case AMDGPU::AReg_256_Align2RegClassID:
2067  case AMDGPU::AV_256RegClassID:
2068  case AMDGPU::AV_256_Align2RegClassID:
2069  return 256;
2070  case AMDGPU::SGPR_512RegClassID:
2071  case AMDGPU::SReg_512RegClassID:
2072  case AMDGPU::VReg_512RegClassID:
2073  case AMDGPU::AReg_512RegClassID:
2074  case AMDGPU::VReg_512_Align2RegClassID:
2075  case AMDGPU::AReg_512_Align2RegClassID:
2076  case AMDGPU::AV_512RegClassID:
2077  case AMDGPU::AV_512_Align2RegClassID:
2078  return 512;
2079  case AMDGPU::SGPR_1024RegClassID:
2080  case AMDGPU::SReg_1024RegClassID:
2081  case AMDGPU::VReg_1024RegClassID:
2082  case AMDGPU::AReg_1024RegClassID:
2083  case AMDGPU::VReg_1024_Align2RegClassID:
2084  case AMDGPU::AReg_1024_Align2RegClassID:
2085  case AMDGPU::AV_1024RegClassID:
2086  case AMDGPU::AV_1024_Align2RegClassID:
2087  return 1024;
2088  default:
2089  llvm_unreachable("Unexpected register class");
2090  }
2091 }
2092 
2093 unsigned getRegBitWidth(const MCRegisterClass &RC) {
2094  return getRegBitWidth(RC.getID());
2095 }
2096 
2097 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
2098  unsigned OpNo) {
2099  assert(OpNo < Desc.NumOperands);
2100  unsigned RCID = Desc.OpInfo[OpNo].RegClass;
2101  return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
2102 }
2103 
2104 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
2105  if (isInlinableIntLiteral(Literal))
2106  return true;
2107 
2108  uint64_t Val = static_cast<uint64_t>(Literal);
2109  return (Val == DoubleToBits(0.0)) ||
2110  (Val == DoubleToBits(1.0)) ||
2111  (Val == DoubleToBits(-1.0)) ||
2112  (Val == DoubleToBits(0.5)) ||
2113  (Val == DoubleToBits(-0.5)) ||
2114  (Val == DoubleToBits(2.0)) ||
2115  (Val == DoubleToBits(-2.0)) ||
2116  (Val == DoubleToBits(4.0)) ||
2117  (Val == DoubleToBits(-4.0)) ||
2118  (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
2119 }
2120 
2121 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
2122  if (isInlinableIntLiteral(Literal))
2123  return true;
2124 
2125  // The actual type of the operand does not seem to matter as long
2126  // as the bits match one of the inline immediate values. For example:
2127  //
2128  // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
2129  // so it is a legal inline immediate.
2130  //
2131  // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
2132  // floating-point, so it is a legal inline immediate.
2133 
2134  uint32_t Val = static_cast<uint32_t>(Literal);
2135  return (Val == FloatToBits(0.0f)) ||
2136  (Val == FloatToBits(1.0f)) ||
2137  (Val == FloatToBits(-1.0f)) ||
2138  (Val == FloatToBits(0.5f)) ||
2139  (Val == FloatToBits(-0.5f)) ||
2140  (Val == FloatToBits(2.0f)) ||
2141  (Val == FloatToBits(-2.0f)) ||
2142  (Val == FloatToBits(4.0f)) ||
2143  (Val == FloatToBits(-4.0f)) ||
2144  (Val == 0x3e22f983 && HasInv2Pi);
2145 }
2146 
2147 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) {
2148  if (!HasInv2Pi)
2149  return false;
2150 
2151  if (isInlinableIntLiteral(Literal))
2152  return true;
2153 
2154  uint16_t Val = static_cast<uint16_t>(Literal);
2155  return Val == 0x3C00 || // 1.0
2156  Val == 0xBC00 || // -1.0
2157  Val == 0x3800 || // 0.5
2158  Val == 0xB800 || // -0.5
2159  Val == 0x4000 || // 2.0
2160  Val == 0xC000 || // -2.0
2161  Val == 0x4400 || // 4.0
2162  Val == 0xC400 || // -4.0
2163  Val == 0x3118; // 1/2pi
2164 }
2165 
2166 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi) {
2167  assert(HasInv2Pi);
2168 
2169  if (isInt<16>(Literal) || isUInt<16>(Literal)) {
2170  int16_t Trunc = static_cast<int16_t>(Literal);
2171  return AMDGPU::isInlinableLiteral16(Trunc, HasInv2Pi);
2172  }
2173  if (!(Literal & 0xffff))
2174  return AMDGPU::isInlinableLiteral16(Literal >> 16, HasInv2Pi);
2175 
2176  int16_t Lo16 = static_cast<int16_t>(Literal);
2177  int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
2178  return Lo16 == Hi16 && isInlinableLiteral16(Lo16, HasInv2Pi);
2179 }
2180 
2181 bool isInlinableIntLiteralV216(int32_t Literal) {
2182  int16_t Lo16 = static_cast<int16_t>(Literal);
2183  if (isInt<16>(Literal) || isUInt<16>(Literal))
2184  return isInlinableIntLiteral(Lo16);
2185 
2186  int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
2187  if (!(Literal & 0xffff))
2188  return isInlinableIntLiteral(Hi16);
2189  return Lo16 == Hi16 && isInlinableIntLiteral(Lo16);
2190 }
2191 
2192 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi) {
2193  assert(HasInv2Pi);
2194 
2195  int16_t Lo16 = static_cast<int16_t>(Literal);
2196  if (isInt<16>(Literal) || isUInt<16>(Literal))
2197  return true;
2198 
2199  int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
2200  if (!(Literal & 0xffff))
2201  return true;
2202  return Lo16 == Hi16;
2203 }
2204 
2205 bool isArgPassedInSGPR(const Argument *A) {
2206  const Function *F = A->getParent();
2207 
2208  // Arguments to compute shaders are never a source of divergence.
2209  CallingConv::ID CC = F->getCallingConv();
2210  switch (CC) {
2213  return true;
2222  // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
2223  // Everything else is in VGPRs.
2224  return F->getAttributes().hasParamAttr(A->getArgNo(), Attribute::InReg) ||
2225  F->getAttributes().hasParamAttr(A->getArgNo(), Attribute::ByVal);
2226  default:
2227  // TODO: Should calls support inreg for SGPR inputs?
2228  return false;
2229  }
2230 }
2231 
2232 static bool hasSMEMByteOffset(const MCSubtargetInfo &ST) {
2233  return isGCN3Encoding(ST) || isGFX10Plus(ST);
2234 }
2235 
2237  return isGFX9Plus(ST);
2238 }
2239 
2241  int64_t EncodedOffset) {
2242  return hasSMEMByteOffset(ST) ? isUInt<20>(EncodedOffset)
2243  : isUInt<8>(EncodedOffset);
2244 }
2245 
2247  int64_t EncodedOffset,
2248  bool IsBuffer) {
2249  return !IsBuffer &&
2251  isInt<21>(EncodedOffset);
2252 }
2253 
2254 static bool isDwordAligned(uint64_t ByteOffset) {
2255  return (ByteOffset & 3) == 0;
2256 }
2257 
2259  uint64_t ByteOffset) {
2260  if (hasSMEMByteOffset(ST))
2261  return ByteOffset;
2262 
2263  assert(isDwordAligned(ByteOffset));
2264  return ByteOffset >> 2;
2265 }
2266 
2268  int64_t ByteOffset, bool IsBuffer) {
2269  // The signed version is always a byte offset.
2270  if (!IsBuffer && hasSMRDSignedImmOffset(ST)) {
2272  return isInt<20>(ByteOffset) ? Optional<int64_t>(ByteOffset) : None;
2273  }
2274 
2275  if (!isDwordAligned(ByteOffset) && !hasSMEMByteOffset(ST))
2276  return None;
2277 
2278  int64_t EncodedOffset = convertSMRDOffsetUnits(ST, ByteOffset);
2279  return isLegalSMRDEncodedUnsignedOffset(ST, EncodedOffset)
2280  ? Optional<int64_t>(EncodedOffset)
2281  : None;
2282 }
2283 
2285  int64_t ByteOffset) {
2286  if (!isCI(ST) || !isDwordAligned(ByteOffset))
2287  return None;
2288 
2289  int64_t EncodedOffset = convertSMRDOffsetUnits(ST, ByteOffset);
2290  return isUInt<32>(EncodedOffset) ? Optional<int64_t>(EncodedOffset) : None;
2291 }
2292 
2294  // Address offset is 12-bit signed for GFX10, 13-bit for GFX9 and GFX11+.
2295  if (AMDGPU::isGFX10(ST))
2296  return Signed ? 12 : 11;
2297 
2298  return Signed ? 13 : 12;
2299 }
2300 
2301 // Given Imm, split it into the values to put into the SOffset and ImmOffset
2302 // fields in an MUBUF instruction. Return false if it is not possible (due to a
2303 // hardware bug needing a workaround).
2304 //
2305 // The required alignment ensures that individual address components remain
2306 // aligned if they are aligned to begin with. It also ensures that additional
2307 // offsets within the given alignment can be added to the resulting ImmOffset.
2308 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
2309  const GCNSubtarget *Subtarget, Align Alignment) {
2310  const uint32_t MaxImm = alignDown(4095, Alignment.value());
2311  uint32_t Overflow = 0;
2312 
2313  if (Imm > MaxImm) {
2314  if (Imm <= MaxImm + 64) {
2315  // Use an SOffset inline constant for 4..64
2316  Overflow = Imm - MaxImm;
2317  Imm = MaxImm;
2318  } else {
2319  // Try to keep the same value in SOffset for adjacent loads, so that
2320  // the corresponding register contents can be re-used.
2321  //
2322  // Load values with all low-bits (except for alignment bits) set into
2323  // SOffset, so that a larger range of values can be covered using
2324  // s_movk_i32.
2325  //
2326  // Atomic operations fail to work correctly when individual address
2327  // components are unaligned, even if their sum is aligned.
2328  uint32_t High = (Imm + Alignment.value()) & ~4095;
2329  uint32_t Low = (Imm + Alignment.value()) & 4095;
2330  Imm = Low;
2331  Overflow = High - Alignment.value();
2332  }
2333  }
2334 
2335  // There is a hardware bug in SI and CI which prevents address clamping in
2336  // MUBUF instructions from working correctly with SOffsets. The immediate
2337  // offset is unaffected.
2338  if (Overflow > 0 &&
2340  return false;
2341 
2342  ImmOffset = Imm;
2343  SOffset = Overflow;
2344  return true;
2345 }
2346 
2348  *this = getDefaultForCallingConv(F.getCallingConv());
2349 
2350  StringRef IEEEAttr = F.getFnAttribute("amdgpu-ieee").getValueAsString();
2351  if (!IEEEAttr.empty())
2352  IEEE = IEEEAttr == "true";
2353 
2354  StringRef DX10ClampAttr
2355  = F.getFnAttribute("amdgpu-dx10-clamp").getValueAsString();
2356  if (!DX10ClampAttr.empty())
2357  DX10Clamp = DX10ClampAttr == "true";
2358 
2359  StringRef DenormF32Attr = F.getFnAttribute("denormal-fp-math-f32").getValueAsString();
2360  if (!DenormF32Attr.empty()) {
2361  DenormalMode DenormMode = parseDenormalFPAttribute(DenormF32Attr);
2364  }
2365 
2366  StringRef DenormAttr = F.getFnAttribute("denormal-fp-math").getValueAsString();
2367  if (!DenormAttr.empty()) {
2368  DenormalMode DenormMode = parseDenormalFPAttribute(DenormAttr);
2369 
2370  if (DenormF32Attr.empty()) {
2373  }
2374 
2377  }
2378 }
2379 
2380 namespace {
2381 
2382 struct SourceOfDivergence {
2383  unsigned Intr;
2384 };
2385 const SourceOfDivergence *lookupSourceOfDivergence(unsigned Intr);
2386 
2387 #define GET_SourcesOfDivergence_IMPL
2388 #define GET_Gfx9BufferFormat_IMPL
2389 #define GET_Gfx10BufferFormat_IMPL
2390 #define GET_Gfx11PlusBufferFormat_IMPL
2391 #include "AMDGPUGenSearchableTables.inc"
2392 
2393 } // end anonymous namespace
2394 
2395 bool isIntrinsicSourceOfDivergence(unsigned IntrID) {
2396  return lookupSourceOfDivergence(IntrID);
2397 }
2398 
2399 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
2400  uint8_t NumComponents,
2401  uint8_t NumFormat,
2402  const MCSubtargetInfo &STI) {
2403  return isGFX11Plus(STI)
2404  ? getGfx11PlusBufferFormatInfo(BitsPerComp, NumComponents,
2405  NumFormat)
2406  : isGFX10(STI) ? getGfx10BufferFormatInfo(BitsPerComp,
2407  NumComponents, NumFormat)
2408  : getGfx9BufferFormatInfo(BitsPerComp,
2409  NumComponents, NumFormat);
2410 }
2411 
2413  const MCSubtargetInfo &STI) {
2414  return isGFX11Plus(STI) ? getGfx11PlusBufferFormatInfo(Format)
2415  : isGFX10(STI) ? getGfx10BufferFormatInfo(Format)
2416  : getGfx9BufferFormatInfo(Format);
2417 }
2418 
2419 } // namespace AMDGPU
2420 
2423  switch (S) {
2425  OS << "Unsupported";
2426  break;
2428  OS << "Any";
2429  break;
2431  OS << "Off";
2432  break;
2434  OS << "On";
2435  break;
2436  }
2437  return OS;
2438 }
2439 
2440 } // namespace llvm
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:173
llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat
bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1505
llvm::AMDGPU::Hwreg::encodeHwreg
uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width)
Definition: AMDGPUBaseInfo.cpp:1329
llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:441
i
i
Definition: README.txt:29
llvm::AMDGPU::MUBUFInfo::elements
uint8_t elements
Definition: AMDGPUBaseInfo.cpp:245
llvm::AMDGPU::Hwreg::OPR_SIZE
const int OPR_SIZE
Definition: AMDGPUAsmUtils.cpp:134
llvm::AMDGPU::OPR_ID_UNSUPPORTED
const int OPR_ID_UNSUPPORTED
Definition: AMDGPUAsmUtils.h:24
llvm::AMDGPU::getMUBUFIsBufferInv
bool getMUBUFIsBufferInv(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:380
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:156
llvm::AMDGPU::getMCReg
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
Definition: AMDGPUBaseInfo.cpp:1917
llvm::AMDGPU::isHsaAbiVersion3
bool isHsaAbiVersion3(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:125
llvm::AMDGPU::UfmtGFX10::UFMT_FIRST
@ UFMT_FIRST
Definition: SIDefines.h:631
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::AMDGPUTargetID
AMDGPUTargetID(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:465
llvm::AMDGPU::mc2PseudoReg
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
Definition: AMDGPUBaseInfo.cpp:1933
llvm::AMDGPU::VOPInfo::IsSingle
bool IsSingle
Definition: AMDGPUBaseInfo.cpp:268
llvm::AMDGPU::VOPDComponentInfo::VOPDOp
uint16_t VOPDOp
Definition: AMDGPUBaseInfo.cpp:277
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4710
llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE
@ FLOAT_DENORM_MODE_FLUSH_NONE
Definition: AMDHSAKernelDescriptor.h:63
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::AMDGPU::getMAIIsDGEMM
bool getMAIIsDGEMM(unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
Definition: AMDGPUBaseInfo.cpp:409
llvm::AMDGPU::IsaInfo::getSGPRAllocGranule
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:735
llvm::AMDGPU::getMUBUFHasSoffset
bool getMUBUFHasSoffset(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:375
llvm::LLVMContext::emitError
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Definition: LLVMContext.cpp:271
llvm::AMDGPU::MTBUFFormat::NumFormat
NumFormat
Definition: SIDefines.h:497
llvm::AMDGPU::Hwreg::getHwreg
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1335
llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1530
llvm::AMDGPU::hasVOPD
bool hasVOPD(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1842
llvm::AMDGPU::MIMGBaseOpcodeInfo::Gradients
bool Gradients
Definition: AMDGPUBaseInfo.h:309
llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumSGPRs
constexpr char NumSGPRs[]
Key for Kernel::CodeProps::Metadata::mNumSGPRs.
Definition: AMDGPUMetadata.h:258
llvm::AMDGPU::Hwreg::getHwregId
int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1312
llvm::CallingConv::AMDGPU_HS
@ AMDGPU_HS
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:207
llvm::AMDGPU::SendMsg::msgRequiresOp
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1620
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bool LodOrClampOrMip
Definition: AMDGPUBaseInfo.h:312
llvm::AMDGPU::MTBUFFormat::getDfmtName
StringRef getDfmtName(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1437
llvm::AMDGPU::SendMsg::encodeMsg
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
Definition: AMDGPUBaseInfo.cpp:1645
llvm::AMDGPU::isGFX11Plus
bool isGFX11Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1794
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IsaVersion getIsaVersion(StringRef GPU)
Definition: TargetParser.cpp:193
llvm::AMDGPU::decodeLgkmcnt
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:1082
llvm::AMDGPU::Hwreg::ID_SHIFT_
@ ID_SHIFT_
Definition: SIDefines.h:411
llvm::AMDGPU::VOPTrue16Info
Definition: AMDGPUBaseInfo.cpp:287
llvm::AMDGPU::SendMsg::OpGsSymbolic
const char *const OpGsSymbolic[OP_GS_LAST_]
Definition: AMDGPUAsmUtils.cpp:77
llvm::Function
Definition: Function.h:60
llvm::AMDGPU::getMUBUFBaseOpcode
int getMUBUFBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:350
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Definition: Attributes.h:65
llvm::AMDGPU::SIModeRegisterDefaults::FP32OutputDenormals
bool FP32OutputDenormals
Definition: AMDGPUBaseInfo.h:1032
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Optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
Definition: AMDGPUBaseInfo.cpp:2267
llvm::AMDGPU::MTBUFFormat::DFMT_MASK
@ DFMT_MASK
Definition: SIDefines.h:494
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isSramEccOnOrAny
bool isSramEccOnOrAny() const
Definition: AMDGPUBaseInfo.h:150
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int getMCOpcode(uint16_t Opcode, unsigned Gen)
Definition: AMDGPUBaseInfo.cpp:454
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unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:1069
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:628
llvm::AMDGPU::hasSRAMECC
bool hasSRAMECC(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1729
llvm::AMDGPU::SIModeRegisterDefaults::IEEE
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
Definition: AMDGPUBaseInfo.h:1023
llvm::AMDGPU::hasXNACK
bool hasXNACK(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1725
llvm::AMDGPU::IsaInfo::TargetIDSetting::Unsupported
@ Unsupported
llvm::AMDGPU::OPERAND_REG_IMM_V2FP16
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:162
High
uint64_t High
Definition: NVVMIntrRange.cpp:61
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1181
llvm::AMDGPU::isVOPD
bool isVOPD(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:432
llvm::AMDGPU::IsaInfo::TargetIDSetting::On
@ On
llvm::AMDGPU::isGFX10_BEncoding
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1818
llvm::Triple::amdgcn
@ amdgcn
Definition: Triple.h:74
llvm::AMDGPU::CustomOperand::Name
StringLiteral Name
Definition: AMDGPUAsmUtils.h:29
llvm::AMDGPU::isGFX10_AEncoding
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1814
amd_kernel_code_t::compute_pgm_resource_registers
uint64_t compute_pgm_resource_registers
Shader program settings for CS.
Definition: AMDKernelCodeT.h:558
llvm::AMDGPU::getVOP2IsSingle
bool getVOP2IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:395
llvm::AMDGPU::OPR_VAL_INVALID
const int OPR_VAL_INVALID
Definition: AMDGPUAsmUtils.h:26
llvm::AMDGPU::MIMGDimInfo
Definition: AMDGPUBaseInfo.h:324
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::AMDGPU::hasArchitectedFlatScratch
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1834
llvm::AMDGPU::MTBUFFormat::encodeDfmtNfmt
int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt)
Definition: AMDGPUBaseInfo.cpp:1475
llvm::AMDGPU::getHsaAbiVersion
Optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:100
llvm::AMDGPU::MTBUFFormat::NFMT_UNDEF
@ NFMT_UNDEF
Definition: SIDefines.h:511
llvm::AMDGPU::VOPDInfo::OpX
uint16_t OpX
Definition: AMDGPUBaseInfo.cpp:283
llvm::AMDGPUSubtarget::SEA_ISLANDS
@ SEA_ISLANDS
Definition: AMDGPUSubtarget.h:38
llvm::AMDGPU::Exp::ET_NULL
@ ET_NULL
Definition: SIDefines.h:862
llvm::AMDGPU::SendMsg::STREAM_ID_MASK_
@ STREAM_ID_MASK_
Definition: SIDefines.h:378
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::AMDGPU::getVOPDFull
int getVOPDFull(unsigned OpX, unsigned OpY)
Definition: AMDGPUBaseInfo.cpp:458
llvm::AMDGPU::SendMsg::OpSysSymbolic
const char *const OpSysSymbolic[OP_SYS_LAST_]
Definition: AMDGPUAsmUtils.cpp:69
llvm::AMDGPU::getSMRDEncodedLiteralOffset32
Optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
Definition: AMDGPUBaseInfo.cpp:2284
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::AMDGPU::getAmdhsaCodeObjectVersion
unsigned getAmdhsaCodeObjectVersion()
Definition: AMDGPUBaseInfo.cpp:148
llvm::AMDGPU::MTBUFInfo::has_vaddr
bool has_vaddr
Definition: AMDGPUBaseInfo.cpp:256
llvm::AMDGPU::SendMsg::OP_GS_LAST_
@ OP_GS_LAST_
Definition: SIDefines.h:360
llvm::AMDGPU::MTBUFFormat::isValidNfmt
bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1471
llvm::AMDGPU::DepCtr::encodeDepCtr
int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1298
llvm::AMDGPU::isGFX11
bool isGFX11(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1790
llvm::X86AS::FS
@ FS
Definition: X86.h:200
Shift
bool Shift
Definition: README.txt:468
llvm::CallingConv::SPIR_KERNEL
@ SPIR_KERNEL
Used for SPIR kernel functions.
Definition: CallingConv.h:141
llvm::AMDGPU::Hwreg::ID_MASK_
@ ID_MASK_
Definition: SIDefines.h:413
llvm::AMDGPU::Exp::ET_POS0
@ ET_POS0
Definition: SIDefines.h:863
llvm::AMDGPU::CustomOperand::Encoding
int Encoding
Definition: AMDGPUAsmUtils.h:30
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_MAX
@ DFMT_NFMT_MAX
Definition: SIDefines.h:526
llvm::FloatToBits
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:593
llvm::AMDGPU::IsaInfo::getNumExtraSGPRs
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
Definition: AMDGPUBaseInfo.cpp:801
llvm::AMDGPU::isGFX10
bool isGFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1782
llvm::AMDGPU::IsaInfo::getTotalNumVGPRs
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:868
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setTargetIDFromTargetIDStream
void setTargetIDFromTargetIDStream(StringRef TargetID)
Definition: AMDGPUBaseInfo.cpp:542
llvm::AMDGPU::IsaInfo::getMinWavesPerEU
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:702
llvm::Optional< uint8_t >
llvm::AMDGPU::SIModeRegisterDefaults::getDefaultForCallingConv
static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.h:1049
llvm::AMDGPU::MUBUFInfo::has_soffset
bool has_soffset
Definition: AMDGPUBaseInfo.cpp:248
llvm::MCRegisterClass::contains
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
Definition: MCRegisterInfo.h:68
llvm::AMDGPU::SIModeRegisterDefaults::FP32InputDenormals
bool FP32InputDenormals
If this is set, neither input or output denormals are flushed for most f32 instructions.
Definition: AMDGPUBaseInfo.h:1031
llvm::AMDGPU::IsaInfo::TargetIDSetting::Any
@ Any
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
AMDGPUAsmUtils.h
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:891
llvm::AMDGPU::getVmcntBitMask
unsigned getVmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:1043
llvm::AMDGPU::isGlobalSegment
bool isGlobalSegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:989
llvm::CallingConv::AMDGPU_ES
@ AMDGPU_ES
Used for AMDPAL shader stage before geometry shader if geometry is in use.
Definition: CallingConv.h:219
llvm::AMDGPU::hasGFX10_3Insts
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1822
TargetParser.h
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
llvm::AMDGPU::VOPTrue16Info::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:288
llvm::AMDGPU::IsaInfo::getMaxNumVGPRs
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:896
llvm::AMDGPU::Exp::ET_PARAM0
@ ET_PARAM0
Definition: SIDefines.h:870
llvm::AMDGPU::getWaitcntBitMask
unsigned getWaitcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:1057
llvm::AMDGPU::isIntrinsicSourceOfDivergence
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
Definition: AMDGPUBaseInfo.cpp:2395
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc2
uint32_t compute_pgm_rsrc2
Definition: AMDHSAKernelDescriptor.h:179
llvm::AMDGPU::SendMsg::MSG_SIZE
const int MSG_SIZE
Definition: AMDGPUAsmUtils.cpp:65
llvm::AMDGPU::MIMGDimInfo::NumGradients
uint8_t NumGradients
Definition: AMDGPUBaseInfo.h:327
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::AMDGPU::getMTBUFOpcode
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
Definition: AMDGPUBaseInfo.cpp:325
llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable
static const StringLiteral * getNfmtLookupTable(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1442
AmdhsaCodeObjectVersion
static llvm::cl::opt< unsigned > AmdhsaCodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden, llvm::cl::desc("AMDHSA Code Object Version"), llvm::cl::init(4))
llvm::AMDGPU::MUBUFInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:243
llvm::AMDGPU::MIMGInfo::VAddrDwords
uint8_t VAddrDwords
Definition: AMDGPUBaseInfo.h:405
llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:690
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::AMDGPU::MTBUFFormat::isValidDfmtNfmt
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1464
llvm::AMDGPU::SendMsg::ID_MASK_PreGFX11_
@ ID_MASK_PreGFX11_
Definition: SIDefines.h:344
llvm::AMDGPU::DepCtr::decodeDepCtr
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1292
llvm::AMDGPU::isTrue16Inst
bool isTrue16Inst(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:436
llvm::AMDGPU::VOPDInfo
Definition: AMDGPUBaseInfo.cpp:281
AMDHSAKernelDescriptor.h
llvm::AMDGPU::HSAMD::V3::VersionMajor
constexpr uint32_t VersionMajor
HSA metadata major version.
Definition: AMDGPUMetadata.h:459
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
llvm::AMDGPU::getDefaultCustomOperandEncoding
static unsigned getDefaultCustomOperandEncoding(const CustomOperandVal *Opr, int Size, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1196
llvm::AMDGPU::IsaInfo::TargetIDSetting
TargetIDSetting
Definition: AMDGPUBaseInfo.h:98
llvm::parseDenormalFPAttribute
DenormalMode parseDenormalFPAttribute(StringRef Str)
Returns the denormal mode to use for inputs and outputs.
Definition: FloatingPointMode.h:176
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::AMDGPU::Hwreg::decodeHwreg
void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)
Definition: AMDGPUBaseInfo.cpp:1340
llvm::AMDGPU::IsaVersion
Instruction set architecture version.
Definition: TargetParser.h:113
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::AMDGPU::IsaInfo::getSGPREncodingGranule
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:744
CommandLine.h
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicVI
const StringLiteral NfmtSymbolicVI[]
Definition: AMDGPUAsmUtils.cpp:182
llvm::AMDGPU::isGFX90A
bool isGFX90A(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1826
llvm::AMDGPU::OPR_ID_DUPLICATE
const int OPR_ID_DUPLICATE
Definition: AMDGPUAsmUtils.h:25
llvm::AMDGPU::SendMsg::OP_GS_FIRST_
@ OP_GS_FIRST_
Definition: SIDefines.h:361
llvm::AMDGPU::OPERAND_REG_IMM_FP32
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:157
llvm::AMDGPU::SendMsg::msgSupportsStream
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1626
llvm::AMDGPU::MTBUFFormat::UfmtSymbolicGFX11
const StringLiteral UfmtSymbolicGFX11[]
Definition: AMDGPUAsmUtils.cpp:381
llvm::AMDGPU::MUBUFInfo::has_srsrc
bool has_srsrc
Definition: AMDGPUBaseInfo.cpp:247
llvm::StringLiteral
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:842
llvm::AMDGPU::getMTBUFHasSrsrc
bool getMTBUFHasSrsrc(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:340
GlobalValue.h
ELF.h
llvm::CallingConv::AMDGPU_CS
@ AMDGPU_CS
Used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:198
llvm::DenormalMode::Input
DenormalModeKind Input
Denormal treatment kind for floating point instruction inputs in the default floating-point environme...
Definition: FloatingPointMode.h:92
llvm::AMDGPU::isShader
bool isShader(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1672
llvm::PGSOQueryType::Test
@ Test
llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:730
llvm::ARM::InvalidIdx
@ InvalidIdx
Definition: ARMRegisterBankInfo.cpp:69
llvm::AMDGPU::MTBUFInfo::has_soffset
bool has_soffset
Definition: AMDGPUBaseInfo.cpp:258
amd_kernel_code_t::amd_kernel_code_version_major
uint32_t amd_kernel_code_version_major
Definition: AMDKernelCodeT.h:527
llvm::AMDGPU::Exp::ET_INVALID
@ ET_INVALID
Definition: SIDefines.h:881
llvm::AMDGPU::Exp::ET_MRTZ_MAX_IDX
@ ET_MRTZ_MAX_IDX
Definition: SIDefines.h:874
GCNSubtarget.h
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:201
llvm::AMDGPU::hasSMEMByteOffset
static bool hasSMEMByteOffset(const MCSubtargetInfo &ST)
Definition: AMDGPUBaseInfo.cpp:2232
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::AMDGPU::getRegOperandSize
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
Definition: AMDGPUBaseInfo.cpp:2097
llvm::AMDGPU::SendMsg::OP_SYS_LAST_
@ OP_SYS_LAST_
Definition: SIDefines.h:367
llvm::AMDGPU::getMIMGBaseOpcode
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:201
llvm::AMDGPU::MIMGBaseOpcodeInfo
Definition: AMDGPUBaseInfo.h:300
llvm::AMDGPU::isInlinableIntLiteralV216
bool isInlinableIntLiteralV216(int32_t Literal)
Definition: AMDGPUBaseInfo.cpp:2181
Intr
unsigned Intr
Definition: AMDGPUBaseInfo.cpp:2383
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:186
llvm::AMDGPU::MTBUFFormat::DfmtSymbolic
const StringLiteral DfmtSymbolic[]
Definition: AMDGPUAsmUtils.cpp:141
llvm::AMDGPU::getMUBUFOpcode
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
Definition: AMDGPUBaseInfo.cpp:355
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:108
llvm::AMDGPU::getSMEMIsBuffer
bool getSMEMIsBuffer(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:385
llvm::AMDGPUAS::GLOBAL_ADDRESS
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:372
llvm::AMDGPU::isGFX940
bool isGFX940(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1830
llvm::AMDGPU::IsaInfo::getMaxNumSGPRs
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
Definition: AMDGPUBaseInfo.cpp:784
llvm::AMDGPU::isSGPR
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
Definition: AMDGPUBaseInfo.cpp:1853
llvm::AMDGPU::hasMAIInsts
bool hasMAIInsts(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1838
llvm::AMDGPU::VOPC64DPPInfo
Definition: AMDGPUBaseInfo.cpp:271
llvm::AMDGPU::IsaInfo::getTargetIDSettingFromFeatureString
static TargetIDSetting getTargetIDSettingFromFeatureString(StringRef FeatureString)
Definition: AMDGPUBaseInfo.cpp:533
llvm::AMDGPU::SendMsg::STREAM_ID_LAST_
@ STREAM_ID_LAST_
Definition: SIDefines.h:374
llvm::SubtargetFeatures::getFeatures
const std::vector< std::string > & getFeatures() const
Returns the vector of individual subtarget features.
Definition: SubtargetFeature.h:193
llvm::DoubleToBits
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:585
llvm::SubtargetFeatures
Manages the enabling and disabling of subtarget specific features.
Definition: SubtargetFeature.h:180
llvm::AMDGPU::SendMsg::ID_SYSMSG
@ ID_SYSMSG
Definition: SIDefines.h:335
llvm::AMDGPU::Hwreg::Id
Id
Definition: SIDefines.h:385
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackOnOrAny
bool isXnackOnOrAny() const
Definition: AMDGPUBaseInfo.h:121
llvm::AMDGPU::decodeExpcnt
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:1077
llvm::AMDGPU::getMAIIsGFX940XDL
bool getMAIIsGFX940XDL(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:414
llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5
@ ELFABIVERSION_AMDGPU_HSA_V5
Definition: ELF.h:377
llvm::AMDGPU::MTBUFInfo::BaseOpcode
uint16_t BaseOpcode
Definition: AMDGPUBaseInfo.cpp:254
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::alignDown
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
Definition: MathExtras.h:694
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
S_00B848_MEM_ORDERED
#define S_00B848_MEM_ORDERED(x)
Definition: SIDefines.h:1011
llvm::AMDGPU::hasGFX10A16
bool hasGFX10A16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1737
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::AMDGPU::Exp::ET_PRIM
@ ET_PRIM
Definition: SIDefines.h:867
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::AMDGPU::encodeCustomOperand
static int encodeCustomOperand(const CustomOperandVal *Opr, int Size, const StringRef Name, int64_t InputVal, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1251
llvm::AMDGPU::SendMsg::OP_GS_NOP
@ OP_GS_NOP
Definition: SIDefines.h:356
llvm::AMDGPU::OPERAND_REG_IMM_FP64
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:158
llvm::AMDGPU::getMTBUFBaseOpcode
int getMTBUFBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:320
llvm::AMDGPU::getInitialPSInputAddr
unsigned getInitialPSInputAddr(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1657
llvm::AMDGPU::SendMsg::OP_SHIFT_
@ OP_SHIFT_
Definition: SIDefines.h:350
llvm::Triple::r600
@ r600
Definition: Triple.h:73
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::AMDGPU::Exp::ExpTgt::Name
StringLiteral Name
Definition: AMDGPUBaseInfo.cpp:1355
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
llvm::AMDGPU::getMTBUFHasSoffset
bool getMTBUFHasSoffset(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:345
llvm::raw_ostream::flush
void flush()
Definition: raw_ostream.h:185
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:230
llvm::AMDGPU::MTBUFFormat::DFMT_UNDEF
@ DFMT_UNDEF
Definition: SIDefines.h:490
llvm::ThreadPriority::Low
@ Low
Lower the current thread's priority such that it does not affect foreground tasks significantly.
llvm::AMDGPU::decodeWaitcnt
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
Definition: AMDGPUBaseInfo.cpp:1087
amd_kernel_code_t::wavefront_size
uint8_t wavefront_size
Wavefront size expressed as a power of two.
Definition: AMDKernelCodeT.h:643
llvm::AMDGPU::MTBUFInfo
Definition: AMDGPUBaseInfo.cpp:252
llvm::AMDGPU::OPERAND_REG_IMM_V2FP32
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:165
llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:721
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::getSramEccSetting
TargetIDSetting getSramEccSetting() const
Definition: AMDGPUBaseInfo.h:164
llvm::amdhsa::kernel_descriptor_t::kernel_code_properties
uint16_t kernel_code_properties
Definition: AMDHSAKernelDescriptor.h:180
llvm::IndexedInstrProf::Version
const uint64_t Version
Definition: InstrProf.h:1056
llvm::AMDGPU::getMUBUFHasSrsrc
bool getMUBUFHasSrsrc(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:370
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::AMDGPU::convertSMRDOffsetUnits
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
Definition: AMDGPUBaseInfo.cpp:2258
llvm::AMDGPU::IsaInfo::getEUsPerCU
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:679
llvm::AMDGPU::MIMGInfo::MIMGEncoding
uint8_t MIMGEncoding
Definition: AMDGPUBaseInfo.h:403
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:90
llvm::AMDGPU::MTBUFInfo::elements
uint8_t elements
Definition: AMDGPUBaseInfo.cpp:255
llvm::AMDGPU::IsaInfo::getLocalMemorySize
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:670
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AMDGPU::getMIMGOpcode
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
Definition: AMDGPUBaseInfo.cpp:194
llvm::Triple::getArch
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:346
llvm::AMDGPU::isCI
bool isCI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1754
llvm::StringRef::getAsInteger
std::enable_if_t< std::numeric_limits< T >::is_signed, bool > getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:463
llvm::None
const NoneType None
Definition: None.h:24
llvm::AMDGPU::SendMsg::StreamId
StreamId
Definition: SIDefines.h:371
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::AMDGPU::VOPC64DPPInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:272
llvm::AMDGPU::isGFX10Plus
bool isGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1786
llvm::AMDGPU::isSymbolicCustomOperandEncoding
static bool isSymbolicCustomOperandEncoding(const CustomOperandVal *Opr, int Size, unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1208
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc3
uint32_t compute_pgm_rsrc3
Definition: AMDHSAKernelDescriptor.h:177
llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND0
@ ET_DUAL_SRC_BLEND0
Definition: SIDefines.h:868
llvm::AMDGPU::isEntryFunctionCC
bool isEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1695
amd_kernel_code_t::amd_machine_version_minor
uint16_t amd_machine_version_minor
Definition: AMDKernelCodeT.h:531
llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1526
llvm::AMDGPU::isHsaAbiVersion2
bool isHsaAbiVersion2(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:119
llvm::AMDGPU::hasPackedD16
bool hasPackedD16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1745
llvm::AMDGPU::MTBUFFormat::NFMT_MIN
@ NFMT_MIN
Definition: SIDefines.h:508
llvm::AMDGPU::VOPDInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:282
llvm::AMDGPU::SMInfo::IsBuffer
bool IsBuffer
Definition: AMDGPUBaseInfo.cpp:263
llvm::AMDGPU::Hwreg::OFFSET_MASK_
@ OFFSET_MASK_
Definition: SIDefines.h:420
llvm::AMDGPU::Hwreg::isValidHwregWidth
bool isValidHwregWidth(int64_t Width)
Definition: AMDGPUBaseInfo.cpp:1325
llvm::AMDGPU::DepCtr::getDefaultDepCtrEncoding
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1279
llvm::AMDGPU::shouldEmitConstantsToTextSection
bool shouldEmitConstantsToTextSection(const Triple &TT)
Definition: AMDGPUBaseInfo.cpp:999
llvm::AMDGPU::SendMsg::getMsgId
int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1548
llvm::AMDGPU::Hwreg::WIDTH_M1_SHIFT_
@ WIDTH_M1_SHIFT_
Definition: SIDefines.h:430
llvm::AMDGPU::DepCtr::DepCtrInfo
const CustomOperandVal DepCtrInfo[]
Definition: AMDGPUAsmUtils.cpp:18
llvm::Triple::AMDHSA
@ AMDHSA
Definition: Triple.h:208
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
llvm::AMDGPU::Hwreg::isValidHwreg
bool isValidHwreg(int64_t Id)
Definition: AMDGPUBaseInfo.cpp:1317
llvm::AMDGPU::UfmtGFX11::UFMT_FIRST
@ UFMT_FIRST
Definition: SIDefines.h:717
llvm::AMDGPU::isVI
bool isVI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1758
llvm::AMDGPU::VOPDInfo::OpY
uint16_t OpY
Definition: AMDGPUBaseInfo.cpp:284
llvm::AMDGPU::MUBUFInfo::BaseOpcode
uint16_t BaseOpcode
Definition: AMDGPUBaseInfo.cpp:244
llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:160
llvm::AMDGPU::isInlinableLiteralV216
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:2166
llvm::AMDGPU::ImplicitArg::HOSTCALL_PTR_OFFSET
@ HOSTCALL_PTR_OFFSET
Definition: SIDefines.h:899
llvm::cl::opt
Definition: CommandLine.h:1400
llvm::AMDGPU::Exp::ET_PARAM_MAX_IDX
@ ET_PARAM_MAX_IDX
Definition: SIDefines.h:879
llvm::AMDGPU::getRegBitWidth
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
Definition: AMDGPUBaseInfo.cpp:1988
llvm::AMDGPU::MTBUFFormat::NFMT_MAX
@ NFMT_MAX
Definition: SIDefines.h:509
llvm::AMDGPU::getExpcntBitMask
unsigned getExpcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:1049
llvm::MCInstrDesc::NumOperands
unsigned short NumOperands
Definition: MCInstrDesc.h:200
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::AMDGPU::getMultigridSyncArgImplicitArgPosition
unsigned getMultigridSyncArgImplicitArgPosition()
Definition: AMDGPUBaseInfo.cpp:152
llvm::divideCeil
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:683
llvm::AMDGPU::isHsaAbiVersion4
bool isHsaAbiVersion4(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:131
llvm::AMDGPU::IsaInfo::getMinNumSGPRs
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:767
llvm::AMDGPU::isInlinableIntLiteral
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
Definition: AMDGPUBaseInfo.h:943
llvm::AMDGPU::hasG16
bool hasG16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1741
AMDGPUMCTargetDesc.h
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:416
llvm::AMDGPU::SMInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:262
uint64_t
llvm::AMDGPU::MTBUFFormat::NFMT_MASK
@ NFMT_MASK
Definition: SIDefines.h:515
llvm::Triple::getOS
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:355
llvm::AMDGPUAS::LOCAL_ADDRESS
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:376
llvm::AMDGPU::isVOPC64DPP
bool isVOPC64DPP(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:405
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:172
llvm::AMDGPU::isGFX9
bool isGFX9(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1762
llvm::AMDGPU::MTBUFFormat::DFMT_SHIFT
@ DFMT_SHIFT
Definition: SIDefines.h:493
llvm::AMDGPU::SendMsg::ID_MASK_GFX11Plus_
@ ID_MASK_GFX11Plus_
Definition: SIDefines.h:345
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::AMDGPU::initDefaultAMDKernelCodeT
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:915
llvm::AMDGPU::getIntegerAttribute
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
Definition: AMDGPUBaseInfo.cpp:1003
llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND1
@ ET_DUAL_SRC_BLEND1
Definition: SIDefines.h:869
llvm::AMDGPU::VOPInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:267
llvm::AMDGPU::OPERAND_SRC_FIRST
@ OPERAND_SRC_FIRST
Definition: SIDefines.h:203
amd_kernel_code_t::call_convention
int32_t call_convention
Definition: AMDKernelCodeT.h:645
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition: MCSubtargetInfo.h:109
llvm::AMDGPU::MUBUFInfo::IsBufferInv
bool IsBufferInv
Definition: AMDGPUBaseInfo.cpp:249
llvm::AMDGPU::OPR_ID_UNKNOWN
const int OPR_ID_UNKNOWN
Definition: AMDGPUAsmUtils.h:23
llvm::DenormalMode
Represent subnormal handling kind for floating point instruction inputs and outputs.
Definition: FloatingPointMode.h:69
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:440
llvm::CallingConv::AMDGPU_GS
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:192
llvm::AMDGPU::getGcnBufferFormatInfo
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2399
llvm::AMDGPU::SendMsg::OP_UNKNOWN_
@ OP_UNKNOWN_
Definition: SIDefines.h:349
llvm::AMDGPU::IsaInfo::getWavefrontSize
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:661
llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V2
@ ELFABIVERSION_AMDGPU_HSA_V2
Definition: ELF.h:374
llvm::AMDGPU::isSISrcInlinableOperand
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
Definition: AMDGPUBaseInfo.cpp:1979
llvm::AMDGPU::Hwreg::isValidHwregOffset
bool isValidHwregOffset(int64_t Offset)
Definition: AMDGPUBaseInfo.cpp:1321
llvm::AMDGPU::VOPTrue16Info::IsTrue16
bool IsTrue16
Definition: AMDGPUBaseInfo.cpp:289
llvm::AMDGPU::SIModeRegisterDefaults::DX10Clamp
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
Definition: AMDGPUBaseInfo.h:1027
llvm::AMDGPU::CanBeVOPD
Definition: AMDGPUBaseInfo.h:473
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AMDGPU::encodeVmcnt
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
Definition: AMDGPUBaseInfo.cpp:1102
llvm::AMDGPU::getAddrSizeMIMGOp
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
Definition: AMDGPUBaseInfo.cpp:214
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::getXnackSetting
TargetIDSetting getXnackSetting() const
Definition: AMDGPUBaseInfo.h:135
llvm::AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
Definition: AMDGPUBaseInfo.h:94
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16InputDenormals
bool FP64FP16InputDenormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
Definition: AMDGPUBaseInfo.h:1036
amd_kernel_code_t::amd_machine_version_stepping
uint16_t amd_machine_version_stepping
Definition: AMDKernelCodeT.h:532
llvm::AMDGPU::isGFX9_GFX10
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1766
amd_kernel_code_t::group_segment_alignment
uint8_t group_segment_alignment
Definition: AMDKernelCodeT.h:635
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::AMDGPU::Waitcnt::LgkmCnt
unsigned LgkmCnt
Definition: AMDGPUBaseInfo.h:554
llvm::AMDGPU::Exp::isSupportedTgtId
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1404
llvm::CallingConv::AMDGPU_LS
@ AMDGPU_LS
Used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:214
llvm::AMDGPU::IsaInfo::getTotalNumSGPRs
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:748
llvm::AMDGPU::getMIMGInfo
const LLVM_READONLY MIMGInfo * getMIMGInfo(unsigned Opc)
llvm::AMDGPU::isGFX10Before1030
bool isGFX10Before1030(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1806
llvm::AMDGPU::VOPInfo
Definition: AMDGPUBaseInfo.cpp:266
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:174
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:195
llvm::AMDGPU::Exp::ET_MRT0
@ ET_MRT0
Definition: SIDefines.h:859
llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:755
llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:161
llvm::DenormalMode::IEEE
@ IEEE
IEEE-754 denormal numbers preserved.
Definition: FloatingPointMode.h:76
llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1509
llvm::AMDGPU::IsaInfo::getNumSGPRBlocks
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
Definition: AMDGPUBaseInfo.cpp:832
amd_kernel_code_t::kernarg_segment_alignment
uint8_t kernarg_segment_alignment
The maximum byte alignment of variables used by the kernel in the specified memory segment.
Definition: AMDKernelCodeT.h:634
amd_kernel_code_t::amd_kernel_code_version_minor
uint32_t amd_kernel_code_version_minor
Definition: AMDKernelCodeT.h:528
llvm::AMDGPU::Exp::ExpTgtInfo
static constexpr ExpTgt ExpTgtInfo[]
Definition: AMDGPUBaseInfo.cpp:1360
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:187
llvm::AMDGPU::IsaInfo::TargetIDSetting::Off
@ Off
llvm::AMDGPU::MTBUFFormat::DFMT_MIN
@ DFMT_MIN
Definition: SIDefines.h:487
llvm::AMDGPU::MIMGInfo::BaseOpcode
uint16_t BaseOpcode
Definition: AMDGPUBaseInfo.h:402
llvm::AMDGPU::CustomOperand
Definition: AMDGPUAsmUtils.h:28
llvm::AMDGPU::isInlinableLiteral16
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:2147
llvm::AMDGPU::getMIMGBaseOpcodeInfo
const LLVM_READONLY MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
llvm::AMDGPU::CPol::SCC
@ SCC
Definition: SIDefines.h:307
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicGFX10
const StringLiteral NfmtSymbolicGFX10[]
Definition: AMDGPUAsmUtils.cpp:160
llvm::AMDGPU::isDwordAligned
static bool isDwordAligned(uint64_t ByteOffset)
Definition: AMDGPUBaseInfo.cpp:2254
llvm::AMDGPU::Exp::ExpTgt::Tgt
unsigned Tgt
Definition: AMDGPUBaseInfo.cpp:1356
llvm::AMDGPU::isHsaAbiVersion5
bool isHsaAbiVersion5(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:137
llvm::AMDGPU::DepCtr::DEP_CTR_SIZE
const int DEP_CTR_SIZE
Definition: AMDGPUAsmUtils.cpp:30
llvm::AMDGPU::hasSMRDSignedImmOffset
static bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST)
Definition: AMDGPUBaseInfo.cpp:2236
llvm::AMDGPU::Exp::ET_MRTZ
@ ET_MRTZ
Definition: SIDefines.h:861
llvm::AMDGPU::MTBUFFormat::UFMT_UNDEF
@ UFMT_UNDEF
Definition: SIDefines.h:531
llvm::AMDGPU::Exp::ExpTgt::MaxIndex
unsigned MaxIndex
Definition: AMDGPUBaseInfo.cpp:1357
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::AMDGPU::WMMAOpcodeMappingInfo
Definition: AMDGPUBaseInfo.h:371
llvm::AMDGPU::isNotGFX10Plus
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1802
llvm::AMDGPU::SendMsg::isValidMsgId
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1553
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::AMDGPU::DepCtr::isSymbolicDepCtrEncoding
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1286
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
AMDGPU.h
MAP_REG2REG
#define MAP_REG2REG
Definition: AMDGPUBaseInfo.cpp:1860
llvm::AMDGPU::getVOP3IsSingle
bool getVOP3IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:400
llvm::AMDGPU::Hwreg::OFFSET_SHIFT_
@ OFFSET_SHIFT_
Definition: SIDefines.h:418
llvm::AMDGPU::isModuleEntryFunctionCC
bool isModuleEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1712
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::AMDGPU::isCompute
bool isCompute(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1691
llvm::AMDGPU::IsaInfo::getVGPREncodingGranule
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:856
llvm::MCRegisterClass::getID
unsigned getID() const
getID() - Return the register class ID number.
Definition: MCRegisterInfo.h:48
uint32_t
llvm::AMDGPU::IsaInfo::getNumVGPRBlocks
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:905
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::AMDGPU::MIMGBaseOpcodeInfo::Coordinates
bool Coordinates
Definition: AMDGPUBaseInfo.h:311
llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
Definition: AMDGPUBaseInfo.cpp:2240
llvm::AMDGPU::isSISrcOperand
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
Definition: AMDGPUBaseInfo.cpp:1943
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::AMDGPU::isGraphics
bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1687
amd_kernel_code_t
AMD Kernel Code Object (amd_kernel_code_t).
Definition: AMDKernelCodeT.h:526
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackSupported
bool isXnackSupported() const
Definition: AMDGPUBaseInfo.h:116
llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:725
llvm::AMDGPU::Exp::getTgtName
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
Definition: AMDGPUBaseInfo.cpp:1370
llvm::AMDGPU::Waitcnt::VmCnt
unsigned VmCnt
Definition: AMDGPUBaseInfo.h:552
llvm::AMDGPU::getMTBUFHasVAddr
bool getMTBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:335
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
AMDHSA_BITS_SET
#define AMDHSA_BITS_SET(DST, MSK, VAL)
Definition: AMDHSAKernelDescriptor.h:42
amd_kernel_code_t::kernel_code_entry_byte_offset
int64_t kernel_code_entry_byte_offset
Byte offset (possibly negative) from start of amd_kernel_code_t object to kernel's entry point instru...
Definition: AMDKernelCodeT.h:544
llvm::AMDGPU::MTBUFFormat::UfmtSymbolicGFX10
const StringLiteral UfmtSymbolicGFX10[]
Definition: AMDGPUAsmUtils.cpp:193
llvm::AMDGPU::GcnBufferFormatInfo
Definition: AMDGPUBaseInfo.h:66
llvm::AMDGPU::isGFX8_GFX9_GFX10
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1770
llvm::AMDGPU::MTBUFFormat::getUnifiedFormat
int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1484
llvm::AMDGPU::isGFX9Plus
bool isGFX9Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1778
llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:951
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPU::MTBUFFormat::UFMT_DEFAULT
@ UFMT_DEFAULT
Definition: SIDefines.h:532
llvm::AMDGPU::SendMsg::Msg
const CustomOperand< const MCSubtargetInfo & > Msg[]
Definition: AMDGPUAsmUtils.cpp:39
amd_kernel_code_t::amd_machine_kind
uint16_t amd_machine_kind
Definition: AMDKernelCodeT.h:529
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: AMDGPUBaseInfo.h:1037
llvm::AMDGPU::isGroupSegment
bool isGroupSegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:985
llvm::AMDGPU::SendMsg::STREAM_ID_FIRST_
@ STREAM_ID_FIRST_
Definition: SIDefines.h:375
llvm::AMDGPU::SMInfo
Definition: AMDGPUBaseInfo.cpp:261
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
llvm::AMDGPUAS::CONSTANT_ADDRESS
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:375
llvm::AMDGPU::encodeWaitcnt
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
Definition: AMDGPUBaseInfo.cpp:1123
llvm::AMDGPU::SendMsg::isValidMsgOp
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1574
llvm::AMDGPU::SendMsg::OP_SYS_FIRST_
@ OP_SYS_FIRST_
Definition: SIDefines.h:368
Attributes.h
llvm::AMDGPU::isSI
bool isSI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1750
llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4
@ ELFABIVERSION_AMDGPU_HSA_V4
Definition: ELF.h:376
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:188
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString
std::string toString() const
Definition: AMDGPUBaseInfo.cpp:554
amd_kernel_code_t::amd_machine_version_major
uint16_t amd_machine_version_major
Definition: AMDKernelCodeT.h:530
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::Any
Definition: Any.h:28
llvm::AMDGPU::OPERAND_SRC_LAST
@ OPERAND_SRC_LAST
Definition: SIDefines.h:204
llvm::AMDGPU::isArgPassedInSGPR
bool isArgPassedInSGPR(const Argument *A)
Definition: AMDGPUBaseInfo.cpp:2205
llvm::AMDGPU::UfmtGFX11::UFMT_LAST
@ UFMT_LAST
Definition: SIDefines.h:718
llvm::AMDGPU::ImplicitArg::MULTIGRID_SYNC_ARG_OFFSET
@ MULTIGRID_SYNC_ARG_OFFSET
Definition: SIDefines.h:900
llvm::AMDGPU::Waitcnt
Represents the counter values to wait for in an s_waitcnt instruction.
Definition: AMDGPUBaseInfo.h:551
llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND_MAX_IDX
@ ET_DUAL_SRC_BLEND_MAX_IDX
Definition: SIDefines.h:878
llvm::AMDGPU::Hwreg::Opr
const CustomOperand< const MCSubtargetInfo & > Opr[]
Definition: AMDGPUAsmUtils.cpp:90
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::AMDGPU::SendMsg::decodeMsg
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1633
amd_kernel_code_t::private_segment_alignment
uint8_t private_segment_alignment
Definition: AMDKernelCodeT.h:636
llvm::AMDGPU::IsaInfo::TRAP_NUM_SGPRS
@ TRAP_NUM_SGPRS
Definition: AMDGPUBaseInfo.h:95
llvm::AMDGPU::SIModeRegisterDefaults::SIModeRegisterDefaults
SIModeRegisterDefaults()
Definition: AMDGPUBaseInfo.h:1039
llvm::AMDGPU::decodeCustomOperand
static bool decodeCustomOperand(const CustomOperandVal *Opr, int Size, unsigned Code, int &Idx, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1227
llvm::AMDGPU::getMUBUFHasVAddr
bool getMUBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:365
llvm::AMDGPU::isInlinableLiteral64
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
Definition: AMDGPUBaseInfo.cpp:2104
llvm::AMDGPU::OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:163
uint16_t
llvm::AMDGPU::getMUBUFElements
int getMUBUFElements(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:360
llvm::AMDGPU::encodeCustomOperandVal
static int encodeCustomOperandVal(const CustomOperandVal &Op, int64_t InputVal)
Definition: AMDGPUBaseInfo.cpp:1244
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_DEFAULT
@ DFMT_NFMT_DEFAULT
Definition: SIDefines.h:520
llvm::AMDGPU::SendMsg::getMsgOpId
int64_t getMsgOpId(int64_t MsgId, const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1562
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::AMDGPU::Exp::ET_POS4
@ ET_POS4
Definition: SIDefines.h:865
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::FPOpFusion::Strict
@ Strict
Definition: TargetOptions.h:39
amd_kernel_code_t::code_properties
uint32_t code_properties
Code properties.
Definition: AMDKernelCodeT.h:562
llvm::AMDGPU::isFoldableLiteralV216
bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:2192
llvm::StringRef::endswith
bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:265
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:175
llvm::AMDGPU::CustomOperand::Cond
bool(* Cond)(T Context)
Definition: AMDGPUAsmUtils.h:31
llvm::AMDGPU::MIMGInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.h:401
Function.h
llvm::AMDGPU::MUBUFInfo::has_vaddr
bool has_vaddr
Definition: AMDGPUBaseInfo.cpp:246
llvm::AMDGPU::OPERAND_REG_INLINE_C_FIRST
@ OPERAND_REG_INLINE_C_FIRST
Definition: SIDefines.h:197
llvm::amdhsa::kernel_descriptor_t
Definition: AMDHSAKernelDescriptor.h:170
llvm::AMDGPU::getVOP1IsSingle
bool getVOP1IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:390
llvm::AMDGPU::getVOPDOpcode
unsigned getVOPDOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:427
llvm::AMDGPU::splitMUBUFOffset
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, Align Alignment)
Definition: AMDGPUBaseInfo.cpp:2308
llvm::AMDGPU::SendMsg::STREAM_ID_NONE_
@ STREAM_ID_NONE_
Definition: SIDefines.h:372
llvm::AMDGPU::MIMGInfo
Definition: AMDGPUBaseInfo.h:400
llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
Definition: AMDGPUBaseInfo.cpp:1479
llvm::AMDGPU::Exp::getTgtId
unsigned getTgtId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1381
llvm::AMDGPU::mapWMMA3AddrTo2AddrOpcode
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:446
llvm::CallingConv::AMDGPU_Gfx
@ AMDGPU_Gfx
Used for AMD graphics targets.
Definition: CallingConv.h:233
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicSICI
const StringLiteral NfmtSymbolicSICI[]
Definition: AMDGPUAsmUtils.cpp:171
llvm::AMDGPU::MTBUFFormat::NFMT_SHIFT
@ NFMT_SHIFT
Definition: SIDefines.h:514
llvm::AMDGPU::getTotalNumVGPRs
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
Definition: AMDGPUBaseInfo.cpp:1846
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:177
llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:879
llvm::AMDGPU::SendMsg::isValidMsgStream
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1600
llvm::AMDGPU::MTBUFFormat::getNfmtName
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1459
AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32
@ AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32
Definition: AMDKernelCodeT.h:127
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc1
uint32_t compute_pgm_rsrc1
Definition: AMDHSAKernelDescriptor.h:178
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::AMDGPU::SendMsg::STREAM_ID_SHIFT_
@ STREAM_ID_SHIFT_
Definition: SIDefines.h:376
llvm::AMDGPU::getLgkmcntBitMask
unsigned getLgkmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:1053
llvm::GlobalValue::getAddressSpace
unsigned getAddressSpace() const
Definition: Globals.cpp:121
llvm::GCNSubtarget::getGeneration
Generation getGeneration() const
Definition: GCNSubtarget.h:266
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::AMDGPU::Hwreg::WIDTH_M1_MASK_
@ WIDTH_M1_MASK_
Definition: SIDefines.h:432
llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs
uint8_t NumExtraArgs
Definition: AMDGPUBaseInfo.h:308
llvm::AMDGPU::isInlinableLiteral32
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:2121
llvm::AMDGPU::isSISrcFPOperand
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
Definition: AMDGPUBaseInfo.cpp:1950
llvm::AMDGPU::isGFX8Plus
bool isGFX8Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1774
llvm::FeatureBitset::test
constexpr bool test(unsigned I) const
Definition: SubtargetFeature.h:87
llvm::AMDGPU::isNotGFX11Plus
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1798
llvm::AMDGPU::encodeExpcnt
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
Definition: AMDGPUBaseInfo.cpp:1111
llvm::AMDGPU::Exp::ET_POS_MAX_IDX
@ ET_POS_MAX_IDX
Definition: SIDefines.h:877
llvm::AMDGPU::isGCN3Encoding
bool isGCN3Encoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1810
llvm::AMDGPU::MTBUFFormat::getNfmt
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1450
llvm::AMDGPU::Exp::ExpTgt
Definition: AMDGPUBaseInfo.cpp:1354
llvm::AMDGPU::isValidOpr
static bool isValidOpr(int Idx, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context)
Definition: AMDGPUBaseInfo.cpp:1148
llvm::AMDGPU::SendMsg::getMsgOpName
StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1594
llvm::AMDGPU::VOPDComponentInfo::BaseVOP
uint16_t BaseVOP
Definition: AMDGPUBaseInfo.cpp:276
llvm::AMDGPU::Exp::ET_PRIM_MAX_IDX
@ ET_PRIM_MAX_IDX
Definition: SIDefines.h:875
llvm::AMDGPU::getNumFlatOffsetBits
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed)
For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
Definition: AMDGPUBaseInfo.cpp:2293
llvm::AMDGPU::SendMsg::ID_GS_DONE_PreGFX11
@ ID_GS_DONE_PreGFX11
Definition: SIDefines.h:322
N
#define N
AMDKernelCodeT.h
llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:715
llvm::AMDGPU::IsaInfo::getMaxWavesPerEU
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:706
llvm::AMDGPU::isHsaAbiVersion3AndAbove
bool isHsaAbiVersion3AndAbove(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:143
llvm::AMDGPU::MTBUFFormat::DfmtNfmt2UFmtGFX10
const unsigned DfmtNfmt2UFmtGFX10[]
Definition: AMDGPUAsmUtils.cpp:287
llvm::AMDGPU::IsaInfo::getMinNumVGPRs
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:885
llvm::AMDGPU::MTBUFFormat::UFMT_MAX
@ UFMT_MAX
Definition: SIDefines.h:530
llvm::AMDGPU::hasMIMG_R128
bool hasMIMG_R128(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1733
llvm::AMDGPU::getCanBeVOPD
CanBeVOPD getCanBeVOPD(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:419
llvm::AMDGPU::MIMGBaseOpcodeInfo::G16
bool G16
Definition: AMDGPUBaseInfo.h:310
llvm::AMDGPU::Exp::ET_NULL_MAX_IDX
@ ET_NULL_MAX_IDX
Definition: SIDefines.h:873
llvm::DenormalMode::Output
DenormalModeKind Output
Denormal flushing mode for floating point instruction results in the default floating point environme...
Definition: FloatingPointMode.h:87
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:171
llvm::StringRef::str
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:221
llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumVGPRs
constexpr char NumVGPRs[]
Key for Kernel::CodeProps::Metadata::mNumVGPRs.
Definition: AMDGPUMetadata.h:260
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setTargetIDFromFeaturesString
void setTargetIDFromFeaturesString(StringRef FS)
Definition: AMDGPUBaseInfo.cpp:474
llvm::AMDGPU::isReadOnlySegment
bool isReadOnlySegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:993
llvm::CallingConv::AMDGPU_VS
@ AMDGPU_VS
Used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (vertex shader if tess...
Definition: CallingConv.h:189
llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
Definition: AMDGPU.h:379
llvm::AMDGPU::SendMsg::OP_NONE_
@ OP_NONE_
Definition: SIDefines.h:351
llvm::AMDGPU::isLegalSMRDEncodedSignedOffset
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
Definition: AMDGPUBaseInfo.cpp:2246
llvm::AMDGPU::VOPDComponentInfo::CanBeVOPDX
bool CanBeVOPDX
Definition: AMDGPUBaseInfo.cpp:278
llvm::AMDGPU::OPERAND_REG_IMM_FP16
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:159
llvm::AMDGPU::Exp::ET_PARAM31
@ ET_PARAM31
Definition: SIDefines.h:871
S_00B848_WGP_MODE
#define S_00B848_WGP_MODE(x)
Definition: SIDefines.h:1008
LLVMContext.h
llvm::AMDGPU::encodeLgkmcnt
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
Definition: AMDGPUBaseInfo.cpp:1117
llvm::AMDGPU::MAIInstInfo
Definition: AMDGPUBaseInfo.h:74
llvm::cl::desc
Definition: CommandLine.h:413
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:189
llvm::AMDGPU::MTBUFFormat::getDfmt
int64_t getDfmt(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1429
llvm::AMDGPU::MTBUFFormat::DfmtNfmt2UFmtGFX11
const unsigned DfmtNfmt2UFmtGFX11[]
Definition: AMDGPUAsmUtils.cpp:461
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:241
llvm::AMDGPU::CustomOperandVal
Definition: AMDGPUAsmUtils.h:34
llvm::AMDGPU::Waitcnt::ExpCnt
unsigned ExpCnt
Definition: AMDGPUBaseInfo.h:553
llvm::AMDGPU::getIntegerPairAttribute
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
Definition: AMDGPUBaseInfo.cpp:1018
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isSramEccSupported
bool isSramEccSupported() const
Definition: AMDGPUBaseInfo.h:145
llvm::AMDGPU::SendMsg::ID_GS_PreGFX11
@ ID_GS_PreGFX11
Definition: SIDefines.h:321
llvm::AMDGPU::MTBUFInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:253
llvm::AMDGPU::isKernelCC
bool isKernelCC(const Function *Func)
Definition: AMDGPUBaseInfo.cpp:1721
llvm::AMDGPU::MTBUFInfo::has_srsrc
bool has_srsrc
Definition: AMDGPUBaseInfo.cpp:257
llvm::AMDGPU::getHostcallImplicitArgPosition
unsigned getHostcallImplicitArgPosition()
Definition: AMDGPUBaseInfo.cpp:169
llvm::AMDGPU::SendMsg::getMsgIdMask
static uint64_t getMsgIdMask(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1544
llvm::AMDGPU::SendMsg::OP_MASK_
@ OP_MASK_
Definition: SIDefines.h:354
llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName
StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1499
llvm::AMDGPU::VOPDComponentInfo
Definition: AMDGPUBaseInfo.cpp:275
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::AMDGPU::MUBUFInfo
Definition: AMDGPUBaseInfo.cpp:242
llvm::AMDGPU::Exp::ET_MRT_MAX_IDX
@ ET_MRT_MAX_IDX
Definition: SIDefines.h:876
llvm::StringRef::split
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:689
llvm::AMDGPU::getHasColorExport
bool getHasColorExport(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1661
llvm::AMDGPU::getHasDepthExport
bool getHasDepthExport(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1668
llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V3
@ ELFABIVERSION_AMDGPU_HSA_V3
Definition: ELF.h:375
llvm::AMDGPU::IsaInfo::getVGPRAllocGranule
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:838
llvm::AMDGPU::SendMsg::getMsgName
StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1557
llvm::AMDGPU::getMaskedMIMGOp
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
Definition: AMDGPUBaseInfo.cpp:206
llvm::AMDGPU::getMTBUFElements
int getMTBUFElements(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:330
llvm::AMDGPU::OPERAND_REG_INLINE_C_LAST
@ OPERAND_REG_INLINE_C_LAST
Definition: SIDefines.h:198
llvm::AMDGPU::UfmtGFX10::UFMT_LAST
@ UFMT_LAST
Definition: SIDefines.h:632
AMDGPUBaseInfo.h
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:190
llvm::AMDGPU::getOprIdx
static int getOprIdx(std::function< bool(const CustomOperand< T > &)> Test, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context)
Definition: AMDGPUBaseInfo.cpp:1155
llvm::AMDGPU::MTBUFFormat::DFMT_MAX
@ DFMT_MAX
Definition: SIDefines.h:488
llvm::AMDGPU::MIMGDimInfo::NumCoords
uint8_t NumCoords
Definition: AMDGPUBaseInfo.h:326