20#include "llvm/IR/IntrinsicsAMDGPU.h"
21#include "llvm/IR/IntrinsicsR600.h"
31#define GET_INSTRINFO_NAMED_OPS
32#define GET_INSTRMAP_INFO
33#include "AMDGPUGenInstrInfo.inc"
38 llvm::cl::desc(
"Set default AMDHSA Code Object Version (module flag "
39 "or asm directive still take priority if present)"));
44unsigned getBitMask(
unsigned Shift,
unsigned Width) {
45 return ((1 << Width) - 1) << Shift;
51unsigned packBits(
unsigned Src,
unsigned Dst,
unsigned Shift,
unsigned Width) {
52 unsigned Mask = getBitMask(Shift, Width);
53 return ((Src << Shift) & Mask) | (Dst & ~Mask);
59unsigned unpackBits(
unsigned Src,
unsigned Shift,
unsigned Width) {
60 return (Src & getBitMask(Shift, Width)) >> Shift;
64unsigned getVmcntBitShiftLo(
unsigned VersionMajor) {
69unsigned getVmcntBitWidthLo(
unsigned VersionMajor) {
74unsigned getExpcntBitShift(
unsigned VersionMajor) {
79unsigned getExpcntBitWidth(
unsigned VersionMajor) {
return 3; }
82unsigned getLgkmcntBitShift(
unsigned VersionMajor) {
87unsigned getLgkmcntBitWidth(
unsigned VersionMajor) {
92unsigned getVmcntBitShiftHi(
unsigned VersionMajor) {
return 14; }
95unsigned getVmcntBitWidthHi(
unsigned VersionMajor) {
96 return (VersionMajor == 9 || VersionMajor == 10) ? 2 : 0;
100unsigned getLoadcntBitWidth(
unsigned VersionMajor) {
105unsigned getSamplecntBitWidth(
unsigned VersionMajor) {
110unsigned getBvhcntBitWidth(
unsigned VersionMajor) {
115unsigned getDscntBitWidth(
unsigned VersionMajor) {
120unsigned getDscntBitShift(
unsigned VersionMajor) {
return 0; }
123unsigned getStorecntBitWidth(
unsigned VersionMajor) {
128unsigned getKmcntBitWidth(
unsigned VersionMajor) {
133unsigned getLoadcntStorecntBitShift(
unsigned VersionMajor) {
138inline unsigned getVmVsrcBitWidth() {
return 3; }
141inline unsigned getVmVsrcBitShift() {
return 2; }
144inline unsigned getVaVdstBitWidth() {
return 4; }
147inline unsigned getVaVdstBitShift() {
return 12; }
150inline unsigned getSaSdstBitWidth() {
return 1; }
153inline unsigned getSaSdstBitShift() {
return 0; }
167 if (
auto Ver = mdconst::extract_or_null<ConstantInt>(
168 M.getModuleFlag(
"amdhsa_code_object_version"))) {
169 return (
unsigned)Ver->getZExtValue() / 100;
180 switch (ABIVersion) {
194 switch (CodeObjectVersion) {
203 Twine(CodeObjectVersion));
208 switch (CodeObjectVersion) {
222 switch (CodeObjectVersion) {
233 switch (CodeObjectVersion) {
244 switch (CodeObjectVersion) {
254#define GET_MIMGBaseOpcodesTable_IMPL
255#define GET_MIMGDimInfoTable_IMPL
256#define GET_MIMGInfoTable_IMPL
257#define GET_MIMGLZMappingTable_IMPL
258#define GET_MIMGMIPMappingTable_IMPL
259#define GET_MIMGBiasMappingTable_IMPL
260#define GET_MIMGOffsetMappingTable_IMPL
261#define GET_MIMGG16MappingTable_IMPL
262#define GET_MAIInstInfoTable_IMPL
263#include "AMDGPUGenSearchableTables.inc"
266 unsigned VDataDwords,
unsigned VAddrDwords) {
267 const MIMGInfo *
Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding,
268 VDataDwords, VAddrDwords);
282 return NewInfo ? NewInfo->
Opcode : -1;
287 bool IsG16Supported) {
294 AddrWords += AddrComponents;
302 if ((IsA16 && !IsG16Supported) || BaseOpcode->
G16)
372#define GET_MTBUFInfoTable_DECL
373#define GET_MTBUFInfoTable_IMPL
374#define GET_MUBUFInfoTable_DECL
375#define GET_MUBUFInfoTable_IMPL
376#define GET_SMInfoTable_DECL
377#define GET_SMInfoTable_IMPL
378#define GET_VOP1InfoTable_DECL
379#define GET_VOP1InfoTable_IMPL
380#define GET_VOP2InfoTable_DECL
381#define GET_VOP2InfoTable_IMPL
382#define GET_VOP3InfoTable_DECL
383#define GET_VOP3InfoTable_IMPL
384#define GET_VOPC64DPPTable_DECL
385#define GET_VOPC64DPPTable_IMPL
386#define GET_VOPC64DPP8Table_DECL
387#define GET_VOPC64DPP8Table_IMPL
388#define GET_VOPCAsmOnlyInfoTable_DECL
389#define GET_VOPCAsmOnlyInfoTable_IMPL
390#define GET_VOP3CAsmOnlyInfoTable_DECL
391#define GET_VOP3CAsmOnlyInfoTable_IMPL
392#define GET_VOPDComponentTable_DECL
393#define GET_VOPDComponentTable_IMPL
394#define GET_VOPDPairs_DECL
395#define GET_VOPDPairs_IMPL
396#define GET_VOPTrue16Table_DECL
397#define GET_VOPTrue16Table_IMPL
398#define GET_WMMAOpcode2AddrMappingTable_DECL
399#define GET_WMMAOpcode2AddrMappingTable_IMPL
400#define GET_WMMAOpcode3AddrMappingTable_DECL
401#define GET_WMMAOpcode3AddrMappingTable_IMPL
402#include "AMDGPUGenSearchableTables.inc"
406 return Info ?
Info->BaseOpcode : -1;
410 const MTBUFInfo *
Info = getMTBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
421 return Info ?
Info->has_vaddr :
false;
426 return Info ?
Info->has_srsrc :
false;
431 return Info ?
Info->has_soffset :
false;
436 return Info ?
Info->BaseOpcode : -1;
440 const MUBUFInfo *
Info = getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
451 return Info ?
Info->has_vaddr :
false;
456 return Info ?
Info->has_srsrc :
false;
461 return Info ?
Info->has_soffset :
false;
466 return Info ?
Info->IsBufferInv :
false;
470 const SMInfo *
Info = getSMEMOpcodeHelper(Opc);
471 return Info ?
Info->IsBuffer :
false;
476 return Info ?
Info->IsSingle :
false;
481 return Info ?
Info->IsSingle :
false;
486 return Info ?
Info->IsSingle :
false;
490 return isVOPC64DPPOpcodeHelper(Opc) || isVOPC64DPP8OpcodeHelper(Opc);
494 return isVOPCAsmOnlyOpcodeHelper(Opc) || isVOP3CAsmOnlyOpcodeHelper(Opc);
499 return Info ?
Info->is_dgemm :
false;
504 return Info ?
Info->is_gfx940_xdl :
false;
508 if (ST.hasFeature(AMDGPU::FeatureGFX12Insts))
510 if (ST.hasFeature(AMDGPU::FeatureGFX11Insts))
518 return {
Info->CanBeVOPDX,
true};
520 return {
false,
false};
533 return Opc == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
534 Opc == AMDGPU::V_MAC_F32_e64_gfx10 ||
535 Opc == AMDGPU::V_MAC_F32_e64_vi ||
536 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 ||
537 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 ||
538 Opc == AMDGPU::V_MAC_F16_e64_vi ||
539 Opc == AMDGPU::V_FMAC_F64_e64_gfx90a ||
540 Opc == AMDGPU::V_FMAC_F32_e64_gfx10 ||
541 Opc == AMDGPU::V_FMAC_F32_e64_gfx11 ||
542 Opc == AMDGPU::V_FMAC_F32_e64_gfx12 ||
543 Opc == AMDGPU::V_FMAC_F32_e64_vi ||
544 Opc == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 ||
545 Opc == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 ||
546 Opc == AMDGPU::V_FMAC_F16_e64_gfx10 ||
547 Opc == AMDGPU::V_FMAC_F16_t16_e64_gfx11 ||
548 Opc == AMDGPU::V_FMAC_F16_t16_e64_gfx12 ||
549 Opc == AMDGPU::V_DOT2C_F32_F16_e64_vi ||
550 Opc == AMDGPU::V_DOT2C_I32_I16_e64_vi ||
551 Opc == AMDGPU::V_DOT4C_I32_I8_e64_vi ||
552 Opc == AMDGPU::V_DOT8C_I32_I4_e64_vi;
556 return Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
557 Opc == AMDGPU::V_PERMLANEX16_B32_gfx10 ||
558 Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx11 ||
559 Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx11 ||
560 Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx12 ||
561 Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx12 ||
562 Opc == AMDGPU::V_PERMLANE16_VAR_B32_e64_gfx12 ||
563 Opc == AMDGPU::V_PERMLANEX16_VAR_B32_e64_gfx12;
567 return Opc == AMDGPU::V_CVT_F32_BF8_e64_gfx12 ||
568 Opc == AMDGPU::V_CVT_F32_FP8_e64_gfx12 ||
569 Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp_gfx12 ||
570 Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp_gfx12 ||
571 Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp8_gfx12 ||
572 Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp8_gfx12 ||
573 Opc == AMDGPU::V_CVT_PK_F32_BF8_e64_gfx12 ||
574 Opc == AMDGPU::V_CVT_PK_F32_FP8_e64_gfx12;
578 return Opc == AMDGPU::G_AMDGPU_ATOMIC_FMIN ||
579 Opc == AMDGPU::G_AMDGPU_ATOMIC_FMAX ||
580 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP ||
581 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD ||
582 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB ||
583 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN ||
584 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN ||
585 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX ||
586 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX ||
587 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND ||
588 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR ||
589 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR ||
590 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC ||
591 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC ||
592 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD ||
593 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN ||
594 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX ||
595 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP ||
596 Opc == AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG;
601 return Info ?
Info->IsTrue16 :
false;
606 return Info ?
Info->Opcode3Addr : ~0u;
611 return Info ?
Info->Opcode2Addr : ~0u;
618 return getMCOpcodeGen(Opcode,
static_cast<Subtarget
>(Gen));
621int getVOPDFull(
unsigned OpX,
unsigned OpY,
unsigned EncodingFamily) {
623 getVOPDInfoFromComponentOpcodes(OpX, OpY, EncodingFamily);
630 auto OpX = getVOPDBaseFromComponent(
Info->OpX);
631 auto OpY = getVOPDBaseFromComponent(
Info->OpY);
633 return {OpX->BaseVOP, OpY->BaseVOP};
645 HasSrc2Acc = TiedIdx != -1;
652 for (CompOprIdx =
Component::SRC1; CompOprIdx < OperandsNum; ++CompOprIdx) {
654 MandatoryLiteralIdx = CompOprIdx;
675 std::function<
unsigned(
unsigned,
unsigned)> GetRegIdx,
bool SkipSrc)
const {
680 const unsigned CompOprNum =
683 for (CompOprIdx = 0; CompOprIdx < CompOprNum; ++CompOprIdx) {
685 if (OpXRegs[CompOprIdx] && OpYRegs[CompOprIdx] &&
686 ((OpXRegs[CompOprIdx] & BanksMasks) ==
687 (OpYRegs[CompOprIdx] & BanksMasks)))
703 std::function<
unsigned(
unsigned,
unsigned)> GetRegIdx)
const {
706 const auto &Comp = CompInfo[CompIdx];
709 RegIndices[
DST] = GetRegIdx(CompIdx, Comp.getIndexOfDstInMCOperands());
712 unsigned CompSrcIdx = CompOprIdx -
DST_NUM;
714 Comp.hasRegSrcOperand(CompSrcIdx)
715 ? GetRegIdx(CompIdx, Comp.getIndexOfSrcInMCOperands(CompSrcIdx))
730 const auto &OpXDesc = InstrInfo->
get(OpX);
731 const auto &OpYDesc = InstrInfo->
get(OpY);
753 std::optional<bool> XnackRequested;
754 std::optional<bool> SramEccRequested;
756 for (
const std::string &Feature : Features.
getFeatures()) {
757 if (Feature ==
"+xnack")
758 XnackRequested =
true;
759 else if (Feature ==
"-xnack")
760 XnackRequested =
false;
761 else if (Feature ==
"+sramecc")
762 SramEccRequested =
true;
763 else if (Feature ==
"-sramecc")
764 SramEccRequested =
false;
770 if (XnackRequested) {
771 if (XnackSupported) {
777 if (*XnackRequested) {
778 errs() <<
"warning: xnack 'On' was requested for a processor that does "
781 errs() <<
"warning: xnack 'Off' was requested for a processor that "
782 "does not support it!\n";
787 if (SramEccRequested) {
788 if (SramEccSupported) {
795 if (*SramEccRequested) {
796 errs() <<
"warning: sramecc 'On' was requested for a processor that "
797 "does not support it!\n";
799 errs() <<
"warning: sramecc 'Off' was requested for a processor that "
800 "does not support it!\n";
818 TargetID.
split(TargetIDSplit,
':');
820 for (
const auto &FeatureString : TargetIDSplit) {
821 if (FeatureString.starts_with(
"xnack"))
823 if (FeatureString.starts_with(
"sramecc"))
829 std::string StringRep;
835 StreamRep << TargetTriple.getArchName() <<
'-'
836 << TargetTriple.getVendorName() <<
'-'
837 << TargetTriple.getOSName() <<
'-'
838 << TargetTriple.getEnvironmentName() <<
'-';
840 std::string Processor;
844 if (Version.Major >= 9)
847 Processor = (
Twine(
"gfx") +
Twine(Version.Major) +
Twine(Version.Minor) +
848 Twine(Version.Stepping))
851 std::string Features;
855 Features +=
":sramecc-";
857 Features +=
":sramecc+";
860 Features +=
":xnack-";
862 Features +=
":xnack+";
865 StreamRep << Processor << Features;
881 unsigned BytesPerCU = 0;
916 unsigned FlatWorkGroupSize) {
917 assert(FlatWorkGroupSize != 0);
927 unsigned MaxBarriers = 16;
931 return std::min(MaxWaves /
N, MaxBarriers);
948 unsigned FlatWorkGroupSize) {
963 unsigned FlatWorkGroupSize) {
969 if (Version.Major >= 10)
971 if (Version.Major >= 8)
982 if (Version.Major >= 8)
992 if (Version.Major >= 10)
994 if (Version.Major >= 8)
1003 if (Version.Major >= 10)
1022 if (Version.Major >= 10)
1023 return Addressable ? AddressableNumSGPRs : 108;
1024 if (Version.Major >= 8 && !Addressable)
1025 AddressableNumSGPRs = 112;
1030 return std::min(MaxNumSGPRs, AddressableNumSGPRs);
1034 bool FlatScrUsed,
bool XNACKUsed) {
1035 unsigned ExtraSGPRs = 0;
1040 if (Version.Major >= 10)
1043 if (Version.Major < 8) {
1066 return divideCeil(std::max(1u, NumRegs), Granule);
1076 std::optional<bool> EnableWavefrontSize32) {
1080 bool IsWave32 = EnableWavefrontSize32 ?
1081 *EnableWavefrontSize32 :
1085 return IsWave32 ? 24 : 12;
1088 return IsWave32 ? 16 : 8;
1090 return IsWave32 ? 8 : 4;
1094 std::optional<bool> EnableWavefrontSize32) {
1098 bool IsWave32 = EnableWavefrontSize32 ?
1099 *EnableWavefrontSize32 :
1102 return IsWave32 ? 8 : 4;
1112 return IsWave32 ? 1536 : 768;
1113 return IsWave32 ? 1024 : 512;
1125 unsigned NumVGPRs) {
1128 if (NumVGPRs < Granule)
1130 unsigned RoundedRegs =
alignTo(NumVGPRs, Granule);
1131 return std::min(std::max(
getTotalNumVGPRs(STI) / RoundedRegs, 1u), MaxWaves);
1138 if (WavesPerEU >= MaxWavesPerEU)
1144 unsigned MaxNumVGPRs =
alignDown(TotNumVGPRs / WavesPerEU, Granule);
1146 if (MaxNumVGPRs ==
alignDown(TotNumVGPRs / MaxWavesPerEU, Granule))
1150 if (WavesPerEU < MinWavesPerEU)
1153 unsigned MaxNumVGPRsNext =
alignDown(TotNumVGPRs / (WavesPerEU + 1), Granule);
1154 unsigned MinNumVGPRs = 1 + std::min(MaxNumVGPRs - Granule, MaxNumVGPRsNext);
1155 return std::min(MinNumVGPRs, AddrsableNumVGPRs);
1164 return std::min(MaxNumVGPRs, AddressableNumVGPRs);
1168 std::optional<bool> EnableWavefrontSize32) {
1176 std::optional<bool> EnableWavefrontSize32) {
1186 memset(&Header, 0,
sizeof(Header));
1188 Header.amd_kernel_code_version_major = 1;
1189 Header.amd_kernel_code_version_minor = 2;
1190 Header.amd_machine_kind = 1;
1191 Header.amd_machine_version_major = Version.Major;
1192 Header.amd_machine_version_minor = Version.Minor;
1193 Header.amd_machine_version_stepping = Version.Stepping;
1194 Header.kernel_code_entry_byte_offset =
sizeof(Header);
1195 Header.wavefront_size = 6;
1199 Header.call_convention = -1;
1203 Header.kernarg_segment_alignment = 4;
1204 Header.group_segment_alignment = 4;
1205 Header.private_segment_alignment = 4;
1207 if (Version.Major >= 10) {
1209 Header.wavefront_size = 5;
1212 Header.compute_pgm_resource_registers |=
1223 memset(&KD, 0,
sizeof(KD));
1226 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64,
1228 if (Version.Major >= 12) {
1230 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN, 0);
1232 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_DISABLE_PERF, 0);
1235 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP, 1);
1237 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE, 1);
1240 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, 1);
1241 if (Version.Major >= 10) {
1243 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
1246 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE,
1249 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED, 1);
1253 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT,
1277std::pair<unsigned, unsigned>
1279 std::pair<unsigned, unsigned>
Default,
1280 bool OnlyFirstRequired) {
1282 if (!
A.isStringAttribute())
1286 std::pair<unsigned, unsigned> Ints =
Default;
1287 std::pair<StringRef, StringRef> Strs =
A.getValueAsString().split(
',');
1288 if (Strs.first.trim().getAsInteger(0, Ints.first)) {
1289 Ctx.
emitError(
"can't parse first integer attribute " +
Name);
1292 if (Strs.second.trim().getAsInteger(0, Ints.second)) {
1293 if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
1294 Ctx.
emitError(
"can't parse second integer attribute " +
Name);
1308 if (!
A.isStringAttribute())
1318 std::pair<StringRef, StringRef> Strs = S.
split(
',');
1320 if (Strs.first.trim().getAsInteger(0, IntVal)) {
1321 Ctx.
emitError(
"can't parse integer attribute " + Strs.first +
" in " +
1331 " has incorrect number of integers; expected " +
1332 llvm::utostr(
Size));
1339 return (1 << (getVmcntBitWidthLo(Version.Major) +
1340 getVmcntBitWidthHi(Version.Major))) -
1345 return (1 << getLoadcntBitWidth(Version.Major)) - 1;
1349 return (1 << getSamplecntBitWidth(Version.Major)) - 1;
1353 return (1 << getBvhcntBitWidth(Version.Major)) - 1;
1357 return (1 << getExpcntBitWidth(Version.Major)) - 1;
1361 return (1 << getLgkmcntBitWidth(Version.Major)) - 1;
1365 return (1 << getDscntBitWidth(Version.Major)) - 1;
1369 return (1 << getKmcntBitWidth(Version.Major)) - 1;
1373 return (1 << getStorecntBitWidth(Version.Major)) - 1;
1377 unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(Version.Major),
1378 getVmcntBitWidthLo(Version.Major));
1379 unsigned Expcnt = getBitMask(getExpcntBitShift(Version.Major),
1380 getExpcntBitWidth(Version.Major));
1381 unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(Version.Major),
1382 getLgkmcntBitWidth(Version.Major));
1383 unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(Version.Major),
1384 getVmcntBitWidthHi(Version.Major));
1385 return VmcntLo | Expcnt | Lgkmcnt | VmcntHi;
1389 unsigned VmcntLo = unpackBits(
Waitcnt, getVmcntBitShiftLo(Version.Major),
1390 getVmcntBitWidthLo(Version.Major));
1391 unsigned VmcntHi = unpackBits(
Waitcnt, getVmcntBitShiftHi(Version.Major),
1392 getVmcntBitWidthHi(Version.Major));
1393 return VmcntLo | VmcntHi << getVmcntBitWidthLo(Version.Major);
1397 return unpackBits(
Waitcnt, getExpcntBitShift(Version.Major),
1398 getExpcntBitWidth(Version.Major));
1402 return unpackBits(
Waitcnt, getLgkmcntBitShift(Version.Major),
1403 getLgkmcntBitWidth(Version.Major));
1407 unsigned &Vmcnt,
unsigned &Expcnt,
unsigned &Lgkmcnt) {
1423 Waitcnt = packBits(Vmcnt,
Waitcnt, getVmcntBitShiftLo(Version.Major),
1424 getVmcntBitWidthLo(Version.Major));
1425 return packBits(Vmcnt >> getVmcntBitWidthLo(Version.Major),
Waitcnt,
1426 getVmcntBitShiftHi(Version.Major),
1427 getVmcntBitWidthHi(Version.Major));
1432 return packBits(Expcnt,
Waitcnt, getExpcntBitShift(Version.Major),
1433 getExpcntBitWidth(Version.Major));
1438 return packBits(Lgkmcnt,
Waitcnt, getLgkmcntBitShift(Version.Major),
1439 getLgkmcntBitWidth(Version.Major));
1443 unsigned Vmcnt,
unsigned Expcnt,
unsigned Lgkmcnt) {
1457 unsigned Dscnt = getBitMask(getDscntBitShift(Version.Major),
1458 getDscntBitWidth(Version.Major));
1460 unsigned Storecnt = getBitMask(getLoadcntStorecntBitShift(Version.Major),
1461 getStorecntBitWidth(Version.Major));
1462 return Dscnt | Storecnt;
1464 unsigned Loadcnt = getBitMask(getLoadcntStorecntBitShift(Version.Major),
1465 getLoadcntBitWidth(Version.Major));
1466 return Dscnt | Loadcnt;
1473 unpackBits(LoadcntDscnt, getLoadcntStorecntBitShift(Version.Major),
1474 getLoadcntBitWidth(Version.Major));
1475 Decoded.
DsCnt = unpackBits(LoadcntDscnt, getDscntBitShift(Version.Major),
1476 getDscntBitWidth(Version.Major));
1483 unpackBits(StorecntDscnt, getLoadcntStorecntBitShift(Version.Major),
1484 getStorecntBitWidth(Version.Major));
1485 Decoded.
DsCnt = unpackBits(StorecntDscnt, getDscntBitShift(Version.Major),
1486 getDscntBitWidth(Version.Major));
1492 return packBits(Loadcnt,
Waitcnt, getLoadcntStorecntBitShift(Version.Major),
1493 getLoadcntBitWidth(Version.Major));
1497 unsigned Storecnt) {
1498 return packBits(Storecnt,
Waitcnt, getLoadcntStorecntBitShift(Version.Major),
1499 getStorecntBitWidth(Version.Major));
1504 return packBits(Dscnt,
Waitcnt, getDscntBitShift(Version.Major),
1505 getDscntBitWidth(Version.Major));
1521 unsigned Storecnt,
unsigned Dscnt) {
1556 for (
int Idx = 0;
Idx < OpInfoSize; ++
Idx) {
1568 int OpInfoSize,
T Context) {
1570 return getOprIdx<T>(
Test, OpInfo, OpInfoSize,
Context);
1575 T Context,
bool QuickCheck =
true) {
1582 if (QuickCheck && isValidOpr<T>(Id, OpInfo, OpInfoSize,
Context) &&
1586 return getOprIdx<T>(
Test, OpInfo, OpInfoSize,
Context);
1598 const auto &
Op = Opr[
Idx];
1599 if (
Op.isSupported(STI))
1600 Enc |=
Op.encode(
Op.Default);
1606 int Size,
unsigned Code,
1607 bool &HasNonDefaultVal,
1609 unsigned UsedOprMask = 0;
1610 HasNonDefaultVal =
false;
1612 const auto &
Op = Opr[
Idx];
1613 if (!
Op.isSupported(STI))
1615 UsedOprMask |=
Op.getMask();
1616 unsigned Val =
Op.decode(Code);
1617 if (!
Op.isValid(Val))
1619 HasNonDefaultVal |= (Val !=
Op.Default);
1621 return (Code & ~UsedOprMask) == 0;
1626 unsigned &Val,
bool &IsDefault,
1629 const auto &
Op = Opr[
Idx++];
1630 if (
Op.isSupported(STI)) {
1632 Val =
Op.decode(Code);
1633 IsDefault = (Val ==
Op.Default);
1643 if (InputVal < 0 || InputVal >
Op.Max)
1645 return Op.encode(InputVal);
1650 unsigned &UsedOprMask,
1654 const auto &
Op = Opr[
Idx];
1656 if (!
Op.isSupported(STI)) {
1660 auto OprMask =
Op.getMask();
1661 if (OprMask & UsedOprMask)
1663 UsedOprMask |= OprMask;
1686 HasNonDefaultVal, STI);
1702 return unpackBits(Encoded, getVmVsrcBitShift(), getVmVsrcBitWidth());
1706 return unpackBits(Encoded, getVaVdstBitShift(), getVaVdstBitWidth());
1710 return unpackBits(Encoded, getSaSdstBitShift(), getSaSdstBitWidth());
1714 return packBits(VmVsrc, Encoded, getVmVsrcBitShift(), getVmVsrcBitWidth());
1722 return packBits(VaVdst, Encoded, getVaVdstBitShift(), getVaVdstBitWidth());
1730 return packBits(SaSdst, Encoded, getSaSdstBitShift(), getSaSdstBitWidth());
1781 if (Val.Tgt <= Id && Id <= Val.Tgt + Val.MaxIndex) {
1782 Index = (Val.MaxIndex == 0) ? -1 : (Id - Val.Tgt);
1793 if (Val.MaxIndex == 0 &&
Name == Val.Name)
1796 if (Val.MaxIndex > 0 &&
Name.starts_with(Val.Name)) {
1804 if (Suffix.
size() > 1 && Suffix[0] ==
'0')
1807 return Val.Tgt + Id;
1836namespace MTBUFFormat {
1862 if (
Name == lookupTable[Id])
1967 int Idx = getOprIdx<const MCSubtargetInfo &>(MsgId,
Msg,
MSG_SIZE, STI);
1975 for (
int i =
F; i < L; ++i) {
1988 return 0 <= OpId && isUInt<OP_WIDTH_>(OpId);
2067 return F.getFnAttributeAsParsedInteger(
"InitialPSInputAddr", 0);
2072 return F.getFnAttributeAsParsedInteger(
2073 "amdgpu-color-export",
2078 return F.getFnAttributeAsParsedInteger(
"amdgpu-depth-export", 0) != 0;
2151 return STI.
hasFeature(AMDGPU::FeatureSRAMECC);
2167 return !STI.
hasFeature(AMDGPU::FeatureUnpackedD16VMem) && !
isCI(STI) &&
2177 if (Version.Major == 10)
2178 return Version.Minor >= 3 ? 13 : 5;
2179 if (Version.Major == 11)
2181 if (Version.Major >= 12)
2182 return HasSampler ? 4 : 5;
2189 return STI.
hasFeature(AMDGPU::FeatureSouthernIslands);
2193 return STI.
hasFeature(AMDGPU::FeatureSeaIslands);
2197 return STI.
hasFeature(AMDGPU::FeatureVolcanicIslands);
2265 return STI.
hasFeature(AMDGPU::FeatureGCN3Encoding);
2269 return STI.
hasFeature(AMDGPU::FeatureGFX10_AEncoding);
2273 return STI.
hasFeature(AMDGPU::FeatureGFX10_BEncoding);
2277 return STI.
hasFeature(AMDGPU::FeatureGFX10_3Insts);
2285 return STI.
hasFeature(AMDGPU::FeatureGFX90AInsts);
2289 return STI.
hasFeature(AMDGPU::FeatureGFX940Insts);
2293 return STI.
hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
2297 return STI.
hasFeature(AMDGPU::FeatureMAIInsts);
2305 return STI.
hasFeature(AMDGPU::FeatureDPPSrc1SGPR);
2309 return STI.
hasFeature(AMDGPU::FeatureKernargPreload);
2313 int32_t ArgNumVGPR) {
2314 if (has90AInsts && ArgNumAGPR)
2315 return alignTo(ArgNumVGPR, 4) + ArgNumAGPR;
2316 return std::max(ArgNumVGPR, ArgNumAGPR);
2321 const unsigned FirstSubReg =
TRI->getSubReg(
Reg, AMDGPU::sub0);
2322 return SGPRClass.
contains(FirstSubReg != 0 ? FirstSubReg :
Reg) ||
2330#define MAP_REG2REG \
2331 using namespace AMDGPU; \
2333 default: return Reg; \
2334 CASE_CI_VI(FLAT_SCR) \
2335 CASE_CI_VI(FLAT_SCR_LO) \
2336 CASE_CI_VI(FLAT_SCR_HI) \
2337 CASE_VI_GFX9PLUS(TTMP0) \
2338 CASE_VI_GFX9PLUS(TTMP1) \
2339 CASE_VI_GFX9PLUS(TTMP2) \
2340 CASE_VI_GFX9PLUS(TTMP3) \
2341 CASE_VI_GFX9PLUS(TTMP4) \
2342 CASE_VI_GFX9PLUS(TTMP5) \
2343 CASE_VI_GFX9PLUS(TTMP6) \
2344 CASE_VI_GFX9PLUS(TTMP7) \
2345 CASE_VI_GFX9PLUS(TTMP8) \
2346 CASE_VI_GFX9PLUS(TTMP9) \
2347 CASE_VI_GFX9PLUS(TTMP10) \
2348 CASE_VI_GFX9PLUS(TTMP11) \
2349 CASE_VI_GFX9PLUS(TTMP12) \
2350 CASE_VI_GFX9PLUS(TTMP13) \
2351 CASE_VI_GFX9PLUS(TTMP14) \
2352 CASE_VI_GFX9PLUS(TTMP15) \
2353 CASE_VI_GFX9PLUS(TTMP0_TTMP1) \
2354 CASE_VI_GFX9PLUS(TTMP2_TTMP3) \
2355 CASE_VI_GFX9PLUS(TTMP4_TTMP5) \
2356 CASE_VI_GFX9PLUS(TTMP6_TTMP7) \
2357 CASE_VI_GFX9PLUS(TTMP8_TTMP9) \
2358 CASE_VI_GFX9PLUS(TTMP10_TTMP11) \
2359 CASE_VI_GFX9PLUS(TTMP12_TTMP13) \
2360 CASE_VI_GFX9PLUS(TTMP14_TTMP15) \
2361 CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3) \
2362 CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7) \
2363 CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11) \
2364 CASE_VI_GFX9PLUS(TTMP12_TTMP13_TTMP14_TTMP15) \
2365 CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
2366 CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
2367 CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
2368 CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
2369 CASE_GFXPRE11_GFX11PLUS(M0) \
2370 CASE_GFXPRE11_GFX11PLUS(SGPR_NULL) \
2371 CASE_GFXPRE11_GFX11PLUS_TO(SGPR_NULL64, SGPR_NULL) \
2374#define CASE_CI_VI(node) \
2375 assert(!isSI(STI)); \
2376 case node: return isCI(STI) ? node##_ci : node##_vi;
2378#define CASE_VI_GFX9PLUS(node) \
2379 case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;
2381#define CASE_GFXPRE11_GFX11PLUS(node) \
2382 case node: return isGFX11Plus(STI) ? node##_gfx11plus : node##_gfxpre11;
2384#define CASE_GFXPRE11_GFX11PLUS_TO(node, result) \
2385 case node: return isGFX11Plus(STI) ? result##_gfx11plus : result##_gfxpre11;
2394#undef CASE_VI_GFX9PLUS
2395#undef CASE_GFXPRE11_GFX11PLUS
2396#undef CASE_GFXPRE11_GFX11PLUS_TO
2398#define CASE_CI_VI(node) case node##_ci: case node##_vi: return node;
2399#define CASE_VI_GFX9PLUS(node) case node##_vi: case node##_gfx9plus: return node;
2400#define CASE_GFXPRE11_GFX11PLUS(node) case node##_gfx11plus: case node##_gfxpre11: return node;
2401#define CASE_GFXPRE11_GFX11PLUS_TO(node, result)
2409 case AMDGPU::SRC_SHARED_BASE_LO:
2410 case AMDGPU::SRC_SHARED_BASE:
2411 case AMDGPU::SRC_SHARED_LIMIT_LO:
2412 case AMDGPU::SRC_SHARED_LIMIT:
2413 case AMDGPU::SRC_PRIVATE_BASE_LO:
2414 case AMDGPU::SRC_PRIVATE_BASE:
2415 case AMDGPU::SRC_PRIVATE_LIMIT_LO:
2416 case AMDGPU::SRC_PRIVATE_LIMIT:
2417 case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
2419 case AMDGPU::SRC_VCCZ:
2420 case AMDGPU::SRC_EXECZ:
2421 case AMDGPU::SRC_SCC:
2423 case AMDGPU::SGPR_NULL:
2431#undef CASE_VI_GFX9PLUS
2432#undef CASE_GFXPRE11_GFX11PLUS
2433#undef CASE_GFXPRE11_GFX11PLUS_TO
2438 unsigned OpType =
Desc.operands()[OpNo].OperandType;
2445 unsigned OpType =
Desc.operands()[OpNo].OperandType;
2452 unsigned OpType =
Desc.operands()[OpNo].OperandType;
2478 unsigned OpType =
Desc.operands()[OpNo].OperandType;
2489 case AMDGPU::SGPR_LO16RegClassID:
2490 case AMDGPU::AGPR_LO16RegClassID:
2492 case AMDGPU::SGPR_32RegClassID:
2493 case AMDGPU::VGPR_32RegClassID:
2494 case AMDGPU::VRegOrLds_32RegClassID:
2495 case AMDGPU::AGPR_32RegClassID:
2496 case AMDGPU::VS_32RegClassID:
2497 case AMDGPU::AV_32RegClassID:
2498 case AMDGPU::SReg_32RegClassID:
2499 case AMDGPU::SReg_32_XM0RegClassID:
2500 case AMDGPU::SRegOrLds_32RegClassID:
2502 case AMDGPU::SGPR_64RegClassID:
2503 case AMDGPU::VS_64RegClassID:
2504 case AMDGPU::SReg_64RegClassID:
2505 case AMDGPU::VReg_64RegClassID:
2506 case AMDGPU::AReg_64RegClassID:
2507 case AMDGPU::SReg_64_XEXECRegClassID:
2508 case AMDGPU::VReg_64_Align2RegClassID:
2509 case AMDGPU::AReg_64_Align2RegClassID:
2510 case AMDGPU::AV_64RegClassID:
2511 case AMDGPU::AV_64_Align2RegClassID:
2513 case AMDGPU::SGPR_96RegClassID:
2514 case AMDGPU::SReg_96RegClassID:
2515 case AMDGPU::VReg_96RegClassID:
2516 case AMDGPU::AReg_96RegClassID:
2517 case AMDGPU::VReg_96_Align2RegClassID:
2518 case AMDGPU::AReg_96_Align2RegClassID:
2519 case AMDGPU::AV_96RegClassID:
2520 case AMDGPU::AV_96_Align2RegClassID:
2522 case AMDGPU::SGPR_128RegClassID:
2523 case AMDGPU::SReg_128RegClassID:
2524 case AMDGPU::VReg_128RegClassID:
2525 case AMDGPU::AReg_128RegClassID:
2526 case AMDGPU::VReg_128_Align2RegClassID:
2527 case AMDGPU::AReg_128_Align2RegClassID:
2528 case AMDGPU::AV_128RegClassID:
2529 case AMDGPU::AV_128_Align2RegClassID:
2531 case AMDGPU::SGPR_160RegClassID:
2532 case AMDGPU::SReg_160RegClassID:
2533 case AMDGPU::VReg_160RegClassID:
2534 case AMDGPU::AReg_160RegClassID:
2535 case AMDGPU::VReg_160_Align2RegClassID:
2536 case AMDGPU::AReg_160_Align2RegClassID:
2537 case AMDGPU::AV_160RegClassID:
2538 case AMDGPU::AV_160_Align2RegClassID:
2540 case AMDGPU::SGPR_192RegClassID:
2541 case AMDGPU::SReg_192RegClassID:
2542 case AMDGPU::VReg_192RegClassID:
2543 case AMDGPU::AReg_192RegClassID:
2544 case AMDGPU::VReg_192_Align2RegClassID:
2545 case AMDGPU::AReg_192_Align2RegClassID:
2546 case AMDGPU::AV_192RegClassID:
2547 case AMDGPU::AV_192_Align2RegClassID:
2549 case AMDGPU::SGPR_224RegClassID:
2550 case AMDGPU::SReg_224RegClassID:
2551 case AMDGPU::VReg_224RegClassID:
2552 case AMDGPU::AReg_224RegClassID:
2553 case AMDGPU::VReg_224_Align2RegClassID:
2554 case AMDGPU::AReg_224_Align2RegClassID:
2555 case AMDGPU::AV_224RegClassID:
2556 case AMDGPU::AV_224_Align2RegClassID:
2558 case AMDGPU::SGPR_256RegClassID:
2559 case AMDGPU::SReg_256RegClassID:
2560 case AMDGPU::VReg_256RegClassID:
2561 case AMDGPU::AReg_256RegClassID:
2562 case AMDGPU::VReg_256_Align2RegClassID:
2563 case AMDGPU::AReg_256_Align2RegClassID:
2564 case AMDGPU::AV_256RegClassID:
2565 case AMDGPU::AV_256_Align2RegClassID:
2567 case AMDGPU::SGPR_288RegClassID:
2568 case AMDGPU::SReg_288RegClassID:
2569 case AMDGPU::VReg_288RegClassID:
2570 case AMDGPU::AReg_288RegClassID:
2571 case AMDGPU::VReg_288_Align2RegClassID:
2572 case AMDGPU::AReg_288_Align2RegClassID:
2573 case AMDGPU::AV_288RegClassID:
2574 case AMDGPU::AV_288_Align2RegClassID:
2576 case AMDGPU::SGPR_320RegClassID:
2577 case AMDGPU::SReg_320RegClassID:
2578 case AMDGPU::VReg_320RegClassID:
2579 case AMDGPU::AReg_320RegClassID:
2580 case AMDGPU::VReg_320_Align2RegClassID:
2581 case AMDGPU::AReg_320_Align2RegClassID:
2582 case AMDGPU::AV_320RegClassID:
2583 case AMDGPU::AV_320_Align2RegClassID:
2585 case AMDGPU::SGPR_352RegClassID:
2586 case AMDGPU::SReg_352RegClassID:
2587 case AMDGPU::VReg_352RegClassID:
2588 case AMDGPU::AReg_352RegClassID:
2589 case AMDGPU::VReg_352_Align2RegClassID:
2590 case AMDGPU::AReg_352_Align2RegClassID:
2591 case AMDGPU::AV_352RegClassID:
2592 case AMDGPU::AV_352_Align2RegClassID:
2594 case AMDGPU::SGPR_384RegClassID:
2595 case AMDGPU::SReg_384RegClassID:
2596 case AMDGPU::VReg_384RegClassID:
2597 case AMDGPU::AReg_384RegClassID:
2598 case AMDGPU::VReg_384_Align2RegClassID:
2599 case AMDGPU::AReg_384_Align2RegClassID:
2600 case AMDGPU::AV_384RegClassID:
2601 case AMDGPU::AV_384_Align2RegClassID:
2603 case AMDGPU::SGPR_512RegClassID:
2604 case AMDGPU::SReg_512RegClassID:
2605 case AMDGPU::VReg_512RegClassID:
2606 case AMDGPU::AReg_512RegClassID:
2607 case AMDGPU::VReg_512_Align2RegClassID:
2608 case AMDGPU::AReg_512_Align2RegClassID:
2609 case AMDGPU::AV_512RegClassID:
2610 case AMDGPU::AV_512_Align2RegClassID:
2612 case AMDGPU::SGPR_1024RegClassID:
2613 case AMDGPU::SReg_1024RegClassID:
2614 case AMDGPU::VReg_1024RegClassID:
2615 case AMDGPU::AReg_1024RegClassID:
2616 case AMDGPU::VReg_1024_Align2RegClassID:
2617 case AMDGPU::AReg_1024_Align2RegClassID:
2618 case AMDGPU::AV_1024RegClassID:
2619 case AMDGPU::AV_1024_Align2RegClassID:
2633 unsigned RCID =
Desc.operands()[OpNo].RegClass;
2642 return (Val == llvm::bit_cast<uint64_t>(0.0)) ||
2643 (Val == llvm::bit_cast<uint64_t>(1.0)) ||
2644 (Val == llvm::bit_cast<uint64_t>(-1.0)) ||
2645 (Val == llvm::bit_cast<uint64_t>(0.5)) ||
2646 (Val == llvm::bit_cast<uint64_t>(-0.5)) ||
2647 (Val == llvm::bit_cast<uint64_t>(2.0)) ||
2648 (Val == llvm::bit_cast<uint64_t>(-2.0)) ||
2649 (Val == llvm::bit_cast<uint64_t>(4.0)) ||
2650 (Val == llvm::bit_cast<uint64_t>(-4.0)) ||
2651 (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
2668 return (Val == llvm::bit_cast<uint32_t>(0.0f)) ||
2669 (Val == llvm::bit_cast<uint32_t>(1.0f)) ||
2670 (Val == llvm::bit_cast<uint32_t>(-1.0f)) ||
2671 (Val == llvm::bit_cast<uint32_t>(0.5f)) ||
2672 (Val == llvm::bit_cast<uint32_t>(-0.5f)) ||
2673 (Val == llvm::bit_cast<uint32_t>(2.0f)) ||
2674 (Val == llvm::bit_cast<uint32_t>(-2.0f)) ||
2675 (Val == llvm::bit_cast<uint32_t>(4.0f)) ||
2676 (Val == llvm::bit_cast<uint32_t>(-4.0f)) ||
2677 (Val == 0x3e22f983 && HasInv2Pi);
2686 return Val == 0x3F00 ||
2707 return Val == 0x3C00 ||
2734 return 192 + std::abs(
Signed);
2739 case 0x3800:
return 240;
2740 case 0xB800:
return 241;
2741 case 0x3C00:
return 242;
2742 case 0xBC00:
return 243;
2743 case 0x4000:
return 244;
2744 case 0xC000:
return 245;
2745 case 0x4400:
return 246;
2746 case 0xC400:
return 247;
2747 case 0x3118:
return 248;
2754 case 0x3F000000:
return 240;
2755 case 0xBF000000:
return 241;
2756 case 0x3F800000:
return 242;
2757 case 0xBF800000:
return 243;
2758 case 0x40000000:
return 244;
2759 case 0xC0000000:
return 245;
2760 case 0x40800000:
return 246;
2761 case 0xC0800000:
return 247;
2762 case 0x3E22F983:
return 248;
2785 return 192 + std::abs(
Signed);
2789 case 0x3F00:
return 240;
2790 case 0xBF00:
return 241;
2791 case 0x3F80:
return 242;
2792 case 0xBF80:
return 243;
2793 case 0x4000:
return 244;
2794 case 0xC000:
return 245;
2795 case 0x4080:
return 246;
2796 case 0xC080:
return 247;
2797 case 0x3E22:
return 248;
2802 return std::nullopt;
2848 return !(Val & 0xffffffffu);
2850 return isUInt<32>(Val) || isInt<32>(Val);
2874 return A->hasAttribute(Attribute::InReg) ||
2875 A->hasAttribute(Attribute::ByVal);
2878 return A->hasAttribute(Attribute::InReg);
2917 int64_t EncodedOffset) {
2919 return isUInt<23>(EncodedOffset);
2922 : isUInt<8>(EncodedOffset);
2926 int64_t EncodedOffset,
2929 return isInt<24>(EncodedOffset);
2933 isInt<21>(EncodedOffset);
2937 return (ByteOffset & 3) == 0;
2946 return ByteOffset >> 2;
2950 int64_t ByteOffset,
bool IsBuffer) {
2952 return isInt<24>(ByteOffset) ? std::optional<int64_t>(ByteOffset)
2958 return isInt<20>(ByteOffset) ? std::optional<int64_t>(ByteOffset)
2963 return std::nullopt;
2967 ? std::optional<int64_t>(EncodedOffset)
2972 int64_t ByteOffset) {
2974 return std::nullopt;
2977 return isUInt<32>(EncodedOffset) ? std::optional<int64_t>(EncodedOffset)
2992struct SourceOfDivergence {
2995const SourceOfDivergence *lookupSourceOfDivergence(
unsigned Intr);
3002#define GET_SourcesOfDivergence_IMPL
3003#define GET_UniformIntrinsics_IMPL
3004#define GET_Gfx9BufferFormat_IMPL
3005#define GET_Gfx10BufferFormat_IMPL
3006#define GET_Gfx11PlusBufferFormat_IMPL
3007#include "AMDGPUGenSearchableTables.inc"
3012 return lookupSourceOfDivergence(IntrID);
3016 return lookupAlwaysUniform(IntrID);
3020 uint8_t NumComponents,
3024 ? getGfx11PlusBufferFormatInfo(BitsPerComp, NumComponents,
3026 :
isGFX10(STI) ? getGfx10BufferFormatInfo(BitsPerComp,
3027 NumComponents, NumFormat)
3028 : getGfx9BufferFormatInfo(BitsPerComp,
3029 NumComponents, NumFormat);
3036 : getGfx9BufferFormatInfo(
Format);
3040 for (
auto OpName : { OpName::vdst, OpName::src0, OpName::src1,
3046 if (OpDesc.
operands()[
Idx].RegClass == AMDGPU::VReg_64RegClassID ||
3047 OpDesc.
operands()[
Idx].RegClass == AMDGPU::VReg_64_Align2RegClassID)
3069 OS <<
"Unsupported";
unsigned const MachineRegisterInfo * MRI
static llvm::cl::opt< unsigned > DefaultAMDHSACodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden, llvm::cl::init(llvm::AMDGPU::AMDHSA_COV5), llvm::cl::desc("Set default AMDHSA Code Object Version (module flag " "or asm directive still take priority if present)"))
Provides AMDGPU specific target descriptions.
AMDHSA kernel descriptor definitions.
#define AMDHSA_BITS_SET(DST, MSK, VAL)
@ AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32
This file contains the simple types necessary to represent the attributes associated with functions a...
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > & Cond
#define S_00B848_MEM_ORDERED(x)
#define S_00B848_WGP_MODE(x)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isSramEccSupported() const
void setTargetIDFromFeaturesString(StringRef FS)
TargetIDSetting getXnackSetting() const
AMDGPUTargetID(const MCSubtargetInfo &STI)
bool isXnackSupported() const
void setTargetIDFromTargetIDStream(StringRef TargetID)
std::string toString() const
TargetIDSetting getSramEccSetting() const
unsigned getIndexInParsedOperands(unsigned CompOprIdx) const
unsigned getIndexOfDstInParsedOperands() const
unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const
unsigned getCompParsedSrcOperandsNum() const
std::optional< unsigned > getInvalidCompOperandIndex(std::function< unsigned(unsigned, unsigned)> GetRegIdx, bool SkipSrc=false) const
std::array< unsigned, Component::MAX_OPR_NUM > RegIndices
This class represents an incoming formal argument to a Function.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
CallingConv::ID getCallingConv() const
bool paramHasAttr(unsigned ArgNo, Attribute::AttrKind Kind) const
Determine whether the argument or parameter has the given attribute.
This class represents an Operation in the Expression.
Encoding
Size and signedness of expression operations' operands.
constexpr bool test(unsigned I) const
unsigned getAddressSpace() const
This is an important class for using LLVM in a threaded context.
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
unsigned getOpcode() const
Return the opcode number for this descriptor.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
MCRegisterClass - Base class of TargetRegisterClass.
unsigned getID() const
getID() - Return the register class ID number.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
const FeatureBitset & getFeatureBits() const
A Module instance is used to store all the information related to an LLVM module.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
std::string str() const
str - Get the contents as an std::string.
constexpr bool empty() const
empty - Check if the string is empty.
constexpr size_t size() const
size - Get the string size.
bool ends_with(StringRef Suffix) const
Check if this string ends with the given Suffix.
Manages the enabling and disabling of subtarget specific features.
const std::vector< std::string > & getFeatures() const
Returns the vector of individual subtarget features.
Triple - Helper class for working with autoconf configuration names.
OSType getOS() const
Get the parsed operating system type of this triple.
ArchType getArch() const
Get the parsed architecture type of this triple.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an std::string.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
@ LOCAL_ADDRESS
Address space for local memory.
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst)
unsigned decodeFieldSaSdst(unsigned Encoded)
unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc)
int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst)
const CustomOperandVal DepCtrInfo[]
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
unsigned decodeFieldVaVdst(unsigned Encoded)
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI)
unsigned decodeFieldVmVsrc(unsigned Encoded)
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
static constexpr ExpTgt ExpTgtInfo[]
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
unsigned getTgtId(const StringRef Name)
@ ET_DUAL_SRC_BLEND_MAX_IDX
constexpr uint32_t VersionMajor
HSA metadata major version.
const CustomOperand< const MCSubtargetInfo & > Opr[]
int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI)
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI)
@ COMPLETION_ACTION_OFFSET
@ MULTIGRID_SYNC_ARG_OFFSET
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
static TargetIDSetting getTargetIDSettingFromFeatureString(StringRef FeatureString)
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI, unsigned NumVGPRs)
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEncodedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
static unsigned getGranulatedNumRegisterBlocks(unsigned NumRegs, unsigned Granule)
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI)
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
unsigned getAllocatedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI)
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI)
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
int64_t getMsgOpId(int64_t MsgId, const StringRef Name)
const char *const OpGsSymbolic[OP_GS_LAST_]
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
const char *const OpSysSymbolic[OP_SYS_LAST_]
static uint64_t getMsgIdMask(const MCSubtargetInfo &STI)
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
const CustomOperand< const MCSubtargetInfo & > Msg[]
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
constexpr unsigned VOPD_VGPR_BANK_MASKS[]
constexpr unsigned COMPONENTS_NUM
bool isGCN3Encoding(const MCSubtargetInfo &STI)
bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi)
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
bool isGFX10_GFX11(const MCSubtargetInfo &STI)
bool isInlinableLiteralV216(uint32_t Literal, uint8_t OpType)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
bool isInlinableLiteralFP16(int16_t Literal, bool HasInv2Pi)
SmallVector< unsigned > getIntegerVecAttribute(const Function &F, StringRef Name, unsigned Size)
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
static unsigned encodeStorecnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Storecnt)
static bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST)
static bool hasSMEMByteOffset(const MCSubtargetInfo &ST)
bool isVOPCAsmOnly(unsigned Opc)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool getMTBUFHasSrsrc(unsigned Opc)
std::optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
static bool isSymbolicCustomOperandEncoding(const CustomOperandVal *Opr, int Size, unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
bool isGFX10Before1030(const MCSubtargetInfo &STI)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc)
const int OPR_ID_UNSUPPORTED
bool shouldEmitConstantsToTextSection(const Triple &TT)
bool isInlinableLiteralV2I16(uint32_t Literal)
int getMTBUFElements(unsigned Opc)
static int encodeCustomOperandVal(const CustomOperandVal &Op, int64_t InputVal)
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
bool isGFX10(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
bool isInlinableLiteralV2BF16(uint32_t Literal)
unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI)
std::optional< unsigned > getInlineEncodingV216(bool IsFloat, uint32_t Literal)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool hasA16(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
bool isGFX12Plus(const MCSubtargetInfo &STI)
unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler)
CanBeVOPD getCanBeVOPD(unsigned Opc)
static int getOprIdx(std::function< bool(const CustomOperand< T > &)> Test, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context)
bool hasPackedD16(const MCSubtargetInfo &STI)
unsigned getStorecntBitMask(const IsaVersion &Version)
unsigned getLdsDwGranularity(const MCSubtargetInfo &ST)
bool isGFX940(const MCSubtargetInfo &STI)
bool isEntryFunctionCC(CallingConv::ID CC)
bool isInlinableLiteralV2F16(uint32_t Literal)
bool isHsaAbi(const MCSubtargetInfo &STI)
bool isGFX11(const MCSubtargetInfo &STI)
const int OPR_VAL_INVALID
bool getSMEMIsBuffer(unsigned Opc)
bool isGFX10_3_GFX11(const MCSubtargetInfo &STI)
bool isGroupSegment(const GlobalValue *GV)
IsaVersion getIsaVersion(StringRef GPU)
bool getMTBUFHasSoffset(unsigned Opc)
bool hasXNACK(const MCSubtargetInfo &STI)
bool isValid32BitLiteral(uint64_t Val, bool IsFP64)
static unsigned getCombinedCountBitMask(const IsaVersion &Version, bool IsStore)
unsigned getVOPDOpcode(unsigned Opc)
bool isDPALU_DPP(const MCInstrDesc &OpDesc)
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
bool isVOPC64DPP(unsigned Opc)
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
bool isCompute(CallingConv::ID cc)
bool getMAIIsGFX940XDL(unsigned Opc)
bool isSI(const MCSubtargetInfo &STI)
unsigned getDefaultAMDHSACodeObjectVersion()
bool isReadOnlySegment(const GlobalValue *GV)
bool isArgPassedInSGPR(const Argument *A)
bool isIntrinsicAlwaysUniform(unsigned IntrID)
int getMUBUFBaseOpcode(unsigned Opc)
unsigned getAMDHSACodeObjectVersion(const Module &M)
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
unsigned getWaitcntBitMask(const IsaVersion &Version)
bool getVOP3IsSingle(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
bool getVOP1IsSingle(unsigned Opc)
static bool isDwordAligned(uint64_t ByteOffset)
unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST)
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this a KImm operand?
bool getHasColorExport(const Function &F)
int getMTBUFBaseOpcode(unsigned Opc)
bool isChainCC(CallingConv::ID CC)
bool isGFX90A(const MCSubtargetInfo &STI)
unsigned getSamplecntBitMask(const IsaVersion &Version)
unsigned getDefaultQueueImplicitArgPosition(unsigned CodeObjectVersion)
bool hasSRAMECC(const MCSubtargetInfo &STI)
bool getHasDepthExport(const Function &F)
static bool isValidOpr(int Idx, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context)
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
bool getMUBUFHasVAddr(unsigned Opc)
int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily)
bool isTrue16Inst(unsigned Opc)
bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc)
std::pair< unsigned, unsigned > getVOPDComponents(unsigned VOPDOpcode)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
bool isGFX12(const MCSubtargetInfo &STI)
unsigned getInitialPSInputAddr(const Function &F)
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this an AMDGPU specific source operand? These include registers, inline constants,...
unsigned getKmcntBitMask(const IsaVersion &Version)
unsigned getVmcntBitMask(const IsaVersion &Version)
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
bool hasMAIInsts(const MCSubtargetInfo &STI)
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
bool isKernelCC(const Function *Func)
bool isGenericAtomic(unsigned Opc)
Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt)
bool isGFX8Plus(const MCSubtargetInfo &STI)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
std::optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
bool isHi(unsigned Reg, const MCRegisterInfo &MRI)
unsigned getBvhcntBitMask(const IsaVersion &Version)
bool hasMIMG_R128(const MCSubtargetInfo &STI)
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool getMUBUFHasSoffset(unsigned Opc)
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
std::optional< unsigned > getInlineEncodingV2F16(uint32_t Literal)
bool isInlineValue(unsigned Reg)
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
bool isShader(CallingConv::ID cc)
unsigned getHostcallImplicitArgPosition(unsigned CodeObjectVersion)
static unsigned getDefaultCustomOperandEncoding(const CustomOperandVal *Opr, int Size, const MCSubtargetInfo &STI)
static unsigned encodeLoadcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Loadcnt)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
static bool decodeCustomOperand(const CustomOperandVal *Opr, int Size, unsigned Code, int &Idx, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
bool isGlobalSegment(const GlobalValue *GV)
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
@ OPERAND_REG_INLINE_C_LAST
@ OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_V2BF16
@ OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_FIRST
@ OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_V2BF16
@ OPERAND_REG_INLINE_C_FIRST
@ OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_AC_LAST
@ OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
bool hasGDS(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
bool isGFX9Plus(const MCSubtargetInfo &STI)
bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI)
const int OPR_ID_DUPLICATE
bool isVOPD(unsigned Opc)
VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc)
Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt)
std::optional< unsigned > getInlineEncodingV2I16(uint32_t Literal)
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
static unsigned encodeStorecntDscnt(const IsaVersion &Version, unsigned Storecnt, unsigned Dscnt)
int getMCOpcode(uint16_t Opcode, unsigned Gen)
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
bool isVI(const MCSubtargetInfo &STI)
bool getMUBUFIsBufferInv(unsigned Opc)
std::optional< unsigned > getInlineEncodingV2BF16(uint32_t Literal)
static int encodeCustomOperand(const CustomOperandVal *Opr, int Size, const StringRef Name, int64_t InputVal, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
bool isCI(const MCSubtargetInfo &STI)
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI)
bool getVOP2IsSingle(unsigned Opc)
bool getMAIIsDGEMM(unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
unsigned getCompletionActionImplicitArgPosition(unsigned CodeObjectVersion)
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
bool isModuleEntryFunctionCC(CallingConv::ID CC)
bool isNotGFX12Plus(const MCSubtargetInfo &STI)
bool getMTBUFHasVAddr(unsigned Opc)
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
std::pair< unsigned, unsigned > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
unsigned getLoadcntBitMask(const IsaVersion &Version)
bool isInlinableLiteralI16(int32_t Literal, bool HasInv2Pi)
bool hasVOPD(const MCSubtargetInfo &STI)
static unsigned encodeDscnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Dscnt)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI)
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
int getMUBUFElements(unsigned Opc)
static unsigned encodeLoadcntDscnt(const IsaVersion &Version, unsigned Loadcnt, unsigned Dscnt)
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
bool isGraphics(CallingConv::ID cc)
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc)
bool isPermlane16(unsigned Opc)
bool getMUBUFHasSrsrc(unsigned Opc)
unsigned getDscntBitMask(const IsaVersion &Version)
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ AMDGPU_CS
Used for Mesa/AMDPAL compute shaders.
@ AMDGPU_VS
Used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (vertex shader if tess...
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
@ AMDGPU_Gfx
Used for AMD graphics targets.
@ AMDGPU_CS_ChainPreserve
Used on AMDGPUs to give the middle-end more control over argument placement.
@ AMDGPU_HS
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
@ AMDGPU_CS_Chain
Used on AMDGPUs to give the middle-end more control over argument placement.
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
@ SPIR_KERNEL
Used for SPIR kernel functions.
@ AMDGPU_ES
Used for AMDPAL shader stage before geometry shader if geometry is in use.
@ AMDGPU_LS
Used for AMDPAL vertex shader if tessellation is in use.
@ ELFABIVERSION_AMDGPU_HSA_V4
@ ELFABIVERSION_AMDGPU_HSA_V5
@ ELFABIVERSION_AMDGPU_HSA_V6
@ FLOAT_DENORM_MODE_FLUSH_NONE
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
DWARFExpression::Operation Op
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
@ AlwaysUniform
The result values are always uniform.
@ Default
The result values are uniform if and only if all operands are uniform.
AMD Kernel Code Object (amd_kernel_code_t).
Instruction set architecture version.
Represents the counter values to wait for in an s_waitcnt instruction.
Description of the encoding of one expression Op.
uint32_t compute_pgm_rsrc1
uint32_t compute_pgm_rsrc2
uint16_t kernel_code_properties
uint32_t compute_pgm_rsrc3