LLVM  13.0.0git
AMDGPUBaseInfo.cpp
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1 //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AMDGPUBaseInfo.h"
10 #include "AMDGPU.h"
11 #include "AMDGPUAsmUtils.h"
12 #include "AMDKernelCodeT.h"
13 #include "GCNSubtarget.h"
15 #include "llvm/BinaryFormat/ELF.h"
16 #include "llvm/IR/Attributes.h"
17 #include "llvm/IR/Function.h"
18 #include "llvm/IR/GlobalValue.h"
19 #include "llvm/IR/IntrinsicsAMDGPU.h"
20 #include "llvm/IR/IntrinsicsR600.h"
21 #include "llvm/IR/LLVMContext.h"
26 
27 #define GET_INSTRINFO_NAMED_OPS
28 #define GET_INSTRMAP_INFO
29 #include "AMDGPUGenInstrInfo.inc"
30 
32  "amdhsa-code-object-version", llvm::cl::Hidden,
33  llvm::cl::desc("AMDHSA Code Object Version"), llvm::cl::init(4),
35 
36 namespace {
37 
38 /// \returns Bit mask for given bit \p Shift and bit \p Width.
39 unsigned getBitMask(unsigned Shift, unsigned Width) {
40  return ((1 << Width) - 1) << Shift;
41 }
42 
43 /// Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
44 ///
45 /// \returns Packed \p Dst.
46 unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
47  Dst &= ~(1 << Shift) & ~getBitMask(Shift, Width);
48  Dst |= (Src << Shift) & getBitMask(Shift, Width);
49  return Dst;
50 }
51 
52 /// Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
53 ///
54 /// \returns Unpacked bits.
55 unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
56  return (Src & getBitMask(Shift, Width)) >> Shift;
57 }
58 
59 /// \returns Vmcnt bit shift (lower bits).
60 unsigned getVmcntBitShiftLo() { return 0; }
61 
62 /// \returns Vmcnt bit width (lower bits).
63 unsigned getVmcntBitWidthLo() { return 4; }
64 
65 /// \returns Expcnt bit shift.
66 unsigned getExpcntBitShift() { return 4; }
67 
68 /// \returns Expcnt bit width.
69 unsigned getExpcntBitWidth() { return 3; }
70 
71 /// \returns Lgkmcnt bit shift.
72 unsigned getLgkmcntBitShift() { return 8; }
73 
74 /// \returns Lgkmcnt bit width.
75 unsigned getLgkmcntBitWidth(unsigned VersionMajor) {
76  return (VersionMajor >= 10) ? 6 : 4;
77 }
78 
79 /// \returns Vmcnt bit shift (higher bits).
80 unsigned getVmcntBitShiftHi() { return 14; }
81 
82 /// \returns Vmcnt bit width (higher bits).
83 unsigned getVmcntBitWidthHi() { return 2; }
84 
85 } // end namespace anonymous
86 
87 namespace llvm {
88 
89 namespace AMDGPU {
90 
92  if (STI && STI->getTargetTriple().getOS() != Triple::AMDHSA)
93  return None;
94 
95  switch (AmdhsaCodeObjectVersion) {
96  case 2:
98  case 3:
100  case 4:
102  default:
103  report_fatal_error(Twine("Unsupported AMDHSA Code Object Version ") +
105  }
106 }
107 
109  if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI))
110  return *HsaAbiVer == ELF::ELFABIVERSION_AMDGPU_HSA_V2;
111  return false;
112 }
113 
115  if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI))
116  return *HsaAbiVer == ELF::ELFABIVERSION_AMDGPU_HSA_V3;
117  return false;
118 }
119 
121  if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI))
122  return *HsaAbiVer == ELF::ELFABIVERSION_AMDGPU_HSA_V4;
123  return false;
124 }
125 
127  return isHsaAbiVersion3(STI) || isHsaAbiVersion4(STI);
128 }
129 
130 #define GET_MIMGBaseOpcodesTable_IMPL
131 #define GET_MIMGDimInfoTable_IMPL
132 #define GET_MIMGInfoTable_IMPL
133 #define GET_MIMGLZMappingTable_IMPL
134 #define GET_MIMGMIPMappingTable_IMPL
135 #define GET_MIMGG16MappingTable_IMPL
136 #include "AMDGPUGenSearchableTables.inc"
137 
138 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
139  unsigned VDataDwords, unsigned VAddrDwords) {
140  const MIMGInfo *Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding,
141  VDataDwords, VAddrDwords);
142  return Info ? Info->Opcode : -1;
143 }
144 
145 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc) {
146  const MIMGInfo *Info = getMIMGInfo(Opc);
147  return Info ? getMIMGBaseOpcodeInfo(Info->BaseOpcode) : nullptr;
148 }
149 
150 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels) {
151  const MIMGInfo *OrigInfo = getMIMGInfo(Opc);
152  const MIMGInfo *NewInfo =
153  getMIMGOpcodeHelper(OrigInfo->BaseOpcode, OrigInfo->MIMGEncoding,
154  NewChannels, OrigInfo->VAddrDwords);
155  return NewInfo ? NewInfo->Opcode : -1;
156 }
157 
158 struct MUBUFInfo {
161  uint8_t elements;
162  bool has_vaddr;
163  bool has_srsrc;
165 };
166 
167 struct MTBUFInfo {
170  uint8_t elements;
171  bool has_vaddr;
172  bool has_srsrc;
174 };
175 
176 struct SMInfo {
178  bool IsBuffer;
179 };
180 
181 struct VOPInfo {
183  bool IsSingle;
184 };
185 
186 #define GET_MTBUFInfoTable_DECL
187 #define GET_MTBUFInfoTable_IMPL
188 #define GET_MUBUFInfoTable_DECL
189 #define GET_MUBUFInfoTable_IMPL
190 #define GET_SMInfoTable_DECL
191 #define GET_SMInfoTable_IMPL
192 #define GET_VOP1InfoTable_DECL
193 #define GET_VOP1InfoTable_IMPL
194 #define GET_VOP2InfoTable_DECL
195 #define GET_VOP2InfoTable_IMPL
196 #define GET_VOP3InfoTable_DECL
197 #define GET_VOP3InfoTable_IMPL
198 #include "AMDGPUGenSearchableTables.inc"
199 
200 int getMTBUFBaseOpcode(unsigned Opc) {
201  const MTBUFInfo *Info = getMTBUFInfoFromOpcode(Opc);
202  return Info ? Info->BaseOpcode : -1;
203 }
204 
205 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements) {
206  const MTBUFInfo *Info = getMTBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
207  return Info ? Info->Opcode : -1;
208 }
209 
210 int getMTBUFElements(unsigned Opc) {
211  const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
212  return Info ? Info->elements : 0;
213 }
214 
215 bool getMTBUFHasVAddr(unsigned Opc) {
216  const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
217  return Info ? Info->has_vaddr : false;
218 }
219 
220 bool getMTBUFHasSrsrc(unsigned Opc) {
221  const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
222  return Info ? Info->has_srsrc : false;
223 }
224 
225 bool getMTBUFHasSoffset(unsigned Opc) {
226  const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
227  return Info ? Info->has_soffset : false;
228 }
229 
230 int getMUBUFBaseOpcode(unsigned Opc) {
231  const MUBUFInfo *Info = getMUBUFInfoFromOpcode(Opc);
232  return Info ? Info->BaseOpcode : -1;
233 }
234 
235 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements) {
236  const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
237  return Info ? Info->Opcode : -1;
238 }
239 
240 int getMUBUFElements(unsigned Opc) {
241  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
242  return Info ? Info->elements : 0;
243 }
244 
245 bool getMUBUFHasVAddr(unsigned Opc) {
246  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
247  return Info ? Info->has_vaddr : false;
248 }
249 
250 bool getMUBUFHasSrsrc(unsigned Opc) {
251  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
252  return Info ? Info->has_srsrc : false;
253 }
254 
255 bool getMUBUFHasSoffset(unsigned Opc) {
256  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
257  return Info ? Info->has_soffset : false;
258 }
259 
260 bool getSMEMIsBuffer(unsigned Opc) {
261  const SMInfo *Info = getSMEMOpcodeHelper(Opc);
262  return Info ? Info->IsBuffer : false;
263 }
264 
265 bool getVOP1IsSingle(unsigned Opc) {
266  const VOPInfo *Info = getVOP1OpcodeHelper(Opc);
267  return Info ? Info->IsSingle : false;
268 }
269 
270 bool getVOP2IsSingle(unsigned Opc) {
271  const VOPInfo *Info = getVOP2OpcodeHelper(Opc);
272  return Info ? Info->IsSingle : false;
273 }
274 
275 bool getVOP3IsSingle(unsigned Opc) {
276  const VOPInfo *Info = getVOP3OpcodeHelper(Opc);
277  return Info ? Info->IsSingle : false;
278 }
279 
280 // Wrapper for Tablegen'd function. enum Subtarget is not defined in any
281 // header files, so we need to wrap it in a function that takes unsigned
282 // instead.
283 int getMCOpcode(uint16_t Opcode, unsigned Gen) {
284  return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
285 }
286 
287 namespace IsaInfo {
288 
290  : STI(STI), XnackSetting(TargetIDSetting::Any),
291  SramEccSetting(TargetIDSetting::Any) {
292  if (!STI.getFeatureBits().test(FeatureSupportsXNACK))
293  XnackSetting = TargetIDSetting::Unsupported;
294  if (!STI.getFeatureBits().test(FeatureSupportsSRAMECC))
295  SramEccSetting = TargetIDSetting::Unsupported;
296 }
297 
299  // Check if xnack or sramecc is explicitly enabled or disabled. In the
300  // absence of the target features we assume we must generate code that can run
301  // in any environment.
302  SubtargetFeatures Features(FS);
303  Optional<bool> XnackRequested;
304  Optional<bool> SramEccRequested;
305 
306  for (const std::string &Feature : Features.getFeatures()) {
307  if (Feature == "+xnack")
308  XnackRequested = true;
309  else if (Feature == "-xnack")
310  XnackRequested = false;
311  else if (Feature == "+sramecc")
312  SramEccRequested = true;
313  else if (Feature == "-sramecc")
314  SramEccRequested = false;
315  }
316 
317  bool XnackSupported = isXnackSupported();
318  bool SramEccSupported = isSramEccSupported();
319 
320  if (XnackRequested) {
321  if (XnackSupported) {
322  XnackSetting =
323  *XnackRequested ? TargetIDSetting::On : TargetIDSetting::Off;
324  } else {
325  // If a specific xnack setting was requested and this GPU does not support
326  // xnack emit a warning. Setting will remain set to "Unsupported".
327  if (*XnackRequested) {
328  errs() << "warning: xnack 'On' was requested for a processor that does "
329  "not support it!\n";
330  } else {
331  errs() << "warning: xnack 'Off' was requested for a processor that "
332  "does not support it!\n";
333  }
334  }
335  }
336 
337  if (SramEccRequested) {
338  if (SramEccSupported) {
339  SramEccSetting =
340  *SramEccRequested ? TargetIDSetting::On : TargetIDSetting::Off;
341  } else {
342  // If a specific sramecc setting was requested and this GPU does not
343  // support sramecc emit a warning. Setting will remain set to
344  // "Unsupported".
345  if (*SramEccRequested) {
346  errs() << "warning: sramecc 'On' was requested for a processor that "
347  "does not support it!\n";
348  } else {
349  errs() << "warning: sramecc 'Off' was requested for a processor that "
350  "does not support it!\n";
351  }
352  }
353  }
354 }
355 
356 static TargetIDSetting
358  if (FeatureString.endswith("-"))
359  return TargetIDSetting::Off;
360  if (FeatureString.endswith("+"))
361  return TargetIDSetting::On;
362 
363  llvm_unreachable("Malformed feature string");
364 }
365 
367  SmallVector<StringRef, 3> TargetIDSplit;
368  TargetID.split(TargetIDSplit, ':');
369 
370  for (const auto &FeatureString : TargetIDSplit) {
371  if (FeatureString.startswith("xnack"))
372  XnackSetting = getTargetIDSettingFromFeatureString(FeatureString);
373  if (FeatureString.startswith("sramecc"))
374  SramEccSetting = getTargetIDSettingFromFeatureString(FeatureString);
375  }
376 }
377 
378 std::string AMDGPUTargetID::toString() const {
379  std::string StringRep = "";
380  raw_string_ostream StreamRep(StringRep);
381 
382  auto TargetTriple = STI.getTargetTriple();
383  auto Version = getIsaVersion(STI.getCPU());
384 
385  StreamRep << TargetTriple.getArchName() << '-'
386  << TargetTriple.getVendorName() << '-'
387  << TargetTriple.getOSName() << '-'
388  << TargetTriple.getEnvironmentName() << '-';
389 
390  std::string Processor = "";
391  // TODO: Following else statement is present here because we used various
392  // alias names for GPUs up until GFX9 (e.g. 'fiji' is same as 'gfx803').
393  // Remove once all aliases are removed from GCNProcessors.td.
394  if (Version.Major >= 9)
395  Processor = STI.getCPU().str();
396  else
397  Processor = (Twine("gfx") + Twine(Version.Major) + Twine(Version.Minor) +
398  Twine(Version.Stepping))
399  .str();
400 
401  std::string Features = "";
402  if (Optional<uint8_t> HsaAbiVersion = getHsaAbiVersion(&STI)) {
403  switch (*HsaAbiVersion) {
405  // Code object V2 only supported specific processors and had fixed
406  // settings for the XNACK.
407  if (Processor == "gfx600") {
408  } else if (Processor == "gfx601") {
409  } else if (Processor == "gfx602") {
410  } else if (Processor == "gfx700") {
411  } else if (Processor == "gfx701") {
412  } else if (Processor == "gfx702") {
413  } else if (Processor == "gfx703") {
414  } else if (Processor == "gfx704") {
415  } else if (Processor == "gfx705") {
416  } else if (Processor == "gfx801") {
417  if (!isXnackOnOrAny())
419  "AMD GPU code object V2 does not support processor " + Processor +
420  " without XNACK");
421  } else if (Processor == "gfx802") {
422  } else if (Processor == "gfx803") {
423  } else if (Processor == "gfx805") {
424  } else if (Processor == "gfx810") {
425  if (!isXnackOnOrAny())
427  "AMD GPU code object V2 does not support processor " + Processor +
428  " without XNACK");
429  } else if (Processor == "gfx900") {
430  if (isXnackOnOrAny())
431  Processor = "gfx901";
432  } else if (Processor == "gfx902") {
433  if (isXnackOnOrAny())
434  Processor = "gfx903";
435  } else if (Processor == "gfx904") {
436  if (isXnackOnOrAny())
437  Processor = "gfx905";
438  } else if (Processor == "gfx906") {
439  if (isXnackOnOrAny())
440  Processor = "gfx907";
441  } else if (Processor == "gfx90c") {
442  if (isXnackOnOrAny())
444  "AMD GPU code object V2 does not support processor " + Processor +
445  " with XNACK being ON or ANY");
446  } else {
448  "AMD GPU code object V2 does not support processor " + Processor);
449  }
450  break;
452  // xnack.
453  if (isXnackOnOrAny())
454  Features += "+xnack";
455  // In code object v2 and v3, "sramecc" feature was spelled with a
456  // hyphen ("sram-ecc").
457  if (isSramEccOnOrAny())
458  Features += "+sram-ecc";
459  break;
461  // sramecc.
463  Features += ":sramecc-";
465  Features += ":sramecc+";
466  // xnack.
468  Features += ":xnack-";
469  else if (getXnackSetting() == TargetIDSetting::On)
470  Features += ":xnack+";
471  break;
472  default:
473  break;
474  }
475  }
476 
477  StreamRep << Processor << Features;
478 
479  StreamRep.flush();
480  return StringRep;
481 }
482 
483 unsigned getWavefrontSize(const MCSubtargetInfo *STI) {
484  if (STI->getFeatureBits().test(FeatureWavefrontSize16))
485  return 16;
486  if (STI->getFeatureBits().test(FeatureWavefrontSize32))
487  return 32;
488 
489  return 64;
490 }
491 
492 unsigned getLocalMemorySize(const MCSubtargetInfo *STI) {
493  if (STI->getFeatureBits().test(FeatureLocalMemorySize32768))
494  return 32768;
495  if (STI->getFeatureBits().test(FeatureLocalMemorySize65536))
496  return 65536;
497 
498  return 0;
499 }
500 
501 unsigned getEUsPerCU(const MCSubtargetInfo *STI) {
502  // "Per CU" really means "per whatever functional block the waves of a
503  // workgroup must share". For gfx10 in CU mode this is the CU, which contains
504  // two SIMDs.
505  if (isGFX10Plus(*STI) && STI->getFeatureBits().test(FeatureCuMode))
506  return 2;
507  // Pre-gfx10 a CU contains four SIMDs. For gfx10 in WGP mode the WGP contains
508  // two CUs, so a total of four SIMDs.
509  return 4;
510 }
511 
513  unsigned FlatWorkGroupSize) {
514  assert(FlatWorkGroupSize != 0);
515  if (STI->getTargetTriple().getArch() != Triple::amdgcn)
516  return 8;
517  unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize);
518  if (N == 1)
519  return 40;
520  N = 40 / N;
521  return std::min(N, 16u);
522 }
523 
524 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI) {
525  return 1;
526 }
527 
528 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI) {
529  // FIXME: Need to take scratch memory into account.
530  if (isGFX90A(*STI))
531  return 8;
532  if (!isGFX10Plus(*STI))
533  return 10;
534  return hasGFX10_3Insts(*STI) ? 16 : 20;
535 }
536 
538  unsigned FlatWorkGroupSize) {
539  return divideCeil(getWavesPerWorkGroup(STI, FlatWorkGroupSize),
540  getEUsPerCU(STI));
541 }
542 
544  return 1;
545 }
546 
548  // Some subtargets allow encoding 2048, but this isn't tested or supported.
549  return 1024;
550 }
551 
553  unsigned FlatWorkGroupSize) {
554  return divideCeil(FlatWorkGroupSize, getWavefrontSize(STI));
555 }
556 
557 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI) {
559  if (Version.Major >= 10)
560  return getAddressableNumSGPRs(STI);
561  if (Version.Major >= 8)
562  return 16;
563  return 8;
564 }
565 
567  return 8;
568 }
569 
570 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI) {
572  if (Version.Major >= 8)
573  return 800;
574  return 512;
575 }
576 
578  if (STI->getFeatureBits().test(FeatureSGPRInitBug))
580 
582  if (Version.Major >= 10)
583  return 106;
584  if (Version.Major >= 8)
585  return 102;
586  return 104;
587 }
588 
589 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
590  assert(WavesPerEU != 0);
591 
593  if (Version.Major >= 10)
594  return 0;
595 
596  if (WavesPerEU >= getMaxWavesPerEU(STI))
597  return 0;
598 
599  unsigned MinNumSGPRs = getTotalNumSGPRs(STI) / (WavesPerEU + 1);
600  if (STI->getFeatureBits().test(FeatureTrapHandler))
601  MinNumSGPRs -= std::min(MinNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
602  MinNumSGPRs = alignDown(MinNumSGPRs, getSGPRAllocGranule(STI)) + 1;
603  return std::min(MinNumSGPRs, getAddressableNumSGPRs(STI));
604 }
605 
606 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
607  bool Addressable) {
608  assert(WavesPerEU != 0);
609 
610  unsigned AddressableNumSGPRs = getAddressableNumSGPRs(STI);
612  if (Version.Major >= 10)
613  return Addressable ? AddressableNumSGPRs : 108;
614  if (Version.Major >= 8 && !Addressable)
615  AddressableNumSGPRs = 112;
616  unsigned MaxNumSGPRs = getTotalNumSGPRs(STI) / WavesPerEU;
617  if (STI->getFeatureBits().test(FeatureTrapHandler))
618  MaxNumSGPRs -= std::min(MaxNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
619  MaxNumSGPRs = alignDown(MaxNumSGPRs, getSGPRAllocGranule(STI));
620  return std::min(MaxNumSGPRs, AddressableNumSGPRs);
621 }
622 
623 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
624  bool FlatScrUsed, bool XNACKUsed) {
625  unsigned ExtraSGPRs = 0;
626  if (VCCUsed)
627  ExtraSGPRs = 2;
628 
630  if (Version.Major >= 10)
631  return ExtraSGPRs;
632 
633  if (Version.Major < 8) {
634  if (FlatScrUsed)
635  ExtraSGPRs = 4;
636  } else {
637  if (XNACKUsed)
638  ExtraSGPRs = 4;
639 
640  if (FlatScrUsed)
641  ExtraSGPRs = 6;
642  }
643 
644  return ExtraSGPRs;
645 }
646 
647 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
648  bool FlatScrUsed) {
649  return getNumExtraSGPRs(STI, VCCUsed, FlatScrUsed,
650  STI->getFeatureBits().test(AMDGPU::FeatureXNACK));
651 }
652 
653 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs) {
655  // SGPRBlocks is actual number of SGPR blocks minus 1.
656  return NumSGPRs / getSGPREncodingGranule(STI) - 1;
657 }
658 
660  Optional<bool> EnableWavefrontSize32) {
661  if (STI->getFeatureBits().test(FeatureGFX90AInsts))
662  return 8;
663 
664  bool IsWave32 = EnableWavefrontSize32 ?
665  *EnableWavefrontSize32 :
666  STI->getFeatureBits().test(FeatureWavefrontSize32);
667 
668  if (hasGFX10_3Insts(*STI))
669  return IsWave32 ? 16 : 8;
670 
671  return IsWave32 ? 8 : 4;
672 }
673 
675  Optional<bool> EnableWavefrontSize32) {
676  if (STI->getFeatureBits().test(FeatureGFX90AInsts))
677  return 8;
678 
679  bool IsWave32 = EnableWavefrontSize32 ?
680  *EnableWavefrontSize32 :
681  STI->getFeatureBits().test(FeatureWavefrontSize32);
682 
683  return IsWave32 ? 8 : 4;
684 }
685 
686 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {
687  if (STI->getFeatureBits().test(FeatureGFX90AInsts))
688  return 512;
689  if (!isGFX10Plus(*STI))
690  return 256;
691  return STI->getFeatureBits().test(FeatureWavefrontSize32) ? 1024 : 512;
692 }
693 
695  if (STI->getFeatureBits().test(FeatureGFX90AInsts))
696  return 512;
697  return 256;
698 }
699 
700 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
701  assert(WavesPerEU != 0);
702 
703  if (WavesPerEU >= getMaxWavesPerEU(STI))
704  return 0;
705  unsigned MinNumVGPRs =
706  alignDown(getTotalNumVGPRs(STI) / (WavesPerEU + 1),
707  getVGPRAllocGranule(STI)) + 1;
708  return std::min(MinNumVGPRs, getAddressableNumVGPRs(STI));
709 }
710 
711 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
712  assert(WavesPerEU != 0);
713 
714  unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(STI) / WavesPerEU,
715  getVGPRAllocGranule(STI));
716  unsigned AddressableNumVGPRs = getAddressableNumVGPRs(STI);
717  return std::min(MaxNumVGPRs, AddressableNumVGPRs);
718 }
719 
720 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs,
721  Optional<bool> EnableWavefrontSize32) {
723  getVGPREncodingGranule(STI, EnableWavefrontSize32));
724  // VGPRBlocks is actual number of VGPR blocks minus 1.
725  return NumVGPRs / getVGPREncodingGranule(STI, EnableWavefrontSize32) - 1;
726 }
727 
728 } // end namespace IsaInfo
729 
731  const MCSubtargetInfo *STI) {
733 
734  memset(&Header, 0, sizeof(Header));
735 
738  Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
739  Header.amd_machine_version_major = Version.Major;
740  Header.amd_machine_version_minor = Version.Minor;
741  Header.amd_machine_version_stepping = Version.Stepping;
742  Header.kernel_code_entry_byte_offset = sizeof(Header);
743  Header.wavefront_size = 6;
744 
745  // If the code object does not support indirect functions, then the value must
746  // be 0xffffffff.
747  Header.call_convention = -1;
748 
749  // These alignment values are specified in powers of two, so alignment =
750  // 2^n. The minimum alignment is 2^4 = 16.
751  Header.kernarg_segment_alignment = 4;
752  Header.group_segment_alignment = 4;
753  Header.private_segment_alignment = 4;
754 
755  if (Version.Major >= 10) {
756  if (STI->getFeatureBits().test(FeatureWavefrontSize32)) {
757  Header.wavefront_size = 5;
759  }
761  S_00B848_WGP_MODE(STI->getFeatureBits().test(FeatureCuMode) ? 0 : 1) |
763  }
764 }
765 
767  const MCSubtargetInfo *STI) {
769 
771  memset(&KD, 0, sizeof(KD));
772 
774  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64,
777  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, 1);
779  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE, 1);
781  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, 1);
782  if (Version.Major >= 10) {
784  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
785  STI->getFeatureBits().test(FeatureWavefrontSize32) ? 1 : 0);
787  amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE,
788  STI->getFeatureBits().test(FeatureCuMode) ? 0 : 1);
790  amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED, 1);
791  }
792  if (AMDGPU::isGFX90A(*STI)) {
794  amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT,
795  STI->getFeatureBits().test(FeatureTgSplit) ? 1 : 0);
796  }
797  return KD;
798 }
799 
800 bool isGroupSegment(const GlobalValue *GV) {
802 }
803 
804 bool isGlobalSegment(const GlobalValue *GV) {
806 }
807 
809  unsigned AS = GV->getAddressSpace();
810  return AS == AMDGPUAS::CONSTANT_ADDRESS ||
812 }
813 
815  return TT.getArch() == Triple::r600;
816 }
817 
818 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
819  Attribute A = F.getFnAttribute(Name);
820  int Result = Default;
821 
822  if (A.isStringAttribute()) {
823  StringRef Str = A.getValueAsString();
824  if (Str.getAsInteger(0, Result)) {
825  LLVMContext &Ctx = F.getContext();
826  Ctx.emitError("can't parse integer attribute " + Name);
827  }
828  }
829 
830  return Result;
831 }
832 
833 std::pair<int, int> getIntegerPairAttribute(const Function &F,
834  StringRef Name,
835  std::pair<int, int> Default,
836  bool OnlyFirstRequired) {
837  Attribute A = F.getFnAttribute(Name);
838  if (!A.isStringAttribute())
839  return Default;
840 
841  LLVMContext &Ctx = F.getContext();
842  std::pair<int, int> Ints = Default;
843  std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
844  if (Strs.first.trim().getAsInteger(0, Ints.first)) {
845  Ctx.emitError("can't parse first integer attribute " + Name);
846  return Default;
847  }
848  if (Strs.second.trim().getAsInteger(0, Ints.second)) {
849  if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
850  Ctx.emitError("can't parse second integer attribute " + Name);
851  return Default;
852  }
853  }
854 
855  return Ints;
856 }
857 
859  unsigned VmcntLo = (1 << getVmcntBitWidthLo()) - 1;
860  if (Version.Major < 9)
861  return VmcntLo;
862 
863  unsigned VmcntHi = ((1 << getVmcntBitWidthHi()) - 1) << getVmcntBitWidthLo();
864  return VmcntLo | VmcntHi;
865 }
866 
868  return (1 << getExpcntBitWidth()) - 1;
869 }
870 
872  return (1 << getLgkmcntBitWidth(Version.Major)) - 1;
873 }
874 
876  unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(), getVmcntBitWidthLo());
877  unsigned Expcnt = getBitMask(getExpcntBitShift(), getExpcntBitWidth());
878  unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(),
879  getLgkmcntBitWidth(Version.Major));
880  unsigned Waitcnt = VmcntLo | Expcnt | Lgkmcnt;
881  if (Version.Major < 9)
882  return Waitcnt;
883 
884  unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(), getVmcntBitWidthHi());
885  return Waitcnt | VmcntHi;
886 }
887 
888 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt) {
889  unsigned VmcntLo =
890  unpackBits(Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
891  if (Version.Major < 9)
892  return VmcntLo;
893 
894  unsigned VmcntHi =
895  unpackBits(Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
896  VmcntHi <<= getVmcntBitWidthLo();
897  return VmcntLo | VmcntHi;
898 }
899 
900 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt) {
901  return unpackBits(Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
902 }
903 
904 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt) {
905  return unpackBits(Waitcnt, getLgkmcntBitShift(),
906  getLgkmcntBitWidth(Version.Major));
907 }
908 
909 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
910  unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
911  Vmcnt = decodeVmcnt(Version, Waitcnt);
912  Expcnt = decodeExpcnt(Version, Waitcnt);
913  Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
914 }
915 
916 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded) {
917  Waitcnt Decoded;
918  Decoded.VmCnt = decodeVmcnt(Version, Encoded);
919  Decoded.ExpCnt = decodeExpcnt(Version, Encoded);
920  Decoded.LgkmCnt = decodeLgkmcnt(Version, Encoded);
921  return Decoded;
922 }
923 
924 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
925  unsigned Vmcnt) {
926  Waitcnt =
927  packBits(Vmcnt, Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
928  if (Version.Major < 9)
929  return Waitcnt;
930 
931  Vmcnt >>= getVmcntBitWidthLo();
932  return packBits(Vmcnt, Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
933 }
934 
935 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
936  unsigned Expcnt) {
937  return packBits(Expcnt, Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
938 }
939 
940 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
941  unsigned Lgkmcnt) {
942  return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(),
943  getLgkmcntBitWidth(Version.Major));
944 }
945 
947  unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
948  unsigned Waitcnt = getWaitcntBitMask(Version);
949  Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
950  Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
951  Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
952  return Waitcnt;
953 }
954 
955 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded) {
956  return encodeWaitcnt(Version, Decoded.VmCnt, Decoded.ExpCnt, Decoded.LgkmCnt);
957 }
958 
959 //===----------------------------------------------------------------------===//
960 // hwreg
961 //===----------------------------------------------------------------------===//
962 
963 namespace Hwreg {
964 
965 int64_t getHwregId(const StringRef Name) {
966  for (int Id = ID_SYMBOLIC_FIRST_; Id < ID_SYMBOLIC_LAST_; ++Id) {
967  if (IdSymbolic[Id] && Name == IdSymbolic[Id])
968  return Id;
969  }
970  return ID_UNKNOWN_;
971 }
972 
973 static unsigned getLastSymbolicHwreg(const MCSubtargetInfo &STI) {
974  if (isSI(STI) || isCI(STI) || isVI(STI))
976  else if (isGFX9(STI))
978  else if (isGFX10(STI) && !isGFX10_BEncoding(STI))
980  else
981  return ID_SYMBOLIC_LAST_;
982 }
983 
984 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI) {
985  return
988 }
989 
990 bool isValidHwreg(int64_t Id) {
991  return 0 <= Id && isUInt<ID_WIDTH_>(Id);
992 }
993 
994 bool isValidHwregOffset(int64_t Offset) {
995  return 0 <= Offset && isUInt<OFFSET_WIDTH_>(Offset);
996 }
997 
998 bool isValidHwregWidth(int64_t Width) {
999  return 0 <= (Width - 1) && isUInt<WIDTH_M1_WIDTH_>(Width - 1);
1000 }
1001 
1002 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width) {
1003  return (Id << ID_SHIFT_) |
1004  (Offset << OFFSET_SHIFT_) |
1005  ((Width - 1) << WIDTH_M1_SHIFT_);
1006 }
1007 
1008 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI) {
1009  return isValidHwreg(Id, STI) ? IdSymbolic[Id] : "";
1010 }
1011 
1012 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width) {
1013  Id = (Val & ID_MASK_) >> ID_SHIFT_;
1014  Offset = (Val & OFFSET_MASK_) >> OFFSET_SHIFT_;
1015  Width = ((Val & WIDTH_M1_MASK_) >> WIDTH_M1_SHIFT_) + 1;
1016 }
1017 
1018 } // namespace Hwreg
1019 
1020 //===----------------------------------------------------------------------===//
1021 // exp tgt
1022 //===----------------------------------------------------------------------===//
1023 
1024 namespace Exp {
1025 
1026 struct ExpTgt {
1028  unsigned Tgt;
1029  unsigned MaxIndex;
1030 };
1031 
1032 static constexpr ExpTgt ExpTgtInfo[] = {
1033  {{"null"}, ET_NULL, ET_NULL_MAX_IDX},
1034  {{"mrtz"}, ET_MRTZ, ET_MRTZ_MAX_IDX},
1035  {{"prim"}, ET_PRIM, ET_PRIM_MAX_IDX},
1036  {{"mrt"}, ET_MRT0, ET_MRT_MAX_IDX},
1037  {{"pos"}, ET_POS0, ET_POS_MAX_IDX},
1038  {{"param"}, ET_PARAM0, ET_PARAM_MAX_IDX},
1039 };
1040 
1041 bool getTgtName(unsigned Id, StringRef &Name, int &Index) {
1042  for (const ExpTgt &Val : ExpTgtInfo) {
1043  if (Val.Tgt <= Id && Id <= Val.Tgt + Val.MaxIndex) {
1044  Index = (Val.MaxIndex == 0) ? -1 : (Id - Val.Tgt);
1045  Name = Val.Name;
1046  return true;
1047  }
1048  }
1049  return false;
1050 }
1051 
1052 unsigned getTgtId(const StringRef Name) {
1053 
1054  for (const ExpTgt &Val : ExpTgtInfo) {
1055  if (Val.MaxIndex == 0 && Name == Val.Name)
1056  return Val.Tgt;
1057 
1058  if (Val.MaxIndex > 0 && Name.startswith(Val.Name)) {
1059  StringRef Suffix = Name.drop_front(Val.Name.size());
1060 
1061  unsigned Id;
1062  if (Suffix.getAsInteger(10, Id) || Id > Val.MaxIndex)
1063  return ET_INVALID;
1064 
1065  // Disable leading zeroes
1066  if (Suffix.size() > 1 && Suffix[0] == '0')
1067  return ET_INVALID;
1068 
1069  return Val.Tgt + Id;
1070  }
1071  }
1072  return ET_INVALID;
1073 }
1074 
1075 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI) {
1076  return (Id != ET_POS4 && Id != ET_PRIM) || isGFX10Plus(STI);
1077 }
1078 
1079 } // namespace Exp
1080 
1081 //===----------------------------------------------------------------------===//
1082 // MTBUF Format
1083 //===----------------------------------------------------------------------===//
1084 
1085 namespace MTBUFFormat {
1086 
1087 int64_t getDfmt(const StringRef Name) {
1088  for (int Id = DFMT_MIN; Id <= DFMT_MAX; ++Id) {
1089  if (Name == DfmtSymbolic[Id])
1090  return Id;
1091  }
1092  return DFMT_UNDEF;
1093 }
1094 
1096  assert(Id <= DFMT_MAX);
1097  return DfmtSymbolic[Id];
1098 }
1099 
1101  if (isSI(STI) || isCI(STI))
1102  return NfmtSymbolicSICI;
1103  if (isVI(STI) || isGFX9(STI))
1104  return NfmtSymbolicVI;
1105  return NfmtSymbolicGFX10;
1106 }
1107 
1108 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI) {
1109  auto lookupTable = getNfmtLookupTable(STI);
1110  for (int Id = NFMT_MIN; Id <= NFMT_MAX; ++Id) {
1111  if (Name == lookupTable[Id])
1112  return Id;
1113  }
1114  return NFMT_UNDEF;
1115 }
1116 
1117 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI) {
1118  assert(Id <= NFMT_MAX);
1119  return getNfmtLookupTable(STI)[Id];
1120 }
1121 
1122 bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI) {
1123  unsigned Dfmt;
1124  unsigned Nfmt;
1125  decodeDfmtNfmt(Id, Dfmt, Nfmt);
1126  return isValidNfmt(Nfmt, STI);
1127 }
1128 
1129 bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI) {
1130  return !getNfmtName(Id, STI).empty();
1131 }
1132 
1133 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt) {
1134  return (Dfmt << DFMT_SHIFT) | (Nfmt << NFMT_SHIFT);
1135 }
1136 
1137 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt) {
1138  Dfmt = (Format >> DFMT_SHIFT) & DFMT_MASK;
1139  Nfmt = (Format >> NFMT_SHIFT) & NFMT_MASK;
1140 }
1141 
1143  for (int Id = UFMT_FIRST; Id <= UFMT_LAST; ++Id) {
1144  if (Name == UfmtSymbolic[Id])
1145  return Id;
1146  }
1147  return UFMT_UNDEF;
1148 }
1149 
1151  return isValidUnifiedFormat(Id) ? UfmtSymbolic[Id] : "";
1152 }
1153 
1154 bool isValidUnifiedFormat(unsigned Id) {
1155  return Id <= UFMT_LAST;
1156 }
1157 
1158 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt) {
1159  int64_t Fmt = encodeDfmtNfmt(Dfmt, Nfmt);
1160  for (int Id = UFMT_FIRST; Id <= UFMT_LAST; ++Id) {
1161  if (Fmt == DfmtNfmt2UFmt[Id])
1162  return Id;
1163  }
1164  return UFMT_UNDEF;
1165 }
1166 
1167 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI) {
1168  return isGFX10Plus(STI) ? (Val <= UFMT_MAX) : (Val <= DFMT_NFMT_MAX);
1169 }
1170 
1172  if (isGFX10Plus(STI))
1173  return UFMT_DEFAULT;
1174  return DFMT_NFMT_DEFAULT;
1175 }
1176 
1177 } // namespace MTBUFFormat
1178 
1179 //===----------------------------------------------------------------------===//
1180 // SendMsg
1181 //===----------------------------------------------------------------------===//
1182 
1183 namespace SendMsg {
1184 
1185 int64_t getMsgId(const StringRef Name) {
1186  for (int i = ID_GAPS_FIRST_; i < ID_GAPS_LAST_; ++i) {
1187  if (IdSymbolic[i] && Name == IdSymbolic[i])
1188  return i;
1189  }
1190  return ID_UNKNOWN_;
1191 }
1192 
1193 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict) {
1194  if (Strict) {
1195  switch (MsgId) {
1196  case ID_SAVEWAVE:
1197  return isVI(STI) || isGFX9Plus(STI);
1198  case ID_STALL_WAVE_GEN:
1199  case ID_HALT_WAVES:
1200  case ID_ORDERED_PS_DONE:
1201  case ID_GS_ALLOC_REQ:
1202  case ID_GET_DOORBELL:
1203  return isGFX9Plus(STI);
1204  case ID_EARLY_PRIM_DEALLOC:
1205  return isGFX9(STI);
1206  case ID_GET_DDID:
1207  return isGFX10Plus(STI);
1208  default:
1209  return 0 <= MsgId && MsgId < ID_GAPS_LAST_ && IdSymbolic[MsgId];
1210  }
1211  } else {
1212  return 0 <= MsgId && isUInt<ID_WIDTH_>(MsgId);
1213  }
1214 }
1215 
1216 StringRef getMsgName(int64_t MsgId) {
1217  assert(0 <= MsgId && MsgId < ID_GAPS_LAST_);
1218  return IdSymbolic[MsgId];
1219 }
1220 
1221 int64_t getMsgOpId(int64_t MsgId, const StringRef Name) {
1222  const char* const *S = (MsgId == ID_SYSMSG) ? OpSysSymbolic : OpGsSymbolic;
1223  const int F = (MsgId == ID_SYSMSG) ? OP_SYS_FIRST_ : OP_GS_FIRST_;
1224  const int L = (MsgId == ID_SYSMSG) ? OP_SYS_LAST_ : OP_GS_LAST_;
1225  for (int i = F; i < L; ++i) {
1226  if (Name == S[i]) {
1227  return i;
1228  }
1229  }
1230  return OP_UNKNOWN_;
1231 }
1232 
1233 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1234  bool Strict) {
1235  assert(isValidMsgId(MsgId, STI, Strict));
1236 
1237  if (!Strict)
1238  return 0 <= OpId && isUInt<OP_WIDTH_>(OpId);
1239 
1240  switch(MsgId)
1241  {
1242  case ID_GS:
1243  return (OP_GS_FIRST_ <= OpId && OpId < OP_GS_LAST_) && OpId != OP_GS_NOP;
1244  case ID_GS_DONE:
1245  return OP_GS_FIRST_ <= OpId && OpId < OP_GS_LAST_;
1246  case ID_SYSMSG:
1247  return OP_SYS_FIRST_ <= OpId && OpId < OP_SYS_LAST_;
1248  default:
1249  return OpId == OP_NONE_;
1250  }
1251 }
1252 
1253 StringRef getMsgOpName(int64_t MsgId, int64_t OpId) {
1254  assert(msgRequiresOp(MsgId));
1255  return (MsgId == ID_SYSMSG)? OpSysSymbolic[OpId] : OpGsSymbolic[OpId];
1256 }
1257 
1258 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
1259  const MCSubtargetInfo &STI, bool Strict) {
1260  assert(isValidMsgOp(MsgId, OpId, STI, Strict));
1261 
1262  if (!Strict)
1263  return 0 <= StreamId && isUInt<STREAM_ID_WIDTH_>(StreamId);
1264 
1265  switch(MsgId)
1266  {
1267  case ID_GS:
1269  case ID_GS_DONE:
1270  return (OpId == OP_GS_NOP)?
1271  (StreamId == STREAM_ID_NONE_) :
1273  default:
1274  return StreamId == STREAM_ID_NONE_;
1275  }
1276 }
1277 
1278 bool msgRequiresOp(int64_t MsgId) {
1279  return MsgId == ID_GS || MsgId == ID_GS_DONE || MsgId == ID_SYSMSG;
1280 }
1281 
1282 bool msgSupportsStream(int64_t MsgId, int64_t OpId) {
1283  return (MsgId == ID_GS || MsgId == ID_GS_DONE) && OpId != OP_GS_NOP;
1284 }
1285 
1286 void decodeMsg(unsigned Val,
1287  uint16_t &MsgId,
1288  uint16_t &OpId,
1289  uint16_t &StreamId) {
1290  MsgId = Val & ID_MASK_;
1291  OpId = (Val & OP_MASK_) >> OP_SHIFT_;
1293 }
1294 
1295 uint64_t encodeMsg(uint64_t MsgId,
1296  uint64_t OpId,
1297  uint64_t StreamId) {
1298  return (MsgId << ID_SHIFT_) |
1299  (OpId << OP_SHIFT_) |
1301 }
1302 
1303 } // namespace SendMsg
1304 
1305 //===----------------------------------------------------------------------===//
1306 //
1307 //===----------------------------------------------------------------------===//
1308 
1310  return getIntegerAttribute(F, "InitialPSInputAddr", 0);
1311 }
1312 
1314  switch(cc) {
1322  return true;
1323  default:
1324  return false;
1325  }
1326 }
1327 
1329  return isShader(cc) || cc == CallingConv::AMDGPU_Gfx;
1330 }
1331 
1333  return !isGraphics(cc) || cc == CallingConv::AMDGPU_CS;
1334 }
1335 
1337  switch (CC) {
1347  return true;
1348  default:
1349  return false;
1350  }
1351 }
1352 
1354  switch (CC) {
1356  return true;
1357  default:
1358  return isEntryFunctionCC(CC);
1359  }
1360 }
1361 
1362 bool hasXNACK(const MCSubtargetInfo &STI) {
1363  return STI.getFeatureBits()[AMDGPU::FeatureXNACK];
1364 }
1365 
1366 bool hasSRAMECC(const MCSubtargetInfo &STI) {
1367  return STI.getFeatureBits()[AMDGPU::FeatureSRAMECC];
1368 }
1369 
1370 bool hasMIMG_R128(const MCSubtargetInfo &STI) {
1371  return STI.getFeatureBits()[AMDGPU::FeatureMIMG_R128] && !STI.getFeatureBits()[AMDGPU::FeatureR128A16];
1372 }
1373 
1374 bool hasGFX10A16(const MCSubtargetInfo &STI) {
1375  return STI.getFeatureBits()[AMDGPU::FeatureGFX10A16];
1376 }
1377 
1378 bool hasG16(const MCSubtargetInfo &STI) {
1379  return STI.getFeatureBits()[AMDGPU::FeatureG16];
1380 }
1381 
1382 bool hasPackedD16(const MCSubtargetInfo &STI) {
1383  return !STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem];
1384 }
1385 
1386 bool isSI(const MCSubtargetInfo &STI) {
1387  return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
1388 }
1389 
1390 bool isCI(const MCSubtargetInfo &STI) {
1391  return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
1392 }
1393 
1394 bool isVI(const MCSubtargetInfo &STI) {
1395  return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1396 }
1397 
1398 bool isGFX9(const MCSubtargetInfo &STI) {
1399  return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
1400 }
1401 
1402 bool isGFX9Plus(const MCSubtargetInfo &STI) {
1403  return isGFX9(STI) || isGFX10Plus(STI);
1404 }
1405 
1406 bool isGFX10(const MCSubtargetInfo &STI) {
1407  return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
1408 }
1409 
1410 bool isGFX10Plus(const MCSubtargetInfo &STI) { return isGFX10(STI); }
1411 
1413  return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding];
1414 }
1415 
1417  return STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding];
1418 }
1419 
1421  return STI.getFeatureBits()[AMDGPU::FeatureGFX10_3Insts];
1422 }
1423 
1424 bool isGFX90A(const MCSubtargetInfo &STI) {
1425  return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts];
1426 }
1427 
1428 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
1429  const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
1430  const unsigned FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0);
1431  return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
1432  Reg == AMDGPU::SCC;
1433 }
1434 
1435 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
1436  for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) {
1437  if (*R == Reg1) return true;
1438  }
1439  return false;
1440 }
1441 
1442 #define MAP_REG2REG \
1443  using namespace AMDGPU; \
1444  switch(Reg) { \
1445  default: return Reg; \
1446  CASE_CI_VI(FLAT_SCR) \
1447  CASE_CI_VI(FLAT_SCR_LO) \
1448  CASE_CI_VI(FLAT_SCR_HI) \
1449  CASE_VI_GFX9PLUS(TTMP0) \
1450  CASE_VI_GFX9PLUS(TTMP1) \
1451  CASE_VI_GFX9PLUS(TTMP2) \
1452  CASE_VI_GFX9PLUS(TTMP3) \
1453  CASE_VI_GFX9PLUS(TTMP4) \
1454  CASE_VI_GFX9PLUS(TTMP5) \
1455  CASE_VI_GFX9PLUS(TTMP6) \
1456  CASE_VI_GFX9PLUS(TTMP7) \
1457  CASE_VI_GFX9PLUS(TTMP8) \
1458  CASE_VI_GFX9PLUS(TTMP9) \
1459  CASE_VI_GFX9PLUS(TTMP10) \
1460  CASE_VI_GFX9PLUS(TTMP11) \
1461  CASE_VI_GFX9PLUS(TTMP12) \
1462  CASE_VI_GFX9PLUS(TTMP13) \
1463  CASE_VI_GFX9PLUS(TTMP14) \
1464  CASE_VI_GFX9PLUS(TTMP15) \
1465  CASE_VI_GFX9PLUS(TTMP0_TTMP1) \
1466  CASE_VI_GFX9PLUS(TTMP2_TTMP3) \
1467  CASE_VI_GFX9PLUS(TTMP4_TTMP5) \
1468  CASE_VI_GFX9PLUS(TTMP6_TTMP7) \
1469  CASE_VI_GFX9PLUS(TTMP8_TTMP9) \
1470  CASE_VI_GFX9PLUS(TTMP10_TTMP11) \
1471  CASE_VI_GFX9PLUS(TTMP12_TTMP13) \
1472  CASE_VI_GFX9PLUS(TTMP14_TTMP15) \
1473  CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3) \
1474  CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7) \
1475  CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11) \
1476  CASE_VI_GFX9PLUS(TTMP12_TTMP13_TTMP14_TTMP15) \
1477  CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
1478  CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
1479  CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
1480  CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
1481  }
1482 
1483 #define CASE_CI_VI(node) \
1484  assert(!isSI(STI)); \
1485  case node: return isCI(STI) ? node##_ci : node##_vi;
1486 
1487 #define CASE_VI_GFX9PLUS(node) \
1488  case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;
1489 
1490 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
1491  if (STI.getTargetTriple().getArch() == Triple::r600)
1492  return Reg;
1493  MAP_REG2REG
1494 }
1495 
1496 #undef CASE_CI_VI
1497 #undef CASE_VI_GFX9PLUS
1498 
1499 #define CASE_CI_VI(node) case node##_ci: case node##_vi: return node;
1500 #define CASE_VI_GFX9PLUS(node) case node##_vi: case node##_gfx9plus: return node;
1501 
1502 unsigned mc2PseudoReg(unsigned Reg) {
1503  MAP_REG2REG
1504 }
1505 
1506 #undef CASE_CI_VI
1507 #undef CASE_VI_GFX9PLUS
1508 #undef MAP_REG2REG
1509 
1510 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
1511  assert(OpNo < Desc.NumOperands);
1512  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
1513  return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
1514  OpType <= AMDGPU::OPERAND_SRC_LAST;
1515 }
1516 
1517 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
1518  assert(OpNo < Desc.NumOperands);
1519  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
1520  switch (OpType) {
1538  return true;
1539  default:
1540  return false;
1541  }
1542 }
1543 
1544 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
1545  assert(OpNo < Desc.NumOperands);
1546  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
1547  return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
1549 }
1550 
1551 // Avoid using MCRegisterClass::getSize, since that function will go away
1552 // (move from MC* level to Target* level). Return size in bits.
1553 unsigned getRegBitWidth(unsigned RCID) {
1554  switch (RCID) {
1555  case AMDGPU::VGPR_LO16RegClassID:
1556  case AMDGPU::VGPR_HI16RegClassID:
1557  case AMDGPU::SGPR_LO16RegClassID:
1558  case AMDGPU::AGPR_LO16RegClassID:
1559  return 16;
1560  case AMDGPU::SGPR_32RegClassID:
1561  case AMDGPU::VGPR_32RegClassID:
1562  case AMDGPU::VRegOrLds_32RegClassID:
1563  case AMDGPU::AGPR_32RegClassID:
1564  case AMDGPU::VS_32RegClassID:
1565  case AMDGPU::AV_32RegClassID:
1566  case AMDGPU::SReg_32RegClassID:
1567  case AMDGPU::SReg_32_XM0RegClassID:
1568  case AMDGPU::SRegOrLds_32RegClassID:
1569  return 32;
1570  case AMDGPU::SGPR_64RegClassID:
1571  case AMDGPU::VS_64RegClassID:
1572  case AMDGPU::AV_64RegClassID:
1573  case AMDGPU::SReg_64RegClassID:
1574  case AMDGPU::VReg_64RegClassID:
1575  case AMDGPU::AReg_64RegClassID:
1576  case AMDGPU::SReg_64_XEXECRegClassID:
1577  case AMDGPU::VReg_64_Align2RegClassID:
1578  case AMDGPU::AReg_64_Align2RegClassID:
1579  return 64;
1580  case AMDGPU::SGPR_96RegClassID:
1581  case AMDGPU::SReg_96RegClassID:
1582  case AMDGPU::VReg_96RegClassID:
1583  case AMDGPU::AReg_96RegClassID:
1584  case AMDGPU::VReg_96_Align2RegClassID:
1585  case AMDGPU::AReg_96_Align2RegClassID:
1586  case AMDGPU::AV_96RegClassID:
1587  return 96;
1588  case AMDGPU::SGPR_128RegClassID:
1589  case AMDGPU::SReg_128RegClassID:
1590  case AMDGPU::VReg_128RegClassID:
1591  case AMDGPU::AReg_128RegClassID:
1592  case AMDGPU::VReg_128_Align2RegClassID:
1593  case AMDGPU::AReg_128_Align2RegClassID:
1594  case AMDGPU::AV_128RegClassID:
1595  return 128;
1596  case AMDGPU::SGPR_160RegClassID:
1597  case AMDGPU::SReg_160RegClassID:
1598  case AMDGPU::VReg_160RegClassID:
1599  case AMDGPU::AReg_160RegClassID:
1600  case AMDGPU::VReg_160_Align2RegClassID:
1601  case AMDGPU::AReg_160_Align2RegClassID:
1602  case AMDGPU::AV_160RegClassID:
1603  return 160;
1604  case AMDGPU::SGPR_192RegClassID:
1605  case AMDGPU::SReg_192RegClassID:
1606  case AMDGPU::VReg_192RegClassID:
1607  case AMDGPU::AReg_192RegClassID:
1608  case AMDGPU::VReg_192_Align2RegClassID:
1609  case AMDGPU::AReg_192_Align2RegClassID:
1610  return 192;
1611  case AMDGPU::SGPR_256RegClassID:
1612  case AMDGPU::SReg_256RegClassID:
1613  case AMDGPU::VReg_256RegClassID:
1614  case AMDGPU::AReg_256RegClassID:
1615  case AMDGPU::VReg_256_Align2RegClassID:
1616  case AMDGPU::AReg_256_Align2RegClassID:
1617  return 256;
1618  case AMDGPU::SGPR_512RegClassID:
1619  case AMDGPU::SReg_512RegClassID:
1620  case AMDGPU::VReg_512RegClassID:
1621  case AMDGPU::AReg_512RegClassID:
1622  case AMDGPU::VReg_512_Align2RegClassID:
1623  case AMDGPU::AReg_512_Align2RegClassID:
1624  return 512;
1625  case AMDGPU::SGPR_1024RegClassID:
1626  case AMDGPU::SReg_1024RegClassID:
1627  case AMDGPU::VReg_1024RegClassID:
1628  case AMDGPU::AReg_1024RegClassID:
1629  case AMDGPU::VReg_1024_Align2RegClassID:
1630  case AMDGPU::AReg_1024_Align2RegClassID:
1631  return 1024;
1632  default:
1633  llvm_unreachable("Unexpected register class");
1634  }
1635 }
1636 
1637 unsigned getRegBitWidth(const MCRegisterClass &RC) {
1638  return getRegBitWidth(RC.getID());
1639 }
1640 
1641 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
1642  unsigned OpNo) {
1643  assert(OpNo < Desc.NumOperands);
1644  unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1645  return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
1646 }
1647 
1648 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
1650  return true;
1651 
1652  uint64_t Val = static_cast<uint64_t>(Literal);
1653  return (Val == DoubleToBits(0.0)) ||
1654  (Val == DoubleToBits(1.0)) ||
1655  (Val == DoubleToBits(-1.0)) ||
1656  (Val == DoubleToBits(0.5)) ||
1657  (Val == DoubleToBits(-0.5)) ||
1658  (Val == DoubleToBits(2.0)) ||
1659  (Val == DoubleToBits(-2.0)) ||
1660  (Val == DoubleToBits(4.0)) ||
1661  (Val == DoubleToBits(-4.0)) ||
1662  (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
1663 }
1664 
1665 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
1667  return true;
1668 
1669  // The actual type of the operand does not seem to matter as long
1670  // as the bits match one of the inline immediate values. For example:
1671  //
1672  // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
1673  // so it is a legal inline immediate.
1674  //
1675  // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
1676  // floating-point, so it is a legal inline immediate.
1677 
1678  uint32_t Val = static_cast<uint32_t>(Literal);
1679  return (Val == FloatToBits(0.0f)) ||
1680  (Val == FloatToBits(1.0f)) ||
1681  (Val == FloatToBits(-1.0f)) ||
1682  (Val == FloatToBits(0.5f)) ||
1683  (Val == FloatToBits(-0.5f)) ||
1684  (Val == FloatToBits(2.0f)) ||
1685  (Val == FloatToBits(-2.0f)) ||
1686  (Val == FloatToBits(4.0f)) ||
1687  (Val == FloatToBits(-4.0f)) ||
1688  (Val == 0x3e22f983 && HasInv2Pi);
1689 }
1690 
1691 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) {
1692  if (!HasInv2Pi)
1693  return false;
1694 
1696  return true;
1697 
1698  uint16_t Val = static_cast<uint16_t>(Literal);
1699  return Val == 0x3C00 || // 1.0
1700  Val == 0xBC00 || // -1.0
1701  Val == 0x3800 || // 0.5
1702  Val == 0xB800 || // -0.5
1703  Val == 0x4000 || // 2.0
1704  Val == 0xC000 || // -2.0
1705  Val == 0x4400 || // 4.0
1706  Val == 0xC400 || // -4.0
1707  Val == 0x3118; // 1/2pi
1708 }
1709 
1710 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi) {
1711  assert(HasInv2Pi);
1712 
1713  if (isInt<16>(Literal) || isUInt<16>(Literal)) {
1714  int16_t Trunc = static_cast<int16_t>(Literal);
1715  return AMDGPU::isInlinableLiteral16(Trunc, HasInv2Pi);
1716  }
1717  if (!(Literal & 0xffff))
1718  return AMDGPU::isInlinableLiteral16(Literal >> 16, HasInv2Pi);
1719 
1720  int16_t Lo16 = static_cast<int16_t>(Literal);
1721  int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
1722  return Lo16 == Hi16 && isInlinableLiteral16(Lo16, HasInv2Pi);
1723 }
1724 
1725 bool isInlinableIntLiteralV216(int32_t Literal) {
1726  int16_t Lo16 = static_cast<int16_t>(Literal);
1728  return isInlinableIntLiteral(Lo16);
1729 
1730  int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
1731  if (!(Literal & 0xffff))
1732  return isInlinableIntLiteral(Hi16);
1733  return Lo16 == Hi16 && isInlinableIntLiteral(Lo16);
1734 }
1735 
1736 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi) {
1737  assert(HasInv2Pi);
1738 
1739  int16_t Lo16 = static_cast<int16_t>(Literal);
1741  return true;
1742 
1743  int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
1744  if (!(Literal & 0xffff))
1745  return true;
1746  return Lo16 == Hi16;
1747 }
1748 
1749 bool isArgPassedInSGPR(const Argument *A) {
1750  const Function *F = A->getParent();
1751 
1752  // Arguments to compute shaders are never a source of divergence.
1753  CallingConv::ID CC = F->getCallingConv();
1754  switch (CC) {
1757  return true;
1766  // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
1767  // Everything else is in VGPRs.
1768  return F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::InReg) ||
1769  F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::ByVal);
1770  default:
1771  // TODO: Should calls support inreg for SGPR inputs?
1772  return false;
1773  }
1774 }
1775 
1776 static bool hasSMEMByteOffset(const MCSubtargetInfo &ST) {
1777  return isGCN3Encoding(ST) || isGFX10Plus(ST);
1778 }
1779 
1781  return isGFX9Plus(ST);
1782 }
1783 
1785  int64_t EncodedOffset) {
1786  return hasSMEMByteOffset(ST) ? isUInt<20>(EncodedOffset)
1787  : isUInt<8>(EncodedOffset);
1788 }
1789 
1791  int64_t EncodedOffset,
1792  bool IsBuffer) {
1793  return !IsBuffer &&
1795  isInt<21>(EncodedOffset);
1796 }
1797 
1798 static bool isDwordAligned(uint64_t ByteOffset) {
1799  return (ByteOffset & 3) == 0;
1800 }
1801 
1803  uint64_t ByteOffset) {
1804  if (hasSMEMByteOffset(ST))
1805  return ByteOffset;
1806 
1807  assert(isDwordAligned(ByteOffset));
1808  return ByteOffset >> 2;
1809 }
1810 
1812  int64_t ByteOffset, bool IsBuffer) {
1813  // The signed version is always a byte offset.
1814  if (!IsBuffer && hasSMRDSignedImmOffset(ST)) {
1816  return isInt<20>(ByteOffset) ? Optional<int64_t>(ByteOffset) : None;
1817  }
1818 
1819  if (!isDwordAligned(ByteOffset) && !hasSMEMByteOffset(ST))
1820  return None;
1821 
1822  int64_t EncodedOffset = convertSMRDOffsetUnits(ST, ByteOffset);
1823  return isLegalSMRDEncodedUnsignedOffset(ST, EncodedOffset)
1824  ? Optional<int64_t>(EncodedOffset)
1825  : None;
1826 }
1827 
1829  int64_t ByteOffset) {
1830  if (!isCI(ST) || !isDwordAligned(ByteOffset))
1831  return None;
1832 
1833  int64_t EncodedOffset = convertSMRDOffsetUnits(ST, ByteOffset);
1834  return isUInt<32>(EncodedOffset) ? Optional<int64_t>(EncodedOffset) : None;
1835 }
1836 
1838  // Address offset is 12-bit signed for GFX10, 13-bit for GFX9.
1839  if (AMDGPU::isGFX10(ST))
1840  return Signed ? 12 : 11;
1841 
1842  return Signed ? 13 : 12;
1843 }
1844 
1845 // Given Imm, split it into the values to put into the SOffset and ImmOffset
1846 // fields in an MUBUF instruction. Return false if it is not possible (due to a
1847 // hardware bug needing a workaround).
1848 //
1849 // The required alignment ensures that individual address components remain
1850 // aligned if they are aligned to begin with. It also ensures that additional
1851 // offsets within the given alignment can be added to the resulting ImmOffset.
1852 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
1853  const GCNSubtarget *Subtarget, Align Alignment) {
1854  const uint32_t MaxImm = alignDown(4095, Alignment.value());
1855  uint32_t Overflow = 0;
1856 
1857  if (Imm > MaxImm) {
1858  if (Imm <= MaxImm + 64) {
1859  // Use an SOffset inline constant for 4..64
1860  Overflow = Imm - MaxImm;
1861  Imm = MaxImm;
1862  } else {
1863  // Try to keep the same value in SOffset for adjacent loads, so that
1864  // the corresponding register contents can be re-used.
1865  //
1866  // Load values with all low-bits (except for alignment bits) set into
1867  // SOffset, so that a larger range of values can be covered using
1868  // s_movk_i32.
1869  //
1870  // Atomic operations fail to work correctly when individual address
1871  // components are unaligned, even if their sum is aligned.
1872  uint32_t High = (Imm + Alignment.value()) & ~4095;
1873  uint32_t Low = (Imm + Alignment.value()) & 4095;
1874  Imm = Low;
1875  Overflow = High - Alignment.value();
1876  }
1877  }
1878 
1879  // There is a hardware bug in SI and CI which prevents address clamping in
1880  // MUBUF instructions from working correctly with SOffsets. The immediate
1881  // offset is unaffected.
1882  if (Overflow > 0 &&
1884  return false;
1885 
1886  ImmOffset = Imm;
1887  SOffset = Overflow;
1888  return true;
1889 }
1890 
1892  *this = getDefaultForCallingConv(F.getCallingConv());
1893 
1894  StringRef IEEEAttr = F.getFnAttribute("amdgpu-ieee").getValueAsString();
1895  if (!IEEEAttr.empty())
1896  IEEE = IEEEAttr == "true";
1897 
1898  StringRef DX10ClampAttr
1899  = F.getFnAttribute("amdgpu-dx10-clamp").getValueAsString();
1900  if (!DX10ClampAttr.empty())
1901  DX10Clamp = DX10ClampAttr == "true";
1902 
1903  StringRef DenormF32Attr = F.getFnAttribute("denormal-fp-math-f32").getValueAsString();
1904  if (!DenormF32Attr.empty()) {
1905  DenormalMode DenormMode = parseDenormalFPAttribute(DenormF32Attr);
1908  }
1909 
1910  StringRef DenormAttr = F.getFnAttribute("denormal-fp-math").getValueAsString();
1911  if (!DenormAttr.empty()) {
1912  DenormalMode DenormMode = parseDenormalFPAttribute(DenormAttr);
1913 
1914  if (DenormF32Attr.empty()) {
1917  }
1918 
1921  }
1922 }
1923 
1924 namespace {
1925 
1926 struct SourceOfDivergence {
1927  unsigned Intr;
1928 };
1929 const SourceOfDivergence *lookupSourceOfDivergence(unsigned Intr);
1930 
1931 #define GET_SourcesOfDivergence_IMPL
1932 #define GET_Gfx9BufferFormat_IMPL
1933 #define GET_Gfx10PlusBufferFormat_IMPL
1934 #include "AMDGPUGenSearchableTables.inc"
1935 
1936 } // end anonymous namespace
1937 
1938 bool isIntrinsicSourceOfDivergence(unsigned IntrID) {
1939  return lookupSourceOfDivergence(IntrID);
1940 }
1941 
1942 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
1943  uint8_t NumComponents,
1944  uint8_t NumFormat,
1945  const MCSubtargetInfo &STI) {
1946  return isGFX10Plus(STI)
1947  ? getGfx10PlusBufferFormatInfo(BitsPerComp, NumComponents,
1948  NumFormat)
1949  : getGfx9BufferFormatInfo(BitsPerComp, NumComponents, NumFormat);
1950 }
1951 
1953  const MCSubtargetInfo &STI) {
1954  return isGFX10Plus(STI) ? getGfx10PlusBufferFormatInfo(Format)
1955  : getGfx9BufferFormatInfo(Format);
1956 }
1957 
1958 } // namespace AMDGPU
1959 
1962  switch (S) {
1964  OS << "Unsupported";
1965  break;
1967  OS << "Any";
1968  break;
1970  OS << "Off";
1971  break;
1973  OS << "On";
1974  break;
1975  }
1976  return OS;
1977 }
1978 
1979 } // namespace llvm
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:154
llvm::AMDGPU::Hwreg::encodeHwreg
uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width)
Definition: AMDGPUBaseInfo.cpp:1002
i
i
Definition: README.txt:29
llvm::AMDGPU::SendMsg::getMsgName
StringRef getMsgName(int64_t MsgId)
Definition: AMDGPUBaseInfo.cpp:1216
llvm::AMDGPU::MUBUFInfo::elements
uint8_t elements
Definition: AMDGPUBaseInfo.cpp:161
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:158
llvm::AMDGPU::getMCReg
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
Definition: AMDGPUBaseInfo.cpp:1490
llvm::AMDGPU::isHsaAbiVersion3
bool isHsaAbiVersion3(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:114
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::AMDGPUTargetID
AMDGPUTargetID(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:289
llvm::AMDGPU::mc2PseudoReg
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
Definition: AMDGPUBaseInfo.cpp:1502
llvm::AMDGPU::VOPInfo::IsSingle
bool IsSingle
Definition: AMDGPUBaseInfo.cpp:183
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4543
llvm::AMDGPU::MTBUFFormat::UFMT_MAX
@ UFMT_MAX
Definition: SIDefines.h:589
llvm
Definition: AllocatorList.h:23
llvm::AMDGPU::IsaInfo::getSGPRAllocGranule
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:557
llvm::AMDGPU::getMUBUFHasSoffset
bool getMUBUFHasSoffset(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:255
llvm::CallingConv::AMDGPU_HS
@ AMDGPU_HS
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:218
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::AMDGPU::MTBUFFormat::NumFormat
NumFormat
Definition: SIDefines.h:461
llvm::AMDGPU::Hwreg::getHwreg
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1008
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:156
llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1171
llvm::AMDGPU::SendMsg::IdSymbolic
const char *const IdSymbolic[ID_GAPS_LAST_]
Definition: AMDGPUAsmUtils.cpp:18
llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumSGPRs
constexpr char NumSGPRs[]
Key for Kernel::CodeProps::Metadata::mNumSGPRs.
Definition: AMDGPUMetadata.h:253
llvm::AMDGPU::MTBUFFormat::getDfmtName
StringRef getDfmtName(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1095
llvm::AMDGPU::SendMsg::encodeMsg
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
Definition: AMDGPUBaseInfo.cpp:1295
llvm::AMDGPU::getIsaVersion
IsaVersion getIsaVersion(StringRef GPU)
Definition: TargetParser.cpp:186
llvm::AMDGPU::decodeLgkmcnt
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:904
llvm::AMDGPU::Hwreg::ID_SHIFT_
@ ID_SHIFT_
Definition: SIDefines.h:375
llvm::StringRef::endswith
LLVM_NODISCARD bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:300
llvm::AMDGPU::SendMsg::OpGsSymbolic
const char *const OpGsSymbolic[OP_GS_LAST_]
Definition: AMDGPUAsmUtils.cpp:46
llvm::Function
Definition: Function.h:61
llvm::AMDGPU::getMUBUFBaseOpcode
int getMUBUFBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:230
llvm::Attribute
Definition: Attributes.h:52
llvm::AMDGPU::SIModeRegisterDefaults::FP32OutputDenormals
bool FP32OutputDenormals
Definition: AMDGPUBaseInfo.h:899
llvm::AMDGPU::getSMRDEncodedOffset
Optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
Definition: AMDGPUBaseInfo.cpp:1811
llvm::AMDGPU::MTBUFFormat::DFMT_MASK
@ DFMT_MASK
Definition: SIDefines.h:458
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isSramEccOnOrAny
bool isSramEccOnOrAny() const
Definition: AMDGPUBaseInfo.h:130
llvm::AMDGPU::getMCOpcode
int getMCOpcode(uint16_t Opcode, unsigned Gen)
Definition: AMDGPUBaseInfo.cpp:283
llvm::AMDGPU::decodeVmcnt
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:888
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:614
llvm::AMDGPU::hasSRAMECC
bool hasSRAMECC(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1366
llvm::AMDGPU::SIModeRegisterDefaults::IEEE
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
Definition: AMDGPUBaseInfo.h:890
llvm::AMDGPU::hasXNACK
bool hasXNACK(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1362
llvm::AMDGPU::IsaInfo::TargetIDSetting::Unsupported
@ Unsupported
llvm::AMDGPU::OPERAND_REG_IMM_V2FP16
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:143
High
uint64_t High
Definition: NVVMIntrRange.cpp:61
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::AMDGPU::SendMsg::ID_STALL_WAVE_GEN
@ ID_STALL_WAVE_GEN
Definition: SIDefines.h:299
llvm::AMDGPU::IsaInfo::TargetIDSetting::On
@ On
llvm::AMDGPU::isGFX10_BEncoding
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1416
llvm::Triple::amdgcn
@ amdgcn
Definition: Triple.h:72
amd_kernel_code_t::compute_pgm_resource_registers
uint64_t compute_pgm_resource_registers
Shader program settings for CS.
Definition: AMDKernelCodeT.h:558
llvm::AMDGPU::getVOP2IsSingle
bool getVOP2IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:270
llvm::AMDGPU::MTBUFFormat::encodeDfmtNfmt
int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt)
Definition: AMDGPUBaseInfo.cpp:1133
llvm::AMDGPU::getHsaAbiVersion
Optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:91
llvm::AMDGPU::MTBUFFormat::NFMT_UNDEF
@ NFMT_UNDEF
Definition: SIDefines.h:475
llvm::AMDGPUSubtarget::SEA_ISLANDS
@ SEA_ISLANDS
Definition: AMDGPUSubtarget.h:38
llvm::AMDGPU::Exp::ET_NULL
@ ET_NULL
Definition: SIDefines.h:736
llvm::AMDGPU::SendMsg::STREAM_ID_MASK_
@ STREAM_ID_MASK_
Definition: SIDefines.h:344
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::AMDGPU::SendMsg::OpSysSymbolic
const char *const OpSysSymbolic[OP_SYS_LAST_]
Definition: AMDGPUAsmUtils.cpp:38
llvm::AMDGPU::getSMRDEncodedLiteralOffset32
Optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
Definition: AMDGPUBaseInfo.cpp:1828
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::AMDGPU::MTBUFInfo::has_vaddr
bool has_vaddr
Definition: AMDGPUBaseInfo.cpp:171
llvm::AMDGPU::SendMsg::OP_GS_LAST_
@ OP_GS_LAST_
Definition: SIDefines.h:326
llvm::AMDGPU::MTBUFFormat::isValidNfmt
bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1129
Shift
bool Shift
Definition: README.txt:468
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_GFX1030_
@ ID_SYMBOLIC_FIRST_GFX1030_
Definition: SIDefines.h:373
llvm::AMDGPU::Hwreg::ID_MASK_
@ ID_MASK_
Definition: SIDefines.h:377
llvm::AMDGPU::Exp::ET_POS0
@ ET_POS0
Definition: SIDefines.h:737
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_MAX
@ DFMT_NFMT_MAX
Definition: SIDefines.h:490
llvm::FloatToBits
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:663
llvm::AMDGPU::IsaInfo::getNumExtraSGPRs
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
Definition: AMDGPUBaseInfo.cpp:623
llvm::AMDGPU::isGFX10
bool isGFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1406
llvm::AMDGPU::IsaInfo::getTotalNumVGPRs
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:686
llvm::AMDGPU::SendMsg::ID_EARLY_PRIM_DEALLOC
@ ID_EARLY_PRIM_DEALLOC
Definition: SIDefines.h:302
llvm::AMDGPU::MTBUFFormat::getUnifiedFormat
int64_t getUnifiedFormat(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1142
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setTargetIDFromTargetIDStream
void setTargetIDFromTargetIDStream(StringRef TargetID)
Definition: AMDGPUBaseInfo.cpp:366
llvm::AMDGPU::IsaInfo::getMinWavesPerEU
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:524
llvm::Optional< uint8_t >
llvm::AMDGPU::SIModeRegisterDefaults::getDefaultForCallingConv
static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.h:916
llvm::AMDGPU::MUBUFInfo::has_soffset
bool has_soffset
Definition: AMDGPUBaseInfo.cpp:164
llvm::MCRegisterClass::contains
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
Definition: MCRegisterInfo.h:68
llvm::AMDGPU::SIModeRegisterDefaults::FP32InputDenormals
bool FP32InputDenormals
If this is set, neither input or output denormals are flushed for most f32 instructions.
Definition: AMDGPUBaseInfo.h:898
llvm::AMDGPU::IsaInfo::TargetIDSetting::Any
@ Any
llvm::GCNSubtarget
Definition: GCNSubtarget.h:38
AMDGPUAsmUtils.h
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:892
llvm::AMDGPU::getVmcntBitMask
unsigned getVmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:858
llvm::AMDGPU::isGlobalSegment
bool isGlobalSegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:804
llvm::AMDGPU::SendMsg::getMsgId
int64_t getMsgId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1185
llvm::AMDGPU::hasGFX10_3Insts
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1420
TargetParser.h
llvm::AMDGPU::SendMsg::ID_GAPS_LAST_
@ ID_GAPS_LAST_
Definition: SIDefines.h:307
llvm::AMDGPU::IsaInfo::getMaxNumVGPRs
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:711
llvm::AMDGPU::Exp::ET_PARAM0
@ ET_PARAM0
Definition: SIDefines.h:742
llvm::AMDGPU::getWaitcntBitMask
unsigned getWaitcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:875
llvm::AMDGPU::isIntrinsicSourceOfDivergence
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
Definition: AMDGPUBaseInfo.cpp:1938
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc2
uint32_t compute_pgm_rsrc2
Definition: AMDHSAKernelDescriptor.h:174
llvm::AMDGPU::SendMsg::getMsgOpName
StringRef getMsgOpName(int64_t MsgId, int64_t OpId)
Definition: AMDGPUBaseInfo.cpp:1253
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::AMDGPU::getMTBUFOpcode
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
Definition: AMDGPUBaseInfo.cpp:205
llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable
static const StringLiteral * getNfmtLookupTable(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1100
llvm::CallingConv::AMDGPU_Gfx
@ AMDGPU_Gfx
Calling convention used for AMD graphics targets.
Definition: CallingConv.h:245
llvm::AMDGPU::MUBUFInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:159
llvm::AMDGPU::SendMsg::ID_SAVEWAVE
@ ID_SAVEWAVE
Definition: SIDefines.h:298
llvm::AMDGPU::MIMGInfo::VAddrDwords
uint8_t VAddrDwords
Definition: AMDGPUBaseInfo.h:355
llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:512
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::AMDGPU::MTBUFFormat::isValidDfmtNfmt
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1122
AMDHSAKernelDescriptor.h
llvm::AMDGPU::HSAMD::V3::VersionMajor
constexpr uint32_t VersionMajor
HSA metadata major version.
Definition: AMDGPUMetadata.h:454
llvm::AMDGPU::SendMsg::ID_MASK_
@ ID_MASK_
Definition: SIDefines.h:311
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
llvm::AMDGPU::IsaInfo::TargetIDSetting
TargetIDSetting
Definition: AMDGPUBaseInfo.h:78
llvm::parseDenormalFPAttribute
DenormalMode parseDenormalFPAttribute(StringRef Str)
Returns the denormal mode to use for inputs and outputs.
Definition: FloatingPointMode.h:174
llvm::AMDGPU::Hwreg::decodeHwreg
void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)
Definition: AMDGPUBaseInfo.cpp:1012
llvm::AMDGPU::Hwreg::ID_UNKNOWN_
@ ID_UNKNOWN_
Definition: SIDefines.h:352
llvm::AMDGPU::IsaVersion
Instruction set architecture version.
Definition: TargetParser.h:102
llvm::AMDGPU::IsaInfo::getSGPREncodingGranule
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:566
CommandLine.h
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicVI
const StringLiteral NfmtSymbolicVI[]
Definition: AMDGPUAsmUtils.cpp:136
llvm::AMDGPU::isGFX90A
bool isGFX90A(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1424
llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
Definition: AMDGPU.h:380
llvm::AMDGPU::SendMsg::OP_GS_FIRST_
@ OP_GS_FIRST_
Definition: SIDefines.h:327
llvm::AMDGPU::OPERAND_REG_IMM_FP32
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:140
llvm::AMDGPU::SendMsg::ID_GET_DOORBELL
@ ID_GET_DOORBELL
Definition: SIDefines.h:304
llvm::AMDGPU::MUBUFInfo::has_srsrc
bool has_srsrc
Definition: AMDGPUBaseInfo.cpp:163
llvm::StringLiteral
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:872
llvm::AMDGPU::getMTBUFHasSrsrc
bool getMTBUFHasSrsrc(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:220
GlobalValue.h
llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4
@ ELFABIVERSION_AMDGPU_HSA_V4
Definition: ELF.h:373
ELF.h
llvm::DenormalMode::Input
DenormalModeKind Input
Denormal treatment kind for floating point instruction inputs in the default floating-point environme...
Definition: FloatingPointMode.h:90
llvm::AMDGPU::isShader
bool isShader(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1313
llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:552
llvm::AMDGPU::MTBUFInfo::has_soffset
bool has_soffset
Definition: AMDGPUBaseInfo.cpp:173
amd_kernel_code_t::amd_kernel_code_version_major
uint32_t amd_kernel_code_version_major
Definition: AMDKernelCodeT.h:527
llvm::AMDGPU::Exp::ET_INVALID
@ ET_INVALID
Definition: SIDefines.h:752
llvm::AMDGPU::Exp::ET_MRTZ_MAX_IDX
@ ET_MRTZ_MAX_IDX
Definition: SIDefines.h:746
llvm::X86AS::FS
@ FS
Definition: X86.h:183
GCNSubtarget.h
llvm::AMDGPU::hasSMEMByteOffset
static bool hasSMEMByteOffset(const MCSubtargetInfo &ST)
Definition: AMDGPUBaseInfo.cpp:1776
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::AMDGPU::getRegOperandSize
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
Definition: AMDGPUBaseInfo.cpp:1641
llvm::AMDGPU::SendMsg::OP_SYS_LAST_
@ OP_SYS_LAST_
Definition: SIDefines.h:333
llvm::ReplacementType::Literal
@ Literal
llvm::AMDGPU::Hwreg::isValidHwreg
bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:984
llvm::AMDGPU::SendMsg::ID_GS_ALLOC_REQ
@ ID_GS_ALLOC_REQ
Definition: SIDefines.h:303
llvm::AMDGPU::MTBUFFormat::UFMT_DEFAULT
@ UFMT_DEFAULT
Definition: SIDefines.h:592
llvm::StringRef::split
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:730
llvm::AMDGPU::MIMGBaseOpcodeInfo
Definition: AMDGPUBaseInfo.h:280
llvm::AMDGPU::isInlinableIntLiteralV216
bool isInlinableIntLiteralV216(int32_t Literal)
Definition: AMDGPUBaseInfo.cpp:1725
Intr
unsigned Intr
Definition: AMDGPUBaseInfo.cpp:1927
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:163
llvm::AMDGPU::MTBUFFormat::DfmtSymbolic
const StringLiteral DfmtSymbolic[]
Definition: AMDGPUAsmUtils.cpp:95
llvm::AMDGPU::getMUBUFOpcode
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
Definition: AMDGPUBaseInfo.cpp:235
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:107
llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V3
@ ELFABIVERSION_AMDGPU_HSA_V3
Definition: ELF.h:372
llvm::AMDGPU::getSMEMIsBuffer
bool getSMEMIsBuffer(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:260
llvm::AMDGPU::IsaInfo::getMaxNumSGPRs
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
Definition: AMDGPUBaseInfo.cpp:606
llvm::AMDGPU::isSGPR
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
Definition: AMDGPUBaseInfo.cpp:1428
llvm::AMDGPU::IsaInfo::getTargetIDSettingFromFeatureString
static TargetIDSetting getTargetIDSettingFromFeatureString(StringRef FeatureString)
Definition: AMDGPUBaseInfo.cpp:357
llvm::AMDGPU::SendMsg::STREAM_ID_LAST_
@ STREAM_ID_LAST_
Definition: SIDefines.h:340
llvm::SubtargetFeatures::getFeatures
const std::vector< std::string > & getFeatures() const
Returns the vector of individual subtarget features.
Definition: SubtargetFeature.h:196
llvm::DoubleToBits
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:653
llvm::SubtargetFeatures
Manages the enabling and disabling of subtarget specific features.
Definition: SubtargetFeature.h:183
llvm::AMDGPU::MTBUFFormat::UfmtSymbolic
const StringLiteral UfmtSymbolic[]
Definition: AMDGPUAsmUtils.cpp:147
llvm::AMDGPU::SendMsg::ID_SYSMSG
@ ID_SYSMSG
Definition: SIDefines.h:306
llvm::AMDGPU::Hwreg::Id
Id
Definition: SIDefines.h:351
llvm::AMDGPUAS::GLOBAL_ADDRESS
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:373
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackOnOrAny
bool isXnackOnOrAny() const
Definition: AMDGPUBaseInfo.h:101
llvm::AMDGPU::decodeExpcnt
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:900
llvm::AMDGPU::SendMsg::ID_SHIFT_
@ ID_SHIFT_
Definition: SIDefines.h:309
llvm::AMDGPU::MTBUFInfo::BaseOpcode
uint16_t BaseOpcode
Definition: AMDGPUBaseInfo.cpp:169
llvm::alignDown
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
Definition: MathExtras.h:753
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:196
S_00B848_MEM_ORDERED
#define S_00B848_MEM_ORDERED(x)
Definition: SIDefines.h:870
llvm::AMDGPU::hasGFX10A16
bool hasGFX10A16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1374
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::AMDGPU::Exp::ET_PRIM
@ ET_PRIM
Definition: SIDefines.h:741
llvm::AMDGPU::SendMsg::OP_GS_NOP
@ OP_GS_NOP
Definition: SIDefines.h:322
llvm::AMDGPU::OPERAND_REG_IMM_FP64
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:141
llvm::AMDGPU::getMTBUFBaseOpcode
int getMTBUFBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:200
llvm::AMDGPU::getInitialPSInputAddr
unsigned getInitialPSInputAddr(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1309
llvm::AMDGPU::SendMsg::OP_SHIFT_
@ OP_SHIFT_
Definition: SIDefines.h:316
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_GFX9_
@ ID_SYMBOLIC_FIRST_GFX9_
Definition: SIDefines.h:362
llvm::Triple::r600
@ r600
Definition: Triple.h:71
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::AMDGPU::Exp::ExpTgt::Name
StringLiteral Name
Definition: AMDGPUBaseInfo.cpp:1027
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
llvm::AMDGPU::getMTBUFHasSoffset
bool getMTBUFHasSoffset(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:225
llvm::raw_ostream::flush
void flush()
Definition: raw_ostream.h:183
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:230
llvm::AMDGPU::MTBUFFormat::DFMT_UNDEF
@ DFMT_UNDEF
Definition: SIDefines.h:454
llvm::AMDGPU::decodeWaitcnt
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
Definition: AMDGPUBaseInfo.cpp:909
amd_kernel_code_t::wavefront_size
uint8_t wavefront_size
Wavefront size expressed as a power of two.
Definition: AMDKernelCodeT.h:643
llvm::AMDGPU::MTBUFInfo
Definition: AMDGPUBaseInfo.cpp:167
llvm::AMDGPU::OPERAND_REG_IMM_V2FP32
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:146
llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:543
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::getSramEccSetting
TargetIDSetting getSramEccSetting() const
Definition: AMDGPUBaseInfo.h:144
llvm::amdhsa::kernel_descriptor_t::kernel_code_properties
uint16_t kernel_code_properties
Definition: AMDHSAKernelDescriptor.h:175
llvm::IndexedInstrProf::Version
const uint64_t Version
Definition: InstrProf.h:991
llvm::AMDGPU::getMUBUFHasSrsrc
bool getMUBUFHasSrsrc(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:250
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::AMDGPU::convertSMRDOffsetUnits
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
Definition: AMDGPUBaseInfo.cpp:1802
llvm::AMDGPU::MTBUFFormat::UFMT_FIRST
@ UFMT_FIRST
Definition: SIDefines.h:586
llvm::AMDGPU::IsaInfo::getEUsPerCU
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:501
llvm::AMDGPU::MIMGInfo::MIMGEncoding
uint8_t MIMGEncoding
Definition: AMDGPUBaseInfo.h:353
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:90
llvm::AMDGPU::MTBUFInfo::elements
uint8_t elements
Definition: AMDGPUBaseInfo.cpp:170
llvm::AMDGPU::IsaInfo::getLocalMemorySize
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:492
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AMDGPU::getMIMGOpcode
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
Definition: AMDGPUBaseInfo.cpp:138
llvm::Triple::getArch
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:307
llvm::AMDGPU::MTBUFFormat::UFMT_UNDEF
@ UFMT_UNDEF
Definition: SIDefines.h:591
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:248
llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat
bool isValidUnifiedFormat(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1154
llvm::AMDGPU::isCI
bool isCI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1390
llvm::StringRef::getAsInteger
std::enable_if_t< std::numeric_limits< T >::is_signed, bool > getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:511
llvm::None
const NoneType None
Definition: None.h:23
llvm::AMDGPU::SendMsg::StreamId
StreamId
Definition: SIDefines.h:337
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::AMDGPU::SendMsg::ID_GAPS_FIRST_
@ ID_GAPS_FIRST_
Definition: SIDefines.h:308
llvm::AMDGPU::isGFX10Plus
bool isGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1410
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc3
uint32_t compute_pgm_rsrc3
Definition: AMDHSAKernelDescriptor.h:172
llvm::AMDGPU::isEntryFunctionCC
bool isEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1336
amd_kernel_code_t::amd_machine_version_minor
uint16_t amd_machine_version_minor
Definition: AMDKernelCodeT.h:531
llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1167
llvm::AMDGPU::isHsaAbiVersion2
bool isHsaAbiVersion2(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:108
llvm::AMDGPU::hasPackedD16
bool hasPackedD16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1382
llvm::AMDGPU::Hwreg::getLastSymbolicHwreg
static unsigned getLastSymbolicHwreg(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:973
llvm::AMDGPU::SendMsg::ID_ORDERED_PS_DONE
@ ID_ORDERED_PS_DONE
Definition: SIDefines.h:301
llvm::AMDGPU::MTBUFFormat::NFMT_MIN
@ NFMT_MIN
Definition: SIDefines.h:472
llvm::AMDGPU::SMInfo::IsBuffer
bool IsBuffer
Definition: AMDGPUBaseInfo.cpp:178
llvm::AMDGPU::Hwreg::OFFSET_MASK_
@ OFFSET_MASK_
Definition: SIDefines.h:384
llvm::AMDGPU::Hwreg::isValidHwregWidth
bool isValidHwregWidth(int64_t Width)
Definition: AMDGPUBaseInfo.cpp:998
llvm::AMDGPU::shouldEmitConstantsToTextSection
bool shouldEmitConstantsToTextSection(const Triple &TT)
Definition: AMDGPUBaseInfo.cpp:814
llvm::AMDGPU::Hwreg::WIDTH_M1_SHIFT_
@ WIDTH_M1_SHIFT_
Definition: SIDefines.h:394
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:117
llvm::Triple::AMDHSA
@ AMDHSA
Definition: Triple.h:190
llvm::AMDGPU::isVI
bool isVI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1394
llvm::AMDGPU::MUBUFInfo::BaseOpcode
uint16_t BaseOpcode
Definition: AMDGPUBaseInfo.cpp:160
llvm::AMDGPU::isInlinableLiteralV216
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:1710
llvm::LLVMContext::emitError
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Definition: LLVMContext.cpp:251
llvm::cl::opt
Definition: CommandLine.h:1419
llvm::CallingConv::AMDGPU_GS
@ AMDGPU_GS
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:202
llvm::AMDGPU::Exp::ET_PARAM_MAX_IDX
@ ET_PARAM_MAX_IDX
Definition: SIDefines.h:750
llvm::AMDGPU::getRegBitWidth
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
Definition: AMDGPUBaseInfo.cpp:1553
llvm::AMDGPU::MTBUFFormat::NFMT_MAX
@ NFMT_MAX
Definition: SIDefines.h:473
llvm::AMDGPU::getExpcntBitMask
unsigned getExpcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:867
llvm::MCInstrDesc::NumOperands
unsigned short NumOperands
Definition: MCInstrDesc.h:199
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:211
llvm::divideCeil
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:742
llvm::AMDGPU::isHsaAbiVersion4
bool isHsaAbiVersion4(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:120
llvm::AMDGPU::IsaInfo::getMinNumSGPRs
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:589
llvm::AMDGPU::isInlinableIntLiteral
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
Definition: AMDGPUBaseInfo.h:810
llvm::AMDGPU::hasG16
bool hasG16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1378
AMDGPUMCTargetDesc.h
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:380
llvm::isUInt< 16 >
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:408
llvm::AMDGPU::SMInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:177
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::AMDGPU::MTBUFFormat::NFMT_MASK
@ NFMT_MASK
Definition: SIDefines.h:479
llvm::Triple::getOS
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:316
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:153
llvm::AMDGPU::isGFX9
bool isGFX9(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1398
llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE
@ FLOAT_DENORM_MODE_FLUSH_NONE
Definition: AMDHSAKernelDescriptor.h:63
llvm::AMDGPU::MTBUFFormat::DFMT_SHIFT
@ DFMT_SHIFT
Definition: SIDefines.h:457
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::AMDGPU::initDefaultAMDKernelCodeT
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:730
llvm::AMDGPU::getIntegerAttribute
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
Definition: AMDGPUBaseInfo.cpp:818
llvm::AMDGPU::VOPInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:182
llvm::AMDGPU::OPERAND_SRC_FIRST
@ OPERAND_SRC_FIRST
Definition: SIDefines.h:180
amd_kernel_code_t::call_convention
int32_t call_convention
Definition: AMDKernelCodeT.h:645
llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V2
@ ELFABIVERSION_AMDGPU_HSA_V2
Definition: ELF.h:371
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition: MCSubtargetInfo.h:108
llvm::DenormalMode
Represent subnormal handling kind for floating point instruction inputs and outputs.
Definition: FloatingPointMode.h:67
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:440
llvm::AMDGPU::getGcnBufferFormatInfo
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1942
llvm::AMDGPU::SendMsg::OP_UNKNOWN_
@ OP_UNKNOWN_
Definition: SIDefines.h:315
llvm::AMDGPU::IsaInfo::getWavefrontSize
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:483
llvm::isUInt< 32 >
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:411
llvm::AMDGPU::isSISrcInlinableOperand
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this opearnd support only inlinable literals?
Definition: AMDGPUBaseInfo.cpp:1544
llvm::AMDGPU::Hwreg::isValidHwregOffset
bool isValidHwregOffset(int64_t Offset)
Definition: AMDGPUBaseInfo.cpp:994
llvm::AMDGPU::SIModeRegisterDefaults::DX10Clamp
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
Definition: AMDGPUBaseInfo.h:894
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AMDGPU::encodeVmcnt
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
Definition: AMDGPUBaseInfo.cpp:924
llvm::isUInt< 8 >
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:405
llvm::AMDGPU::SendMsg::msgRequiresOp
bool msgRequiresOp(int64_t MsgId)
Definition: AMDGPUBaseInfo.cpp:1278
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::getXnackSetting
TargetIDSetting getXnackSetting() const
Definition: AMDGPUBaseInfo.h:115
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16InputDenormals
bool FP64FP16InputDenormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
Definition: AMDGPUBaseInfo.h:903
amd_kernel_code_t::amd_machine_version_stepping
uint16_t amd_machine_version_stepping
Definition: AMDKernelCodeT.h:532
amd_kernel_code_t::group_segment_alignment
uint8_t group_segment_alignment
Definition: AMDKernelCodeT.h:635
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:207
llvm::AMDGPU::Waitcnt::LgkmCnt
unsigned LgkmCnt
Definition: AMDGPUBaseInfo.h:464
llvm::AMDGPU::Exp::isSupportedTgtId
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1075
llvm::AMDGPU::IsaInfo::getTotalNumSGPRs
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:570
llvm::AMDGPU::getMIMGInfo
const LLVM_READONLY MIMGInfo * getMIMGInfo(unsigned Opc)
llvm::AMDGPU::VOPInfo
Definition: AMDGPUBaseInfo.cpp:181
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:155
llvm::AMDGPU::Exp::ET_MRT0
@ ET_MRT0
Definition: SIDefines.h:733
llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:577
AmdhsaCodeObjectVersion
static llvm::cl::opt< unsigned > AmdhsaCodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden, llvm::cl::desc("AMDHSA Code Object Version"), llvm::cl::init(4), llvm::cl::ZeroOrMore)
llvm::DenormalMode::IEEE
@ IEEE
IEEE-754 denormal numbers preserved.
Definition: FloatingPointMode.h:74
llvm::AMDGPU::IsaInfo::getNumSGPRBlocks
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
Definition: AMDGPUBaseInfo.cpp:653
amd_kernel_code_t::kernarg_segment_alignment
uint8_t kernarg_segment_alignment
The maximum byte alignment of variables used by the kernel in the specified memory segment.
Definition: AMDKernelCodeT.h:634
amd_kernel_code_t::amd_kernel_code_version_minor
uint32_t amd_kernel_code_version_minor
Definition: AMDKernelCodeT.h:528
llvm::AMDGPU::Exp::ExpTgtInfo
static constexpr ExpTgt ExpTgtInfo[]
Definition: AMDGPUBaseInfo.cpp:1032
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:164
llvm::AMDGPU::IsaInfo::TargetIDSetting::Off
@ Off
llvm::AMDGPU::MTBUFFormat::DFMT_MIN
@ DFMT_MIN
Definition: SIDefines.h:451
llvm::AMDGPU::MIMGInfo::BaseOpcode
uint16_t BaseOpcode
Definition: AMDGPUBaseInfo.h:352
llvm::AMDGPU::isInlinableLiteral16
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:1691
llvm::AMDGPU::getMIMGBaseOpcodeInfo
const LLVM_READONLY MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
llvm::AMDGPU::CPol::SCC
@ SCC
Definition: SIDefines.h:285
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicGFX10
const StringLiteral NfmtSymbolicGFX10[]
Definition: AMDGPUAsmUtils.cpp:114
llvm::AMDGPU::isDwordAligned
static bool isDwordAligned(uint64_t ByteOffset)
Definition: AMDGPUBaseInfo.cpp:1798
llvm::AMDGPU::SendMsg::msgSupportsStream
bool msgSupportsStream(int64_t MsgId, int64_t OpId)
Definition: AMDGPUBaseInfo.cpp:1282
llvm::AMDGPU::Exp::ExpTgt::Tgt
unsigned Tgt
Definition: AMDGPUBaseInfo.cpp:1028
llvm::AMDGPU::hasSMRDSignedImmOffset
static bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST)
Definition: AMDGPUBaseInfo.cpp:1780
llvm::AMDGPU::Exp::ET_MRTZ
@ ET_MRTZ
Definition: SIDefines.h:735
llvm::AMDGPU::Hwreg::ID_XNACK_MASK
@ ID_XNACK_MASK
Definition: SIDefines.h:370
llvm::AMDGPU::Exp::ExpTgt::MaxIndex
unsigned MaxIndex
Definition: AMDGPUBaseInfo.cpp:1029
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
AMDGPU.h
MAP_REG2REG
#define MAP_REG2REG
Definition: AMDGPUBaseInfo.cpp:1442
llvm::AMDGPU::getVOP3IsSingle
bool getVOP3IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:275
llvm::AMDGPU::Hwreg::OFFSET_SHIFT_
@ OFFSET_SHIFT_
Definition: SIDefines.h:382
llvm::AMDGPU::isModuleEntryFunctionCC
bool isModuleEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1353
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::AMDGPU::isCompute
bool isCompute(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1332
llvm::AMDGPU::IsaInfo::getVGPREncodingGranule
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:674
llvm::MCRegisterClass::getID
unsigned getID() const
getID() - Return the register class ID number.
Definition: MCRegisterInfo.h:48
uint32_t
llvm::AMDGPU::IsaInfo::getNumVGPRBlocks
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:720
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
Definition: AMDGPUBaseInfo.cpp:1784
llvm::AMDGPU::isSISrcOperand
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
Definition: AMDGPUBaseInfo.cpp:1510
llvm::AMDGPU::isGraphics
bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1328
amd_kernel_code_t
AMD Kernel Code Object (amd_kernel_code_t).
Definition: AMDKernelCodeT.h:526
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackSupported
bool isXnackSupported() const
Definition: AMDGPUBaseInfo.h:96
llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:547
llvm::AMDGPU::Exp::getTgtName
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
Definition: AMDGPUBaseInfo.cpp:1041
llvm::AMDGPU::Waitcnt::VmCnt
unsigned VmCnt
Definition: AMDGPUBaseInfo.h:462
llvm::AMDGPU::getMTBUFHasVAddr
bool getMTBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:215
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
AMDHSA_BITS_SET
#define AMDHSA_BITS_SET(DST, MSK, VAL)
Definition: AMDHSAKernelDescriptor.h:42
llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt)
Definition: AMDGPUBaseInfo.cpp:1158
amd_kernel_code_t::kernel_code_entry_byte_offset
int64_t kernel_code_entry_byte_offset
Byte offset (possibly negative) from start of amd_kernel_code_t object to kernel's entry point instru...
Definition: AMDKernelCodeT.h:544
llvm::AMDGPU::MTBUFFormat::DfmtNfmt2UFmt
const unsigned DfmtNfmt2UFmt[]
Definition: AMDGPUAsmUtils.cpp:241
llvm::AMDGPU::GcnBufferFormatInfo
Definition: AMDGPUBaseInfo.h:54
llvm::AMDGPU::SendMsg::ID_GS
@ ID_GS
Definition: SIDefines.h:296
llvm::AMDGPU::isGFX9Plus
bool isGFX9Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1402
llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:766
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::CallingConv::AMDGPU_LS
@ AMDGPU_LS
Calling convention used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:226
llvm::AMDGPU::SendMsg::ID_GS_DONE
@ ID_GS_DONE
Definition: SIDefines.h:297
amd_kernel_code_t::amd_machine_kind
uint16_t amd_machine_kind
Definition: AMDKernelCodeT.h:529
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: AMDGPUBaseInfo.h:904
llvm::AMDGPU::isGroupSegment
bool isGroupSegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:800
llvm::AMDGPU::SendMsg::STREAM_ID_FIRST_
@ STREAM_ID_FIRST_
Definition: SIDefines.h:341
llvm::AMDGPU::SMInfo
Definition: AMDGPUBaseInfo.cpp:176
llvm::AMDGPU::MTBUFFormat::UFMT_LAST
@ UFMT_LAST
Definition: SIDefines.h:587
llvm::AMDGPU::Hwreg::IdSymbolic
const char *const IdSymbolic[]
Definition: AMDGPUAsmUtils.cpp:58
llvm::AMDGPU::encodeWaitcnt
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
Definition: AMDGPUBaseInfo.cpp:946
llvm::AMDGPU::SendMsg::isValidMsgOp
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1233
llvm::AMDGPU::SendMsg::OP_SYS_FIRST_
@ OP_SYS_FIRST_
Definition: SIDefines.h:334
Attributes.h
llvm::isInt< 16 >
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:370
llvm::AMDGPU::isSI
bool isSI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1386
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:165
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString
std::string toString() const
Definition: AMDGPUBaseInfo.cpp:378
amd_kernel_code_t::amd_machine_version_major
uint16_t amd_machine_version_major
Definition: AMDKernelCodeT.h:530
llvm::CallingConv::SPIR_KERNEL
@ SPIR_KERNEL
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:147
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
llvm::Any
Definition: Any.h:26
llvm::AMDGPU::OPERAND_SRC_LAST
@ OPERAND_SRC_LAST
Definition: SIDefines.h:181
llvm::AMDGPU::isArgPassedInSGPR
bool isArgPassedInSGPR(const Argument *A)
Definition: AMDGPUBaseInfo.cpp:1749
llvm::AMDGPU::Waitcnt
Represents the counter values to wait for in an s_waitcnt instruction.
Definition: AMDGPUBaseInfo.h:461
llvm::AMDGPU::IsaInfo::TRAP_NUM_SGPRS
@ TRAP_NUM_SGPRS
Definition: AMDGPUBaseInfo.h:75
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
amd_kernel_code_t::private_segment_alignment
uint8_t private_segment_alignment
Definition: AMDKernelCodeT.h:636
llvm::AMDGPU::SIModeRegisterDefaults::SIModeRegisterDefaults
SIModeRegisterDefaults()
Definition: AMDGPUBaseInfo.h:906
llvm::AMDGPU::getMUBUFHasVAddr
bool getMUBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:245
llvm::AMDGPU::isInlinableLiteral64
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
Definition: AMDGPUBaseInfo.cpp:1648
llvm::AMDGPU::OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:144
uint16_t
llvm::AMDGPU::getMIMGBaseOpcode
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:145
llvm::AMDGPU::getMUBUFElements
int getMUBUFElements(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:240
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_DEFAULT
@ DFMT_NFMT_DEFAULT
Definition: SIDefines.h:484
llvm::AMDGPU::SendMsg::getMsgOpId
int64_t getMsgOpId(int64_t MsgId, const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1221
llvm::AMDGPU::Exp::ET_POS4
@ ET_POS4
Definition: SIDefines.h:739
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::FPOpFusion::Strict
@ Strict
Definition: TargetOptions.h:39
amd_kernel_code_t::code_properties
uint32_t code_properties
Code properties.
Definition: AMDKernelCodeT.h:562
llvm::AMDGPU::SendMsg::ID_GET_DDID
@ ID_GET_DDID
Definition: SIDefines.h:305
llvm::AMDGPU::isFoldableLiteralV216
bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:1736
llvm::AMDGPUAS::LOCAL_ADDRESS
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:377
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:156
llvm::AMDGPU::MIMGInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.h:351
Function.h
llvm::AMDGPU::MUBUFInfo::has_vaddr
bool has_vaddr
Definition: AMDGPUBaseInfo.cpp:162
llvm::AMDGPU::OPERAND_REG_INLINE_C_FIRST
@ OPERAND_REG_INLINE_C_FIRST
Definition: SIDefines.h:174
llvm::amdhsa::kernel_descriptor_t
Definition: AMDHSAKernelDescriptor.h:165
llvm::AMDGPU::getVOP1IsSingle
bool getVOP1IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:265
llvm::AMDGPU::SendMsg::ID_UNKNOWN_
@ ID_UNKNOWN_
Definition: SIDefines.h:294
llvm::AMDGPU::splitMUBUFOffset
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, Align Alignment)
Definition: AMDGPUBaseInfo.cpp:1852
llvm::AMDGPU::SendMsg::STREAM_ID_NONE_
@ STREAM_ID_NONE_
Definition: SIDefines.h:338
llvm::AMDGPU::MIMGInfo
Definition: AMDGPUBaseInfo.h:350
llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
Definition: AMDGPUBaseInfo.cpp:1137
llvm::AMDGPU::Exp::getTgtId
unsigned getTgtId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1052
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicSICI
const StringLiteral NfmtSymbolicSICI[]
Definition: AMDGPUAsmUtils.cpp:125
llvm::AMDGPU::MTBUFFormat::NFMT_SHIFT
@ NFMT_SHIFT
Definition: SIDefines.h:478
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:158
llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:694
llvm::AMDGPU::SendMsg::decodeMsg
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId)
Definition: AMDGPUBaseInfo.cpp:1286
llvm::AMDGPU::SendMsg::isValidMsgStream
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1258
llvm::AMDGPU::MTBUFFormat::getNfmtName
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1117
AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32
@ AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32
Definition: AMDKernelCodeT.h:127
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_
@ ID_SYMBOLIC_FIRST_
Definition: SIDefines.h:353
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc1
uint32_t compute_pgm_rsrc1
Definition: AMDHSAKernelDescriptor.h:173
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:403
llvm::AMDGPU::SendMsg::STREAM_ID_SHIFT_
@ STREAM_ID_SHIFT_
Definition: SIDefines.h:342
llvm::AMDGPU::getLgkmcntBitMask
unsigned getLgkmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:871
llvm::GlobalValue::getAddressSpace
unsigned getAddressSpace() const
Definition: Globals.cpp:112
llvm::GCNSubtarget::getGeneration
Generation getGeneration() const
Definition: GCNSubtarget.h:265
llvm::AMDGPU::Hwreg::WIDTH_M1_MASK_
@ WIDTH_M1_MASK_
Definition: SIDefines.h:396
llvm::AMDGPU::isInlinableLiteral32
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:1665
llvm::AMDGPU::isSISrcFPOperand
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
Definition: AMDGPUBaseInfo.cpp:1517
llvm::FeatureBitset::test
constexpr bool test(unsigned I) const
Definition: SubtargetFeature.h:90
llvm::AMDGPU::encodeExpcnt
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
Definition: AMDGPUBaseInfo.cpp:935
llvm::AMDGPU::isRegIntersect
bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
Is there any intersection between registers.
Definition: AMDGPUBaseInfo.cpp:1435
llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName
StringRef getUnifiedFormatName(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1150
llvm::AMDGPU::Exp::ET_POS_MAX_IDX
@ ET_POS_MAX_IDX
Definition: SIDefines.h:749
llvm::AMDGPU::isGCN3Encoding
bool isGCN3Encoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1412
llvm::AMDGPU::MTBUFFormat::getNfmt
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1108
llvm::AMDGPU::Exp::ExpTgt
Definition: AMDGPUBaseInfo.cpp:1026
llvm::AMDGPU::Exp::ET_PRIM_MAX_IDX
@ ET_PRIM_MAX_IDX
Definition: SIDefines.h:747
llvm::AMDGPU::getNumFlatOffsetBits
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed)
For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
Definition: AMDGPUBaseInfo.cpp:1837
N
#define N
AMDKernelCodeT.h
llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:537
llvm::AMDGPU::IsaInfo::getMaxWavesPerEU
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:528
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
llvm::AMDGPU::IsaInfo::getMinNumVGPRs
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:700
llvm::AMDGPU::Hwreg::getHwregId
int64_t getHwregId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:965
llvm::AMDGPU::hasMIMG_R128
bool hasMIMG_R128(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1370
llvm::AMDGPU::Exp::ET_NULL_MAX_IDX
@ ET_NULL_MAX_IDX
Definition: SIDefines.h:745
llvm::DenormalMode::Output
DenormalModeKind Output
Denormal flushing mode for floating point instruction results in the default floating point environme...
Definition: FloatingPointMode.h:85
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:152
llvm::CallingConv::AMDGPU_ES
@ AMDGPU_ES
Calling convention used for AMDPAL shader stage before geometry shader if geometry is in use.
Definition: CallingConv.h:231
llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumVGPRs
constexpr char NumVGPRs[]
Key for Kernel::CodeProps::Metadata::mNumVGPRs.
Definition: AMDGPUMetadata.h:255
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setTargetIDFromFeaturesString
void setTargetIDFromFeaturesString(StringRef FS)
Definition: AMDGPUBaseInfo.cpp:298
llvm::AMDGPU::isReadOnlySegment
bool isReadOnlySegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:808
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_LAST_
@ ID_SYMBOLIC_LAST_
Definition: SIDefines.h:374
llvm::AMDGPU::SendMsg::OP_NONE_
@ OP_NONE_
Definition: SIDefines.h:317
llvm::AMDGPU::isLegalSMRDEncodedSignedOffset
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
Definition: AMDGPUBaseInfo.cpp:1790
llvm::AMDGPU::OPERAND_REG_IMM_FP16
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:142
S_00B848_WGP_MODE
#define S_00B848_WGP_MODE(x)
Definition: SIDefines.h:867
LLVMContext.h
llvm::AMDGPUAS::CONSTANT_ADDRESS
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:376
llvm::AMDGPU::encodeLgkmcnt
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
Definition: AMDGPUBaseInfo.cpp:940
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:205
llvm::cl::desc
Definition: CommandLine.h:411
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:166
llvm::AMDGPU::MTBUFFormat::getDfmt
int64_t getDfmt(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1087
llvm::CallingConv::AMDGPU_VS
@ AMDGPU_VS
Calling convention used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (ve...
Definition: CallingConv.h:199
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:221
llvm::AMDGPU::isHsaAbiVersion3Or4
bool isHsaAbiVersion3Or4(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:126
llvm::AMDGPU::Waitcnt::ExpCnt
unsigned ExpCnt
Definition: AMDGPUBaseInfo.h:463
llvm::AMDGPU::getIntegerPairAttribute
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
Definition: AMDGPUBaseInfo.cpp:833
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isSramEccSupported
bool isSramEccSupported() const
Definition: AMDGPUBaseInfo.h:125
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:160
llvm::AMDGPU::MTBUFInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:168
llvm::AMDGPU::MTBUFInfo::has_srsrc
bool has_srsrc
Definition: AMDGPUBaseInfo.cpp:172
llvm::AMDGPU::SendMsg::isValidMsgId
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1193
llvm::AMDGPU::SendMsg::OP_MASK_
@ OP_MASK_
Definition: SIDefines.h:320
llvm::AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
Definition: AMDGPUBaseInfo.h:74
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::AMDGPU::MUBUFInfo
Definition: AMDGPUBaseInfo.cpp:158
llvm::AMDGPU::Exp::ET_MRT_MAX_IDX
@ ET_MRT_MAX_IDX
Definition: SIDefines.h:748
llvm::AMDGPU::SendMsg::ID_HALT_WAVES
@ ID_HALT_WAVES
Definition: SIDefines.h:300
llvm::CallingConv::AMDGPU_CS
@ AMDGPU_CS
Calling convention used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:208
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_GFX10_
@ ID_SYMBOLIC_FIRST_GFX10_
Definition: SIDefines.h:364
llvm::AMDGPU::IsaInfo::getVGPRAllocGranule
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:659
llvm::AMDGPU::getMaskedMIMGOp
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
Definition: AMDGPUBaseInfo.cpp:150
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
llvm::AMDGPU::getMTBUFElements
int getMTBUFElements(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:210
llvm::AMDGPU::OPERAND_REG_INLINE_C_LAST
@ OPERAND_REG_INLINE_C_LAST
Definition: SIDefines.h:175
AMDGPUBaseInfo.h
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:167
llvm::AMDGPU::MTBUFFormat::DFMT_MAX
@ DFMT_MAX
Definition: SIDefines.h:452