46#include "llvm/IR/IntrinsicsAMDGPU.h"
99static SGPRRegisterRegAlloc
100defaultSGPRRegAlloc(
"default",
101 "pick SGPR register allocator based on -O option",
104static cl::opt<SGPRRegisterRegAlloc::FunctionPassCtor,
false,
107 cl::desc(
"Register allocator to use for SGPRs"));
109static cl::opt<VGPRRegisterRegAlloc::FunctionPassCtor,
false,
112 cl::desc(
"Register allocator to use for VGPRs"));
115static void initializeDefaultSGPRRegisterAllocatorOnce() {
120 SGPRRegisterRegAlloc::setDefault(SGPRRegAlloc);
124static void initializeDefaultVGPRRegisterAllocatorOnce() {
129 VGPRRegisterRegAlloc::setDefault(VGPRRegAlloc);
133static FunctionPass *createBasicSGPRRegisterAllocator() {
137static FunctionPass *createGreedySGPRRegisterAllocator() {
145static FunctionPass *createBasicVGPRRegisterAllocator() {
149static FunctionPass *createGreedyVGPRRegisterAllocator() {
157static SGPRRegisterRegAlloc basicRegAllocSGPR(
158 "basic",
"basic register allocator", createBasicSGPRRegisterAllocator);
159static SGPRRegisterRegAlloc greedyRegAllocSGPR(
160 "greedy",
"greedy register allocator", createGreedySGPRRegisterAllocator);
162static SGPRRegisterRegAlloc fastRegAllocSGPR(
163 "fast",
"fast register allocator", createFastSGPRRegisterAllocator);
166static VGPRRegisterRegAlloc basicRegAllocVGPR(
167 "basic",
"basic register allocator", createBasicVGPRRegisterAllocator);
168static VGPRRegisterRegAlloc greedyRegAllocVGPR(
169 "greedy",
"greedy register allocator", createGreedyVGPRRegisterAllocator);
171static VGPRRegisterRegAlloc fastRegAllocVGPR(
172 "fast",
"fast register allocator", createFastVGPRRegisterAllocator);
177 cl::desc(
"Run SROA after promote alloca pass"),
183 cl::desc(
"Run early if-conversion"),
188 cl::desc(
"Run pre-RA exec mask optimizations"),
193 "amdgpu-load-store-vectorizer",
194 cl::desc(
"Enable load store vectorizer"),
200 "amdgpu-scalarize-global-loads",
201 cl::desc(
"Enable global load scalarization"),
207 "amdgpu-internalize-symbols",
208 cl::desc(
"Enable elimination of non-kernel functions and unused globals"),
214 "amdgpu-early-inline-all",
215 cl::desc(
"Inline all functions early"),
220 "amdgpu-enable-remove-incompatible-functions",
cl::Hidden,
221 cl::desc(
"Enable removal of functions when they"
222 "use features not supported by the target GPU"),
226 "amdgpu-sdwa-peephole",
231 "amdgpu-dpp-combine",
237 cl::desc(
"Enable AMDGPU Alias Analysis"),
242 "amdgpu-late-structurize",
243 cl::desc(
"Enable late CFG structurization"),
249 "amdgpu-simplify-libcall",
250 cl::desc(
"Enable amdgpu library simplifications"),
255 "amdgpu-ir-lower-kernel-arguments",
256 cl::desc(
"Lower kernel argument loads in IR pass"),
261 "amdgpu-reassign-regs",
262 cl::desc(
"Enable register reassign optimizations on gfx10+"),
267 "amdgpu-opt-vgpr-liverange",
268 cl::desc(
"Enable VGPR liverange optimizations for if-else structure"),
273 "amdgpu-atomic-optimizations",
274 cl::desc(
"Enable atomic optimizations"),
280 "amdgpu-mode-register",
281 cl::desc(
"Enable mode register pass"),
288 cl::desc(
"Enable s_delay_alu insertion"),
294 cl::desc(
"Enable VOPD, dual issue of VALU in wave32"),
301 cl::desc(
"Enable machine DCE inside regalloc"));
308 "amdgpu-scalar-ir-passes",
309 cl::desc(
"Enable scalar IR passes"),
314 "amdgpu-enable-structurizer-workarounds",
319 "amdgpu-enable-lds-replace-with-pointer",
324 "amdgpu-enable-lower-module-lds",
cl::desc(
"Enable lower module lds pass"),
329 "amdgpu-enable-pre-ra-optimizations",
334 "amdgpu-enable-promote-kernel-arguments",
335 cl::desc(
"Enable promotion of flat kernel pointer arguments to global"),
339 "amdgpu-enable-max-ilp-scheduling-strategy",
340 cl::desc(
"Enable scheduling strategy to maximize ILP for a single wave."),
423 return std::make_unique<AMDGPUTargetObjectFile>();
436 if (ST.shouldClusterStores())
458 if (ST.shouldClusterStores())
474 if (ST.shouldClusterStores())
486 "Run GCN scheduler to maximize occupancy",
494 "gcn-iterative-max-occupancy-experimental",
495 "Run GCN scheduler to maximize occupancy (experimental)",
499 "gcn-iterative-minreg",
500 "Run GCN iterative scheduler for minimal register usage (experimental)",
505 "Run GCN iterative scheduler for ILP scheduling (experimental)",
511 return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
512 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
517 return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
518 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
519 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
544 std::optional<Reloc::Model> RM,
545 std::optional<CodeModel::Model> CM,
567 Attribute GPUAttr =
F.getFnAttribute(
"target-cpu");
572 Attribute FSAttr =
F.getFnAttribute(
"target-features");
580 if (
const Function *
F = dyn_cast<Function>(&GV))
581 return F->isDeclaration() ||
F->getName().startswith(
"__asan_") ||
582 F->getName().startswith(
"__sanitizer_") ||
597 if (
PassName ==
"amdgpu-propagate-attributes-late") {
601 if (
PassName ==
"amdgpu-unify-metadata") {
605 if (
PassName ==
"amdgpu-printf-runtime-binding") {
609 if (
PassName ==
"amdgpu-always-inline") {
613 if (
PassName ==
"amdgpu-replace-lds-use-with-pointer") {
617 if (
PassName ==
"amdgpu-lower-module-lds") {
621 if (
PassName ==
"amdgpu-lower-ctor-dtor") {
630 if (
PassName ==
"amdgpu-simplifylib") {
634 if (
PassName ==
"amdgpu-usenative") {
638 if (
PassName ==
"amdgpu-promote-alloca") {
642 if (
PassName ==
"amdgpu-promote-alloca-to-vector") {
646 if (
PassName ==
"amdgpu-lower-kernel-attributes") {
650 if (
PassName ==
"amdgpu-propagate-attributes-early") {
654 if (
PassName ==
"amdgpu-promote-kernel-arguments") {
666 if (AAName ==
"amdgpu-aa") {
744 unsigned DestAS)
const {
750 const auto *LD = dyn_cast<LoadInst>(V);
755 assert(V->getType()->isPointerTy() &&
758 const auto *
Ptr = LD->getPointerOperand();
768std::pair<const Value *, unsigned>
770 if (
auto *II = dyn_cast<IntrinsicInst>(V)) {
771 switch (II->getIntrinsicID()) {
772 case Intrinsic::amdgcn_is_shared:
774 case Intrinsic::amdgcn_is_private:
779 return std::pair(
nullptr, -1);
786 const_cast<Value *
>(V),
788 m_Not(m_Intrinsic<Intrinsic::amdgcn_is_private>(
792 return std::pair(
nullptr, -1);
818 std::optional<Reloc::Model> RM,
819 std::optional<CodeModel::Model> CM,
831 auto &
I = SubtargetMap[SubtargetKey];
837 I = std::make_unique<GCNSubtarget>(
TargetTriple, GPU, FS, *
this);
867 setRequiresCodeGenSCCOrder(
true);
872 return getTM<GCNTargetMachine>();
881 C, std::make_unique<PostGenericScheduler>(
C),
885 if (
ST.shouldClusterStores())
894 bool addPreISel()
override;
895 void addMachineSSAOptimization()
override;
896 bool addILPOpts()
override;
897 bool addInstSelector()
override;
898 bool addIRTranslator()
override;
899 void addPreLegalizeMachineIR()
override;
900 bool addLegalizeMachineIR()
override;
901 void addPreRegBankSelect()
override;
902 bool addRegBankSelect()
override;
903 void addPreGlobalInstructionSelect()
override;
904 bool addGlobalInstructionSelect()
override;
905 void addFastRegAlloc()
override;
906 void addOptimizedRegAlloc()
override;
910 FunctionPass *createRegAllocPass(
bool Optimized)
override;
912 bool addRegAssignAndRewriteFast()
override;
913 bool addRegAssignAndRewriteOptimized()
override;
915 void addPreRegAlloc()
override;
916 bool addPreRewrite()
override;
917 void addPostRegAlloc()
override;
918 void addPreSched2()
override;
919 void addPreEmitPass()
override;
1097 if (ST.shouldClusterStores())
1105 return R600MachineFunctionInfo::create<R600MachineFunctionInfo>(
1116 if (ST.enableSIScheduler())
1125bool GCNPassConfig::addPreISel() {
1164void GCNPassConfig::addMachineSSAOptimization() {
1188bool GCNPassConfig::addILPOpts() {
1196bool GCNPassConfig::addInstSelector() {
1203bool GCNPassConfig::addIRTranslator() {
1208void GCNPassConfig::addPreLegalizeMachineIR() {
1214bool GCNPassConfig::addLegalizeMachineIR() {
1219void GCNPassConfig::addPreRegBankSelect() {
1224bool GCNPassConfig::addRegBankSelect() {
1229void GCNPassConfig::addPreGlobalInstructionSelect() {
1234bool GCNPassConfig::addGlobalInstructionSelect() {
1239void GCNPassConfig::addPreRegAlloc() {
1245void GCNPassConfig::addFastRegAlloc() {
1260void GCNPassConfig::addOptimizedRegAlloc() {
1294bool GCNPassConfig::addPreRewrite() {
1300FunctionPass *GCNPassConfig::createSGPRAllocPass(
bool Optimized) {
1303 initializeDefaultSGPRRegisterAllocatorOnce);
1315FunctionPass *GCNPassConfig::createVGPRAllocPass(
bool Optimized) {
1318 initializeDefaultVGPRRegisterAllocatorOnce);
1325 return createGreedyVGPRRegisterAllocator();
1327 return createFastVGPRRegisterAllocator();
1330FunctionPass *GCNPassConfig::createRegAllocPass(
bool Optimized) {
1335 "-regalloc not supported with amdgcn. Use -sgpr-regalloc and -vgpr-regalloc";
1337bool GCNPassConfig::addRegAssignAndRewriteFast() {
1338 if (!usingDefaultRegAlloc())
1341 addPass(createSGPRAllocPass(
false));
1346 addPass(createVGPRAllocPass(
false));
1350bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
1351 if (!usingDefaultRegAlloc())
1354 addPass(createSGPRAllocPass(
true));
1365 addPass(createVGPRAllocPass(
true));
1373void GCNPassConfig::addPostRegAlloc() {
1380void GCNPassConfig::addPreSched2() {
1386void GCNPassConfig::addPreEmitPass() {
1422 return new GCNPassConfig(*
this, PM);
1428 return SIMachineFunctionInfo::create<SIMachineFunctionInfo>(
1454 if (MFI->Occupancy == 0) {
1463 SourceRange =
RegName.SourceRange;
1476 if (parseOptionalRegister(YamlMFI.
VGPRForAGPRCopy, MFI->VGPRForAGPRCopy))
1485 "incorrect register class for field",
RegName.Value,
1486 std::nullopt, std::nullopt);
1487 SourceRange =
RegName.SourceRange;
1491 if (parseRegister(YamlMFI.
ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1496 if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1497 !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1501 if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1502 !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1506 if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1507 !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1513 if (parseRegister(YamlReg, ParsedReg))
1519 auto parseAndCheckArgument = [&](
const std::optional<yaml::SIArgument> &
A,
1522 unsigned SystemSGPRs) {
1527 if (
A->IsRegister) {
1530 SourceRange =
A->RegisterName.SourceRange;
1533 if (!RC.contains(Reg))
1534 return diagnoseRegisterClass(
A->RegisterName);
1542 MFI->NumUserSGPRs += UserSGPRs;
1543 MFI->NumSystemSGPRs += SystemSGPRs;
1548 (parseAndCheckArgument(YamlMFI.
ArgInfo->PrivateSegmentBuffer,
1549 AMDGPU::SGPR_128RegClass,
1551 parseAndCheckArgument(YamlMFI.
ArgInfo->DispatchPtr,
1552 AMDGPU::SReg_64RegClass, MFI->ArgInfo.
DispatchPtr,
1554 parseAndCheckArgument(YamlMFI.
ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1556 parseAndCheckArgument(YamlMFI.
ArgInfo->KernargSegmentPtr,
1557 AMDGPU::SReg_64RegClass,
1559 parseAndCheckArgument(YamlMFI.
ArgInfo->DispatchID,
1560 AMDGPU::SReg_64RegClass, MFI->ArgInfo.
DispatchID,
1562 parseAndCheckArgument(YamlMFI.
ArgInfo->FlatScratchInit,
1563 AMDGPU::SReg_64RegClass,
1565 parseAndCheckArgument(YamlMFI.
ArgInfo->PrivateSegmentSize,
1566 AMDGPU::SGPR_32RegClass,
1568 parseAndCheckArgument(YamlMFI.
ArgInfo->LDSKernelId,
1569 AMDGPU::SGPR_32RegClass,
1571 parseAndCheckArgument(YamlMFI.
ArgInfo->WorkGroupIDX,
1574 parseAndCheckArgument(YamlMFI.
ArgInfo->WorkGroupIDY,
1577 parseAndCheckArgument(YamlMFI.
ArgInfo->WorkGroupIDZ,
1580 parseAndCheckArgument(YamlMFI.
ArgInfo->WorkGroupInfo,
1581 AMDGPU::SGPR_32RegClass,
1583 parseAndCheckArgument(YamlMFI.
ArgInfo->PrivateSegmentWaveByteOffset,
1584 AMDGPU::SGPR_32RegClass,
1586 parseAndCheckArgument(YamlMFI.
ArgInfo->ImplicitArgPtr,
1587 AMDGPU::SReg_64RegClass,
1589 parseAndCheckArgument(YamlMFI.
ArgInfo->ImplicitBufferPtr,
1590 AMDGPU::SReg_64RegClass,
1592 parseAndCheckArgument(YamlMFI.
ArgInfo->WorkItemIDX,
1593 AMDGPU::VGPR_32RegClass,
1595 parseAndCheckArgument(YamlMFI.
ArgInfo->WorkItemIDY,
1596 AMDGPU::VGPR_32RegClass,
1598 parseAndCheckArgument(YamlMFI.
ArgInfo->WorkItemIDZ,
1599 AMDGPU::VGPR_32RegClass,
static cl::opt< bool > EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(true))
This is the AMGPU address space based alias analysis pass.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static cl::opt< bool > EnableDCEInRA("amdgpu-dce-in-ra", cl::init(true), cl::Hidden, cl::desc("Enable machine DCE inside regalloc"))
static cl::opt< bool, true > EnableLowerModuleLDS("amdgpu-enable-lower-module-lds", cl::desc("Enable lower module lds pass"), cl::location(AMDGPUTargetMachine::EnableLowerModuleLDS), cl::init(true), cl::Hidden)
static MachineSchedRegistry SISchedRegistry("si", "Run SI's custom scheduler", createSIMachineScheduler)
static ScheduleDAGInstrs * createIterativeILPMachineScheduler(MachineSchedContext *C)
static cl::opt< bool > EarlyInlineAll("amdgpu-early-inline-all", cl::desc("Inline all functions early"), cl::init(false), cl::Hidden)
static cl::opt< bool > EnableLowerKernelArguments("amdgpu-ir-lower-kernel-arguments", cl::desc("Lower kernel argument loads in IR pass"), cl::init(true), cl::Hidden)
static ScheduleDAGInstrs * createGCNMaxILPMachineScheduler(MachineSchedContext *C)
static cl::opt< bool > EnableSDWAPeephole("amdgpu-sdwa-peephole", cl::desc("Enable SDWA peepholer"), cl::init(true))
static MachineSchedRegistry GCNMinRegSchedRegistry("gcn-iterative-minreg", "Run GCN iterative scheduler for minimal register usage (experimental)", createMinRegScheduler)
static cl::opt< bool > EnableSIModeRegisterPass("amdgpu-mode-register", cl::desc("Enable mode register pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableDPPCombine("amdgpu-dpp-combine", cl::desc("Enable DPP combiner"), cl::init(true))
static MachineSchedRegistry IterativeGCNMaxOccupancySchedRegistry("gcn-iterative-max-occupancy-experimental", "Run GCN scheduler to maximize occupancy (experimental)", createIterativeGCNMaxOccupancyMachineScheduler)
static cl::opt< bool > EnableSetWavePriority("amdgpu-set-wave-priority", cl::desc("Adjust wave priority"), cl::init(false), cl::Hidden)
static cl::opt< bool > EnableLDSReplaceWithPointer("amdgpu-enable-lds-replace-with-pointer", cl::desc("Enable LDS replace with pointer pass"), cl::init(false), cl::Hidden)
static cl::opt< bool > OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden, cl::desc("Run pre-RA exec mask optimizations"), cl::init(true))
static cl::opt< bool > EnablePromoteKernelArguments("amdgpu-enable-promote-kernel-arguments", cl::desc("Enable promotion of flat kernel pointer arguments to global"), cl::Hidden, cl::init(true))
static cl::opt< bool > EnableLibCallSimplify("amdgpu-simplify-libcall", cl::desc("Enable amdgpu library simplifications"), cl::init(true), cl::Hidden)
static MachineSchedRegistry GCNMaxILPSchedRegistry("gcn-max-ilp", "Run GCN scheduler to maximize ilp", createGCNMaxILPMachineScheduler)
static cl::opt< bool > InternalizeSymbols("amdgpu-internalize-symbols", cl::desc("Enable elimination of non-kernel functions and unused globals"), cl::init(false), cl::Hidden)
static cl::opt< bool > EnableAtomicOptimizations("amdgpu-atomic-optimizations", cl::desc("Enable atomic optimizations"), cl::init(false), cl::Hidden)
static LLVM_READNONE StringRef getGPUOrDefault(const Triple &TT, StringRef GPU)
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
static cl::opt< bool > EnableStructurizerWorkarounds("amdgpu-enable-structurizer-workarounds", cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden, cl::desc("Enable AMDGPU Alias Analysis"), cl::init(true))
static ScheduleDAGInstrs * createMinRegScheduler(MachineSchedContext *C)
static cl::opt< bool, true > LateCFGStructurize("amdgpu-late-structurize", cl::desc("Enable late CFG structurization"), cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG), cl::Hidden)
static cl::opt< bool > EnableInsertDelayAlu("amdgpu-enable-delay-alu", cl::desc("Enable s_delay_alu insertion"), cl::init(true), cl::Hidden)
static ScheduleDAGInstrs * createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C)
static cl::opt< bool > EnableLoadStoreVectorizer("amdgpu-load-store-vectorizer", cl::desc("Enable load store vectorizer"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableMaxIlpSchedStrategy("amdgpu-enable-max-ilp-scheduling-strategy", cl::desc("Enable scheduling strategy to maximize ILP for a single wave."), cl::Hidden, cl::init(false))
static bool mustPreserveGV(const GlobalValue &GV)
Predicate for Internalize pass.
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget()
static cl::opt< bool > EnableSROA("amdgpu-sroa", cl::desc("Run SROA after promote alloca pass"), cl::ReallyHidden, cl::init(true))
static cl::opt< bool > RemoveIncompatibleFunctions("amdgpu-enable-remove-incompatible-functions", cl::Hidden, cl::desc("Enable removal of functions when they" "use features not supported by the target GPU"), cl::init(true))
static cl::opt< bool > EnableScalarIRPasses("amdgpu-scalar-ir-passes", cl::desc("Enable scalar IR passes"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableRegReassign("amdgpu-reassign-regs", cl::desc("Enable register reassign optimizations on gfx10+"), cl::init(true), cl::Hidden)
static cl::opt< bool > OptVGPRLiveRange("amdgpu-opt-vgpr-liverange", cl::desc("Enable VGPR liverange optimizations for if-else structure"), cl::init(true), cl::Hidden)
static ScheduleDAGInstrs * createSIMachineScheduler(MachineSchedContext *C)
static cl::opt< bool > EnablePreRAOptimizations("amdgpu-enable-pre-ra-optimizations", cl::desc("Enable Pre-RA optimizations pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableVOPD("amdgpu-enable-vopd", cl::desc("Enable VOPD, dual issue of VALU in wave32"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(false))
static ScheduleDAGInstrs * createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C)
static MachineSchedRegistry GCNILPSchedRegistry("gcn-iterative-ilp", "Run GCN iterative scheduler for ILP scheduling (experimental)", createIterativeILPMachineScheduler)
static cl::opt< bool > ScalarizeGlobal("amdgpu-scalarize-global-loads", cl::desc("Enable global load scalarization"), cl::init(true), cl::Hidden)
static const char RegAllocOptNotSupportedMessage[]
static MachineSchedRegistry GCNMaxOccupancySchedRegistry("gcn-max-occupancy", "Run GCN scheduler to maximize occupancy", createGCNMaxOccupancyMachineScheduler)
The AMDGPU TargetMachine interface definition for hw codegen targets.
This file declares the AMDGPU-specific subclass of TargetLoweringObjectFile.
Provides passes to inlining "always_inline" functions.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
This header provides classes for managing passes over SCCs of the call graph.
Provides analysis for continuously CSEing during GISel passes.
#define LLVM_EXTERNAL_VISIBILITY
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file defines the class GCNIterativeScheduler, which uses an iterative approach to find a best sc...
This file provides the interface for LLVM's Global Value Numbering pass which eliminates fully redund...
This file declares the IRTranslator pass.
static std::string computeDataLayout()
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
FunctionAnalysisManager FAM
const char LLVMTargetMachineRef TM
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
This header defines various interfaces for pass management in LLVM.
The AMDGPU TargetMachine interface definition for hw codegen targets.
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI Machine Scheduler interface.
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Target-Independent Code Generator Pass Configuration Options pass.
static std::unique_ptr< TargetLoweringObjectFile > createTLOF()
static const char PassName[]
A manager for alias analyses.
void registerFunctionAnalysis()
Register a specific AA result.
void addAAResult(AAResultT &AAResult)
Register a specific AA result.
Legacy wrapper pass to provide the AMDGPUAAResult object.
Analysis pass providing a never-invalidated alias analysis result.
Lower llvm.global_ctors and llvm.global_dtors to special kernels.
uint32_t getLDSSize() const
AMDGPUTargetMachine & getAMDGPUTargetMachine() const
std::unique_ptr< CSEConfigBase > getCSEConfig() const override
Returns the CSEConfig object to use for the current optimization level.
ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const override
Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this ...
bool addPreISel() override
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
bool isPassEnabled(const cl::opt< bool > &Opt, CodeGenOpt::Level Level=CodeGenOpt::Default) const
Check if a pass is enabled given Opt option.
bool addInstSelector() override
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
bool addGCPasses() override
addGCPasses - Add late codegen passes that analyze code for garbage collection.
void addStraightLineScalarOptimizationPasses()
AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
void addIRPasses() override
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
void addEarlyCSEOrGVNPass()
void addCodeGenPrepare() override
Add pass to prepare the LLVM IR for code generation.
static int64_t getNullPointerValue(unsigned AddrSpace)
Get the integer value of a null pointer in the given address space.
unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override
getAddressSpaceForPseudoSourceKind - Given the kind of memory (e.g.
const TargetSubtargetInfo * getSubtargetImpl() const
void registerDefaultAliasAnalyses(AAManager &) override
Allow the target to register alias analyses with the AAManager for use with the new pass manager.
~AMDGPUTargetMachine() override
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const override
If the specified predicate checks whether a generic pointer falls within a specified address space,...
StringRef getFeatureString(const Function &F) const
static bool EnableLateStructurizeCFG
static bool EnableFunctionCalls
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
void registerPassBuilderCallbacks(PassBuilder &PB) override
Allow the target to modify the pass pipeline.
static bool EnableLowerModuleLDS
AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL)
StringRef getGPUName(const Function &F) const
unsigned getAssumedAddrSpace(const Value *V) const override
If the specified generic pointer could be assumed as a pointer to a specific address space,...
A container for analyses that lazily runs them and caches their results.
bool registerPass(PassBuilderT &&PassBuilder)
Register an analysis pass with the manager.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
StringRef getValueAsString() const
Return the attribute's value as a string.
bool isValid() const
Return true if the attribute is any kind of attribute.
Allocate memory in an ever growing pool, as if by bump-pointer.
void removeDeadConstantUsers() const
If there are any dead constant users dangling off of this constant, remove them.
Lightweight error class with error context and mandatory checking.
FunctionPass class - This class is used to implement most global optimizations.
@ SCHEDULE_LEGACYMAXOCCUPANCY
const SIRegisterInfo * getRegisterInfo() const override
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
Pass to remove unused function declarations.
This pass is responsible for selecting generic machine instructions to target-specific instructions.
A pass that internalizes all functions and variables other than those that must be preserved accordin...
This class describes a target machine that is implemented with the LLVM target-independent code gener...
This pass implements the localization mechanism described at the top of this file.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineSchedRegistry provides a selection of available machine instruction schedulers.
This interface provides simple read-only access to a block of memory, and provides simple methods for...
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
static const OptimizationLevel O0
Disable as many optimizations as possible.
unsigned getSpeedupLevel() const
static const OptimizationLevel O1
Optimize quickly without destroying debuggability.
This class provides access to building LLVM's passes.
void registerPipelineEarlySimplificationEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
void registerPipelineStartEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
void registerParseAACallback(const std::function< bool(StringRef Name, AAManager &AA)> &C)
Register a callback for parsing an AliasAnalysis Name to populate the given AAManager AA.
void registerAnalysisRegistrationCallback(const std::function< void(CGSCCAnalysisManager &)> &C)
{{@ Register callbacks for analysis registration with this PassBuilder instance.
void registerCGSCCOptimizerLateEPCallback(const std::function< void(CGSCCPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
void registerPipelineParsingCallback(const std::function< bool(StringRef Name, CGSCCPassManager &, ArrayRef< PipelineElement >)> &C)
{{@ Register pipeline parsing callbacks with this pass builder instance.
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same< PassT, PassManager >::value > addPass(PassT &&Pass)
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
@ ExternalSymbolCallEntry
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
RegisterPassParser class - Handle the addition of new machine passes.
RegisterRegAllocBase class - Track the registration of register allocators.
FunctionPass *(*)() FunctionPassCtor
Wrapper class representing virtual and physical registers.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
void reserveWWMRegister(Register Reg)
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a location in source code.
Represents a range in source code.
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
const TargetInstrInfo * TII
Target instruction information.
const TargetRegisterInfo * TRI
Target processor register info.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
void append(StringRef RHS)
Append from a StringRef.
unsigned getMainFileID() const
const MemoryBuffer * getMemoryBuffer(unsigned i) const
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
const Triple & getTargetTriple() const
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
const MCSubtargetInfo * getMCSubtargetInfo() const
StringRef getTargetFeatureString() const
StringRef getTargetCPU() const
std::unique_ptr< const MCSubtargetInfo > STI
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
std::unique_ptr< const MCRegisterInfo > MRI
Target-Independent Code Generator Pass Configuration Options.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
CodeGenOpt::Level getOptLevel() const
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
void disablePass(AnalysisID PassID)
Allow the target to disable a specific standard pass by default.
AnalysisID addPass(AnalysisID PassID)
Utilities for targets to add passes to the pass manager.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
ArchType getArch() const
Get the parsed architecture type of this triple.
LLVM Value Representation.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Interfaces for registering analysis passes, producing common pass manager configurations,...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ REGION_ADDRESS
Address space for region memory. (GDS)
@ LOCAL_ADDRESS
Address space for local memory.
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
@ FLAT_ADDRESS
Address space for flat memory.
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
@ PRIVATE_ADDRESS
Address space for private memory.
bool isFlatGlobalAddrSpace(unsigned AS)
bool isEntryFunctionCC(CallingConv::ID CC)
@ C
The default llvm calling convention, compatible with C.
Level
Code generation optimization level.
BinaryOp_match< LHS, RHS, Instruction::And, true > m_c_And(const LHS &L, const RHS &R)
Matches an And with LHS and RHS in either order.
bool match(Val *V, const Pattern &P)
deferredval_ty< Value > m_Deferred(Value *const &V)
Like m_Specific(), but works if the specific value to match is determined as part of the same match()...
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
BinaryOp_match< cst_pred_ty< is_all_ones >, ValTy, Instruction::Xor, true > m_Not(const ValTy &V)
Matches a 'Not' as 'xor V, -1' or 'xor -1, V'.
initializer< Ty > init(const Ty &Val)
LocationClass< Ty > location(Ty &L)
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createFlattenCFGPass()
void initializeSIFormMemoryClausesPass(PassRegistry &)
char & SIPreAllocateWWMRegsID
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
ImmutablePass * createAMDGPUAAWrapperPass()
char & PostRAHazardRecognizerID
PostRAHazardRecognizer - This pass runs the post-ra hazard recognizer.
FunctionPass * createAMDGPUSetWavePriorityPass()
void initializeAMDGPUUseNativeCallsPass(PassRegistry &)
void initializeGCNCreateVOPDPass(PassRegistry &)
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
char & GCNPreRAOptimizationsID
char & GCLoweringID
GCLowering Pass - Used by gc.root to perform its default lowering operations.
void initializeGCNPreRAOptimizationsPass(PassRegistry &)
Pass * createLoadStoreVectorizerPass()
Create a legacy pass manager instance of the LoadStoreVectorizer pass.
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
FunctionPass * createSIModeRegisterPass()
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
void initializeR600ClauseMergePassPass(PassRegistry &)
void initializeSIModeRegisterPass(PassRegistry &)
ModulePass * createAMDGPUCtorDtorLoweringLegacyPass()
void initializeSIOptimizeVGPRLiveRangePass(PassRegistry &)
ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false)
A function to deduce a function pass type and wrap it in the templated adaptor.
void initializeAMDGPULateCodeGenPreparePass(PassRegistry &)
void initializeAMDGPUAttributorPass(PassRegistry &)
FunctionPass * createAMDGPUPreLegalizeCombiner(bool IsOptNone)
FunctionPass * createAMDGPUPostLegalizeCombiner(bool IsOptNone)
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
FunctionPass * createAMDGPUISelDag(TargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a AMDGPU-specific.
void initializeSIShrinkInstructionsPass(PassRegistry &)
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &)
char & SILoadStoreOptimizerID
FunctionPass * createNaryReassociatePass()
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &)
void initializeR600PacketizerPass(PassRegistry &)
char & AMDGPUReleaseVGPRsID
std::unique_ptr< ScheduleDAGMutation > createVOPDPairingMutation()
ModulePass * createAMDGPULowerIntrinsicsPass()
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
void initializeSIPreEmitPeepholePass(PassRegistry &)
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
void initializeSIFixVGPRCopiesPass(PassRegistry &)
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
Pass * createStructurizeCFGPass(bool SkipUniformRegions=false)
When SkipUniformRegions is true the structizer will not structurize regions that only contain uniform...
void initializeAMDGPURemoveIncompatibleFunctionsPass(PassRegistry &)
void initializeGCNNSAReassignPass(PassRegistry &)
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
void initializeSIInsertWaitcntsPass(PassRegistry &)
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
char & SIFormMemoryClausesID
void initializeAMDGPUCtorDtorLoweringLegacyPass(PassRegistry &)
void initializeAMDGPURegBankCombinerPass(PassRegistry &)
void initializeSILoadStoreOptimizerPass(PassRegistry &)
void initializeSILateBranchLoweringPass(PassRegistry &)
void initializeSIPeepholeSDWAPass(PassRegistry &)
char & AMDGPUUnifyDivergentExitNodesID
ModulePass * createAMDGPULowerModuleLDSPass()
char & ShadowStackGCLoweringID
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC.
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
char & AMDGPUPerfHintAnalysisID
char & SILowerSGPRSpillsID
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
char & SILateBranchLoweringPassID
void initializeAMDGPURewriteUndefForPHIPass(PassRegistry &)
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
FunctionPass * createSinkingPass()
CGSCCToFunctionPassAdaptor createCGSCCToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false, bool NoRerun=false)
A function to deduce a function pass type and wrap it in the templated adaptor.
std::unique_ptr< ScheduleDAGMutation > createIGroupLPDAGMutation()
FunctionPass * createSIShrinkInstructionsPass()
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
void initializeSIPostRABundlerPass(PassRegistry &)
FunctionPass * createAMDGPUAtomicOptimizerPass()
void initializeAMDGPUReplaceLDSUseWithPointerPass(PassRegistry &)
void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry &)
void initializeAMDGPULowerModuleLDSPass(PassRegistry &)
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
void initializeSIWholeQuadModePass(PassRegistry &)
FunctionPass * createAMDGPULowerKernelArgumentsPass()
char & AMDGPUInsertDelayAluID
Pass * createAMDGPUAnnotateKernelFeaturesPass()
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
std::unique_ptr< ScheduleDAGMutation > createAMDGPUMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAMDGPUMacroFusionDAGMutation()); to AMDGPUPassConfig...
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
char & SIOptimizeVGPRLiveRangeID
FunctionPass * createUnifyLoopExitsPass()
char & SIOptimizeExecMaskingPreRAID
FunctionPass * createFixIrreduciblePass()
FunctionPass * createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *)
char & FuncletLayoutID
This pass lays out funclets contiguously.
void initializeSIInsertHardClausesPass(PassRegistry &)
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &)
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &)
void initializeSIAnnotateControlFlowPass(PassRegistry &)
ModulePass * createAMDGPUPrintfRuntimeBinding()
void initializeSIMemoryLegalizerPass(PassRegistry &)
Pass * createAlwaysInlinerLegacyPass(bool InsertLifetime=true)
Create a legacy pass manager instance of a pass to inline and remove functions marked as "always_inli...
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
void initializeR600ControlFlowFinalizerPass(PassRegistry &)
ModulePass * createAMDGPUReplaceLDSUseWithPointerPass()
void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &)
FunctionPass * createAMDGPUAnnotateUniformValues()
void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &)
FunctionPass * createAMDGPUPromoteAlloca()
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
char & SIPreEmitPeepholeID
ModulePass * createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *)
FunctionPass * createSILowerI1CopiesPass()
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
FunctionPass * createBasicRegisterAllocator()
BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)
ModulePass * createR600OpenCLImageTypeLoweringPass()
FunctionPass * createAMDGPUCodeGenPreparePass()
Target & getTheGCNTarget()
The target for GCN GPUs.
void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &)
FunctionPass * createAMDGPURewriteUndefForPHIPass()
FunctionPass * createAMDGPURegBankCombiner(bool IsOptNone)
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
FunctionPass * createGVNPass(bool NoMemDepAnalysis=false)
Create a legacy GVN pass.
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
void initializeSILowerSGPRSpillsPass(PassRegistry &)
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
char & SIInsertHardClausesID
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &)
void initializeSIFixSGPRCopiesPass(PassRegistry &)
FunctionPass * createInferAddressSpacesPass(unsigned AddressSpace=~0u)
Pass * createAMDGPUAttributorPass()
char & VirtRegRewriterID
VirtRegRewriter pass.
void initializeSILowerI1CopiesPass(PassRegistry &)
char & SILowerControlFlowID
FunctionPass * createLowerSwitchPass()
FunctionPass * createVirtRegRewriter(bool ClearVirtRegs=true)
void initializeR600VectorRegMergerPass(PassRegistry &)
ImmutablePass * createExternalAAWrapperPass(std::function< void(Pass &, Function &, AAResults &)> Callback)
A wrapper pass around a callback which can be used to populate the AAResults in the AAResultsWrapperP...
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
FunctionPass * createSIMemoryLegalizerPass()
void initializeSIFoldOperandsPass(PassRegistry &)
void initializeSILowerControlFlowPass(PassRegistry &)
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
void initializeAMDGPUReleaseVGPRsPass(PassRegistry &)
void initializeAMDGPURegBankSelectPass(PassRegistry &)
MCRegisterInfo * createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour)
FunctionPass * createStraightLineStrengthReducePass()
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
FunctionPass * createSIInsertWaitcntsPass()
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
void initializeGCNDPPCombinePass(PassRegistry &)
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
FunctionPass * createAMDGPULateCodeGenPreparePass()
FunctionPass * createSROAPass(bool PreserveCFG=true)
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
std::unique_ptr< ScheduleDAGMutation > createAMDGPUExportClusteringDAGMutation()
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry &)
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
void initializeAMDGPUInsertDelayAluPass(PassRegistry &)
char & SIOptimizeExecMaskingID
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &)
ArgDescriptor PrivateSegmentBuffer
ArgDescriptor WorkGroupIDY
ArgDescriptor WorkGroupIDZ
ArgDescriptor PrivateSegmentSize
ArgDescriptor ImplicitArgPtr
ArgDescriptor PrivateSegmentWaveByteOffset
ArgDescriptor WorkGroupInfo
ArgDescriptor WorkItemIDZ
ArgDescriptor WorkItemIDY
ArgDescriptor LDSKernelId
ArgDescriptor KernargSegmentPtr
ArgDescriptor WorkItemIDX
ArgDescriptor FlatScratchInit
ArgDescriptor DispatchPtr
ArgDescriptor ImplicitBufferPtr
ArgDescriptor WorkGroupIDX
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
static constexpr ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask)
static constexpr ArgDescriptor createStack(unsigned Offset, unsigned Mask=~0u)
DenormalModeKind Input
Denormal treatment kind for floating point instruction inputs in the default floating-point environme...
@ PreserveSign
The sign of a flushed-to-zero number is preserved in the sign of 0.
@ IEEE
IEEE-754 denormal numbers preserved.
DenormalModeKind Output
Denormal flushing mode for floating point instruction results in the default floating point environme...
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
RegisterTargetMachine - Helper template for registering a target machine implementation,...
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
DenormalMode FP64FP16Denormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
DenormalMode FP32Denormals
If this is set, neither input or output denormals are flushed for most f32 instructions.
The llvm::once_flag structure.
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
SmallVector< StringValue > WWMReservedRegs
StringValue FrameOffsetReg
StringValue VGPRForAGPRCopy
std::optional< SIArgumentInfo > ArgInfo
StringValue ScratchRSrcReg
StringValue StackPtrOffsetReg
bool FP64FP16OutputDenormals
bool FP64FP16InputDenormals
A wrapper around std::string which contains a source range that's being set during parsing.