LLVM  15.0.0git
AMDGPUTargetMachine.cpp
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1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information needed to emit code for SI+ GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMFMAClustering.h"
20 #include "AMDGPUMacroFusion.h"
21 #include "AMDGPUTargetObjectFile.h"
23 #include "GCNIterativeScheduler.h"
24 #include "GCNSchedStrategy.h"
25 #include "R600.h"
26 #include "R600TargetMachine.h"
27 #include "SIMachineFunctionInfo.h"
28 #include "SIMachineScheduler.h"
38 #include "llvm/CodeGen/Passes.h"
41 #include "llvm/IR/IntrinsicsAMDGPU.h"
43 #include "llvm/IR/PassManager.h"
44 #include "llvm/IR/PatternMatch.h"
45 #include "llvm/InitializePasses.h"
46 #include "llvm/MC/TargetRegistry.h"
48 #include "llvm/Transforms/IPO.h"
53 #include "llvm/Transforms/Scalar.h"
56 #include "llvm/Transforms/Utils.h"
59 
60 using namespace llvm;
61 using namespace llvm::PatternMatch;
62 
63 namespace {
64 class SGPRRegisterRegAlloc : public RegisterRegAllocBase<SGPRRegisterRegAlloc> {
65 public:
66  SGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
67  : RegisterRegAllocBase(N, D, C) {}
68 };
69 
70 class VGPRRegisterRegAlloc : public RegisterRegAllocBase<VGPRRegisterRegAlloc> {
71 public:
72  VGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
73  : RegisterRegAllocBase(N, D, C) {}
74 };
75 
76 static bool onlyAllocateSGPRs(const TargetRegisterInfo &TRI,
77  const TargetRegisterClass &RC) {
78  return static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
79 }
80 
81 static bool onlyAllocateVGPRs(const TargetRegisterInfo &TRI,
82  const TargetRegisterClass &RC) {
83  return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
84 }
85 
86 
87 /// -{sgpr|vgpr}-regalloc=... command line option.
88 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
89 
90 /// A dummy default pass factory indicates whether the register allocator is
91 /// overridden on the command line.
92 static llvm::once_flag InitializeDefaultSGPRRegisterAllocatorFlag;
93 static llvm::once_flag InitializeDefaultVGPRRegisterAllocatorFlag;
94 
95 static SGPRRegisterRegAlloc
96 defaultSGPRRegAlloc("default",
97  "pick SGPR register allocator based on -O option",
99 
100 static cl::opt<SGPRRegisterRegAlloc::FunctionPassCtor, false,
102 SGPRRegAlloc("sgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
103  cl::desc("Register allocator to use for SGPRs"));
104 
105 static cl::opt<VGPRRegisterRegAlloc::FunctionPassCtor, false,
107 VGPRRegAlloc("vgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
108  cl::desc("Register allocator to use for VGPRs"));
109 
110 
111 static void initializeDefaultSGPRRegisterAllocatorOnce() {
112  RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
113 
114  if (!Ctor) {
115  Ctor = SGPRRegAlloc;
116  SGPRRegisterRegAlloc::setDefault(SGPRRegAlloc);
117  }
118 }
119 
120 static void initializeDefaultVGPRRegisterAllocatorOnce() {
121  RegisterRegAlloc::FunctionPassCtor Ctor = VGPRRegisterRegAlloc::getDefault();
122 
123  if (!Ctor) {
124  Ctor = VGPRRegAlloc;
125  VGPRRegisterRegAlloc::setDefault(VGPRRegAlloc);
126  }
127 }
128 
129 static FunctionPass *createBasicSGPRRegisterAllocator() {
130  return createBasicRegisterAllocator(onlyAllocateSGPRs);
131 }
132 
133 static FunctionPass *createGreedySGPRRegisterAllocator() {
134  return createGreedyRegisterAllocator(onlyAllocateSGPRs);
135 }
136 
137 static FunctionPass *createFastSGPRRegisterAllocator() {
138  return createFastRegisterAllocator(onlyAllocateSGPRs, false);
139 }
140 
141 static FunctionPass *createBasicVGPRRegisterAllocator() {
142  return createBasicRegisterAllocator(onlyAllocateVGPRs);
143 }
144 
145 static FunctionPass *createGreedyVGPRRegisterAllocator() {
146  return createGreedyRegisterAllocator(onlyAllocateVGPRs);
147 }
148 
149 static FunctionPass *createFastVGPRRegisterAllocator() {
150  return createFastRegisterAllocator(onlyAllocateVGPRs, true);
151 }
152 
153 static SGPRRegisterRegAlloc basicRegAllocSGPR(
154  "basic", "basic register allocator", createBasicSGPRRegisterAllocator);
155 static SGPRRegisterRegAlloc greedyRegAllocSGPR(
156  "greedy", "greedy register allocator", createGreedySGPRRegisterAllocator);
157 
158 static SGPRRegisterRegAlloc fastRegAllocSGPR(
159  "fast", "fast register allocator", createFastSGPRRegisterAllocator);
160 
161 
162 static VGPRRegisterRegAlloc basicRegAllocVGPR(
163  "basic", "basic register allocator", createBasicVGPRRegisterAllocator);
164 static VGPRRegisterRegAlloc greedyRegAllocVGPR(
165  "greedy", "greedy register allocator", createGreedyVGPRRegisterAllocator);
166 
167 static VGPRRegisterRegAlloc fastRegAllocVGPR(
168  "fast", "fast register allocator", createFastVGPRRegisterAllocator);
169 }
170 
172  "amdgpu-sroa",
173  cl::desc("Run SROA after promote alloca pass"),
175  cl::init(true));
176 
177 static cl::opt<bool>
178 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
179  cl::desc("Run early if-conversion"),
180  cl::init(false));
181 
182 static cl::opt<bool>
183 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
184  cl::desc("Run pre-RA exec mask optimizations"),
185  cl::init(true));
186 
187 // Option to disable vectorizer for tests.
189  "amdgpu-load-store-vectorizer",
190  cl::desc("Enable load store vectorizer"),
191  cl::init(true),
192  cl::Hidden);
193 
194 // Option to control global loads scalarization
196  "amdgpu-scalarize-global-loads",
197  cl::desc("Enable global load scalarization"),
198  cl::init(true),
199  cl::Hidden);
200 
201 // Option to run internalize pass.
203  "amdgpu-internalize-symbols",
204  cl::desc("Enable elimination of non-kernel functions and unused globals"),
205  cl::init(false),
206  cl::Hidden);
207 
208 // Option to inline all early.
210  "amdgpu-early-inline-all",
211  cl::desc("Inline all functions early"),
212  cl::init(false),
213  cl::Hidden);
214 
216  "amdgpu-sdwa-peephole",
217  cl::desc("Enable SDWA peepholer"),
218  cl::init(true));
219 
221  "amdgpu-dpp-combine",
222  cl::desc("Enable DPP combiner"),
223  cl::init(true));
224 
225 // Enable address space based alias analysis
226 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
227  cl::desc("Enable AMDGPU Alias Analysis"),
228  cl::init(true));
229 
230 // Option to run late CFG structurizer
232  "amdgpu-late-structurize",
233  cl::desc("Enable late CFG structurization"),
235  cl::Hidden);
236 
237 // Enable lib calls simplifications
239  "amdgpu-simplify-libcall",
240  cl::desc("Enable amdgpu library simplifications"),
241  cl::init(true),
242  cl::Hidden);
243 
245  "amdgpu-ir-lower-kernel-arguments",
246  cl::desc("Lower kernel argument loads in IR pass"),
247  cl::init(true),
248  cl::Hidden);
249 
251  "amdgpu-reassign-regs",
252  cl::desc("Enable register reassign optimizations on gfx10+"),
253  cl::init(true),
254  cl::Hidden);
255 
257  "amdgpu-opt-vgpr-liverange",
258  cl::desc("Enable VGPR liverange optimizations for if-else structure"),
259  cl::init(true), cl::Hidden);
260 
261 // Enable atomic optimization
263  "amdgpu-atomic-optimizations",
264  cl::desc("Enable atomic optimizations"),
265  cl::init(false),
266  cl::Hidden);
267 
268 // Enable Mode register optimization
270  "amdgpu-mode-register",
271  cl::desc("Enable mode register pass"),
272  cl::init(true),
273  cl::Hidden);
274 
275 // Option is used in lit tests to prevent deadcoding of patterns inspected.
276 static cl::opt<bool>
277 EnableDCEInRA("amdgpu-dce-in-ra",
278  cl::init(true), cl::Hidden,
279  cl::desc("Enable machine DCE inside regalloc"));
280 
281 static cl::opt<bool> EnableSetWavePriority("amdgpu-set-wave-priority",
282  cl::desc("Adjust wave priority"),
283  cl::init(false), cl::Hidden);
284 
286  "amdgpu-scalar-ir-passes",
287  cl::desc("Enable scalar IR passes"),
288  cl::init(true),
289  cl::Hidden);
290 
292  "amdgpu-enable-structurizer-workarounds",
293  cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
294  cl::Hidden);
295 
297  "amdgpu-enable-lds-replace-with-pointer",
298  cl::desc("Enable LDS replace with pointer pass"), cl::init(false),
299  cl::Hidden);
300 
302  "amdgpu-enable-lower-module-lds", cl::desc("Enable lower module lds pass"),
304  cl::Hidden);
305 
307  "amdgpu-enable-pre-ra-optimizations",
308  cl::desc("Enable Pre-RA optimizations pass"), cl::init(true),
309  cl::Hidden);
310 
312  "amdgpu-enable-promote-kernel-arguments",
313  cl::desc("Enable promotion of flat kernel pointer arguments to global"),
314  cl::Hidden, cl::init(true));
315 
317  // Register the target
320 
387 }
388 
389 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
390  return std::make_unique<AMDGPUTargetObjectFile>();
391 }
392 
394  return new SIScheduleDAGMI(C);
395 }
396 
397 static ScheduleDAGInstrs *
399  ScheduleDAGMILive *DAG =
400  new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
405  return DAG;
406 }
407 
408 static ScheduleDAGInstrs *
410  auto DAG = new GCNIterativeScheduler(C,
412  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
413  return DAG;
414 }
415 
417  return new GCNIterativeScheduler(C,
419 }
420 
421 static ScheduleDAGInstrs *
423  auto DAG = new GCNIterativeScheduler(C,
425  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
426  DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
427  return DAG;
428 }
429 
431 SISchedRegistry("si", "Run SI's custom scheduler",
433 
435 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
436  "Run GCN scheduler to maximize occupancy",
438 
440 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
441  "Run GCN scheduler to maximize occupancy (experimental)",
443 
445 GCNMinRegSchedRegistry("gcn-minreg",
446  "Run GCN iterative scheduler for minimal register usage (experimental)",
448 
450 GCNILPSchedRegistry("gcn-ilp",
451  "Run GCN iterative scheduler for ILP scheduling (experimental)",
453 
454 static StringRef computeDataLayout(const Triple &TT) {
455  if (TT.getArch() == Triple::r600) {
456  // 32-bit pointers.
457  return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
458  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
459  }
460 
461  // 32-bit private, local, and region pointers. 64-bit global, constant and
462  // flat, non-integral buffer fat pointers.
463  return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
464  "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
465  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
466  "-ni:7";
467 }
468 
470 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
471  if (!GPU.empty())
472  return GPU;
473 
474  // Need to default to a target with flat support for HSA.
475  if (TT.getArch() == Triple::amdgcn)
476  return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
477 
478  return "r600";
479 }
480 
482  // The AMDGPU toolchain only supports generating shared objects, so we
483  // must always use PIC.
484  return Reloc::PIC_;
485 }
486 
488  StringRef CPU, StringRef FS,
492  CodeGenOpt::Level OptLevel)
495  getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
496  TLOF(createTLOF(getTargetTriple())) {
497  initAsmInfo();
498  if (TT.getArch() == Triple::amdgcn) {
499  if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
501  else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
503  }
504 }
505 
509 
511 
513  Attribute GPUAttr = F.getFnAttribute("target-cpu");
514  return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
515 }
516 
518  Attribute FSAttr = F.getFnAttribute("target-features");
519 
520  return FSAttr.isValid() ? FSAttr.getValueAsString()
522 }
523 
524 /// Predicate for Internalize pass.
525 static bool mustPreserveGV(const GlobalValue &GV) {
526  if (const Function *F = dyn_cast<Function>(&GV))
527  return F->isDeclaration() || F->getName().startswith("__asan_") ||
528  F->getName().startswith("__sanitizer_") ||
529  AMDGPU::isEntryFunctionCC(F->getCallingConv());
530 
532  return !GV.use_empty();
533 }
534 
536  Builder.DivergentTarget = true;
537 
538  bool EnableOpt = getOptLevel() > CodeGenOpt::None;
539  bool Internalize = InternalizeSymbols;
540  bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
541  bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
542  bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
543  bool PromoteKernelArguments =
545 
546  if (EnableFunctionCalls) {
547  delete Builder.Inliner;
549  }
550 
551  Builder.addExtension(
553  [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
555  if (AMDGPUAA) {
558  }
561  if (Internalize)
564  if (Internalize)
565  PM.add(createGlobalDCEPass());
566  if (EarlyInline)
568  });
569 
570  Builder.addExtension(
572  [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
574  if (AMDGPUAA) {
577  }
580  if (LibCallSimplify)
582  });
583 
584  Builder.addExtension(
586  [EnableOpt, PromoteKernelArguments](const PassManagerBuilder &,
588  // Add promote kernel arguments pass to the opt pipeline right before
589  // infer address spaces which is needed to do actual address space
590  // rewriting.
591  if (PromoteKernelArguments)
593 
594  // Add infer address spaces pass to the opt pipeline after inlining
595  // but before SROA to increase SROA opportunities.
597 
598  // This should run after inlining to have any chance of doing anything,
599  // and before other cleanup optimizations.
601 
602  // Promote alloca to vector before SROA and loop unroll. If we manage
603  // to eliminate allocas before unroll we may choose to unroll less.
604  if (EnableOpt)
606  });
607 }
608 
611 }
612 
617  if (PassName == "amdgpu-propagate-attributes-late") {
619  return true;
620  }
621  if (PassName == "amdgpu-unify-metadata") {
623  return true;
624  }
625  if (PassName == "amdgpu-printf-runtime-binding") {
627  return true;
628  }
629  if (PassName == "amdgpu-always-inline") {
631  return true;
632  }
633  if (PassName == "amdgpu-replace-lds-use-with-pointer") {
635  return true;
636  }
637  if (PassName == "amdgpu-lower-module-lds") {
639  return true;
640  }
641  return false;
642  });
646  if (PassName == "amdgpu-simplifylib") {
648  return true;
649  }
650  if (PassName == "amdgpu-usenative") {
652  return true;
653  }
654  if (PassName == "amdgpu-promote-alloca") {
655  PM.addPass(AMDGPUPromoteAllocaPass(*this));
656  return true;
657  }
658  if (PassName == "amdgpu-promote-alloca-to-vector") {
660  return true;
661  }
662  if (PassName == "amdgpu-lower-kernel-attributes") {
664  return true;
665  }
666  if (PassName == "amdgpu-propagate-attributes-early") {
668  return true;
669  }
670  if (PassName == "amdgpu-promote-kernel-arguments") {
672  return true;
673  }
674  return false;
675  });
676 
678  FAM.registerPass([&] { return AMDGPUAA(); });
679  });
680 
681  PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
682  if (AAName == "amdgpu-aa") {
684  return true;
685  }
686  return false;
687  });
688 
697  });
698 
702  return;
703 
706 
707  if (InternalizeSymbols) {
709  }
711  if (InternalizeSymbols) {
712  PM.addPass(GlobalDCEPass());
713  }
716  });
717 
721  return;
722 
724 
725  // Add promote kernel arguments pass to the opt pipeline right before
726  // infer address spaces which is needed to do actual address space
727  // rewriting.
728  if (Level.getSpeedupLevel() > OptimizationLevel::O1.getSpeedupLevel() &&
731 
732  // Add infer address spaces pass to the opt pipeline after inlining
733  // but before SROA to increase SROA opportunities.
735 
736  // This should run after inlining to have any chance of doing
737  // anything, and before other cleanup optimizations.
739 
740  if (Level != OptimizationLevel::O0) {
741  // Promote alloca to vector before SROA and loop unroll. If we
742  // manage to eliminate allocas before unroll we may choose to unroll
743  // less.
745  }
746 
748  });
749 }
750 
751 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
752  return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
753  AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
754  AddrSpace == AMDGPUAS::REGION_ADDRESS)
755  ? -1
756  : 0;
757 }
758 
760  unsigned DestAS) const {
761  return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
763 }
764 
766  const auto *LD = dyn_cast<LoadInst>(V);
767  if (!LD)
769 
770  // It must be a generic pointer loaded.
771  assert(V->getType()->isPointerTy() &&
773 
774  const auto *Ptr = LD->getPointerOperand();
775  if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
777  // For a generic pointer loaded from the constant memory, it could be assumed
778  // as a global pointer since the constant memory is only populated on the
779  // host side. As implied by the offload programming model, only global
780  // pointers could be referenced on the host side.
782 }
783 
784 std::pair<const Value *, unsigned>
786  if (auto *II = dyn_cast<IntrinsicInst>(V)) {
787  switch (II->getIntrinsicID()) {
788  case Intrinsic::amdgcn_is_shared:
789  return std::make_pair(II->getArgOperand(0), AMDGPUAS::LOCAL_ADDRESS);
790  case Intrinsic::amdgcn_is_private:
791  return std::make_pair(II->getArgOperand(0), AMDGPUAS::PRIVATE_ADDRESS);
792  default:
793  break;
794  }
795  return std::make_pair(nullptr, -1);
796  }
797  // Check the global pointer predication based on
798  // (!is_share(p) && !is_private(p)). Note that logic 'and' is commutative and
799  // the order of 'is_shared' and 'is_private' is not significant.
800  Value *Ptr;
801  if (match(
802  const_cast<Value *>(V),
803  m_c_And(m_Not(m_Intrinsic<Intrinsic::amdgcn_is_shared>(m_Value(Ptr))),
804  m_Not(m_Intrinsic<Intrinsic::amdgcn_is_private>(
805  m_Deferred(Ptr))))))
806  return std::make_pair(Ptr, AMDGPUAS::GLOBAL_ADDRESS);
807 
808  return std::make_pair(nullptr, -1);
809 }
810 
811 //===----------------------------------------------------------------------===//
812 // GCN Target Machine (SI+)
813 //===----------------------------------------------------------------------===//
814 
816  StringRef CPU, StringRef FS,
820  CodeGenOpt::Level OL, bool JIT)
821  : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
822 
823 const TargetSubtargetInfo *
825  StringRef GPU = getGPUName(F);
827 
828  SmallString<128> SubtargetKey(GPU);
829  SubtargetKey.append(FS);
830 
831  auto &I = SubtargetMap[SubtargetKey];
832  if (!I) {
833  // This needs to be done before we create a new subtarget since any
834  // creation will depend on the TM and the code generation flags on the
835  // function that reside in TargetOptions.
837  I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
838  }
839 
840  I->setScalarizeGlobalBehavior(ScalarizeGlobal);
841 
842  return I.get();
843 }
844 
847  return TargetTransformInfo(GCNTTIImpl(this, F));
848 }
849 
850 //===----------------------------------------------------------------------===//
851 // AMDGPU Pass Setup
852 //===----------------------------------------------------------------------===//
853 
854 std::unique_ptr<CSEConfigBase> llvm::AMDGPUPassConfig::getCSEConfig() const {
856 }
857 
858 namespace {
859 
860 class GCNPassConfig final : public AMDGPUPassConfig {
861 public:
862  GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
863  : AMDGPUPassConfig(TM, PM) {
864  // It is necessary to know the register usage of the entire call graph. We
865  // allow calls without EnableAMDGPUFunctionCalls if they are marked
866  // noinline, so this is always required.
867  setRequiresCodeGenSCCOrder(true);
868  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
869  }
870 
871  GCNTargetMachine &getGCNTargetMachine() const {
872  return getTM<GCNTargetMachine>();
873  }
874 
876  createMachineScheduler(MachineSchedContext *C) const override;
877 
879  createPostMachineScheduler(MachineSchedContext *C) const override {
881  const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
883  DAG->addMutation(ST.createFillMFMAShadowMutation(DAG->TII));
885  return DAG;
886  }
887 
888  bool addPreISel() override;
889  void addMachineSSAOptimization() override;
890  bool addILPOpts() override;
891  bool addInstSelector() override;
892  bool addIRTranslator() override;
893  void addPreLegalizeMachineIR() override;
894  bool addLegalizeMachineIR() override;
895  void addPreRegBankSelect() override;
896  bool addRegBankSelect() override;
897  void addPreGlobalInstructionSelect() override;
898  bool addGlobalInstructionSelect() override;
899  void addFastRegAlloc() override;
900  void addOptimizedRegAlloc() override;
901 
902  FunctionPass *createSGPRAllocPass(bool Optimized);
903  FunctionPass *createVGPRAllocPass(bool Optimized);
904  FunctionPass *createRegAllocPass(bool Optimized) override;
905 
906  bool addRegAssignAndRewriteFast() override;
907  bool addRegAssignAndRewriteOptimized() override;
908 
909  void addPreRegAlloc() override;
910  bool addPreRewrite() override;
911  void addPostRegAlloc() override;
912  void addPreSched2() override;
913  void addPreEmitPass() override;
914 };
915 
916 } // end anonymous namespace
917 
919  : TargetPassConfig(TM, PM) {
920  // Exceptions and StackMaps are not supported, so these passes will never do
921  // anything.
924  // Garbage collection is not supported.
927 }
928 
932  else
934 }
935 
940  // ReassociateGEPs exposes more opportunities for SLSR. See
941  // the example in reassociate-geps-and-slsr.ll.
943  // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
944  // EarlyCSE can reuse.
946  // Run NaryReassociate after EarlyCSE/GVN to be more effective.
948  // NaryReassociate on GEPs creates redundant common expressions, so run
949  // EarlyCSE after it.
951 }
952 
955 
956  // There is no reason to run these.
960 
963 
964  // A call to propagate attributes pass in the backend in case opt was not run.
966 
968 
969  // Function calls are not supported, so make sure we inline everything.
972  // We need to add the barrier noop pass, otherwise adding the function
973  // inlining pass will cause all of the PassConfigs passes to be run
974  // one function at a time, which means if we have a module with two
975  // functions, then we will generate code for the first function
976  // without ever running any passes on the second.
978 
979  // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
982 
983  // Replace OpenCL enqueued block function pointers with global variables.
985 
986  // Can increase LDS used by kernel so runs before PromoteAlloca
987  if (EnableLowerModuleLDS) {
988  // The pass "amdgpu-replace-lds-use-with-pointer" need to be run before the
989  // pass "amdgpu-lower-module-lds", and also it required to be run only if
990  // "amdgpu-lower-module-lds" pass is enabled.
993 
995  }
996 
999 
1001 
1002  if (TM.getOptLevel() > CodeGenOpt::None) {
1004 
1005  if (EnableSROA)
1009 
1013  AAResults &AAR) {
1014  if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
1015  AAR.addAAResult(WrapperPass->getResult());
1016  }));
1017  }
1018 
1020  // TODO: May want to move later or split into an early and late one.
1022  }
1023  }
1024 
1026 
1027  // EarlyCSE is not always strong enough to clean up what LSR produces. For
1028  // example, GVN can combine
1029  //
1030  // %0 = add %a, %b
1031  // %1 = add %b, %a
1032  //
1033  // and
1034  //
1035  // %0 = shl nsw %a, 2
1036  // %1 = shl %a, 2
1037  //
1038  // but EarlyCSE can do neither of them.
1041 }
1042 
1044  if (TM->getTargetTriple().getArch() == Triple::amdgcn) {
1046 
1047  // FIXME: This pass adds 2 hacky attributes that can be replaced with an
1048  // analysis, and should be removed.
1050  }
1051 
1052  if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
1055 
1057 
1060 
1061  // LowerSwitch pass may introduce unreachable blocks that can
1062  // cause unexpected behavior for subsequent passes. Placing it
1063  // here seems better that these blocks would get cleaned up by
1064  // UnreachableBlockElim inserted next in the pass flow.
1066 }
1067 
1069  if (TM->getOptLevel() > CodeGenOpt::None)
1071  return false;
1072 }
1073 
1076  return false;
1077 }
1078 
1080  // Do nothing. GC is not supported.
1081  return false;
1082 }
1083 
1087  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1088  return DAG;
1089 }
1090 
1091 //===----------------------------------------------------------------------===//
1092 // GCN Pass Setup
1093 //===----------------------------------------------------------------------===//
1094 
1095 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1096  MachineSchedContext *C) const {
1097  const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1098  if (ST.enableSIScheduler())
1099  return createSIMachineScheduler(C);
1101 }
1102 
1103 bool GCNPassConfig::addPreISel() {
1105 
1106  if (TM->getOptLevel() > CodeGenOpt::None)
1108 
1109  if (isPassEnabled(EnableAtomicOptimizations, CodeGenOpt::Less)) {
1111  }
1112 
1113  if (TM->getOptLevel() > CodeGenOpt::None)
1114  addPass(createSinkingPass());
1115 
1116  // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1117  // regions formed by them.
1119  if (!LateCFGStructurize) {
1121  addPass(createFixIrreduciblePass());
1122  addPass(createUnifyLoopExitsPass());
1123  }
1124  addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1125  }
1127  if (!LateCFGStructurize) {
1129  }
1130  addPass(createLCSSAPass());
1131 
1132  if (TM->getOptLevel() > CodeGenOpt::Less)
1133  addPass(&AMDGPUPerfHintAnalysisID);
1134 
1135  return false;
1136 }
1137 
1138 void GCNPassConfig::addMachineSSAOptimization() {
1140 
1141  // We want to fold operands after PeepholeOptimizer has run (or as part of
1142  // it), because it will eliminate extra copies making it easier to fold the
1143  // real source operand. We want to eliminate dead instructions after, so that
1144  // we see fewer uses of the copies. We then need to clean up the dead
1145  // instructions leftover after the operands are folded as well.
1146  //
1147  // XXX - Can we get away without running DeadMachineInstructionElim again?
1148  addPass(&SIFoldOperandsID);
1149  if (EnableDPPCombine)
1150  addPass(&GCNDPPCombineID);
1151  addPass(&SILoadStoreOptimizerID);
1152  if (isPassEnabled(EnableSDWAPeephole)) {
1153  addPass(&SIPeepholeSDWAID);
1154  addPass(&EarlyMachineLICMID);
1155  addPass(&MachineCSEID);
1156  addPass(&SIFoldOperandsID);
1157  }
1158  addPass(&DeadMachineInstructionElimID);
1159  addPass(createSIShrinkInstructionsPass());
1160 }
1161 
1162 bool GCNPassConfig::addILPOpts() {
1164  addPass(&EarlyIfConverterID);
1165 
1167  return false;
1168 }
1169 
1170 bool GCNPassConfig::addInstSelector() {
1172  addPass(&SIFixSGPRCopiesID);
1173  addPass(createSILowerI1CopiesPass());
1174  return false;
1175 }
1176 
1177 bool GCNPassConfig::addIRTranslator() {
1178  addPass(new IRTranslator(getOptLevel()));
1179  return false;
1180 }
1181 
1182 void GCNPassConfig::addPreLegalizeMachineIR() {
1183  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1184  addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1185  addPass(new Localizer());
1186 }
1187 
1188 bool GCNPassConfig::addLegalizeMachineIR() {
1189  addPass(new Legalizer());
1190  return false;
1191 }
1192 
1193 void GCNPassConfig::addPreRegBankSelect() {
1194  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1195  addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1196 }
1197 
1198 bool GCNPassConfig::addRegBankSelect() {
1199  addPass(new RegBankSelect());
1200  return false;
1201 }
1202 
1203 void GCNPassConfig::addPreGlobalInstructionSelect() {
1204  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1205  addPass(createAMDGPURegBankCombiner(IsOptNone));
1206 }
1207 
1208 bool GCNPassConfig::addGlobalInstructionSelect() {
1209  addPass(new InstructionSelect(getOptLevel()));
1210  return false;
1211 }
1212 
1213 void GCNPassConfig::addPreRegAlloc() {
1214  if (LateCFGStructurize) {
1216  }
1217 }
1218 
1219 void GCNPassConfig::addFastRegAlloc() {
1220  // FIXME: We have to disable the verifier here because of PHIElimination +
1221  // TwoAddressInstructions disabling it.
1222 
1223  // This must be run immediately after phi elimination and before
1224  // TwoAddressInstructions, otherwise the processing of the tied operand of
1225  // SI_ELSE will introduce a copy of the tied operand source after the else.
1226  insertPass(&PHIEliminationID, &SILowerControlFlowID);
1227 
1230 
1232 }
1233 
1234 void GCNPassConfig::addOptimizedRegAlloc() {
1235  // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1236  // instructions that cause scheduling barriers.
1237  insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1239 
1240  if (OptExecMaskPreRA)
1242 
1243  if (isPassEnabled(EnablePreRAOptimizations))
1245 
1246  // This is not an essential optimization and it has a noticeable impact on
1247  // compilation time, so we only enable it from O2.
1248  if (TM->getOptLevel() > CodeGenOpt::Less)
1250 
1251  // FIXME: when an instruction has a Killed operand, and the instruction is
1252  // inside a bundle, seems only the BUNDLE instruction appears as the Kills of
1253  // the register in LiveVariables, this would trigger a failure in verifier,
1254  // we should fix it and enable the verifier.
1255  if (OptVGPRLiveRange)
1257  // This must be run immediately after phi elimination and before
1258  // TwoAddressInstructions, otherwise the processing of the tied operand of
1259  // SI_ELSE will introduce a copy of the tied operand source after the else.
1260  insertPass(&PHIEliminationID, &SILowerControlFlowID);
1261 
1262  if (EnableDCEInRA)
1264 
1266 }
1267 
1268 bool GCNPassConfig::addPreRewrite() {
1269  if (EnableRegReassign)
1270  addPass(&GCNNSAReassignID);
1271  return true;
1272 }
1273 
1274 FunctionPass *GCNPassConfig::createSGPRAllocPass(bool Optimized) {
1275  // Initialize the global default.
1276  llvm::call_once(InitializeDefaultSGPRRegisterAllocatorFlag,
1277  initializeDefaultSGPRRegisterAllocatorOnce);
1278 
1279  RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
1280  if (Ctor != useDefaultRegisterAllocator)
1281  return Ctor();
1282 
1283  if (Optimized)
1284  return createGreedyRegisterAllocator(onlyAllocateSGPRs);
1285 
1286  return createFastRegisterAllocator(onlyAllocateSGPRs, false);
1287 }
1288 
1289 FunctionPass *GCNPassConfig::createVGPRAllocPass(bool Optimized) {
1290  // Initialize the global default.
1291  llvm::call_once(InitializeDefaultVGPRRegisterAllocatorFlag,
1292  initializeDefaultVGPRRegisterAllocatorOnce);
1293 
1294  RegisterRegAlloc::FunctionPassCtor Ctor = VGPRRegisterRegAlloc::getDefault();
1295  if (Ctor != useDefaultRegisterAllocator)
1296  return Ctor();
1297 
1298  if (Optimized)
1299  return createGreedyVGPRRegisterAllocator();
1300 
1301  return createFastVGPRRegisterAllocator();
1302 }
1303 
1304 FunctionPass *GCNPassConfig::createRegAllocPass(bool Optimized) {
1305  llvm_unreachable("should not be used");
1306 }
1307 
1308 static const char RegAllocOptNotSupportedMessage[] =
1309  "-regalloc not supported with amdgcn. Use -sgpr-regalloc and -vgpr-regalloc";
1310 
1311 bool GCNPassConfig::addRegAssignAndRewriteFast() {
1312  if (!usingDefaultRegAlloc())
1314 
1315  addPass(createSGPRAllocPass(false));
1316 
1317  // Equivalent of PEI for SGPRs.
1318  addPass(&SILowerSGPRSpillsID);
1319 
1320  addPass(createVGPRAllocPass(false));
1321  return true;
1322 }
1323 
1324 bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
1325  if (!usingDefaultRegAlloc())
1327 
1328  addPass(createSGPRAllocPass(true));
1329 
1330  // Commit allocated register changes. This is mostly necessary because too
1331  // many things rely on the use lists of the physical registers, such as the
1332  // verifier. This is only necessary with allocators which use LiveIntervals,
1333  // since FastRegAlloc does the replacements itself.
1334  addPass(createVirtRegRewriter(false));
1335 
1336  // Equivalent of PEI for SGPRs.
1337  addPass(&SILowerSGPRSpillsID);
1338 
1339  addPass(createVGPRAllocPass(true));
1340 
1341  addPreRewrite();
1342  addPass(&VirtRegRewriterID);
1343 
1344  return true;
1345 }
1346 
1347 void GCNPassConfig::addPostRegAlloc() {
1348  addPass(&SIFixVGPRCopiesID);
1349  if (getOptLevel() > CodeGenOpt::None)
1350  addPass(&SIOptimizeExecMaskingID);
1352 }
1353 
1354 void GCNPassConfig::addPreSched2() {
1355  if (TM->getOptLevel() > CodeGenOpt::None)
1356  addPass(createSIShrinkInstructionsPass());
1357  addPass(&SIPostRABundlerID);
1358 }
1359 
1360 void GCNPassConfig::addPreEmitPass() {
1361  addPass(createSIMemoryLegalizerPass());
1362  addPass(createSIInsertWaitcntsPass());
1363 
1364  addPass(createSIModeRegisterPass());
1365 
1366  if (getOptLevel() > CodeGenOpt::None)
1367  addPass(&SIInsertHardClausesID);
1368 
1369  addPass(&SILateBranchLoweringPassID);
1370  if (isPassEnabled(EnableSetWavePriority, CodeGenOpt::Less))
1372  if (getOptLevel() > CodeGenOpt::None)
1373  addPass(&SIPreEmitPeepholeID);
1374  // The hazard recognizer that runs as part of the post-ra scheduler does not
1375  // guarantee to be able handle all hazards correctly. This is because if there
1376  // are multiple scheduling regions in a basic block, the regions are scheduled
1377  // bottom up, so when we begin to schedule a region we don't know what
1378  // instructions were emitted directly before it.
1379  //
1380  // Here we add a stand-alone hazard recognizer pass which can handle all
1381  // cases.
1382  addPass(&PostRAHazardRecognizerID);
1383  addPass(&BranchRelaxationPassID);
1384 }
1385 
1387  return new GCNPassConfig(*this, PM);
1388 }
1389 
1391  return new yaml::SIMachineFunctionInfo();
1392 }
1393 
1397  return new yaml::SIMachineFunctionInfo(
1398  *MFI, *MF.getSubtarget().getRegisterInfo(), MF);
1399 }
1400 
1403  SMDiagnostic &Error, SMRange &SourceRange) const {
1404  const yaml::SIMachineFunctionInfo &YamlMFI =
1405  static_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1406  MachineFunction &MF = PFS.MF;
1408 
1409  if (MFI->initializeBaseYamlFields(YamlMFI, MF, PFS, Error, SourceRange))
1410  return true;
1411 
1412  if (MFI->Occupancy == 0) {
1413  // Fixup the subtarget dependent default value.
1414  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1415  MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1416  }
1417 
1418  auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1419  Register TempReg;
1420  if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1421  SourceRange = RegName.SourceRange;
1422  return true;
1423  }
1424  RegVal = TempReg;
1425 
1426  return false;
1427  };
1428 
1429  auto parseOptionalRegister = [&](const yaml::StringValue &RegName,
1430  Register &RegVal) {
1431  return !RegName.Value.empty() && parseRegister(RegName, RegVal);
1432  };
1433 
1434  if (parseOptionalRegister(YamlMFI.VGPRForAGPRCopy, MFI->VGPRForAGPRCopy))
1435  return true;
1436 
1437  auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1438  // Create a diagnostic for a the register string literal.
1439  const MemoryBuffer &Buffer =
1440  *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1441  Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1442  RegName.Value.size(), SourceMgr::DK_Error,
1443  "incorrect register class for field", RegName.Value,
1444  None, None);
1445  SourceRange = RegName.SourceRange;
1446  return true;
1447  };
1448 
1449  if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1450  parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1451  parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1452  return true;
1453 
1454  if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1455  !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1456  return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1457  }
1458 
1459  if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1460  !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1461  return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1462  }
1463 
1464  if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1465  !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1466  return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1467  }
1468 
1469  for (const auto &YamlReg : YamlMFI.WWMReservedRegs) {
1470  Register ParsedReg;
1471  if (parseRegister(YamlReg, ParsedReg))
1472  return true;
1473 
1474  MFI->reserveWWMRegister(ParsedReg);
1475  }
1476 
1477  auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1478  const TargetRegisterClass &RC,
1479  ArgDescriptor &Arg, unsigned UserSGPRs,
1480  unsigned SystemSGPRs) {
1481  // Skip parsing if it's not present.
1482  if (!A)
1483  return false;
1484 
1485  if (A->IsRegister) {
1486  Register Reg;
1487  if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1488  SourceRange = A->RegisterName.SourceRange;
1489  return true;
1490  }
1491  if (!RC.contains(Reg))
1492  return diagnoseRegisterClass(A->RegisterName);
1494  } else
1495  Arg = ArgDescriptor::createStack(A->StackOffset);
1496  // Check and apply the optional mask.
1497  if (A->Mask)
1498  Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1499 
1500  MFI->NumUserSGPRs += UserSGPRs;
1501  MFI->NumSystemSGPRs += SystemSGPRs;
1502  return false;
1503  };
1504 
1505  if (YamlMFI.ArgInfo &&
1506  (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1507  AMDGPU::SGPR_128RegClass,
1508  MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1509  parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1510  AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1511  2, 0) ||
1512  parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1513  MFI->ArgInfo.QueuePtr, 2, 0) ||
1514  parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1515  AMDGPU::SReg_64RegClass,
1516  MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1517  parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1518  AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1519  2, 0) ||
1520  parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1521  AMDGPU::SReg_64RegClass,
1522  MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1523  parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1524  AMDGPU::SGPR_32RegClass,
1525  MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1526  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1527  AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1528  0, 1) ||
1529  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1530  AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1531  0, 1) ||
1532  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1533  AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1534  0, 1) ||
1535  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1536  AMDGPU::SGPR_32RegClass,
1537  MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1538  parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1539  AMDGPU::SGPR_32RegClass,
1540  MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1541  parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1542  AMDGPU::SReg_64RegClass,
1543  MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1544  parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1545  AMDGPU::SReg_64RegClass,
1546  MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1547  parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1548  AMDGPU::VGPR_32RegClass,
1549  MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1550  parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1551  AMDGPU::VGPR_32RegClass,
1552  MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1553  parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1554  AMDGPU::VGPR_32RegClass,
1555  MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1556  return true;
1557 
1558  MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1559  MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1564 
1565  return false;
1566 }
llvm::AAResults::addAAResult
void addAAResult(AAResultT &AAResult)
Register a specific AA result.
Definition: AliasAnalysis.h:520
llvm::initializeR600ControlFlowFinalizerPass
void initializeR600ControlFlowFinalizerPass(PassRegistry &)
llvm::TargetPassConfig::addPostRegAlloc
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Definition: TargetPassConfig.h:417
EnableDCEInRA
static cl::opt< bool > EnableDCEInRA("amdgpu-dce-in-ra", cl::init(true), cl::Hidden, cl::desc("Enable machine DCE inside regalloc"))
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:186
llvm::createFastRegisterAllocator
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
Definition: RegAllocFast.cpp:1570
llvm::AAManager
A manager for alias analyses.
Definition: AliasAnalysis.h:1299
llvm::AMDGPUAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: AMDGPUAliasAnalysis.h:48
llvm::ArgDescriptor::createStack
static constexpr ArgDescriptor createStack(unsigned Offset, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:49
llvm::AMDGPUFunctionArgInfo::QueuePtr
ArgDescriptor QueuePtr
Definition: AMDGPUArgumentUsageInfo.h:126
EnableLowerModuleLDS
static cl::opt< bool, true > EnableLowerModuleLDS("amdgpu-enable-lower-module-lds", cl::desc("Enable lower module lds pass"), cl::location(AMDGPUTargetMachine::EnableLowerModuleLDS), cl::init(true), cl::Hidden)
llvm::initializeR600PacketizerPass
void initializeR600PacketizerPass(PassRegistry &)
LLVMInitializeAMDGPUTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget()
Definition: AMDGPUTargetMachine.cpp:316
llvm::createAMDGPUCtorDtorLoweringPass
ModulePass * createAMDGPUCtorDtorLoweringPass()
RegAllocOptNotSupportedMessage
static const char RegAllocOptNotSupportedMessage[]
Definition: AMDGPUTargetMachine.cpp:1308
llvm::InferAddressSpacesPass
Definition: InferAddressSpaces.h:16
EnableSIModeRegisterPass
static cl::opt< bool > EnableSIModeRegisterPass("amdgpu-mode-register", cl::desc("Enable mode register pass"), cl::init(true), cl::Hidden)
llvm::PerFunctionMIParsingState::SM
SourceMgr * SM
Definition: MIParser.h:165
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
PassBuilder.h
llvm::createGreedyRegisterAllocator
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
Definition: RegAllocGreedy.cpp:179
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:169
llvm::createAMDGPUAttributorPass
Pass * createAMDGPUAttributorPass()
Definition: AMDGPUAttributor.cpp:777
llvm::AMDGPUTargetMachine::registerDefaultAliasAnalyses
void registerDefaultAliasAnalyses(AAManager &) override
Allow the target to register alias analyses with the AAManager for use with the new pass manager.
Definition: AMDGPUTargetMachine.cpp:609
mustPreserveGV
static bool mustPreserveGV(const GlobalValue &GV)
Predicate for Internalize pass.
Definition: AMDGPUTargetMachine.cpp:525
llvm::createSeparateConstOffsetFromGEPPass
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
Definition: SeparateConstOffsetFromGEP.cpp:498
llvm::OptimizationLevel::O1
static const OptimizationLevel O1
Optimize quickly without destroying debuggability.
Definition: OptimizationLevel.h:57
llvm::GCNTargetMachine::convertFuncInfoToYAML
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
Definition: AMDGPUTargetMachine.cpp:1395
llvm::AMDGPULowerModuleLDSPass
Definition: AMDGPU.h:155
llvm::initializeR600ExpandSpecialInstrsPassPass
void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &)
llvm::initializeAMDGPUPostLegalizerCombinerPass
void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &)
llvm::initializeAMDGPUPromoteAllocaPass
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
llvm::createSIMemoryLegalizerPass
FunctionPass * createSIMemoryLegalizerPass()
Definition: SIMemoryLegalizer.cpp:2240
llvm::SILowerSGPRSpillsID
char & SILowerSGPRSpillsID
Definition: SILowerSGPRSpills.cpp:73
llvm::Wave32
@ Wave32
Definition: AMDGPUMCTargetDesc.h:31
llvm::createAMDGPUSetWavePriorityPass
FunctionPass * createAMDGPUSetWavePriorityPass()
llvm::PassBuilder::registerPipelineStartEPCallback
void registerPipelineStartEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:457
llvm::Type::isPointerTy
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:218
llvm::TargetOptions
Definition: TargetOptions.h:124
llvm::AMDGPUAlwaysInlinePass
Definition: AMDGPU.h:248
llvm::yaml::SIMachineFunctionInfo::ArgInfo
Optional< SIArgumentInfo > ArgInfo
Definition: SIMachineFunctionInfo.h:296
SIMachineFunctionInfo.h
Scalar.h
llvm::ArgDescriptor::createArg
static constexpr ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask)
Definition: AMDGPUArgumentUsageInfo.h:54
createMinRegScheduler
static ScheduleDAGInstrs * createMinRegScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:416
llvm::initializeGCNPreRAOptimizationsPass
void initializeGCNPreRAOptimizationsPass(PassRegistry &)
T
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::Function
Definition: Function.h:60
llvm::cl::location
LocationClass< Ty > location(Ty &L)
Definition: CommandLine.h:447
llvm::Attribute
Definition: Attributes.h:52
llvm::AMDGPU::SIModeRegisterDefaults::FP32OutputDenormals
bool FP32OutputDenormals
Definition: AMDGPUBaseInfo.h:996
llvm::PassManager::addPass
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same< PassT, PassManager >::value > addPass(PassT &&Pass)
Definition: PassManager.h:550
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::initializeAMDGPUAlwaysInlinePass
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
llvm::yaml::MachineFunctionInfo
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
Definition: MIRYamlMapping.h:676
llvm::PHIEliminationID
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
Definition: PHIElimination.cpp:128
llvm::initializeSIInsertHardClausesPass
void initializeSIInsertHardClausesPass(PassRegistry &)
llvm::initializeAMDGPUOpenCLEnqueuedBlockLoweringPass
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
llvm::initializeSIPreAllocateWWMRegsPass
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)
llvm::createMFMAClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createMFMAClusterDAGMutation()
Definition: AMDGPUMFMAClustering.cpp:168
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::initializeAMDGPUPropagateAttributesLatePass
void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &)
InferAddressSpaces.h
llvm::AMDGPU::SIModeRegisterDefaults::IEEE
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
Definition: AMDGPUBaseInfo.h:987
llvm::createAlwaysInlinerLegacyPass
Pass * createAlwaysInlinerLegacyPass(bool InsertLifetime=true)
Create a legacy pass manager instance of a pass to inline and remove functions marked as "always_inli...
Definition: AlwaysInliner.cpp:177
getGPUOrDefault
static LLVM_READNONE StringRef getGPUOrDefault(const Triple &TT, StringRef GPU)
Definition: AMDGPUTargetMachine.cpp:470
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:140
llvm::AMDGPUPromoteAllocaToVectorPass
Definition: AMDGPU.h:233
llvm::initializeAMDGPULateCodeGenPreparePass
void initializeAMDGPULateCodeGenPreparePass(PassRegistry &)
llvm::createFixIrreduciblePass
FunctionPass * createFixIrreduciblePass()
Definition: FixIrreducible.cpp:104
llvm::MachineSchedRegistry
MachineSchedRegistry provides a selection of available machine instruction schedulers.
Definition: MachineScheduler.h:141
llvm::createVirtRegRewriter
FunctionPass * createVirtRegRewriter(bool ClearVirtRegs=true)
Definition: VirtRegMap.cpp:646
llvm::Triple::amdgcn
@ amdgcn
Definition: Triple.h:74
GCNSchedStrategy.h
llvm::GCNIterativeScheduler::SCHEDULE_ILP
@ SCHEDULE_ILP
Definition: GCNIterativeScheduler.h:37
llvm::yaml::SIMachineFunctionInfo::VGPRForAGPRCopy
StringValue VGPRForAGPRCopy
Definition: SIMachineFunctionInfo.h:299
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:167
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:729
llvm::createAMDGPULateCodeGenPreparePass
FunctionPass * createAMDGPULateCodeGenPreparePass()
Definition: AMDGPULateCodeGenPrepare.cpp:193
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::createSILowerI1CopiesPass
FunctionPass * createSILowerI1CopiesPass()
Definition: SILowerI1Copies.cpp:413
llvm::initializeR600ClauseMergePassPass
void initializeR600ClauseMergePassPass(PassRegistry &)
llvm::GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY
@ SCHEDULE_LEGACYMAXOCCUPANCY
Definition: GCNIterativeScheduler.h:36
llvm::createFlattenCFGPass
FunctionPass * createFlattenCFGPass()
Definition: FlattenCFGPass.cpp:81
llvm::InternalizePass
A pass that internalizes all functions and variables other than those that must be preserved accordin...
Definition: Internalize.h:35
llvm::initializeSIOptimizeExecMaskingPreRAPass
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
llvm::AMDGPUFunctionArgInfo::FlatScratchInit
ArgDescriptor FlatScratchInit
Definition: AMDGPUArgumentUsageInfo.h:129
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
FAM
FunctionAnalysisManager FAM
Definition: PassBuilderBindings.cpp:59
llvm::createEarlyCSEPass
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1759
llvm::Wave64
@ Wave64
Definition: AMDGPUMCTargetDesc.h:31
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::initializeSILowerI1CopiesPass
void initializeSILowerI1CopiesPass(PassRegistry &)
llvm::AMDGPUMachineFunction::getLDSSize
uint32_t getLDSSize() const
Definition: AMDGPUMachineFunction.h:74
EnableSetWavePriority
static cl::opt< bool > EnableSetWavePriority("amdgpu-set-wave-priority", cl::desc("Adjust wave priority"), cl::init(false), cl::Hidden)
llvm::SIPreEmitPeepholeID
char & SIPreEmitPeepholeID
llvm::createAMDGPUPostLegalizeCombiner
FunctionPass * createAMDGPUPostLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPostLegalizerCombiner.cpp:448
llvm::initializeAMDGPUDAGToDAGISelPass
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
llvm::initializeSIPeepholeSDWAPass
void initializeSIPeepholeSDWAPass(PassRegistry &)
llvm::ShadowStackGCLoweringID
char & ShadowStackGCLoweringID
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC.
Definition: ShadowStackGCLowering.cpp:91
llvm::SILowerControlFlowID
char & SILowerControlFlowID
Definition: SILowerControlFlow.cpp:174
llvm::yaml::SIMachineFunctionInfo
Definition: SIMachineFunctionInfo.h:270
llvm::SIOptimizeVGPRLiveRangeID
char & SIOptimizeVGPRLiveRangeID
Definition: SIOptimizeVGPRLiveRange.cpp:618
llvm::createAMDGPUUnifyMetadataPass
ModulePass * createAMDGPUUnifyMetadataPass()
InstructionSelect.h
EnableStructurizerWorkarounds
static cl::opt< bool > EnableStructurizerWorkarounds("amdgpu-enable-structurizer-workarounds", cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true), cl::Hidden)
llvm::AMDGPUPassConfig
Definition: AMDGPUTargetMachine.h:106
llvm::AMDGPUAAWrapperPass
Legacy wrapper pass to provide the AMDGPUAAResult object.
Definition: AMDGPUAliasAnalysis.h:62
EnableAtomicOptimizations
static cl::opt< bool > EnableAtomicOptimizations("amdgpu-atomic-optimizations", cl::desc("Enable atomic optimizations"), cl::init(false), cl::Hidden)
createGCNMaxOccupancyMachineScheduler
static ScheduleDAGInstrs * createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:398
llvm::Optional< Reloc::Model >
llvm::GCNScheduleDAGMILive
Definition: GCNSchedStrategy.h:74
llvm::initializeSIFoldOperandsPass
void initializeSIFoldOperandsPass(PassRegistry &)
llvm::createBarrierNoopPass
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
Definition: BarrierNoopPass.cpp:43
llvm::createAMDGPUISelDag
FunctionPass * createAMDGPUISelDag(TargetMachine *TM=nullptr, CodeGenOpt::Level OptLevel=CodeGenOpt::Default)
This pass converts a legalized DAG into a AMDGPU-specific.
Definition: AMDGPUISelDAGToDAG.cpp:112
InternalizeSymbols
static cl::opt< bool > InternalizeSymbols("amdgpu-internalize-symbols", cl::desc("Enable elimination of non-kernel functions and unused globals"), cl::init(false), cl::Hidden)
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
llvm::AMDGPU::SIModeRegisterDefaults::FP32InputDenormals
bool FP32InputDenormals
If this is set, neither input or output denormals are flushed for most f32 instructions.
Definition: AMDGPUBaseInfo.h:995
llvm::PassBuilder::registerAnalysisRegistrationCallback
void registerAnalysisRegistrationCallback(const std::function< void(CGSCCAnalysisManager &)> &C)
{{@ Register callbacks for analysis registration with this PassBuilder instance.
Definition: PassBuilder.h:517
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
SIMachineScheduler.h
llvm::yaml::SIMode::FP32OutputDenormals
bool FP32OutputDenormals
Definition: SIMachineFunctionInfo.h:234
llvm::createGVNPass
FunctionPass * createGVNPass(bool NoMemDepAnalysis=false)
Create a legacy GVN pass.
Definition: GVN.cpp:3250
llvm::AMDGPUAS::FLAT_ADDRESS
@ FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:358
llvm::createCGSCCToFunctionPassAdaptor
CGSCCToFunctionPassAdaptor createCGSCCToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false, bool NoRerun=false)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: CGSCCPassManager.h:509
llvm::AMDGPUFunctionArgInfo::PrivateSegmentSize
ArgDescriptor PrivateSegmentSize
Definition: AMDGPUArgumentUsageInfo.h:130
llvm::createR600OpenCLImageTypeLoweringPass
ModulePass * createR600OpenCLImageTypeLoweringPass()
Definition: R600OpenCLImageTypeLoweringPass.cpp:372
llvm::AMDGPUUseNativeCallsPass
Definition: AMDGPU.h:69
llvm::AMDGPUFunctionArgInfo::DispatchPtr
ArgDescriptor DispatchPtr
Definition: AMDGPUArgumentUsageInfo.h:125
llvm::PatternMatch::m_c_And
BinaryOp_match< LHS, RHS, Instruction::And, true > m_c_And(const LHS &L, const RHS &R)
Matches an And with LHS and RHS in either order.
Definition: PatternMatch.h:2257
llvm::initializeAMDGPUPropagateAttributesEarlyPass
void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &)
llvm::SIPreAllocateWWMRegsID
char & SIPreAllocateWWMRegsID
Definition: SIPreAllocateWWMRegs.cpp:84
llvm::initializeAMDGPUPromoteKernelArgumentsPass
void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &)
llvm::SIPostRABundlerID
char & SIPostRABundlerID
Definition: SIPostRABundler.cpp:69
llvm::OptimizationLevel::O0
static const OptimizationLevel O0
Disable as many optimizations as possible.
Definition: OptimizationLevel.h:41
llvm::initializeSIShrinkInstructionsPass
void initializeSIShrinkInstructionsPass(PassRegistry &)
LegacyPassManager.h
llvm::TwoAddressInstructionPassID
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Definition: TwoAddressInstructionPass.cpp:192
PassManagerBuilder.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::cl::ReallyHidden
@ ReallyHidden
Definition: CommandLine.h:140
llvm::GCNTargetMachine::parseMachineFunctionInfo
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
Definition: AMDGPUTargetMachine.cpp:1401
llvm::initializeAMDGPUSimplifyLibCallsPass
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &)
Internalize.h
createSIMachineScheduler
static ScheduleDAGInstrs * createSIMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:393
llvm::PatternMatch::m_Deferred
deferredval_ty< Value > m_Deferred(Value *const &V)
Like m_Specific(), but works if the specific value to match is determined as part of the same match()...
Definition: PatternMatch.h:798
llvm::MemoryBuffer
This interface provides simple read-only access to a block of memory, and provides simple methods for...
Definition: MemoryBuffer.h:50
llvm::AMDGPUMachineFunction::Mode
AMDGPU::SIModeRegisterDefaults Mode
Definition: AMDGPUMachineFunction.h:48
llvm::AMDGPUPassConfig::addGCPasses
bool addGCPasses() override
addGCPasses - Add late codegen passes that analyze code for garbage collection.
Definition: AMDGPUTargetMachine.cpp:1079
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::createAMDGPUExternalAAWrapperPass
ImmutablePass * createAMDGPUExternalAAWrapperPass()
Definition: AMDGPUAliasAnalysis.cpp:37
llvm::AMDGPUFunctionArgInfo::DispatchID
ArgDescriptor DispatchID
Definition: AMDGPUArgumentUsageInfo.h:128
llvm::initializeAMDGPULowerIntrinsicsPass
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &)
llvm::initializeGCNDPPCombinePass
void initializeGCNDPPCombinePass(PassRegistry &)
llvm::AMDGPUUnifyMetadataPass
Definition: AMDGPU.h:274
llvm::AMDGPUFunctionArgInfo::ImplicitArgPtr
ArgDescriptor ImplicitArgPtr
Definition: AMDGPUArgumentUsageInfo.h:141
EnableSDWAPeephole
static cl::opt< bool > EnableSDWAPeephole("amdgpu-sdwa-peephole", cl::desc("Enable SDWA peepholer"), cl::init(true))
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
CSEInfo.h
llvm::AMDGPUAS::REGION_ADDRESS
@ REGION_ADDRESS
Address space for region memory. (GDS)
Definition: AMDGPU.h:360
FunctionPassCtor
llvm::SIOptimizeExecMaskingID
char & SIOptimizeExecMaskingID
Definition: SIOptimizeExecMasking.cpp:53
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::initializeAMDGPUUnifyMetadataPass
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
llvm::yaml::SIMachineFunctionInfo::FrameOffsetReg
StringValue FrameOffsetReg
Definition: SIMachineFunctionInfo.h:290
llvm::initializeAMDGPUArgumentUsageInfoPass
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
R600.h
llvm::AMDGPUPassConfig::addIRPasses
void addIRPasses() override
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: AMDGPUTargetMachine.cpp:953
SISchedRegistry
static MachineSchedRegistry SISchedRegistry("si", "Run SI's custom scheduler", createSIMachineScheduler)
GCNIterativeScheduler.h
llvm::AMDGPUFunctionArgInfo::WorkGroupIDX
ArgDescriptor WorkGroupIDX
Definition: AMDGPUArgumentUsageInfo.h:133
llvm::GCNTargetMachine::GCNTargetMachine
GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: AMDGPUTargetMachine.cpp:815
llvm::createInferAddressSpacesPass
FunctionPass * createInferAddressSpacesPass(unsigned AddressSpace=~0u)
Definition: InferAddressSpaces.cpp:1308
llvm::initializeSILateBranchLoweringPass
void initializeSILateBranchLoweringPass(PassRegistry &)
llvm::TargetPassConfig::TM
LLVMTargetMachine * TM
Definition: TargetPassConfig.h:122
AMDGPUAliasAnalysis.h
llvm::AMDGPUTargetMachine
Definition: AMDGPUTargetMachine.h:28
llvm::MSP430Attrs::CodeModel
CodeModel
Definition: MSP430Attributes.h:37
llvm::createAMDGPUUseNativeCallsPass
FunctionPass * createAMDGPUUseNativeCallsPass()
Definition: AMDGPULibCalls.cpp:1663
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
AlwaysInliner.h
llvm::PatternMatch::match
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
llvm::AAResults
Definition: AliasAnalysis.h:511
llvm::yaml::SIMode::FP32InputDenormals
bool FP32InputDenormals
Definition: SIMachineFunctionInfo.h:233
llvm::PassBuilder::registerParseAACallback
void registerParseAACallback(const std::function< bool(StringRef Name, AAManager &AA)> &C)
Register a callback for parsing an AliasAnalysis Name to populate the given AAManager AA.
Definition: PassBuilder.h:509
ScalarizeGlobal
static cl::opt< bool > ScalarizeGlobal("amdgpu-scalarize-global-loads", cl::desc("Enable global load scalarization"), cl::init(true), cl::Hidden)
llvm::createNaryReassociatePass
FunctionPass * createNaryReassociatePass()
Definition: NaryReassociate.cpp:165
llvm::PostRAHazardRecognizerID
char & PostRAHazardRecognizerID
PostRAHazardRecognizer - This pass runs the post-ra hazard recognizer.
Definition: PostRAHazardRecognizer.cpp:61
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:738
llvm::initializeAMDGPULowerKernelArgumentsPass
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
llvm::initializeSIWholeQuadModePass
void initializeSIWholeQuadModePass(PassRegistry &)
llvm::initializeAMDGPUAtomicOptimizerPass
void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)
llvm::getTheAMDGPUTarget
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
Definition: AMDGPUTargetInfo.cpp:20
llvm::Legalizer
Definition: Legalizer.h:36
llvm::AMDGPUFunctionArgInfo::WorkItemIDX
ArgDescriptor WorkItemIDX
Definition: AMDGPUArgumentUsageInfo.h:148
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
EnableAMDGPUAliasAnalysis
static cl::opt< bool > EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden, cl::desc("Enable AMDGPU Alias Analysis"), cl::init(true))
EnableLowerKernelArguments
static cl::opt< bool > EnableLowerKernelArguments("amdgpu-ir-lower-kernel-arguments", cl::desc("Lower kernel argument loads in IR pass"), cl::init(true), cl::Hidden)
EnableLoadStoreVectorizer
static cl::opt< bool > EnableLoadStoreVectorizer("amdgpu-load-store-vectorizer", cl::desc("Enable load store vectorizer"), cl::init(true), cl::Hidden)
AMDGPUTargetInfo.h
llvm::createAMDGPULowerModuleLDSPass
ModulePass * createAMDGPULowerModuleLDSPass()
R600TargetMachine.h
llvm::FuncletLayoutID
char & FuncletLayoutID
This pass lays out funclets contiguously.
Definition: FuncletLayout.cpp:39
AMDGPUMacroFusion.h
llvm::initializeAMDGPUUseNativeCallsPass
void initializeAMDGPUUseNativeCallsPass(PassRegistry &)
llvm::createSIInsertWaitcntsPass
FunctionPass * createSIInsertWaitcntsPass()
Definition: SIInsertWaitcnts.cpp:803
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
EnableLDSReplaceWithPointer
static cl::opt< bool > EnableLDSReplaceWithPointer("amdgpu-enable-lds-replace-with-pointer", cl::desc("Enable LDS replace with pointer pass"), cl::init(false), cl::Hidden)
llvm::PassBuilder
This class provides access to building LLVM's passes.
Definition: PassBuilder.h:94
EnableRegReassign
static cl::opt< bool > EnableRegReassign("amdgpu-reassign-regs", cl::desc("Enable register reassign optimizations on gfx10+"), cl::init(true), cl::Hidden)
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
llvm::yaml::SIMode::FP64FP16InputDenormals
bool FP64FP16InputDenormals
Definition: SIMachineFunctionInfo.h:235
llvm::createAMDGPUAnnotateUniformValues
FunctionPass * createAMDGPUAnnotateUniformValues()
Definition: AMDGPUAnnotateUniformValues.cpp:122
llvm::initializeAMDGPUUnifyDivergentExitNodesPass
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:782
useDefaultRegisterAllocator
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Definition: TargetPassConfig.cpp:1126
llvm::AMDGPUPromoteAllocaPass
Definition: AMDGPU.h:225
llvm::createGenericSchedPostRA
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
Definition: MachineScheduler.cpp:3646
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:33
llvm::AMDGPUTargetMachine::getNullPointerValue
static int64_t getNullPointerValue(unsigned AddrSpace)
Get the integer value of a null pointer in the given address space.
Definition: AMDGPUTargetMachine.cpp:751
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1296
llvm::ScheduleDAGMI::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:323
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::Triple::r600
@ r600
Definition: Triple.h:73
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createUnifyLoopExitsPass
FunctionPass * createUnifyLoopExitsPass()
Definition: UnifyLoopExits.cpp:55
llvm::GCNIterativeScheduler
Definition: GCNIterativeScheduler.h:29
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: AMDGPUTargetMachine.cpp:389
llvm::SourceMgr::getMainFileID
unsigned getMainFileID() const
Definition: SourceMgr.h:132
AMDGPUTargetObjectFile.h
llvm::AMDGPULowerKernelAttributesPass
Definition: AMDGPU.h:115
GVN.h
llvm::createAMDGPUPropagateAttributesLatePass
ModulePass * createAMDGPUPropagateAttributesLatePass(const TargetMachine *)
Definition: AMDGPUPropagateAttributes.cpp:406
llvm::initializeSIMemoryLegalizerPass
void initializeSIMemoryLegalizerPass(PassRegistry &)
llvm::createLoadStoreVectorizerPass
Pass * createLoadStoreVectorizerPass()
Create a legacy pass manager instance of the LoadStoreVectorizer pass.
llvm::initializeAMDGPUResourceUsageAnalysisPass
void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &)
EnableDPPCombine
static cl::opt< bool > EnableDPPCombine("amdgpu-dpp-combine", cl::desc("Enable DPP combiner"), cl::init(true))
llvm::createAMDGPULowerIntrinsicsPass
ModulePass * createAMDGPULowerIntrinsicsPass()
Definition: AMDGPULowerIntrinsics.cpp:175
llvm::AMDGPUPassConfig::addCodeGenPrepare
void addCodeGenPrepare() override
Add pass to prepare the LLVM IR for code generation.
Definition: AMDGPUTargetMachine.cpp:1043
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::StackMapLivenessID
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
Definition: StackMapLivenessAnalysis.cpp:86
llvm::createAMDGPUAnnotateKernelFeaturesPass
Pass * createAMDGPUAnnotateKernelFeaturesPass()
Definition: AMDGPUAnnotateKernelFeatures.cpp:137
llvm::initializeAMDGPUReplaceLDSUseWithPointerPass
void initializeAMDGPUReplaceLDSUseWithPointerPass(PassRegistry &)
PatternMatch.h
llvm::AMDGPUTargetMachine::~AMDGPUTargetMachine
~AMDGPUTargetMachine() override
llvm::AMDGPUTargetMachine::getSubtargetImpl
const TargetSubtargetInfo * getSubtargetImpl() const
llvm::createSinkingPass
FunctionPass * createSinkingPass()
Definition: Sink.cpp:279
llvm::Triple::getArch
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:337
llvm::createSpeculativeExecutionPass
FunctionPass * createSpeculativeExecutionPass()
Definition: SpeculativeExecution.cpp:325
Utils.h
llvm::SILoadStoreOptimizerID
char & SILoadStoreOptimizerID
Definition: SILoadStoreOptimizer.cpp:734
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:305
llvm::RegisterPassParser
RegisterPassParser class - Handle the addition of new machine passes.
Definition: MachinePassRegistry.h:135
llvm::None
const NoneType None
Definition: None.h:24
llvm::Value::use_empty
bool use_empty() const
Definition: Value.h:344
llvm::createAMDGPUExportClusteringDAGMutation
std::unique_ptr< ScheduleDAGMutation > createAMDGPUExportClusteringDAGMutation()
Definition: AMDGPUExportClustering.cpp:144
llvm::initializeSIOptimizeVGPRLiveRangePass
void initializeSIOptimizeVGPRLiveRangePass(PassRegistry &)
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:53
llvm::AMDGPU::isEntryFunctionCC
bool isEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1599
llvm::SmallString< 128 >
llvm::SourceMgr::getMemoryBuffer
const MemoryBuffer * getMemoryBuffer(unsigned i) const
Definition: SourceMgr.h:125
llvm::createFunctionInliningPass
Pass * createFunctionInliningPass()
createFunctionInliningPass - Return a new pass object that uses a heuristic to inline direct function...
Definition: InlineSimple.cpp:91
llvm::legacy::PassManagerBase::add
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
llvm::MemoryBuffer::getBufferIdentifier
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
Definition: MemoryBuffer.h:75
llvm::createAMDGPUAAWrapperPass
ImmutablePass * createAMDGPUAAWrapperPass()
Definition: AMDGPUAliasAnalysis.cpp:33
llvm::PassManagerBuilder
PassManagerBuilder - This class is used to set up a standard optimization sequence for languages like...
Definition: PassManagerBuilder.h:57
llvm::createLowerSwitchPass
FunctionPass * createLowerSwitchPass()
Definition: LowerSwitch.cpp:587
llvm::createAMDGPUPrintfRuntimeBinding
ModulePass * createAMDGPUPrintfRuntimeBinding()
Definition: AMDGPUPrintfRuntimeBinding.cpp:93
AMDGPUTargetTransformInfo.h
llvm::AMDGPUPassConfig::addInstSelector
bool addInstSelector() override
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
Definition: AMDGPUTargetMachine.cpp:1074
PB
PassBuilder PB(Machine, PassOpts->PTO, None, &PIC)
Passes.h
llvm::Triple::AMDHSA
@ AMDHSA
Definition: Triple.h:199
llvm::VirtRegRewriterID
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:227
llvm::createAMDGPUAlwaysInlinePass
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Definition: AMDGPUAlwaysInlinePass.cpp:163
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::SmallString::append
void append(StringRef RHS)
Append from a StringRef.
Definition: SmallString.h:68
llvm::initializeSILowerSGPRSpillsPass
void initializeSILowerSGPRSpillsPass(PassRegistry &)
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::PassBuilder::registerPipelineEarlySimplificationEPCallback
void registerPipelineEarlySimplificationEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:466
llvm::AMDGPUTargetMachine::getFeatureString
StringRef getFeatureString(const Function &F) const
Definition: AMDGPUTargetMachine.cpp:517
OptVGPRLiveRange
static cl::opt< bool > OptVGPRLiveRange("amdgpu-opt-vgpr-liverange", cl::desc("Enable VGPR liverange optimizations for if-else structure"), cl::init(true), cl::Hidden)
llvm::cl::opt
Definition: CommandLine.h:1392
llvm::createLCSSAPass
Pass * createLCSSAPass()
Definition: LCSSA.cpp:485
llvm::createModuleToFunctionPassAdaptor
ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: PassManager.h:1224
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
OptExecMaskPreRA
static cl::opt< bool > OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden, cl::desc("Run pre-RA exec mask optimizations"), cl::init(true))
llvm::GCLoweringID
char & GCLoweringID
GCLowering Pass - Used by gc.root to perform its default lowering operations.
Definition: GCRootLowering.cpp:85
llvm::yaml::SIMachineFunctionInfo::ScratchRSrcReg
StringValue ScratchRSrcReg
Definition: SIMachineFunctionInfo.h:289
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::AMDGPUAS::GLOBAL_ADDRESS
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:359
llvm::AMDGPUUnifyDivergentExitNodesID
char & AMDGPUUnifyDivergentExitNodesID
Definition: AMDGPUUnifyDivergentExitNodes.cpp:79
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::initializeSIInsertWaitcntsPass
void initializeSIInsertWaitcntsPass(PassRegistry &)
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::initializeSIAnnotateControlFlowPass
void initializeSIAnnotateControlFlowPass(PassRegistry &)
llvm::createGenericSchedLive
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3489
llvm::AMDGPUFunctionArgInfo::WorkGroupIDZ
ArgDescriptor WorkGroupIDZ
Definition: AMDGPUArgumentUsageInfo.h:135
llvm::RegisterRegAllocBase< RegisterRegAlloc >::FunctionPassCtor
FunctionPass *(*)() FunctionPassCtor
Definition: RegAllocRegistry.h:32
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
llvm::DetectDeadLanesID
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
Definition: DetectDeadLanes.cpp:125
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::TargetMachine::getMCSubtargetInfo
const MCSubtargetInfo * getMCSubtargetInfo() const
Definition: TargetMachine.h:209
llvm::AMDGPUFunctionArgInfo::PrivateSegmentBuffer
ArgDescriptor PrivateSegmentBuffer
Definition: AMDGPUArgumentUsageInfo.h:124
llvm::SIMachineFunctionInfo::reserveWWMRegister
void reserveWWMRegister(Register Reg)
Definition: SIMachineFunctionInfo.h:552
llvm::createAMDGPUAtomicOptimizerPass
FunctionPass * createAMDGPUAtomicOptimizerPass()
Definition: AMDGPUAtomicOptimizer.cpp:707
llvm::initializeR600VectorRegMergerPass
void initializeR600VectorRegMergerPass(PassRegistry &)
IPO.h
llvm::SIPeepholeSDWAID
char & SIPeepholeSDWAID
Definition: SIPeepholeSDWA.cpp:191
llvm::SIMachineFunctionInfo::initializeBaseYamlFields
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
Definition: SIMachineFunctionInfo.cpp:606
llvm::createGlobalDCEPass
ModulePass * createGlobalDCEPass()
createGlobalDCEPass - This transform is designed to eliminate unreachable internal globals (functions...
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::GCNTTIImpl
Definition: AMDGPUTargetTransformInfo.h:59
llvm::SIFixVGPRCopiesID
char & SIFixVGPRCopiesID
Definition: SIFixVGPRCopies.cpp:45
llvm::initializeAMDGPURewriteOutArgumentsPass
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
CGSCCPassManager.h
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:125
llvm::GCNIterativeScheduler::SCHEDULE_MINREGFORCED
@ SCHEDULE_MINREGFORCED
Definition: GCNIterativeScheduler.h:35
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::AMDGPUSimplifyLibCallsPass
Definition: AMDGPU.h:61
llvm::AMDGPUPassConfig::createMachineScheduler
ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const override
Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this ...
Definition: AMDGPUTargetMachine.cpp:1085
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:854
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::TargetPassConfig::addOptimizedRegAlloc
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
Definition: TargetPassConfig.cpp:1452
llvm::AMDGPUFunctionArgInfo::PrivateSegmentWaveByteOffset
ArgDescriptor PrivateSegmentWaveByteOffset
Definition: AMDGPUArgumentUsageInfo.h:137
llvm::SIFormMemoryClausesID
char & SIFormMemoryClausesID
Definition: SIFormMemoryClauses.cpp:91
llvm::LiveVariablesID
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
Definition: LiveVariables.cpp:45
LateCFGStructurize
static cl::opt< bool, true > LateCFGStructurize("amdgpu-late-structurize", cl::desc("Enable late CFG structurization"), cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG), cl::Hidden)
TargetPassConfig.h
llvm::yaml::SIMachineFunctionInfo::WWMReservedRegs
SmallVector< StringValue > WWMReservedRegs
Definition: SIMachineFunctionInfo.h:287
llvm::createExternalAAWrapperPass
ImmutablePass * createExternalAAWrapperPass(std::function< void(Pass &, Function &, AAResults &)> Callback)
A wrapper pass around a callback which can be used to populate the AAResults in the AAResultsWrapperP...
llvm::SIFixSGPRCopiesID
char & SIFixSGPRCopiesID
Definition: SIFixSGPRCopies.cpp:121
llvm::AMDGPUFunctionArgInfo::WorkGroupIDY
ArgDescriptor WorkGroupIDY
Definition: AMDGPUArgumentUsageInfo.h:134
Localizer.h
llvm::MachineCSEID
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:157
llvm::GCNDPPCombineID
char & GCNDPPCombineID
Definition: GCNDPPCombine.cpp:111
llvm::TargetPassConfig::addCodeGenPrepare
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: TargetPassConfig.cpp:996
llvm::AMDGPU::SIModeRegisterDefaults::DX10Clamp
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
Definition: AMDGPUBaseInfo.h:991
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SIInsertHardClausesID
char & SIInsertHardClausesID
Definition: SIInsertHardClauses.cpp:221
GCNMinRegSchedRegistry
static MachineSchedRegistry GCNMinRegSchedRegistry("gcn-minreg", "Run GCN iterative scheduler for minimal register usage (experimental)", createMinRegScheduler)
llvm::AMDGPUPassConfig::addStraightLineScalarOptimizationPasses
void addStraightLineScalarOptimizationPasses()
Definition: AMDGPUTargetMachine.cpp:936
llvm::AMDGPU::isFlatGlobalAddrSpace
bool isFlatGlobalAddrSpace(unsigned AS)
Definition: AMDGPU.h:406
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16InputDenormals
bool FP64FP16InputDenormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
Definition: AMDGPUBaseInfo.h:1000
llvm::AMDGPUTargetMachine::getPredicatedAddrSpace
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const override
If the specified predicate checks whether a generic pointer falls within a specified address space,...
Definition: AMDGPUTargetMachine.cpp:785
llvm::getTheGCNTarget
Target & getTheGCNTarget()
The target for GCN GPUs.
Definition: AMDGPUTargetInfo.cpp:25
llvm::AMDGPUPassConfig::getAMDGPUTargetMachine
AMDGPUTargetMachine & getAMDGPUTargetMachine() const
Definition: AMDGPUTargetMachine.h:110
llvm::initializeSIOptimizeExecMaskingPass
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
llvm::initializeSIPostRABundlerPass
void initializeSIPostRABundlerPass(PassRegistry &)
llvm::SIScheduleDAGMI
Definition: SIMachineScheduler.h:425
llvm::PassBuilder::registerPipelineParsingCallback
void registerPipelineParsingCallback(const std::function< bool(StringRef Name, CGSCCPassManager &, ArrayRef< PipelineElement >)> &C)
{{@ Register pipeline parsing callbacks with this pass builder instance.
Definition: PassBuilder.h:539
llvm::initializeAMDGPUAAWrapperPassPass
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:271
llvm::initializeAMDGPUCodeGenPreparePass
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
llvm::AMDGPUPassConfig::AMDGPUPassConfig
AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
Definition: AMDGPUTargetMachine.cpp:918
llvm::createAMDGPUOpenCLEnqueuedBlockLoweringPass
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
llvm::initializeGCNNSAReassignPass
void initializeGCNNSAReassignPass(PassRegistry &)
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::AMDGPUTargetMachine::EnableLowerModuleLDS
static bool EnableLowerModuleLDS
Definition: AMDGPUTargetMachine.h:38
llvm::yaml::StringValue
A wrapper around std::string which contains a source range that's being set during parsing.
Definition: MIRYamlMapping.h:34
llvm::GlobalDCEPass
Pass to remove unused function declarations.
Definition: GlobalDCE.h:36
llvm::PatchableFunctionID
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
Definition: PatchableFunction.cpp:96
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
IterativeGCNMaxOccupancySchedRegistry
static MachineSchedRegistry IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental", "Run GCN scheduler to maximize occupancy (experimental)", createIterativeGCNMaxOccupancyMachineScheduler)
AMDGPUExportClustering.h
llvm::PatternMatch::m_Value
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:76
llvm::AMDGPUFunctionArgInfo::WorkItemIDZ
ArgDescriptor WorkItemIDZ
Definition: AMDGPUArgumentUsageInfo.h:150
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::createSIShrinkInstructionsPass
FunctionPass * createSIShrinkInstructionsPass()
llvm::createAMDGPUMachineCFGStructurizerPass
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
Definition: AMDGPUMachineCFGStructurizer.cpp:2851
llvm::GCNTargetMachine
Definition: AMDGPUTargetMachine.h:73
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:481
llvm::ScheduleDAG::TRI
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:559
llvm::TargetPassConfig::addPass
AnalysisID addPass(AnalysisID PassID)
Utilities for targets to add passes to the pass manager.
Definition: TargetPassConfig.cpp:782
llvm::AMDGPUAS::UNKNOWN_ADDRESS_SPACE
@ UNKNOWN_ADDRESS_SPACE
Definition: AMDGPU.h:399
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::Constant::removeDeadConstantUsers
void removeDeadConstantUsers() const
If there are any dead constant users dangling off of this constant, remove them.
Definition: Constants.cpp:742
llvm::initializeSIFormMemoryClausesPass
void initializeSIFormMemoryClausesPass(PassRegistry &)
computeDataLayout
static StringRef computeDataLayout(const Triple &TT)
Definition: AMDGPUTargetMachine.cpp:454
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::initializeAMDGPUExternalAAWrapperPass
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)
AMDGPU.h
llvm::yaml::SIMachineFunctionInfo::StackPtrOffsetReg
StringValue StackPtrOffsetReg
Definition: SIMachineFunctionInfo.h:291
SimplifyLibCalls.h
llvm::AMDGPUPassConfig::addPreISel
bool addPreISel() override
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
Definition: AMDGPUTargetMachine.cpp:1068
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
GlobalDCE.h
llvm::yaml::SIMachineFunctionInfo::Mode
SIMode Mode
Definition: SIMachineFunctionInfo.h:297
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:75
llvm::createAMDGPURegBankCombiner
FunctionPass * createAMDGPURegBankCombiner(bool IsOptNone)
Definition: AMDGPURegBankCombiner.cpp:486
EnablePreRAOptimizations
static cl::opt< bool > EnablePreRAOptimizations("amdgpu-enable-pre-ra-optimizations", cl::desc("Enable Pre-RA optimizations pass"), cl::init(true), cl::Hidden)
IRTranslator.h
llvm::TargetMachine::getTargetFeatureString
StringRef getTargetFeatureString() const
Definition: TargetMachine.h:128
EarlyInlineAll
static cl::opt< bool > EarlyInlineAll("amdgpu-early-inline-all", cl::desc("Inline all functions early"), cl::init(false), cl::Hidden)
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
AMDGPUMFMAClustering.h
llvm::once_flag
std::once_flag once_flag
Definition: Threading.h:57
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::AMDGPUFunctionArgInfo::ImplicitBufferPtr
ArgDescriptor ImplicitBufferPtr
Definition: AMDGPUArgumentUsageInfo.h:144
llvm::SIWholeQuadModeID
char & SIWholeQuadModeID
Definition: SIWholeQuadMode.cpp:265
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
EnableSROA
static cl::opt< bool > EnableSROA("amdgpu-sroa", cl::desc("Run SROA after promote alloca pass"), cl::ReallyHidden, cl::init(true))
llvm::initializeAMDGPULowerKernelAttributesPass
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:497
llvm::AMDGPUPassConfig::getCSEConfig
std::unique_ptr< CSEConfigBase > getCSEConfig() const override
Returns the CSEConfig object to use for the current optimization level.
Definition: AMDGPUTargetMachine.cpp:854
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
llvm::initializeAMDGPUAnnotateUniformValuesPass
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
llvm::RenameIndependentSubregsID
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
Definition: RenameIndependentSubregs.cpp:113
llvm::AMDGPUPrintfRuntimeBindingPass
Definition: AMDGPU.h:265
llvm::AMDGPUReplaceLDSUseWithPointerPass
Definition: AMDGPU.h:147
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::createStructurizeCFGPass
Pass * createStructurizeCFGPass(bool SkipUniformRegions=false)
When SkipUniformRegions is true the structizer will not structurize regions that only contain uniform...
Definition: StructurizeCFG.cpp:1107
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: AMDGPUBaseInfo.h:1001
llvm::GCNTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: AMDGPUTargetMachine.cpp:1386
llvm::PassManager< Module >
llvm::createAMDGPULowerKernelAttributesPass
ModulePass * createAMDGPULowerKernelAttributesPass()
Definition: AMDGPULowerKernelAttributes.cpp:248
llvm::initializeSIFixSGPRCopiesPass
void initializeSIFixSGPRCopiesPass(PassRegistry &)
llvm::PerFunctionMIParsingState
Definition: MIParser.h:162
llvm::AMDGPUFunctionArgInfo::WorkGroupInfo
ArgDescriptor WorkGroupInfo
Definition: AMDGPUArgumentUsageInfo.h:136
llvm::createAMDGPUPromoteAllocaToVector
FunctionPass * createAMDGPUPromoteAllocaToVector()
Definition: AMDGPUPromoteAlloca.cpp:1146
llvm::OptimizationLevel::getSpeedupLevel
unsigned getSpeedupLevel() const
Definition: OptimizationLevel.h:121
llvm::initializeAMDGPULowerModuleLDSPass
void initializeAMDGPULowerModuleLDSPass(PassRegistry &)
LLVM_READNONE
#define LLVM_READNONE
Definition: Compiler.h:199
createIterativeILPMachineScheduler
static ScheduleDAGInstrs * createIterativeILPMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:422
llvm::parseNamedRegisterReference
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
Definition: MIParser.cpp:3456
EnableEarlyIfConversion
static cl::opt< bool > EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(false))
llvm::initializeSIFixVGPRCopiesPass
void initializeSIFixVGPRCopiesPass(PassRegistry &)
llvm::yaml::SIMode::DX10Clamp
bool DX10Clamp
Definition: SIMachineFunctionInfo.h:232
llvm::initializeAMDGPUPromoteAllocaToVectorPass
void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry &)
EnableScalarIRPasses
static cl::opt< bool > EnableScalarIRPasses("amdgpu-scalar-ir-passes", cl::desc("Enable scalar IR passes"), cl::init(true), cl::Hidden)
llvm::AMDGPUPromoteKernelArgumentsPass
Definition: AMDGPU.h:106
llvm::initializeSIPreEmitPeepholePass
void initializeSIPreEmitPeepholePass(PassRegistry &)
createIterativeGCNMaxOccupancyMachineScheduler
static ScheduleDAGInstrs * createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:409
llvm::call_once
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:87
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
llvm::GCNTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: AMDGPUTargetMachine.cpp:846
llvm::AMDGPUTargetMachine::registerPassBuilderCallbacks
void registerPassBuilderCallbacks(PassBuilder &PB) override
Allow the target to modify the pass pipeline with New Pass Manager (similar to adjustPassManager for ...
Definition: AMDGPUTargetMachine.cpp:613
EnablePromoteKernelArguments
static cl::opt< bool > EnablePromoteKernelArguments("amdgpu-enable-promote-kernel-arguments", cl::desc("Enable promotion of flat kernel pointer arguments to global"), cl::Hidden, cl::init(true))
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1303
llvm::AMDGPUPassConfig::addEarlyCSEOrGVNPass
void addEarlyCSEOrGVNPass()
Definition: AMDGPUTargetMachine.cpp:929
llvm::createAMDGPUPropagateAttributesEarlyPass
FunctionPass * createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *)
Definition: AMDGPUPropagateAttributes.cpp:401
llvm::AMDGPUPropagateAttributesEarlyPass
Definition: AMDGPU.h:123
llvm::initializeSIModeRegisterPass
void initializeSIModeRegisterPass(PassRegistry &)
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
llvm::createLoadClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1573
RegBankSelect.h
llvm::ScheduleDAG::TII
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
GCNMaxOccupancySchedRegistry
static MachineSchedRegistry GCNMaxOccupancySchedRegistry("gcn-max-occupancy", "Run GCN scheduler to maximize occupancy", createGCNMaxOccupancyMachineScheduler)
llvm::createAMDGPULowerKernelArgumentsPass
FunctionPass * createAMDGPULowerKernelArgumentsPass()
Definition: AMDGPULowerKernelArguments.cpp:248
llvm::AMDGPUTargetMachine::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: AMDGPUTargetMachine.cpp:759
llvm::PassManagerBuilder::EP_ModuleOptimizerEarly
@ EP_ModuleOptimizerEarly
EP_ModuleOptimizerEarly - This extension point allows adding passes just before the main module-level...
Definition: PassManagerBuilder.h:74
llvm::createSIModeRegisterPass
FunctionPass * createSIModeRegisterPass()
Definition: SIModeRegister.cpp:158
llvm::OptimizationLevel
Definition: OptimizationLevel.h:22
llvm::ArgDescriptor::createRegister
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:44
PassManager.h
llvm::createInternalizePass
ModulePass * createInternalizePass(std::function< bool(const GlobalValue &)> MustPreserveGV)
createInternalizePass - This pass loops over all of the functions in the input module,...
Definition: Internalize.cpp:312
llvm::AMDGPUAS::PRIVATE_ADDRESS
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:364
llvm::SourceMgr::DK_Error
@ DK_Error
Definition: SourceMgr.h:34
llvm::createAMDGPUReplaceLDSUseWithPointerPass
ModulePass * createAMDGPUReplaceLDSUseWithPointerPass()
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:639
llvm::AMDGPUTargetMachine::adjustPassManager
void adjustPassManager(PassManagerBuilder &) override
Allow the target to modify the pass manager, e.g.
Definition: AMDGPUTargetMachine.cpp:535
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:405
llvm::TargetPassConfig::disablePass
void disablePass(AnalysisID PassID)
Allow the target to disable a specific standard pass by default.
Definition: TargetPassConfig.h:196
llvm::DeadMachineInstructionElimID
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
Definition: DeadMachineInstructionElim.cpp:56
llvm::PerFunctionMIParsingState::MF
MachineFunction & MF
Definition: MIParser.h:164
GCNILPSchedRegistry
static MachineSchedRegistry GCNILPSchedRegistry("gcn-ilp", "Run GCN iterative scheduler for ILP scheduling (experimental)", createIterativeILPMachineScheduler)
llvm::AnalysisManager::registerPass
bool registerPass(PassBuilderT &&PassBuilder)
Register an analysis pass with the manager.
Definition: PassManager.h:842
llvm::AMDGPUFunctionArgInfo::KernargSegmentPtr
ArgDescriptor KernargSegmentPtr
Definition: AMDGPUArgumentUsageInfo.h:127
llvm::AMDGPUAS::CONSTANT_ADDRESS
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:362
llvm::createAMDGPUPromoteAlloca
FunctionPass * createAMDGPUPromoteAlloca()
Definition: AMDGPUPromoteAlloca.cpp:1142
llvm::initializeAMDGPUPrintfRuntimeBindingPass
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry &)
llvm::AMDGPUAS::LOCAL_ADDRESS
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:363
llvm::AAManager::registerFunctionAnalysis
void registerFunctionAnalysis()
Register a specific AA result.
Definition: AliasAnalysis.h:1304
llvm::AMDGPUPassConfig::isPassEnabled
bool isPassEnabled(const cl::opt< bool > &Opt, CodeGenOpt::Level Level=CodeGenOpt::Default) const
Check if a pass is enabled given Opt option.
Definition: AMDGPUTargetMachine.h:131
llvm::BranchRelaxationPassID
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
Definition: BranchRelaxation.cpp:118
llvm::initializeAMDGPUPreLegalizerCombinerPass
void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &)
llvm::createAMDGPUCodeGenPreparePass
FunctionPass * createAMDGPUCodeGenPreparePass()
Definition: AMDGPUCodeGenPrepare.cpp:1465
llvm::createAMDGPUPromoteKernelArgumentsPass
FunctionPass * createAMDGPUPromoteKernelArgumentsPass()
Definition: AMDGPUPromoteKernelArguments.cpp:203
llvm::RegisterRegAllocBase
RegisterRegAllocBase class - Track the registration of register allocators.
Definition: RegAllocRegistry.h:30
llvm::MachineSchedulerID
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
Definition: MachineScheduler.cpp:213
llvm::AMDGPUTargetMachine::EnableFunctionCalls
static bool EnableFunctionCalls
Definition: AMDGPUTargetMachine.h:37
llvm::initializeAMDGPUAttributorPass
void initializeAMDGPUAttributorPass(PassRegistry &)
Legalizer.h
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::createLICMPass
Pass * createLICMPass()
Definition: LICM.cpp:345
llvm::GCNNSAReassignID
char & GCNNSAReassignID
Definition: GCNNSAReassign.cpp:105
llvm::TargetMachine::getTargetCPU
StringRef getTargetCPU() const
Definition: TargetMachine.h:127
llvm::PassManagerBuilder::EP_EarlyAsPossible
@ EP_EarlyAsPossible
EP_EarlyAsPossible - This extension point allows adding passes before any other transformations,...
Definition: PassManagerBuilder.h:70
llvm::initializeAMDGPUAnnotateKernelFeaturesPass
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:197
llvm::AMDGPUFunctionArgInfo::WorkItemIDY
ArgDescriptor WorkItemIDY
Definition: AMDGPUArgumentUsageInfo.h:149
llvm::createAMDGPUPreLegalizeCombiner
FunctionPass * createAMDGPUPreLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPreLegalizerCombiner.cpp:298
llvm::AMDGPUTargetMachine::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const override
If the specified generic pointer could be assumed as a pointer to a specific address space,...
Definition: AMDGPUTargetMachine.cpp:765
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
N
#define N
llvm::createStraightLineStrengthReducePass
FunctionPass * createStraightLineStrengthReducePass()
Definition: StraightLineStrengthReduce.cpp:268
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:348
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:126
llvm::GCNPreRAOptimizationsID
char & GCNPreRAOptimizationsID
Definition: GCNPreRAOptimizations.cpp:79
llvm::initializeSILoadStoreOptimizerPass
void initializeSILoadStoreOptimizerPass(PassRegistry &)
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::PatternMatch
Definition: PatternMatch.h:47
llvm::IRTranslator
Definition: IRTranslator.h:62
llvm::PassBuilder::registerCGSCCOptimizerLateEPCallback
void registerCGSCCOptimizerLateEPCallback(const std::function< void(CGSCCPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:436
llvm::initializeAMDGPURegBankCombinerPass
void initializeAMDGPURegBankCombinerPass(PassRegistry &)
RegName
#define RegName(no)
llvm::createSIAnnotateControlFlowPass
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
Definition: SIAnnotateControlFlow.cpp:389
Vectorize.h
llvm::yaml::SIMode::IEEE
bool IEEE
Definition: SIMachineFunctionInfo.h:231
llvm::initializeAMDGPUCtorDtorLoweringPass
void initializeAMDGPUCtorDtorLoweringPass(PassRegistry &)
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:42
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::SIFoldOperandsID
char & SIFoldOperandsID
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::createBasicRegisterAllocator
FunctionPass * createBasicRegisterAllocator()
BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...
Definition: RegAllocBasic.cpp:332
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::MIPatternMatch::m_Not
BinaryOp_match< SrcTy, SpecificConstantMatch, TargetOpcode::G_XOR, true > m_Not(const SrcTy &&Src)
Matches a register not-ed by a G_XOR.
Definition: MIPatternMatch.h:696
llvm::EarlyMachineLICMID
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
Definition: MachineLICM.cpp:298
llvm::AMDGPUTargetMachine::getGPUName
StringRef getGPUName(const Function &F) const
Definition: AMDGPUTargetMachine.cpp:512
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:244
llvm::cl::desc
Definition: CommandLine.h:405
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:390
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::PassManagerBuilder::EP_CGSCCOptimizerLate
@ EP_CGSCCOptimizerLate
EP_CGSCCOptimizerLate - This extension point allows adding CallGraphSCC passes at the end of the main...
Definition: PassManagerBuilder.h:115
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::CodeGenOpt::Less
@ Less
Definition: CodeGen.h:54
llvm::AMDGPUTargetMachine::AMDGPUTargetMachine
AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL)
Definition: AMDGPUTargetMachine.cpp:487
llvm::TargetPassConfig::addFastRegAlloc
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Definition: TargetPassConfig.cpp:1442
llvm::AMDGPUPerfHintAnalysisID
char & AMDGPUPerfHintAnalysisID
Definition: AMDGPUPerfHintAnalysis.cpp:58
TargetRegistry.h
llvm::createSROAPass
FunctionPass * createSROAPass()
Definition: SROA.cpp:4809
llvm::AMDGPUPropagateAttributesLatePass
Definition: AMDGPU.h:135
EnableLibCallSimplify
static cl::opt< bool > EnableLibCallSimplify("amdgpu-simplify-libcall", cl::desc("Enable amdgpu library simplifications"), cl::init(true), cl::Hidden)
InitializePasses.h
llvm::yaml::SIMode::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: SIMachineFunctionInfo.h:236
llvm::SIOptimizeExecMaskingPreRAID
char & SIOptimizeExecMaskingPreRAID
Definition: SIOptimizeExecMaskingPreRA.cpp:75
llvm::createGCNMCRegisterInfo
MCRegisterInfo * createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour)
Definition: AMDGPUMCTargetDesc.cpp:70
llvm::TargetMachine::MRI
std::unique_ptr< const MCRegisterInfo > MRI
Definition: TargetMachine.h:106
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AMDGPUTargetMachine::EnableLateStructurizeCFG
static bool EnableLateStructurizeCFG
Definition: AMDGPUTargetMachine.h:36
llvm::TargetPassConfig::addILPOpts
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
Definition: TargetPassConfig.h:371
llvm::TargetPassConfig::getOptLevel
CodeGenOpt::Level getOptLevel() const
Definition: TargetPassConfig.cpp:645
AMDGPUTargetMachine.h
llvm::GCNTargetMachine::createDefaultFuncInfoYAML
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
Definition: AMDGPUTargetMachine.cpp:1390
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:671
llvm::initializeSILowerControlFlowPass
void initializeSILowerControlFlowPass(PassRegistry &)
llvm::SILateBranchLoweringPassID
char & SILateBranchLoweringPassID
Definition: SILateBranchLowering.cpp:66
RegAllocRegistry.h
llvm::createAMDGPUSimplifyLibCallsPass
FunctionPass * createAMDGPUSimplifyLibCallsPass(const TargetMachine *)
Definition: AMDGPULibCalls.cpp:1659
MIParser.h
llvm::Localizer
This pass implements the localization mechanism described at the top of this file.
Definition: Localizer.h:43
llvm::createAMDGPUMacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createAMDGPUMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAMDGPUMacroFusionDAGMutation()); to AMDGPUPassConfig...
Definition: AMDGPUMacroFusion.cpp:62