LLVM  10.0.0svn
PPCMIPeephole.cpp
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1 //===-------------- PPCMIPeephole.cpp - MI Peephole Cleanups -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===---------------------------------------------------------------------===//
8 //
9 // This pass performs peephole optimizations to clean up ugly code
10 // sequences at the MachineInstruction layer. It runs at the end of
11 // the SSA phases, following VSX swap removal. A pass of dead code
12 // elimination follows this one for quick clean-up of any dead
13 // instructions introduced here. Although we could do this as callbacks
14 // from the generic peephole pass, this would have a couple of bad
15 // effects: it might remove optimization opportunities for VSX swap
16 // removal, and it would miss cleanups made possible following VSX
17 // swap removal.
18 //
19 //===---------------------------------------------------------------------===//
20 
21 #include "PPC.h"
22 #include "PPCInstrBuilder.h"
23 #include "PPCInstrInfo.h"
24 #include "PPCMachineFunctionInfo.h"
25 #include "PPCTargetMachine.h"
26 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Support/Debug.h"
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "ppc-mi-peepholes"
39 
40 STATISTIC(RemoveTOCSave, "Number of TOC saves removed");
41 STATISTIC(MultiTOCSaves,
42  "Number of functions with multiple TOC saves that must be kept");
43 STATISTIC(NumTOCSavesInPrologue, "Number of TOC saves placed in the prologue");
44 STATISTIC(NumEliminatedSExt, "Number of eliminated sign-extensions");
45 STATISTIC(NumEliminatedZExt, "Number of eliminated zero-extensions");
46 STATISTIC(NumOptADDLIs, "Number of optimized ADD instruction fed by LI");
47 STATISTIC(NumConvertedToImmediateForm,
48  "Number of instructions converted to their immediate form");
49 STATISTIC(NumFunctionsEnteredInMIPeephole,
50  "Number of functions entered in PPC MI Peepholes");
51 STATISTIC(NumFixedPointIterations,
52  "Number of fixed-point iterations converting reg-reg instructions "
53  "to reg-imm ones");
54 STATISTIC(NumRotatesCollapsed,
55  "Number of pairs of rotate left, clear left/right collapsed");
56 STATISTIC(NumEXTSWAndSLDICombined,
57  "Number of pairs of EXTSW and SLDI combined as EXTSWSLI");
58 
59 static cl::opt<bool>
60 FixedPointRegToImm("ppc-reg-to-imm-fixed-point", cl::Hidden, cl::init(true),
61  cl::desc("Iterate to a fixed point when attempting to "
62  "convert reg-reg instructions to reg-imm"));
63 
64 static cl::opt<bool>
65 ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(true),
66  cl::desc("Convert eligible reg+reg instructions to reg+imm"));
67 
68 static cl::opt<bool>
69  EnableSExtElimination("ppc-eliminate-signext",
70  cl::desc("enable elimination of sign-extensions"),
71  cl::init(false), cl::Hidden);
72 
73 static cl::opt<bool>
74  EnableZExtElimination("ppc-eliminate-zeroext",
75  cl::desc("enable elimination of zero-extensions"),
76  cl::init(false), cl::Hidden);
77 
78 namespace {
79 
80 struct PPCMIPeephole : public MachineFunctionPass {
81 
82  static char ID;
83  const PPCInstrInfo *TII;
84  MachineFunction *MF;
86 
87  PPCMIPeephole() : MachineFunctionPass(ID) {
89  }
90 
91 private:
95  uint64_t EntryFreq;
96 
97  // Initialize class variables.
98  void initialize(MachineFunction &MFParm);
99 
100  // Perform peepholes.
101  bool simplifyCode(void);
102 
103  // Perform peepholes.
104  bool eliminateRedundantCompare(void);
105  bool eliminateRedundantTOCSaves(std::map<MachineInstr *, bool> &TOCSaves);
106  bool combineSEXTAndSHL(MachineInstr &MI, MachineInstr *&ToErase);
107  bool emitRLDICWhenLoweringJumpTables(MachineInstr &MI);
108  void UpdateTOCSaves(std::map<MachineInstr *, bool> &TOCSaves,
109  MachineInstr *MI);
110 
111 public:
112 
113  void getAnalysisUsage(AnalysisUsage &AU) const override {
121  }
122 
123  // Main entry point for this pass.
124  bool runOnMachineFunction(MachineFunction &MF) override {
125  if (skipFunction(MF.getFunction()))
126  return false;
127  initialize(MF);
128  return simplifyCode();
129  }
130 };
131 
132 // Initialize class variables.
134  MF = &MFParm;
135  MRI = &MF->getRegInfo();
136  MDT = &getAnalysis<MachineDominatorTree>();
137  MPDT = &getAnalysis<MachinePostDominatorTree>();
138  MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
139  EntryFreq = MBFI->getEntryFreq();
140  TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
141  LLVM_DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n");
142  LLVM_DEBUG(MF->dump());
143 }
144 
145 static MachineInstr *getVRegDefOrNull(MachineOperand *Op,
146  MachineRegisterInfo *MRI) {
147  assert(Op && "Invalid Operand!");
148  if (!Op->isReg())
149  return nullptr;
150 
151  unsigned Reg = Op->getReg();
153  return nullptr;
154 
155  return MRI->getVRegDef(Reg);
156 }
157 
158 // This function returns number of known zero bits in output of MI
159 // starting from the most significant bit.
160 static unsigned
161 getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) {
162  unsigned Opcode = MI->getOpcode();
163  if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
164  Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo)
165  return MI->getOperand(3).getImm();
166 
167  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
168  MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm())
169  return MI->getOperand(3).getImm();
170 
171  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
172  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo ||
173  Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
174  MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
175  return 32 + MI->getOperand(3).getImm();
176 
177  if (Opcode == PPC::ANDIo) {
178  uint16_t Imm = MI->getOperand(2).getImm();
179  return 48 + countLeadingZeros(Imm);
180  }
181 
182  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo ||
183  Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo ||
184  Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8)
185  // The result ranges from 0 to 32.
186  return 58;
187 
188  if (Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo ||
189  Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo)
190  // The result ranges from 0 to 64.
191  return 57;
192 
193  if (Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
194  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
195  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
196  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8)
197  return 48;
198 
199  if (Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
200  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
201  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
202  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8)
203  return 56;
204 
205  if (TII->isZeroExtended(*MI))
206  return 32;
207 
208  return 0;
209 }
210 
211 // This function maintains a map for the pairs <TOC Save Instr, Keep>
212 // Each time a new TOC save is encountered, it checks if any of the existing
213 // ones are dominated by the new one. If so, it marks the existing one as
214 // redundant by setting it's entry in the map as false. It then adds the new
215 // instruction to the map with either true or false depending on if any
216 // existing instructions dominated the new one.
217 void PPCMIPeephole::UpdateTOCSaves(
218  std::map<MachineInstr *, bool> &TOCSaves, MachineInstr *MI) {
219  assert(TII->isTOCSaveMI(*MI) && "Expecting a TOC save instruction here");
221  "TOC-save removal only supported on ELFv2");
223 
224  MachineBasicBlock *Entry = &MF->front();
225  uint64_t CurrBlockFreq = MBFI->getBlockFreq(MI->getParent()).getFrequency();
226 
227  // If the block in which the TOC save resides is in a block that
228  // post-dominates Entry, or a block that is hotter than entry (keep in mind
229  // that early MachineLICM has already run so the TOC save won't be hoisted)
230  // we can just do the save in the prologue.
231  if (CurrBlockFreq > EntryFreq || MPDT->dominates(MI->getParent(), Entry))
232  FI->setMustSaveTOC(true);
233 
234  // If we are saving the TOC in the prologue, all the TOC saves can be removed
235  // from the code.
236  if (FI->mustSaveTOC()) {
237  for (auto &TOCSave : TOCSaves)
238  TOCSave.second = false;
239  // Add new instruction to map.
240  TOCSaves[MI] = false;
241  return;
242  }
243 
244  bool Keep = true;
245  for (auto It = TOCSaves.begin(); It != TOCSaves.end(); It++ ) {
246  MachineInstr *CurrInst = It->first;
247  // If new instruction dominates an existing one, mark existing one as
248  // redundant.
249  if (It->second && MDT->dominates(MI, CurrInst))
250  It->second = false;
251  // Check if the new instruction is redundant.
252  if (MDT->dominates(CurrInst, MI)) {
253  Keep = false;
254  break;
255  }
256  }
257  // Add new instruction to map.
258  TOCSaves[MI] = Keep;
259 }
260 
261 // Perform peephole optimizations.
262 bool PPCMIPeephole::simplifyCode(void) {
263  bool Simplified = false;
264  MachineInstr* ToErase = nullptr;
265  std::map<MachineInstr *, bool> TOCSaves;
266  const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
267  NumFunctionsEnteredInMIPeephole++;
268  if (ConvertRegReg) {
269  // Fixed-point conversion of reg/reg instructions fed by load-immediate
270  // into reg/imm instructions. FIXME: This is expensive, control it with
271  // an option.
272  bool SomethingChanged = false;
273  do {
274  NumFixedPointIterations++;
275  SomethingChanged = false;
276  for (MachineBasicBlock &MBB : *MF) {
277  for (MachineInstr &MI : MBB) {
278  if (MI.isDebugInstr())
279  continue;
280 
281  if (TII->convertToImmediateForm(MI)) {
282  // We don't erase anything in case the def has other uses. Let DCE
283  // remove it if it can be removed.
284  LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");
285  LLVM_DEBUG(MI.dump());
286  NumConvertedToImmediateForm++;
287  SomethingChanged = true;
288  Simplified = true;
289  continue;
290  }
291  }
292  }
293  } while (SomethingChanged && FixedPointRegToImm);
294  }
295 
296  for (MachineBasicBlock &MBB : *MF) {
297  for (MachineInstr &MI : MBB) {
298 
299  // If the previous instruction was marked for elimination,
300  // remove it now.
301  if (ToErase) {
302  ToErase->eraseFromParent();
303  ToErase = nullptr;
304  }
305 
306  // Ignore debug instructions.
307  if (MI.isDebugInstr())
308  continue;
309 
310  // Per-opcode peepholes.
311  switch (MI.getOpcode()) {
312 
313  default:
314  break;
315 
316  case PPC::STD: {
317  MachineFrameInfo &MFI = MF->getFrameInfo();
318  if (MFI.hasVarSizedObjects() ||
319  !MF->getSubtarget<PPCSubtarget>().isELFv2ABI())
320  break;
321  // When encountering a TOC save instruction, call UpdateTOCSaves
322  // to add it to the TOCSaves map and mark any existing TOC saves
323  // it dominates as redundant.
324  if (TII->isTOCSaveMI(MI))
325  UpdateTOCSaves(TOCSaves, &MI);
326  break;
327  }
328  case PPC::XXPERMDI: {
329  // Perform simplifications of 2x64 vector swaps and splats.
330  // A swap is identified by an immediate value of 2, and a splat
331  // is identified by an immediate value of 0 or 3.
332  int Immed = MI.getOperand(3).getImm();
333 
334  if (Immed != 1) {
335 
336  // For each of these simplifications, we need the two source
337  // regs to match. Unfortunately, MachineCSE ignores COPY and
338  // SUBREG_TO_REG, so for example we can see
339  // XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), immed.
340  // We have to look through chains of COPY and SUBREG_TO_REG
341  // to find the real source values for comparison.
342  unsigned TrueReg1 =
343  TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI);
344  unsigned TrueReg2 =
345  TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI);
346 
347  if (TrueReg1 == TrueReg2
349  MachineInstr *DefMI = MRI->getVRegDef(TrueReg1);
350  unsigned DefOpc = DefMI ? DefMI->getOpcode() : 0;
351 
352  // If this is a splat fed by a splatting load, the splat is
353  // redundant. Replace with a copy. This doesn't happen directly due
354  // to code in PPCDAGToDAGISel.cpp, but it can happen when converting
355  // a load of a double to a vector of 64-bit integers.
356  auto isConversionOfLoadAndSplat = [=]() -> bool {
357  if (DefOpc != PPC::XVCVDPSXDS && DefOpc != PPC::XVCVDPUXDS)
358  return false;
359  unsigned DefReg =
360  TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI);
362  MachineInstr *LoadMI = MRI->getVRegDef(DefReg);
363  if (LoadMI && LoadMI->getOpcode() == PPC::LXVDSX)
364  return true;
365  }
366  return false;
367  };
368  if (DefMI && (Immed == 0 || Immed == 3)) {
369  if (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat()) {
370  LLVM_DEBUG(dbgs() << "Optimizing load-and-splat/splat "
371  "to load-and-splat/copy: ");
372  LLVM_DEBUG(MI.dump());
373  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
374  MI.getOperand(0).getReg())
375  .add(MI.getOperand(1));
376  ToErase = &MI;
377  Simplified = true;
378  }
379  }
380 
381  // If this is a splat or a swap fed by another splat, we
382  // can replace it with a copy.
383  if (DefOpc == PPC::XXPERMDI) {
384  unsigned FeedImmed = DefMI->getOperand(3).getImm();
385  unsigned FeedReg1 =
386  TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI);
387  unsigned FeedReg2 =
388  TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI);
389 
390  if ((FeedImmed == 0 || FeedImmed == 3) && FeedReg1 == FeedReg2) {
391  LLVM_DEBUG(dbgs() << "Optimizing splat/swap or splat/splat "
392  "to splat/copy: ");
393  LLVM_DEBUG(MI.dump());
394  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
395  MI.getOperand(0).getReg())
396  .add(MI.getOperand(1));
397  ToErase = &MI;
398  Simplified = true;
399  }
400 
401  // If this is a splat fed by a swap, we can simplify modify
402  // the splat to splat the other value from the swap's input
403  // parameter.
404  else if ((Immed == 0 || Immed == 3)
405  && FeedImmed == 2 && FeedReg1 == FeedReg2) {
406  LLVM_DEBUG(dbgs() << "Optimizing swap/splat => splat: ");
407  LLVM_DEBUG(MI.dump());
408  MI.getOperand(1).setReg(DefMI->getOperand(1).getReg());
409  MI.getOperand(2).setReg(DefMI->getOperand(2).getReg());
410  MI.getOperand(3).setImm(3 - Immed);
411  Simplified = true;
412  }
413 
414  // If this is a swap fed by a swap, we can replace it
415  // with a copy from the first swap's input.
416  else if (Immed == 2 && FeedImmed == 2 && FeedReg1 == FeedReg2) {
417  LLVM_DEBUG(dbgs() << "Optimizing swap/swap => copy: ");
418  LLVM_DEBUG(MI.dump());
419  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
420  MI.getOperand(0).getReg())
421  .add(DefMI->getOperand(1));
422  ToErase = &MI;
423  Simplified = true;
424  }
425  } else if ((Immed == 0 || Immed == 3) && DefOpc == PPC::XXPERMDIs &&
426  (DefMI->getOperand(2).getImm() == 0 ||
427  DefMI->getOperand(2).getImm() == 3)) {
428  // Splat fed by another splat - switch the output of the first
429  // and remove the second.
430  DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
431  ToErase = &MI;
432  Simplified = true;
433  LLVM_DEBUG(dbgs() << "Removing redundant splat: ");
434  LLVM_DEBUG(MI.dump());
435  }
436  }
437  }
438  break;
439  }
440  case PPC::VSPLTB:
441  case PPC::VSPLTH:
442  case PPC::XXSPLTW: {
443  unsigned MyOpcode = MI.getOpcode();
444  unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2;
445  unsigned TrueReg =
446  TRI->lookThruCopyLike(MI.getOperand(OpNo).getReg(), MRI);
448  break;
449  MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
450  if (!DefMI)
451  break;
452  unsigned DefOpcode = DefMI->getOpcode();
453  auto isConvertOfSplat = [=]() -> bool {
454  if (DefOpcode != PPC::XVCVSPSXWS && DefOpcode != PPC::XVCVSPUXWS)
455  return false;
456  unsigned ConvReg = DefMI->getOperand(1).getReg();
458  return false;
459  MachineInstr *Splt = MRI->getVRegDef(ConvReg);
460  return Splt && (Splt->getOpcode() == PPC::LXVWSX ||
461  Splt->getOpcode() == PPC::XXSPLTW);
462  };
463  bool AlreadySplat = (MyOpcode == DefOpcode) ||
464  (MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) ||
465  (MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) ||
466  (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs) ||
467  (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::LXVWSX) ||
468  (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::MTVSRWS)||
469  (MyOpcode == PPC::XXSPLTW && isConvertOfSplat());
470  // If the instruction[s] that feed this splat have already splat
471  // the value, this splat is redundant.
472  if (AlreadySplat) {
473  LLVM_DEBUG(dbgs() << "Changing redundant splat to a copy: ");
474  LLVM_DEBUG(MI.dump());
475  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
476  MI.getOperand(0).getReg())
477  .add(MI.getOperand(OpNo));
478  ToErase = &MI;
479  Simplified = true;
480  }
481  // Splat fed by a shift. Usually when we align value to splat into
482  // vector element zero.
483  if (DefOpcode == PPC::XXSLDWI) {
484  unsigned ShiftRes = DefMI->getOperand(0).getReg();
485  unsigned ShiftOp1 = DefMI->getOperand(1).getReg();
486  unsigned ShiftOp2 = DefMI->getOperand(2).getReg();
487  unsigned ShiftImm = DefMI->getOperand(3).getImm();
488  unsigned SplatImm = MI.getOperand(2).getImm();
489  if (ShiftOp1 == ShiftOp2) {
490  unsigned NewElem = (SplatImm + ShiftImm) & 0x3;
491  if (MRI->hasOneNonDBGUse(ShiftRes)) {
492  LLVM_DEBUG(dbgs() << "Removing redundant shift: ");
493  LLVM_DEBUG(DefMI->dump());
494  ToErase = DefMI;
495  }
496  Simplified = true;
497  LLVM_DEBUG(dbgs() << "Changing splat immediate from " << SplatImm
498  << " to " << NewElem << " in instruction: ");
499  LLVM_DEBUG(MI.dump());
500  MI.getOperand(1).setReg(ShiftOp1);
501  MI.getOperand(2).setImm(NewElem);
502  }
503  }
504  break;
505  }
506  case PPC::XVCVDPSP: {
507  // If this is a DP->SP conversion fed by an FRSP, the FRSP is redundant.
508  unsigned TrueReg =
509  TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI);
511  break;
512  MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
513 
514  // This can occur when building a vector of single precision or integer
515  // values.
516  if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) {
517  unsigned DefsReg1 =
518  TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI);
519  unsigned DefsReg2 =
520  TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI);
521  if (!TargetRegisterInfo::isVirtualRegister(DefsReg1) ||
523  break;
524  MachineInstr *P1 = MRI->getVRegDef(DefsReg1);
525  MachineInstr *P2 = MRI->getVRegDef(DefsReg2);
526 
527  if (!P1 || !P2)
528  break;
529 
530  // Remove the passed FRSP instruction if it only feeds this MI and
531  // set any uses of that FRSP (in this MI) to the source of the FRSP.
532  auto removeFRSPIfPossible = [&](MachineInstr *RoundInstr) {
533  if (RoundInstr->getOpcode() == PPC::FRSP &&
534  MRI->hasOneNonDBGUse(RoundInstr->getOperand(0).getReg())) {
535  Simplified = true;
536  unsigned ConvReg1 = RoundInstr->getOperand(1).getReg();
537  unsigned FRSPDefines = RoundInstr->getOperand(0).getReg();
538  MachineInstr &Use = *(MRI->use_instr_begin(FRSPDefines));
539  for (int i = 0, e = Use.getNumOperands(); i < e; ++i)
540  if (Use.getOperand(i).isReg() &&
541  Use.getOperand(i).getReg() == FRSPDefines)
542  Use.getOperand(i).setReg(ConvReg1);
543  LLVM_DEBUG(dbgs() << "Removing redundant FRSP:\n");
544  LLVM_DEBUG(RoundInstr->dump());
545  LLVM_DEBUG(dbgs() << "As it feeds instruction:\n");
546  LLVM_DEBUG(MI.dump());
547  LLVM_DEBUG(dbgs() << "Through instruction:\n");
548  LLVM_DEBUG(DefMI->dump());
549  RoundInstr->eraseFromParent();
550  }
551  };
552 
553  // If the input to XVCVDPSP is a vector that was built (even
554  // partially) out of FRSP's, the FRSP(s) can safely be removed
555  // since this instruction performs the same operation.
556  if (P1 != P2) {
557  removeFRSPIfPossible(P1);
558  removeFRSPIfPossible(P2);
559  break;
560  }
561  removeFRSPIfPossible(P1);
562  }
563  break;
564  }
565  case PPC::EXTSH:
566  case PPC::EXTSH8:
567  case PPC::EXTSH8_32_64: {
568  if (!EnableSExtElimination) break;
569  unsigned NarrowReg = MI.getOperand(1).getReg();
571  break;
572 
573  MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg);
574  // If we've used a zero-extending load that we will sign-extend,
575  // just do a sign-extending load.
576  if (SrcMI->getOpcode() == PPC::LHZ ||
577  SrcMI->getOpcode() == PPC::LHZX) {
578  if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
579  break;
580  auto is64Bit = [] (unsigned Opcode) {
581  return Opcode == PPC::EXTSH8;
582  };
583  auto isXForm = [] (unsigned Opcode) {
584  return Opcode == PPC::LHZX;
585  };
586  auto getSextLoadOp = [] (bool is64Bit, bool isXForm) {
587  if (is64Bit)
588  if (isXForm) return PPC::LHAX8;
589  else return PPC::LHA8;
590  else
591  if (isXForm) return PPC::LHAX;
592  else return PPC::LHA;
593  };
594  unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
595  isXForm(SrcMI->getOpcode()));
596  LLVM_DEBUG(dbgs() << "Zero-extending load\n");
597  LLVM_DEBUG(SrcMI->dump());
598  LLVM_DEBUG(dbgs() << "and sign-extension\n");
599  LLVM_DEBUG(MI.dump());
600  LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n");
601  SrcMI->setDesc(TII->get(Opc));
602  SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
603  ToErase = &MI;
604  Simplified = true;
605  NumEliminatedSExt++;
606  }
607  break;
608  }
609  case PPC::EXTSW:
610  case PPC::EXTSW_32:
611  case PPC::EXTSW_32_64: {
612  if (!EnableSExtElimination) break;
613  unsigned NarrowReg = MI.getOperand(1).getReg();
615  break;
616 
617  MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg);
618  // If we've used a zero-extending load that we will sign-extend,
619  // just do a sign-extending load.
620  if (SrcMI->getOpcode() == PPC::LWZ ||
621  SrcMI->getOpcode() == PPC::LWZX) {
622  if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
623  break;
624  auto is64Bit = [] (unsigned Opcode) {
625  return Opcode == PPC::EXTSW || Opcode == PPC::EXTSW_32_64;
626  };
627  auto isXForm = [] (unsigned Opcode) {
628  return Opcode == PPC::LWZX;
629  };
630  auto getSextLoadOp = [] (bool is64Bit, bool isXForm) {
631  if (is64Bit)
632  if (isXForm) return PPC::LWAX;
633  else return PPC::LWA;
634  else
635  if (isXForm) return PPC::LWAX_32;
636  else return PPC::LWA_32;
637  };
638  unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
639  isXForm(SrcMI->getOpcode()));
640  LLVM_DEBUG(dbgs() << "Zero-extending load\n");
641  LLVM_DEBUG(SrcMI->dump());
642  LLVM_DEBUG(dbgs() << "and sign-extension\n");
643  LLVM_DEBUG(MI.dump());
644  LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n");
645  SrcMI->setDesc(TII->get(Opc));
646  SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
647  ToErase = &MI;
648  Simplified = true;
649  NumEliminatedSExt++;
650  } else if (MI.getOpcode() == PPC::EXTSW_32_64 &&
651  TII->isSignExtended(*SrcMI)) {
652  // We can eliminate EXTSW if the input is known to be already
653  // sign-extended.
654  LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
655  unsigned TmpReg =
656  MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass);
657  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF),
658  TmpReg);
659  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG),
660  MI.getOperand(0).getReg())
661  .addReg(TmpReg)
662  .addReg(NarrowReg)
663  .addImm(PPC::sub_32);
664  ToErase = &MI;
665  Simplified = true;
666  NumEliminatedSExt++;
667  }
668  break;
669  }
670  case PPC::RLDICL: {
671  // We can eliminate RLDICL (e.g. for zero-extension)
672  // if all bits to clear are already zero in the input.
673  // This code assume following code sequence for zero-extension.
674  // %6 = COPY %5:sub_32; (optional)
675  // %8 = IMPLICIT_DEF;
676  // %7<def,tied1> = INSERT_SUBREG %8<tied0>, %6, sub_32;
677  if (!EnableZExtElimination) break;
678 
679  if (MI.getOperand(2).getImm() != 0)
680  break;
681 
682  unsigned SrcReg = MI.getOperand(1).getReg();
684  break;
685 
686  MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
687  if (!(SrcMI && SrcMI->getOpcode() == PPC::INSERT_SUBREG &&
688  SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg()))
689  break;
690 
691  MachineInstr *ImpDefMI, *SubRegMI;
692  ImpDefMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
693  SubRegMI = MRI->getVRegDef(SrcMI->getOperand(2).getReg());
694  if (ImpDefMI->getOpcode() != PPC::IMPLICIT_DEF) break;
695 
696  SrcMI = SubRegMI;
697  if (SubRegMI->getOpcode() == PPC::COPY) {
698  unsigned CopyReg = SubRegMI->getOperand(1).getReg();
700  SrcMI = MRI->getVRegDef(CopyReg);
701  }
702 
703  unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcMI, TII);
704  if (MI.getOperand(3).getImm() <= KnownZeroCount) {
705  LLVM_DEBUG(dbgs() << "Removing redundant zero-extension\n");
706  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
707  MI.getOperand(0).getReg())
708  .addReg(SrcReg);
709  ToErase = &MI;
710  Simplified = true;
711  NumEliminatedZExt++;
712  }
713  break;
714  }
715 
716  // TODO: Any instruction that has an immediate form fed only by a PHI
717  // whose operands are all load immediate can be folded away. We currently
718  // do this for ADD instructions, but should expand it to arithmetic and
719  // binary instructions with immediate forms in the future.
720  case PPC::ADD4:
721  case PPC::ADD8: {
722  auto isSingleUsePHI = [&](MachineOperand *PhiOp) {
723  assert(PhiOp && "Invalid Operand!");
724  MachineInstr *DefPhiMI = getVRegDefOrNull(PhiOp, MRI);
725 
726  return DefPhiMI && (DefPhiMI->getOpcode() == PPC::PHI) &&
727  MRI->hasOneNonDBGUse(DefPhiMI->getOperand(0).getReg());
728  };
729 
730  auto dominatesAllSingleUseLIs = [&](MachineOperand *DominatorOp,
731  MachineOperand *PhiOp) {
732  assert(PhiOp && "Invalid Operand!");
733  assert(DominatorOp && "Invalid Operand!");
734  MachineInstr *DefPhiMI = getVRegDefOrNull(PhiOp, MRI);
735  MachineInstr *DefDomMI = getVRegDefOrNull(DominatorOp, MRI);
736 
737  // Note: the vregs only show up at odd indices position of PHI Node,
738  // the even indices position save the BB info.
739  for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) {
740  MachineInstr *LiMI =
741  getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI);
742  if (!LiMI ||
743  (LiMI->getOpcode() != PPC::LI && LiMI->getOpcode() != PPC::LI8)
744  || !MRI->hasOneNonDBGUse(LiMI->getOperand(0).getReg()) ||
745  !MDT->dominates(DefDomMI, LiMI))
746  return false;
747  }
748 
749  return true;
750  };
751 
752  MachineOperand Op1 = MI.getOperand(1);
753  MachineOperand Op2 = MI.getOperand(2);
754  if (isSingleUsePHI(&Op2) && dominatesAllSingleUseLIs(&Op1, &Op2))
755  std::swap(Op1, Op2);
756  else if (!isSingleUsePHI(&Op1) || !dominatesAllSingleUseLIs(&Op2, &Op1))
757  break; // We don't have an ADD fed by LI's that can be transformed
758 
759  // Now we know that Op1 is the PHI node and Op2 is the dominator
760  unsigned DominatorReg = Op2.getReg();
761 
762  const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8
763  ? &PPC::G8RC_and_G8RC_NOX0RegClass
764  : &PPC::GPRC_and_GPRC_NOR0RegClass;
765  MRI->setRegClass(DominatorReg, TRC);
766 
767  // replace LIs with ADDIs
768  MachineInstr *DefPhiMI = getVRegDefOrNull(&Op1, MRI);
769  for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) {
770  MachineInstr *LiMI = getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI);
771  LLVM_DEBUG(dbgs() << "Optimizing LI to ADDI: ");
772  LLVM_DEBUG(LiMI->dump());
773 
774  // There could be repeated registers in the PHI, e.g: %1 =
775  // PHI %6, <%bb.2>, %8, <%bb.3>, %8, <%bb.6>; So if we've
776  // already replaced the def instruction, skip.
777  if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8)
778  continue;
779 
780  assert((LiMI->getOpcode() == PPC::LI ||
781  LiMI->getOpcode() == PPC::LI8) &&
782  "Invalid Opcode!");
783  auto LiImm = LiMI->getOperand(1).getImm(); // save the imm of LI
784  LiMI->RemoveOperand(1); // remove the imm of LI
785  LiMI->setDesc(TII->get(LiMI->getOpcode() == PPC::LI ? PPC::ADDI
786  : PPC::ADDI8));
787  MachineInstrBuilder(*LiMI->getParent()->getParent(), *LiMI)
788  .addReg(DominatorReg)
789  .addImm(LiImm); // restore the imm of LI
790  LLVM_DEBUG(LiMI->dump());
791  }
792 
793  // Replace ADD with COPY
794  LLVM_DEBUG(dbgs() << "Optimizing ADD to COPY: ");
795  LLVM_DEBUG(MI.dump());
796  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
797  MI.getOperand(0).getReg())
798  .add(Op1);
799  ToErase = &MI;
800  Simplified = true;
801  NumOptADDLIs++;
802  break;
803  }
804  case PPC::RLDICR: {
805  Simplified |= emitRLDICWhenLoweringJumpTables(MI) ||
806  combineSEXTAndSHL(MI, ToErase);
807  break;
808  }
809  }
810  }
811 
812  // If the last instruction was marked for elimination,
813  // remove it now.
814  if (ToErase) {
815  ToErase->eraseFromParent();
816  ToErase = nullptr;
817  }
818  }
819 
820  // Eliminate all the TOC save instructions which are redundant.
821  Simplified |= eliminateRedundantTOCSaves(TOCSaves);
822  PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>();
823  if (FI->mustSaveTOC())
824  NumTOCSavesInPrologue++;
825 
826  // We try to eliminate redundant compare instruction.
827  Simplified |= eliminateRedundantCompare();
828 
829  return Simplified;
830 }
831 
832 // helper functions for eliminateRedundantCompare
833 static bool isEqOrNe(MachineInstr *BI) {
835  unsigned PredCond = PPC::getPredicateCondition(Pred);
836  return (PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE);
837 }
838 
839 static bool isSupportedCmpOp(unsigned opCode) {
840  return (opCode == PPC::CMPLD || opCode == PPC::CMPD ||
841  opCode == PPC::CMPLW || opCode == PPC::CMPW ||
842  opCode == PPC::CMPLDI || opCode == PPC::CMPDI ||
843  opCode == PPC::CMPLWI || opCode == PPC::CMPWI);
844 }
845 
846 static bool is64bitCmpOp(unsigned opCode) {
847  return (opCode == PPC::CMPLD || opCode == PPC::CMPD ||
848  opCode == PPC::CMPLDI || opCode == PPC::CMPDI);
849 }
850 
851 static bool isSignedCmpOp(unsigned opCode) {
852  return (opCode == PPC::CMPD || opCode == PPC::CMPW ||
853  opCode == PPC::CMPDI || opCode == PPC::CMPWI);
854 }
855 
856 static unsigned getSignedCmpOpCode(unsigned opCode) {
857  if (opCode == PPC::CMPLD) return PPC::CMPD;
858  if (opCode == PPC::CMPLW) return PPC::CMPW;
859  if (opCode == PPC::CMPLDI) return PPC::CMPDI;
860  if (opCode == PPC::CMPLWI) return PPC::CMPWI;
861  return opCode;
862 }
863 
864 // We can decrement immediate x in (GE x) by changing it to (GT x-1) or
865 // (LT x) to (LE x-1)
866 static unsigned getPredicateToDecImm(MachineInstr *BI, MachineInstr *CMPI) {
867  uint64_t Imm = CMPI->getOperand(2).getImm();
868  bool SignedCmp = isSignedCmpOp(CMPI->getOpcode());
869  if ((!SignedCmp && Imm == 0) || (SignedCmp && Imm == 0x8000))
870  return 0;
871 
873  unsigned PredCond = PPC::getPredicateCondition(Pred);
874  unsigned PredHint = PPC::getPredicateHint(Pred);
875  if (PredCond == PPC::PRED_GE)
876  return PPC::getPredicate(PPC::PRED_GT, PredHint);
877  if (PredCond == PPC::PRED_LT)
878  return PPC::getPredicate(PPC::PRED_LE, PredHint);
879 
880  return 0;
881 }
882 
883 // We can increment immediate x in (GT x) by changing it to (GE x+1) or
884 // (LE x) to (LT x+1)
885 static unsigned getPredicateToIncImm(MachineInstr *BI, MachineInstr *CMPI) {
886  uint64_t Imm = CMPI->getOperand(2).getImm();
887  bool SignedCmp = isSignedCmpOp(CMPI->getOpcode());
888  if ((!SignedCmp && Imm == 0xFFFF) || (SignedCmp && Imm == 0x7FFF))
889  return 0;
890 
892  unsigned PredCond = PPC::getPredicateCondition(Pred);
893  unsigned PredHint = PPC::getPredicateHint(Pred);
894  if (PredCond == PPC::PRED_GT)
895  return PPC::getPredicate(PPC::PRED_GE, PredHint);
896  if (PredCond == PPC::PRED_LE)
897  return PPC::getPredicate(PPC::PRED_LT, PredHint);
898 
899  return 0;
900 }
901 
902 // This takes a Phi node and returns a register value for the specified BB.
903 static unsigned getIncomingRegForBlock(MachineInstr *Phi,
904  MachineBasicBlock *MBB) {
905  for (unsigned I = 2, E = Phi->getNumOperands() + 1; I != E; I += 2) {
906  MachineOperand &MO = Phi->getOperand(I);
907  if (MO.getMBB() == MBB)
908  return Phi->getOperand(I-1).getReg();
909  }
910  llvm_unreachable("invalid src basic block for this Phi node\n");
911  return 0;
912 }
913 
914 // This function tracks the source of the register through register copy.
915 // If BB1 and BB2 are non-NULL, we also track PHI instruction in BB2
916 // assuming that the control comes from BB1 into BB2.
917 static unsigned getSrcVReg(unsigned Reg, MachineBasicBlock *BB1,
919  unsigned SrcReg = Reg;
920  while (1) {
921  unsigned NextReg = SrcReg;
922  MachineInstr *Inst = MRI->getVRegDef(SrcReg);
923  if (BB1 && Inst->getOpcode() == PPC::PHI && Inst->getParent() == BB2) {
924  NextReg = getIncomingRegForBlock(Inst, BB1);
925  // We track through PHI only once to avoid infinite loop.
926  BB1 = nullptr;
927  }
928  else if (Inst->isFullCopy())
929  NextReg = Inst->getOperand(1).getReg();
930  if (NextReg == SrcReg || !TargetRegisterInfo::isVirtualRegister(NextReg))
931  break;
932  SrcReg = NextReg;
933  }
934  return SrcReg;
935 }
936 
937 static bool eligibleForCompareElimination(MachineBasicBlock &MBB,
938  MachineBasicBlock *&PredMBB,
939  MachineBasicBlock *&MBBtoMoveCmp,
940  MachineRegisterInfo *MRI) {
941 
942  auto isEligibleBB = [&](MachineBasicBlock &BB) {
943  auto BII = BB.getFirstInstrTerminator();
944  // We optimize BBs ending with a conditional branch.
945  // We check only for BCC here, not BCCLR, because BCCLR
946  // will be formed only later in the pipeline.
947  if (BB.succ_size() == 2 &&
948  BII != BB.instr_end() &&
949  (*BII).getOpcode() == PPC::BCC &&
950  (*BII).getOperand(1).isReg()) {
951  // We optimize only if the condition code is used only by one BCC.
952  unsigned CndReg = (*BII).getOperand(1).getReg();
954  !MRI->hasOneNonDBGUse(CndReg))
955  return false;
956 
957  MachineInstr *CMPI = MRI->getVRegDef(CndReg);
958  // We assume compare and branch are in the same BB for ease of analysis.
959  if (CMPI->getParent() != &BB)
960  return false;
961 
962  // We skip this BB if a physical register is used in comparison.
963  for (MachineOperand &MO : CMPI->operands())
965  return false;
966 
967  return true;
968  }
969  return false;
970  };
971 
972  // If this BB has more than one successor, we can create a new BB and
973  // move the compare instruction in the new BB.
974  // So far, we do not move compare instruction to a BB having multiple
975  // successors to avoid potentially increasing code size.
976  auto isEligibleForMoveCmp = [](MachineBasicBlock &BB) {
977  return BB.succ_size() == 1;
978  };
979 
980  if (!isEligibleBB(MBB))
981  return false;
982 
983  unsigned NumPredBBs = MBB.pred_size();
984  if (NumPredBBs == 1) {
985  MachineBasicBlock *TmpMBB = *MBB.pred_begin();
986  if (isEligibleBB(*TmpMBB)) {
987  PredMBB = TmpMBB;
988  MBBtoMoveCmp = nullptr;
989  return true;
990  }
991  }
992  else if (NumPredBBs == 2) {
993  // We check for partially redundant case.
994  // So far, we support cases with only two predecessors
995  // to avoid increasing the number of instructions.
997  MachineBasicBlock *Pred1MBB = *PI;
998  MachineBasicBlock *Pred2MBB = *(PI+1);
999 
1000  if (isEligibleBB(*Pred1MBB) && isEligibleForMoveCmp(*Pred2MBB)) {
1001  // We assume Pred1MBB is the BB containing the compare to be merged and
1002  // Pred2MBB is the BB to which we will append a compare instruction.
1003  // Hence we can proceed as is.
1004  }
1005  else if (isEligibleBB(*Pred2MBB) && isEligibleForMoveCmp(*Pred1MBB)) {
1006  // We need to swap Pred1MBB and Pred2MBB to canonicalize.
1007  std::swap(Pred1MBB, Pred2MBB);
1008  }
1009  else return false;
1010 
1011  // Here, Pred2MBB is the BB to which we need to append a compare inst.
1012  // We cannot move the compare instruction if operands are not available
1013  // in Pred2MBB (i.e. defined in MBB by an instruction other than PHI).
1014  MachineInstr *BI = &*MBB.getFirstInstrTerminator();
1015  MachineInstr *CMPI = MRI->getVRegDef(BI->getOperand(1).getReg());
1016  for (int I = 1; I <= 2; I++)
1017  if (CMPI->getOperand(I).isReg()) {
1018  MachineInstr *Inst = MRI->getVRegDef(CMPI->getOperand(I).getReg());
1019  if (Inst->getParent() == &MBB && Inst->getOpcode() != PPC::PHI)
1020  return false;
1021  }
1022 
1023  PredMBB = Pred1MBB;
1024  MBBtoMoveCmp = Pred2MBB;
1025  return true;
1026  }
1027 
1028  return false;
1029 }
1030 
1031 // This function will iterate over the input map containing a pair of TOC save
1032 // instruction and a flag. The flag will be set to false if the TOC save is
1033 // proven redundant. This function will erase from the basic block all the TOC
1034 // saves marked as redundant.
1035 bool PPCMIPeephole::eliminateRedundantTOCSaves(
1036  std::map<MachineInstr *, bool> &TOCSaves) {
1037  bool Simplified = false;
1038  int NumKept = 0;
1039  for (auto TOCSave : TOCSaves) {
1040  if (!TOCSave.second) {
1041  TOCSave.first->eraseFromParent();
1042  RemoveTOCSave++;
1043  Simplified = true;
1044  } else {
1045  NumKept++;
1046  }
1047  }
1048 
1049  if (NumKept > 1)
1050  MultiTOCSaves++;
1051 
1052  return Simplified;
1053 }
1054 
1055 // If multiple conditional branches are executed based on the (essentially)
1056 // same comparison, we merge compare instructions into one and make multiple
1057 // conditional branches on this comparison.
1058 // For example,
1059 // if (a == 0) { ... }
1060 // else if (a < 0) { ... }
1061 // can be executed by one compare and two conditional branches instead of
1062 // two pairs of a compare and a conditional branch.
1063 //
1064 // This method merges two compare instructions in two MBBs and modifies the
1065 // compare and conditional branch instructions if needed.
1066 // For the above example, the input for this pass looks like:
1067 // cmplwi r3, 0
1068 // beq 0, .LBB0_3
1069 // cmpwi r3, -1
1070 // bgt 0, .LBB0_4
1071 // So, before merging two compares, we need to modify these instructions as
1072 // cmpwi r3, 0 ; cmplwi and cmpwi yield same result for beq
1073 // beq 0, .LBB0_3
1074 // cmpwi r3, 0 ; greather than -1 means greater or equal to 0
1075 // bge 0, .LBB0_4
1076 
1077 bool PPCMIPeephole::eliminateRedundantCompare(void) {
1078  bool Simplified = false;
1079 
1080  for (MachineBasicBlock &MBB2 : *MF) {
1081  MachineBasicBlock *MBB1 = nullptr, *MBBtoMoveCmp = nullptr;
1082 
1083  // For fully redundant case, we select two basic blocks MBB1 and MBB2
1084  // as an optimization target if
1085  // - both MBBs end with a conditional branch,
1086  // - MBB1 is the only predecessor of MBB2, and
1087  // - compare does not take a physical register as a operand in both MBBs.
1088  // In this case, eligibleForCompareElimination sets MBBtoMoveCmp nullptr.
1089  //
1090  // As partially redundant case, we additionally handle if MBB2 has one
1091  // additional predecessor, which has only one successor (MBB2).
1092  // In this case, we move the compare instruction originally in MBB2 into
1093  // MBBtoMoveCmp. This partially redundant case is typically appear by
1094  // compiling a while loop; here, MBBtoMoveCmp is the loop preheader.
1095  //
1096  // Overview of CFG of related basic blocks
1097  // Fully redundant case Partially redundant case
1098  // -------- ---------------- --------
1099  // | MBB1 | (w/ 2 succ) | MBBtoMoveCmp | | MBB1 | (w/ 2 succ)
1100  // -------- ---------------- --------
1101  // | \ (w/ 1 succ) \ | \
1102  // | \ \ | \
1103  // | \ |
1104  // -------- --------
1105  // | MBB2 | (w/ 1 pred | MBB2 | (w/ 2 pred
1106  // -------- and 2 succ) -------- and 2 succ)
1107  // | \ | \
1108  // | \ | \
1109  //
1110  if (!eligibleForCompareElimination(MBB2, MBB1, MBBtoMoveCmp, MRI))
1111  continue;
1112 
1113  MachineInstr *BI1 = &*MBB1->getFirstInstrTerminator();
1114  MachineInstr *CMPI1 = MRI->getVRegDef(BI1->getOperand(1).getReg());
1115 
1116  MachineInstr *BI2 = &*MBB2.getFirstInstrTerminator();
1117  MachineInstr *CMPI2 = MRI->getVRegDef(BI2->getOperand(1).getReg());
1118  bool IsPartiallyRedundant = (MBBtoMoveCmp != nullptr);
1119 
1120  // We cannot optimize an unsupported compare opcode or
1121  // a mix of 32-bit and 64-bit comaprisons
1122  if (!isSupportedCmpOp(CMPI1->getOpcode()) ||
1123  !isSupportedCmpOp(CMPI2->getOpcode()) ||
1124  is64bitCmpOp(CMPI1->getOpcode()) != is64bitCmpOp(CMPI2->getOpcode()))
1125  continue;
1126 
1127  unsigned NewOpCode = 0;
1128  unsigned NewPredicate1 = 0, NewPredicate2 = 0;
1129  int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0;
1130  bool SwapOperands = false;
1131 
1132  if (CMPI1->getOpcode() != CMPI2->getOpcode()) {
1133  // Typically, unsigned comparison is used for equality check, but
1134  // we replace it with a signed comparison if the comparison
1135  // to be merged is a signed comparison.
1136  // In other cases of opcode mismatch, we cannot optimize this.
1137 
1138  // We cannot change opcode when comparing against an immediate
1139  // if the most significant bit of the immediate is one
1140  // due to the difference in sign extension.
1141  auto CmpAgainstImmWithSignBit = [](MachineInstr *I) {
1142  if (!I->getOperand(2).isImm())
1143  return false;
1144  int16_t Imm = (int16_t)I->getOperand(2).getImm();
1145  return Imm < 0;
1146  };
1147 
1148  if (isEqOrNe(BI2) && !CmpAgainstImmWithSignBit(CMPI2) &&
1149  CMPI1->getOpcode() == getSignedCmpOpCode(CMPI2->getOpcode()))
1150  NewOpCode = CMPI1->getOpcode();
1151  else if (isEqOrNe(BI1) && !CmpAgainstImmWithSignBit(CMPI1) &&
1152  getSignedCmpOpCode(CMPI1->getOpcode()) == CMPI2->getOpcode())
1153  NewOpCode = CMPI2->getOpcode();
1154  else continue;
1155  }
1156 
1157  if (CMPI1->getOperand(2).isReg() && CMPI2->getOperand(2).isReg()) {
1158  // In case of comparisons between two registers, these two registers
1159  // must be same to merge two comparisons.
1160  unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(),
1161  nullptr, nullptr, MRI);
1162  unsigned Cmp1Operand2 = getSrcVReg(CMPI1->getOperand(2).getReg(),
1163  nullptr, nullptr, MRI);
1164  unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(),
1165  MBB1, &MBB2, MRI);
1166  unsigned Cmp2Operand2 = getSrcVReg(CMPI2->getOperand(2).getReg(),
1167  MBB1, &MBB2, MRI);
1168 
1169  if (Cmp1Operand1 == Cmp2Operand1 && Cmp1Operand2 == Cmp2Operand2) {
1170  // Same pair of registers in the same order; ready to merge as is.
1171  }
1172  else if (Cmp1Operand1 == Cmp2Operand2 && Cmp1Operand2 == Cmp2Operand1) {
1173  // Same pair of registers in different order.
1174  // We reverse the predicate to merge compare instructions.
1175  PPC::Predicate Pred = (PPC::Predicate)BI2->getOperand(0).getImm();
1176  NewPredicate2 = (unsigned)PPC::getSwappedPredicate(Pred);
1177  // In case of partial redundancy, we need to swap operands
1178  // in another compare instruction.
1179  SwapOperands = true;
1180  }
1181  else continue;
1182  }
1183  else if (CMPI1->getOperand(2).isImm() && CMPI2->getOperand(2).isImm()) {
1184  // In case of comparisons between a register and an immediate,
1185  // the operand register must be same for two compare instructions.
1186  unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(),
1187  nullptr, nullptr, MRI);
1188  unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(),
1189  MBB1, &MBB2, MRI);
1190  if (Cmp1Operand1 != Cmp2Operand1)
1191  continue;
1192 
1193  NewImm1 = Imm1 = (int16_t)CMPI1->getOperand(2).getImm();
1194  NewImm2 = Imm2 = (int16_t)CMPI2->getOperand(2).getImm();
1195 
1196  // If immediate are not same, we try to adjust by changing predicate;
1197  // e.g. GT imm means GE (imm+1).
1198  if (Imm1 != Imm2 && (!isEqOrNe(BI2) || !isEqOrNe(BI1))) {
1199  int Diff = Imm1 - Imm2;
1200  if (Diff < -2 || Diff > 2)
1201  continue;
1202 
1203  unsigned PredToInc1 = getPredicateToIncImm(BI1, CMPI1);
1204  unsigned PredToDec1 = getPredicateToDecImm(BI1, CMPI1);
1205  unsigned PredToInc2 = getPredicateToIncImm(BI2, CMPI2);
1206  unsigned PredToDec2 = getPredicateToDecImm(BI2, CMPI2);
1207  if (Diff == 2) {
1208  if (PredToInc2 && PredToDec1) {
1209  NewPredicate2 = PredToInc2;
1210  NewPredicate1 = PredToDec1;
1211  NewImm2++;
1212  NewImm1--;
1213  }
1214  }
1215  else if (Diff == 1) {
1216  if (PredToInc2) {
1217  NewImm2++;
1218  NewPredicate2 = PredToInc2;
1219  }
1220  else if (PredToDec1) {
1221  NewImm1--;
1222  NewPredicate1 = PredToDec1;
1223  }
1224  }
1225  else if (Diff == -1) {
1226  if (PredToDec2) {
1227  NewImm2--;
1228  NewPredicate2 = PredToDec2;
1229  }
1230  else if (PredToInc1) {
1231  NewImm1++;
1232  NewPredicate1 = PredToInc1;
1233  }
1234  }
1235  else if (Diff == -2) {
1236  if (PredToDec2 && PredToInc1) {
1237  NewPredicate2 = PredToDec2;
1238  NewPredicate1 = PredToInc1;
1239  NewImm2--;
1240  NewImm1++;
1241  }
1242  }
1243  }
1244 
1245  // We cannot merge two compares if the immediates are not same.
1246  if (NewImm2 != NewImm1)
1247  continue;
1248  }
1249 
1250  LLVM_DEBUG(dbgs() << "Optimize two pairs of compare and branch:\n");
1251  LLVM_DEBUG(CMPI1->dump());
1252  LLVM_DEBUG(BI1->dump());
1253  LLVM_DEBUG(CMPI2->dump());
1254  LLVM_DEBUG(BI2->dump());
1255 
1256  // We adjust opcode, predicates and immediate as we determined above.
1257  if (NewOpCode != 0 && NewOpCode != CMPI1->getOpcode()) {
1258  CMPI1->setDesc(TII->get(NewOpCode));
1259  }
1260  if (NewPredicate1) {
1261  BI1->getOperand(0).setImm(NewPredicate1);
1262  }
1263  if (NewPredicate2) {
1264  BI2->getOperand(0).setImm(NewPredicate2);
1265  }
1266  if (NewImm1 != Imm1) {
1267  CMPI1->getOperand(2).setImm(NewImm1);
1268  }
1269 
1270  if (IsPartiallyRedundant) {
1271  // We touch up the compare instruction in MBB2 and move it to
1272  // a previous BB to handle partially redundant case.
1273  if (SwapOperands) {
1274  unsigned Op1 = CMPI2->getOperand(1).getReg();
1275  unsigned Op2 = CMPI2->getOperand(2).getReg();
1276  CMPI2->getOperand(1).setReg(Op2);
1277  CMPI2->getOperand(2).setReg(Op1);
1278  }
1279  if (NewImm2 != Imm2)
1280  CMPI2->getOperand(2).setImm(NewImm2);
1281 
1282  for (int I = 1; I <= 2; I++) {
1283  if (CMPI2->getOperand(I).isReg()) {
1284  MachineInstr *Inst = MRI->getVRegDef(CMPI2->getOperand(I).getReg());
1285  if (Inst->getParent() != &MBB2)
1286  continue;
1287 
1288  assert(Inst->getOpcode() == PPC::PHI &&
1289  "We cannot support if an operand comes from this BB.");
1290  unsigned SrcReg = getIncomingRegForBlock(Inst, MBBtoMoveCmp);
1291  CMPI2->getOperand(I).setReg(SrcReg);
1292  }
1293  }
1294  auto I = MachineBasicBlock::iterator(MBBtoMoveCmp->getFirstTerminator());
1295  MBBtoMoveCmp->splice(I, &MBB2, MachineBasicBlock::iterator(CMPI2));
1296 
1297  DebugLoc DL = CMPI2->getDebugLoc();
1298  unsigned NewVReg = MRI->createVirtualRegister(&PPC::CRRCRegClass);
1299  BuildMI(MBB2, MBB2.begin(), DL,
1300  TII->get(PPC::PHI), NewVReg)
1301  .addReg(BI1->getOperand(1).getReg()).addMBB(MBB1)
1302  .addReg(BI2->getOperand(1).getReg()).addMBB(MBBtoMoveCmp);
1303  BI2->getOperand(1).setReg(NewVReg);
1304  }
1305  else {
1306  // We finally eliminate compare instruction in MBB2.
1307  BI2->getOperand(1).setReg(BI1->getOperand(1).getReg());
1308  CMPI2->eraseFromParent();
1309  }
1310  BI2->getOperand(1).setIsKill(true);
1311  BI1->getOperand(1).setIsKill(false);
1312 
1313  LLVM_DEBUG(dbgs() << "into a compare and two branches:\n");
1314  LLVM_DEBUG(CMPI1->dump());
1315  LLVM_DEBUG(BI1->dump());
1316  LLVM_DEBUG(BI2->dump());
1317  if (IsPartiallyRedundant) {
1318  LLVM_DEBUG(dbgs() << "The following compare is moved into "
1319  << printMBBReference(*MBBtoMoveCmp)
1320  << " to handle partial redundancy.\n");
1321  LLVM_DEBUG(CMPI2->dump());
1322  }
1323 
1324  Simplified = true;
1325  }
1326 
1327  return Simplified;
1328 }
1329 
1330 // We miss the opportunity to emit an RLDIC when lowering jump tables
1331 // since ISEL sees only a single basic block. When selecting, the clear
1332 // and shift left will be in different blocks.
1333 bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI) {
1334  if (MI.getOpcode() != PPC::RLDICR)
1335  return false;
1336 
1337  unsigned SrcReg = MI.getOperand(1).getReg();
1339  return false;
1340 
1341  MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
1342  if (SrcMI->getOpcode() != PPC::RLDICL)
1343  return false;
1344 
1345  MachineOperand MOpSHSrc = SrcMI->getOperand(2);
1346  MachineOperand MOpMBSrc = SrcMI->getOperand(3);
1347  MachineOperand MOpSHMI = MI.getOperand(2);
1348  MachineOperand MOpMEMI = MI.getOperand(3);
1349  if (!(MOpSHSrc.isImm() && MOpMBSrc.isImm() && MOpSHMI.isImm() &&
1350  MOpMEMI.isImm()))
1351  return false;
1352 
1353  uint64_t SHSrc = MOpSHSrc.getImm();
1354  uint64_t MBSrc = MOpMBSrc.getImm();
1355  uint64_t SHMI = MOpSHMI.getImm();
1356  uint64_t MEMI = MOpMEMI.getImm();
1357  uint64_t NewSH = SHSrc + SHMI;
1358  uint64_t NewMB = MBSrc - SHMI;
1359  if (NewMB > 63 || NewSH > 63)
1360  return false;
1361 
1362  // The bits cleared with RLDICL are [0, MBSrc).
1363  // The bits cleared with RLDICR are (MEMI, 63].
1364  // After the sequence, the bits cleared are:
1365  // [0, MBSrc-SHMI) and (MEMI, 63).
1366  //
1367  // The bits cleared with RLDIC are [0, NewMB) and (63-NewSH, 63].
1368  if ((63 - NewSH) != MEMI)
1369  return false;
1370 
1371  LLVM_DEBUG(dbgs() << "Converting pair: ");
1372  LLVM_DEBUG(SrcMI->dump());
1373  LLVM_DEBUG(MI.dump());
1374 
1375  MI.setDesc(TII->get(PPC::RLDIC));
1376  MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
1377  MI.getOperand(2).setImm(NewSH);
1378  MI.getOperand(3).setImm(NewMB);
1379 
1380  LLVM_DEBUG(dbgs() << "To: ");
1381  LLVM_DEBUG(MI.dump());
1382  NumRotatesCollapsed++;
1383  return true;
1384 }
1385 
1386 // For case in LLVM IR
1387 // entry:
1388 // %iconv = sext i32 %index to i64
1389 // br i1 undef label %true, label %false
1390 // true:
1391 // %ptr = getelementptr inbounds i32, i32* null, i64 %iconv
1392 // ...
1393 // PPCISelLowering::combineSHL fails to combine, because sext and shl are in
1394 // different BBs when conducting instruction selection. We can do a peephole
1395 // optimization to combine these two instructions into extswsli after
1396 // instruction selection.
1397 bool PPCMIPeephole::combineSEXTAndSHL(MachineInstr &MI,
1398  MachineInstr *&ToErase) {
1399  if (MI.getOpcode() != PPC::RLDICR)
1400  return false;
1401 
1402  if (!MF->getSubtarget<PPCSubtarget>().isISA3_0())
1403  return false;
1404 
1405  assert(MI.getNumOperands() == 4 && "RLDICR should have 4 operands");
1406 
1407  MachineOperand MOpSHMI = MI.getOperand(2);
1408  MachineOperand MOpMEMI = MI.getOperand(3);
1409  if (!(MOpSHMI.isImm() && MOpMEMI.isImm()))
1410  return false;
1411 
1412  uint64_t SHMI = MOpSHMI.getImm();
1413  uint64_t MEMI = MOpMEMI.getImm();
1414  if (SHMI + MEMI != 63)
1415  return false;
1416 
1417  unsigned SrcReg = MI.getOperand(1).getReg();
1419  return false;
1420 
1421  MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
1422  if (SrcMI->getOpcode() != PPC::EXTSW &&
1423  SrcMI->getOpcode() != PPC::EXTSW_32_64)
1424  return false;
1425 
1426  // If the register defined by extsw has more than one use, combination is not
1427  // needed.
1428  if (!MRI->hasOneNonDBGUse(SrcReg))
1429  return false;
1430 
1431  LLVM_DEBUG(dbgs() << "Combining pair: ");
1432  LLVM_DEBUG(SrcMI->dump());
1433  LLVM_DEBUG(MI.dump());
1434 
1435  MachineInstr *NewInstr =
1436  BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
1437  SrcMI->getOpcode() == PPC::EXTSW ? TII->get(PPC::EXTSWSLI)
1438  : TII->get(PPC::EXTSWSLI_32_64),
1439  MI.getOperand(0).getReg())
1440  .add(SrcMI->getOperand(1))
1441  .add(MOpSHMI);
1442  (void)NewInstr;
1443 
1444  LLVM_DEBUG(dbgs() << "TO: ");
1445  LLVM_DEBUG(NewInstr->dump());
1446  ++NumEXTSWAndSLDICombined;
1447  ToErase = &MI;
1448  // SrcMI, which is extsw, is of no use now, erase it.
1449  SrcMI->eraseFromParent();
1450  return true;
1451 }
1452 
1453 } // end default namespace
1454 
1455 INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE,
1456  "PowerPC MI Peephole Optimization", false, false)
1461  "PowerPC MI Peephole Optimization", false, false)
1462 
1463 char PPCMIPeephole::ID = 0;
1464 FunctionPass*
1465 llvm::createPPCMIPeepholePass() { return new PPCMIPeephole(); }
1466 
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
MachineBasicBlock * getMBB() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
instr_iterator getFirstInstrTerminator()
Same getFirstTerminator but it ignores bundles and return an instr_iterator instead.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
void initializePPCMIPeepholePass(PassRegistry &)
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:461
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void dump() const
dump - Print the current MachineFunction to cerr, useful for debugger use.
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
Definition: PPCInstrInfo.h:414
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
bool isISA3_0() const
Definition: PPCSubtarget.h:295
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE, "PowerPC MI Peephole Optimization", false, false) INITIALIZE_PASS_END(PPCMIPeephole
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
bool isTOCSaveMI(const MachineInstr &MI) const
bool isFullCopy() const
#define DEBUG_TYPE
static cl::opt< bool > EnableSExtElimination("ppc-eliminate-signext", cl::desc("enable elimination of sign-extensions"), cl::init(false), cl::Hidden)
bool isELFv2ABI() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static cl::opt< bool > ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(true), cl::desc("Convert eligible reg+reg instructions to reg+imm"))
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
MachineInstrBundleIterator< MachineInstr > iterator
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static bool is64Bit(const char *name)
Represent the analysis usage information of a pass.
use_instr_iterator use_instr_begin(unsigned RegNo) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
std::vector< MachineBasicBlock * >::iterator pred_iterator
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
unsigned countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the most significant bit to the least stopping at the first 1...
Definition: MathExtras.h:188
unsigned getPredicateHint(Predicate Opcode)
Return the hint bits of the predicate.
Definition: PPCPredicates.h:82
bool isDebugInstr() const
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setIsKill(bool Val=true)
EXTSWSLI = The PPC extswsli instruction, which does an extend-sign word and shift left immediate...
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:87
static cl::opt< bool > FixedPointRegToImm("ppc-reg-to-imm-fixed-point", cl::Hidden, cl::init(true), cl::desc("Iterate to a fixed point when attempting to " "convert reg-reg instructions to reg-imm"))
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
PostDominatorTree Class - Concrete subclass of DominatorTree that is used to compute the post-dominat...
static uint64_t add(uint64_t LeftOp, uint64_t RightOp)
Definition: FileCheck.cpp:207
MachineOperand class - Representation of each machine instruction operand.
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
MachineInstrBuilder MachineInstrBuilder & DefMI
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
int64_t getImm() const
unsigned pred_size() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, ArrayRef< StringRef > StandardNames)
Initialize the set of available library functions based on the specified target triple.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
PowerPC MI Peephole Optimization
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
static cl::opt< bool > EnableZExtElimination("ppc-eliminate-zeroext", cl::desc("enable elimination of zero-extensions"), cl::init(false), cl::Hidden)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
FunctionPass * createPPCMIPeepholePass()
unsigned getPredicateCondition(Predicate Opcode)
Return the condition without hint bits.
Definition: PPCPredicates.h:77
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:185
virtual unsigned lookThruCopyLike(unsigned SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
XXPERMDI - The PPC XXPERMDI instruction.
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
Definition: PPCInstrInfo.h:420
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...