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X86ISelLowering.h
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1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that X86 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
15 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 
21 
22 namespace llvm {
23  class X86Subtarget;
24  class X86TargetMachine;
25 
26  namespace X86ISD {
27  // X86 Specific DAG Nodes
28  enum NodeType : unsigned {
29  // Start the numbering where the builtin ops leave off.
31 
32  /// Bit scan forward.
33  BSF,
34  /// Bit scan reverse.
35  BSR,
36 
37  /// Double shift instructions. These correspond to
38  /// X86::SHLDxx and X86::SHRDxx instructions.
41 
42  /// Bitwise logical AND of floating point values. This corresponds
43  /// to X86::ANDPS or X86::ANDPD.
45 
46  /// Bitwise logical OR of floating point values. This corresponds
47  /// to X86::ORPS or X86::ORPD.
48  FOR,
49 
50  /// Bitwise logical XOR of floating point values. This corresponds
51  /// to X86::XORPS or X86::XORPD.
53 
54  /// Bitwise logical ANDNOT of floating point values. This
55  /// corresponds to X86::ANDNPS or X86::ANDNPD.
57 
58  /// These operations represent an abstract X86 call
59  /// instruction, which includes a bunch of information. In particular the
60  /// operands of these node are:
61  ///
62  /// #0 - The incoming token chain
63  /// #1 - The callee
64  /// #2 - The number of arg bytes the caller pushes on the stack.
65  /// #3 - The number of arg bytes the callee pops off the stack.
66  /// #4 - The value to pass in AL/AX/EAX (optional)
67  /// #5 - The value to pass in DL/DX/EDX (optional)
68  ///
69  /// The result values of these nodes are:
70  ///
71  /// #0 - The outgoing token chain
72  /// #1 - The first register result value (optional)
73  /// #2 - The second register result value (optional)
74  ///
76 
77  /// Same as call except it adds the NoTrack prefix.
79 
80  /// X86 compare and logical compare instructions.
82 
83  /// X86 bit-test instructions.
84  BT,
85 
86  /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
87  /// operand, usually produced by a CMP instruction.
89 
90  /// X86 Select
92 
93  // Same as SETCC except it's materialized with a sbb and the value is all
94  // one's or all zero's.
95  SETCC_CARRY, // R = carry_bit ? ~0 : 0
96 
97  /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
98  /// Operands are two FP values to compare; result is a mask of
99  /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
101 
102  /// X86 FP SETCC, similar to above, but with output as an i1 mask and
103  /// and a version with SAE.
105 
106  /// X86 conditional moves. Operand 0 and operand 1 are the two values
107  /// to select from. Operand 2 is the condition code, and operand 3 is the
108  /// flag operand produced by a CMP or TEST instruction. It also writes a
109  /// flag result.
111 
112  /// X86 conditional branches. Operand 0 is the chain operand, operand 1
113  /// is the block to branch if condition is true, operand 2 is the
114  /// condition code, and operand 3 is the flag operand produced by a CMP
115  /// or TEST instruction.
117 
118  /// BRIND node with NoTrack prefix. Operand 0 is the chain operand and
119  /// operand 1 is the target address.
121 
122  /// Return with a flag operand. Operand 0 is the chain operand, operand
123  /// 1 is the number of bytes of stack to pop.
125 
126  /// Return from interrupt. Operand 0 is the number of bytes to pop.
128 
129  /// Repeat fill, corresponds to X86::REP_STOSx.
131 
132  /// Repeat move, corresponds to X86::REP_MOVSx.
134 
135  /// On Darwin, this node represents the result of the popl
136  /// at function entry, used for PIC code.
138 
139  /// A wrapper node for TargetConstantPool, TargetJumpTable,
140  /// TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress,
141  /// MCSymbol and TargetBlockAddress.
143 
144  /// Special wrapper used under X86-64 PIC mode for RIP
145  /// relative displacements.
147 
148  /// Copies a 64-bit value from the low word of an XMM vector
149  /// to an MMX vector.
151 
152  /// Copies a 32-bit value from the low word of a MMX
153  /// vector to a GPR.
155 
156  /// Copies a GPR into the low 32-bit word of a MMX vector
157  /// and zero out the high word.
159 
160  /// Extract an 8-bit value from a vector and zero extend it to
161  /// i32, corresponds to X86::PEXTRB.
163 
164  /// Extract a 16-bit value from a vector and zero extend it to
165  /// i32, corresponds to X86::PEXTRW.
167 
168  /// Insert any element of a 4 x float vector into any element
169  /// of a destination 4 x floatvector.
171 
172  /// Insert the lower 8-bits of a 32-bit value to a vector,
173  /// corresponds to X86::PINSRB.
175 
176  /// Insert the lower 16-bits of a 32-bit value to a vector,
177  /// corresponds to X86::PINSRW.
179 
180  /// Shuffle 16 8-bit values within a vector.
182 
183  /// Compute Sum of Absolute Differences.
185  /// Compute Double Block Packed Sum-Absolute-Differences
187 
188  /// Bitwise Logical AND NOT of Packed FP values.
190 
191  /// Blend where the selector is an immediate.
193 
194  /// Dynamic (non-constant condition) vector blend where only the sign bits
195  /// of the condition elements are used. This is used to enforce that the
196  /// condition mask is not valid for generic VSELECT optimizations. This
197  /// is also used to implement the intrinsics.
198  /// Operands are in VSELECT order: MASK, TRUE, FALSE
200 
201  /// Combined add and sub on an FP vector.
203 
204  // FP vector ops with rounding mode.
212 
213  // FP vector get exponent.
215  // Extract Normalized Mantissas.
217  // FP Scale.
220 
221  // Unsigned Integer average.
223 
224  /// Integer horizontal add/sub.
227 
228  /// Floating point horizontal add/sub.
231 
232  // Detect Conflicts Within a Vector
234 
235  /// Floating point max and min.
237 
238  /// Commutative FMIN and FMAX.
240 
241  /// Scalar intrinsic floating point max and min.
243 
244  /// Floating point reciprocal-sqrt and reciprocal approximation.
245  /// Note that these typically require refinement
246  /// in order to obtain suitable precision.
248 
249  // AVX-512 reciprocal approximations with a little more precision.
251 
252  // Thread Local Storage.
254 
255  // Thread Local Storage. A call to get the start address
256  // of the TLS block for the current module.
258 
259  // Thread Local Storage. When calling to an OS provided
260  // thunk at the address from an earlier relocation.
262 
263  // Exception Handling helpers.
265 
266  // SjLj exception handling setjmp.
268 
269  // SjLj exception handling longjmp.
271 
272  // SjLj exception handling dispatch.
274 
275  /// Tail call return. See X86TargetLowering::LowerCall for
276  /// the list of operands.
278 
279  // Vector move to low scalar and zero higher vector elements.
281 
282  // Vector integer truncate.
284  // Vector integer truncate with unsigned/signed saturation.
286 
287  // Masked version of the above. Used when less than a 128-bit result is
288  // produced since the mask only applies to the lower elements and can't
289  // be represented by a select.
290  // SRC, PASSTHRU, MASK
292 
293  // Vector FP extend.
295 
296  // Vector FP round.
298 
299  // Masked version of above. Used for v2f64->v4f32.
300  // SRC, PASSTHRU, MASK
302 
303  // 128-bit vector logical left / right shift
305 
306  // Vector shift elements
308 
309  // Vector variable shift
311 
312  // Vector shift elements by immediate
314 
315  // Shifts of mask registers.
317 
318  // Bit rotate by immediate
320 
321  // Vector packed double/float comparison.
323 
324  // Vector integer comparisons.
326 
327  // v8i16 Horizontal minimum and position.
329 
331 
332  /// Vector comparison generating mask bits for fp and
333  /// integer signed and unsigned data types.
335  // Vector comparison with SAE for FP values
337 
338  // Arithmetic operations with FLAGS results.
340  OR, XOR, AND,
341 
342  // Bit field extract.
344 
345  // Zero High Bits Starting with Specified Bit Position.
347 
348  // X86-specific multiply by immediate.
350 
351  // Vector sign bit extraction.
353 
354  // Vector bitwise comparisons.
356 
357  // Vector packed fp sign bitwise comparisons.
359 
360  // OR/AND test for masks.
363 
364  // ADD for masks.
366 
367  // Several flavors of instructions with vector shuffle behaviors.
368  // Saturated signed/unnsigned packing.
371  // Intra-lane alignr.
373  // AVX512 inter-lane alignr.
379  // VBMI2 Concat & Shift.
384  //Shuffle Packed Values at 128-bit granularity.
399 
400  // Variable Permute (VPERM).
401  // Res = VPERMV MaskV, V0
403 
404  // 3-op Variable Permute (VPERMT2).
405  // Res = VPERMV3 V0, MaskV, V1
407 
408  // Bitwise ternary logic.
410  // Fix Up Special Packed Float32/64 values.
413  // Range Restriction Calculation For Packed Pairs of Float32/64 values.
415  // Reduce - Perform Reduction Transformation on scalar\packed FP.
417  // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
418  // Also used by the legacy (V)ROUND intrinsics where we mask out the
419  // scaling part of the immediate.
421  // Tests Types Of a FP Values for packed types.
423  // Tests Types Of a FP Values for scalar types.
425 
426  // Broadcast scalar to vector.
428  // Broadcast mask to vector.
430  // Broadcast subvector to vector.
432 
433  /// SSE4A Extraction and Insertion.
435 
436  // XOP arithmetic/logical shifts.
438  // XOP signed/unsigned integer comparisons.
440  // XOP packed permute bytes.
442  // XOP two source permutation.
444 
445  // Vector multiply packed unsigned doubleword integers.
447  // Vector multiply packed signed doubleword integers.
449  // Vector Multiply Packed UnsignedIntegers with Round and Scale.
451 
452  // Multiply and Add Packed Integers.
454 
455  // AVX512IFMA multiply and add.
456  // NOTE: These are different than the instruction and perform
457  // op0 x op1 + op2.
459 
460  // VNNI
465 
466  // FMA nodes.
467  // We use the target independent ISD::FMA for the non-inverted case.
473 
474  // FMA with rounding mode.
481 
482  // Compress and expand.
485 
486  // Bits shuffle
488 
489  // Convert Unsigned/Integer to Floating-Point Value with rounding mode.
493 
494  // Vector float/double to signed/unsigned integer.
496  // Scalar float/double to signed/unsigned integer.
498 
499  // Vector float/double to signed/unsigned integer with truncation.
501  // Scalar float/double to signed/unsigned integer with truncation.
503 
504  // Vector signed/unsigned integer to float/double.
506 
507  // Masked versions of above. Used for v2f64->v4f32.
508  // SRC, PASSTHRU, MASK
511 
512  // Vector float to bfloat16.
513  // Convert TWO packed single data to one packed BF16 data
515  // Convert packed single data to packed BF16 data
517  // Masked version of above.
518  // SRC, PASSTHRU, MASK
520 
521  // Dot product of BF16 pairs to accumulated into
522  // packed single precision.
524 
525  // Save xmm argument registers to the stack, according to %al. An operator
526  // is needed so that this can be expanded with control flow.
528 
529  // Windows's _chkstk call to do stack probing.
531 
532  // For allocating variable amounts of stack space when using
533  // segmented stacks. Check if the current stacklet has enough space, and
534  // falls back to heap allocation if not.
536 
537  // Memory barriers.
540 
541  // Store FP status word into i16 register.
543 
544  // Store contents of %ah into %eflags.
546 
547  // Get a random integer and indicate whether it is valid in CF.
549 
550  // Get a NIST SP800-90B & C compliant random integer and
551  // indicate whether it is valid in CF.
553 
554  // Protection keys
555  // RDPKRU - Operand 0 is chain. Operand 1 is value for ECX.
556  // WRPKRU - Operand 0 is chain. Operand 1 is value for EDX. Operand 2 is
557  // value for ECX.
559 
560  // SSE42 string comparisons.
561  // These nodes produce 3 results, index, mask, and flags. X86ISelDAGToDAG
562  // will emit one or two instructions based on which results are used. If
563  // flags and index/mask this allows us to use a single instruction since
564  // we won't have to pick and opcode for flags. Instead we can rely on the
565  // DAG to CSE everything and decide at isel.
568 
569  // Test if in transactional execution.
571 
572  // ERI instructions.
575 
576  // Conversions between float and half-float.
578 
579  // Masked version of above.
580  // SRC, RND, PASSTHRU, MASK
582 
583  // Galois Field Arithmetic Instructions
585 
586  // LWP insert record.
588 
589  // User level wait
591 
592  // Enqueue Stores Instructions
594 
595  // For avx512-vp2intersect
597 
598  // Compare and swap.
604 
605  /// LOCK-prefixed arithmetic read-modify-write instructions.
606  /// EFLAGS, OUTCHAIN = LADD(INCHAIN, PTR, RHS)
608 
609  // Load, scalar_to_vector, and zero extend.
611 
612  // extract_vector_elt, store.
614 
615  // Store FP control world into i16 memory.
617 
618  /// This instruction implements FP_TO_SINT with the
619  /// integer destination in memory and a FP reg source. This corresponds
620  /// to the X86::FIST*m instructions and the rounding mode change stuff. It
621  /// has two inputs (token chain and address) and two outputs (int value
622  /// and token chain). Memory VT specifies the type to store to.
624 
625  /// This instruction implements SINT_TO_FP with the
626  /// integer source in memory and FP reg result. This corresponds to the
627  /// X86::FILD*m instructions. It has two inputs (token chain and address)
628  /// and two outputs (FP value and token chain). FILD_FLAG also produces a
629  /// flag). The integer source type is specified by the memory VT.
632 
633  /// This instruction implements a fp->int store from FP stack
634  /// slots. This corresponds to the fist instruction. It takes a
635  /// chain operand, value to store, address, and glue. The memory VT
636  /// specifies the type to store as.
638 
639  /// This instruction implements an extending load to FP stack slots.
640  /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
641  /// operand, and ptr to load from. The memory VT specifies the type to
642  /// load from.
644 
645  /// This instruction implements a truncating store from FP stack
646  /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
647  /// chain operand, value to store, address, and glue. The memory VT
648  /// specifies the type to store as.
650 
651  /// This instruction grabs the address of the next argument
652  /// from a va_list. (reads and modifies the va_list in memory)
654 
655  // Vector truncating store with unsigned/signed saturation
657  // Vector truncating masked store with unsigned/signed saturation
659 
660  // X86 specific gather and scatter
662 
663  // WARNING: Do not add anything in the end unless you want the node to
664  // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
665  // opcodes will be thought as target memory ops!
666  };
667  } // end namespace X86ISD
668 
669  /// Define some predicates that are used for node matching.
670  namespace X86 {
671  /// Returns true if Elt is a constant zero or floating point constant +0.0.
672  bool isZeroNode(SDValue Elt);
673 
674  /// Returns true of the given offset can be
675  /// fit into displacement field of the instruction.
677  bool hasSymbolicDisplacement = true);
678 
679  /// Determines whether the callee is required to pop its
680  /// own arguments. Callee pop is necessary to support tail calls.
682  bool is64Bit, bool IsVarArg, bool GuaranteeTCO);
683 
684  } // end namespace X86
685 
686  //===--------------------------------------------------------------------===//
687  // X86 Implementation of the TargetLowering interface
688  class X86TargetLowering final : public TargetLowering {
689  public:
690  explicit X86TargetLowering(const X86TargetMachine &TM,
691  const X86Subtarget &STI);
692 
693  unsigned getJumpTableEncoding() const override;
694  bool useSoftFloat() const override;
695 
696  void markLibCallAttributes(MachineFunction *MF, unsigned CC,
697  ArgListTy &Args) const override;
698 
699  MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override {
700  return MVT::i8;
701  }
702 
703  const MCExpr *
704  LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
705  const MachineBasicBlock *MBB, unsigned uid,
706  MCContext &Ctx) const override;
707 
708  /// Returns relocation base for the given PIC jumptable.
709  SDValue getPICJumpTableRelocBase(SDValue Table,
710  SelectionDAG &DAG) const override;
711  const MCExpr *
712  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
713  unsigned JTI, MCContext &Ctx) const override;
714 
715  /// Return the desired alignment for ByVal aggregate
716  /// function arguments in the caller parameter area. For X86, aggregates
717  /// that contains are placed at 16-byte boundaries while the rest are at
718  /// 4-byte boundaries.
719  unsigned getByValTypeAlignment(Type *Ty,
720  const DataLayout &DL) const override;
721 
722  /// Returns the target specific optimal type for load
723  /// and store operations as a result of memset, memcpy, and memmove
724  /// lowering. If DstAlign is zero that means it's safe to destination
725  /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
726  /// means there isn't a need to check it against alignment requirement,
727  /// probably because the source does not need to be loaded. If 'IsMemset' is
728  /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
729  /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
730  /// source is constant so it does not need to be loaded.
731  /// It returns EVT::Other if the type should be determined using generic
732  /// target-independent logic.
733  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
734  bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
735  const AttributeList &FuncAttributes) const override;
736 
737  /// Returns true if it's safe to use load / store of the
738  /// specified type to expand memcpy / memset inline. This is mostly true
739  /// for all types except for some special cases. For example, on X86
740  /// targets without SSE2 f64 load / store are done with fldl / fstpl which
741  /// also does type conversion. Note the specified type doesn't have to be
742  /// legal as the hook is used before type legalization.
743  bool isSafeMemOpType(MVT VT) const override;
744 
745  /// Returns true if the target allows unaligned memory accesses of the
746  /// specified type. Returns whether it is "fast" in the last argument.
747  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
749  bool *Fast) const override;
750 
751  /// Provide custom lowering hooks for some operations.
752  ///
753  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
754 
755  /// Places new result values for the node in Results (their number
756  /// and types must exactly match those of the original return values of
757  /// the node), or leaves Results empty, which indicates that the node is not
758  /// to be custom lowered after all.
759  void LowerOperationWrapper(SDNode *N,
761  SelectionDAG &DAG) const override;
762 
763  /// Replace the results of node with an illegal result
764  /// type with new values built out of custom code.
765  ///
766  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
767  SelectionDAG &DAG) const override;
768 
769  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
770 
771  // Return true if it is profitable to combine a BUILD_VECTOR with a
772  // stride-pattern to a shuffle and a truncate.
773  // Example of such a combine:
774  // v4i32 build_vector((extract_elt V, 1),
775  // (extract_elt V, 3),
776  // (extract_elt V, 5),
777  // (extract_elt V, 7))
778  // -->
779  // v4i32 truncate (bitcast (shuffle<1,u,3,u,4,u,5,u,6,u,7,u> V, u) to
780  // v4i64)
781  bool isDesirableToCombineBuildVectorToShuffleTruncate(
782  ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const override;
783 
784  /// Return true if the target has native support for
785  /// the specified value type and it is 'desirable' to use the type for the
786  /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
787  /// instruction encodings are longer and some i16 instructions are slow.
788  bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
789 
790  /// Return true if the target has native support for the
791  /// specified value type and it is 'desirable' to use the type. e.g. On x86
792  /// i16 is legal, but undesirable since i16 instruction encodings are longer
793  /// and some i16 instructions are slow.
794  bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
795 
797  EmitInstrWithCustomInserter(MachineInstr &MI,
798  MachineBasicBlock *MBB) const override;
799 
800  /// This method returns the name of a target specific DAG node.
801  const char *getTargetNodeName(unsigned Opcode) const override;
802 
803  /// Do not merge vector stores after legalization because that may conflict
804  /// with x86-specific store splitting optimizations.
805  bool mergeStoresAfterLegalization(EVT MemVT) const override {
806  return !MemVT.isVector();
807  }
808 
809  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
810  const SelectionDAG &DAG) const override;
811 
812  bool isCheapToSpeculateCttz() const override;
813 
814  bool isCheapToSpeculateCtlz() const override;
815 
816  bool isCtlzFast() const override;
817 
818  bool hasBitPreservingFPLogic(EVT VT) const override {
819  return VT == MVT::f32 || VT == MVT::f64 || VT.isVector();
820  }
821 
822  bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
823  // If the pair to store is a mixture of float and int values, we will
824  // save two bitwise instructions and one float-to-int instruction and
825  // increase one store instruction. There is potentially a more
826  // significant benefit because it avoids the float->int domain switch
827  // for input value. So It is more likely a win.
828  if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
829  (LTy.isInteger() && HTy.isFloatingPoint()))
830  return true;
831  // If the pair only contains int values, we will save two bitwise
832  // instructions and increase one store instruction (costing one more
833  // store buffer). Since the benefit is more blurred so we leave
834  // such pair out until we get testcase to prove it is a win.
835  return false;
836  }
837 
838  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
839 
840  bool hasAndNotCompare(SDValue Y) const override;
841 
842  bool hasAndNot(SDValue Y) const override;
843 
844  bool shouldFoldConstantShiftPairToMask(const SDNode *N,
845  CombineLevel Level) const override;
846 
847  bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override;
848 
849  bool
851  unsigned KeptBits) const override {
852  // For vectors, we don't have a preference..
853  if (XVT.isVector())
854  return false;
855 
856  auto VTIsOk = [](EVT VT) -> bool {
857  return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
858  VT == MVT::i64;
859  };
860 
861  // We are ok with KeptBitsVT being byte/word/dword, what MOVS supports.
862  // XVT will be larger than KeptBitsVT.
863  MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
864  return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
865  }
866 
867  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
869  return false;
870  return true;
871  }
872 
873  bool shouldSplatInsEltVarIndex(EVT VT) const override;
874 
875  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
876  return VT.isScalarInteger();
877  }
878 
879  /// Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
880  MVT hasFastEqualityCompare(unsigned NumBits) const override;
881 
882  /// Allow multiple load pairs per block for smaller and faster code.
883  unsigned getMemcmpEqZeroLoadsPerBlock() const override {
884  return 2;
885  }
886 
887  /// Return the value type to use for ISD::SETCC.
888  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
889  EVT VT) const override;
890 
891  bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
892  TargetLoweringOpt &TLO) const override;
893 
894  /// Determine which of the bits specified in Mask are known to be either
895  /// zero or one and return them in the KnownZero/KnownOne bitsets.
896  void computeKnownBitsForTargetNode(const SDValue Op,
897  KnownBits &Known,
898  const APInt &DemandedElts,
899  const SelectionDAG &DAG,
900  unsigned Depth = 0) const override;
901 
902  /// Determine the number of bits in the operation that are sign bits.
903  unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
904  const APInt &DemandedElts,
905  const SelectionDAG &DAG,
906  unsigned Depth) const override;
907 
908  bool SimplifyDemandedVectorEltsForTargetNode(SDValue Op,
909  const APInt &DemandedElts,
910  APInt &KnownUndef,
911  APInt &KnownZero,
912  TargetLoweringOpt &TLO,
913  unsigned Depth) const override;
914 
915  bool SimplifyDemandedBitsForTargetNode(SDValue Op,
916  const APInt &DemandedBits,
917  const APInt &DemandedElts,
918  KnownBits &Known,
919  TargetLoweringOpt &TLO,
920  unsigned Depth) const override;
921 
922  const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
923 
924  SDValue unwrapAddress(SDValue N) const override;
925 
926  SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
927 
928  bool ExpandInlineAsm(CallInst *CI) const override;
929 
930  ConstraintType getConstraintType(StringRef Constraint) const override;
931 
932  /// Examine constraint string and operand type and determine a weight value.
933  /// The operand object must already have been set up with the operand type.
935  getSingleConstraintMatchWeight(AsmOperandInfo &info,
936  const char *constraint) const override;
937 
938  const char *LowerXConstraint(EVT ConstraintVT) const override;
939 
940  /// Lower the specified operand into the Ops vector. If it is invalid, don't
941  /// add anything to Ops. If hasMemory is true it means one of the asm
942  /// constraint of the inline asm instruction being processed is 'm'.
943  void LowerAsmOperandForConstraint(SDValue Op,
944  std::string &Constraint,
945  std::vector<SDValue> &Ops,
946  SelectionDAG &DAG) const override;
947 
948  unsigned
949  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
950  if (ConstraintCode == "i")
952  else if (ConstraintCode == "o")
954  else if (ConstraintCode == "v")
956  else if (ConstraintCode == "X")
958  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
959  }
960 
961  /// Handle Lowering flag assembly outputs.
962  SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, SDLoc DL,
963  const AsmOperandInfo &Constraint,
964  SelectionDAG &DAG) const override;
965 
966  /// Given a physical register constraint
967  /// (e.g. {edx}), return the register number and the register class for the
968  /// register. This should only be used for C_Register constraints. On
969  /// error, this returns a register number of 0.
970  std::pair<unsigned, const TargetRegisterClass *>
971  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
972  StringRef Constraint, MVT VT) const override;
973 
974  /// Return true if the addressing mode represented
975  /// by AM is legal for this target, for a load/store of the specified type.
976  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
977  Type *Ty, unsigned AS,
978  Instruction *I = nullptr) const override;
979 
980  /// Return true if the specified immediate is legal
981  /// icmp immediate, that is the target has icmp instructions which can
982  /// compare a register against the immediate without having to materialize
983  /// the immediate into a register.
984  bool isLegalICmpImmediate(int64_t Imm) const override;
985 
986  /// Return true if the specified immediate is legal
987  /// add immediate, that is the target has add instructions which can
988  /// add a register and the immediate without having to materialize
989  /// the immediate into a register.
990  bool isLegalAddImmediate(int64_t Imm) const override;
991 
992  bool isLegalStoreImmediate(int64_t Imm) const override;
993 
994  /// Return the cost of the scaling factor used in the addressing
995  /// mode represented by AM for this target, for a load/store
996  /// of the specified type.
997  /// If the AM is supported, the return value must be >= 0.
998  /// If the AM is not supported, it returns a negative value.
999  int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
1000  unsigned AS) const override;
1001 
1002  bool isVectorShiftByScalarCheap(Type *Ty) const override;
1003 
1004  /// Add x86-specific opcodes to the default list.
1005  bool isBinOp(unsigned Opcode) const override;
1006 
1007  /// Returns true if the opcode is a commutative binary operation.
1008  bool isCommutativeBinOp(unsigned Opcode) const override;
1009 
1010  /// Return true if it's free to truncate a value of
1011  /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1012  /// register EAX to i16 by referencing its sub-register AX.
1013  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
1014  bool isTruncateFree(EVT VT1, EVT VT2) const override;
1015 
1016  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
1017 
1018  /// Return true if any actual instruction that defines a
1019  /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
1020  /// register. This does not necessarily include registers defined in
1021  /// unknown ways, such as incoming arguments, or copies from unknown
1022  /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1023  /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1024  /// all instructions that define 32-bit values implicit zero-extend the
1025  /// result out to 64 bits.
1026  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
1027  bool isZExtFree(EVT VT1, EVT VT2) const override;
1028  bool isZExtFree(SDValue Val, EVT VT2) const override;
1029 
1030  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
1031  /// extend node) is profitable.
1032  bool isVectorLoadExtDesirable(SDValue) const override;
1033 
1034  /// Return true if an FMA operation is faster than a pair of fmul and fadd
1035  /// instructions. fmuladd intrinsics will be expanded to FMAs when this
1036  /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
1037  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
1038 
1039  /// Return true if it's profitable to narrow
1040  /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1041  /// from i32 to i8 but not from i32 to i16.
1042  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
1043 
1044  /// Given an intrinsic, checks if on the target the intrinsic will need to map
1045  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
1046  /// true and stores the intrinsic information into the IntrinsicInfo that was
1047  /// passed to the function.
1048  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
1049  MachineFunction &MF,
1050  unsigned Intrinsic) const override;
1051 
1052  /// Returns true if the target can instruction select the
1053  /// specified FP immediate natively. If false, the legalizer will
1054  /// materialize the FP immediate as a load from a constant pool.
1055  bool isFPImmLegal(const APFloat &Imm, EVT VT,
1056  bool ForCodeSize) const override;
1057 
1058  /// Targets can use this to indicate that they only support *some*
1059  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
1060  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
1061  /// be legal.
1062  bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
1063 
1064  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
1065  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
1066  /// constant pool entry.
1067  bool isVectorClearMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
1068 
1069  /// Returns true if lowering to a jump table is allowed.
1070  bool areJTsAllowed(const Function *Fn) const override;
1071 
1072  /// If true, then instruction selection should
1073  /// seek to shrink the FP constant of the specified type to a smaller type
1074  /// in order to save space and / or reduce runtime.
1075  bool ShouldShrinkFPConstant(EVT VT) const override {
1076  // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
1077  // expensive than a straight movsd. On the other hand, it's important to
1078  // shrink long double fp constant since fldt is very slow.
1079  return !X86ScalarSSEf64 || VT == MVT::f80;
1080  }
1081 
1082  /// Return true if we believe it is correct and profitable to reduce the
1083  /// load node to a smaller type.
1084  bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
1085  EVT NewVT) const override;
1086 
1087  /// Return true if the specified scalar FP type is computed in an SSE
1088  /// register, not on the X87 floating point stack.
1089  bool isScalarFPTypeInSSEReg(EVT VT) const {
1090  return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
1091  (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
1092  }
1093 
1094  /// Returns true if it is beneficial to convert a load of a constant
1095  /// to just the constant itself.
1096  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1097  Type *Ty) const override;
1098 
1099  bool reduceSelectOfFPConstantLoads(bool IsFPSetCC) const override;
1100 
1101  bool convertSelectOfConstantsToMath(EVT VT) const override;
1102 
1103  bool decomposeMulByConstant(EVT VT, SDValue C) const override;
1104 
1105  bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT,
1106  bool IsSigned) const override;
1107 
1108  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1109  /// with this index.
1110  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
1111  unsigned Index) const override;
1112 
1113  /// Scalar ops always have equal or better analysis/performance/power than
1114  /// the vector equivalent, so this always makes sense if the scalar op is
1115  /// supported.
1116  bool shouldScalarizeBinop(SDValue) const override;
1117 
1118  /// Extract of a scalar FP value from index 0 of a vector is free.
1119  bool isExtractVecEltCheap(EVT VT, unsigned Index) const override {
1120  EVT EltVT = VT.getScalarType();
1121  return (EltVT == MVT::f32 || EltVT == MVT::f64) && Index == 0;
1122  }
1123 
1124  /// Overflow nodes should get combined/lowered to optimal instructions
1125  /// (they should allow eliminating explicit compares by getting flags from
1126  /// math ops).
1127  bool shouldFormOverflowOp(unsigned Opcode, EVT VT) const override;
1128 
1129  bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem,
1130  unsigned AddrSpace) const override {
1131  // If we can replace more than 2 scalar stores, there will be a reduction
1132  // in instructions even after we add a vector constant load.
1133  return NumElem > 2;
1134  }
1135 
1136  bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT) const override;
1137 
1138  /// Intel processors have a unified instruction and data cache
1139  const char * getClearCacheBuiltinName() const override {
1140  return nullptr; // nothing to do, move along.
1141  }
1142 
1143  unsigned getRegisterByName(const char* RegName, EVT VT,
1144  SelectionDAG &DAG) const override;
1145 
1146  /// If a physical register, this returns the register that receives the
1147  /// exception address on entry to an EH pad.
1148  unsigned
1149  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
1150 
1151  /// If a physical register, this returns the register that receives the
1152  /// exception typeid on entry to a landing pad.
1153  unsigned
1154  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
1155 
1156  virtual bool needsFixedCatchObjects() const override;
1157 
1158  /// This method returns a target specific FastISel object,
1159  /// or null if the target does not support "fast" ISel.
1161  const TargetLibraryInfo *libInfo) const override;
1162 
1163  /// If the target has a standard location for the stack protector cookie,
1164  /// returns the address of that location. Otherwise, returns nullptr.
1165  Value *getIRStackGuard(IRBuilder<> &IRB) const override;
1166 
1167  bool useLoadStackGuardNode() const override;
1168  bool useStackGuardXorFP() const override;
1169  void insertSSPDeclarations(Module &M) const override;
1170  Value *getSDagStackGuard(const Module &M) const override;
1171  Function *getSSPStackGuardCheck(const Module &M) const override;
1172  SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
1173  const SDLoc &DL) const override;
1174 
1175 
1176  /// Return true if the target stores SafeStack pointer at a fixed offset in
1177  /// some non-standard address space, and populates the address space and
1178  /// offset as appropriate.
1179  Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
1180 
1181  SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
1182  SelectionDAG &DAG) const;
1183 
1184  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
1185 
1186  /// Customize the preferred legalization strategy for certain types.
1187  LegalizeTypeAction getPreferredVectorAction(MVT VT) const override;
1188 
1189  MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
1190  EVT VT) const override;
1191 
1192  unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1193  CallingConv::ID CC,
1194  EVT VT) const override;
1195 
1196  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
1197 
1198  bool supportSwiftError() const override;
1199 
1200  StringRef getStackProbeSymbolName(MachineFunction &MF) const override;
1201 
1202  bool hasVectorBlend() const override { return true; }
1203 
1204  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
1205 
1206  /// Lower interleaved load(s) into target specific
1207  /// instructions/intrinsics.
1208  bool lowerInterleavedLoad(LoadInst *LI,
1210  ArrayRef<unsigned> Indices,
1211  unsigned Factor) const override;
1212 
1213  /// Lower interleaved store(s) into target specific
1214  /// instructions/intrinsics.
1215  bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
1216  unsigned Factor) const override;
1217 
1218  SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value,
1219  SDValue Addr, SelectionDAG &DAG)
1220  const override;
1221 
1222  protected:
1223  std::pair<const TargetRegisterClass *, uint8_t>
1224  findRepresentativeClass(const TargetRegisterInfo *TRI,
1225  MVT VT) const override;
1226 
1227  private:
1228  /// Keep a reference to the X86Subtarget around so that we can
1229  /// make the right decision when generating code for different targets.
1230  const X86Subtarget &Subtarget;
1231 
1232  /// Select between SSE or x87 floating point ops.
1233  /// When SSE is available, use it for f32 operations.
1234  /// When SSE2 is available, use it for f64 operations.
1235  bool X86ScalarSSEf32;
1236  bool X86ScalarSSEf64;
1237 
1238  /// A list of legal FP immediates.
1239  std::vector<APFloat> LegalFPImmediates;
1240 
1241  /// Indicate that this x86 target can instruction
1242  /// select the specified FP immediate natively.
1243  void addLegalFPImmediate(const APFloat& Imm) {
1244  LegalFPImmediates.push_back(Imm);
1245  }
1246 
1247  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1248  CallingConv::ID CallConv, bool isVarArg,
1250  const SDLoc &dl, SelectionDAG &DAG,
1251  SmallVectorImpl<SDValue> &InVals,
1252  uint32_t *RegMask) const;
1253  SDValue LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
1254  const SmallVectorImpl<ISD::InputArg> &ArgInfo,
1255  const SDLoc &dl, SelectionDAG &DAG,
1256  const CCValAssign &VA, MachineFrameInfo &MFI,
1257  unsigned i) const;
1259  const SDLoc &dl, SelectionDAG &DAG,
1260  const CCValAssign &VA,
1261  ISD::ArgFlagsTy Flags) const;
1262 
1263  // Call lowering helpers.
1264 
1265  /// Check whether the call is eligible for tail call optimization. Targets
1266  /// that want to do tail call optimization should implement this function.
1267  bool IsEligibleForTailCallOptimization(SDValue Callee,
1268  CallingConv::ID CalleeCC,
1269  bool isVarArg,
1270  bool isCalleeStructRet,
1271  bool isCallerStructRet,
1272  Type *RetTy,
1273  const SmallVectorImpl<ISD::OutputArg> &Outs,
1274  const SmallVectorImpl<SDValue> &OutVals,
1275  const SmallVectorImpl<ISD::InputArg> &Ins,
1276  SelectionDAG& DAG) const;
1277  SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
1278  SDValue Chain, bool IsTailCall,
1279  bool Is64Bit, int FPDiff,
1280  const SDLoc &dl) const;
1281 
1282  unsigned GetAlignedArgumentStackSize(unsigned StackSize,
1283  SelectionDAG &DAG) const;
1284 
1285  unsigned getAddressSpace(void) const;
1286 
1287  SDValue FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool isSigned) const;
1288 
1289  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1290  SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
1293 
1294  unsigned getGlobalWrapperKind(const GlobalValue *GV = nullptr,
1295  const unsigned char OpFlags = 0) const;
1296  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1297  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1298  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1299  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1300  SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
1301 
1302  /// Creates target global address or external symbol nodes for calls or
1303  /// other uses.
1304  SDValue LowerGlobalOrExternal(SDValue Op, SelectionDAG &DAG,
1305  bool ForCall) const;
1306 
1307  SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1308  SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1309  SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1310  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1311  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1312  SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
1313  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1314  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
1315  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1317  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1318  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1319  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1320  SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1321  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1322  SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1323  SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
1324  SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1325  SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1326  SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
1327  SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1328  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1329  SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
1330  SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const;
1331  SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const;
1332  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1333 
1334  SDValue
1335  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1336  const SmallVectorImpl<ISD::InputArg> &Ins,
1337  const SDLoc &dl, SelectionDAG &DAG,
1338  SmallVectorImpl<SDValue> &InVals) const override;
1339  SDValue LowerCall(CallLoweringInfo &CLI,
1340  SmallVectorImpl<SDValue> &InVals) const override;
1341 
1342  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1343  const SmallVectorImpl<ISD::OutputArg> &Outs,
1344  const SmallVectorImpl<SDValue> &OutVals,
1345  const SDLoc &dl, SelectionDAG &DAG) const override;
1346 
1347  bool supportSplitCSR(MachineFunction *MF) const override {
1349  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
1350  }
1351  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
1352  void insertCopiesSplitCSR(
1353  MachineBasicBlock *Entry,
1354  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
1355 
1356  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1357 
1358  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1359 
1360  EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
1361  ISD::NodeType ExtendKind) const override;
1362 
1363  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1364  bool isVarArg,
1365  const SmallVectorImpl<ISD::OutputArg> &Outs,
1366  LLVMContext &Context) const override;
1367 
1368  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1369 
1371  shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
1372  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1374  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1375 
1376  LoadInst *
1377  lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1378 
1379  bool needsCmpXchgNb(Type *MemType) const;
1380 
1381  void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
1382  MachineBasicBlock *DispatchBB, int FI) const;
1383 
1384  // Utility function to emit the low-level va_arg code for X86-64.
1386  EmitVAARG64WithCustomInserter(MachineInstr &MI,
1387  MachineBasicBlock *MBB) const;
1388 
1389  /// Utility function to emit the xmm reg save portion of va_start.
1391  EmitVAStartSaveXMMRegsWithCustomInserter(MachineInstr &BInstr,
1392  MachineBasicBlock *BB) const;
1393 
1394  MachineBasicBlock *EmitLoweredCascadedSelect(MachineInstr &MI1,
1395  MachineInstr &MI2,
1396  MachineBasicBlock *BB) const;
1397 
1398  MachineBasicBlock *EmitLoweredSelect(MachineInstr &I,
1399  MachineBasicBlock *BB) const;
1400 
1401  MachineBasicBlock *EmitLoweredAtomicFP(MachineInstr &I,
1402  MachineBasicBlock *BB) const;
1403 
1404  MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI,
1405  MachineBasicBlock *BB) const;
1406 
1407  MachineBasicBlock *EmitLoweredCatchPad(MachineInstr &MI,
1408  MachineBasicBlock *BB) const;
1409 
1410  MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &MI,
1411  MachineBasicBlock *BB) const;
1412 
1413  MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr &MI,
1414  MachineBasicBlock *BB) const;
1415 
1416  MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &MI,
1417  MachineBasicBlock *BB) const;
1418 
1419  MachineBasicBlock *EmitLoweredRetpoline(MachineInstr &MI,
1420  MachineBasicBlock *BB) const;
1421 
1422  MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
1423  MachineBasicBlock *MBB) const;
1424 
1425  void emitSetJmpShadowStackFix(MachineInstr &MI,
1426  MachineBasicBlock *MBB) const;
1427 
1428  MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
1429  MachineBasicBlock *MBB) const;
1430 
1431  MachineBasicBlock *emitLongJmpShadowStackFix(MachineInstr &MI,
1432  MachineBasicBlock *MBB) const;
1433 
1434  MachineBasicBlock *emitFMA3Instr(MachineInstr &MI,
1435  MachineBasicBlock *MBB) const;
1436 
1437  MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr &MI,
1438  MachineBasicBlock *MBB) const;
1439 
1440  /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1441  /// equivalent, for use with the given x86 condition code.
1442  SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, const SDLoc &dl,
1443  SelectionDAG &DAG) const;
1444 
1445  /// Convert a comparison if required by the subtarget.
1446  SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1447 
1448  /// Emit flags for the given setcc condition and operands. Also returns the
1449  /// corresponding X86 condition code constant in X86CC.
1450  SDValue emitFlagsForSetcc(SDValue Op0, SDValue Op1,
1451  ISD::CondCode CC, const SDLoc &dl,
1452  SelectionDAG &DAG,
1453  SDValue &X86CC) const;
1454 
1455  /// Check if replacement of SQRT with RSQRT should be disabled.
1456  bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override;
1457 
1458  /// Use rsqrt* to speed up sqrt calculations.
1459  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1460  int &RefinementSteps, bool &UseOneConstNR,
1461  bool Reciprocal) const override;
1462 
1463  /// Use rcp* to speed up fdiv calculations.
1464  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1465  int &RefinementSteps) const override;
1466 
1467  /// Reassociate floating point divisions into multiply by reciprocal.
1468  unsigned combineRepeatedFPDivisors() const override;
1469  };
1470 
1471  namespace X86 {
1473  const TargetLibraryInfo *libInfo);
1474  } // end namespace X86
1475 
1476  // Base class for all X86 non-masked store operations.
1477  class X86StoreSDNode : public MemSDNode {
1478  public:
1479  X86StoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl,
1480  SDVTList VTs, EVT MemVT,
1481  MachineMemOperand *MMO)
1482  :MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {}
1483  const SDValue &getValue() const { return getOperand(1); }
1484  const SDValue &getBasePtr() const { return getOperand(2); }
1485 
1486  static bool classof(const SDNode *N) {
1487  return N->getOpcode() == X86ISD::VTRUNCSTORES ||
1489  }
1490  };
1491 
1492  // Base class for all X86 masked store operations.
1493  // The class has the same order of operands as MaskedStoreSDNode for
1494  // convenience.
1496  public:
1497  X86MaskedStoreSDNode(unsigned Opcode, unsigned Order,
1498  const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1499  MachineMemOperand *MMO)
1500  : MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {}
1501 
1502  const SDValue &getValue() const { return getOperand(1); }
1503  const SDValue &getBasePtr() const { return getOperand(2); }
1504  const SDValue &getMask() const { return getOperand(3); }
1505 
1506  static bool classof(const SDNode *N) {
1507  return N->getOpcode() == X86ISD::VMTRUNCSTORES ||
1509  }
1510  };
1511 
1512  // X86 Truncating Store with Signed saturation.
1514  public:
1515  TruncSStoreSDNode(unsigned Order, const DebugLoc &dl,
1516  SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
1517  : X86StoreSDNode(X86ISD::VTRUNCSTORES, Order, dl, VTs, MemVT, MMO) {}
1518 
1519  static bool classof(const SDNode *N) {
1520  return N->getOpcode() == X86ISD::VTRUNCSTORES;
1521  }
1522  };
1523 
1524  // X86 Truncating Store with Unsigned saturation.
1526  public:
1527  TruncUSStoreSDNode(unsigned Order, const DebugLoc &dl,
1528  SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
1529  : X86StoreSDNode(X86ISD::VTRUNCSTOREUS, Order, dl, VTs, MemVT, MMO) {}
1530 
1531  static bool classof(const SDNode *N) {
1532  return N->getOpcode() == X86ISD::VTRUNCSTOREUS;
1533  }
1534  };
1535 
1536  // X86 Truncating Masked Store with Signed saturation.
1538  public:
1539  MaskedTruncSStoreSDNode(unsigned Order,
1540  const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1541  MachineMemOperand *MMO)
1542  : X86MaskedStoreSDNode(X86ISD::VMTRUNCSTORES, Order, dl, VTs, MemVT, MMO) {}
1543 
1544  static bool classof(const SDNode *N) {
1545  return N->getOpcode() == X86ISD::VMTRUNCSTORES;
1546  }
1547  };
1548 
1549  // X86 Truncating Masked Store with Unsigned saturation.
1551  public:
1553  const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1554  MachineMemOperand *MMO)
1555  : X86MaskedStoreSDNode(X86ISD::VMTRUNCSTOREUS, Order, dl, VTs, MemVT, MMO) {}
1556 
1557  static bool classof(const SDNode *N) {
1558  return N->getOpcode() == X86ISD::VMTRUNCSTOREUS;
1559  }
1560  };
1561 
1562  // X86 specific Gather/Scatter nodes.
1563  // The class has the same order of operands as MaskedGatherScatterSDNode for
1564  // convenience.
1566  public:
1567  X86MaskedGatherScatterSDNode(unsigned Opc, unsigned Order,
1568  const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1569  MachineMemOperand *MMO)
1570  : MemSDNode(Opc, Order, dl, VTs, MemVT, MMO) {}
1571 
1572  const SDValue &getBasePtr() const { return getOperand(3); }
1573  const SDValue &getIndex() const { return getOperand(4); }
1574  const SDValue &getMask() const { return getOperand(2); }
1575  const SDValue &getScale() const { return getOperand(5); }
1576 
1577  static bool classof(const SDNode *N) {
1578  return N->getOpcode() == X86ISD::MGATHER ||
1579  N->getOpcode() == X86ISD::MSCATTER;
1580  }
1581  };
1582 
1584  public:
1585  X86MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
1586  EVT MemVT, MachineMemOperand *MMO)
1587  : X86MaskedGatherScatterSDNode(X86ISD::MGATHER, Order, dl, VTs, MemVT,
1588  MMO) {}
1589 
1590  const SDValue &getPassThru() const { return getOperand(1); }
1591 
1592  static bool classof(const SDNode *N) {
1593  return N->getOpcode() == X86ISD::MGATHER;
1594  }
1595  };
1596 
1598  public:
1599  X86MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
1600  EVT MemVT, MachineMemOperand *MMO)
1601  : X86MaskedGatherScatterSDNode(X86ISD::MSCATTER, Order, dl, VTs, MemVT,
1602  MMO) {}
1603 
1604  const SDValue &getValue() const { return getOperand(1); }
1605 
1606  static bool classof(const SDNode *N) {
1607  return N->getOpcode() == X86ISD::MSCATTER;
1608  }
1609  };
1610 
1611  /// Generate unpacklo/unpackhi shuffle mask.
1612  template <typename T = int>
1614  bool Unary) {
1615  assert(Mask.empty() && "Expected an empty shuffle mask vector");
1616  int NumElts = VT.getVectorNumElements();
1617  int NumEltsInLane = 128 / VT.getScalarSizeInBits();
1618  for (int i = 0; i < NumElts; ++i) {
1619  unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
1620  int Pos = (i % NumEltsInLane) / 2 + LaneStart;
1621  Pos += (Unary ? 0 : NumElts * (i % 2));
1622  Pos += (Lo ? 0 : NumEltsInLane / 2);
1623  Mask.push_back(Pos);
1624  }
1625  }
1626 
1627  /// Helper function to scale a shuffle or target shuffle mask, replacing each
1628  /// mask index with the scaled sequential indices for an equivalent narrowed
1629  /// mask. This is the reverse process to canWidenShuffleElements, but can
1630  /// always succeed.
1631  template <typename T>
1633  SmallVectorImpl<T> &ScaledMask) {
1634  assert(0 < Scale && "Unexpected scaling factor");
1635  size_t NumElts = Mask.size();
1636  ScaledMask.assign(NumElts * Scale, -1);
1637 
1638  for (int i = 0; i != (int)NumElts; ++i) {
1639  int M = Mask[i];
1640 
1641  // Repeat sentinel values in every mask element.
1642  if (M < 0) {
1643  for (int s = 0; s != Scale; ++s)
1644  ScaledMask[(Scale * i) + s] = M;
1645  continue;
1646  }
1647 
1648  // Scale mask element and increment across each mask element.
1649  for (int s = 0; s != Scale; ++s)
1650  ScaledMask[(Scale * i) + s] = (Scale * M) + s;
1651  }
1652  }
1653 } // end namespace llvm
1654 
1655 #endif // LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
const SDValue & getIndex() const
Double shift instructions.
uint64_t CallInst * C
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
static MVT getIntegerVT(unsigned BitWidth)
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
This instruction implements a fp->int store from FP stack slots.
TruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:913
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Vector comparison generating mask bits for fp and integer signed and unsigned data types...
Repeat move, corresponds to X86::REP_MOVSx.
void createUnpackShuffleMask(MVT VT, SmallVectorImpl< T > &Mask, bool Lo, bool Unary)
Generate unpacklo/unpackhi shuffle mask.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
static bool classof(const SDNode *N)
Return with a flag operand.
const SDValue & getValue() const
const SDValue & getBasePtr() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const SDValue & getScale() const
bool mergeStoresAfterLegalization(EVT MemVT) const override
Do not merge vector stores after legalization because that may conflict with x86-specific store split...
Tail call return.
Compute Double Block Packed Sum-Absolute-Differences.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
static bool classof(const SDNode *N)
Same as call except it adds the NoTrack prefix.
static void LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, const SDLoc &dl)
LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls...
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
X86 conditional moves.
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:145
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned getVectorNumElements() const
Function Alias Analysis Results
This instruction constructs a fixed permutation of two input vectors.
bool isExtractVecEltCheap(EVT VT, unsigned Index) const override
Extract of a scalar FP value from index 0 of a vector is free.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
static bool classof(const SDNode *N)
SSE4A Extraction and Insertion.
static bool classof(const SDNode *N)
An instruction for reading from memory.
Definition: Instructions.h:167
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:691
Bitwise logical ANDNOT of floating point values.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
bool isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
X86MaskedGatherScatterSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
X86 compare and logical compare instructions.
MaskedTruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
Extract an 8-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRB.
A description of a memory reference used in the backend.
X86StoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
Dynamic (non-constant condition) vector blend where only the sign bits of the condition elements are ...
Bitwise Logical AND NOT of Packed FP values.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:742
This instruction implements SINT_TO_FP with the integer source in memory and FP reg result...
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Integer horizontal add/sub.
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
Copies a 64-bit value from the low word of an XMM vector to an MMX vector.
void assign(size_type NumElts, const T &Elt)
Definition: SmallVector.h:412
Context object for machine code objects.
Definition: MCContext.h:62
static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
Copies a 32-bit value from the low word of a MMX vector to a GPR.
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:400
X86 FP SETCC, similar to above, but with output as an i1 mask and and a version with SAE...
Return from interrupt. Operand 0 is the number of bytes to pop.
This contains information for each constraint that we are lowering.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
An instruction for storing to memory.
Definition: Instructions.h:320
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:995
static bool classof(const SDNode *N)
This instruction implements FP_TO_SINT with the integer destination in memory and a FP reg source...
X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
const SDValue & getBasePtr() const
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Floating point horizontal add/sub.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Bitwise logical XOR of floating point values.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
static bool classof(const SDNode *N)
const SDValue & getMask() const
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This instruction implements an extending load to FP stack slots.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
Insert any element of a 4 x float vector into any element of a destination 4 x floatvector.
unsigned getScalarSizeInBits() const
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
This is an important base class in LLVM.
Definition: Constant.h:41
Repeat fill, corresponds to X86::REP_STOSx.
static bool is64Bit(const char *name)
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:970
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
X86 conditional branches.
CombineLevel
Definition: DAGCombine.h:15
Insert the lower 16-bits of a 32-bit value to a vector, corresponds to X86::PINSRW.
Commutative FMIN and FMAX.
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
On Darwin, this node represents the result of the popl at function entry, used for PIC code...
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
const SDValue & getValue() const
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
lazy value info
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
These operations represent an abstract X86 call instruction, which includes a bunch of information...
Floating point max and min.
static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG)
TruncSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
bool isScalarFPTypeInSSEReg(EVT VT) const
Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating p...
Copies a GPR into the low 32-bit word of a MMX vector and zero out the high word. ...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
AddressSpace
Definition: NVPTXBaseInfo.h:21
unsigned getMemcmpEqZeroLoadsPerBlock() const override
Allow multiple load pairs per block for smaller and faster code.
X86MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
This is an abstract virtual class for memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Bit scan reverse.
Floating point reciprocal-sqrt and reciprocal approximation.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:920
const SDValue & getValue() const
Represents one node in the SelectionDAG.
X86 bit-test instructions.
static bool Enabled
Definition: Statistic.cpp:50
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static bool classof(const SDNode *N)
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
MaskedTruncSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
static bool classof(const SDNode *N)
Bit scan forward.
const char * getClearCacheBuiltinName() const override
Intel processors have a unified instruction and data cache.
Flags
Flags values. These may be or&#39;d together.
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Representation of each machine instruction.
Definition: MachineInstr.h:63
static unsigned getScalingFactorCost(const TargetTransformInfo &TTI, const LSRUse &LU, const Formula &F, const Loop &L)
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
Insert the lower 8-bits of a 32-bit value to a vector, corresponds to X86::PINSRB.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
A wrapper node for TargetConstantPool, TargetJumpTable, TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress, MCSymbol and TargetBlockAddress.
Bitwise logical AND of floating point values.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:611
static bool classof(const SDNode *N)
X86MaskedStoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
uint32_t Size
Definition: Profile.cpp:46
LOCK-prefixed arithmetic read-modify-write instructions.
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Extract a 16-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRW.
bool hasVectorBlend() const override
Return true if the target has a vector blend instruction.
Blend where the selector is an immediate.
X86MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
This instruction implements a truncating store from FP stack slots.
Combined add and sub on an FP vector.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
This instruction grabs the address of the next argument from a va_list.
LLVM Value Representation.
Definition: Value.h:72
Bitwise logical OR of floating point values.
const SDValue & getBasePtr() const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
IRTranslator LLVM IR MI
bool isZeroNode(SDValue Elt)
Returns true if Elt is a constant zero or floating point constant +0.0.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement=true)
Returns true of the given offset can be fit into displacement field of the instruction.
const SDValue & getPassThru() const
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Compute Sum of Absolute Differences.
Scalar intrinsic floating point max and min.
MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
void scaleShuffleMask(int Scale, ArrayRef< T > Mask, SmallVectorImpl< T > &ScaledMask)
Helper function to scale a shuffle or target shuffle mask, replacing each mask index with the scaled ...
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
BRIND node with NoTrack prefix.
Shuffle 16 8-bit values within a vector.
This file describes how to lower LLVM code to machine code.
Special wrapper used under X86-64 PIC mode for RIP relative displacements.
This class is used to represent ISD::LOAD nodes.