LLVM  9.0.0svn
X86ISelLowering.cpp
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1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86IntrinsicsInfo.h"
21 #include "X86MachineFunctionInfo.h"
22 #include "X86TargetMachine.h"
23 #include "X86TargetObjectFile.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringSwitch.h"
39 #include "llvm/IR/CallSite.h"
40 #include "llvm/IR/CallingConv.h"
41 #include "llvm/IR/Constants.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/DiagnosticInfo.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalAlias.h"
46 #include "llvm/IR/GlobalVariable.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/MC/MCAsmInfo.h"
50 #include "llvm/MC/MCContext.h"
51 #include "llvm/MC/MCExpr.h"
52 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/KnownBits.h"
59 #include <algorithm>
60 #include <bitset>
61 #include <cctype>
62 #include <numeric>
63 using namespace llvm;
64 
65 #define DEBUG_TYPE "x86-isel"
66 
67 STATISTIC(NumTailCalls, "Number of tail calls");
68 
70  "x86-experimental-vector-widening-legalization", cl::init(false),
71  cl::desc("Enable an experimental vector type legalization through widening "
72  "rather than promotion."),
73  cl::Hidden);
74 
76  "x86-experimental-pref-loop-alignment", cl::init(4),
77  cl::desc("Sets the preferable loop alignment for experiments "
78  "(the last x86-experimental-pref-loop-alignment bits"
79  " of the loop header PC will be 0)."),
80  cl::Hidden);
81 
83  "mul-constant-optimization", cl::init(true),
84  cl::desc("Replace 'mul x, Const' with more effective instructions like "
85  "SHIFT, LEA, etc."),
86  cl::Hidden);
87 
88 /// Call this when the user attempts to do something unsupported, like
89 /// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
90 /// report_fatal_error, so calling code should attempt to recover without
91 /// crashing.
92 static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
93  const char *Msg) {
95  DAG.getContext()->diagnose(
97 }
98 
100  const X86Subtarget &STI)
101  : TargetLowering(TM), Subtarget(STI) {
102  bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
103  X86ScalarSSEf64 = Subtarget.hasSSE2();
104  X86ScalarSSEf32 = Subtarget.hasSSE1();
106 
107  // Set up the TargetLowering object.
108 
109  // X86 is weird. It always uses i8 for shift amounts and setcc results.
111  // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
113 
114  // For 64-bit, since we have so many registers, use the ILP scheduler.
115  // For 32-bit, use the register pressure specific scheduling.
116  // For Atom, always use ILP scheduling.
117  if (Subtarget.isAtom())
119  else if (Subtarget.is64Bit())
121  else
123  const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
125 
126  // Bypass expensive divides and use cheaper ones.
127  if (TM.getOptLevel() >= CodeGenOpt::Default) {
128  if (Subtarget.hasSlowDivide32())
129  addBypassSlowDiv(32, 8);
130  if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
131  addBypassSlowDiv(64, 32);
132  }
133 
134  if (Subtarget.isTargetKnownWindowsMSVC() ||
135  Subtarget.isTargetWindowsItanium()) {
136  // Setup Windows compiler runtime calls.
137  setLibcallName(RTLIB::SDIV_I64, "_alldiv");
138  setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
139  setLibcallName(RTLIB::SREM_I64, "_allrem");
140  setLibcallName(RTLIB::UREM_I64, "_aullrem");
141  setLibcallName(RTLIB::MUL_I64, "_allmul");
147  }
148 
149  if (Subtarget.isTargetDarwin()) {
150  // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
151  setUseUnderscoreSetJmp(false);
153  } else if (Subtarget.isTargetWindowsGNU()) {
154  // MS runtime is weird: it exports _setjmp, but longjmp!
157  } else {
160  }
161 
162  // Set up the register classes.
163  addRegisterClass(MVT::i8, &X86::GR8RegClass);
164  addRegisterClass(MVT::i16, &X86::GR16RegClass);
165  addRegisterClass(MVT::i32, &X86::GR32RegClass);
166  if (Subtarget.is64Bit())
167  addRegisterClass(MVT::i64, &X86::GR64RegClass);
168 
169  for (MVT VT : MVT::integer_valuetypes())
171 
172  // We don't accept any truncstore of integer registers.
179 
181 
182  // SETOEQ and SETUNE require checking two conditions.
189 
190  // Integer absolute.
191  if (Subtarget.hasCMov()) {
194  if (Subtarget.is64Bit())
196  }
197 
198  // Funnel shifts.
199  for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
200  setOperationAction(ShiftOp , MVT::i16 , Custom);
201  setOperationAction(ShiftOp , MVT::i32 , Custom);
202  if (Subtarget.is64Bit())
203  setOperationAction(ShiftOp , MVT::i64 , Custom);
204  }
205 
206  // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
207  // operation.
211 
212  if (Subtarget.is64Bit()) {
213  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512())
214  // f32/f64 are legal, f80 is custom.
216  else
219  } else if (!Subtarget.useSoftFloat()) {
220  // We have an algorithm for SSE2->double, and we turn this into a
221  // 64-bit FILD followed by conditional FADD for other targets.
223  // We have an algorithm for SSE2, and we turn this into a 64-bit
224  // FILD or VCVTUSI2SS/SD for other targets.
226  } else {
228  }
229 
230  // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
231  // this operation.
234 
235  if (!Subtarget.useSoftFloat()) {
236  // SSE has no i16 to fp conversion, only i32.
237  if (X86ScalarSSEf32) {
239  // f32 and f64 cases are Legal, f80 case is not
241  } else {
244  }
245  } else {
248  }
249 
250  // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
251  // this operation.
254 
255  if (!Subtarget.useSoftFloat()) {
256  // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
257  // are Legal, f80 is custom lowered.
260 
261  if (X86ScalarSSEf32) {
263  // f32 and f64 cases are Legal, f80 case is not
265  } else {
268  }
269  } else {
273  }
274 
275  // Handle FP_TO_UINT by promoting the destination to a larger signed
276  // conversion.
280 
281  if (Subtarget.is64Bit()) {
282  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
283  // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
286  } else {
289  }
290  } else if (!Subtarget.useSoftFloat()) {
291  // Since AVX is a superset of SSE3, only check for SSE here.
292  if (Subtarget.hasSSE1() && !Subtarget.hasSSE3())
293  // Expand FP_TO_UINT into a select.
294  // FIXME: We would like to use a Custom expander here eventually to do
295  // the optimal thing for SSE vs. the default expansion in the legalizer.
297  else
298  // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
299  // With SSE3 we can use fisttpll to convert to a signed i64; without
300  // SSE, we're stuck with a fistpll.
302 
304  }
305 
306  // TODO: when we have SSE, these could be more efficient, by using movd/movq.
307  if (!X86ScalarSSEf64) {
310  if (Subtarget.is64Bit()) {
312  // Without SSE, i64->f64 goes through memory.
314  }
315  } else if (!Subtarget.is64Bit())
317 
318  // Scalar integer divide and remainder are lowered to use operations that
319  // produce two results, to match the available instructions. This exposes
320  // the two-result form to trivial CSE, which is able to combine x/y and x%y
321  // into a single instruction.
322  //
323  // Scalar integer multiply-high is also lowered to use two-result
324  // operations, to match the available instructions. However, plain multiply
325  // (low) operations are left as Legal, as there are single-result
326  // instructions for this in x86. Using the two-result multiply instructions
327  // when both high and low results are needed must be arranged by dagcombine.
328  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
335  }
336 
339  for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
343  }
344  if (Subtarget.is64Bit())
350 
355 
356  // Promote the i8 variants and force them on up to i32 which has a shorter
357  // encoding.
360  if (!Subtarget.hasBMI()) {
365  if (Subtarget.is64Bit()) {
368  }
369  }
370 
371  if (Subtarget.hasLZCNT()) {
372  // When promoting the i8 variants, force them to i32 for a shorter
373  // encoding.
376  } else {
383  if (Subtarget.is64Bit()) {
386  }
387  }
388 
389  // Special handling for half-precision floating point conversions.
390  // If we don't have F16C support, then lower half float conversions
391  // into library calls.
392  if (Subtarget.useSoftFloat() || !Subtarget.hasF16C()) {
395  }
396 
397  // There's never any support for operations beyond MVT::f32.
402 
409 
410  if (Subtarget.hasPOPCNT()) {
412  } else {
416  if (Subtarget.is64Bit())
418  }
419 
421 
422  if (!Subtarget.hasMOVBE())
424 
425  // These should be promoted to a larger select which is supported.
427  // X86 wants to expand cmov itself.
428  for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
431  }
432  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
433  if (VT == MVT::i64 && !Subtarget.is64Bit())
434  continue;
437  }
438 
439  // Custom action for SELECT MMX and expand action for SELECT_CC MMX
442 
444  // NOTE: EH_SJLJ_SETJMP/_LONGJMP are not recommended, since
445  // LLVM/Clang supports zero-cost DWARF and SEH exception handling.
450  setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
451 
452  // Darwin ABI issue.
453  for (auto VT : { MVT::i32, MVT::i64 }) {
454  if (VT == MVT::i64 && !Subtarget.is64Bit())
455  continue;
462  }
463 
464  // 64-bit shl, sra, srl (iff 32-bit x86)
465  for (auto VT : { MVT::i32, MVT::i64 }) {
466  if (VT == MVT::i64 && !Subtarget.is64Bit())
467  continue;
471  }
472 
473  if (Subtarget.hasSSEPrefetch() || Subtarget.has3DNow())
475 
477 
478  // Expand certain atomics
479  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
487  }
488 
489  if (Subtarget.hasCmpxchg16b()) {
491  }
492 
493  // FIXME - use subtarget debug flags
494  if (!Subtarget.isTargetDarwin() && !Subtarget.isTargetELF() &&
495  !Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64() &&
498  }
499 
502 
505 
508 
509  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
512  bool Is64Bit = Subtarget.is64Bit();
514  setOperationAction(ISD::VACOPY, MVT::Other, Is64Bit ? Custom : Expand);
515 
518 
520 
521  // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
524 
525  if (!Subtarget.useSoftFloat() && X86ScalarSSEf64) {
526  // f32 and f64 use SSE.
527  // Set up the FP register classes.
528  addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
529  : &X86::FR32RegClass);
530  addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
531  : &X86::FR64RegClass);
532 
533  for (auto VT : { MVT::f32, MVT::f64 }) {
534  // Use ANDPD to simulate FABS.
536 
537  // Use XORP to simulate FNEG.
539 
540  // Use ANDPD and ORPD to simulate FCOPYSIGN.
542 
543  // These might be better off as horizontal vector ops.
546 
547  // We don't support sin/cos/fmod
548  setOperationAction(ISD::FSIN , VT, Expand);
549  setOperationAction(ISD::FCOS , VT, Expand);
550  setOperationAction(ISD::FSINCOS, VT, Expand);
551  }
552 
553  // Lower this to MOVMSK plus an AND.
556 
557  } else if (!useSoftFloat() && X86ScalarSSEf32 && (UseX87 || Is64Bit)) {
558  // Use SSE for f32, x87 for f64.
559  // Set up the FP register classes.
560  addRegisterClass(MVT::f32, &X86::FR32RegClass);
561  if (UseX87)
562  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
563 
564  // Use ANDPS to simulate FABS.
566 
567  // Use XORP to simulate FNEG.
569 
570  if (UseX87)
572 
573  // Use ANDPS and ORPS to simulate FCOPYSIGN.
574  if (UseX87)
577 
578  // We don't support sin/cos/fmod
582 
583  if (UseX87) {
584  // Always expand sin/cos functions even though x87 has an instruction.
588  }
589  } else if (UseX87) {
590  // f32 and f64 in x87.
591  // Set up the FP register classes.
592  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
593  addRegisterClass(MVT::f32, &X86::RFP32RegClass);
594 
595  for (auto VT : { MVT::f32, MVT::f64 }) {
596  setOperationAction(ISD::UNDEF, VT, Expand);
597  setOperationAction(ISD::FCOPYSIGN, VT, Expand);
598 
599  // Always expand sin/cos functions even though x87 has an instruction.
600  setOperationAction(ISD::FSIN , VT, Expand);
601  setOperationAction(ISD::FCOS , VT, Expand);
602  setOperationAction(ISD::FSINCOS, VT, Expand);
603  }
604  }
605 
606  // Expand FP32 immediates into loads from the stack, save special cases.
607  if (isTypeLegal(MVT::f32)) {
608  if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
609  addLegalFPImmediate(APFloat(+0.0f)); // FLD0
610  addLegalFPImmediate(APFloat(+1.0f)); // FLD1
611  addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
612  addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
613  } else // SSE immediates.
614  addLegalFPImmediate(APFloat(+0.0f)); // xorps
615  }
616  // Expand FP64 immediates into loads from the stack, save special cases.
617  if (isTypeLegal(MVT::f64)) {
618  if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) {
619  addLegalFPImmediate(APFloat(+0.0)); // FLD0
620  addLegalFPImmediate(APFloat(+1.0)); // FLD1
621  addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
622  addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
623  } else // SSE immediates.
624  addLegalFPImmediate(APFloat(+0.0)); // xorpd
625  }
626 
627  // We don't support FMA.
630 
631  // Long double always uses X87, except f128 in MMX.
632  if (UseX87) {
633  if (Subtarget.is64Bit() && Subtarget.hasMMX()) {
634  addRegisterClass(MVT::f128, Subtarget.hasVLX() ? &X86::VR128XRegClass
635  : &X86::VR128RegClass);
640  }
641 
642  addRegisterClass(MVT::f80, &X86::RFP80RegClass);
645  {
647  addLegalFPImmediate(TmpFlt); // FLD0
648  TmpFlt.changeSign();
649  addLegalFPImmediate(TmpFlt); // FLD0/FCHS
650 
651  bool ignored;
652  APFloat TmpFlt2(+1.0);
654  &ignored);
655  addLegalFPImmediate(TmpFlt2); // FLD1
656  TmpFlt2.changeSign();
657  addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
658  }
659 
660  // Always expand sin/cos functions even though x87 has an instruction.
664 
671  }
672 
673  // Always use a library call for pow.
677 
685 
686  // Some FP actions are always expanded for vector types.
687  for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32,
689  setOperationAction(ISD::FSIN, VT, Expand);
690  setOperationAction(ISD::FSINCOS, VT, Expand);
691  setOperationAction(ISD::FCOS, VT, Expand);
692  setOperationAction(ISD::FREM, VT, Expand);
693  setOperationAction(ISD::FCOPYSIGN, VT, Expand);
694  setOperationAction(ISD::FPOW, VT, Expand);
695  setOperationAction(ISD::FLOG, VT, Expand);
696  setOperationAction(ISD::FLOG2, VT, Expand);
697  setOperationAction(ISD::FLOG10, VT, Expand);
698  setOperationAction(ISD::FEXP, VT, Expand);
699  setOperationAction(ISD::FEXP2, VT, Expand);
700  }
701 
702  // First set operation action for all vector types to either promote
703  // (for widening) or expand (for scalarization). Then we will selectively
704  // turn on ones that can be effectively codegen'd.
705  for (MVT VT : MVT::vector_valuetypes()) {
706  setOperationAction(ISD::SDIV, VT, Expand);
707  setOperationAction(ISD::UDIV, VT, Expand);
708  setOperationAction(ISD::SREM, VT, Expand);
709  setOperationAction(ISD::UREM, VT, Expand);
714  setOperationAction(ISD::FMA, VT, Expand);
715  setOperationAction(ISD::FFLOOR, VT, Expand);
716  setOperationAction(ISD::FCEIL, VT, Expand);
717  setOperationAction(ISD::FTRUNC, VT, Expand);
718  setOperationAction(ISD::FRINT, VT, Expand);
719  setOperationAction(ISD::FNEARBYINT, VT, Expand);
720  setOperationAction(ISD::SMUL_LOHI, VT, Expand);
721  setOperationAction(ISD::MULHS, VT, Expand);
722  setOperationAction(ISD::UMUL_LOHI, VT, Expand);
723  setOperationAction(ISD::MULHU, VT, Expand);
724  setOperationAction(ISD::SDIVREM, VT, Expand);
725  setOperationAction(ISD::UDIVREM, VT, Expand);
726  setOperationAction(ISD::CTPOP, VT, Expand);
727  setOperationAction(ISD::CTTZ, VT, Expand);
728  setOperationAction(ISD::CTLZ, VT, Expand);
729  setOperationAction(ISD::ROTL, VT, Expand);
730  setOperationAction(ISD::ROTR, VT, Expand);
731  setOperationAction(ISD::BSWAP, VT, Expand);
732  setOperationAction(ISD::SETCC, VT, Expand);
733  setOperationAction(ISD::FP_TO_UINT, VT, Expand);
734  setOperationAction(ISD::FP_TO_SINT, VT, Expand);
735  setOperationAction(ISD::UINT_TO_FP, VT, Expand);
736  setOperationAction(ISD::SINT_TO_FP, VT, Expand);
738  setOperationAction(ISD::TRUNCATE, VT, Expand);
741  setOperationAction(ISD::ANY_EXTEND, VT, Expand);
742  setOperationAction(ISD::SELECT_CC, VT, Expand);
743  for (MVT InnerVT : MVT::vector_valuetypes()) {
744  setTruncStoreAction(InnerVT, VT, Expand);
745 
746  setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
747  setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
748 
749  // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
750  // types, we have to deal with them whether we ask for Expansion or not.
751  // Setting Expand causes its own optimisation problems though, so leave
752  // them legal.
753  if (VT.getVectorElementType() == MVT::i1)
754  setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
755 
756  // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
757  // split/scalarized right now.
758  if (VT.getVectorElementType() == MVT::f16)
759  setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
760  }
761  }
762 
763  // FIXME: In order to prevent SSE instructions being expanded to MMX ones
764  // with -msoft-float, disable use of MMX as well.
765  if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {
766  addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
767  // No operations on x86mmx supported, everything uses intrinsics.
768  }
769 
770  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) {
771  addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
772  : &X86::VR128RegClass);
773 
783  }
784 
785  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
786  addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
787  : &X86::VR128RegClass);
788 
789  // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
790  // registers cannot be used even for integer operations.
791  addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
792  : &X86::VR128RegClass);
793  addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
794  : &X86::VR128RegClass);
795  addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
796  : &X86::VR128RegClass);
797  addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
798  : &X86::VR128RegClass);
799 
800  for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
806  }
807 
814 
828 
829  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
831  setOperationAction(ISD::SMIN, VT, VT == MVT::v8i16 ? Legal : Custom);
832  setOperationAction(ISD::UMAX, VT, VT == MVT::v16i8 ? Legal : Custom);
833  setOperationAction(ISD::UMIN, VT, VT == MVT::v16i8 ? Legal : Custom);
834  }
835 
844 
846  // Use widening instead of promotion.
847  for (auto VT : { MVT::v8i8, MVT::v4i8, MVT::v2i8,
848  MVT::v4i16, MVT::v2i16 }) {
853  }
854  }
855 
859 
860  // Provide custom widening for v2f32 setcc. This is really for VLX when
861  // setcc result type returns v2i1/v4i1 vector for v2f32/v4f32 leading to
862  // type legalization changing the result type to v4i1 during widening.
863  // It works fine for SSE2 and is probably faster so no need to qualify with
864  // VLX support.
866 
867  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
871 
872  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
873  // setcc all the way to isel and prefer SETGT in some isel patterns.
876  }
877 
878  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
884  }
885 
886  // We support custom legalizing of sext and anyext loads for specific
887  // memory vector types which we can load as a scalar (or sequence of
888  // scalars) and extend in-register to a legal 128-bit vector type. For sext
889  // loads these must work with a single scalar load.
890  for (MVT VT : MVT::integer_vector_valuetypes()) {
897  }
898 
899  for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
903 
904  if (VT == MVT::v2i64 && !Subtarget.is64Bit())
905  continue;
906 
909  }
910 
911  // Custom lower v2i64 and v2f64 selects.
917 
921 
922  // Custom legalize these to avoid over promotion or custom promotion.
933 
934  // By marking FP_TO_SINT v8i16 as Custom, will trick type legalization into
935  // promoting v8i8 FP_TO_UINT into FP_TO_SINT. When the v8i16 FP_TO_SINT is
936  // split again based on the input type, this will cause an AssertSExt i16 to
937  // be emitted instead of an AssertZExt. This will allow packssdw followed by
938  // packuswb to be used to truncate to v8i8. This is necessary since packusdw
939  // isn't available until sse4.1.
941 
944 
946 
947  // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
949 
952 
953  for (MVT VT : MVT::fp_vector_valuetypes())
955 
956  // We want to legalize this to an f64 load rather than an i64 load on
957  // 64-bit targets and two 32-bit loads on a 32-bit target. Similar for
958  // store.
967 
971  if (!Subtarget.hasAVX512())
973 
977 
980 
987  } else {
989  }
990 
991  // In the customized shift lowering, the legal v4i32/v2i64 cases
992  // in AVX2 will be recognized.
993  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
997  }
998 
1001 
1002  // With AVX512, expanding (and promoting the shifts) is better.
1003  if (!Subtarget.hasAVX512())
1005  }
1006 
1007  if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
1016 
1017  // These might be better off as horizontal vector ops.
1022  }
1023 
1024  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) {
1025  for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
1026  setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
1027  setOperationAction(ISD::FCEIL, RoundedTy, Legal);
1028  setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
1029  setOperationAction(ISD::FRINT, RoundedTy, Legal);
1031  }
1032 
1041 
1042  // FIXME: Do we need to handle scalar-to-vector here?
1044 
1045  // We directly match byte blends in the backend as they match the VSELECT
1046  // condition form.
1048 
1049  // SSE41 brings specific instructions for doing vector sign extend even in
1050  // cases where we don't have SRA.
1051  for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1054  }
1055 
1057  // Avoid narrow result types when widening. The legal types are listed
1058  // in the next loop.
1059  for (MVT VT : MVT::integer_vector_valuetypes()) {
1063  }
1064  }
1065 
1066  // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
1067  for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1076  }
1077 
1078  // i8 vectors are custom because the source register and source
1079  // source memory operand types are not the same width.
1081  }
1082 
1083  if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
1084  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1087 
1088  // XOP can efficiently perform BITREVERSE with VPPERM.
1089  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
1091 
1092  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1095  }
1096 
1097  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX()) {
1098  bool HasInt256 = Subtarget.hasInt256();
1099 
1100  addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass
1101  : &X86::VR256RegClass);
1102  addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass
1103  : &X86::VR256RegClass);
1104  addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1105  : &X86::VR256RegClass);
1106  addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1107  : &X86::VR256RegClass);
1108  addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1109  : &X86::VR256RegClass);
1110  addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1111  : &X86::VR256RegClass);
1112 
1113  for (auto VT : { MVT::v8f32, MVT::v4f64 }) {
1122  }
1123 
1124  // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1125  // even though v8i16 is a legal type.
1129 
1132 
1133  if (!Subtarget.hasAVX512())
1135 
1136  for (MVT VT : MVT::fp_vector_valuetypes())
1138 
1139  // In the customized shift lowering, the legal v8i32/v4i64 cases
1140  // in AVX2 will be recognized.
1141  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1145  }
1146 
1148  // These types need custom splitting if their input is a 128-bit vector.
1153  }
1154 
1157 
1158  // With BWI, expanding (and promoting the shifts) is the better.
1159  if (!Subtarget.hasBWI())
1161 
1168 
1169  for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1173  }
1174 
1179 
1180  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1184 
1185  // TODO - remove this once 256-bit X86ISD::ANDNP correctly split.
1186  setOperationAction(ISD::CTTZ, VT, HasInt256 ? Expand : Custom);
1187 
1188  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1189  // setcc all the way to isel and prefer SETGT in some isel patterns.
1190  setCondCodeAction(ISD::SETLT, VT, Custom);
1191  setCondCodeAction(ISD::SETLE, VT, Custom);
1192  }
1193 
1194  if (Subtarget.hasAnyFMA()) {
1195  for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1198  }
1199 
1200  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1201  setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1202  setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1203  }
1204 
1207  setOperationAction(ISD::MUL, MVT::v16i16, HasInt256 ? Legal : Custom);
1209 
1212  setOperationAction(ISD::MULHU, MVT::v16i16, HasInt256 ? Legal : Custom);
1213  setOperationAction(ISD::MULHS, MVT::v16i16, HasInt256 ? Legal : Custom);
1216 
1222 
1223  setOperationAction(ISD::UADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1224  setOperationAction(ISD::SADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1225  setOperationAction(ISD::USUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1226  setOperationAction(ISD::SSUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1227  setOperationAction(ISD::UADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1228  setOperationAction(ISD::SADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1229  setOperationAction(ISD::USUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1230  setOperationAction(ISD::SSUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1231 
1232  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1233  setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom);
1234  setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1235  setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1236  setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1237  setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom);
1238  }
1239 
1240  for (auto VT : {MVT::v16i16, MVT::v8i32, MVT::v4i64}) {
1243  }
1244 
1245  if (HasInt256) {
1246  // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1247  // when we have a 256bit-wide blend with immediate.
1249 
1250  // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1251  for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1258  }
1259  }
1260 
1261  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1265  }
1266 
1267  // Extract subvector is special because the value type
1268  // (result) is 128-bit but the source is 256-bit wide.
1269  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1270  MVT::v4f32, MVT::v2f64 }) {
1272  }
1273 
1274  // Custom lower several nodes for 256-bit types.
1276  MVT::v8f32, MVT::v4f64 }) {
1279  setOperationAction(ISD::VSELECT, VT, Custom);
1285  }
1286 
1287  if (HasInt256)
1289 
1290  if (HasInt256) {
1291  // Custom legalize 2x32 to get a little better code.
1294 
1295  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1297  setOperationAction(ISD::MGATHER, VT, Custom);
1298  }
1299  }
1300 
1301  // This block controls legalization of the mask vector sizes that are
1302  // available with AVX512. 512-bit vectors are in a separate block controlled
1303  // by useAVX512Regs.
1304  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1305  addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1306  addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1307  addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1308  addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1309  addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1310 
1314 
1321 
1322  // There is no byte sized k-register load or store without AVX512DQ.
1323  if (!Subtarget.hasDQI()) {
1328 
1333  }
1334 
1335  // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1336  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1340  }
1341 
1342  for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1353 
1358  setOperationAction(ISD::VSELECT, VT, Expand);
1359  }
1360 
1368  for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
1370  }
1371 
1372  // This block controls legalization for 512-bit operations with 32/64 bit
1373  // elements. 512-bits can be disabled based on prefer-vector-width and
1374  // required-vector-width function attributes.
1375  if (!Subtarget.useSoftFloat() && Subtarget.useAVX512Regs()) {
1376  addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1377  addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1378  addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1379  addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1380 
1381  for (MVT VT : MVT::fp_vector_valuetypes())
1383 
1384  for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1390  }
1391 
1392  for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
1397  }
1398 
1409 
1415 
1416  if (!Subtarget.hasVLX()) {
1417  // With 512-bit vectors and no VLX, we prefer to widen MLOAD/MSTORE
1418  // to 512-bit rather than use the AVX2 instructions so that we can use
1419  // k-masks.
1420  for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1424  }
1425  }
1426 
1435 
1437  // Need to custom widen this if we don't have AVX512BW.
1441  }
1442 
1443  for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
1449  }
1450 
1451  // Without BWI we need to use custom lowering to handle MVT::v64i8 input.
1452  for (auto VT : {MVT::v16i32, MVT::v8i64, MVT::v64i8}) {
1455  }
1456 
1461 
1464 
1467 
1474 
1475  for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1488 
1489  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1490  // setcc all the way to isel and prefer SETGT in some isel patterns.
1493  }
1494 
1495  if (Subtarget.hasDQI()) {
1500 
1502  }
1503 
1504  if (Subtarget.hasCDI()) {
1505  // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1506  for (auto VT : { MVT::v16i32, MVT::v8i64} ) {
1508  }
1509  } // Subtarget.hasCDI()
1510 
1511  if (Subtarget.hasVPOPCNTDQ()) {
1512  for (auto VT : { MVT::v16i32, MVT::v8i64 })
1514  }
1515 
1516  // Extract subvector is special because the value type
1517  // (result) is 256-bit but the source is 512-bit wide.
1518  // 128-bit was made Legal under AVX1.
1519  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1522 
1523  for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
1535  }
1536  // Need to custom split v32i16/v64i8 bitcasts.
1537  if (!Subtarget.hasBWI()) {
1540  }
1541 
1542  if (Subtarget.hasVBMI2()) {
1543  for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1546  }
1547  }
1548  }// has AVX-512
1549 
1550  // This block controls legalization for operations that don't have
1551  // pre-AVX512 equivalents. Without VLX we use 512-bit operations for
1552  // narrower widths.
1553  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1554  // These operations are handled on non-VLX by artificially widening in
1555  // isel patterns.
1556  // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1557 
1563 
1564  for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1570  }
1571 
1572  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1575  }
1576 
1577  // Custom legalize 2x32 to get a little better code.
1580 
1581  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1584 
1585  if (Subtarget.hasDQI()) {
1586  for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1591 
1593  }
1594  }
1595 
1596  if (Subtarget.hasCDI()) {
1597  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1599  }
1600  } // Subtarget.hasCDI()
1601 
1602  if (Subtarget.hasVPOPCNTDQ()) {
1603  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 })
1605  }
1606  }
1607 
1608  // This block control legalization of v32i1/v64i1 which are available with
1609  // AVX512BW. 512-bit v32i16 and v64i8 vector legalization is controlled with
1610  // useBWIRegs.
1611  if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1612  addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1613  addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1614 
1615  for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
1619  setOperationAction(ISD::VSELECT, VT, Expand);
1624 
1632  }
1633 
1638  for (auto VT : { MVT::v16i1, MVT::v32i1 })
1640 
1641  // Extends from v32i1 masks to 256-bit vectors.
1645  }
1646 
1647  // This block controls legalization for v32i16 and v64i8. 512-bits can be
1648  // disabled based on prefer-vector-width and required-vector-width function
1649  // attributes.
1650  if (!Subtarget.useSoftFloat() && Subtarget.useBWIRegs()) {
1651  addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1652  addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1653 
1654  // Extends from v64i1 masks to 512-bit vectors.
1658 
1682 
1685 
1687 
1688  for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1708 
1709  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1710  // setcc all the way to isel and prefer SETGT in some isel patterns.
1713  }
1714 
1715  for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1717  }
1718 
1719  if (Subtarget.hasBITALG()) {
1720  for (auto VT : { MVT::v64i8, MVT::v32i16 })
1722  }
1723 
1724  if (Subtarget.hasVBMI2()) {
1727  }
1728  }
1729 
1730  if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1731  for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
1732  setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1733  setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom);
1734  }
1735 
1736  // These operations are handled on non-VLX by artificially widening in
1737  // isel patterns.
1738  // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1739 
1740  if (Subtarget.hasBITALG()) {
1741  for (auto VT : { MVT::v16i8, MVT::v32i8, MVT::v8i16, MVT::v16i16 })
1743  }
1744  }
1745 
1746  if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {
1752 
1758 
1759  if (Subtarget.hasDQI()) {
1760  // Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
1761  // v2f32 UINT_TO_FP is already custom under SSE2.
1764  "Unexpected operation action!");
1765  // v2i64 FP_TO_S/UINT(v2f32) custom conversion.
1768  }
1769 
1770  if (Subtarget.hasBWI()) {
1773  }
1774 
1775  if (Subtarget.hasVBMI2()) {
1776  // TODO: Make these legal even without VLX?
1777  for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64,
1781  }
1782  }
1783  }
1784 
1785  // We want to custom lower some of our intrinsics.
1789  if (!Subtarget.is64Bit()) {
1792  }
1793 
1794  // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1795  // handle type legalization for these operations here.
1796  //
1797  // FIXME: We really should do custom legalization for addition and
1798  // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1799  // than generic legalization for 64-bit multiplication-with-overflow, though.
1800  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1801  if (VT == MVT::i64 && !Subtarget.is64Bit())
1802  continue;
1803  // Add/Sub/Mul with overflow operations are custom lowered.
1810 
1811  // Support carry in as value rather than glue.
1815  }
1816 
1817  if (!Subtarget.is64Bit()) {
1818  // These libcalls are not available in 32-bit.
1819  setLibcallName(RTLIB::SHL_I128, nullptr);
1820  setLibcallName(RTLIB::SRL_I128, nullptr);
1821  setLibcallName(RTLIB::SRA_I128, nullptr);
1822  setLibcallName(RTLIB::MUL_I128, nullptr);
1823  }
1824 
1825  // Combine sin / cos into _sincos_stret if it is available.
1826  if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1827  getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1830  }
1831 
1832  if (Subtarget.isTargetWin64()) {
1839  }
1840 
1841  // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
1842  // is. We should promote the value to 64-bits to solve this.
1843  // This is what the CRT headers do - `fmodf` is an inline header
1844  // function casting to f64 and calling `fmod`.
1845  if (Subtarget.is32Bit() && (Subtarget.isTargetKnownWindowsMSVC() ||
1846  Subtarget.isTargetWindowsItanium()))
1847  for (ISD::NodeType Op :
1852 
1853  // We have target-specific dag combine patterns for the following nodes:
1891 
1893 
1894  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1896  MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1898  MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1900 
1901  // TODO: These control memcmp expansion in CGP and could be raised higher, but
1902  // that needs to benchmarked and balanced with the potential use of vector
1903  // load/store types (PR33329, PR33914).
1904  MaxLoadsPerMemcmp = 2;
1906 
1907  // Set loop alignment to 2^ExperimentalPrefLoopAlignment bytes (default: 2^4).
1909 
1910  // An out-of-order CPU can speculatively execute past a predictable branch,
1911  // but a conditional move could be stalled by an expensive earlier operation.
1912  PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
1913  EnableExtLdPromotion = true;
1914  setPrefFunctionAlignment(4); // 2^4 bytes.
1915 
1917 }
1918 
1919 // This has so far only been implemented for 64-bit MachO.
1921  return Subtarget.isTargetMachO() && Subtarget.is64Bit();
1922 }
1923 
1925  // Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
1926  return Subtarget.getTargetTriple().isOSMSVCRT();
1927 }
1928 
1930  const SDLoc &DL) const {
1931  EVT PtrTy = getPointerTy(DAG.getDataLayout());
1932  unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
1933  MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);
1934  return SDValue(Node, 0);
1935 }
1936 
1939  if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
1940  return TypeSplitVector;
1941 
1943  VT.getVectorNumElements() != 1 &&
1944  VT.getVectorElementType() != MVT::i1)
1945  return TypeWidenVector;
1946 
1948 }
1949 
1951  CallingConv::ID CC,
1952  EVT VT) const {
1953  if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
1954  return MVT::v32i8;
1955  return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
1956 }
1957 
1959  CallingConv::ID CC,
1960  EVT VT) const {
1961  if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
1962  return 1;
1963  return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
1964 }
1965 
1968  EVT VT) const {
1969  if (!VT.isVector())
1970  return MVT::i8;
1971 
1972  if (Subtarget.hasAVX512()) {
1973  const unsigned NumElts = VT.getVectorNumElements();
1974 
1975  // Figure out what this type will be legalized to.
1976  EVT LegalVT = VT;
1977  while (getTypeAction(Context, LegalVT) != TypeLegal)
1978  LegalVT = getTypeToTransformTo(Context, LegalVT);
1979 
1980  // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
1981  if (LegalVT.getSimpleVT().is512BitVector())
1982  return EVT::getVectorVT(Context, MVT::i1, NumElts);
1983 
1984  if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
1985  // If we legalized to less than a 512-bit vector, then we will use a vXi1
1986  // compare for vXi32/vXi64 for sure. If we have BWI we will also support
1987  // vXi16/vXi8.
1988  MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
1989  if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
1990  return EVT::getVectorVT(Context, MVT::i1, NumElts);
1991  }
1992  }
1993 
1995 }
1996 
1997 /// Helper for getByValTypeAlignment to determine
1998 /// the desired ByVal argument alignment.
1999 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
2000  if (MaxAlign == 16)
2001  return;
2002  if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
2003  if (VTy->getBitWidth() == 128)
2004  MaxAlign = 16;
2005  } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
2006  unsigned EltAlign = 0;
2007  getMaxByValAlign(ATy->getElementType(), EltAlign);
2008  if (EltAlign > MaxAlign)
2009  MaxAlign = EltAlign;
2010  } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
2011  for (auto *EltTy : STy->elements()) {
2012  unsigned EltAlign = 0;
2013  getMaxByValAlign(EltTy, EltAlign);
2014  if (EltAlign > MaxAlign)
2015  MaxAlign = EltAlign;
2016  if (MaxAlign == 16)
2017  break;
2018  }
2019  }
2020 }
2021 
2022 /// Return the desired alignment for ByVal aggregate
2023 /// function arguments in the caller parameter area. For X86, aggregates
2024 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
2025 /// are at 4-byte boundaries.
2027  const DataLayout &DL) const {
2028  if (Subtarget.is64Bit()) {
2029  // Max of 8 and alignment of type.
2030  unsigned TyAlign = DL.getABITypeAlignment(Ty);
2031  if (TyAlign > 8)
2032  return TyAlign;
2033  return 8;
2034  }
2035 
2036  unsigned Align = 4;
2037  if (Subtarget.hasSSE1())
2038  getMaxByValAlign(Ty, Align);
2039  return Align;
2040 }
2041 
2042 /// Returns the target specific optimal type for load
2043 /// and store operations as a result of memset, memcpy, and memmove
2044 /// lowering. If DstAlign is zero that means it's safe to destination
2045 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
2046 /// means there isn't a need to check it against alignment requirement,
2047 /// probably because the source does not need to be loaded. If 'IsMemset' is
2048 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
2049 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
2050 /// source is constant so it does not need to be loaded.
2051 /// It returns EVT::Other if the type should be determined using generic
2052 /// target-independent logic.
2053 EVT
2055  unsigned DstAlign, unsigned SrcAlign,
2056  bool IsMemset, bool ZeroMemset,
2057  bool MemcpyStrSrc,
2058  MachineFunction &MF) const {
2059  const Function &F = MF.getFunction();
2060  if (!F.hasFnAttribute(Attribute::NoImplicitFloat)) {
2061  if (Size >= 16 &&
2062  (!Subtarget.isUnalignedMem16Slow() ||
2063  ((DstAlign == 0 || DstAlign >= 16) &&
2064  (SrcAlign == 0 || SrcAlign >= 16)))) {
2065  // FIXME: Check if unaligned 32-byte accesses are slow.
2066  if (Size >= 32 && Subtarget.hasAVX()) {
2067  // Although this isn't a well-supported type for AVX1, we'll let
2068  // legalization and shuffle lowering produce the optimal codegen. If we
2069  // choose an optimal type with a vector element larger than a byte,
2070  // getMemsetStores() may create an intermediate splat (using an integer
2071  // multiply) before we splat as a vector.
2072  return MVT::v32i8;
2073  }
2074  if (Subtarget.hasSSE2())
2075  return MVT::v16i8;
2076  // TODO: Can SSE1 handle a byte vector?
2077  // If we have SSE1 registers we should be able to use them.
2078  if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()))
2079  return MVT::v4f32;
2080  } else if ((!IsMemset || ZeroMemset) && !MemcpyStrSrc && Size >= 8 &&
2081  !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
2082  // Do not use f64 to lower memcpy if source is string constant. It's
2083  // better to use i32 to avoid the loads.
2084  // Also, do not use f64 to lower memset unless this is a memset of zeros.
2085  // The gymnastics of splatting a byte value into an XMM register and then
2086  // only using 8-byte stores (because this is a CPU with slow unaligned
2087  // 16-byte accesses) makes that a loser.
2088  return MVT::f64;
2089  }
2090  }
2091  // This is a compromise. If we reach here, unaligned accesses may be slow on
2092  // this target. However, creating smaller, aligned accesses could be even
2093  // slower and would certainly be a lot more code.
2094  if (Subtarget.is64Bit() && Size >= 8)
2095  return MVT::i64;
2096  return MVT::i32;
2097 }
2098 
2100  if (VT == MVT::f32)
2101  return X86ScalarSSEf32;
2102  else if (VT == MVT::f64)
2103  return X86ScalarSSEf64;
2104  return true;
2105 }
2106 
2107 bool
2109  unsigned,
2110  unsigned,
2111  bool *Fast) const {
2112  if (Fast) {
2113  switch (VT.getSizeInBits()) {
2114  default:
2115  // 8-byte and under are always assumed to be fast.
2116  *Fast = true;
2117  break;
2118  case 128:
2119  *Fast = !Subtarget.isUnalignedMem16Slow();
2120  break;
2121  case 256:
2122  *Fast = !Subtarget.isUnalignedMem32Slow();
2123  break;
2124  // TODO: What about AVX-512 (512-bit) accesses?
2125  }
2126  }
2127  // Misaligned accesses of any size are always allowed.
2128  return true;
2129 }
2130 
2131 /// Return the entry encoding for a jump table in the
2132 /// current function. The returned value is a member of the
2133 /// MachineJumpTableInfo::JTEntryKind enum.
2135  // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2136  // symbol.
2137  if (isPositionIndependent() && Subtarget.isPICStyleGOT())
2139 
2140  // Otherwise, use the normal jump table encoding heuristics.
2142 }
2143 
2145  return Subtarget.useSoftFloat();
2146 }
2147 
2149  ArgListTy &Args) const {
2150 
2151  // Only relabel X86-32 for C / Stdcall CCs.
2152  if (Subtarget.is64Bit())
2153  return;
2154  if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
2155  return;
2156  unsigned ParamRegs = 0;
2157  if (auto *M = MF->getFunction().getParent())
2158  ParamRegs = M->getNumberRegisterParameters();
2159 
2160  // Mark the first N int arguments as having reg
2161  for (unsigned Idx = 0; Idx < Args.size(); Idx++) {
2162  Type *T = Args[Idx].Ty;
2163  if (T->isIntOrPtrTy())
2164  if (MF->getDataLayout().getTypeAllocSize(T) <= 8) {
2165  unsigned numRegs = 1;
2166  if (MF->getDataLayout().getTypeAllocSize(T) > 4)
2167  numRegs = 2;
2168  if (ParamRegs < numRegs)
2169  return;
2170  ParamRegs -= numRegs;
2171  Args[Idx].IsInReg = true;
2172  }
2173  }
2174 }
2175 
2176 const MCExpr *
2178  const MachineBasicBlock *MBB,
2179  unsigned uid,MCContext &Ctx) const{
2180  assert(isPositionIndependent() && Subtarget.isPICStyleGOT());
2181  // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2182  // entries.
2183  return MCSymbolRefExpr::create(MBB->getSymbol(),
2185 }
2186 
2187 /// Returns relocation base for the given PIC jumptable.
2189  SelectionDAG &DAG) const {
2190  if (!Subtarget.is64Bit())
2191  // This doesn't have SDLoc associated with it, but is not really the
2192  // same as a Register.
2193  return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2194  getPointerTy(DAG.getDataLayout()));
2195  return Table;
2196 }
2197 
2198 /// This returns the relocation base for the given PIC jumptable,
2199 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2202  MCContext &Ctx) const {
2203  // X86-64 uses RIP relative addressing based on the jump table label.
2204  if (Subtarget.isPICStyleRIPRel())
2205  return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2206 
2207  // Otherwise, the reference is relative to the PIC base.
2208  return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2209 }
2210 
2211 std::pair<const TargetRegisterClass *, uint8_t>
2213  MVT VT) const {
2214  const TargetRegisterClass *RRC = nullptr;
2215  uint8_t Cost = 1;
2216  switch (VT.SimpleTy) {
2217  default:
2219  case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2220  RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2221  break;
2222  case MVT::x86mmx:
2223  RRC = &X86::VR64RegClass;
2224  break;
2225  case MVT::f32: case MVT::f64:
2226  case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2227  case MVT::v4f32: case MVT::v2f64:
2228  case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
2229  case MVT::v8f32: case MVT::v4f64:
2230  case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
2231  case MVT::v16f32: case MVT::v8f64:
2232  RRC = &X86::VR128XRegClass;
2233  break;
2234  }
2235  return std::make_pair(RRC, Cost);
2236 }
2237 
2238 unsigned X86TargetLowering::getAddressSpace() const {
2239  if (Subtarget.is64Bit())
2240  return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? 256 : 257;
2241  return 256;
2242 }
2243 
2244 static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
2245  return TargetTriple.isOSGlibc() || TargetTriple.isOSFuchsia() ||
2246  (TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));
2247 }
2248 
2250  unsigned Offset, unsigned AddressSpace) {
2253  Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2254 }
2255 
2257  // glibc, bionic, and Fuchsia have a special slot for the stack guard in
2258  // tcbhead_t; use it instead of the usual global variable (see
2259  // sysdeps/{i386,x86_64}/nptl/tls.h)
2260  if (hasStackGuardSlotTLS(Subtarget.getTargetTriple())) {
2261  if (Subtarget.isTargetFuchsia()) {
2262  // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
2263  return SegmentOffset(IRB, 0x10, getAddressSpace());
2264  } else {
2265  // %fs:0x28, unless we're using a Kernel code model, in which case
2266  // it's %gs:0x28. gs:0x14 on i386.
2267  unsigned Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
2268  return SegmentOffset(IRB, Offset, getAddressSpace());
2269  }
2270  }
2271 
2272  return TargetLowering::getIRStackGuard(IRB);
2273 }
2274 
2276  // MSVC CRT provides functionalities for stack protection.
2277  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2279  // MSVC CRT has a global variable holding security cookie.
2280  M.getOrInsertGlobal("__security_cookie",
2282 
2283  // MSVC CRT has a function to validate security cookie.
2284  auto *SecurityCheckCookie = cast<Function>(
2285  M.getOrInsertFunction("__security_check_cookie",
2288  SecurityCheckCookie->setCallingConv(CallingConv::X86_FastCall);
2289  SecurityCheckCookie->addAttribute(1, Attribute::AttrKind::InReg);
2290  return;
2291  }
2292  // glibc, bionic, and Fuchsia have a special slot for the stack guard.
2293  if (hasStackGuardSlotTLS(Subtarget.getTargetTriple()))
2294  return;
2296 }
2297 
2299  // MSVC CRT has a global variable holding security cookie.
2300  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2302  return M.getGlobalVariable("__security_cookie");
2303  }
2305 }
2306 
2308  // MSVC CRT has a function to validate security cookie.
2309  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2311  return M.getFunction("__security_check_cookie");
2312  }
2314 }
2315 
2317  if (Subtarget.getTargetTriple().isOSContiki())
2318  return getDefaultSafeStackPointerLocation(IRB, false);
2319 
2320  // Android provides a fixed TLS slot for the SafeStack pointer. See the
2321  // definition of TLS_SLOT_SAFESTACK in
2322  // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2323  if (Subtarget.isTargetAndroid()) {
2324  // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2325  // %gs:0x24 on i386
2326  unsigned Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
2327  return SegmentOffset(IRB, Offset, getAddressSpace());
2328  }
2329 
2330  // Fuchsia is similar.
2331  if (Subtarget.isTargetFuchsia()) {
2332  // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
2333  return SegmentOffset(IRB, 0x18, getAddressSpace());
2334  }
2335 
2337 }
2338 
2340  unsigned DestAS) const {
2341  assert(SrcAS != DestAS && "Expected different address spaces!");
2342 
2343  return SrcAS < 256 && DestAS < 256;
2344 }
2345 
2346 //===----------------------------------------------------------------------===//
2347 // Return Value Calling Convention Implementation
2348 //===----------------------------------------------------------------------===//
2349 
2350 #include "X86GenCallingConv.inc"
2351 
2352 bool X86TargetLowering::CanLowerReturn(
2353  CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2354  const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2356  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2357  return CCInfo.CheckReturn(Outs, RetCC_X86);
2358 }
2359 
2360 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2361  static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2362  return ScratchRegs;
2363 }
2364 
2365 /// Lowers masks values (v*i1) to the local register values
2366 /// \returns DAG node after lowering to register type
2367 static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
2368  const SDLoc &Dl, SelectionDAG &DAG) {
2369  EVT ValVT = ValArg.getValueType();
2370 
2371  if (ValVT == MVT::v1i1)
2372  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg,
2373  DAG.getIntPtrConstant(0, Dl));
2374 
2375  if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
2376  (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
2377  // Two stage lowering might be required
2378  // bitcast: v8i1 -> i8 / v16i1 -> i16
2379  // anyextend: i8 -> i32 / i16 -> i32
2380  EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
2381  SDValue ValToCopy = DAG.getBitcast(TempValLoc, ValArg);
2382  if (ValLoc == MVT::i32)
2383  ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy);
2384  return ValToCopy;
2385  }
2386 
2387  if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
2388  (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
2389  // One stage lowering is required
2390  // bitcast: v32i1 -> i32 / v64i1 -> i64
2391  return DAG.getBitcast(ValLoc, ValArg);
2392  }
2393 
2394  return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg);
2395 }
2396 
2397 /// Breaks v64i1 value into two registers and adds the new node to the DAG
2399  const SDLoc &Dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg,
2400  SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA,
2401  CCValAssign &NextVA, const X86Subtarget &Subtarget) {
2402  assert(Subtarget.hasBWI() && "Expected AVX512BW target!");
2403  assert(Subtarget.is32Bit() && "Expecting 32 bit target");
2404  assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value");
2405  assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2406  "The value should reside in two registers");
2407 
2408  // Before splitting the value we cast it to i64
2409  Arg = DAG.getBitcast(MVT::i64, Arg);
2410 
2411  // Splitting the value into two i32 types
2412  SDValue Lo, Hi;
2413  Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2414  DAG.getConstant(0, Dl, MVT::i32));
2415  Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2416  DAG.getConstant(1, Dl, MVT::i32));
2417 
2418  // Attach the two i32 types into corresponding registers
2419  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
2420  RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi));
2421 }
2422 
2423 SDValue
2424 X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2425  bool isVarArg,
2426  const SmallVectorImpl<ISD::OutputArg> &Outs,
2427  const SmallVectorImpl<SDValue> &OutVals,
2428  const SDLoc &dl, SelectionDAG &DAG) const {
2429  MachineFunction &MF = DAG.getMachineFunction();
2431 
2432  // In some cases we need to disable registers from the default CSR list.
2433  // For example, when they are used for argument passing.
2434  bool ShouldDisableCalleeSavedRegister =
2435  CallConv == CallingConv::X86_RegCall ||
2436  MF.getFunction().hasFnAttribute("no_caller_saved_registers");
2437 
2438  if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2439  report_fatal_error("X86 interrupts may not return any value");
2440 
2442  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2443  CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2444 
2445  SDValue Flag;
2446  SmallVector<SDValue, 6> RetOps;
2447  RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2448  // Operand #1 = Bytes To Pop
2449  RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2450  MVT::i32));
2451 
2452  // Copy the result values into the output registers.
2453  for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
2454  ++I, ++OutsIndex) {
2455  CCValAssign &VA = RVLocs[I];
2456  assert(VA.isRegLoc() && "Can only return in registers!");
2457 
2458  // Add the register to the CalleeSaveDisableRegs list.
2459  if (ShouldDisableCalleeSavedRegister)
2461 
2462  SDValue ValToCopy = OutVals[OutsIndex];
2463  EVT ValVT = ValToCopy.getValueType();
2464 
2465  // Promote values to the appropriate types.
2466  if (VA.getLocInfo() == CCValAssign::SExt)
2467  ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2468  else if (VA.getLocInfo() == CCValAssign::ZExt)
2469  ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2470  else if (VA.getLocInfo() == CCValAssign::AExt) {
2471  if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2472  ValToCopy = lowerMasksToReg(ValToCopy, VA.getLocVT(), dl, DAG);
2473  else
2474  ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2475  }
2476  else if (VA.getLocInfo() == CCValAssign::BCvt)
2477  ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2478 
2480  "Unexpected FP-extend for return value.");
2481 
2482  // If this is x86-64, and we disabled SSE, we can't return FP values,
2483  // or SSE or MMX vectors.
2484  if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2485  VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2486  (Subtarget.is64Bit() && !Subtarget.hasSSE1())) {
2487  errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2488  VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2489  } else if (ValVT == MVT::f64 &&
2490  (Subtarget.is64Bit() && !Subtarget.hasSSE2())) {
2491  // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2492  // llvm-gcc has never done it right and no one has noticed, so this
2493  // should be OK for now.
2494  errorUnsupported(DAG, dl, "SSE2 register return with SSE2 disabled");
2495  VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2496  }
2497 
2498  // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2499  // the RET instruction and handled by the FP Stackifier.
2500  if (VA.getLocReg() == X86::FP0 ||
2501  VA.getLocReg() == X86::FP1) {
2502  // If this is a copy from an xmm register to ST(0), use an FPExtend to
2503  // change the value to the FP stack register class.
2504  if (isScalarFPTypeInSSEReg(VA.getValVT()))
2505  ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2506  RetOps.push_back(ValToCopy);
2507  // Don't emit a copytoreg.
2508  continue;
2509  }
2510 
2511  // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2512  // which is returned in RAX / RDX.
2513  if (Subtarget.is64Bit()) {
2514  if (ValVT == MVT::x86mmx) {
2515  if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2516  ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2517  ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2518  ValToCopy);
2519  // If we don't have SSE2 available, convert to v4f32 so the generated
2520  // register is legal.
2521  if (!Subtarget.hasSSE2())
2522  ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2523  }
2524  }
2525  }
2526 
2528 
2529  if (VA.needsCustom()) {
2530  assert(VA.getValVT() == MVT::v64i1 &&
2531  "Currently the only custom case is when we split v64i1 to 2 regs");
2532 
2533  Passv64i1ArgInRegs(dl, DAG, Chain, ValToCopy, RegsToPass, VA, RVLocs[++I],
2534  Subtarget);
2535 
2536  assert(2 == RegsToPass.size() &&
2537  "Expecting two registers after Pass64BitArgInRegs");
2538 
2539  // Add the second register to the CalleeSaveDisableRegs list.
2540  if (ShouldDisableCalleeSavedRegister)
2541  MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg());
2542  } else {
2543  RegsToPass.push_back(std::make_pair(VA.getLocReg(), ValToCopy));
2544  }
2545 
2546  // Add nodes to the DAG and add the values into the RetOps list
2547  for (auto &Reg : RegsToPass) {
2548  Chain = DAG.getCopyToReg(Chain, dl, Reg.first, Reg.second, Flag);
2549  Flag = Chain.getValue(1);
2550  RetOps.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
2551  }
2552  }
2553 
2554  // Swift calling convention does not require we copy the sret argument
2555  // into %rax/%eax for the return, and SRetReturnReg is not set for Swift.
2556 
2557  // All x86 ABIs require that for returning structs by value we copy
2558  // the sret argument into %rax/%eax (depending on ABI) for the return.
2559  // We saved the argument into a virtual register in the entry block,
2560  // so now we copy the value out and into %rax/%eax.
2561  //
2562  // Checking Function.hasStructRetAttr() here is insufficient because the IR
2563  // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2564  // false, then an sret argument may be implicitly inserted in the SelDAG. In
2565  // either case FuncInfo->setSRetReturnReg() will have been called.
2566  if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2567  // When we have both sret and another return value, we should use the
2568  // original Chain stored in RetOps[0], instead of the current Chain updated
2569  // in the above loop. If we only have sret, RetOps[0] equals to Chain.
2570 
2571  // For the case of sret and another return value, we have
2572  // Chain_0 at the function entry
2573  // Chain_1 = getCopyToReg(Chain_0) in the above loop
2574  // If we use Chain_1 in getCopyFromReg, we will have
2575  // Val = getCopyFromReg(Chain_1)
2576  // Chain_2 = getCopyToReg(Chain_1, Val) from below
2577 
2578  // getCopyToReg(Chain_0) will be glued together with
2579  // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
2580  // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
2581  // Data dependency from Unit B to Unit A due to usage of Val in
2582  // getCopyToReg(Chain_1, Val)
2583  // Chain dependency from Unit A to Unit B
2584 
2585  // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
2586  SDValue Val = DAG.getCopyFromReg(RetOps[0], dl, SRetReg,
2587  getPointerTy(MF.getDataLayout()));
2588 
2589  unsigned RetValReg
2590  = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ?
2591  X86::RAX : X86::EAX;
2592  Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2593  Flag = Chain.getValue(1);
2594 
2595  // RAX/EAX now acts like a return value.
2596  RetOps.push_back(
2597  DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2598 
2599  // Add the returned register to the CalleeSaveDisableRegs list.
2600  if (ShouldDisableCalleeSavedRegister)
2601  MF.getRegInfo().disableCalleeSavedRegister(RetValReg);
2602  }
2603 
2604  const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
2605  const MCPhysReg *I =
2607  if (I) {
2608  for (; *I; ++I) {
2609  if (X86::GR64RegClass.contains(*I))
2610  RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2611  else
2612  llvm_unreachable("Unexpected register class in CSRsViaCopy!");
2613  }
2614  }
2615 
2616  RetOps[0] = Chain; // Update chain.
2617 
2618  // Add the flag if we have it.
2619  if (Flag.getNode())
2620  RetOps.push_back(Flag);
2621 
2623  if (CallConv == CallingConv::X86_INTR)
2624  opcode = X86ISD::IRET;
2625  return DAG.getNode(opcode, dl, MVT::Other, RetOps);
2626 }
2627 
2628 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2629  if (N->getNumValues() != 1 || !N->hasNUsesOfValue(1, 0))
2630  return false;
2631 
2632  SDValue TCChain = Chain;
2633  SDNode *Copy = *N->use_begin();
2634  if (Copy->getOpcode() == ISD::CopyToReg) {
2635  // If the copy has a glue operand, we conservatively assume it isn't safe to
2636  // perform a tail call.
2637  if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2638  return false;
2639  TCChain = Copy->getOperand(0);
2640  } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2641  return false;
2642 
2643  bool HasRet = false;
2644  for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2645  UI != UE; ++UI) {
2646  if (UI->getOpcode() != X86ISD::RET_FLAG)
2647  return false;
2648  // If we are returning more than one value, we can definitely
2649  // not make a tail call see PR19530
2650  if (UI->getNumOperands() > 4)
2651  return false;
2652  if (UI->getNumOperands() == 4 &&
2653  UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2654  return false;
2655  HasRet = true;
2656  }
2657 
2658  if (!HasRet)
2659  return false;
2660 
2661  Chain = TCChain;
2662  return true;
2663 }
2664 
2665 EVT X86TargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
2666  ISD::NodeType ExtendKind) const {
2667  MVT ReturnMVT = MVT::i32;
2668 
2669  bool Darwin = Subtarget.getTargetTriple().isOSDarwin();
2670  if (VT == MVT::i1 || (!Darwin && (VT == MVT::i8 || VT == MVT::i16))) {
2671  // The ABI does not require i1, i8 or i16 to be extended.
2672  //
2673  // On Darwin, there is code in the wild relying on Clang's old behaviour of
2674  // always extending i8/i16 return values, so keep doing that for now.
2675  // (PR26665).
2676  ReturnMVT = MVT::i8;
2677  }
2678 
2679  EVT MinVT = getRegisterType(Context, ReturnMVT);
2680  return VT.bitsLT(MinVT) ? MinVT : VT;
2681 }
2682 
2683 /// Reads two 32 bit registers and creates a 64 bit mask value.
2684 /// \param VA The current 32 bit value that need to be assigned.
2685 /// \param NextVA The next 32 bit value that need to be assigned.
2686 /// \param Root The parent DAG node.
2687 /// \param [in,out] InFlag Represents SDvalue in the parent DAG node for
2688 /// glue purposes. In the case the DAG is already using
2689 /// physical register instead of virtual, we should glue
2690 /// our new SDValue to InFlag SDvalue.
2691 /// \return a new SDvalue of size 64bit.
2693  SDValue &Root, SelectionDAG &DAG,
2694  const SDLoc &Dl, const X86Subtarget &Subtarget,
2695  SDValue *InFlag = nullptr) {
2696  assert((Subtarget.hasBWI()) && "Expected AVX512BW target!");
2697  assert(Subtarget.is32Bit() && "Expecting 32 bit target");
2698  assert(VA.getValVT() == MVT::v64i1 &&
2699  "Expecting first location of 64 bit width type");
2700  assert(NextVA.getValVT() == VA.getValVT() &&
2701  "The locations should have the same type");
2702  assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2703  "The values should reside in two registers");
2704 
2705  SDValue Lo, Hi;
2706  unsigned Reg;
2707  SDValue ArgValueLo, ArgValueHi;
2708 
2709  MachineFunction &MF = DAG.getMachineFunction();
2710  const TargetRegisterClass *RC = &X86::GR32RegClass;
2711 
2712  // Read a 32 bit value from the registers.
2713  if (nullptr == InFlag) {
2714  // When no physical register is present,
2715  // create an intermediate virtual register.
2716  Reg = MF.addLiveIn(VA.getLocReg(), RC);
2717  ArgValueLo = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
2718  Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2719  ArgValueHi = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
2720  } else {
2721  // When a physical register is available read the value from it and glue
2722  // the reads together.
2723  ArgValueLo =
2724  DAG.getCopyFromReg(Root, Dl, VA.getLocReg(), MVT::i32, *InFlag);
2725  *InFlag = ArgValueLo.getValue(2);
2726  ArgValueHi =
2727  DAG.getCopyFromReg(Root, Dl, NextVA.getLocReg(), MVT::i32, *InFlag);
2728  *InFlag = ArgValueHi.getValue(2);
2729  }
2730 
2731  // Convert the i32 type into v32i1 type.
2732  Lo = DAG.getBitcast(MVT::v32i1, ArgValueLo);
2733 
2734  // Convert the i32 type into v32i1 type.
2735  Hi = DAG.getBitcast(MVT::v32i1, ArgValueHi);
2736 
2737  // Concatenate the two values together.
2738  return DAG.getNode(ISD::CONCAT_VECTORS, Dl, MVT::v64i1, Lo, Hi);
2739 }
2740 
2741 /// The function will lower a register of various sizes (8/16/32/64)
2742 /// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
2743 /// \returns a DAG node contains the operand after lowering to mask type.
2744 static SDValue lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT,
2745  const EVT &ValLoc, const SDLoc &Dl,
2746  SelectionDAG &DAG) {
2747  SDValue ValReturned = ValArg;
2748 
2749  if (ValVT == MVT::v1i1)
2750  return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned);
2751 
2752  if (ValVT == MVT::v64i1) {
2753  // In 32 bit machine, this case is handled by getv64i1Argument
2754  assert(ValLoc == MVT::i64 && "Expecting only i64 locations");
2755  // In 64 bit machine, There is no need to truncate the value only bitcast
2756  } else {
2757  MVT maskLen;
2758  switch (ValVT.getSimpleVT().SimpleTy) {
2759  case MVT::v8i1:
2760  maskLen = MVT::i8;
2761  break;
2762  case MVT::v16i1:
2763  maskLen = MVT::i16;
2764  break;
2765  case MVT::v32i1:
2766  maskLen = MVT::i32;
2767  break;
2768  default:
2769  llvm_unreachable("Expecting a vector of i1 types");
2770  }
2771 
2772  ValReturned = DAG.getNode(ISD::TRUNCATE, Dl, maskLen, ValReturned);
2773  }
2774  return DAG.getBitcast(ValVT, ValReturned);
2775 }
2776 
2777 /// Lower the result values of a call into the
2778 /// appropriate copies out of appropriate physical registers.
2779 ///
2780 SDValue X86TargetLowering::LowerCallResult(
2781  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2782  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2783  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
2784  uint32_t *RegMask) const {
2785 
2786  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2787  // Assign locations to each value returned by this call.
2789  bool Is64Bit = Subtarget.is64Bit();
2790  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2791  *DAG.getContext());
2792  CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2793 
2794  // Copy all of the result registers out of their specified physreg.
2795  for (unsigned I = 0, InsIndex = 0, E = RVLocs.size(); I != E;
2796  ++I, ++InsIndex) {
2797  CCValAssign &VA = RVLocs[I];
2798  EVT CopyVT = VA.getLocVT();
2799 
2800  // In some calling conventions we need to remove the used registers
2801  // from the register mask.
2802  if (RegMask) {
2803  for (MCSubRegIterator SubRegs(VA.getLocReg(), TRI, /*IncludeSelf=*/true);
2804  SubRegs.isValid(); ++SubRegs)
2805  RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
2806  }
2807 
2808  // If this is x86-64, and we disabled SSE, we can't return FP values
2809  if ((CopyVT == MVT::f32 || CopyVT == MVT::f64 || CopyVT == MVT::f128) &&
2810  ((Is64Bit || Ins[InsIndex].Flags.isInReg()) && !Subtarget.hasSSE1())) {
2811  errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2812  VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2813  }
2814 
2815  // If we prefer to use the value in xmm registers, copy it out as f80 and
2816  // use a truncate to move it from fp stack reg to xmm reg.
2817  bool RoundAfterCopy = false;
2818  if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2820  if (!Subtarget.hasX87())
2821  report_fatal_error("X87 register return with X87 disabled");
2822  CopyVT = MVT::f80;
2823  RoundAfterCopy = (CopyVT != VA.getLocVT());
2824  }
2825 
2826  SDValue Val;
2827  if (VA.needsCustom()) {
2828  assert(VA.getValVT() == MVT::v64i1 &&
2829  "Currently the only custom case is when we split v64i1 to 2 regs");
2830  Val =
2831  getv64i1Argument(VA, RVLocs[++I], Chain, DAG, dl, Subtarget, &InFlag);
2832  } else {
2833  Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), CopyVT, InFlag)
2834  .getValue(1);
2835  Val = Chain.getValue(0);
2836  InFlag = Chain.getValue(2);
2837  }
2838 
2839  if (RoundAfterCopy)
2840  Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2841  // This truncation won't change the value.
2842  DAG.getIntPtrConstant(1, dl));
2843 
2844  if (VA.isExtInLoc() && (VA.getValVT().getScalarType() == MVT::i1)) {
2845  if (VA.getValVT().isVector() &&
2846  ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
2847  (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
2848  // promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
2849  Val = lowerRegToMasks(Val, VA.getValVT(), VA.getLocVT(), dl, DAG);
2850  } else
2851  Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2852  }
2853 
2854  InVals.push_back(Val);
2855  }
2856 
2857  return Chain;
2858 }
2859 
2860 //===----------------------------------------------------------------------===//
2861 // C & StdCall & Fast Calling Convention implementation
2862 //===----------------------------------------------------------------------===//
2863 // StdCall calling convention seems to be standard for many Windows' API
2864 // routines and around. It differs from C calling convention just a little:
2865 // callee should clean up the stack, not caller. Symbols should be also
2866 // decorated in some fancy way :) It doesn't support any vector arguments.
2867 // For info on fast calling convention see Fast Calling Convention (tail call)
2868 // implementation LowerX86_32FastCCCallTo.
2869 
2870 /// CallIsStructReturn - Determines whether a call uses struct return
2871 /// semantics.
2876 };
2877 static StructReturnType
2879  if (Outs.empty())
2880  return NotStructReturn;
2881 
2882  const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2883  if (!Flags.isSRet())
2884  return NotStructReturn;
2885  if (Flags.isInReg() || IsMCU)
2886  return RegStructReturn;
2887  return StackStructReturn;
2888 }
2889 
2890 /// Determines whether a function uses struct return semantics.
2891 static StructReturnType
2893  if (Ins.empty())
2894  return NotStructReturn;
2895 
2896  const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2897  if (!Flags.isSRet())
2898  return NotStructReturn;
2899  if (Flags.isInReg() || IsMCU)
2900  return RegStructReturn;
2901  return StackStructReturn;
2902 }
2903 
2904 /// Make a copy of an aggregate at address specified by "Src" to address
2905 /// "Dst" with size and alignment information specified by the specific
2906 /// parameter attribute. The copy will be passed as a byval function parameter.
2908  SDValue Chain, ISD::ArgFlagsTy Flags,
2909  SelectionDAG &DAG, const SDLoc &dl) {
2910  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2911 
2912  return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2913  /*isVolatile*/false, /*AlwaysInline=*/true,
2914  /*isTailCall*/false,
2916 }
2917 
2918 /// Return true if the calling convention is one that we can guarantee TCO for.
2920  return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2922  CC == CallingConv::HHVM);
2923 }
2924 
2925 /// Return true if we might ever do TCO for calls with this calling convention.
2927  switch (CC) {
2928  // C calling conventions:
2929  case CallingConv::C:
2930  case CallingConv::Win64:
2932  // Callee pop conventions:
2937  return true;
2938  default:
2939  return canGuaranteeTCO(CC);
2940  }
2941 }
2942 
2943 /// Return true if the function is being made into a tailcall target by
2944 /// changing its ABI.
2945 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2946  return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2947 }
2948 
2949 bool X86TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2950  auto Attr =
2951  CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2952  if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2953  return false;
2954 
2955  ImmutableCallSite CS(CI);
2956  CallingConv::ID CalleeCC = CS.getCallingConv();
2957  if (!mayTailCallThisCC(CalleeCC))
2958  return false;
2959 
2960  return true;
2961 }
2962 
2963 SDValue
2964 X86TargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
2965  const SmallVectorImpl<ISD::InputArg> &Ins,
2966  const SDLoc &dl, SelectionDAG &DAG,
2967  const CCValAssign &VA,
2968  MachineFrameInfo &MFI, unsigned i) const {
2969  // Create the nodes corresponding to a load from this parameter slot.
2970  ISD::ArgFlagsTy Flags = Ins[i].Flags;
2971  bool AlwaysUseMutable = shouldGuaranteeTCO(
2972  CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2973  bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2974  EVT ValVT;
2975  MVT PtrVT = getPointerTy(DAG.getDataLayout());
2976 
2977  // If value is passed by pointer we have address passed instead of the value
2978  // itself. No need to extend if the mask value and location share the same
2979  // absolute size.
2980  bool ExtendedInMem =
2981  VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1 &&
2982  VA.getValVT().getSizeInBits() != VA.getLocVT().getSizeInBits();
2983 
2984  if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2985  ValVT = VA.getLocVT();
2986  else
2987  ValVT = VA.getValVT();
2988 
2989  // Calculate SP offset of interrupt parameter, re-arrange the slot normally
2990  // taken by a return address.
2991  int Offset = 0;
2992  if (CallConv == CallingConv::X86_INTR) {
2993  // X86 interrupts may take one or two arguments.
2994  // On the stack there will be no return address as in regular call.
2995  // Offset of last argument need to be set to -4/-8 bytes.
2996  // Where offset of the first argument out of two, should be set to 0 bytes.
2997  Offset = (Subtarget.is64Bit() ? 8 : 4) * ((i + 1) % Ins.size() - 1);
2998  if (Subtarget.is64Bit() && Ins.size() == 2) {
2999  // The stack pointer needs to be realigned for 64 bit handlers with error
3000  // code, so the argument offset changes by 8 bytes.
3001  Offset += 8;
3002  }
3003  }
3004 
3005  // FIXME: For now, all byval parameter objects are marked mutable. This can be
3006  // changed with more analysis.
3007  // In case of tail call optimization mark all arguments mutable. Since they
3008  // could be overwritten by lowering of arguments in case of a tail call.
3009  if (Flags.isByVal()) {
3010  unsigned Bytes = Flags.getByValSize();
3011  if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
3012 
3013  // FIXME: For now, all byval parameter objects are marked as aliasing. This
3014  // can be improved with deeper analysis.
3015  int FI = MFI.CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable,
3016  /*isAliased=*/true);
3017  // Adjust SP offset of interrupt parameter.
3018  if (CallConv == CallingConv::X86_INTR) {
3019  MFI.setObjectOffset(FI, Offset);
3020  }
3021  return DAG.getFrameIndex(FI, PtrVT);
3022  }
3023 
3024  // This is an argument in memory. We might be able to perform copy elision.
3025  if (Flags.isCopyElisionCandidate()) {
3026  EVT ArgVT = Ins[i].ArgVT;
3027  SDValue PartAddr;
3028  if (Ins[i].PartOffset == 0) {
3029  // If this is a one-part value or the first part of a multi-part value,
3030  // create a stack object for the entire argument value type and return a
3031  // load from our portion of it. This assumes that if the first part of an
3032  // argument is in memory, the rest will also be in memory.
3033  int FI = MFI.CreateFixedObject(ArgVT.getStoreSize(), VA.getLocMemOffset(),
3034  /*Immutable=*/false);
3035  PartAddr = DAG.getFrameIndex(FI, PtrVT);
3036  return DAG.getLoad(
3037  ValVT, dl, Chain, PartAddr,
3039  } else {
3040  // This is not the first piece of an argument in memory. See if there is
3041  // already a fixed stack object including this offset. If so, assume it
3042  // was created by the PartOffset == 0 branch above and create a load from
3043  // the appropriate offset into it.
3044  int64_t PartBegin = VA.getLocMemOffset();
3045  int64_t PartEnd = PartBegin + ValVT.getSizeInBits() / 8;
3046  int FI = MFI.getObjectIndexBegin();
3047  for (; MFI.isFixedObjectIndex(FI); ++FI) {
3048  int64_t ObjBegin = MFI.getObjectOffset(FI);
3049  int64_t ObjEnd = ObjBegin + MFI.getObjectSize(FI);
3050  if (ObjBegin <= PartBegin && PartEnd <= ObjEnd)
3051  break;
3052  }
3053  if (MFI.isFixedObjectIndex(FI)) {
3054  SDValue Addr =
3055  DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getFrameIndex(FI, PtrVT),
3056  DAG.getIntPtrConstant(Ins[i].PartOffset, dl));
3057  return DAG.getLoad(
3058  ValVT, dl, Chain, Addr,
3060  Ins[i].PartOffset));
3061  }
3062  }
3063  }
3064 
3065  int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
3066  VA.getLocMemOffset(), isImmutable);
3067 
3068  // Set SExt or ZExt flag.
3069  if (VA.getLocInfo() == CCValAssign::ZExt) {
3070  MFI.setObjectZExt(FI, true);
3071  } else if (VA.getLocInfo() == CCValAssign::SExt) {
3072  MFI.setObjectSExt(FI, true);
3073  }
3074 
3075  // Adjust SP offset of interrupt parameter.
3076  if (CallConv == CallingConv::X86_INTR) {
3077  MFI.setObjectOffset(FI, Offset);
3078  }
3079 
3080  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3081  SDValue Val = DAG.getLoad(
3082  ValVT, dl, Chain, FIN,
3084  return ExtendedInMem
3085  ? (VA.getValVT().isVector()
3086  ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val)
3087  : DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val))
3088  : Val;
3089 }
3090 
3091 // FIXME: Get this from tablegen.
3093  const X86Subtarget &Subtarget) {
3094  assert(Subtarget.is64Bit());
3095 
3096  if (Subtarget.isCallingConvWin64(CallConv)) {
3097  static const MCPhysReg GPR64ArgRegsWin64[] = {
3098  X86::RCX, X86::RDX, X86::R8, X86::R9
3099  };
3100  return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
3101  }
3102 
3103  static const MCPhysReg GPR64ArgRegs64Bit[] = {
3104  X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
3105  };
3106  return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
3107 }
3108 
3109 // FIXME: Get this from tablegen.
3111  CallingConv::ID CallConv,
3112  const X86Subtarget &Subtarget) {
3113  assert(Subtarget.is64Bit());
3114  if (Subtarget.isCallingConvWin64(CallConv)) {
3115  // The XMM registers which might contain var arg parameters are shadowed
3116  // in their paired GPR. So we only need to save the GPR to their home
3117  // slots.
3118  // TODO: __vectorcall will change this.
3119  return None;
3120  }
3121 
3122  const Function &F = MF.getFunction();
3123  bool NoImplicitFloatOps = F.hasFnAttribute(Attribute::NoImplicitFloat);
3124  bool isSoftFloat = Subtarget.useSoftFloat();
3125  assert(!(isSoftFloat && NoImplicitFloatOps) &&
3126  "SSE register cannot be used when SSE is disabled!");
3127  if (isSoftFloat || NoImplicitFloatOps || !Subtarget.hasSSE1())
3128  // Kernel mode asks for SSE to be disabled, so there are no XMM argument
3129  // registers.
3130  return None;
3131 
3132  static const MCPhysReg XMMArgRegs64Bit[] = {
3133  X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3134  X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3135  };
3136  return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
3137 }
3138 
3139 #ifndef NDEBUG
3141  return std::is_sorted(ArgLocs.begin(), ArgLocs.end(),
3142  [](const CCValAssign &A, const CCValAssign &B) -> bool {
3143  return A.getValNo() < B.getValNo();
3144  });
3145 }
3146 #endif
3147 
3148 SDValue X86TargetLowering::LowerFormalArguments(
3149  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3150  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3151  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3152  MachineFunction &MF = DAG.getMachineFunction();
3154  const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
3155 
3156  const Function &F = MF.getFunction();
3157  if (F.hasExternalLinkage() && Subtarget.isTargetCygMing() &&
3158  F.getName() == "main")
3159  FuncInfo->setForceFramePointer(true);
3160 
3161  MachineFrameInfo &MFI = MF.getFrameInfo();
3162  bool Is64Bit = Subtarget.is64Bit();
3163  bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
3164 
3165  assert(
3166  !(isVarArg && canGuaranteeTCO(CallConv)) &&
3167  "Var args not supported with calling conv' regcall, fastcc, ghc or hipe");
3168 
3169  if (CallConv == CallingConv::X86_INTR) {
3170  bool isLegal = Ins.size() == 1 ||
3171  (Ins.size() == 2 && ((Is64Bit && Ins[1].VT == MVT::i64) ||
3172  (!Is64Bit && Ins[1].VT == MVT::i32)));
3173  if (!isLegal)
3174  report_fatal_error("X86 interrupts may take one or two arguments");
3175  }
3176 
3177  // Assign locations to all of the incoming arguments.
3179  CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3180 
3181  // Allocate shadow area for Win64.
3182  if (IsWin64)
3183  CCInfo.AllocateStack(32, 8);
3184 
3185  CCInfo.AnalyzeArguments(Ins, CC_X86);
3186 
3187  // In vectorcall calling convention a second pass is required for the HVA
3188  // types.
3189  if (CallingConv::X86_VectorCall == CallConv) {
3190  CCInfo.AnalyzeArgumentsSecondPass(Ins, CC_X86);
3191  }
3192 
3193  // The next loop assumes that the locations are in the same order of the
3194  // input arguments.
3195  assert(isSortedByValueNo(ArgLocs) &&
3196  "Argument Location list must be sorted before lowering");
3197 
3198  SDValue ArgValue;
3199  for (unsigned I = 0, InsIndex = 0, E = ArgLocs.size(); I != E;
3200  ++I, ++InsIndex) {
3201  assert(InsIndex < Ins.size() && "Invalid Ins index");
3202  CCValAssign &VA = ArgLocs[I];
3203 
3204  if (VA.isRegLoc()) {
3205  EVT RegVT = VA.getLocVT();
3206  if (VA.needsCustom()) {
3207  assert(
3208  VA.getValVT() == MVT::v64i1 &&
3209  "Currently the only custom case is when we split v64i1 to 2 regs");
3210 
3211  // v64i1 values, in regcall calling convention, that are
3212  // compiled to 32 bit arch, are split up into two registers.
3213  ArgValue =
3214  getv64i1Argument(VA, ArgLocs[++I], Chain, DAG, dl, Subtarget);
3215  } else {
3216  const TargetRegisterClass *RC;
3217  if (RegVT == MVT::i8)
3218  RC = &X86::GR8RegClass;
3219  else if (RegVT == MVT::i16)
3220  RC = &X86::GR16RegClass;
3221  else if (RegVT == MVT::i32)
3222  RC = &X86::GR32RegClass;
3223  else if (Is64Bit && RegVT == MVT::i64)
3224  RC = &X86::GR64RegClass;
3225  else if (RegVT == MVT::f32)
3226  RC = Subtarget.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
3227  else if (RegVT == MVT::f64)
3228  RC = Subtarget.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
3229  else if (RegVT == MVT::f80)
3230  RC = &X86::RFP80RegClass;
3231  else if (RegVT == MVT::f128)
3232  RC = &X86::VR128RegClass;
3233  else if (RegVT.is512BitVector())
3234  RC = &X86::VR512RegClass;
3235  else if (RegVT.is256BitVector())
3236  RC = Subtarget.hasVLX() ? &X86::VR256XRegClass : &X86::VR256RegClass;
3237  else if (RegVT.is128BitVector())
3238  RC = Subtarget.hasVLX() ? &X86::VR128XRegClass : &X86::VR128RegClass;
3239  else if (RegVT == MVT::x86mmx)
3240  RC = &X86::VR64RegClass;
3241  else if (RegVT == MVT::v1i1)
3242  RC = &X86::VK1RegClass;
3243  else if (RegVT == MVT::v8i1)
3244  RC = &X86::VK8RegClass;
3245  else if (RegVT == MVT::v16i1)
3246  RC = &X86::VK16RegClass;
3247  else if (RegVT == MVT::v32i1)
3248  RC = &X86::VK32RegClass;
3249  else if (RegVT == MVT::v64i1)
3250  RC = &X86::VK64RegClass;
3251  else
3252  llvm_unreachable("Unknown argument type!");
3253 
3254  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3255  ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3256  }
3257 
3258  // If this is an 8 or 16-bit value, it is really passed promoted to 32
3259  // bits. Insert an assert[sz]ext to capture this, then truncate to the
3260  // right size.
3261  if (VA.getLocInfo() == CCValAssign::SExt)
3262  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3263  DAG.getValueType(VA.getValVT()));
3264  else if (VA.getLocInfo() == CCValAssign::ZExt)
3265  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3266  DAG.getValueType(VA.getValVT()));
3267  else if (VA.getLocInfo() == CCValAssign::BCvt)
3268  ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
3269 
3270  if (VA.isExtInLoc()) {
3271  // Handle MMX values passed in XMM regs.
3272  if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
3273  ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
3274  else if (VA.getValVT().isVector() &&
3275  VA.getValVT().getScalarType() == MVT::i1 &&
3276  ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
3277  (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3278  // Promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
3279  ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG);
3280  } else
3281  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3282  }
3283  } else {
3284  assert(VA.isMemLoc());
3285  ArgValue =
3286  LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, InsIndex);
3287  }
3288 
3289  // If value is passed via pointer - do a load.
3290  if (VA.getLocInfo() == CCValAssign::Indirect && !Ins[I].Flags.isByVal())
3291  ArgValue =
3292  DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, MachinePointerInfo());
3293 
3294  InVals.push_back(ArgValue);
3295  }
3296 
3297  for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
3298  // Swift calling convention does not require we copy the sret argument
3299  // into %rax/%eax for the return. We don't set SRetReturnReg for Swift.
3300  if (CallConv == CallingConv::Swift)
3301  continue;
3302 
3303  // All x86 ABIs require that for returning structs by value we copy the
3304  // sret argument into %rax/%eax (depending on ABI) for the return. Save
3305  // the argument into a virtual register so that we can access it from the
3306  // return points.
3307  if (Ins[I].Flags.isSRet()) {
3308  unsigned Reg = FuncInfo->getSRetReturnReg();
3309  if (!Reg) {
3310  MVT PtrTy = getPointerTy(DAG.getDataLayout());
3311  Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
3312  FuncInfo->setSRetReturnReg(Reg);
3313  }
3314  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[I]);
3315  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3316  break;
3317  }
3318  }
3319 
3320  unsigned StackSize = CCInfo.getNextStackOffset();
3321  // Align stack specially for tail calls.
3322  if (shouldGuaranteeTCO(CallConv,
3324  StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
3325 
3326  // If the function takes variable number of arguments, make a frame index for
3327  // the start of the first vararg value... for expansion of llvm.va_start. We
3328  // can skip this if there are no va_start calls.
3329  if (MFI.hasVAStart() &&
3330  (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
3331  CallConv != CallingConv::X86_ThisCall))) {
3332  FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
3333  }
3334 
3335  // Figure out if XMM registers are in use.
3336  assert(!(Subtarget.useSoftFloat() &&
3337  F.hasFnAttribute(Attribute::NoImplicitFloat)) &&
3338  "SSE register cannot be used when SSE is disabled!");
3339 
3340  // 64-bit calling conventions support varargs and register parameters, so we
3341  // have to do extra work to spill them in the prologue.
3342  if (Is64Bit && isVarArg && MFI.hasVAStart()) {
3343  // Find the first unallocated argument registers.
3344  ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
3345  ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
3346  unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
3347  unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
3348  assert(!(NumXMMRegs && !Subtarget.hasSSE1()) &&
3349  "SSE register cannot be used when SSE is disabled!");
3350 
3351  // Gather all the live in physical registers.
3352  SmallVector<SDValue, 6> LiveGPRs;
3353  SmallVector<SDValue, 8> LiveXMMRegs;
3354  SDValue ALVal;
3355  for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
3356  unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
3357  LiveGPRs.push_back(
3358  DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
3359  }
3360  if (!ArgXMMs.empty()) {
3361  unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3362  ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
3363  for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
3364  unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
3365  LiveXMMRegs.push_back(
3366  DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
3367  }
3368  }
3369 
3370  if (IsWin64) {
3371  // Get to the caller-allocated home save location. Add 8 to account
3372  // for the return address.
3373  int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
3374  FuncInfo->setRegSaveFrameIndex(
3375  MFI.CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
3376  // Fixup to set vararg frame on shadow area (4 x i64).
3377  if (NumIntRegs < 4)
3378  FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
3379  } else {
3380  // For X86-64, if there are vararg parameters that are passed via
3381  // registers, then we must store them to their spots on the stack so
3382  // they may be loaded by dereferencing the result of va_next.
3383  FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
3384  FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
3386  ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
3387  }
3388 
3389  // Store the integer parameter registers.
3390  SmallVector<SDValue, 8> MemOps;
3391  SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
3392  getPointerTy(DAG.getDataLayout()));
3393  unsigned Offset = FuncInfo->getVarArgsGPOffset();
3394  for (SDValue Val : LiveGPRs) {
3395  SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3396  RSFIN, DAG.getIntPtrConstant(Offset, dl));
3397  SDValue Store =
3398  DAG.getStore(Val.getValue(1), dl, Val, FIN,
3400  DAG.getMachineFunction(),
3401  FuncInfo->getRegSaveFrameIndex(), Offset));
3402  MemOps.push_back(Store);
3403  Offset += 8;
3404  }
3405 
3406  if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
3407  // Now store the XMM (fp + vector) parameter registers.
3408  SmallVector<SDValue, 12> SaveXMMOps;
3409  SaveXMMOps.push_back(Chain);
3410  SaveXMMOps.push_back(ALVal);
3411  SaveXMMOps.push_back(DAG.getIntPtrConstant(
3412  FuncInfo->getRegSaveFrameIndex(), dl));
3413  SaveXMMOps.push_back(DAG.getIntPtrConstant(
3414  FuncInfo->getVarArgsFPOffset(), dl));
3415  SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
3416  LiveXMMRegs.end());
3418  MVT::Other, SaveXMMOps));
3419  }
3420 
3421  if (!MemOps.empty())
3422  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3423  }
3424 
3425  if (isVarArg && MFI.hasMustTailInVarArgFunc()) {
3426  // Find the largest legal vector type.
3427  MVT VecVT = MVT::Other;
3428  // FIXME: Only some x86_32 calling conventions support AVX512.
3429  if (Subtarget.hasAVX512() &&
3430  (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
3431  CallConv == CallingConv::Intel_OCL_BI)))
3432  VecVT = MVT::v16f32;
3433  else if (Subtarget.hasAVX())
3434  VecVT = MVT::v8f32;
3435  else if (Subtarget.hasSSE2())
3436  VecVT = MVT::v4f32;
3437 
3438  // We forward some GPRs and some vector types.
3439  SmallVector<MVT, 2> RegParmTypes;
3440  MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
3441  RegParmTypes.push_back(IntVT);
3442  if (VecVT != MVT::Other)
3443  RegParmTypes.push_back(VecVT);
3444 
3445  // Compute the set of forwarded registers. The rest are scratch.
3447  FuncInfo->getForwardedMustTailRegParms();
3448  CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
3449 
3450  // Conservatively forward AL on x86_64, since it might be used for varargs.
3451  if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
3452  unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3453  Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
3454  }
3455 
3456  // Copy all forwards from physical to virtual registers.
3457  for (ForwardedRegister &F : Forwards) {
3458  // FIXME: Can we use a less constrained schedule?
3459  SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3460  F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
3461  Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
3462  }
3463  }
3464 
3465  // Some CCs need callee pop.
3466  if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3468  FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
3469  } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
3470  // X86 interrupts must pop the error code (and the alignment padding) if
3471  // present.
3472  FuncInfo->setBytesToPopOnReturn(Is64Bit ? 16 : 4);
3473  } else {
3474  FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
3475  // If this is an sret function, the return should pop the hidden pointer.
3476  if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3477  !Subtarget.getTargetTriple().isOSMSVCRT() &&
3478  argsAreStructReturn(Ins, Subtarget.isTargetMCU()) == StackStructReturn)
3479  FuncInfo->setBytesToPopOnReturn(4);
3480  }
3481 
3482  if (!Is64Bit) {
3483  // RegSaveFrameIndex is X86-64 only.
3484  FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
3485  if (CallConv == CallingConv::X86_FastCall ||
3486  CallConv == CallingConv::X86_ThisCall)
3487  // fastcc functions can't have varargs.
3488  FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
3489  }
3490 
3491  FuncInfo->setArgumentStackSize(StackSize);
3492 
3493  if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
3495  if (Personality == EHPersonality::CoreCLR) {
3496  assert(Is64Bit);
3497  // TODO: Add a mechanism to frame lowering that will allow us to indicate
3498  // that we'd prefer this slot be allocated towards the bottom of the frame
3499  // (i.e. near the stack pointer after allocating the frame). Every
3500  // funclet needs a copy of this slot in its (mostly empty) frame, and the
3501  // offset from the bottom of this and each funclet's frame must be the
3502  // same, so the size of funclets' (mostly empty) frames is dictated by
3503  // how far this slot is from the bottom (since they allocate just enough
3504  // space to accommodate holding this slot at the correct offset).
3505  int PSPSymFI = MFI.CreateStackObject(8, 8, /*isSS=*/false);
3506  EHInfo->PSPSymFrameIdx = PSPSymFI;
3507  }
3508  }
3509 
3510  if (CallConv == CallingConv::X86_RegCall ||
3511  F.hasFnAttribute("no_caller_saved_registers")) {
3513  for (std::pair<unsigned, unsigned> Pair : MRI.liveins())
3514  MRI.disableCalleeSavedRegister(Pair.first);
3515  }
3516 
3517  return Chain;
3518 }
3519 
3520 SDValue X86TargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
3521  SDValue Arg, const SDLoc &dl,
3522  SelectionDAG &DAG,
3523  const CCValAssign &VA,
3524  ISD::ArgFlagsTy Flags) const {
3525  unsigned LocMemOffset = VA.getLocMemOffset();
3526  SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
3527  PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3528  StackPtr, PtrOff);
3529  if (Flags.isByVal())
3530  return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
3531 
3532  return DAG.getStore(
3533  Chain, dl, Arg, PtrOff,
3534  MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
3535 }
3536 
3537 /// Emit a load of return address if tail call
3538 /// optimization is performed and it is required.
3539 SDValue X86TargetLowering::EmitTailCallLoadRetAddr(
3540  SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall,
3541  bool Is64Bit, int FPDiff, const SDLoc &dl) const {
3542  // Adjust the Return address stack slot.
3543  EVT VT = getPointerTy(DAG.getDataLayout());
3544  OutRetAddr = getReturnAddressFrameIndex(DAG);
3545 
3546  // Load the "old" Return address.
3547  OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo());
3548  return SDValue(OutRetAddr.getNode(), 1);
3549 }
3550 
3551 /// Emit a store of the return address if tail call
3552 /// optimization is performed and it is required (FPDiff!=0).
3554  SDValue Chain, SDValue RetAddrFrIdx,
3555  EVT PtrVT, unsigned SlotSize,
3556  int FPDiff, const SDLoc &dl) {
3557  // Store the return address to the appropriate stack slot.
3558  if (!FPDiff) return Chain;
3559  // Calculate the new stack slot for the return address.
3560  int NewReturnAddrFI =
3561  MF.getFrameInfo().CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
3562  false);
3563  SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
3564  Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
3566  DAG.getMachineFunction(), NewReturnAddrFI));
3567  return Chain;
3568 }
3569 
3570 /// Returns a vector_shuffle mask for an movs{s|d}, movd
3571 /// operation of specified width.
3572 static SDValue getMOVL(SelectionDAG &DAG, const SDLoc &dl, MVT VT, SDValue V1,
3573  SDValue V2) {
3574  unsigned NumElems = VT.getVectorNumElements();
3576  Mask.push_back(NumElems);
3577  for (unsigned i = 1; i != NumElems; ++i)
3578  Mask.push_back(i);
3579  return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
3580 }
3581 
3582 SDValue
3583 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3584  SmallVectorImpl<SDValue> &InVals) const {
3585  SelectionDAG &DAG = CLI.DAG;
3586  SDLoc &dl = CLI.DL;