Go to the documentation of this file.
32 auto NamedMD =
M.getNamedMetadata(
"amdgpu.pal.metadata.msgpack");
33 if (NamedMD && NamedMD->getNumOperands()) {
37 auto MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0));
38 if (MDN && MDN->getNumOperands()) {
39 if (
auto MDS = dyn_cast<MDString>(MDN->getOperand(0)))
40 setFromMsgPackBlob(MDS->getString());
45 NamedMD =
M.getNamedMetadata(
"amdgpu.pal.metadata");
46 if (!NamedMD || !NamedMD->getNumOperands()) {
55 auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
58 for (
unsigned I = 0,
E = Tuple->getNumOperands() & -2;
I !=
E;
I += 2) {
59 auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(
I));
60 auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(
I + 1));
63 setRegister(
Key->getZExtValue(), Val->getZExtValue());
73 return setFromLegacyBlob(Blob);
74 return setFromMsgPackBlob(Blob);
78 bool AMDGPUPALMetadata::setFromLegacyBlob(
StringRef Blob) {
81 setRegister(Data[
I * 2], Data[
I * 2 + 1]);
86 bool AMDGPUPALMetadata::setFromMsgPackBlob(
StringRef Blob) {
88 return MsgPackDoc.readFromBlob(Blob,
false);
162 auto Regs = getRegisters();
163 auto It = Regs.find(MsgPackDoc.getNode(
Reg));
164 if (It == Regs.end())
178 if (
Reg >= 0x10000000)
181 auto &
N = getRegisters()[MsgPackDoc.getNode(
Reg)];
184 N =
N.getDocument()->getNode(Val);
192 getHwStage(CC)[
".entry_point"] = MsgPackDoc.getNode(
Name,
true);
205 setRegister(NumUsedVgprsKey, Val);
209 getHwStage(CC)[
".vgpr_count"] = MsgPackDoc.getNode(Val);
214 getHwStage(CC)[
".agpr_count"] = Val;
226 setRegister(NumUsedSgprsKey, Val);
230 getHwStage(CC)[
".sgpr_count"] = MsgPackDoc.getNode(Val);
241 getHwStage(CC)[
".scratch_memory_size"] = MsgPackDoc.getNode(Val);
248 Node[
".stack_frame_size_in_bytes"] = MsgPackDoc.getNode(Val);
255 Node[
".lds_size"] = MsgPackDoc.getNode(Val);
262 Node[
".vgpr_count"] = MsgPackDoc.getNode(Val);
269 Node[
".sgpr_count"] = MsgPackDoc.getNode(Val);
299 static const struct RegInfo {
325 {0x2c07,
"SPI_SHADER_PGM_RSRC3_PS"},
326 {0x2c46,
"SPI_SHADER_PGM_RSRC3_VS"},
327 {0x2c87,
"SPI_SHADER_PGM_RSRC3_GS"},
328 {0x2cc7,
"SPI_SHADER_PGM_RSRC3_ES"},
329 {0x2d07,
"SPI_SHADER_PGM_RSRC3_HS"},
330 {0x2d47,
"SPI_SHADER_PGM_RSRC3_LS"},
332 {0xa1c3,
"SPI_SHADER_POS_FORMAT"},
333 {0xa1b1,
"SPI_VS_OUT_CONFIG"},
334 {0xa207,
"PA_CL_VS_OUT_CNTL"},
335 {0xa204,
"PA_CL_CLIP_CNTL"},
336 {0xa206,
"PA_CL_VTE_CNTL"},
337 {0xa2f9,
"PA_SU_VTX_CNTL"},
338 {0xa293,
"PA_SC_MODE_CNTL_1"},
339 {0xa2a1,
"VGT_PRIMITIVEID_EN"},
340 {0x2c81,
"SPI_SHADER_PGM_RSRC4_GS"},
341 {0x2e18,
"COMPUTE_TMPRING_SIZE"},
342 {0xa1b5,
"SPI_INTERP_CONTROL_0"},
343 {0xa1ba,
"SPI_TMPRING_SIZE"},
344 {0xa1c4,
"SPI_SHADER_Z_FORMAT"},
345 {0xa1c5,
"SPI_SHADER_COL_FORMAT"},
346 {0xa203,
"DB_SHADER_CONTROL"},
347 {0xa08f,
"CB_SHADER_MASK"},
348 {0xa191,
"SPI_PS_INPUT_CNTL_0"},
349 {0xa192,
"SPI_PS_INPUT_CNTL_1"},
350 {0xa193,
"SPI_PS_INPUT_CNTL_2"},
351 {0xa194,
"SPI_PS_INPUT_CNTL_3"},
352 {0xa195,
"SPI_PS_INPUT_CNTL_4"},
353 {0xa196,
"SPI_PS_INPUT_CNTL_5"},
354 {0xa197,
"SPI_PS_INPUT_CNTL_6"},
355 {0xa198,
"SPI_PS_INPUT_CNTL_7"},
356 {0xa199,
"SPI_PS_INPUT_CNTL_8"},
357 {0xa19a,
"SPI_PS_INPUT_CNTL_9"},
358 {0xa19b,
"SPI_PS_INPUT_CNTL_10"},
359 {0xa19c,
"SPI_PS_INPUT_CNTL_11"},
360 {0xa19d,
"SPI_PS_INPUT_CNTL_12"},
361 {0xa19e,
"SPI_PS_INPUT_CNTL_13"},
362 {0xa19f,
"SPI_PS_INPUT_CNTL_14"},
363 {0xa1a0,
"SPI_PS_INPUT_CNTL_15"},
364 {0xa1a1,
"SPI_PS_INPUT_CNTL_16"},
365 {0xa1a2,
"SPI_PS_INPUT_CNTL_17"},
366 {0xa1a3,
"SPI_PS_INPUT_CNTL_18"},
367 {0xa1a4,
"SPI_PS_INPUT_CNTL_19"},
368 {0xa1a5,
"SPI_PS_INPUT_CNTL_20"},
369 {0xa1a6,
"SPI_PS_INPUT_CNTL_21"},
370 {0xa1a7,
"SPI_PS_INPUT_CNTL_22"},
371 {0xa1a8,
"SPI_PS_INPUT_CNTL_23"},
372 {0xa1a9,
"SPI_PS_INPUT_CNTL_24"},
373 {0xa1aa,
"SPI_PS_INPUT_CNTL_25"},
374 {0xa1ab,
"SPI_PS_INPUT_CNTL_26"},
375 {0xa1ac,
"SPI_PS_INPUT_CNTL_27"},
376 {0xa1ad,
"SPI_PS_INPUT_CNTL_28"},
377 {0xa1ae,
"SPI_PS_INPUT_CNTL_29"},
378 {0xa1af,
"SPI_PS_INPUT_CNTL_30"},
379 {0xa1b0,
"SPI_PS_INPUT_CNTL_31"},
381 {0xa2ce,
"VGT_GS_MAX_VERT_OUT"},
382 {0xa2ab,
"VGT_ESGS_RING_ITEMSIZE"},
383 {0xa290,
"VGT_GS_MODE"},
384 {0xa291,
"VGT_GS_ONCHIP_CNTL"},
385 {0xa2d7,
"VGT_GS_VERT_ITEMSIZE"},
386 {0xa2d8,
"VGT_GS_VERT_ITEMSIZE_1"},
387 {0xa2d9,
"VGT_GS_VERT_ITEMSIZE_2"},
388 {0xa2da,
"VGT_GS_VERT_ITEMSIZE_3"},
389 {0xa298,
"VGT_GSVS_RING_OFFSET_1"},
390 {0xa299,
"VGT_GSVS_RING_OFFSET_2"},
391 {0xa29a,
"VGT_GSVS_RING_OFFSET_3"},
393 {0xa2e4,
"VGT_GS_INSTANCE_CNT"},
394 {0xa297,
"VGT_GS_PER_VS"},
395 {0xa29b,
"VGT_GS_OUT_PRIM_TYPE"},
396 {0xa2ac,
"VGT_GSVS_RING_ITEMSIZE"},
398 {0xa2ad,
"VGT_REUSE_OFF"},
399 {0xa1b8,
"SPI_BARYC_CNTL"},
401 {0x2c4c,
"SPI_SHADER_USER_DATA_VS_0"},
402 {0x2c4d,
"SPI_SHADER_USER_DATA_VS_1"},
403 {0x2c4e,
"SPI_SHADER_USER_DATA_VS_2"},
404 {0x2c4f,
"SPI_SHADER_USER_DATA_VS_3"},
405 {0x2c50,
"SPI_SHADER_USER_DATA_VS_4"},
406 {0x2c51,
"SPI_SHADER_USER_DATA_VS_5"},
407 {0x2c52,
"SPI_SHADER_USER_DATA_VS_6"},
408 {0x2c53,
"SPI_SHADER_USER_DATA_VS_7"},
409 {0x2c54,
"SPI_SHADER_USER_DATA_VS_8"},
410 {0x2c55,
"SPI_SHADER_USER_DATA_VS_9"},
411 {0x2c56,
"SPI_SHADER_USER_DATA_VS_10"},
412 {0x2c57,
"SPI_SHADER_USER_DATA_VS_11"},
413 {0x2c58,
"SPI_SHADER_USER_DATA_VS_12"},
414 {0x2c59,
"SPI_SHADER_USER_DATA_VS_13"},
415 {0x2c5a,
"SPI_SHADER_USER_DATA_VS_14"},
416 {0x2c5b,
"SPI_SHADER_USER_DATA_VS_15"},
417 {0x2c5c,
"SPI_SHADER_USER_DATA_VS_16"},
418 {0x2c5d,
"SPI_SHADER_USER_DATA_VS_17"},
419 {0x2c5e,
"SPI_SHADER_USER_DATA_VS_18"},
420 {0x2c5f,
"SPI_SHADER_USER_DATA_VS_19"},
421 {0x2c60,
"SPI_SHADER_USER_DATA_VS_20"},
422 {0x2c61,
"SPI_SHADER_USER_DATA_VS_21"},
423 {0x2c62,
"SPI_SHADER_USER_DATA_VS_22"},
424 {0x2c63,
"SPI_SHADER_USER_DATA_VS_23"},
425 {0x2c64,
"SPI_SHADER_USER_DATA_VS_24"},
426 {0x2c65,
"SPI_SHADER_USER_DATA_VS_25"},
427 {0x2c66,
"SPI_SHADER_USER_DATA_VS_26"},
428 {0x2c67,
"SPI_SHADER_USER_DATA_VS_27"},
429 {0x2c68,
"SPI_SHADER_USER_DATA_VS_28"},
430 {0x2c69,
"SPI_SHADER_USER_DATA_VS_29"},
431 {0x2c6a,
"SPI_SHADER_USER_DATA_VS_30"},
432 {0x2c6b,
"SPI_SHADER_USER_DATA_VS_31"},
434 {0x2c8c,
"SPI_SHADER_USER_DATA_GS_0"},
435 {0x2c8d,
"SPI_SHADER_USER_DATA_GS_1"},
436 {0x2c8e,
"SPI_SHADER_USER_DATA_GS_2"},
437 {0x2c8f,
"SPI_SHADER_USER_DATA_GS_3"},
438 {0x2c90,
"SPI_SHADER_USER_DATA_GS_4"},
439 {0x2c91,
"SPI_SHADER_USER_DATA_GS_5"},
440 {0x2c92,
"SPI_SHADER_USER_DATA_GS_6"},
441 {0x2c93,
"SPI_SHADER_USER_DATA_GS_7"},
442 {0x2c94,
"SPI_SHADER_USER_DATA_GS_8"},
443 {0x2c95,
"SPI_SHADER_USER_DATA_GS_9"},
444 {0x2c96,
"SPI_SHADER_USER_DATA_GS_10"},
445 {0x2c97,
"SPI_SHADER_USER_DATA_GS_11"},
446 {0x2c98,
"SPI_SHADER_USER_DATA_GS_12"},
447 {0x2c99,
"SPI_SHADER_USER_DATA_GS_13"},
448 {0x2c9a,
"SPI_SHADER_USER_DATA_GS_14"},
449 {0x2c9b,
"SPI_SHADER_USER_DATA_GS_15"},
450 {0x2c9c,
"SPI_SHADER_USER_DATA_GS_16"},
451 {0x2c9d,
"SPI_SHADER_USER_DATA_GS_17"},
452 {0x2c9e,
"SPI_SHADER_USER_DATA_GS_18"},
453 {0x2c9f,
"SPI_SHADER_USER_DATA_GS_19"},
454 {0x2ca0,
"SPI_SHADER_USER_DATA_GS_20"},
455 {0x2ca1,
"SPI_SHADER_USER_DATA_GS_21"},
456 {0x2ca2,
"SPI_SHADER_USER_DATA_GS_22"},
457 {0x2ca3,
"SPI_SHADER_USER_DATA_GS_23"},
458 {0x2ca4,
"SPI_SHADER_USER_DATA_GS_24"},
459 {0x2ca5,
"SPI_SHADER_USER_DATA_GS_25"},
460 {0x2ca6,
"SPI_SHADER_USER_DATA_GS_26"},
461 {0x2ca7,
"SPI_SHADER_USER_DATA_GS_27"},
462 {0x2ca8,
"SPI_SHADER_USER_DATA_GS_28"},
463 {0x2ca9,
"SPI_SHADER_USER_DATA_GS_29"},
464 {0x2caa,
"SPI_SHADER_USER_DATA_GS_30"},
465 {0x2cab,
"SPI_SHADER_USER_DATA_GS_31"},
467 {0x2ccc,
"SPI_SHADER_USER_DATA_ES_0"},
468 {0x2ccd,
"SPI_SHADER_USER_DATA_ES_1"},
469 {0x2cce,
"SPI_SHADER_USER_DATA_ES_2"},
470 {0x2ccf,
"SPI_SHADER_USER_DATA_ES_3"},
471 {0x2cd0,
"SPI_SHADER_USER_DATA_ES_4"},
472 {0x2cd1,
"SPI_SHADER_USER_DATA_ES_5"},
473 {0x2cd2,
"SPI_SHADER_USER_DATA_ES_6"},
474 {0x2cd3,
"SPI_SHADER_USER_DATA_ES_7"},
475 {0x2cd4,
"SPI_SHADER_USER_DATA_ES_8"},
476 {0x2cd5,
"SPI_SHADER_USER_DATA_ES_9"},
477 {0x2cd6,
"SPI_SHADER_USER_DATA_ES_10"},
478 {0x2cd7,
"SPI_SHADER_USER_DATA_ES_11"},
479 {0x2cd8,
"SPI_SHADER_USER_DATA_ES_12"},
480 {0x2cd9,
"SPI_SHADER_USER_DATA_ES_13"},
481 {0x2cda,
"SPI_SHADER_USER_DATA_ES_14"},
482 {0x2cdb,
"SPI_SHADER_USER_DATA_ES_15"},
483 {0x2cdc,
"SPI_SHADER_USER_DATA_ES_16"},
484 {0x2cdd,
"SPI_SHADER_USER_DATA_ES_17"},
485 {0x2cde,
"SPI_SHADER_USER_DATA_ES_18"},
486 {0x2cdf,
"SPI_SHADER_USER_DATA_ES_19"},
487 {0x2ce0,
"SPI_SHADER_USER_DATA_ES_20"},
488 {0x2ce1,
"SPI_SHADER_USER_DATA_ES_21"},
489 {0x2ce2,
"SPI_SHADER_USER_DATA_ES_22"},
490 {0x2ce3,
"SPI_SHADER_USER_DATA_ES_23"},
491 {0x2ce4,
"SPI_SHADER_USER_DATA_ES_24"},
492 {0x2ce5,
"SPI_SHADER_USER_DATA_ES_25"},
493 {0x2ce6,
"SPI_SHADER_USER_DATA_ES_26"},
494 {0x2ce7,
"SPI_SHADER_USER_DATA_ES_27"},
495 {0x2ce8,
"SPI_SHADER_USER_DATA_ES_28"},
496 {0x2ce9,
"SPI_SHADER_USER_DATA_ES_29"},
497 {0x2cea,
"SPI_SHADER_USER_DATA_ES_30"},
498 {0x2ceb,
"SPI_SHADER_USER_DATA_ES_31"},
500 {0x2c0c,
"SPI_SHADER_USER_DATA_PS_0"},
501 {0x2c0d,
"SPI_SHADER_USER_DATA_PS_1"},
502 {0x2c0e,
"SPI_SHADER_USER_DATA_PS_2"},
503 {0x2c0f,
"SPI_SHADER_USER_DATA_PS_3"},
504 {0x2c10,
"SPI_SHADER_USER_DATA_PS_4"},
505 {0x2c11,
"SPI_SHADER_USER_DATA_PS_5"},
506 {0x2c12,
"SPI_SHADER_USER_DATA_PS_6"},
507 {0x2c13,
"SPI_SHADER_USER_DATA_PS_7"},
508 {0x2c14,
"SPI_SHADER_USER_DATA_PS_8"},
509 {0x2c15,
"SPI_SHADER_USER_DATA_PS_9"},
510 {0x2c16,
"SPI_SHADER_USER_DATA_PS_10"},
511 {0x2c17,
"SPI_SHADER_USER_DATA_PS_11"},
512 {0x2c18,
"SPI_SHADER_USER_DATA_PS_12"},
513 {0x2c19,
"SPI_SHADER_USER_DATA_PS_13"},
514 {0x2c1a,
"SPI_SHADER_USER_DATA_PS_14"},
515 {0x2c1b,
"SPI_SHADER_USER_DATA_PS_15"},
516 {0x2c1c,
"SPI_SHADER_USER_DATA_PS_16"},
517 {0x2c1d,
"SPI_SHADER_USER_DATA_PS_17"},
518 {0x2c1e,
"SPI_SHADER_USER_DATA_PS_18"},
519 {0x2c1f,
"SPI_SHADER_USER_DATA_PS_19"},
520 {0x2c20,
"SPI_SHADER_USER_DATA_PS_20"},
521 {0x2c21,
"SPI_SHADER_USER_DATA_PS_21"},
522 {0x2c22,
"SPI_SHADER_USER_DATA_PS_22"},
523 {0x2c23,
"SPI_SHADER_USER_DATA_PS_23"},
524 {0x2c24,
"SPI_SHADER_USER_DATA_PS_24"},
525 {0x2c25,
"SPI_SHADER_USER_DATA_PS_25"},
526 {0x2c26,
"SPI_SHADER_USER_DATA_PS_26"},
527 {0x2c27,
"SPI_SHADER_USER_DATA_PS_27"},
528 {0x2c28,
"SPI_SHADER_USER_DATA_PS_28"},
529 {0x2c29,
"SPI_SHADER_USER_DATA_PS_29"},
530 {0x2c2a,
"SPI_SHADER_USER_DATA_PS_30"},
531 {0x2c2b,
"SPI_SHADER_USER_DATA_PS_31"},
533 {0x2e40,
"COMPUTE_USER_DATA_0"},
534 {0x2e41,
"COMPUTE_USER_DATA_1"},
535 {0x2e42,
"COMPUTE_USER_DATA_2"},
536 {0x2e43,
"COMPUTE_USER_DATA_3"},
537 {0x2e44,
"COMPUTE_USER_DATA_4"},
538 {0x2e45,
"COMPUTE_USER_DATA_5"},
539 {0x2e46,
"COMPUTE_USER_DATA_6"},
540 {0x2e47,
"COMPUTE_USER_DATA_7"},
541 {0x2e48,
"COMPUTE_USER_DATA_8"},
542 {0x2e49,
"COMPUTE_USER_DATA_9"},
543 {0x2e4a,
"COMPUTE_USER_DATA_10"},
544 {0x2e4b,
"COMPUTE_USER_DATA_11"},
545 {0x2e4c,
"COMPUTE_USER_DATA_12"},
546 {0x2e4d,
"COMPUTE_USER_DATA_13"},
547 {0x2e4e,
"COMPUTE_USER_DATA_14"},
548 {0x2e4f,
"COMPUTE_USER_DATA_15"},
550 {0x2e07,
"COMPUTE_NUM_THREAD_X"},
551 {0x2e08,
"COMPUTE_NUM_THREAD_Y"},
552 {0x2e09,
"COMPUTE_NUM_THREAD_Z"},
553 {0xa2db,
"VGT_TF_PARAM"},
554 {0xa2d6,
"VGT_LS_HS_CONFIG"},
555 {0xa287,
"VGT_HOS_MIN_TESS_LEVEL"},
556 {0xa286,
"VGT_HOS_MAX_TESS_LEVEL"},
557 {0xa2f8,
"PA_SC_AA_CONFIG"},
558 {0xa310,
"PA_SC_SHADER_CONTROL"},
559 {0xa313,
"PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"},
561 {0x2d0c,
"SPI_SHADER_USER_DATA_HS_0"},
562 {0x2d0d,
"SPI_SHADER_USER_DATA_HS_1"},
563 {0x2d0e,
"SPI_SHADER_USER_DATA_HS_2"},
564 {0x2d0f,
"SPI_SHADER_USER_DATA_HS_3"},
565 {0x2d10,
"SPI_SHADER_USER_DATA_HS_4"},
566 {0x2d11,
"SPI_SHADER_USER_DATA_HS_5"},
567 {0x2d12,
"SPI_SHADER_USER_DATA_HS_6"},
568 {0x2d13,
"SPI_SHADER_USER_DATA_HS_7"},
569 {0x2d14,
"SPI_SHADER_USER_DATA_HS_8"},
570 {0x2d15,
"SPI_SHADER_USER_DATA_HS_9"},
571 {0x2d16,
"SPI_SHADER_USER_DATA_HS_10"},
572 {0x2d17,
"SPI_SHADER_USER_DATA_HS_11"},
573 {0x2d18,
"SPI_SHADER_USER_DATA_HS_12"},
574 {0x2d19,
"SPI_SHADER_USER_DATA_HS_13"},
575 {0x2d1a,
"SPI_SHADER_USER_DATA_HS_14"},
576 {0x2d1b,
"SPI_SHADER_USER_DATA_HS_15"},
577 {0x2d1c,
"SPI_SHADER_USER_DATA_HS_16"},
578 {0x2d1d,
"SPI_SHADER_USER_DATA_HS_17"},
579 {0x2d1e,
"SPI_SHADER_USER_DATA_HS_18"},
580 {0x2d1f,
"SPI_SHADER_USER_DATA_HS_19"},
581 {0x2d20,
"SPI_SHADER_USER_DATA_HS_20"},
582 {0x2d21,
"SPI_SHADER_USER_DATA_HS_21"},
583 {0x2d22,
"SPI_SHADER_USER_DATA_HS_22"},
584 {0x2d23,
"SPI_SHADER_USER_DATA_HS_23"},
585 {0x2d24,
"SPI_SHADER_USER_DATA_HS_24"},
586 {0x2d25,
"SPI_SHADER_USER_DATA_HS_25"},
587 {0x2d26,
"SPI_SHADER_USER_DATA_HS_26"},
588 {0x2d27,
"SPI_SHADER_USER_DATA_HS_27"},
589 {0x2d28,
"SPI_SHADER_USER_DATA_HS_28"},
590 {0x2d29,
"SPI_SHADER_USER_DATA_HS_29"},
591 {0x2d2a,
"SPI_SHADER_USER_DATA_HS_30"},
592 {0x2d2b,
"SPI_SHADER_USER_DATA_HS_31"},
594 {0x2d4c,
"SPI_SHADER_USER_DATA_LS_0"},
595 {0x2d4d,
"SPI_SHADER_USER_DATA_LS_1"},
596 {0x2d4e,
"SPI_SHADER_USER_DATA_LS_2"},
597 {0x2d4f,
"SPI_SHADER_USER_DATA_LS_3"},
598 {0x2d50,
"SPI_SHADER_USER_DATA_LS_4"},
599 {0x2d51,
"SPI_SHADER_USER_DATA_LS_5"},
600 {0x2d52,
"SPI_SHADER_USER_DATA_LS_6"},
601 {0x2d53,
"SPI_SHADER_USER_DATA_LS_7"},
602 {0x2d54,
"SPI_SHADER_USER_DATA_LS_8"},
603 {0x2d55,
"SPI_SHADER_USER_DATA_LS_9"},
604 {0x2d56,
"SPI_SHADER_USER_DATA_LS_10"},
605 {0x2d57,
"SPI_SHADER_USER_DATA_LS_11"},
606 {0x2d58,
"SPI_SHADER_USER_DATA_LS_12"},
607 {0x2d59,
"SPI_SHADER_USER_DATA_LS_13"},
608 {0x2d5a,
"SPI_SHADER_USER_DATA_LS_14"},
609 {0x2d5b,
"SPI_SHADER_USER_DATA_LS_15"},
611 {0xa2aa,
"IA_MULTI_VGT_PARAM"},
612 {0xa2a5,
"VGT_GS_MAX_PRIMS_PER_SUBGROUP"},
613 {0xa2e6,
"VGT_STRMOUT_BUFFER_CONFIG"},
614 {0xa2e5,
"VGT_STRMOUT_CONFIG"},
615 {0xa2b5,
"VGT_STRMOUT_VTX_STRIDE_0"},
616 {0xa2b9,
"VGT_STRMOUT_VTX_STRIDE_1"},
617 {0xa2bd,
"VGT_STRMOUT_VTX_STRIDE_2"},
618 {0xa2c1,
"VGT_STRMOUT_VTX_STRIDE_3"},
619 {0xa316,
"VGT_VERTEX_REUSE_BLOCK_CNTL"},
621 {0x2e28,
"COMPUTE_PGM_RSRC3"},
622 {0x2e2a,
"COMPUTE_SHADER_CHKSUM"},
623 {0x2e24,
"COMPUTE_USER_ACCUM_0"},
624 {0x2e25,
"COMPUTE_USER_ACCUM_1"},
625 {0x2e26,
"COMPUTE_USER_ACCUM_2"},
626 {0x2e27,
"COMPUTE_USER_ACCUM_3"},
627 {0xa1ff,
"GE_MAX_OUTPUT_PER_SUBGROUP"},
628 {0xa2d3,
"GE_NGG_SUBGRP_CNTL"},
629 {0xc25f,
"GE_STEREO_CNTL"},
630 {0xc262,
"GE_USER_VGPR_EN"},
631 {0xc258,
"IA_MULTI_VGT_PARAM_PIPED"},
632 {0xa210,
"PA_STEREO_CNTL"},
633 {0xa1c2,
"SPI_SHADER_IDX_FORMAT"},
634 {0x2c80,
"SPI_SHADER_PGM_CHKSUM_GS"},
635 {0x2d00,
"SPI_SHADER_PGM_CHKSUM_HS"},
636 {0x2c06,
"SPI_SHADER_PGM_CHKSUM_PS"},
637 {0x2c45,
"SPI_SHADER_PGM_CHKSUM_VS"},
638 {0x2c88,
"SPI_SHADER_PGM_LO_GS"},
639 {0x2cb2,
"SPI_SHADER_USER_ACCUM_ESGS_0"},
640 {0x2cb3,
"SPI_SHADER_USER_ACCUM_ESGS_1"},
641 {0x2cb4,
"SPI_SHADER_USER_ACCUM_ESGS_2"},
642 {0x2cb5,
"SPI_SHADER_USER_ACCUM_ESGS_3"},
643 {0x2d32,
"SPI_SHADER_USER_ACCUM_LSHS_0"},
644 {0x2d33,
"SPI_SHADER_USER_ACCUM_LSHS_1"},
645 {0x2d34,
"SPI_SHADER_USER_ACCUM_LSHS_2"},
646 {0x2d35,
"SPI_SHADER_USER_ACCUM_LSHS_3"},
647 {0x2c32,
"SPI_SHADER_USER_ACCUM_PS_0"},
648 {0x2c33,
"SPI_SHADER_USER_ACCUM_PS_1"},
649 {0x2c34,
"SPI_SHADER_USER_ACCUM_PS_2"},
650 {0x2c35,
"SPI_SHADER_USER_ACCUM_PS_3"},
651 {0x2c72,
"SPI_SHADER_USER_ACCUM_VS_0"},
652 {0x2c73,
"SPI_SHADER_USER_ACCUM_VS_1"},
653 {0x2c74,
"SPI_SHADER_USER_ACCUM_VS_2"},
654 {0x2c75,
"SPI_SHADER_USER_ACCUM_VS_3"},
657 auto Entry = RegInfoTable;
658 for (; Entry->Num && Entry->Num != RegNum; ++Entry)
674 auto Regs = getRegisters();
675 for (
auto I = Regs.begin(),
E = Regs.end();
I !=
E; ++
I) {
676 if (
I != Regs.begin())
678 unsigned Reg =
I->first.getUInt();
679 unsigned Val =
I->second.getUInt();
688 MsgPackDoc.setHexMode();
689 auto &RegsObj = refRegisters();
690 auto OrigRegs = RegsObj.getMap();
691 RegsObj = MsgPackDoc.getMapNode();
692 for (
auto I : OrigRegs) {
695 std::string KeyName =
Key.toString();
699 Key = MsgPackDoc.getNode(KeyName,
true);
701 RegsObj.getMap()[
Key] =
I.second;
706 MsgPackDoc.toYAML(Stream);
723 void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) {
736 void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) {
738 MsgPackDoc.writeToBlob(Blob);
744 if (!MsgPackDoc.fromYAML(
S))
750 auto &RegsObj = refRegisters();
751 auto OrigRegs = RegsObj;
752 RegsObj = MsgPackDoc.getMapNode();
755 for (
auto I : OrigRegs.getMap()) {
760 if (
S.consumeInteger(0, Val)) {
762 errs() <<
"Unrecognized PAL metadata register key '" <<
S <<
"'\n";
776 .getMap(
true)[MsgPackDoc.getNode(
"amdpal.pipelines")]
778 .getMap(
true)[MsgPackDoc.getNode(
".registers")];
794 .getMap(
true)[MsgPackDoc.getNode(
"amdpal.pipelines")]
796 .getMap(
true)[MsgPackDoc.getNode(
".shader_functions")];
803 if (ShaderFunctions.isEmpty())
804 ShaderFunctions = refShaderFunctions();
805 return ShaderFunctions.getMap();
810 auto Functions = getShaderFunctions();
811 return Functions[
Name].getMap(
true);
839 if (HwStages.isEmpty())
840 HwStages = MsgPackDoc.getRoot()
841 .
getMap(
true)[
"amdpal.pipelines"]
843 .
getMap(
true)[
".hardware_stages"]
862 bool AMDGPUPALMetadata::isLegacy()
const {
875 HwStages = MsgPackDoc.getEmptyNode();
MapDocNode & getMap(bool Convert=false)
Get a MapDocNode for a map node.
This is an optimization pass for GlobalISel generic memory operations.
@ R_A2D5_VGT_SHADER_STAGES_EN
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
@ R_2D4A_SPI_SHADER_PGM_RSRC1_LS
A raw_ostream that writes to an std::string.
@ R_A1B4_SPI_PS_INPUT_ADDR
@ AMDGPU_Gfx
Calling convention used for AMD graphics targets.
@ R_2E12_COMPUTE_PGM_RSRC1
Reg
All possible values of the reg field in the ModR/M byte.
SI Pre allocate WWM Registers
The instances of the Type class are immutable: once they are created, they are never changed.
#define S_0286D8_PS_W32_EN(x)
@ R_A1B3_SPI_PS_INPUT_ENA
constexpr char AssemblerDirective[]
PAL metadata (old linear format) assembler directive.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Adapter to write values to a stream in a particular byte order.
constexpr char AssemblerDirectiveBegin[]
PAL metadata (new MsgPack format) beginning assembler directive.
@ AMDGPU_HS
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
@ AMDGPU_LS
Calling convention used for AMDPAL vertex shader if tessellation is in use.
A node in a MsgPack Document.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
@ R_2C8A_SPI_SHADER_PGM_RSRC1_GS
#define S_028B54_VS_W32_EN(x)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
#define S_00B800_CS_W32_EN(x)
static Twine utohexstr(const uint64_t &Val)
@ R_2E00_COMPUTE_DISPATCH_INITIATOR
A Module instance is used to store all the information related to an LLVM module.
@ R_2C4A_SPI_SHADER_PGM_RSRC1_VS
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
StringRef getName() const
Return a constant reference to the value's name.
Reads MessagePack objects from memory, one at a time.
@ AMDGPU_GS
Calling convention used for Mesa/AMDPAL geometry shaders.
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
Function & getFunction()
Return the LLVM function that this machine code represents.
@ R_2C0A_SPI_SHADER_PGM_RSRC1_PS
#define S_028B54_GS_W32_EN(x)
ArrayDocNode & getArray(bool Convert=false)
Get an ArrayDocNode for an array node.
@ R_A1B6_SPI_PS_IN_CONTROL
@ R_2CCA_SPI_SHADER_PGM_RSRC1_ES
constexpr char AssemblerDirectiveEnd[]
PAL metadata (new MsgPack format) ending assembler directive.
@ AMDGPU_VS
Calling convention used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (ve...
@ AMDGPU_ES
Calling convention used for AMDPAL shader stage before geometry shader if geometry is in use.
@ AMDGPU_CS
Calling convention used for Mesa/AMDPAL compute shaders.
#define S_028B54_HS_W32_EN(x)
@ R_2D0A_SPI_SHADER_PGM_RSRC1_HS
const LLVM_NODISCARD char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
@ AMDGPU_PS
Calling convention used for Mesa/AMDPAL pixel shaders.