LLVM  14.0.0git
SIMachineScheduler.h
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1 //===-- SIMachineScheduler.h - SI Scheduler Interface -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// SI Machine Scheduler interface
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINESCHEDULER_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINESCHEDULER_H
16 
20 #include <cstdint>
21 #include <set>
22 #include <vector>
23 
24 namespace llvm {
25 
26 class SIInstrInfo;
27 class SIRegisterInfo;
28 
36 };
37 
39  // The reason for this candidate.
41 
42  // Set of reasons that apply to multiple candidates.
44 
45  SISchedulerCandidate() = default;
46 
47  bool isRepeat(SIScheduleCandReason R) { return RepeatReasonSet & (1 << R); }
49 };
50 
51 class SIScheduleDAGMI;
52 class SIScheduleBlockCreator;
53 
57 };
58 
60  SIScheduleDAGMI *DAG;
62 
63  std::vector<SUnit*> SUnits;
64  std::map<unsigned, unsigned> NodeNum2Index;
65  std::vector<SUnit*> TopReadySUs;
66  std::vector<SUnit*> ScheduledSUnits;
67 
68  /// The top of the unscheduled zone.
69  IntervalPressure TopPressure;
70  RegPressureTracker TopRPTracker;
71 
72  // Pressure: number of said class of registers needed to
73  // store the live virtual and real registers.
74  // We do care only of SGPR32 and VGPR32 and do track only virtual registers.
75  // Pressure of additional registers required inside the block.
76  std::vector<unsigned> InternalAdditionnalPressure;
77  // Pressure of input and output registers
78  std::vector<unsigned> LiveInPressure;
79  std::vector<unsigned> LiveOutPressure;
80  // Registers required by the block, and outputs.
81  // We do track only virtual registers.
82  // Note that some registers are not 32 bits,
83  // and thus the pressure is not equal
84  // to the number of live registers.
85  std::set<unsigned> LiveInRegs;
86  std::set<unsigned> LiveOutRegs;
87 
88  bool Scheduled = false;
89  bool HighLatencyBlock = false;
90 
91  std::vector<unsigned> HasLowLatencyNonWaitedParent;
92 
93  // Unique ID, the index of the Block in the SIScheduleDAGMI Blocks table.
94  unsigned ID;
95 
96  std::vector<SIScheduleBlock*> Preds; // All blocks predecessors.
97  // All blocks successors, and the kind of link
98  std::vector<std::pair<SIScheduleBlock*, SIScheduleBlockLinkKind>> Succs;
99  unsigned NumHighLatencySuccessors = 0;
100 
101 public:
103  unsigned ID):
104  DAG(DAG), BC(BC), TopRPTracker(TopPressure), ID(ID) {}
105 
106  ~SIScheduleBlock() = default;
107 
108  unsigned getID() const { return ID; }
109 
110  /// Functions for Block construction.
111  void addUnit(SUnit *SU);
112 
113  // When all SUs have been added.
114  void finalizeUnits();
115 
116  // Add block pred, which has instruction predecessor of SU.
117  void addPred(SIScheduleBlock *Pred);
119 
120  const std::vector<SIScheduleBlock*>& getPreds() const { return Preds; }
122  getSuccs() const { return Succs; }
123 
124  unsigned Height; // Maximum topdown path length to block without outputs
125  unsigned Depth; // Maximum bottomup path length to block without inputs
126 
127  unsigned getNumHighLatencySuccessors() const {
128  return NumHighLatencySuccessors;
129  }
130 
131  bool isHighLatencyBlock() { return HighLatencyBlock; }
132 
133  // This is approximative.
134  // Ideally should take into accounts some instructions (rcp, etc)
135  // are 4 times slower.
136  int getCost() { return SUnits.size(); }
137 
138  // The block Predecessors and Successors must be all registered
139  // before fastSchedule().
140  // Fast schedule with no particular requirement.
141  void fastSchedule();
142 
143  std::vector<SUnit*> getScheduledUnits() { return ScheduledSUnits; }
144 
145  // Complete schedule that will try to minimize reg pressure and
146  // low latencies, and will fill liveins and liveouts.
147  // Needs all MIs to be grouped between BeginBlock and EndBlock.
148  // The MIs can be moved after the scheduling,
149  // it is just used to allow correct track of live registers.
150  void schedule(MachineBasicBlock::iterator BeginBlock,
151  MachineBasicBlock::iterator EndBlock);
152 
153  bool isScheduled() { return Scheduled; }
154 
155  // Needs the block to be scheduled inside
156  // TODO: find a way to compute it.
157  std::vector<unsigned> &getInternalAdditionnalRegUsage() {
158  return InternalAdditionnalPressure;
159  }
160 
161  std::set<unsigned> &getInRegs() { return LiveInRegs; }
162  std::set<unsigned> &getOutRegs() { return LiveOutRegs; }
163 
164  void printDebug(bool Full);
165 
166 private:
167  struct SISchedCandidate : SISchedulerCandidate {
168  // The best SUnit candidate.
169  SUnit *SU = nullptr;
170 
171  unsigned SGPRUsage;
172  unsigned VGPRUsage;
173  bool IsLowLatency;
174  unsigned LowLatencyOffset;
175  bool HasLowLatencyNonWaitedParent;
176 
177  SISchedCandidate() = default;
178 
179  bool isValid() const { return SU; }
180 
181  // Copy the status of another candidate without changing policy.
182  void setBest(SISchedCandidate &Best) {
183  assert(Best.Reason != NoCand && "uninitialized Sched candidate");
184  SU = Best.SU;
185  Reason = Best.Reason;
186  SGPRUsage = Best.SGPRUsage;
187  VGPRUsage = Best.VGPRUsage;
188  IsLowLatency = Best.IsLowLatency;
189  LowLatencyOffset = Best.LowLatencyOffset;
190  HasLowLatencyNonWaitedParent = Best.HasLowLatencyNonWaitedParent;
191  }
192  };
193 
194  void undoSchedule();
195 
196  void undoReleaseSucc(SUnit *SU, SDep *SuccEdge);
197  void releaseSucc(SUnit *SU, SDep *SuccEdge);
198  // InOrOutBlock: restrict to links pointing inside the block (true),
199  // or restrict to links pointing outside the block (false).
200  void releaseSuccessors(SUnit *SU, bool InOrOutBlock);
201 
202  void nodeScheduled(SUnit *SU);
203  void tryCandidateTopDown(SISchedCandidate &Cand, SISchedCandidate &TryCand);
204  void tryCandidateBottomUp(SISchedCandidate &Cand, SISchedCandidate &TryCand);
205  SUnit* pickNode();
206  void traceCandidate(const SISchedCandidate &Cand);
207  void initRegPressure(MachineBasicBlock::iterator BeginBlock,
208  MachineBasicBlock::iterator EndBlock);
209 };
210 
212  std::vector<SIScheduleBlock*> Blocks;
213  std::vector<int> TopDownIndex2Block;
214  std::vector<int> TopDownBlock2Index;
215 };
216 
221 };
222 
224  SIScheduleDAGMI *DAG;
225  // unique_ptr handles freeing memory for us.
226  std::vector<std::unique_ptr<SIScheduleBlock>> BlockPtrs;
228  SIScheduleBlocks> Blocks;
229  std::vector<SIScheduleBlock*> CurrentBlocks;
230  std::vector<int> Node2CurrentBlock;
231 
232  // Topological sort
233  // Maps topological index to the node number.
234  std::vector<int> TopDownIndex2Block;
235  std::vector<int> TopDownBlock2Index;
236  std::vector<int> BottomUpIndex2Block;
237 
238  // 0 -> Color not given.
239  // 1 to SUnits.size() -> Reserved group (you should only add elements to them).
240  // Above -> Other groups.
241  int NextReservedID;
242  int NextNonReservedID;
243  std::vector<int> CurrentColoring;
244  std::vector<int> CurrentTopDownReservedDependencyColoring;
245  std::vector<int> CurrentBottomUpReservedDependencyColoring;
246 
247 public:
249 
252 
253  bool isSUInBlock(SUnit *SU, unsigned ID);
254 
255 private:
256  // Give a Reserved color to every high latency.
257  void colorHighLatenciesAlone();
258 
259  // Create groups of high latencies with a Reserved color.
260  void colorHighLatenciesGroups();
261 
262  // Compute coloring for topdown and bottom traversals with
263  // different colors depending on dependencies on Reserved colors.
264  void colorComputeReservedDependencies();
265 
266  // Give color to all non-colored SUs according to Reserved groups dependencies.
267  void colorAccordingToReservedDependencies();
268 
269  // Divides Blocks having no bottom up or top down dependencies on Reserved groups.
270  // The new colors are computed according to the dependencies on the other blocks
271  // formed with colorAccordingToReservedDependencies.
272  void colorEndsAccordingToDependencies();
273 
274  // Cut groups into groups with SUs in consecutive order (except for Reserved groups).
275  void colorForceConsecutiveOrderInGroup();
276 
277  // Merge Constant loads that have all their users into another group to the group.
278  // (TODO: else if all their users depend on the same group, put them there)
279  void colorMergeConstantLoadsNextGroup();
280 
281  // Merge SUs that have all their users into another group to the group
282  void colorMergeIfPossibleNextGroup();
283 
284  // Merge SUs that have all their users into another group to the group,
285  // but only for Reserved groups.
286  void colorMergeIfPossibleNextGroupOnlyForReserved();
287 
288  // Merge SUs that have all their users into another group to the group,
289  // but only if the group is no more than a few SUs.
290  void colorMergeIfPossibleSmallGroupsToNextGroup();
291 
292  // Divides Blocks with important size.
293  // Idea of implementation: attribute new colors depending on topdown and
294  // bottom up links to other blocks.
295  void cutHugeBlocks();
296 
297  // Put in one group all instructions with no users in this scheduling region
298  // (we'd want these groups be at the end).
299  void regroupNoUserInstructions();
300 
301  // Give Reserved color to export instructions
302  void colorExports();
303 
304  void createBlocksForVariant(SISchedulerBlockCreatorVariant BlockVariant);
305 
306  void topologicalSort();
307 
308  void scheduleInsideBlocks();
309 
310  void fillStats();
311 };
312 
317 };
318 
320  SIScheduleDAGMI *DAG;
322  std::vector<SIScheduleBlock*> Blocks;
323 
324  std::vector<std::map<unsigned, unsigned>> LiveOutRegsNumUsages;
325  std::set<unsigned> LiveRegs;
326  // Num of schedulable unscheduled blocks reading the register.
327  std::map<unsigned, unsigned> LiveRegsConsumers;
328 
329  std::vector<unsigned> LastPosHighLatencyParentScheduled;
330  int LastPosWaitedHighLatency;
331 
332  std::vector<SIScheduleBlock*> BlocksScheduled;
333  unsigned NumBlockScheduled;
334  std::vector<SIScheduleBlock*> ReadyBlocks;
335 
336  unsigned VregCurrentUsage;
337  unsigned SregCurrentUsage;
338 
339  // Currently is only approximation.
340  unsigned maxVregUsage;
341  unsigned maxSregUsage;
342 
343  std::vector<unsigned> BlockNumPredsLeft;
344  std::vector<unsigned> BlockNumSuccsLeft;
345 
346 public:
349  SIScheduleBlocks BlocksStruct);
350  ~SIScheduleBlockScheduler() = default;
351 
352  std::vector<SIScheduleBlock*> getBlocks() { return BlocksScheduled; }
353 
354  unsigned getVGPRUsage() { return maxVregUsage; }
355  unsigned getSGPRUsage() { return maxSregUsage; }
356 
357 private:
358  struct SIBlockSchedCandidate : SISchedulerCandidate {
359  // The best Block candidate.
360  SIScheduleBlock *Block = nullptr;
361 
362  bool IsHighLatency;
363  int VGPRUsageDiff;
364  unsigned NumSuccessors;
365  unsigned NumHighLatencySuccessors;
366  unsigned LastPosHighLatParentScheduled;
367  unsigned Height;
368 
369  SIBlockSchedCandidate() = default;
370 
371  bool isValid() const { return Block; }
372 
373  // Copy the status of another candidate without changing policy.
374  void setBest(SIBlockSchedCandidate &Best) {
375  assert(Best.Reason != NoCand && "uninitialized Sched candidate");
376  Block = Best.Block;
377  Reason = Best.Reason;
378  IsHighLatency = Best.IsHighLatency;
379  VGPRUsageDiff = Best.VGPRUsageDiff;
380  NumSuccessors = Best.NumSuccessors;
381  NumHighLatencySuccessors = Best.NumHighLatencySuccessors;
382  LastPosHighLatParentScheduled = Best.LastPosHighLatParentScheduled;
383  Height = Best.Height;
384  }
385  };
386 
387  bool tryCandidateLatency(SIBlockSchedCandidate &Cand,
388  SIBlockSchedCandidate &TryCand);
389  bool tryCandidateRegUsage(SIBlockSchedCandidate &Cand,
390  SIBlockSchedCandidate &TryCand);
391  SIScheduleBlock *pickBlock();
392 
393  void addLiveRegs(std::set<unsigned> &Regs);
394  void decreaseLiveRegs(SIScheduleBlock *Block, std::set<unsigned> &Regs);
395  void releaseBlockSuccs(SIScheduleBlock *Parent);
396  void blockScheduled(SIScheduleBlock *Block);
397 
398  // Check register pressure change
399  // by scheduling a block with these LiveIn and LiveOut.
400  std::vector<int> checkRegUsageImpact(std::set<unsigned> &InRegs,
401  std::set<unsigned> &OutRegs);
402 
403  void schedule();
404 };
405 
407  std::vector<unsigned> SUs;
408  unsigned MaxSGPRUsage;
409  unsigned MaxVGPRUsage;
410 };
411 
412 class SIScheduler {
413  SIScheduleDAGMI *DAG;
414  SIScheduleBlockCreator BlockCreator;
415 
416 public:
417  SIScheduler(SIScheduleDAGMI *DAG) : DAG(DAG), BlockCreator(DAG) {}
418 
419  ~SIScheduler() = default;
420 
421  struct SIScheduleBlockResult
423  SISchedulerBlockSchedulerVariant ScheduleVariant);
424 };
425 
426 class SIScheduleDAGMI final : public ScheduleDAGMILive {
427  const SIInstrInfo *SITII;
428  const SIRegisterInfo *SITRI;
429 
430  std::vector<SUnit> SUnitsLinksBackup;
431 
432  // For moveLowLatencies. After all Scheduling variants are tested.
433  std::vector<unsigned> ScheduledSUnits;
434  std::vector<unsigned> ScheduledSUnitsInv;
435 
436 public:
438 
439  ~SIScheduleDAGMI() override;
440 
441  // Entry point for the schedule.
442  void schedule() override;
443 
444  // To init Block's RPTracker.
446  RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false);
447  }
448 
449  MachineBasicBlock *getBB() { return BB; }
452  LiveIntervals *getLIS() { return LIS; }
454  const TargetRegisterInfo *getTRI() { return TRI; }
456  SUnit &getEntrySU() { return EntrySU; }
457  SUnit& getExitSU() { return ExitSU; }
458 
459  void restoreSULinksLeft();
460 
461  template<typename _Iterator> void fillVgprSgprCost(_Iterator First,
462  _Iterator End,
463  unsigned &VgprUsage,
464  unsigned &SgprUsage);
465 
466  std::set<unsigned> getInRegs() {
467  std::set<unsigned> InRegs;
468  for (const auto &RegMaskPair : RPTracker.getPressure().LiveInRegs) {
469  InRegs.insert(RegMaskPair.RegUnit);
470  }
471  return InRegs;
472  }
473 
474  std::set<unsigned> getOutRegs() {
475  std::set<unsigned> OutRegs;
476  for (const auto &RegMaskPair : RPTracker.getPressure().LiveOutRegs) {
477  OutRegs.insert(RegMaskPair.RegUnit);
478  }
479  return OutRegs;
480  };
481 
482 private:
483  void topologicalSort();
484  // After scheduling is done, improve low latency placements.
485  void moveLowLatencies();
486 
487 public:
488  // Some stats for scheduling inside blocks.
489  std::vector<unsigned> IsLowLatencySU;
490  std::vector<unsigned> LowLatencyOffset;
491  std::vector<unsigned> IsHighLatencySU;
492  // Topological sort
493  // Maps topological index to the node number.
494  std::vector<int> TopDownIndex2SU;
495  std::vector<int> BottomUpIndex2SU;
496 };
497 
498 } // end namespace llvm
499 
500 #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINESCHEDULER_H
llvm::ScheduleDAG::MRI
MachineRegisterInfo & MRI
Virtual/real register map.
Definition: ScheduleDAG.h:561
llvm::SIScheduleBlocks::TopDownIndex2Block
std::vector< int > TopDownIndex2Block
Definition: SIMachineScheduler.h:213
llvm::SIScheduleDAGMI::SIScheduleDAGMI
SIScheduleDAGMI(MachineSchedContext *C)
Definition: SIMachineScheduler.cpp:1777
llvm::SIScheduleBlocks::Blocks
std::vector< SIScheduleBlock * > Blocks
Definition: SIMachineScheduler.h:212
llvm::SIScheduleBlockCreator::getBlocks
SIScheduleBlocks getBlocks(SISchedulerBlockCreatorVariant BlockVariant)
Definition: SIMachineScheduler.cpp:608
ScheduleDAG.h
llvm::SIScheduleBlockResult::MaxVGPRUsage
unsigned MaxVGPRUsage
Definition: SIMachineScheduler.h:409
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::RegPressureTracker::init
void init(const MachineFunction *mf, const RegisterClassInfo *rci, const LiveIntervals *lis, const MachineBasicBlock *mbb, MachineBasicBlock::const_iterator pos, bool TrackLaneMasks, bool TrackUntiedDefs)
Setup the RegPressureTracker.
Definition: RegisterPressure.cpp:263
llvm::LatenciesAlone
@ LatenciesAlone
Definition: SIMachineScheduler.h:218
llvm::SIScheduleDAGMI::LowLatencyOffset
std::vector< unsigned > LowLatencyOffset
Definition: SIMachineScheduler.h:490
llvm::Latency
@ Latency
Definition: SIMachineScheduler.h:32
llvm::SIScheduleDAGMI::getMRI
MachineRegisterInfo * getMRI()
Definition: SIMachineScheduler.h:453
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::SIScheduleBlock::getID
unsigned getID() const
Definition: SIMachineScheduler.h:108
llvm::SIScheduleDAGMI::IsLowLatencySU
std::vector< unsigned > IsLowLatencySU
Definition: SIMachineScheduler.h:489
llvm::SIScheduleDAGMI::~SIScheduleDAGMI
~SIScheduleDAGMI() override
llvm::NoCand
@ NoCand
Definition: SIMachineScheduler.h:30
llvm::IntervalPressure
RegisterPressure computed within a region of instructions delimited by TopIdx and BottomIdx.
Definition: RegisterPressure.h:68
llvm::ScheduleDAGInstrs::Topo
ScheduleDAGTopologicalSort Topo
Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries.
Definition: ScheduleDAGInstrs.h:241
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:34
llvm::SISchedulerCandidate::Reason
SIScheduleCandReason Reason
Definition: SIMachineScheduler.h:40
llvm::SIScheduleBlock::getInternalAdditionnalRegUsage
std::vector< unsigned > & getInternalAdditionnalRegUsage()
Definition: SIMachineScheduler.h:157
llvm::RegPressureTracker
Track the current register pressure at some position in the instruction stream, and remember the high...
Definition: RegisterPressure.h:358
llvm::SIScheduleBlockCreator::isSUInBlock
bool isSUInBlock(SUnit *SU, unsigned ID)
Definition: SIMachineScheduler.cpp:627
llvm::SIScheduleBlock::getScheduledUnits
std::vector< SUnit * > getScheduledUnits()
Definition: SIMachineScheduler.h:143
llvm::SIScheduleDAGMI::getCurrentTop
MachineBasicBlock::iterator getCurrentTop()
Definition: SIMachineScheduler.h:450
llvm::ScheduleDAGMI::CurrentBottom
MachineBasicBlock::iterator CurrentBottom
The bottom of the unscheduled zone.
Definition: MachineScheduler.h:279
llvm::SIScheduleDAGMI::fillVgprSgprCost
void fillVgprSgprCost(_Iterator First, _Iterator End, unsigned &VgprUsage, unsigned &SgprUsage)
Definition: SIMachineScheduler.cpp:1880
llvm::SIScheduleDAGMI::BottomUpIndex2SU
std::vector< int > BottomUpIndex2SU
Definition: SIMachineScheduler.h:495
llvm::SIScheduler::~SIScheduler
~SIScheduler()=default
llvm::Data
@ Data
Definition: SIMachineScheduler.h:56
llvm::SIScheduleBlock::SIScheduleBlock
SIScheduleBlock(SIScheduleDAGMI *DAG, SIScheduleBlockCreator *BC, unsigned ID)
Definition: SIMachineScheduler.h:102
RegisterPressure.h
llvm::SIScheduleBlock::fastSchedule
void fastSchedule()
Definition: SIMachineScheduler.cpp:269
llvm::SIScheduleDAGMI::restoreSULinksLeft
void restoreSULinksLeft()
Definition: SIMachineScheduler.cpp:1868
llvm::SIScheduleBlockScheduler::SIScheduleBlockScheduler
SIScheduleBlockScheduler(SIScheduleDAGMI *DAG, SISchedulerBlockSchedulerVariant Variant, SIScheduleBlocks BlocksStruct)
Definition: SIMachineScheduler.cpp:1422
llvm::SIScheduleDAGMI::IsHighLatencySU
std::vector< unsigned > IsHighLatencySU
Definition: SIMachineScheduler.h:491
llvm::ScheduleDAGTopologicalSort
This class can compute a topological ordering for SUnits and provides methods for dynamically updatin...
Definition: ScheduleDAG.h:694
llvm::RegUsage
@ RegUsage
Definition: SIMachineScheduler.h:31
llvm::SIScheduleBlock::schedule
void schedule(MachineBasicBlock::iterator BeginBlock, MachineBasicBlock::iterator EndBlock)
Definition: SIMachineScheduler.cpp:379
llvm::NodeOrder
@ NodeOrder
Definition: SIMachineScheduler.h:35
llvm::SISchedulerBlockSchedulerVariant
SISchedulerBlockSchedulerVariant
Definition: SIMachineScheduler.h:313
llvm::SIScheduleBlockScheduler::getVGPRUsage
unsigned getVGPRUsage()
Definition: SIMachineScheduler.h:354
llvm::SIScheduleDAGMI::getEntrySU
SUnit & getEntrySU()
Definition: SIMachineScheduler.h:456
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::SISchedulerBlockCreatorVariant
SISchedulerBlockCreatorVariant
Definition: SIMachineScheduler.h:217
llvm::SIScheduleBlockScheduler::getBlocks
std::vector< SIScheduleBlock * > getBlocks()
Definition: SIMachineScheduler.h:352
llvm::SIScheduleDAGMI::getBB
MachineBasicBlock * getBB()
Definition: SIMachineScheduler.h:449
llvm::RegisterPressure::LiveOutRegs
SmallVector< RegisterMaskPair, 8 > LiveOutRegs
Definition: RegisterPressure.h:54
llvm::SIScheduleDAGMI::getOutRegs
std::set< unsigned > getOutRegs()
Definition: SIMachineScheduler.h:474
llvm::LatenciesGrouped
@ LatenciesGrouped
Definition: SIMachineScheduler.h:219
llvm::SIScheduleDAGMI::schedule
void schedule() override
Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.
Definition: SIMachineScheduler.cpp:1899
llvm::SIScheduleBlock::addUnit
void addUnit(SUnit *SU)
Functions for Block construction.
Definition: SIMachineScheduler.cpp:178
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:29
llvm::SISchedulerCandidate::isRepeat
bool isRepeat(SIScheduleCandReason R)
Definition: SIMachineScheduler.h:47
llvm::SISchedulerCandidate
Definition: SIMachineScheduler.h:38
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::ScheduleDAGMILive::RPTracker
RegPressureTracker RPTracker
Definition: MachineScheduler.h:408
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::ScheduleDAGMILive::RegClassInfo
RegisterClassInfo * RegClassInfo
Definition: MachineScheduler.h:387
llvm::BlockRegUsage
@ BlockRegUsage
Definition: SIMachineScheduler.h:316
llvm::ScheduleDAGMI::LIS
LiveIntervals * LIS
Definition: MachineScheduler.h:269
llvm::SIScheduleDAGMI::getTRI
const TargetRegisterInfo * getTRI()
Definition: SIMachineScheduler.h:454
llvm::SIScheduleBlock::addPred
void addPred(SIScheduleBlock *Pred)
Definition: SIMachineScheduler.cpp:518
llvm::SIScheduleDAGMI::getExitSU
SUnit & getExitSU()
Definition: SIMachineScheduler.h:457
llvm::SISchedulerCandidate::RepeatReasonSet
uint32_t RepeatReasonSet
Definition: SIMachineScheduler.h:43
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:120
llvm::SIScheduleBlock::getPreds
const std::vector< SIScheduleBlock * > & getPreds() const
Definition: SIMachineScheduler.h:120
llvm::SIScheduleBlockResult::MaxSGPRUsage
unsigned MaxSGPRUsage
Definition: SIMachineScheduler.h:408
llvm::SIScheduleBlock::~SIScheduleBlock
~SIScheduleBlock()=default
llvm::SIScheduleBlockResult::SUs
std::vector< unsigned > SUs
Definition: SIMachineScheduler.h:407
llvm::SIScheduleBlock
Definition: SIMachineScheduler.h:59
llvm::SIScheduleBlock::getNumHighLatencySuccessors
unsigned getNumHighLatencySuccessors() const
Definition: SIMachineScheduler.h:127
llvm::RegPressureTracker::getPressure
RegisterPressure & getPressure()
Get the resulting register pressure over the traversed region.
Definition: RegisterPressure.h:459
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::RegisterPressure::LiveInRegs
SmallVector< RegisterMaskPair, 8 > LiveInRegs
List of live in virtual registers or physical register units.
Definition: RegisterPressure.h:53
llvm::SIScheduleBlock::addSucc
void addSucc(SIScheduleBlock *Succ, SIScheduleBlockLinkKind Kind)
Definition: SIMachineScheduler.cpp:536
llvm::SISchedulerCandidate::SISchedulerCandidate
SISchedulerCandidate()=default
llvm::SIScheduleDAGMI::getLIS
LiveIntervals * getLIS()
Definition: SIMachineScheduler.h:452
llvm::LatenciesAlonePlusConsecutive
@ LatenciesAlonePlusConsecutive
Definition: SIMachineScheduler.h:220
llvm::SIScheduleDAGMI
Definition: SIMachineScheduler.h:426
llvm::SIScheduleBlock::printDebug
void printDebug(bool Full)
Definition: SIMachineScheduler.cpp:559
llvm::NoData
@ NoData
Definition: SIMachineScheduler.h:55
llvm::SIScheduleBlocks
Definition: SIMachineScheduler.h:211
llvm::SIScheduleBlock::getOutRegs
std::set< unsigned > & getOutRegs()
Definition: SIMachineScheduler.h:162
llvm::ScheduleDAG::TRI
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:559
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::ScheduleDAG::MF
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:560
llvm::SIScheduleBlock::isScheduled
bool isScheduled()
Definition: SIMachineScheduler.h:153
uint32_t
llvm::SIScheduler
Definition: SIMachineScheduler.h:412
llvm::ScheduleDAG::EntrySU
SUnit EntrySU
Special node for the region entry.
Definition: ScheduleDAG.h:563
llvm::ScheduleDAGMI::CurrentTop
MachineBasicBlock::iterator CurrentTop
The top of the unscheduled zone.
Definition: MachineScheduler.h:276
llvm::SIScheduleBlockLinkKind
SIScheduleBlockLinkKind
Definition: SIMachineScheduler.h:54
llvm::SIScheduleBlockCreator
Definition: SIMachineScheduler.h:223
llvm::SIScheduleBlock::Height
unsigned Height
Definition: SIMachineScheduler.h:124
llvm::SIScheduleBlockScheduler
Definition: SIMachineScheduler.h:319
llvm::SIScheduler::scheduleVariant
struct SIScheduleBlockResult scheduleVariant(SISchedulerBlockCreatorVariant BlockVariant, SISchedulerBlockSchedulerVariant ScheduleVariant)
Definition: SIMachineScheduler.cpp:1753
llvm::SIScheduleDAGMI::getInRegs
std::set< unsigned > getInRegs()
Definition: SIMachineScheduler.h:466
llvm::SIScheduleBlockResult
Definition: SIMachineScheduler.h:406
llvm::SISchedulerCandidate::setRepeat
void setRepeat(SIScheduleCandReason R)
Definition: SIMachineScheduler.h:48
llvm::ScheduleDAGInstrs::RegionBegin
MachineBasicBlock::iterator RegionBegin
The beginning of the range to be scheduled.
Definition: ScheduleDAGInstrs.h:148
llvm::SIScheduleBlock::finalizeUnits
void finalizeUnits()
Definition: SIMachineScheduler.cpp:507
llvm::Successor
@ Successor
Definition: SIMachineScheduler.h:33
llvm::SIScheduleBlockCreator::SIScheduleBlockCreator
SIScheduleBlockCreator(SIScheduleDAGMI *DAG)
Definition: SIMachineScheduler.cpp:604
llvm::BlockRegUsageLatency
@ BlockRegUsageLatency
Definition: SIMachineScheduler.h:315
llvm::SIScheduleBlock::isHighLatencyBlock
bool isHighLatencyBlock()
Definition: SIMachineScheduler.h:131
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::SIScheduleDAGMI::initRPTracker
void initRPTracker(RegPressureTracker &RPTracker)
Definition: SIMachineScheduler.h:445
llvm::SIInstrInfo
Definition: SIInstrInfo.h:38
llvm::ScheduleDAGInstrs::BB
MachineBasicBlock * BB
The block in which to insert instructions.
Definition: ScheduleDAGInstrs.h:145
llvm::SIScheduleCandReason
SIScheduleCandReason
Definition: SIMachineScheduler.h:29
llvm::SIScheduleDAGMI::getCurrentBottom
MachineBasicBlock::iterator getCurrentBottom()
Definition: SIMachineScheduler.h:451
llvm::SIScheduleDAGMI::GetTopo
ScheduleDAGTopologicalSort * GetTopo()
Definition: SIMachineScheduler.h:455
llvm::SIScheduleBlockScheduler::~SIScheduleBlockScheduler
~SIScheduleBlockScheduler()=default
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:216
MachineScheduler.h
llvm::SIScheduleBlockScheduler::getSGPRUsage
unsigned getSGPRUsage()
Definition: SIMachineScheduler.h:355
llvm::SIScheduler::SIScheduler
SIScheduler(SIScheduleDAGMI *DAG)
Definition: SIMachineScheduler.h:417
llvm::SIScheduleBlock::getSuccs
ArrayRef< std::pair< SIScheduleBlock *, SIScheduleBlockLinkKind > > getSuccs() const
Definition: SIMachineScheduler.h:122
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::BlockLatencyRegUsage
@ BlockLatencyRegUsage
Definition: SIMachineScheduler.h:314
llvm::SIScheduleDAGMI::TopDownIndex2SU
std::vector< int > TopDownIndex2SU
Definition: SIMachineScheduler.h:494
llvm::SIScheduleBlock::getCost
int getCost()
Definition: SIMachineScheduler.h:136
llvm::SIScheduleBlocks::TopDownBlock2Index
std::vector< int > TopDownBlock2Index
Definition: SIMachineScheduler.h:214
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:385
llvm::SIScheduleBlock::Depth
unsigned Depth
Definition: SIMachineScheduler.h:125
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::ScheduleDAG::ExitSU
SUnit ExitSU
Special node for the region exit.
Definition: ScheduleDAG.h:564
llvm::SIScheduleBlock::getInRegs
std::set< unsigned > & getInRegs()
Definition: SIMachineScheduler.h:161
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38