85 if (&Subtarget == &NewSubtarget)
88 Names2InstrOpCodes.
clear();
90 Names2RegMasks.
clear();
91 Names2SubRegIndices.
clear();
92 Names2TargetIndices.
clear();
93 Names2DirectTargetFlags.
clear();
94 Names2BitmaskTargetFlags.
clear();
95 Names2MMOTargetFlags.
clear();
97 initNames2RegClasses();
101void PerTargetMIParsingState::initNames2Regs() {
102 if (!Names2Regs.empty())
106 Names2Regs.insert(std::make_pair(
"noreg", 0));
108 assert(
TRI &&
"Expected target register info");
110 for (
unsigned I = 0,
E =
TRI->getNumRegs();
I <
E; ++
I) {
115 assert(WasInserted &&
"Expected registers to be unique case-insensitively");
122 auto RegInfo = Names2Regs.find(
RegName);
123 if (RegInfo == Names2Regs.end())
125 Reg = RegInfo->getValue();
129void PerTargetMIParsingState::initNames2InstrOpCodes() {
130 if (!Names2InstrOpCodes.
empty())
133 assert(
TII &&
"Expected target instruction info");
134 for (
unsigned I = 0,
E =
TII->getNumOpcodes();
I <
E; ++
I)
140 initNames2InstrOpCodes();
148void PerTargetMIParsingState::initNames2RegMasks() {
149 if (!Names2RegMasks.
empty())
152 assert(
TRI &&
"Expected target register info");
156 for (
size_t I = 0,
E = RegMasks.
size();
I <
E; ++
I)
158 std::make_pair(
StringRef(RegMaskNames[
I]).lower(), RegMasks[
I]));
162 initNames2RegMasks();
163 auto RegMaskInfo = Names2RegMasks.
find(Identifier);
164 if (RegMaskInfo == Names2RegMasks.
end())
166 return RegMaskInfo->getValue();
169void PerTargetMIParsingState::initNames2SubRegIndices() {
170 if (!Names2SubRegIndices.
empty())
173 for (
unsigned I = 1,
E =
TRI->getNumSubRegIndices();
I <
E; ++
I)
174 Names2SubRegIndices.
insert(
175 std::make_pair(
TRI->getSubRegIndexName(
I),
I));
179 initNames2SubRegIndices();
180 auto SubRegInfo = Names2SubRegIndices.
find(
Name);
181 if (SubRegInfo == Names2SubRegIndices.
end())
183 return SubRegInfo->getValue();
186void PerTargetMIParsingState::initNames2TargetIndices() {
187 if (!Names2TargetIndices.
empty())
190 assert(
TII &&
"Expected target instruction info");
191 auto Indices =
TII->getSerializableTargetIndices();
192 for (
const auto &
I : Indices)
197 initNames2TargetIndices();
198 auto IndexInfo = Names2TargetIndices.
find(
Name);
199 if (IndexInfo == Names2TargetIndices.
end())
201 Index = IndexInfo->second;
205void PerTargetMIParsingState::initNames2DirectTargetFlags() {
206 if (!Names2DirectTargetFlags.
empty())
210 assert(
TII &&
"Expected target instruction info");
212 for (
const auto &
I : Flags)
213 Names2DirectTargetFlags.
insert(
219 initNames2DirectTargetFlags();
220 auto FlagInfo = Names2DirectTargetFlags.
find(
Name);
221 if (FlagInfo == Names2DirectTargetFlags.
end())
223 Flag = FlagInfo->second;
227void PerTargetMIParsingState::initNames2BitmaskTargetFlags() {
228 if (!Names2BitmaskTargetFlags.
empty())
232 assert(
TII &&
"Expected target instruction info");
234 for (
const auto &
I : Flags)
235 Names2BitmaskTargetFlags.
insert(
241 initNames2BitmaskTargetFlags();
242 auto FlagInfo = Names2BitmaskTargetFlags.
find(
Name);
243 if (FlagInfo == Names2BitmaskTargetFlags.
end())
245 Flag = FlagInfo->second;
249void PerTargetMIParsingState::initNames2MMOTargetFlags() {
250 if (!Names2MMOTargetFlags.
empty())
254 assert(
TII &&
"Expected target instruction info");
255 auto Flags =
TII->getSerializableMachineMemOperandTargetFlags();
256 for (
const auto &
I : Flags)
262 initNames2MMOTargetFlags();
263 auto FlagInfo = Names2MMOTargetFlags.
find(
Name);
264 if (FlagInfo == Names2MMOTargetFlags.
end())
266 Flag = FlagInfo->second;
270void PerTargetMIParsingState::initNames2RegClasses() {
271 if (!Names2RegClasses.
empty())
275 for (
unsigned I = 0,
E =
TRI->getNumRegClasses();
I <
E; ++
I) {
276 const auto *RC =
TRI->getRegClass(
I);
282void PerTargetMIParsingState::initNames2RegBanks() {
283 if (!Names2RegBanks.
empty())
301 auto RegClassInfo = Names2RegClasses.
find(
Name);
302 if (RegClassInfo == Names2RegClasses.
end())
304 return RegClassInfo->getValue();
308 auto RegBankInfo = Names2RegBanks.
find(
Name);
309 if (RegBankInfo == Names2RegBanks.
end())
311 return RegBankInfo->getValue();
316 : MF(MF), SM(&SM), IRSlots(IRSlots),
Target(
T) {
320 auto I =
VRegInfos.insert(std::make_pair(Num,
nullptr));
324 Info->VReg =
MRI.createIncompleteVirtualRegister();
325 I.first->second =
Info;
327 return *
I.first->second;
337 I.first->second =
Info;
339 return *
I.first->second;
347 Slots2Values.
insert(std::make_pair(
unsigned(Slot), V));
355 for (
const auto &
Arg :
F.args())
357 for (
const auto &BB :
F) {
359 for (
const auto &
I : BB)
374struct ParsedMachineOperand {
378 std::optional<unsigned> TiedDefIdx;
382 std::optional<unsigned> &TiedDefIdx)
383 : Operand(Operand), Begin(Begin), End(End), TiedDefIdx(TiedDefIdx) {
386 "Only used register operands can be tied");
408 void lex(
unsigned SkipChar = 0);
422 bool parseBasicBlocks();
428 bool parseStandaloneStackObject(
int &FI);
431 bool parseMDTuple(
MDNode *&MD,
bool IsDistinct);
446 bool parseRegisterFlag(
unsigned &
Flags);
448 bool parseSubRegisterIndex(
unsigned &
SubReg);
449 bool parseRegisterTiedDefIndex(
unsigned &TiedDefIdx);
451 std::optional<unsigned> &TiedDefIdx,
462 bool parseStackFrameIndex(
int &FI);
464 bool parseFixedStackFrameIndex(
int &FI);
474 bool parseDIExpression(
MDNode *&Expr);
475 bool parseDILocation(
MDNode *&Expr);
477 bool parseCFIOffset(
int &
Offset);
480 bool parseCFIEscapeValues(std::string& Values);
491 bool parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
493 std::optional<unsigned> &TiedDefIdx);
494 bool parseMachineOperandAndTargetFlags(
const unsigned OpCode,
495 const unsigned OpIdx,
497 std::optional<unsigned> &TiedDefIdx);
498 bool parseOffset(int64_t &
Offset);
499 bool parseIRBlockAddressTaken(
BasicBlock *&BB);
500 bool parseAlignment(
uint64_t &Alignment);
501 bool parseAddrspace(
unsigned &Addrspace);
502 bool parseSectionID(std::optional<MBBSectionID> &SID);
503 bool parseBBID(std::optional<unsigned> &BBID);
512 bool parsePreOrPostInstrSymbol(
MCSymbol *&Symbol);
516 bool parseTargetImmMnemonic(
const unsigned OpCode,
const unsigned OpIdx,
544 bool parseInstruction(
unsigned &OpCode,
unsigned &
Flags);
560 bool parseStringConstant(std::string &Result);
577 SourceRange(SourceRange), PFS(PFS) {}
579void MIParser::lex(
unsigned SkipChar) {
585bool MIParser::error(
const Twine &Msg) {
return error(Token.location(), Msg); }
600 Source, std::nullopt, std::nullopt);
605 assert(SourceRange.isValid() &&
"Invalid source range");
627 return "<unknown token>";
632 if (Token.isNot(TokenKind))
639 if (Token.isNot(TokenKind))
646bool MIParser::parseSectionID(std::optional<MBBSectionID> &SID) {
652 return error(
"Unknown Section ID");
655 const StringRef &S = Token.stringValue();
656 if (S ==
"Exception")
658 else if (S ==
"Cold")
661 return error(
"Unknown Section ID");
668bool MIParser::parseBBID(std::optional<unsigned> &BBID) {
673 return error(
"Unknown BB ID");
679bool MIParser::parseBasicBlockDefinition(
685 auto Loc = Token.location();
686 auto Name = Token.stringValue();
688 bool MachineBlockAddressTaken =
false;
690 bool IsLandingPad =
false;
691 bool IsInlineAsmBrIndirectTarget =
false;
692 bool IsEHFuncletEntry =
false;
693 std::optional<MBBSectionID> SectionID;
695 std::optional<unsigned> BBID;
700 switch (Token.kind()) {
702 MachineBlockAddressTaken =
true;
706 if (parseIRBlockAddressTaken(AddressTakenIRBlock))
714 IsInlineAsmBrIndirectTarget =
true;
718 IsEHFuncletEntry =
true;
722 if (parseAlignment(Alignment))
728 if (parseIRBlock(BB, MF.getFunction()))
733 if (parseSectionID(SectionID))
751 BB = dyn_cast_or_null<BasicBlock>(
752 MF.getFunction().getValueSymbolTable()->lookup(
Name));
755 "' is not defined in the function '" +
758 auto *
MBB = MF.CreateMachineBasicBlock(BB);
760 bool WasInserted = MBBSlots.
insert(std::make_pair(
ID,
MBB)).second;
762 return error(Loc,
Twine(
"redefinition of machine basic block with id #") +
766 if (MachineBlockAddressTaken)
768 if (AddressTakenIRBlock)
777 if (BBID.has_value()) {
780 if (!MF.hasBBSections())
787bool MIParser::parseBasicBlockDefinitions(
793 if (Token.isErrorOrEOF())
794 return Token.isError();
796 return error(
"expected a basic block definition before instructions");
797 unsigned BraceDepth = 0;
799 if (parseBasicBlockDefinition(MBBSlots))
801 bool IsAfterNewline =
false;
805 Token.isErrorOrEOF())
808 return error(
"basic block definition should be located at the start of "
811 IsAfterNewline =
true;
814 IsAfterNewline =
false;
819 return error(
"extraneous closing brace ('}')");
825 if (!Token.isError() && BraceDepth)
826 return error(
"expected '}'");
827 }
while (!Token.isErrorOrEOF());
828 return Token.isError();
836 if (Token.isNewlineOrEOF())
840 return error(
"expected a named register");
842 if (parseNamedRegister(Reg))
850 return error(
"expected a lane mask");
852 "Use correct get-function for lane mask");
855 return error(
"invalid lane mask value");
869 if (Token.isNewlineOrEOF())
873 return error(
"expected a machine basic block reference");
882 return error(
"expected an integer literal after '('");
916 bool ExplicitSuccessors =
false;
919 if (parseBasicBlockSuccessors(
MBB))
921 ExplicitSuccessors =
true;
923 if (parseBasicBlockLiveins(
MBB))
929 if (!Token.isNewlineOrEOF())
930 return error(
"expected line break at the end of a list");
935 bool IsInBundle =
false;
959 return error(
"nested instruction bundles are not allowed");
968 assert(Token.isNewlineOrEOF() &&
"MI is not fully parsed");
973 if (!ExplicitSuccessors) {
981 AddFalthroughFrom = &
MBB;
990bool MIParser::parseBasicBlocks() {
995 if (Token.isErrorOrEOF())
996 return Token.isError();
1005 if (AddFalthroughFrom) {
1009 AddFalthroughFrom =
nullptr;
1011 if (parseBasicBlock(*
MBB, AddFalthroughFrom))
1024 while (Token.isRegister() || Token.isRegisterFlag()) {
1025 auto Loc = Token.location();
1026 std::optional<unsigned> TiedDefIdx;
1027 if (parseRegisterOperand(MO, TiedDefIdx,
true))
1030 ParsedMachineOperand(MO, Loc, Token.location(), TiedDefIdx));
1038 unsigned OpCode,
Flags = 0;
1039 if (Token.isError() || parseInstruction(OpCode, Flags))
1051 auto Loc = Token.location();
1052 std::optional<unsigned> TiedDefIdx;
1053 if (parseMachineOperandAndTargetFlags(OpCode,
Operands.size(), MO, TiedDefIdx))
1056 ParsedMachineOperand(MO, Loc, Token.location(), TiedDefIdx));
1061 return error(
"expected ',' before the next machine operand");
1065 MCSymbol *PreInstrSymbol =
nullptr;
1067 if (parsePreOrPostInstrSymbol(PreInstrSymbol))
1069 MCSymbol *PostInstrSymbol =
nullptr;
1071 if (parsePreOrPostInstrSymbol(PostInstrSymbol))
1073 MDNode *HeapAllocMarker =
nullptr;
1075 if (parseHeapAllocMarker(HeapAllocMarker))
1077 MDNode *PCSections =
nullptr;
1079 if (parsePCSections(PCSections))
1082 unsigned CFIType = 0;
1086 return error(
"expected an integer literal after 'cfi-type'");
1096 unsigned InstrNum = 0;
1100 return error(
"expected an integer literal after 'debug-instr-number'");
1117 if (parseDILocation(
Node))
1120 return error(
"expected a metadata node after 'debug-location'");
1121 if (!isa<DILocation>(
Node))
1122 return error(
"referenced metadata is not a DILocation");
1130 while (!Token.isNewlineOrEOF()) {
1132 if (parseMachineMemoryOperand(
MemOp))
1135 if (Token.isNewlineOrEOF())
1138 return error(
"expected ',' before the next machine memory operand");
1143 const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
1144 if (!MCID.isVariadic()) {
1146 if (verifyImplicitOperands(
Operands, MCID))
1150 MI = MF.CreateMachineInstr(MCID, DebugLocation,
true);
1151 MI->setFlags(Flags);
1153 unsigned NumExplicitOps = 0;
1154 for (
const auto &Operand :
Operands) {
1155 bool IsImplicitOp = Operand.Operand.isReg() && Operand.Operand.isImplicit();
1156 if (!IsImplicitOp) {
1157 if (!MCID.isVariadic() && NumExplicitOps >= MCID.getNumOperands() &&
1158 !Operand.Operand.isValidExcessOperand())
1159 return error(Operand.Begin,
"too many operands for instruction");
1164 MI->addOperand(MF, Operand.Operand);
1170 MI->setPreInstrSymbol(MF, PreInstrSymbol);
1171 if (PostInstrSymbol)
1172 MI->setPostInstrSymbol(MF, PostInstrSymbol);
1173 if (HeapAllocMarker)
1174 MI->setHeapAllocMarker(MF, HeapAllocMarker);
1176 MI->setPCSections(MF, PCSections);
1178 MI->setCFIType(MF, CFIType);
1179 if (!MemOperands.
empty())
1180 MI->setMemRefs(MF, MemOperands);
1182 MI->setDebugInstrNum(InstrNum);
1189 return error(
"expected a machine basic block reference");
1195 "expected end of string after the machine basic block reference");
1199bool MIParser::parseStandaloneNamedRegister(
Register &Reg) {
1202 return error(
"expected a named register");
1203 if (parseNamedRegister(Reg))
1207 return error(
"expected end of string after the register reference");
1211bool MIParser::parseStandaloneVirtualRegister(
VRegInfo *&Info) {
1214 return error(
"expected a virtual register");
1215 if (parseVirtualRegister(Info))
1219 return error(
"expected end of string after the register reference");
1223bool MIParser::parseStandaloneRegister(
Register &Reg) {
1227 return error(
"expected either a named or virtual register");
1230 if (parseRegister(Reg, Info))
1235 return error(
"expected end of string after the register reference");
1239bool MIParser::parseStandaloneStackObject(
int &FI) {
1242 return error(
"expected a stack object");
1243 if (parseStackFrameIndex(FI))
1246 return error(
"expected end of string after the stack object reference");
1250bool MIParser::parseStandaloneMDNode(
MDNode *&
Node) {
1256 if (parseDIExpression(
Node))
1259 if (parseDILocation(
Node))
1262 return error(
"expected a metadata node");
1264 return error(
"expected end of string after the metadata node");
1268bool MIParser::parseMachineMetadata() {
1271 return error(
"expected a metadata node");
1275 return error(
"expected metadata id after '!'");
1286 return error(
"expected a metadata node");
1290 if (parseMDTuple(MD, IsDistinct))
1293 auto FI = PFS.MachineForwardRefMDNodes.find(
ID);
1294 if (FI != PFS.MachineForwardRefMDNodes.end()) {
1296 PFS.MachineForwardRefMDNodes.erase(FI);
1298 assert(PFS.MachineMetadataNodes[
ID] == MD &&
"Tracking VH didn't work");
1300 if (PFS.MachineMetadataNodes.count(
ID))
1301 return error(
"Metadata id is already used");
1302 PFS.MachineMetadataNodes[
ID].reset(MD);
1308bool MIParser::parseMDTuple(
MDNode *&MD,
bool IsDistinct) {
1310 if (parseMDNodeVector(Elts))
1319 return error(
"expected '{' here");
1340 return error(
"expected end of metadata node");
1348bool MIParser::parseMetadata(
Metadata *&MD) {
1350 return error(
"expected '!' here");
1355 if (parseStringConstant(Str))
1362 return error(
"expected metadata id after '!'");
1364 SMLoc Loc = mapSMLoc(Token.location());
1371 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(
ID);
1372 if (NodeInfo != PFS.IRSlots.MetadataNodes.end()) {
1373 MD = NodeInfo->second.get();
1377 NodeInfo = PFS.MachineMetadataNodes.find(
ID);
1378 if (NodeInfo != PFS.MachineMetadataNodes.end()) {
1379 MD = NodeInfo->second.get();
1383 auto &FwdRef = PFS.MachineForwardRefMDNodes[
ID];
1384 FwdRef = std::make_pair(
1386 PFS.MachineMetadataNodes[
ID].reset(FwdRef.first.get());
1387 MD = FwdRef.first.get();
1394 return MO.
isDef() ?
"implicit-def" :
"implicit";
1399 assert(Reg.isPhysical() &&
"expected phys reg");
1427 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
1428 assert(
TRI &&
"Expected target register info");
1429 for (
const auto &
I : ImplicitOperands) {
1433 Twine(
"missing implicit register operand '") +
1440bool MIParser::parseInstruction(
unsigned &OpCode,
unsigned &Flags) {
1486 return error(
"expected a machine instruction");
1487 StringRef InstrName = Token.stringValue();
1488 if (PFS.Target.parseInstrName(InstrName, OpCode))
1489 return error(
Twine(
"unknown machine instruction name '") + InstrName +
"'");
1494bool MIParser::parseNamedRegister(
Register &Reg) {
1497 if (PFS.Target.getRegisterByName(
Name, Reg))
1502bool MIParser::parseNamedVirtualRegister(
VRegInfo *&Info) {
1507 Info = &PFS.getVRegInfoNamed(
Name);
1511bool MIParser::parseVirtualRegister(
VRegInfo *&Info) {
1513 return parseNamedVirtualRegister(Info);
1518 Info = &PFS.getVRegInfo(
ID);
1523 switch (Token.kind()) {
1528 return parseNamedRegister(Reg);
1531 if (parseVirtualRegister(Info))
1543 return error(
"expected '_', register class, or register bank name");
1558 return error(Loc,
Twine(
"conflicting register classes, previously: ") +
1567 return error(Loc,
"register class specification on generic register");
1575 RegBank = PFS.Target.getRegBank(
Name);
1577 return error(Loc,
"expected '_', register class, or register bank name");
1588 return error(Loc,
"conflicting generic register banks");
1594 return error(Loc,
"register bank specification on normal register");
1599bool MIParser::parseRegisterFlag(
unsigned &Flags) {
1600 const unsigned OldFlags =
Flags;
1601 switch (Token.kind()) {
1635 if (OldFlags == Flags)
1638 return error(
"duplicate '" + Token.stringValue() +
"' register flag");
1643bool MIParser::parseSubRegisterIndex(
unsigned &
SubReg) {
1647 return error(
"expected a subregister index after '.'");
1648 auto Name = Token.stringValue();
1651 return error(
Twine(
"use of unknown subregister index '") +
Name +
"'");
1656bool MIParser::parseRegisterTiedDefIndex(
unsigned &TiedDefIdx) {
1660 return error(
"expected an integer literal after 'tied-def'");
1677 unsigned DefIdx = *
Operands[
I].TiedDefIdx;
1680 Twine(
"use of invalid tied-def operand index '" +
1681 Twine(DefIdx) +
"'; instruction has only ") +
1683 const auto &DefOperand =
Operands[DefIdx].Operand;
1684 if (!DefOperand.isReg() || !DefOperand.isDef())
1687 Twine(
"use of invalid tied-def operand index '") +
1688 Twine(DefIdx) +
"'; the operand #" +
Twine(DefIdx) +
1689 " isn't a defined register");
1691 for (
const auto &TiedPair : TiedRegisterPairs) {
1692 if (TiedPair.first == DefIdx)
1694 Twine(
"the tied-def operand #") +
Twine(DefIdx) +
1695 " is already tied with another register operand");
1697 TiedRegisterPairs.push_back(std::make_pair(DefIdx,
I));
1701 for (
const auto &TiedPair : TiedRegisterPairs)
1702 MI.tieOperands(TiedPair.first, TiedPair.second);
1707 std::optional<unsigned> &TiedDefIdx,
1710 while (Token.isRegisterFlag()) {
1711 if (parseRegisterFlag(Flags))
1714 if (!Token.isRegister())
1715 return error(
"expected a register after register flags");
1718 if (parseRegister(Reg,
RegInfo))
1723 if (parseSubRegisterIndex(
SubReg))
1725 if (!
Reg.isVirtual())
1726 return error(
"subregister index expects a virtual register");
1729 if (!
Reg.isVirtual())
1730 return error(
"register class specification expects a virtual register");
1732 if (parseRegisterClassOrBank(*
RegInfo))
1739 if (!parseRegisterTiedDefIndex(
Idx))
1744 if (parseLowLevelType(Token.location(), Ty))
1745 return error(
"expected tied-def or low-level type after '('");
1750 if (
MRI.getType(Reg).isValid() &&
MRI.getType(Reg) != Ty)
1751 return error(
"inconsistent type for generic virtual register");
1754 MRI.setType(Reg, Ty);
1759 if (!
Reg.isVirtual())
1760 return error(
"unexpected type on physical register");
1763 if (parseLowLevelType(Token.location(), Ty))
1769 if (
MRI.getType(Reg).isValid() &&
MRI.getType(Reg) != Ty)
1770 return error(
"inconsistent type for generic virtual register");
1773 MRI.setType(Reg, Ty);
1774 }
else if (
Reg.isVirtual()) {
1780 return error(
"generic virtual registers must have a type");
1785 return error(
"cannot have a killed def operand");
1788 return error(
"cannot have a dead use operand");
1802 const APSInt &
Int = Token.integerValue();
1803 if (
auto SImm =
Int.trySExtValue();
Int.isSigned() && SImm.has_value())
1805 else if (
auto UImm =
Int.tryZExtValue(); !
Int.isSigned() && UImm.has_value())
1808 return error(
"integer literal is too large to be an immediate operand");
1813bool MIParser::parseTargetImmMnemonic(
const unsigned OpCode,
1814 const unsigned OpIdx,
1818 auto Loc = Token.location();
1824 Len += Token.range().size();
1833 Src =
StringRef(Loc, Len + Token.stringValue().size());
1838 ->
bool { return error(Loc, Msg); }))
1850 auto Source = StringValue.
str();
1855 return ErrCB(Loc + Err.getColumnNo(), Err.getMessage());
1861 return ::parseIRConstant(
1862 Loc, StringValue, PFS,
C,
1864 return error(Loc, Msg);
1877 return Size != 0 && isUInt<16>(
Size);
1881 return NumElts != 0 && isUInt<16>(NumElts);
1885 return isUInt<24>(AddrSpace);
1889 if (Token.range().front() ==
's' || Token.range().front() ==
'p') {
1892 return error(
"expected integers after 's'/'p' type character");
1895 if (Token.range().front() ==
's') {
1898 return error(
"invalid size for scalar type");
1903 }
else if (Token.range().front() ==
'p') {
1907 return error(
"invalid address space number");
1917 "expected sN, pA, <M x sN>, or <M x pA> for GlobalISel type");
1921 return error(Loc,
"expected <M x sN> or <M x pA> for vector type");
1922 uint64_t NumElements = Token.integerValue().getZExtValue();
1924 return error(
"invalid number of vector elements");
1929 return error(Loc,
"expected <M x sN> or <M x pA> for vector type");
1932 if (Token.range().front() !=
's' && Token.range().front() !=
'p')
1933 return error(Loc,
"expected <M x sN> or <M x pA> for vector type");
1936 return error(
"expected integers after 's'/'p' type character");
1938 if (Token.range().front() ==
's') {
1941 return error(
"invalid size for scalar type");
1943 }
else if (Token.range().front() ==
'p') {
1947 return error(
"invalid address space number");
1951 return error(Loc,
"expected <M x sN> or <M x pA> for vector type");
1955 return error(Loc,
"expected <M x sN> or <M x pA> for vector type");
1965 if (TypeStr.
front() !=
'i' && TypeStr.
front() !=
's' &&
1966 TypeStr.
front() !=
'p')
1968 "a typed immediate operand should start with one of 'i', 's', or 'p'");
1971 return error(
"expected integers after 'i'/'s'/'p' type character");
1973 auto Loc = Token.location();
1977 !(Token.range() ==
"true" || Token.range() ==
"false"))
1978 return error(
"expected an integer literal");
1988 auto Loc = Token.location();
1992 return error(
"expected a floating point literal");
2003 assert(S[0] ==
'0' && tolower(S[1]) ==
'x');
2005 if (!isxdigit(S[2]))
2008 APInt A(V.size()*4, V, 16);
2012 unsigned NumBits = (
A == 0) ? 32 :
A.getActiveBits();
2023 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2031 if (
A.getBitWidth() > 32)
2032 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2033 Result =
A.getZExtValue();
2039bool MIParser::getUnsigned(
unsigned &Result) {
2040 return ::getUnsigned(
2042 return error(Loc, Msg);
2052 auto MBBInfo = PFS.MBBSlots.find(
Number);
2053 if (MBBInfo == PFS.MBBSlots.end())
2054 return error(
Twine(
"use of undefined machine basic block #") +
2056 MBB = MBBInfo->second;
2059 if (!Token.stringValue().empty() && Token.stringValue() !=
MBB->
getName())
2061 " isn't '" + Token.stringValue() +
"'");
2074bool MIParser::parseStackFrameIndex(
int &FI) {
2079 auto ObjectInfo = PFS.StackObjectSlots.find(
ID);
2080 if (ObjectInfo == PFS.StackObjectSlots.end())
2084 if (
const auto *Alloca =
2085 MF.getFrameInfo().getObjectAllocation(ObjectInfo->second))
2086 Name = Alloca->getName();
2087 if (!Token.stringValue().empty() && Token.stringValue() !=
Name)
2089 "' isn't '" + Token.stringValue() +
"'");
2091 FI = ObjectInfo->second;
2097 if (parseStackFrameIndex(FI))
2103bool MIParser::parseFixedStackFrameIndex(
int &FI) {
2108 auto ObjectInfo = PFS.FixedStackObjectSlots.find(
ID);
2109 if (ObjectInfo == PFS.FixedStackObjectSlots.end())
2110 return error(
Twine(
"use of undefined fixed stack object '%fixed-stack.") +
2113 FI = ObjectInfo->second;
2117bool MIParser::parseFixedStackObjectOperand(
MachineOperand &Dest) {
2119 if (parseFixedStackFrameIndex(FI))
2128 switch (Token.
kind()) {
2133 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '") +
2134 Token.
range() +
"'");
2142 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '@") +
2143 Twine(GVIdx) +
"'");
2153bool MIParser::parseGlobalValue(
GlobalValue *&GV) {
2154 return ::parseGlobalValue(
2157 return error(Loc, Msg);
2167 if (parseOperandsOffset(Dest))
2172bool MIParser::parseConstantPoolIndexOperand(
MachineOperand &Dest) {
2179 return error(
"use of undefined constant '%const." +
Twine(
ID) +
"'");
2182 if (parseOperandsOffset(Dest))
2192 auto JumpTableEntryInfo = PFS.JumpTableSlots.find(
ID);
2193 if (JumpTableEntryInfo == PFS.JumpTableSlots.end())
2194 return error(
"use of undefined jump table '%jump-table." +
Twine(
ID) +
"'");
2202 const char *
Symbol = MF.createExternalSymbolName(Token.stringValue());
2205 if (parseOperandsOffset(Dest))
2215 if (parseOperandsOffset(Dest))
2220bool MIParser::parseSubRegisterIndexOperand(
MachineOperand &Dest) {
2223 unsigned SubRegIndex = PFS.Target.getSubRegIndex(Token.stringValue());
2224 if (SubRegIndex == 0)
2234 auto Loc = Token.location();
2237 return error(
"expected metadata id after '!'");
2241 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(
ID);
2242 if (NodeInfo == PFS.IRSlots.MetadataNodes.end()) {
2243 NodeInfo = PFS.MachineMetadataNodes.find(
ID);
2244 if (NodeInfo == PFS.MachineMetadataNodes.end())
2245 return error(Loc,
"use of undefined metadata '!" +
Twine(
ID) +
"'");
2248 Node = NodeInfo->second.get();
2252bool MIParser::parseDIExpression(
MDNode *&Expr) {
2275 return error(
Twine(
"invalid DWARF op '") + Token.stringValue() +
"'");
2279 Token.integerValue().isSigned())
2280 return error(
"expected unsigned integer");
2282 auto &
U = Token.integerValue();
2298bool MIParser::parseDILocation(
MDNode *&Loc) {
2302 bool HaveLine =
false;
2304 unsigned Column = 0;
2306 MDNode *InlinedAt =
nullptr;
2307 bool ImplicitCode =
false;
2315 if (Token.stringValue() ==
"line") {
2320 Token.integerValue().isSigned())
2321 return error(
"expected unsigned integer");
2322 Line = Token.integerValue().getZExtValue();
2327 if (Token.stringValue() ==
"column") {
2332 Token.integerValue().isSigned())
2333 return error(
"expected unsigned integer");
2334 Column = Token.integerValue().getZExtValue();
2338 if (Token.stringValue() ==
"scope") {
2343 return error(
"expected metadata node");
2344 if (!isa<DIScope>(Scope))
2345 return error(
"expected DIScope node");
2348 if (Token.stringValue() ==
"inlinedAt") {
2356 if (parseDILocation(InlinedAt))
2359 return error(
"expected metadata node");
2360 if (!isa<DILocation>(InlinedAt))
2361 return error(
"expected DILocation node");
2364 if (Token.stringValue() ==
"isImplicitCode") {
2369 return error(
"expected true/false");
2373 if (Token.stringValue() ==
"true")
2374 ImplicitCode =
true;
2375 else if (Token.stringValue() ==
"false")
2376 ImplicitCode =
false;
2378 return error(
"expected true/false");
2383 return error(
Twine(
"invalid DILocation argument '") +
2384 Token.stringValue() +
"'");
2392 return error(
"DILocation requires line number");
2394 return error(
"DILocation requires a scope");
2396 Loc =
DILocation::get(MF.getFunction().getContext(), Line, Column, Scope,
2397 InlinedAt, ImplicitCode);
2407 if (parseDIExpression(
Node))
2414bool MIParser::parseCFIOffset(
int &
Offset) {
2416 return error(
"expected a cfi offset");
2417 if (Token.integerValue().getSignificantBits() > 32)
2418 return error(
"expected a 32 bit integer (the cfi offset is too large)");
2419 Offset = (int)Token.integerValue().getExtValue();
2424bool MIParser::parseCFIRegister(
Register &Reg) {
2426 return error(
"expected a cfi register");
2428 if (parseNamedRegister(LLVMReg))
2430 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
2431 assert(
TRI &&
"Expected target register info");
2432 int DwarfReg =
TRI->getDwarfRegNum(LLVMReg,
true);
2434 return error(
"invalid DWARF register");
2440bool MIParser::parseCFIAddressSpace(
unsigned &
AddressSpace) {
2442 return error(
"expected a cfi address space literal");
2443 if (Token.integerValue().isSigned())
2444 return error(
"expected an unsigned integer (cfi address space)");
2450bool MIParser::parseCFIEscapeValues(std::string &Values) {
2453 return error(
"expected a hexadecimal literal");
2457 if (
Value > UINT8_MAX)
2458 return error(
"expected a 8-bit integer (too large)");
2459 Values.push_back(
static_cast<uint8_t
>(
Value));
2466 auto Kind = Token.kind();
2474 if (parseCFIRegister(Reg))
2489 CFIIndex = MF.addFrameInst(
2493 if (parseCFIRegister(Reg))
2499 if (parseCFIOffset(
Offset))
2505 if (parseCFIOffset(
Offset))
2507 CFIIndex = MF.addFrameInst(
2529 if (parseCFIRegister(Reg))
2537 if (parseCFIRegister(Reg))
2544 parseCFIRegister(Reg2))
2559 if (parseCFIEscapeValues(Values))
2573 switch (Token.kind()) {
2575 BB = dyn_cast_or_null<BasicBlock>(
2576 F.getValueSymbolTable()->lookup(Token.stringValue()));
2578 return error(
Twine(
"use of undefined IR block '") + Token.range() +
"'");
2582 unsigned SlotNumber = 0;
2585 BB =
const_cast<BasicBlock *
>(getIRBlock(SlotNumber,
F));
2587 return error(
Twine(
"use of undefined IR block '%ir-block.") +
2588 Twine(SlotNumber) +
"'");
2604 return error(
"expected a global value");
2608 auto *
F = dyn_cast<Function>(GV);
2610 return error(
"expected an IR function reference");
2616 return error(
"expected an IR block reference");
2617 if (parseIRBlock(BB, *
F))
2623 if (parseOperandsOffset(Dest))
2632 return error(
"expected syntax intrinsic(@llvm.whatever)");
2635 return error(
"expected syntax intrinsic(@llvm.whatever)");
2637 std::string
Name = std::string(Token.stringValue());
2641 return error(
"expected ')' to terminate intrinsic name");
2651 return error(
"unknown intrinsic name");
2663 return error(
"expected syntax intpred(whatever) or floatpred(whatever");
2666 return error(
"whatever");
2689 return error(
"invalid floating-point predicate");
2704 return error(
"invalid integer predicate");
2710 return error(
"predicate should be terminated by ')'.");
2720 return error(
"expected syntax shufflemask(<integer or undef>, ...)");
2727 const APSInt &
Int = Token.integerValue();
2730 return error(
"expected integer constant");
2736 return error(
"shufflemask should be terminated by ')'.");
2748 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2751 return error(
"expected unsigned integer for instruction index");
2752 uint64_t InstrIdx = Token.integerValue().getZExtValue();
2753 assert(InstrIdx <= std::numeric_limits<unsigned>::max() &&
2754 "Instruction reference's instruction index is too large");
2758 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2761 return error(
"expected unsigned integer for operand index");
2762 uint64_t OpIdx = Token.integerValue().getZExtValue();
2763 assert(OpIdx <= std::numeric_limits<unsigned>::max() &&
2764 "Instruction reference's operand index is too large");
2768 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2780 return error(
"expected the name of the target index");
2782 if (PFS.Target.getTargetIndex(Token.stringValue(),
Index))
2783 return error(
"use of undefined target index '" + Token.stringValue() +
"'");
2788 if (parseOperandsOffset(Dest))
2793bool MIParser::parseCustomRegisterMaskOperand(
MachineOperand &Dest) {
2794 assert(Token.stringValue() ==
"CustomRegMask" &&
"Expected a custom RegMask");
2803 return error(
"expected a named register");
2805 if (parseNamedRegister(Reg))
2820bool MIParser::parseLiveoutRegisterMaskOperand(
MachineOperand &Dest) {
2828 return error(
"expected a named register");
2830 if (parseNamedRegister(Reg))
2845bool MIParser::parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
2847 std::optional<unsigned> &TiedDefIdx) {
2848 switch (Token.kind()) {
2863 return parseRegisterOperand(Dest, TiedDefIdx);
2865 return parseImmediateOperand(Dest);
2872 return parseFPImmediateOperand(Dest);
2874 return parseMBBOperand(Dest);
2876 return parseStackObjectOperand(Dest);
2878 return parseFixedStackObjectOperand(Dest);
2881 return parseGlobalAddressOperand(Dest);
2883 return parseConstantPoolIndexOperand(Dest);
2885 return parseJumpTableIndexOperand(Dest);
2887 return parseExternalSymbolOperand(Dest);
2889 return parseMCSymbolOperand(Dest);
2891 return parseSubRegisterIndexOperand(Dest);
2894 return parseMetadataOperand(Dest);
2911 return parseCFIOperand(Dest);
2913 return parseBlockAddressOperand(Dest);
2915 return parseIntrinsicOperand(Dest);
2917 return parseTargetIndexOperand(Dest);
2919 return parseLiveoutRegisterMaskOperand(Dest);
2922 return parsePredicateOperand(Dest);
2924 return parseShuffleMaskOperand(Dest);
2926 return parseDbgInstrRefOperand(Dest);
2930 if (
const auto *RegMask = PFS.Target.getRegMask(Token.stringValue())) {
2934 }
else if (Token.stringValue() ==
"CustomRegMask") {
2935 return parseCustomRegisterMaskOperand(Dest);
2937 return parseTypedImmediateOperand(Dest);
2939 const auto *
TII = MF.getSubtarget().getInstrInfo();
2940 if (
const auto *Formatter =
TII->getMIRFormatter()) {
2941 return parseTargetImmMnemonic(OpCode, OpIdx, Dest, *Formatter);
2947 return error(
"expected a machine operand");
2952bool MIParser::parseMachineOperandAndTargetFlags(
2953 const unsigned OpCode,
const unsigned OpIdx,
MachineOperand &Dest,
2954 std::optional<unsigned> &TiedDefIdx) {
2956 bool HasTargetFlags =
false;
2958 HasTargetFlags =
true;
2963 return error(
"expected the name of the target flag");
2964 if (PFS.Target.getDirectTargetFlag(Token.stringValue(), TF)) {
2965 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), TF))
2966 return error(
"use of undefined target flag '" + Token.stringValue() +
2973 return error(
"expected the name of the target flag");
2974 unsigned BitFlag = 0;
2975 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), BitFlag))
2976 return error(
"use of undefined target flag '" + Token.stringValue() +
2985 auto Loc = Token.location();
2986 if (parseMachineOperand(OpCode, OpIdx, Dest, TiedDefIdx))
2988 if (!HasTargetFlags)
2991 return error(Loc,
"register operands can't have target flags");
2996bool MIParser::parseOffset(int64_t &
Offset) {
3003 return error(
"expected an integer literal after '" + Sign +
"'");
3004 if (Token.integerValue().getSignificantBits() > 64)
3005 return error(
"expected 64-bit integer (too large)");
3006 Offset = Token.integerValue().getExtValue();
3013bool MIParser::parseIRBlockAddressTaken(
BasicBlock *&BB) {
3017 return error(
"expected basic block after 'ir_block_address_taken'");
3019 if (parseIRBlock(BB, MF.getFunction()))
3026bool MIParser::parseAlignment(
uint64_t &Alignment) {
3030 return error(
"expected an integer literal after 'align'");
3031 if (getUint64(Alignment))
3036 return error(
"expected a power-of-2 literal after 'align'");
3041bool MIParser::parseAddrspace(
unsigned &Addrspace) {
3045 return error(
"expected an integer literal after 'addrspace'");
3062 switch (Token.
kind()) {
3068 unsigned SlotNumber = 0;
3096 return ErrCB(Token.
location(),
Twine(
"use of undefined IR value '") + Token.
range() +
"'");
3100bool MIParser::parseIRValue(
const Value *&V) {
3101 return ::parseIRValue(
3103 return error(Loc, Msg);
3107bool MIParser::getUint64(
uint64_t &Result) {
3108 if (Token.hasIntegerValue()) {
3109 if (Token.integerValue().getActiveBits() > 64)
3110 return error(
"expected 64-bit integer (too large)");
3111 Result = Token.integerValue().getZExtValue();
3118 if (
A.getBitWidth() > 64)
3119 return error(
"expected 64-bit integer (too large)");
3126bool MIParser::getHexUint(
APInt &Result) {
3127 return ::getHexUint(Token, Result);
3131 const auto OldFlags =
Flags;
3132 switch (Token.kind()) {
3147 if (PFS.Target.getMMOTargetFlag(Token.stringValue(), TF))
3148 return error(
"use of undefined target MMO flag '" + Token.stringValue() +
3156 if (OldFlags == Flags)
3159 return error(
"duplicate '" + Token.stringValue() +
"' memory operand flag");
3165 switch (Token.kind()) {
3167 PSV = MF.getPSVManager().getStack();
3170 PSV = MF.getPSVManager().getGOT();
3173 PSV = MF.getPSVManager().getJumpTable();
3176 PSV = MF.getPSVManager().getConstantPool();
3180 if (parseFixedStackFrameIndex(FI))
3182 PSV = MF.getPSVManager().getFixedStack(FI);
3188 if (parseStackFrameIndex(FI))
3190 PSV = MF.getPSVManager().getFixedStack(FI);
3196 switch (Token.kind()) {
3202 PSV = MF.getPSVManager().getGlobalValueCallEntry(GV);
3206 PSV = MF.getPSVManager().getExternalSymbolCallEntry(
3207 MF.createExternalSymbolName(Token.stringValue()));
3211 "expected a global value or an external symbol after 'call-entry'");
3216 const auto *
TII = MF.getSubtarget().getInstrInfo();
3217 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3218 if (Formatter->parseCustomPseudoSourceValue(
3219 Token.stringValue(), MF, PFS, PSV,
3221 return error(Loc, Msg);
3225 return error(
"unable to parse target custom pseudo source value");
3241 if (parseMemoryPseudoSourceValue(PSV))
3254 return error(
"expected an IR value reference");
3255 const Value *
V =
nullptr;
3258 if (V && !
V->getType()->isPointerTy())
3259 return error(
"expected a pointer IR value");
3268bool MIParser::parseOptionalScope(
LLVMContext &Context,
3274 return error(
"expected '(' in syncscope");
3277 if (parseStringConstant(SSN))
3282 return error(
"expected ')' in syncscope");
3288bool MIParser::parseOptionalAtomicOrdering(
AtomicOrdering &Order) {
3307 return error(
"expected an atomic scope, ordering or a size specification");
3314 while (Token.isMemoryOperandFlag()) {
3315 if (parseMemoryOperandFlag(Flags))
3319 (Token.stringValue() !=
"load" && Token.stringValue() !=
"store"))
3320 return error(
"expected 'load' or 'store' memory operation");
3321 if (Token.stringValue() ==
"load")
3335 if (parseOptionalScope(MF.getFunction().getContext(), SSID))
3340 if (parseOptionalAtomicOrdering(Order))
3343 if (parseOptionalAtomicOrdering(FailureOrder))
3350 return error(
"expected memory LLT, the size integer literal or 'unknown-size' after "
3351 "memory operation");
3355 if (getUint64(
Size))
3367 if (parseLowLevelType(Token.location(), MemoryType))
3382 if (Token.stringValue() !=
Word)
3386 if (parseMachinePointerInfo(
Ptr))
3394 switch (Token.kind()) {
3398 if (parseAlignment(Alignment))
3400 if (
Ptr.Offset & (Alignment - 1)) {
3405 return error(
"specified alignment is more aligned than offset");
3407 BaseAlignment = Alignment;
3412 if (parseAlignment(BaseAlignment))
3416 if (parseAddrspace(
Ptr.AddrSpace))
3441 return error(
"expected 'align' or '!tbaa' or '!alias.scope' or "
3442 "'!noalias' or '!range'");
3447 Dest = MF.getMachineMemOperand(
Ptr, Flags, MemoryType,
Align(BaseAlignment),
3448 AAInfo, Range, SSID, Order, FailureOrder);
3452bool MIParser::parsePreOrPostInstrSymbol(
MCSymbol *&Symbol) {
3455 "Invalid token for a pre- post-instruction symbol!");
3458 return error(
"expected a symbol after 'pre-instr-symbol'");
3459 Symbol = getOrCreateMCSymbol(Token.stringValue());
3465 return error(
"expected ',' before the next machine operand");
3470bool MIParser::parseHeapAllocMarker(
MDNode *&
Node) {
3472 "Invalid token for a heap alloc marker!");
3476 return error(
"expected a MDNode after 'heap-alloc-marker'");
3481 return error(
"expected ',' before the next machine operand");
3486bool MIParser::parsePCSections(
MDNode *&
Node) {
3488 "Invalid token for a PC sections!");
3492 return error(
"expected a MDNode after 'pcsections'");
3497 return error(
"expected ',' before the next machine operand");
3507 for (
const auto &BB :
F) {
3513 Slots2BasicBlocks.
insert(std::make_pair(
unsigned(Slot), &BB));
3520 return Slots2BasicBlocks.
lookup(Slot);
3523const BasicBlock *MIParser::getIRBlock(
unsigned Slot) {
3524 if (Slots2BasicBlocks.empty())
3530 if (&
F == &MF.getFunction())
3531 return getIRBlock(Slot);
3543 return MF.getContext().getOrCreateSymbol(
Name);
3546bool MIParser::parseStringConstant(std::string &Result) {
3548 return error(
"expected string constant");
3549 Result = std::string(Token.stringValue());
3557 return MIParser(PFS,
Error, Src).parseBasicBlockDefinitions(PFS.
MBBSlots);
3562 return MIParser(PFS,
Error, Src).parseBasicBlocks();
3568 return MIParser(PFS,
Error, Src).parseStandaloneMBB(
MBB);
3574 return MIParser(PFS,
Error, Src).parseStandaloneRegister(Reg);
3580 return MIParser(PFS,
Error, Src).parseStandaloneNamedRegister(Reg);
3586 return MIParser(PFS,
Error, Src).parseStandaloneVirtualRegister(
Info);
3592 return MIParser(PFS,
Error, Src).parseStandaloneStackObject(FI);
3597 return MIParser(PFS,
Error, Src).parseStandaloneMDNode(Node);
3602 return MIParser(PFS,
Error, Src, SrcRange).parseMachineMetadata();
3610 ErrorCallback(Loc, Msg);
3614 return ::parseIRValue(Token, PFS, V, ErrorCallback);
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file defines the StringMap class.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
This file implements a class to represent arbitrary precision integral constant values and operations...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
Atomic ordering constants.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
const HexagonInstrInfo * TII
A common definition of LaneBitmask for use in TableGen and CodeGen.
Implement a low-level type suitable for MachineInstr level instruction selection.
static const char * printImplicitRegisterFlag(const MachineOperand &MO)
static const BasicBlock * getIRBlockFromSlot(unsigned Slot, const DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
static bool parseIRConstant(StringRef::iterator Loc, StringRef StringValue, PerFunctionMIParsingState &PFS, const Constant *&C, ErrorCallbackType ErrCB)
static void initSlots2Values(const Function &F, DenseMap< unsigned, const Value * > &Slots2Values)
Creates the mapping from slot numbers to function's unnamed IR values.
static bool parseIRValue(const MIToken &Token, PerFunctionMIParsingState &PFS, const Value *&V, ErrorCallbackType ErrCB)
static bool verifyScalarSize(uint64_t Size)
static bool getUnsigned(const MIToken &Token, unsigned &Result, ErrorCallbackType ErrCB)
static bool getHexUint(const MIToken &Token, APInt &Result)
static bool verifyVectorElementCount(uint64_t NumElts)
static void mapValueToSlot(const Value *V, ModuleSlotTracker &MST, DenseMap< unsigned, const Value * > &Slots2Values)
static void initSlots2BasicBlocks(const Function &F, DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
function_ref< bool(StringRef::iterator Loc, const Twine &)> ErrorCallbackType
static bool isImplicitOperandIn(const MachineOperand &ImplicitOperand, ArrayRef< ParsedMachineOperand > Operands)
Return true if the parsed machine operands contain a given machine operand.
static bool parseGlobalValue(const MIToken &Token, PerFunctionMIParsingState &PFS, GlobalValue *&GV, ErrorCallbackType ErrCB)
static bool verifyAddrSpace(uint64_t AddrSpace)
mir Rename Register Operands
unsigned const TargetRegisterInfo * TRI
This file provides utility analysis objects describing memory locations.
Module.h This file contains the declarations for the Module class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool parseMetadata(const StringRef &Input, uint64_t &FunctionHash, uint32_t &Attributes)
Parse Input that contains metadata.
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value.
An arbitrary precision integer that knows its signedness.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
static BlockAddress * get(Function *F, BasicBlock *BB)
Return a BlockAddress for the specified function and basic block.
static BranchProbability getRaw(uint32_t N)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
@ ICMP_SLT
signed less than
@ ICMP_SLE
signed less or equal
@ FCMP_OLT
0 1 0 0 True if ordered and less than
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
@ ICMP_UGE
unsigned greater or equal
@ ICMP_UGT
unsigned greater than
@ ICMP_SGT
signed greater than
@ FCMP_ULT
1 1 0 0 True if unordered or less than
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
@ ICMP_ULT
unsigned less than
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
@ ICMP_SGE
signed greater or equal
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
@ ICMP_ULE
unsigned less or equal
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
bool isFPPredicate() const
bool isIntPredicate() const
This is an important base class in LLVM.
A parsed version of the target data layout string in and methods for querying it.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Lightweight error class with error context and mandatory checking.
static Intrinsic::ID lookupIntrinsicID(StringRef Name)
This does the actual lookup of an intrinsic ID which matches the given function name.
ValueSymbolTable * getValueSymbolTable()
getSymbolTable() - Return the symbol table if any, otherwise nullptr.
Module * getParent()
Get the module that this global value is contained inside of...
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
This is an important class for using LLVM in a threaded context.
SyncScope::ID getOrInsertSyncScopeID(StringRef SSN)
getOrInsertSyncScopeID - Maps synchronization scope name to synchronization scope ID.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register)
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register)
.cfi_same_value Current value of Register is the same as in the previous frame.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
static MCCFIInstruction createUndefined(MCSymbol *L, unsigned Register)
.cfi_undefined From now on the previous value of Register can't be restored anymore.
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int Adjustment)
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createRememberState(MCSymbol *L)
.cfi_remember_state Save all current rules for all registers.
static MCCFIInstruction createLLVMDefAspaceCfa(MCSymbol *L, unsigned Register, int Offset, unsigned AddressSpace)
.cfi_llvm_def_aspace_cfa defines the rule for computing the CFA to be the result of evaluating the DW...
static MCCFIInstruction createWindowSave(MCSymbol *L)
.cfi_window_save SPARC register window is saved.
static MCCFIInstruction createRestoreState(MCSymbol *L)
.cfi_restore_state Restore the previously saved state.
static MCCFIInstruction createNegateRAState(MCSymbol *L)
.cfi_negate_ra_state AArch64 negate RA state.
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals, StringRef Comment="")
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction createRelOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_rel_offset Previous value of Register is saved at offset Offset from the current CFA register.
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2)
.cfi_register Previous value of Register1 is saved in register Register2.
Describe properties that are true of each instruction in the target description file.
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
bool isCall() const
Return true if the instruction is a call.
ArrayRef< MCPhysReg > implicit_uses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
void replaceAllUsesWith(Metadata *MD)
RAUW a temporary.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static MDString * get(LLVMContext &Context, StringRef Str)
static MDTuple * getDistinct(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Return a distinct node.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static TempMDTuple getTemporary(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Return a temporary node.
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
void setAddressTakenIRBlock(BasicBlock *BB)
Set this block to reflect that it corresponds to an IR-level basic block with a BlockAddress.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
void setAlignment(Align A)
Set alignment of the basic block.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void setSectionID(MBBSectionID V)
Sets the section ID for this basic block.
void setIsInlineAsmBrIndirectTarget(bool V=true)
Indicates if this is the indirect dest of an INLINEASM_BR.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
void setIsEHFuncletEntry(bool V=true)
Indicates if this is the entry block of an EH funclet.
void setBBID(unsigned V)
Sets the fixed BBID of this basic block.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
void setMachineBlockAddressTaken()
Set this block to indicate that its address is used as something other than the target of a terminato...
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
void setFlag(MIFlag Flag)
Set a MI flag.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
static MachineOperand CreateFPImm(const ConstantFP *CFP)
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static MachineOperand CreateCImm(const ConstantInt *CI)
static MachineOperand CreateMetadata(const MDNode *Meta)
static MachineOperand CreatePredicate(unsigned Pred)
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx)
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
void setTargetFlags(unsigned F)
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
static MachineOperand CreateFI(int Idx)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
This interface provides simple read-only access to a block of memory, and provides simple methods for...
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
const char * getBufferEnd() const
const char * getBufferStart() const
Manage lifetime of a slot tracker for printing IR.
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
void incorporateFunction(const Function &F)
Incorporate the given function.
A Module instance is used to store all the information related to an LLVM module.
Special value supplied for machine level alias analysis.
Holds all the information related to register banks.
unsigned getNumRegBanks() const
Get the total number of register banks.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a location in source code.
static SMLoc getFromPointer(const char *Ptr)
Represents a range in source code.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This owns the files read by a parser, handles include stacks, and handles diagnostic wrangling.
unsigned getMainFileID() const
const MemoryBuffer * getMemoryBuffer(unsigned i) const
SMDiagnostic GetMessage(SMLoc Loc, DiagKind Kind, const Twine &Msg, ArrayRef< SMRange > Ranges={}, ArrayRef< SMFixIt > FixIts={}) const
Return an SMDiagnostic at the specified location with the specified string.
iterator find(StringRef Key)
bool insert(MapEntryTy *KeyValue)
insert - Insert the specified key/value pair into the map.
StringRef - Represent a constant reference to a string, i.e.
std::string str() const
str - Get the contents as an std::string.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
StringRef drop_front(size_t N=1) const
Return a StringRef equal to 'this' but with the first N elements dropped.
constexpr size_t size() const
size - Get the string size.
char front() const
front - Get the first character in the string.
std::string lower() const
static constexpr size_t npos
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
TargetIntrinsicInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Target - Wrapper for Target specific information.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Value * lookup(StringRef Name) const
This method finds the value with the given Name in the the symbol table.
LLVM Value Representation.
An efficient, type-erasing, non-owning reference to a callable.
unsigned getOperationEncoding(StringRef OperationEncodingString)
unsigned getAttributeEncoding(StringRef EncodingString)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const CustomOperand< const MCSubtargetInfo & > Msg[]
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Debug
Register 'use' is for debugging purpose.
@ Renamable
Register that may be renamed.
@ Define
Register definition.
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
@ EarlyClobber
Register definition happens before uses.
@ System
Synchronized with respect to all concurrently executing threads.
Reg
All possible values of the reg field in the ModR/M byte.
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
support::ulittle32_t Word
Scope
Defines the scope in which this symbol should be visible: Default – Visible in the public interface o...
This is an optimization pass for GlobalISel generic memory operations.
bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI, StringRef Src, SMDiagnostic &Error)
bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src, SMDiagnostic &Error)
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
StringRef lexMIToken(StringRef Source, MIToken &Token, function_ref< void(StringRef::iterator, const Twine &)> ErrorCallback)
Consume a single machine instruction token in the given source and return the remaining source string...
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine basic block definitions, and skip the machine instructions.
void guessSuccessors(const MachineBasicBlock &MBB, SmallVectorImpl< MachineBasicBlock * > &Result, bool &IsFallthrough)
Determine a possible list of successors of a basic block based on the basic block machine operand bei...
bool parseMBBReference(PerFunctionMIParsingState &PFS, MachineBasicBlock *&MBB, StringRef Src, SMDiagnostic &Error)
uint64_t PowerOf2Ceil(uint64_t A)
Returns the power of two which is greater than or equal to the given value.
AtomicOrdering
Atomic ordering for LLVM's memory model.
bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine instructions.
bool parseRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
Constant * parseConstantValue(StringRef Asm, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots=nullptr)
Parse a type and a constant value in the given string.
bool parseMachineMetadata(PerFunctionMIParsingState &PFS, StringRef Src, SMRange SourceRange, SMDiagnostic &Error)
bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS, VRegInfo *&Info, StringRef Src, SMDiagnostic &Error)
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * Scope
The tag for alias scope specification (used with noalias).
MDNode * TBAA
The tag for type-based alias analysis.
MDNode * NoAlias
The tag specifying the noalias scope.
This struct is a compact representation of a valid (non-zero power of two) alignment.
static constexpr LaneBitmask getAll()
static const MBBSectionID ExceptionSectionID
static const MBBSectionID ColdSectionID
A token produced by the machine instruction lexer.
bool hasIntegerValue() const
bool is(TokenKind K) const
StringRef stringValue() const
Return the token's string value.
@ kw_cfi_aarch64_negate_ra_sign_state
@ kw_cfi_llvm_def_aspace_cfa
@ kw_inlineasm_br_indirect_target
@ kw_cfi_def_cfa_register
@ kw_cfi_adjust_cfa_offset
@ kw_machine_block_address_taken
@ kw_ir_block_address_taken
StringRef::iterator location() const
const APSInt & integerValue() const
This class contains a discriminated union of information about pointers in memory operands,...
VRegInfo & getVRegInfo(Register Num)
const SlotMapping & IRSlots
const Value * getIRValue(unsigned Slot)
DenseMap< unsigned, MachineBasicBlock * > MBBSlots
StringMap< VRegInfo * > VRegInfosNamed
DenseMap< unsigned, const Value * > Slots2Values
Maps from slot numbers to function's unnamed values.
PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM, const SlotMapping &IRSlots, PerTargetMIParsingState &Target)
DenseMap< Register, VRegInfo * > VRegInfos
VRegInfo & getVRegInfoNamed(StringRef RegName)
BumpPtrAllocator Allocator
bool getDirectTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a direct target flag to the corresponding target flag.
const RegisterBank * getRegBank(StringRef Name)
Check if the given identifier is a name of a register bank.
bool parseInstrName(StringRef InstrName, unsigned &OpCode)
Try to convert an instruction name to an opcode.
unsigned getSubRegIndex(StringRef Name)
Check if the given identifier is a name of a subregister index.
bool getTargetIndex(StringRef Name, int &Index)
Try to convert a name of target index to the corresponding target index.
void setTarget(const TargetSubtargetInfo &NewSubtarget)
bool getRegisterByName(StringRef RegName, Register &Reg)
Try to convert a register name to a register number.
bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag)
Try to convert a name of a MachineMemOperand target flag to the corresponding target flag.
bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a bitmask target flag to the corresponding target flag.
const TargetRegisterClass * getRegClass(StringRef Name)
Check if the given identifier is a name of a register class.
const uint32_t * getRegMask(StringRef Identifier)
Check if the given identifier is a name of a register mask.
This struct contains the mappings from the slot numbers to unnamed metadata nodes,...
std::vector< GlobalValue * > GlobalValues