Go to the documentation of this file.
87 if (&Subtarget == &NewSubtarget)
90 Names2InstrOpCodes.
clear();
92 Names2RegMasks.
clear();
93 Names2SubRegIndices.
clear();
94 Names2TargetIndices.
clear();
95 Names2DirectTargetFlags.
clear();
96 Names2BitmaskTargetFlags.
clear();
97 Names2MMOTargetFlags.
clear();
99 initNames2RegClasses();
100 initNames2RegBanks();
103 void PerTargetMIParsingState::initNames2Regs() {
104 if (!Names2Regs.empty())
108 Names2Regs.insert(std::make_pair(
"noreg", 0));
110 assert(
TRI &&
"Expected target register info");
117 assert(WasInserted &&
"Expected registers to be unique case-insensitively");
124 auto RegInfo = Names2Regs.find(
RegName);
125 if (RegInfo == Names2Regs.end())
127 Reg = RegInfo->getValue();
131 void PerTargetMIParsingState::initNames2InstrOpCodes() {
132 if (!Names2InstrOpCodes.
empty())
135 assert(
TII &&
"Expected target instruction info");
136 for (
unsigned I = 0,
E =
TII->getNumOpcodes();
I <
E; ++
I)
142 initNames2InstrOpCodes();
143 auto InstrInfo = Names2InstrOpCodes.
find(InstrName);
144 if (InstrInfo == Names2InstrOpCodes.
end())
146 OpCode = InstrInfo->getValue();
150 void PerTargetMIParsingState::initNames2RegMasks() {
151 if (!Names2RegMasks.
empty())
154 assert(
TRI &&
"Expected target register info");
158 for (
size_t I = 0,
E = RegMasks.
size();
I <
E; ++
I)
160 std::make_pair(
StringRef(RegMaskNames[
I]).lower(), RegMasks[
I]));
164 initNames2RegMasks();
165 auto RegMaskInfo = Names2RegMasks.
find(Identifier);
166 if (RegMaskInfo == Names2RegMasks.
end())
168 return RegMaskInfo->getValue();
171 void PerTargetMIParsingState::initNames2SubRegIndices() {
172 if (!Names2SubRegIndices.
empty())
176 Names2SubRegIndices.
insert(
181 initNames2SubRegIndices();
182 auto SubRegInfo = Names2SubRegIndices.
find(
Name);
183 if (SubRegInfo == Names2SubRegIndices.
end())
185 return SubRegInfo->getValue();
188 void PerTargetMIParsingState::initNames2TargetIndices() {
189 if (!Names2TargetIndices.
empty())
192 assert(
TII &&
"Expected target instruction info");
193 auto Indices =
TII->getSerializableTargetIndices();
194 for (
const auto &
I : Indices)
199 initNames2TargetIndices();
200 auto IndexInfo = Names2TargetIndices.
find(
Name);
201 if (IndexInfo == Names2TargetIndices.
end())
203 Index = IndexInfo->second;
207 void PerTargetMIParsingState::initNames2DirectTargetFlags() {
208 if (!Names2DirectTargetFlags.
empty())
212 assert(
TII &&
"Expected target instruction info");
214 for (
const auto &
I : Flags)
215 Names2DirectTargetFlags.
insert(
221 initNames2DirectTargetFlags();
222 auto FlagInfo = Names2DirectTargetFlags.
find(
Name);
223 if (FlagInfo == Names2DirectTargetFlags.
end())
225 Flag = FlagInfo->second;
229 void PerTargetMIParsingState::initNames2BitmaskTargetFlags() {
230 if (!Names2BitmaskTargetFlags.
empty())
234 assert(
TII &&
"Expected target instruction info");
236 for (
const auto &
I : Flags)
237 Names2BitmaskTargetFlags.
insert(
243 initNames2BitmaskTargetFlags();
244 auto FlagInfo = Names2BitmaskTargetFlags.
find(
Name);
245 if (FlagInfo == Names2BitmaskTargetFlags.
end())
247 Flag = FlagInfo->second;
251 void PerTargetMIParsingState::initNames2MMOTargetFlags() {
252 if (!Names2MMOTargetFlags.
empty())
256 assert(
TII &&
"Expected target instruction info");
257 auto Flags =
TII->getSerializableMachineMemOperandTargetFlags();
258 for (
const auto &
I : Flags)
264 initNames2MMOTargetFlags();
265 auto FlagInfo = Names2MMOTargetFlags.
find(
Name);
266 if (FlagInfo == Names2MMOTargetFlags.
end())
268 Flag = FlagInfo->second;
272 void PerTargetMIParsingState::initNames2RegClasses() {
273 if (!Names2RegClasses.
empty())
284 void PerTargetMIParsingState::initNames2RegBanks() {
285 if (!Names2RegBanks.
empty())
303 auto RegClassInfo = Names2RegClasses.
find(
Name);
304 if (RegClassInfo == Names2RegClasses.
end())
306 return RegClassInfo->getValue();
310 auto RegBankInfo = Names2RegBanks.
find(
Name);
311 if (RegBankInfo == Names2RegBanks.
end())
313 return RegBankInfo->getValue();
318 : MF(MF), SM(&SM), IRSlots(IRSlots),
Target(
T) {
322 auto I =
VRegInfos.insert(std::make_pair(Num,
nullptr));
327 I.first->second =
Info;
329 return *
I.first->second;
339 I.first->second =
Info;
341 return *
I.first->second;
349 Slots2Values.
insert(std::make_pair(
unsigned(Slot), V));
357 for (
const auto &
Arg :
F.args())
359 for (
const auto &
BB :
F) {
361 for (
const auto &
I :
BB)
376 struct ParsedMachineOperand {
384 : Operand(Operand), Begin(Begin), End(End), TiedDefIdx(TiedDefIdx) {
387 "Only used register operands can be tied");
409 void lex(
unsigned SkipChar = 0);
423 bool parseBasicBlocks();
429 bool parseStandaloneStackObject(
int &FI);
430 bool parseStandaloneMDNode(
MDNode *&Node);
432 bool parseMDTuple(
MDNode *&MD,
bool IsDistinct);
447 bool parseRegisterFlag(
unsigned &Flags);
448 bool parseRegisterClassOrBank(
VRegInfo &RegInfo);
449 bool parseSubRegisterIndex(
unsigned &
SubReg);
450 bool parseRegisterTiedDefIndex(
unsigned &TiedDefIdx);
462 bool parseStackFrameIndex(
int &FI);
464 bool parseFixedStackFrameIndex(
int &FI);
474 bool parseDIExpression(
MDNode *&Expr);
475 bool parseDILocation(
MDNode *&Expr);
477 bool parseCFIOffset(
int &Offset);
480 bool parseCFIEscapeValues(std::string& Values);
490 bool parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
493 bool parseMachineOperandAndTargetFlags(
const unsigned OpCode,
494 const unsigned OpIdx,
497 bool parseOffset(int64_t &Offset);
498 bool parseAlignment(
uint64_t &Alignment);
499 bool parseAddrspace(
unsigned &Addrspace);
510 bool parseHeapAllocMarker(
MDNode *&Node);
512 bool parseTargetImmMnemonic(
const unsigned OpCode,
const unsigned OpIdx,
540 bool parseInstruction(
unsigned &
OpCode,
unsigned &Flags);
556 bool parseStringConstant(std::string &Result);
573 SourceRange(SourceRange), PFS(PFS) {}
575 void MIParser::lex(
unsigned SkipChar) {
601 assert(SourceRange.isValid() &&
"Invalid source range");
623 return "<unknown token>";
628 if (Token.isNot(TokenKind))
635 if (Token.isNot(TokenKind))
648 return error(
"Unknown Section ID");
652 if (
S ==
"Exception")
654 else if (
S ==
"Cold")
657 return error(
"Unknown Section ID");
663 bool MIParser::parseBasicBlockDefinition(
669 auto Loc = Token.location();
670 auto Name = Token.stringValue();
672 bool HasAddressTaken =
false;
673 bool IsLandingPad =
false;
674 bool IsInlineAsmBrIndirectTarget =
false;
675 bool IsEHFuncletEntry =
false;
682 switch (Token.kind()) {
684 HasAddressTaken =
true;
692 IsInlineAsmBrIndirectTarget =
true;
696 IsEHFuncletEntry =
true;
700 if (parseAlignment(Alignment))
705 if (parseIRBlock(
BB, MF.getFunction()))
710 if (parseSectionID(SectionID))
724 BB = dyn_cast_or_null<BasicBlock>(
725 MF.getFunction().getValueSymbolTable()->lookup(
Name));
728 "' is not defined in the function '" +
731 auto *
MBB = MF.CreateMachineBasicBlock(
BB);
733 bool WasInserted = MBBSlots.
insert(std::make_pair(
ID,
MBB)).second;
735 return error(Loc,
Twine(
"redefinition of machine basic block with id #") +
751 bool MIParser::parseBasicBlockDefinitions(
757 if (Token.isErrorOrEOF())
758 return Token.isError();
760 return error(
"expected a basic block definition before instructions");
761 unsigned BraceDepth = 0;
763 if (parseBasicBlockDefinition(MBBSlots))
765 bool IsAfterNewline =
false;
769 Token.isErrorOrEOF())
772 return error(
"basic block definition should be located at the start of "
775 IsAfterNewline =
true;
778 IsAfterNewline =
false;
783 return error(
"extraneous closing brace ('}')");
789 if (!Token.isError() && BraceDepth)
790 return error(
"expected '}'");
791 }
while (!Token.isErrorOrEOF());
792 return Token.isError();
800 if (Token.isNewlineOrEOF())
804 return error(
"expected a named register");
806 if (parseNamedRegister(
Reg))
814 return error(
"expected a lane mask");
816 "Use correct get-function for lane mask");
819 return error(
"invalid lane mask value");
833 if (Token.isNewlineOrEOF())
837 return error(
"expected a machine basic block reference");
846 return error(
"expected an integer literal after '('");
880 bool ExplicitSuccessors =
false;
883 if (parseBasicBlockSuccessors(
MBB))
885 ExplicitSuccessors =
true;
887 if (parseBasicBlockLiveins(
MBB))
893 if (!Token.isNewlineOrEOF())
894 return error(
"expected line break at the end of a list");
899 bool IsInBundle =
false;
923 return error(
"nested instruction bundles are not allowed");
932 assert(Token.isNewlineOrEOF() &&
"MI is not fully parsed");
937 if (!ExplicitSuccessors) {
945 AddFalthroughFrom = &
MBB;
954 bool MIParser::parseBasicBlocks() {
959 if (Token.isErrorOrEOF())
960 return Token.isError();
969 if (AddFalthroughFrom) {
973 AddFalthroughFrom =
nullptr;
975 if (parseBasicBlock(*
MBB, AddFalthroughFrom))
988 while (Token.isRegister() || Token.isRegisterFlag()) {
989 auto Loc = Token.location();
991 if (parseRegisterOperand(MO, TiedDefIdx,
true))
994 ParsedMachineOperand(MO, Loc, Token.location(), TiedDefIdx));
1002 unsigned OpCode, Flags = 0;
1003 if (Token.isError() || parseInstruction(
OpCode, Flags))
1013 auto Loc = Token.location();
1015 if (parseMachineOperandAndTargetFlags(
OpCode,
Operands.size(), MO, TiedDefIdx))
1018 ParsedMachineOperand(MO, Loc, Token.location(), TiedDefIdx));
1023 return error(
"expected ',' before the next machine operand");
1027 MCSymbol *PreInstrSymbol =
nullptr;
1029 if (parsePreOrPostInstrSymbol(PreInstrSymbol))
1031 MCSymbol *PostInstrSymbol =
nullptr;
1033 if (parsePreOrPostInstrSymbol(PostInstrSymbol))
1035 MDNode *HeapAllocMarker =
nullptr;
1037 if (parseHeapAllocMarker(HeapAllocMarker))
1040 unsigned InstrNum = 0;
1044 return error(
"expected an integer literal after 'debug-instr-number'");
1061 if (parseDILocation(Node))
1064 return error(
"expected a metadata node after 'debug-location'");
1065 if (!isa<DILocation>(Node))
1066 return error(
"referenced metadata is not a DILocation");
1074 while (!Token.isNewlineOrEOF()) {
1076 if (parseMachineMemoryOperand(
MemOp))
1078 MemOperands.push_back(
MemOp);
1079 if (Token.isNewlineOrEOF())
1082 return error(
"expected ',' before the next machine memory operand");
1087 const auto &MCID = MF.getSubtarget().getInstrInfo()->get(
OpCode);
1088 if (!MCID.isVariadic()) {
1090 if (verifyImplicitOperands(
Operands, MCID))
1094 MI = MF.CreateMachineInstr(MCID, DebugLocation,
true);
1095 MI->setFlags(Flags);
1097 unsigned NumExplicitOps = 0;
1098 for (
const auto &Operand :
Operands) {
1099 bool IsImplicitOp = Operand.Operand.isReg() && Operand.Operand.isImplicit();
1100 if (!IsImplicitOp) {
1101 if (!MCID.isVariadic() && NumExplicitOps >= MCID.getNumOperands() &&
1102 !Operand.Operand.isValidExcessOperand())
1103 return error(Operand.Begin,
"too many operands for instruction");
1108 MI->addOperand(MF, Operand.Operand);
1114 MI->setPreInstrSymbol(MF, PreInstrSymbol);
1115 if (PostInstrSymbol)
1116 MI->setPostInstrSymbol(MF, PostInstrSymbol);
1117 if (HeapAllocMarker)
1118 MI->setHeapAllocMarker(MF, HeapAllocMarker);
1119 if (!MemOperands.empty())
1120 MI->setMemRefs(MF, MemOperands);
1122 MI->setDebugInstrNum(InstrNum);
1129 return error(
"expected a machine basic block reference");
1135 "expected end of string after the machine basic block reference");
1139 bool MIParser::parseStandaloneNamedRegister(
Register &
Reg) {
1142 return error(
"expected a named register");
1143 if (parseNamedRegister(
Reg))
1147 return error(
"expected end of string after the register reference");
1151 bool MIParser::parseStandaloneVirtualRegister(
VRegInfo *&
Info) {
1154 return error(
"expected a virtual register");
1155 if (parseVirtualRegister(
Info))
1159 return error(
"expected end of string after the register reference");
1163 bool MIParser::parseStandaloneRegister(
Register &
Reg) {
1167 return error(
"expected either a named or virtual register");
1175 return error(
"expected end of string after the register reference");
1179 bool MIParser::parseStandaloneStackObject(
int &FI) {
1182 return error(
"expected a stack object");
1183 if (parseStackFrameIndex(FI))
1186 return error(
"expected end of string after the stack object reference");
1190 bool MIParser::parseStandaloneMDNode(
MDNode *&Node) {
1196 if (parseDIExpression(Node))
1199 if (parseDILocation(Node))
1202 return error(
"expected a metadata node");
1204 return error(
"expected end of string after the metadata node");
1211 return error(
"expected a metadata node");
1215 return error(
"expected metadata id after '!'");
1226 return error(
"expected a metadata node");
1230 if (parseMDTuple(MD, IsDistinct))
1233 auto FI = PFS.MachineForwardRefMDNodes.find(
ID);
1234 if (FI != PFS.MachineForwardRefMDNodes.end()) {
1236 PFS.MachineForwardRefMDNodes.erase(FI);
1238 assert(PFS.MachineMetadataNodes[
ID] == MD &&
"Tracking VH didn't work");
1240 if (PFS.MachineMetadataNodes.count(
ID))
1241 return error(
"Metadata id is already used");
1242 PFS.MachineMetadataNodes[
ID].reset(MD);
1248 bool MIParser::parseMDTuple(
MDNode *&MD,
bool IsDistinct) {
1250 if (parseMDNodeVector(Elts))
1259 return error(
"expected '{' here");
1280 return error(
"expected end of metadata node");
1290 return error(
"expected '!' here");
1295 if (parseStringConstant(Str))
1302 return error(
"expected metadata id after '!'");
1304 SMLoc Loc = mapSMLoc(Token.location());
1311 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(
ID);
1312 if (NodeInfo != PFS.IRSlots.MetadataNodes.end()) {
1313 MD = NodeInfo->second.get();
1317 NodeInfo = PFS.MachineMetadataNodes.find(
ID);
1318 if (NodeInfo != PFS.MachineMetadataNodes.end()) {
1319 MD = NodeInfo->second.get();
1323 auto &FwdRef = PFS.MachineForwardRefMDNodes[
ID];
1324 FwdRef = std::make_pair(
1326 PFS.MachineMetadataNodes[
ID].reset(FwdRef.first.get());
1327 MD = FwdRef.first.get();
1334 return MO.
isDef() ?
"implicit-def" :
"implicit";
1364 ImplicitOperands.push_back(
1368 ImplicitOperands.push_back(
1371 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
1372 assert(
TRI &&
"Expected target register info");
1373 for (
const auto &
I : ImplicitOperands) {
1377 Twine(
"missing implicit register operand '") +
1384 bool MIParser::parseInstruction(
unsigned &
OpCode,
unsigned &Flags) {
1430 return error(
"expected a machine instruction");
1431 StringRef InstrName = Token.stringValue();
1432 if (PFS.Target.parseInstrName(InstrName,
OpCode))
1433 return error(
Twine(
"unknown machine instruction name '") + InstrName +
"'");
1438 bool MIParser::parseNamedRegister(
Register &
Reg) {
1441 if (PFS.Target.getRegisterByName(
Name,
Reg))
1446 bool MIParser::parseNamedVirtualRegister(
VRegInfo *&
Info) {
1451 Info = &PFS.getVRegInfoNamed(
Name);
1457 return parseNamedVirtualRegister(
Info);
1462 Info = &PFS.getVRegInfo(
ID);
1467 switch (Token.kind()) {
1472 return parseNamedRegister(
Reg);
1475 if (parseVirtualRegister(
Info))
1485 bool MIParser::parseRegisterClassOrBank(
VRegInfo &RegInfo) {
1487 return error(
"expected '_', register class, or register bank name");
1496 switch (RegInfo.
Kind) {
1502 return error(Loc,
Twine(
"conflicting register classes, previously: ") +
1511 return error(Loc,
"register class specification on generic register");
1519 RegBank = PFS.Target.getRegBank(
Name);
1521 return error(Loc,
"expected '_', register class, or register bank name");
1526 switch (RegInfo.
Kind) {
1532 return error(Loc,
"conflicting generic register banks");
1538 return error(Loc,
"register bank specification on normal register");
1543 bool MIParser::parseRegisterFlag(
unsigned &Flags) {
1544 const unsigned OldFlags = Flags;
1545 switch (Token.kind()) {
1579 if (OldFlags == Flags)
1582 return error(
"duplicate '" + Token.stringValue() +
"' register flag");
1587 bool MIParser::parseSubRegisterIndex(
unsigned &
SubReg) {
1591 return error(
"expected a subregister index after '.'");
1592 auto Name = Token.stringValue();
1595 return error(
Twine(
"use of unknown subregister index '") +
Name +
"'");
1600 bool MIParser::parseRegisterTiedDefIndex(
unsigned &TiedDefIdx) {
1604 return error(
"expected an integer literal after 'tied-def'");
1621 unsigned DefIdx =
Operands[
I].TiedDefIdx.getValue();
1624 Twine(
"use of invalid tied-def operand index '" +
1625 Twine(DefIdx) +
"'; instruction has only ") +
1627 const auto &DefOperand =
Operands[DefIdx].Operand;
1628 if (!DefOperand.isReg() || !DefOperand.isDef())
1631 Twine(
"use of invalid tied-def operand index '") +
1632 Twine(DefIdx) +
"'; the operand #" +
Twine(DefIdx) +
1633 " isn't a defined register");
1635 for (
const auto &TiedPair : TiedRegisterPairs) {
1636 if (TiedPair.first == DefIdx)
1638 Twine(
"the tied-def operand #") +
Twine(DefIdx) +
1639 " is already tied with another register operand");
1641 TiedRegisterPairs.push_back(std::make_pair(DefIdx,
I));
1645 for (
const auto &TiedPair : TiedRegisterPairs)
1646 MI.tieOperands(TiedPair.first, TiedPair.second);
1654 while (Token.isRegisterFlag()) {
1655 if (parseRegisterFlag(Flags))
1658 if (!Token.isRegister())
1659 return error(
"expected a register after register flags");
1662 if (parseRegister(
Reg, RegInfo))
1667 if (parseSubRegisterIndex(
SubReg))
1670 return error(
"subregister index expects a virtual register");
1674 return error(
"register class specification expects a virtual register");
1676 if (parseRegisterClassOrBank(*RegInfo))
1683 if (!parseRegisterTiedDefIndex(Idx))
1688 if (parseLowLevelType(Token.location(), Ty))
1689 return error(
"expected tied-def or low-level type after '('");
1695 return error(
"inconsistent type for generic virtual register");
1704 return error(
"unexpected type on physical register");
1707 if (parseLowLevelType(Token.location(), Ty))
1714 return error(
"inconsistent type for generic virtual register");
1724 return error(
"generic virtual registers must have a type");
1729 return error(
"cannot have a killed def operand");
1732 return error(
"cannot have a dead use operand");
1746 const APSInt &
Int = Token.integerValue();
1747 if (
Int.getMinSignedBits() > 64)
1748 return error(
"integer literal is too large to be an immediate operand");
1754 bool MIParser::parseTargetImmMnemonic(
const unsigned OpCode,
1755 const unsigned OpIdx,
1759 auto Loc = Token.location();
1765 Len += Token.range().size();
1774 Src =
StringRef(Loc, Len + Token.stringValue().size());
1779 ->
bool { return error(Loc, Msg); }))
1796 return ErrCB(Loc + Err.getColumnNo(), Err.getMessage());
1803 Loc, StringValue, PFS,
C,
1826 return isUInt<24>(AddrSpace);
1830 if (Token.range().front() ==
's' || Token.range().front() ==
'p') {
1833 return error(
"expected integers after 's'/'p' type character");
1836 if (Token.range().front() ==
's') {
1837 auto ScalarSize =
APSInt(Token.range().drop_front()).getZExtValue();
1839 return error(
"invalid size for scalar type");
1844 }
else if (Token.range().front() ==
'p') {
1848 return error(
"invalid address space number");
1858 "expected sN, pA, <M x sN>, or <M x pA> for GlobalISel type");
1862 return error(Loc,
"expected <M x sN> or <M x pA> for vector type");
1863 uint64_t NumElements = Token.integerValue().getZExtValue();
1865 return error(
"invalid number of vector elements");
1870 return error(Loc,
"expected <M x sN> or <M x pA> for vector type");
1873 if (Token.range().front() !=
's' && Token.range().front() !=
'p')
1874 return error(Loc,
"expected <M x sN> or <M x pA> for vector type");
1877 return error(
"expected integers after 's'/'p' type character");
1879 if (Token.range().front() ==
's') {
1880 auto ScalarSize =
APSInt(Token.range().drop_front()).getZExtValue();
1882 return error(
"invalid size for scalar type");
1884 }
else if (Token.range().front() ==
'p') {
1888 return error(
"invalid address space number");
1892 return error(Loc,
"expected <M x sN> or <M x pA> for vector type");
1896 return error(Loc,
"expected <M x sN> or <M x pA> for vector type");
1903 bool MIParser::parseTypedImmediateOperand(
MachineOperand &Dest) {
1906 if (TypeStr.
front() !=
'i' && TypeStr.
front() !=
's' &&
1907 TypeStr.
front() !=
'p')
1909 "a typed immediate operand should start with one of 'i', 's', or 'p'");
1912 return error(
"expected integers after 'i'/'s'/'p' type character");
1914 auto Loc = Token.location();
1918 !(Token.range() ==
"true" || Token.range() ==
"false"))
1919 return error(
"expected an integer literal");
1929 auto Loc = Token.location();
1933 return error(
"expected a floating point literal");
1944 assert(
S[0] ==
'0' && tolower(
S[1]) ==
'x');
1946 if (!isxdigit(
S[2]))
1953 unsigned NumBits = (A == 0) ? 32 : A.getActiveBits();
1964 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
1972 if (A.getBitWidth() > 32)
1973 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
1974 Result = A.getZExtValue();
1993 auto MBBInfo = PFS.MBBSlots.find(Number);
1994 if (MBBInfo == PFS.MBBSlots.end())
1995 return error(
Twine(
"use of undefined machine basic block #") +
1997 MBB = MBBInfo->second;
2000 if (!Token.stringValue().empty() && Token.stringValue() !=
MBB->
getName())
2001 return error(
Twine(
"the name of machine basic block #") +
Twine(Number) +
2002 " isn't '" + Token.stringValue() +
"'");
2015 bool MIParser::parseStackFrameIndex(
int &FI) {
2020 auto ObjectInfo = PFS.StackObjectSlots.find(
ID);
2021 if (ObjectInfo == PFS.StackObjectSlots.end())
2025 if (
const auto *Alloca =
2026 MF.getFrameInfo().getObjectAllocation(ObjectInfo->second))
2027 Name = Alloca->getName();
2028 if (!Token.stringValue().empty() && Token.stringValue() !=
Name)
2030 "' isn't '" + Token.stringValue() +
"'");
2032 FI = ObjectInfo->second;
2038 if (parseStackFrameIndex(FI))
2044 bool MIParser::parseFixedStackFrameIndex(
int &FI) {
2049 auto ObjectInfo = PFS.FixedStackObjectSlots.find(
ID);
2050 if (ObjectInfo == PFS.FixedStackObjectSlots.end())
2051 return error(
Twine(
"use of undefined fixed stack object '%fixed-stack.") +
2054 FI = ObjectInfo->second;
2058 bool MIParser::parseFixedStackObjectOperand(
MachineOperand &Dest) {
2060 if (parseFixedStackFrameIndex(FI))
2069 switch (Token.
kind()) {
2074 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '") +
2075 Token.
range() +
"'");
2083 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '@") +
2084 Twine(GVIdx) +
"'");
2108 if (parseOperandsOffset(Dest))
2113 bool MIParser::parseConstantPoolIndexOperand(
MachineOperand &Dest) {
2120 return error(
"use of undefined constant '%const." +
Twine(
ID) +
"'");
2123 if (parseOperandsOffset(Dest))
2128 bool MIParser::parseJumpTableIndexOperand(
MachineOperand &Dest) {
2133 auto JumpTableEntryInfo = PFS.JumpTableSlots.find(
ID);
2134 if (JumpTableEntryInfo == PFS.JumpTableSlots.end())
2135 return error(
"use of undefined jump table '%jump-table." +
Twine(
ID) +
"'");
2141 bool MIParser::parseExternalSymbolOperand(
MachineOperand &Dest) {
2143 const char *
Symbol = MF.createExternalSymbolName(Token.stringValue());
2146 if (parseOperandsOffset(Dest))
2156 if (parseOperandsOffset(Dest))
2161 bool MIParser::parseSubRegisterIndexOperand(
MachineOperand &Dest) {
2164 unsigned SubRegIndex = PFS.Target.getSubRegIndex(Token.stringValue());
2165 if (SubRegIndex == 0)
2175 auto Loc = Token.location();
2178 return error(
"expected metadata id after '!'");
2182 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(
ID);
2183 if (NodeInfo == PFS.IRSlots.MetadataNodes.end()) {
2184 NodeInfo = PFS.MachineMetadataNodes.find(
ID);
2185 if (NodeInfo == PFS.MachineMetadataNodes.end())
2186 return error(Loc,
"use of undefined metadata '!" +
Twine(
ID) +
"'");
2189 Node = NodeInfo->second.get();
2193 bool MIParser::parseDIExpression(
MDNode *&Expr) {
2208 Elements.push_back(
Op);
2213 Elements.push_back(Enc);
2216 return error(
Twine(
"invalid DWARF op '") + Token.stringValue() +
"'");
2220 Token.integerValue().isSigned())
2221 return error(
"expected unsigned integer");
2223 auto &U = Token.integerValue();
2226 Elements.push_back(U.getZExtValue());
2239 bool MIParser::parseDILocation(
MDNode *&Loc) {
2243 bool HaveLine =
false;
2245 unsigned Column = 0;
2247 MDNode *InlinedAt =
nullptr;
2248 bool ImplicitCode =
false;
2256 if (Token.stringValue() ==
"line") {
2261 Token.integerValue().isSigned())
2262 return error(
"expected unsigned integer");
2263 Line = Token.integerValue().getZExtValue();
2268 if (Token.stringValue() ==
"column") {
2273 Token.integerValue().isSigned())
2274 return error(
"expected unsigned integer");
2275 Column = Token.integerValue().getZExtValue();
2279 if (Token.stringValue() ==
"scope") {
2284 return error(
"expected metadata node");
2285 if (!isa<DIScope>(
Scope))
2286 return error(
"expected DIScope node");
2289 if (Token.stringValue() ==
"inlinedAt") {
2297 if (parseDILocation(InlinedAt))
2300 return error(
"expected metadata node");
2301 if (!isa<DILocation>(InlinedAt))
2302 return error(
"expected DILocation node");
2305 if (Token.stringValue() ==
"isImplicitCode") {
2310 return error(
"expected true/false");
2314 if (Token.stringValue() ==
"true")
2315 ImplicitCode =
true;
2316 else if (Token.stringValue() ==
"false")
2317 ImplicitCode =
false;
2319 return error(
"expected true/false");
2324 return error(
Twine(
"invalid DILocation argument '") +
2325 Token.stringValue() +
"'");
2333 return error(
"DILocation requires line number");
2335 return error(
"DILocation requires a scope");
2338 InlinedAt, ImplicitCode);
2348 if (parseDIExpression(Node))
2355 bool MIParser::parseCFIOffset(
int &Offset) {
2357 return error(
"expected a cfi offset");
2358 if (Token.integerValue().getMinSignedBits() > 32)
2359 return error(
"expected a 32 bit integer (the cfi offset is too large)");
2360 Offset = (
int)Token.integerValue().getExtValue();
2367 return error(
"expected a cfi register");
2369 if (parseNamedRegister(LLVMReg))
2371 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
2372 assert(
TRI &&
"Expected target register info");
2375 return error(
"invalid DWARF register");
2376 Reg = (unsigned)DwarfReg;
2381 bool MIParser::parseCFIAddressSpace(
unsigned &
AddressSpace) {
2383 return error(
"expected a cfi address space literal");
2384 if (Token.integerValue().isSigned())
2385 return error(
"expected an unsigned integer (cfi address space)");
2391 bool MIParser::parseCFIEscapeValues(std::string &Values) {
2394 return error(
"expected a hexadecimal literal");
2398 if (
Value > UINT8_MAX)
2399 return error(
"expected a 8-bit integer (too large)");
2400 Values.push_back(
static_cast<uint8_t
>(
Value));
2407 auto Kind = Token.kind();
2415 if (parseCFIRegister(
Reg))
2421 parseCFIOffset(Offset))
2428 parseCFIOffset(Offset))
2430 CFIIndex = MF.addFrameInst(
2434 if (parseCFIRegister(
Reg))
2440 if (parseCFIOffset(Offset))
2446 if (parseCFIOffset(Offset))
2448 CFIIndex = MF.addFrameInst(
2453 parseCFIOffset(Offset))
2470 if (parseCFIRegister(
Reg))
2478 if (parseCFIRegister(
Reg))
2485 parseCFIRegister(Reg2))
2500 if (parseCFIEscapeValues(Values))
2514 switch (Token.kind()) {
2516 BB = dyn_cast_or_null<BasicBlock>(
2517 F.getValueSymbolTable()->lookup(Token.stringValue()));
2519 return error(
Twine(
"use of undefined IR block '") + Token.range() +
"'");
2523 unsigned SlotNumber = 0;
2528 return error(
Twine(
"use of undefined IR block '%ir-block.") +
2529 Twine(SlotNumber) +
"'");
2545 return error(
"expected a global value");
2549 auto *
F = dyn_cast<Function>(GV);
2551 return error(
"expected an IR function reference");
2557 return error(
"expected an IR block reference");
2558 if (parseIRBlock(
BB, *
F))
2564 if (parseOperandsOffset(Dest))
2573 return error(
"expected syntax intrinsic(@llvm.whatever)");
2576 return error(
"expected syntax intrinsic(@llvm.whatever)");
2578 std::string
Name = std::string(Token.stringValue());
2582 return error(
"expected ')' to terminate intrinsic name");
2592 return error(
"unknown intrinsic name");
2604 return error(
"expected syntax intpred(whatever) or floatpred(whatever");
2607 return error(
"whatever");
2630 return error(
"invalid floating-point predicate");
2645 return error(
"invalid integer predicate");
2651 return error(
"predicate should be terminated by ')'.");
2661 return error(
"expected syntax shufflemask(<integer or undef>, ...)");
2666 ShufMask.push_back(-1);
2668 const APSInt &
Int = Token.integerValue();
2669 ShufMask.push_back(
Int.getExtValue());
2671 return error(
"expected integer constant");
2677 return error(
"shufflemask should be terminated by ')'.");
2690 return error(
"expected the name of the target index");
2692 if (PFS.Target.getTargetIndex(Token.stringValue(), Index))
2693 return error(
"use of undefined target index '" + Token.stringValue() +
"'");
2698 if (parseOperandsOffset(Dest))
2703 bool MIParser::parseCustomRegisterMaskOperand(
MachineOperand &Dest) {
2704 assert(Token.stringValue() ==
"CustomRegMask" &&
"Expected a custom RegMask");
2712 return error(
"expected a named register");
2714 if (parseNamedRegister(
Reg))
2730 bool MIParser::parseLiveoutRegisterMaskOperand(
MachineOperand &Dest) {
2738 return error(
"expected a named register");
2740 if (parseNamedRegister(
Reg))
2755 bool MIParser::parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
2758 switch (Token.kind()) {
2773 return parseRegisterOperand(Dest, TiedDefIdx);
2775 return parseImmediateOperand(Dest);
2782 return parseFPImmediateOperand(Dest);
2784 return parseMBBOperand(Dest);
2786 return parseStackObjectOperand(Dest);
2788 return parseFixedStackObjectOperand(Dest);
2791 return parseGlobalAddressOperand(Dest);
2793 return parseConstantPoolIndexOperand(Dest);
2795 return parseJumpTableIndexOperand(Dest);
2797 return parseExternalSymbolOperand(Dest);
2799 return parseMCSymbolOperand(Dest);
2801 return parseSubRegisterIndexOperand(Dest);
2804 return parseMetadataOperand(Dest);
2821 return parseCFIOperand(Dest);
2823 return parseBlockAddressOperand(Dest);
2825 return parseIntrinsicOperand(Dest);
2827 return parseTargetIndexOperand(Dest);
2829 return parseLiveoutRegisterMaskOperand(Dest);
2832 return parsePredicateOperand(Dest);
2834 return parseShuffleMaskOperand(Dest);
2838 if (
const auto *RegMask = PFS.Target.getRegMask(Token.stringValue())) {
2842 }
else if (Token.stringValue() ==
"CustomRegMask") {
2843 return parseCustomRegisterMaskOperand(Dest);
2845 return parseTypedImmediateOperand(Dest);
2847 const auto *
TII = MF.getSubtarget().getInstrInfo();
2848 if (
const auto *Formatter =
TII->getMIRFormatter()) {
2849 return parseTargetImmMnemonic(
OpCode, OpIdx, Dest, *Formatter);
2855 return error(
"expected a machine operand");
2860 bool MIParser::parseMachineOperandAndTargetFlags(
2864 bool HasTargetFlags =
false;
2866 HasTargetFlags =
true;
2871 return error(
"expected the name of the target flag");
2872 if (PFS.Target.getDirectTargetFlag(Token.stringValue(), TF)) {
2873 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), TF))
2874 return error(
"use of undefined target flag '" + Token.stringValue() +
2881 return error(
"expected the name of the target flag");
2882 unsigned BitFlag = 0;
2883 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), BitFlag))
2884 return error(
"use of undefined target flag '" + Token.stringValue() +
2893 auto Loc = Token.location();
2894 if (parseMachineOperand(
OpCode, OpIdx, Dest, TiedDefIdx))
2896 if (!HasTargetFlags)
2899 return error(Loc,
"register operands can't have target flags");
2904 bool MIParser::parseOffset(int64_t &Offset) {
2911 return error(
"expected an integer literal after '" + Sign +
"'");
2912 if (Token.integerValue().getMinSignedBits() > 64)
2913 return error(
"expected 64-bit integer (too large)");
2914 Offset = Token.integerValue().getExtValue();
2921 bool MIParser::parseAlignment(
uint64_t &Alignment) {
2925 return error(
"expected an integer literal after 'align'");
2926 if (getUint64(Alignment))
2931 return error(
"expected a power-of-2 literal after 'align'");
2936 bool MIParser::parseAddrspace(
unsigned &Addrspace) {
2940 return error(
"expected an integer literal after 'addrspace'");
2949 if (parseOffset(Offset))
2951 Op.setOffset(Offset);
2957 switch (Token.
kind()) {
2963 unsigned SlotNumber = 0;
2991 return ErrCB(Token.
location(),
Twine(
"use of undefined IR value '") + Token.
range() +
"'");
3002 bool MIParser::getUint64(
uint64_t &Result) {
3003 if (Token.hasIntegerValue()) {
3004 if (Token.integerValue().getActiveBits() > 64)
3005 return error(
"expected 64-bit integer (too large)");
3006 Result = Token.integerValue().getZExtValue();
3013 if (
A.getBitWidth() > 64)
3014 return error(
"expected 64-bit integer (too large)");
3026 const auto OldFlags = Flags;
3027 switch (Token.kind()) {
3042 if (PFS.Target.getMMOTargetFlag(Token.stringValue(), TF))
3043 return error(
"use of undefined target MMO flag '" + Token.stringValue() +
3051 if (OldFlags == Flags)
3054 return error(
"duplicate '" + Token.stringValue() +
"' memory operand flag");
3060 switch (Token.kind()) {
3062 PSV = MF.getPSVManager().getStack();
3065 PSV = MF.getPSVManager().getGOT();
3068 PSV = MF.getPSVManager().getJumpTable();
3071 PSV = MF.getPSVManager().getConstantPool();
3075 if (parseFixedStackFrameIndex(FI))
3077 PSV = MF.getPSVManager().getFixedStack(FI);
3083 if (parseStackFrameIndex(FI))
3085 PSV = MF.getPSVManager().getFixedStack(FI);
3091 switch (Token.kind()) {
3097 PSV = MF.getPSVManager().getGlobalValueCallEntry(GV);
3101 PSV = MF.getPSVManager().getExternalSymbolCallEntry(
3102 MF.createExternalSymbolName(Token.stringValue()));
3106 "expected a global value or an external symbol after 'call-entry'");
3111 const auto *
TII = MF.getSubtarget().getInstrInfo();
3112 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3113 if (Formatter->parseCustomPseudoSourceValue(
3114 Token.stringValue(), MF, PFS, PSV,
3116 return error(Loc, Msg);
3120 return error(
"unable to parse target custom pseudo source value");
3136 if (parseMemoryPseudoSourceValue(PSV))
3139 if (parseOffset(Offset))
3149 return error(
"expected an IR value reference");
3150 const Value *V =
nullptr;
3154 return error(
"expected a pointer IR value");
3157 if (parseOffset(Offset))
3169 return error(
"expected '(' in syncscope");
3172 if (parseStringConstant(SSN))
3177 return error(
"expected ')' in syncscope");
3183 bool MIParser::parseOptionalAtomicOrdering(
AtomicOrdering &Order) {
3202 return error(
"expected an atomic scope, ordering or a size specification");
3209 while (Token.isMemoryOperandFlag()) {
3210 if (parseMemoryOperandFlag(Flags))
3214 (Token.stringValue() !=
"load" && Token.stringValue() !=
"store"))
3215 return error(
"expected 'load' or 'store' memory operation");
3216 if (Token.stringValue() ==
"load")
3230 if (parseOptionalScope(MF.getFunction().getContext(), SSID))
3235 if (parseOptionalAtomicOrdering(Order))
3238 if (parseOptionalAtomicOrdering(FailureOrder))
3245 return error(
"expected memory LLT, the size integer literal or 'unknown-size' after "
3246 "memory operation");
3250 if (getUint64(Size))
3262 if (parseLowLevelType(Token.location(),
MemoryType))
3277 if (Token.stringValue() !=
Word)
3281 if (parseMachinePointerInfo(Ptr))
3289 switch (Token.kind()) {
3293 if (parseAlignment(Alignment))
3295 if (Ptr.
Offset & (Alignment - 1)) {
3300 return error(
"specified alignment is more aligned than offset");
3307 if (parseAlignment(BaseAlignment))
3336 return error(
"expected 'align' or '!tbaa' or '!alias.scope' or "
3337 "'!noalias' or '!range'");
3342 Dest = MF.getMachineMemOperand(Ptr, Flags,
MemoryType,
Align(BaseAlignment),
3343 AAInfo, Range, SSID, Order, FailureOrder);
3350 "Invalid token for a pre- post-instruction symbol!");
3353 return error(
"expected a symbol after 'pre-instr-symbol'");
3354 Symbol = getOrCreateMCSymbol(Token.stringValue());
3360 return error(
"expected ',' before the next machine operand");
3365 bool MIParser::parseHeapAllocMarker(
MDNode *&Node) {
3367 "Invalid token for a heap alloc marker!");
3371 return error(
"expected a MDNode after 'heap-alloc-marker'");
3376 return error(
"expected ',' before the next machine operand");
3386 for (
auto &
BB :
F) {
3392 Slots2BasicBlocks.
insert(std::make_pair(
unsigned(Slot), &
BB));
3399 return Slots2BasicBlocks.
lookup(Slot);
3402 const BasicBlock *MIParser::getIRBlock(
unsigned Slot) {
3403 if (Slots2BasicBlocks.empty())
3409 if (&
F == &MF.getFunction())
3410 return getIRBlock(Slot);
3422 return MF.getContext().getOrCreateSymbol(
Name);
3425 bool MIParser::parseStringConstant(std::string &Result) {
3427 return error(
"expected string constant");
3428 Result = std::string(Token.stringValue());
3436 return MIParser(PFS,
Error, Src).parseBasicBlockDefinitions(PFS.
MBBSlots);
3441 return MIParser(PFS,
Error, Src).parseBasicBlocks();
3447 return MIParser(PFS,
Error, Src).parseStandaloneMBB(
MBB);
3453 return MIParser(PFS,
Error, Src).parseStandaloneRegister(
Reg);
3459 return MIParser(PFS,
Error, Src).parseStandaloneNamedRegister(
Reg);
3465 return MIParser(PFS,
Error, Src).parseStandaloneVirtualRegister(
Info);
3471 return MIParser(PFS,
Error, Src).parseStandaloneStackObject(FI);
3476 return MIParser(PFS,
Error, Src).parseStandaloneMDNode(Node);
3481 return MIParser(PFS,
Error, Src, SrcRange).parseMachineMetadata();
3489 ErrorCallback(Loc,
Msg);
StringSwitch & Case(StringLiteral S, T Value)
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
function_ref< bool(StringRef::iterator Loc, const Twine &)> ErrorCallbackType
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
This is an optimization pass for GlobalISel generic memory operations.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
A parsed version of the target data layout string in and methods for querying it.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static const BasicBlock * getIRBlockFromSlot(unsigned Slot, const DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
@ Define
Register definition.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
bool isPointerTy() const
True if this is an instance of PointerType.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
virtual const TargetInstrInfo * getInstrInfo() const
LLVM_NODISCARD R Default(T Value)
const RegisterBank * RegBank
const RegisterBank * getRegBank(StringRef Name)
Check if the given identifier is a name of a register bank.
Target - Wrapper for Target specific information.
const APSInt & integerValue() const
virtual ArrayRef< const char * > getRegMaskNames() const =0
static constexpr size_t npos
@ Undef
Value of the register doesn't matter.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
static void mapValueToSlot(const Value *V, ModuleSlotTracker &MST, DenseMap< unsigned, const Value * > &Slots2Values)
enum llvm::VRegInfo::uint8_t Kind
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
int getDwarfRegNum(MCRegister RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM, const SlotMapping &IRSlots, PerTargetMIParsingState &Target)
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Reg
All possible values of the reg field in the ModR/M byte.
@ MOInvariant
The memory access always returns the same value (or traps).
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
@ ICMP_SGT
signed greater than
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
static MCCFIInstruction createRelOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_rel_offset Previous value of Register is saved at offset Offset from the current CFA register.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
static MachineOperand CreateMetadata(const MDNode *Meta)
bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine instructions.
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
A description of a memory reference used in the backend.
@ Debug
Register 'use' is for debugging purpose.
static bool getHexUint(const MIToken &Token, APInt &Result)
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
StringMap< VRegInfo * > VRegInfosNamed
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
@ kw_inlineasm_br_indirect_target
static const char * printImplicitRegisterFlag(const MachineOperand &MO)
@ ICMP_SLE
signed less or equal
VRegInfo & getVRegInfoNamed(StringRef RegName)
union llvm::VRegInfo::@198 D
void incorporateFunction(const Function &F)
Incorporate the given function.
uint64_t PowerOf2Ceil(uint64_t A)
Returns the power of two which is greater than or equal to the given value.
iterator find(StringRef Key)
MDNode * Scope
The tag for alias scope specification (used with noalias).
bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag)
Try to convert a name of a MachineMemOperand target flag to the corresponding target flag.
const TargetRegisterClass * RC
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register)
.cfi_same_value Current value of Register is the same as in the previous frame.
Manage lifetime of a slot tracker for printing IR.
unsigned const TargetRegisterInfo * TRI
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
@ EarlyClobber
Register definition happens before uses.
This interface provides simple read-only access to a block of memory, and provides simple methods for...
A token produced by the machine instruction lexer.
static MCCFIInstruction createLLVMDefAspaceCfa(MCSymbol *L, unsigned Register, int Offset, unsigned AddressSpace)
.cfi_llvm_def_aspace_cfa defines the rule for computing the CFA to be the result of evaluating the DW...
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine basic block definitions, and skip the machine instructions.
LLVM Basic Block Representation.
bool parseInstrName(StringRef InstrName, unsigned &OpCode)
Try to convert an instruction name to an opcode.
BumpPtrAllocator Allocator
@ kw_cfi_def_cfa_register
TargetIntrinsicInfo - Interface to description of machine instruction set.
static MDTuple * getDistinct(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Return a distinct node.
static bool parseIRConstant(StringRef::iterator Loc, StringRef StringValue, PerFunctionMIParsingState &PFS, const Constant *&C, ErrorCallbackType ErrCB)
constexpr bool hasValue() const
StringRef stringValue() const
Return the token's string value.
@ FCMP_ULT
1 1 0 0 True if unordered or less than
int64_t Offset
Offset - This is an offset from the base Value*.
static LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
void setSectionID(MBBSectionID V)
Sets the section ID for this basic block.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
@ kw_cfi_llvm_def_aspace_cfa
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
static bool verifyScalarSize(uint64_t Size)
void setIsInlineAsmBrIndirectTarget(bool V=true)
Indicates if this is the indirect dest of an INLINEASM_BR.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
static bool verifyVectorElementCount(uint64_t NumElts)
static bool verifyAddrSpace(uint64_t AddrSpace)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI, StringRef Src, SMDiagnostic &Error)
bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src, SMDiagnostic &Error)
This class implements the register bank concept.
Represents a location in source code.
bool isFPPredicate() const
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
const MCPhysReg * ImplicitUses
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
const char * getBufferEnd() const
static MachineOperand CreateImm(int64_t Val)
const SlotMapping & IRSlots
bool getTargetIndex(StringRef Name, int &Index)
Try to convert a name of target index to the corresponding target index.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
(vector float) vec_cmpeq(*A, *B) C
@ ICMP_ULE
unsigned less or equal
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
bool insert(MapEntryTy *KeyValue)
insert - Insert the specified key/value pair into the map.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
void guessSuccessors(const MachineBasicBlock &MBB, SmallVectorImpl< MachineBasicBlock * > &Result, bool &IsFallthrough)
Determine a possible list of successors of a basic block based on the basic block machine operand bei...
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value.
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
static MCCFIInstruction createRestoreState(MCSymbol *L)
.cfi_restore_state Restore the previously saved state.
An arbitrary precision integer that knows its signedness.
unsigned getMainFileID() const
static MachineOperand CreateFI(int Idx)
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
Analysis containing CSE Info
@ FCMP_OLT
0 1 0 0 True if ordered and less than
void setTargetFlags(unsigned F)
Special value supplied for machine level alias analysis.
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals, StringRef Comment="")
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
const TargetRegisterClass * getRegClass(StringRef Name)
Check if the given identifier is a name of a register class.
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
static bool getUnsigned(const MIToken &Token, unsigned &Result, ErrorCallbackType ErrCB)
static bool parseMetadata(const StringRef &Input, uint64_t &FunctionHash, uint32_t &Attributes)
Parse Input that contains metadata.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
SyncScope::ID getOrInsertSyncScopeID(StringRef SSN)
getOrInsertSyncScopeID - Maps synchronization scope name to synchronization scope ID.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
const MemoryBuffer * getMemoryBuffer(unsigned i) const
@ Renamable
Register that may be renamed.
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
mir Rename Register Operands
@ System
Synchronized with respect to all concurrently executing threads.
void setAlignment(Align A)
Set alignment of the basic block.
bool hasIntegerValue() const
An efficient, type-erasing, non-owning reference to a callable.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
AtomicOrdering
Atomic ordering for LLVM's memory model.
DenseMap< Register, VRegInfo * > VRegInfos
@ kw_cfi_adjust_cfa_offset
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
const Value * getIRValue(unsigned Slot)
unsigned getNumRegBanks() const
Get the total number of register banks.
This struct contains the mappings from the slot numbers to unnamed metadata nodes,...
Holds all the information related to register banks.
This is an important base class in LLVM.
bool parseMachineMetadata(PerFunctionMIParsingState &PFS, StringRef Src, SMRange SourceRange, SMDiagnostic &Error)
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
static bool isImplicitOperandIn(const MachineOperand &ImplicitOperand, ArrayRef< ParsedMachineOperand > Operands)
Return true if the parsed machine operands contain a given machine operand.
constexpr bool isUInt< 16 >(uint64_t x)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
VRegInfo & getVRegInfo(Register Num)
static bool parseIRValue(const MIToken &Token, PerFunctionMIParsingState &PFS, const Value *&V, ErrorCallbackType ErrCB)
Module * getParent()
Get the module that this global value is contained inside of...
bool isCall() const
Return true if the instruction is a call.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
This class contains a discriminated union of information about pointers in memory operands,...
This is an important class for using LLVM in a threaded context.
static MCCFIInstruction createNegateRAState(MCSymbol *L)
.cfi_negate_ra_state AArch64 negate RA state.
LLVM_NODISCARD char front() const
front - Get the first character in the string.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
LLVM_NODISCARD std::string lower() const
static MDString * get(LLVMContext &Context, StringRef Str)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Flags
Flags values. These may be or'd together.
const static MBBSectionID ExceptionSectionID
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
constexpr const T & getValue() const &
void setHasAddressTaken()
Set this block to reflect that it potentially is the target of an indirect branch.
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
static Intrinsic::ID lookupIntrinsicID(StringRef Name)
This does the actual lookup of an intrinsic ID which matches the given function name.
@ ICMP_UGE
unsigned greater or equal
@ MONonTemporal
The memory access is non-temporal.
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
A Module instance is used to store all the information related to an LLVM module.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
static void initSlots2Values(const Function &F, DenseMap< unsigned, const Value * > &Slots2Values)
Creates the mapping from slot numbers to function's unnamed IR values.
support::ulittle32_t Word
bool getRegisterByName(StringRef RegName, Register &Reg)
Try to convert a register name to a register number.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
void setIsEHFuncletEntry(bool V=true)
Indicates if this is the entry block of an EH funclet.
Class for arbitrary precision integers.
@ ICMP_SLT
signed less than
bool isIntPredicate() const
unsigned getAttributeEncoding(StringRef EncodingString)
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Scope
Defines the scope in which this symbol should be visible: Default – Visible in the public interface o...
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
StringRef - Represent a constant reference to a string, i.e.
@ ICMP_ULT
unsigned less than
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Type * getType() const
All values are typed, get the type of this value.
@ kw_cfi_aarch64_negate_ra_sign_state
This owns the files read by a parser, handles include stacks, and handles diagnostic wrangling.
static llvm::Error parse(DataExtractor &Data, uint64_t BaseAddr, LineEntryCallback const &Callback)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int Adjustment)
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
static MachineOperand CreateCImm(const ConstantInt *CI)
static TempMDTuple getTemporary(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Return a temporary node.
void setTarget(const TargetSubtargetInfo &NewSubtarget)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
@ MOVolatile
The memory access is volatile.
TargetSubtargetInfo - Generic base class for all target subtargets.
@ MOLoad
The memory access reads data.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const CustomOperand< const MCSubtargetInfo & > Msg[]
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
void replaceAllUsesWith(Metadata *MD)
RAUW a temporary.
ValueSymbolTable * getValueSymbolTable()
getSymbolTable() - Return the symbol table if any, otherwise nullptr.
DenseMap< unsigned, const Value * > Slots2Values
Maps from slot numbers to function's unnamed values.
const char * getBufferStart() const
Function & getFunction()
Return the LLVM function that this machine code represents.
LLVM_NODISCARD StringRef drop_front(size_t N=1) const
Return a StringRef equal to 'this' but with the first N elements dropped.
unsigned getOperationEncoding(StringRef OperationEncodingString)
MDNode * NoAlias
The tag specifying the noalias scope.
std::vector< GlobalValue * > GlobalValues
const char * toString(DWARFSectionKind Kind)
const static MBBSectionID ColdSectionID
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Lightweight error class with error context and mandatory checking.
unsigned getSubRegIndex(StringRef Name)
Check if the given identifier is a name of a subregister index.
@ ICMP_SGE
signed greater or equal
unsigned getNumRegClasses() const
SMDiagnostic GetMessage(SMLoc Loc, DiagKind Kind, const Twine &Msg, ArrayRef< SMRange > Ranges={}, ArrayRef< SMFixIt > FixIts={}) const
Return an SMDiagnostic at the specified location with the specified string.
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
@ MOStore
The memory access writes data.
static bool parseGlobalValue(const MIToken &Token, PerFunctionMIParsingState &PFS, GlobalValue *&GV, ErrorCallbackType ErrCB)
MDNode * TBAA
The tag for type-based alias analysis.
bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS, VRegInfo *&Info, StringRef Src, SMDiagnostic &Error)
Constant * parseConstantValue(StringRef Asm, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots=nullptr)
Parse a type and a constant value in the given string.
static BranchProbability getRaw(uint32_t N)
const uint32_t * getRegMask(StringRef Identifier)
Check if the given identifier is a name of a register mask.
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2)
.cfi_register Previous value of Register1 is saved in register Register2.
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
static MCCFIInstruction createUndefined(MCSymbol *L, unsigned Register)
.cfi_undefined From now on the previous value of Register can't be restored anymore.
@ ICMP_UGT
unsigned greater than
Represents a range in source code.
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
bool is(TokenKind K) const
StringRef::iterator location() const
DenseMap< unsigned, MachineBasicBlock * > MBBSlots
static BlockAddress * get(Function *F, BasicBlock *BB)
Return a BlockAddress for the specified function and basic block.
size_t size() const
size - Get the array size.
Align max(MaybeAlign Lhs, Align Rhs)
static void initSlots2BasicBlocks(const Function &F, DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
static SMLoc getFromPointer(const char *Ptr)
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
A switch()-like statement whose cases are string literals.
bool parseRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
Value * lookup(StringRef Name) const
This method finds the value with the given Name in the the symbol table.
static MCCFIInstruction createRememberState(MCSymbol *L)
.cfi_remember_state Save all current rules for all registers.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a bitmask target flag to the corresponding target flag.
@ Kill
The last use of a register.
bool getDirectTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a direct target flag to the corresponding target flag.
bool Explicit
VReg was explicitly specified in the .mir file.
bool parseMBBReference(PerFunctionMIParsingState &PFS, MachineBasicBlock *&MBB, StringRef Src, SMDiagnostic &Error)
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static MachineOperand CreatePredicate(unsigned Pred)
StringRef lexMIToken(StringRef Source, MIToken &Token, function_ref< void(StringRef::iterator, const Twine &)> ErrorCallback)
Consume a single machine instruction token in the given source and return the remaining source string...
LLVM Value Representation.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
static constexpr LaneBitmask getAll()
static MachineOperand CreateFPImm(const ConstantFP *CFP)
static MCCFIInstruction createWindowSave(MCSymbol *L)
.cfi_window_save SPARC register window is saved.
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
virtual ArrayRef< const uint32_t * > getRegMasks() const =0
Return all the call-preserved register masks defined for this target.
void setFlag(MIFlag Flag)
Set a MI flag.
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
const MCPhysReg * ImplicitDefs
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register)
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)