85 if (&Subtarget == &NewSubtarget)
88 Names2InstrOpCodes.clear();
90 Names2RegMasks.clear();
91 Names2SubRegIndices.clear();
92 Names2TargetIndices.clear();
93 Names2DirectTargetFlags.clear();
94 Names2BitmaskTargetFlags.clear();
95 Names2MMOTargetFlags.clear();
97 initNames2RegClasses();
101void PerTargetMIParsingState::initNames2Regs() {
102 if (!Names2Regs.empty())
106 Names2Regs.insert(std::make_pair(
"noreg", 0));
108 assert(
TRI &&
"Expected target register info");
110 for (
unsigned I = 0, E =
TRI->getNumRegs();
I < E; ++
I) {
115 assert(WasInserted &&
"Expected registers to be unique case-insensitively");
122 auto RegInfo = Names2Regs.find(
RegName);
123 if (RegInfo == Names2Regs.end())
125 Reg = RegInfo->getValue();
131 const auto *
TRI = Subtarget.getRegisterInfo();
132 std::optional<uint8_t> FV =
TRI->getVRegFlagValue(FlagName);
139void PerTargetMIParsingState::initNames2InstrOpCodes() {
140 if (!Names2InstrOpCodes.
empty())
143 assert(
TII &&
"Expected target instruction info");
144 for (
unsigned I = 0, E =
TII->getNumOpcodes();
I < E; ++
I)
150 initNames2InstrOpCodes();
151 auto InstrInfo = Names2InstrOpCodes.find(InstrName);
152 if (InstrInfo == Names2InstrOpCodes.end())
154 OpCode = InstrInfo->getValue();
158void PerTargetMIParsingState::initNames2RegMasks() {
159 if (!Names2RegMasks.
empty())
162 assert(
TRI &&
"Expected target register info");
166 for (
size_t I = 0, E = RegMasks.
size();
I < E; ++
I)
168 std::make_pair(
StringRef(RegMaskNames[
I]).lower(), RegMasks[
I]));
172 initNames2RegMasks();
173 auto RegMaskInfo = Names2RegMasks.find(Identifier);
174 if (RegMaskInfo == Names2RegMasks.end())
176 return RegMaskInfo->getValue();
179void PerTargetMIParsingState::initNames2SubRegIndices() {
180 if (!Names2SubRegIndices.
empty())
183 for (
unsigned I = 1, E =
TRI->getNumSubRegIndices();
I < E; ++
I)
184 Names2SubRegIndices.
insert(
185 std::make_pair(
TRI->getSubRegIndexName(
I),
I));
189 initNames2SubRegIndices();
190 auto SubRegInfo = Names2SubRegIndices.find(Name);
191 if (SubRegInfo == Names2SubRegIndices.end())
193 return SubRegInfo->getValue();
196void PerTargetMIParsingState::initNames2TargetIndices() {
197 if (!Names2TargetIndices.
empty())
200 assert(
TII &&
"Expected target instruction info");
201 auto Indices =
TII->getSerializableTargetIndices();
202 for (
const auto &
I : Indices)
207 initNames2TargetIndices();
208 auto IndexInfo = Names2TargetIndices.find(Name);
209 if (IndexInfo == Names2TargetIndices.end())
211 Index = IndexInfo->second;
215void PerTargetMIParsingState::initNames2DirectTargetFlags() {
216 if (!Names2DirectTargetFlags.
empty())
220 assert(
TII &&
"Expected target instruction info");
221 auto Flags =
TII->getSerializableDirectMachineOperandTargetFlags();
222 for (
const auto &
I : Flags)
223 Names2DirectTargetFlags.
insert(
229 initNames2DirectTargetFlags();
230 auto FlagInfo = Names2DirectTargetFlags.find(Name);
231 if (FlagInfo == Names2DirectTargetFlags.end())
233 Flag = FlagInfo->second;
237void PerTargetMIParsingState::initNames2BitmaskTargetFlags() {
238 if (!Names2BitmaskTargetFlags.
empty())
242 assert(
TII &&
"Expected target instruction info");
243 auto Flags =
TII->getSerializableBitmaskMachineOperandTargetFlags();
244 for (
const auto &
I : Flags)
245 Names2BitmaskTargetFlags.
insert(
251 initNames2BitmaskTargetFlags();
252 auto FlagInfo = Names2BitmaskTargetFlags.find(Name);
253 if (FlagInfo == Names2BitmaskTargetFlags.end())
255 Flag = FlagInfo->second;
259void PerTargetMIParsingState::initNames2MMOTargetFlags() {
260 if (!Names2MMOTargetFlags.
empty())
264 assert(
TII &&
"Expected target instruction info");
265 auto Flags =
TII->getSerializableMachineMemOperandTargetFlags();
266 for (
const auto &
I : Flags)
272 initNames2MMOTargetFlags();
273 auto FlagInfo = Names2MMOTargetFlags.find(Name);
274 if (FlagInfo == Names2MMOTargetFlags.end())
276 Flag = FlagInfo->second;
280void PerTargetMIParsingState::initNames2RegClasses() {
281 if (!Names2RegClasses.
empty())
285 for (
unsigned I = 0, E =
TRI->getNumRegClasses();
I < E; ++
I) {
286 const auto *RC =
TRI->getRegClass(
I);
292void PerTargetMIParsingState::initNames2RegBanks() {
293 if (!Names2RegBanks.empty())
296 const RegisterBankInfo *RBI = Subtarget.getRegBankInfo();
304 Names2RegBanks.insert(
305 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank));
311 auto RegClassInfo = Names2RegClasses.find(Name);
312 if (RegClassInfo == Names2RegClasses.end())
314 return RegClassInfo->getValue();
318 auto RegBankInfo = Names2RegBanks.find(Name);
319 if (RegBankInfo == Names2RegBanks.end())
321 return RegBankInfo->getValue();
335 I.first->second = Info;
337 return *
I.first->second;
346 Info->
VReg =
MF.getRegInfo().createIncompleteVirtualRegister(
RegName);
347 I.first->second = Info;
349 return *
I.first->second;
357 Slots2Values.
insert(std::make_pair(
unsigned(Slot), V));
365 for (
const auto &Arg :
F.args())
367 for (
const auto &BB :
F) {
369 for (
const auto &
I : BB)
384struct ParsedMachineOperand {
388 std::optional<unsigned> TiedDefIdx;
392 std::optional<unsigned> &TiedDefIdx)
393 : Operand(Operand), Begin(Begin),
End(
End), TiedDefIdx(TiedDefIdx) {
396 "Only used register operands can be tied");
403 StringRef
Source, CurrentSource;
405 PerFunctionMIParsingState &PFS;
407 DenseMap<unsigned, const BasicBlock *> Slots2BasicBlocks;
410 MIParser(PerFunctionMIParsingState &PFS, SMDiagnostic &
Error,
415 void lex(
unsigned SkipChar = 0);
428 parseBasicBlockDefinitions(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
429 bool parseBasicBlocks();
431 bool parseStandaloneMBB(MachineBasicBlock *&
MBB);
433 bool parseStandaloneVirtualRegister(VRegInfo *&Info);
435 bool parseStandaloneStackObject(
int &FI);
436 bool parseStandaloneMDNode(MDNode *&Node);
439 parseBasicBlockDefinition(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
440 bool parseBasicBlock(MachineBasicBlock &
MBB,
441 MachineBasicBlock *&AddFalthroughFrom);
442 bool parseBasicBlockLiveins(MachineBasicBlock &
MBB);
443 bool parseBasicBlockSuccessors(MachineBasicBlock &
MBB);
446 bool parseVirtualRegister(VRegInfo *&Info);
447 bool parseNamedVirtualRegister(VRegInfo *&Info);
448 bool parseRegister(
Register &
Reg, VRegInfo *&VRegInfo);
449 bool parseRegisterFlag(
RegState &Flags);
450 bool parseRegisterClassOrBank(VRegInfo &RegInfo);
451 bool parseSubRegisterIndex(
unsigned &SubReg);
452 bool parseRegisterTiedDefIndex(
unsigned &TiedDefIdx);
453 bool parseRegisterOperand(MachineOperand &Dest,
454 std::optional<unsigned> &TiedDefIdx,
456 bool parseImmediateOperand(MachineOperand &Dest);
457 bool parseSymbolicInlineAsmOperand(
unsigned OpIdx, MachineOperand &Dest);
462 bool parseTypedImmediateOperand(MachineOperand &Dest);
463 bool parseFPImmediateOperand(MachineOperand &Dest);
465 bool parseMBBOperand(MachineOperand &Dest);
466 bool parseStackFrameIndex(
int &FI);
467 bool parseStackObjectOperand(MachineOperand &Dest);
468 bool parseFixedStackFrameIndex(
int &FI);
469 bool parseFixedStackObjectOperand(MachineOperand &Dest);
471 bool parseGlobalAddressOperand(MachineOperand &Dest);
472 bool parseConstantPoolIndexOperand(MachineOperand &Dest);
473 bool parseSubRegisterIndexOperand(MachineOperand &Dest);
474 bool parseJumpTableIndexOperand(MachineOperand &Dest);
475 bool parseExternalSymbolOperand(MachineOperand &Dest);
476 bool parseMCSymbolOperand(MachineOperand &Dest);
478 bool parseDIExpression(MDNode *&Expr);
479 bool parseDILocation(MDNode *&Expr);
480 bool parseMetadataOperand(MachineOperand &Dest);
481 bool parseCFIOffset(
int &
Offset);
482 bool parseCFIUnsigned(
unsigned &
Value);
483 bool parseCFIRegister(
unsigned &
Reg);
485 bool parseCFIEscapeValues(std::string&
Values);
486 bool parseCFIOperand(MachineOperand &Dest);
487 bool parseIRBlock(BasicBlock *&BB,
const Function &
F);
488 bool parseBlockAddressOperand(MachineOperand &Dest);
489 bool parseIntrinsicOperand(MachineOperand &Dest);
490 bool parsePredicateOperand(MachineOperand &Dest);
491 bool parseShuffleMaskOperand(MachineOperand &Dest);
492 bool parseTargetIndexOperand(MachineOperand &Dest);
493 bool parseDbgInstrRefOperand(MachineOperand &Dest);
494 bool parseCustomRegisterMaskOperand(MachineOperand &Dest);
495 bool parseLaneMaskOperand(MachineOperand &Dest);
496 bool parseLiveoutRegisterMaskOperand(MachineOperand &Dest);
497 bool parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
498 MachineOperand &Dest,
499 std::optional<unsigned> &TiedDefIdx);
500 bool parseMachineOperandAndTargetFlags(
const unsigned OpCode,
501 const unsigned OpIdx,
502 MachineOperand &Dest,
503 std::optional<unsigned> &TiedDefIdx);
504 bool parseOffset(int64_t &
Offset);
505 bool parseIRBlockAddressTaken(BasicBlock *&BB);
507 bool parseAddrspace(
unsigned &Addrspace);
508 bool parseSectionID(std::optional<MBBSectionID> &SID);
509 bool parseBBID(std::optional<UniqueBBID> &BBID);
510 bool parseCallFrameSize(
unsigned &CallFrameSize);
511 bool parseMaxBytesForAlignment(
unsigned &MaxBytesForAlignment);
513 bool parseOperandsOffset(MachineOperand &
Op);
516 bool parseMemoryPseudoSourceValue(
const PseudoSourceValue *&PSV);
517 bool parseMachinePointerInfo(MachinePointerInfo &Dest);
520 bool parseMachineMemoryOperand(MachineMemOperand *&Dest);
521 bool parsePreOrPostInstrSymbol(MCSymbol *&Symbol);
522 bool parseHeapAllocMarker(MDNode *&Node);
523 bool parsePCSections(MDNode *&Node);
524 bool parseMMRA(MDNode *&Node);
526 bool parseTargetImmMnemonic(
const unsigned OpCode,
const unsigned OpIdx,
527 MachineOperand &Dest,
const MIRFormatter &MF);
554 bool parseInstruction(
unsigned &OpCode,
unsigned &Flags);
556 bool assignRegisterTies(MachineInstr &
MI,
560 const MCInstrDesc &MCID);
566 MCSymbol *getOrCreateMCSymbol(StringRef Name);
570 bool parseStringConstant(std::string &Result);
580void MIParser::lex(
unsigned SkipChar) {
582 CurrentSource.substr(SkipChar), Token,
586bool MIParser::error(
const Twine &
Msg) {
return error(Token.location(),
Msg); }
621 return "<unknown token>";
626 if (Token.isNot(TokenKind))
633 if (Token.isNot(TokenKind))
640bool MIParser::parseSectionID(std::optional<MBBSectionID> &SID) {
646 return error(
"Unknown Section ID");
649 const StringRef &S = Token.stringValue();
650 if (S ==
"Exception")
652 else if (S ==
"Cold")
655 return error(
"Unknown Section ID");
662bool MIParser::parseBBID(std::optional<UniqueBBID> &BBID) {
664 return error(
"expected 'bb_id'");
667 unsigned CloneID = 0;
670 auto Parts = S.
split(
'.');
671 if (Parts.first.getAsInteger(10, BaseID) ||
672 Parts.second.getAsInteger(10, CloneID))
673 return error(
"Unknown BB ID");
677 return error(
"Unknown BB ID");
682 return error(
"Unknown Clone ID");
686 return error(
"Unknown Clone ID");
690 BBID = {BaseID, CloneID};
695bool MIParser::parseCallFrameSize(
unsigned &CallFrameSize) {
700 return error(
"Unknown call frame size");
701 CallFrameSize =
Value;
708bool MIParser::parseMaxBytesForAlignment(
unsigned &MaxBytesForAlignment) {
712 return error(
"expected an integer literal after 'max-bytes-for-alignment'");
716 MaxBytesForAlignment =
Value;
723 std::optional<UniqueBBID> BBID;
732bool MIParser::parseBasicBlockDefinition(
738 auto Loc = Token.location();
739 auto Name = Token.stringValue();
741 bool MachineBlockAddressTaken =
false;
743 bool IsLandingPad =
false;
744 bool IsInlineAsmBrIndirectTarget =
false;
745 bool IsEHFuncletEntry =
false;
746 bool IsEHScopeEntry =
false;
747 bool IsCleanupFuncletEntry =
false;
748 bool IsEHContTarget =
false;
749 std::optional<MBBSectionID> SectionID;
751 unsigned MaxBytesForAlignment = 0;
752 std::optional<UniqueBBID> BBID;
753 unsigned CallFrameSize = 0;
758 switch (Token.kind()) {
760 MachineBlockAddressTaken =
true;
764 if (parseIRBlockAddressTaken(AddressTakenIRBlock))
772 IsInlineAsmBrIndirectTarget =
true;
776 IsEHFuncletEntry =
true;
780 IsEHScopeEntry =
true;
784 IsCleanupFuncletEntry =
true;
788 IsEHContTarget =
true;
796 if (parseMaxBytesForAlignment(MaxBytesForAlignment))
802 if (parseIRBlock(BB, MF.getFunction()))
807 if (parseSectionID(SectionID))
815 if (parseCallFrameSize(CallFrameSize))
830 MF.getFunction().getValueSymbolTable()->lookup(Name));
833 "' is not defined in the function '" +
836 auto *
MBB = MF.CreateMachineBasicBlock(BB, BBID);
838 bool WasInserted = MBBSlots.
insert(std::make_pair(ID,
MBB)).second;
840 return error(
Loc,
Twine(
"redefinition of machine basic block with id #") +
844 else if (MaxBytesForAlignment)
845 return error(
Loc,
"'max-bytes-for-alignment' requires 'align'");
847 if (MachineBlockAddressTaken)
849 if (AddressTakenIRBlock)
865bool MIParser::parseBasicBlockDefinitions(
871 if (Token.isErrorOrEOF())
872 return Token.isError();
874 return error(
"expected a basic block definition before instructions");
875 unsigned BraceDepth = 0;
877 if (parseBasicBlockDefinition(MBBSlots))
879 bool IsAfterNewline =
false;
883 Token.isErrorOrEOF())
886 return error(
"basic block definition should be located at the start of "
889 IsAfterNewline =
true;
892 IsAfterNewline =
false;
897 return error(
"extraneous closing brace ('}')");
903 if (!Token.isError() && BraceDepth)
904 return error(
"expected '}'");
905 }
while (!Token.isErrorOrEOF());
906 return Token.isError();
914 if (Token.isNewlineOrEOF())
918 return error(
"expected a named register");
920 if (parseNamedRegister(
Reg))
928 return error(
"expected a lane mask");
930 "Use correct get-function for lane mask");
933 return error(
"invalid lane mask value");
947 if (Token.isNewlineOrEOF())
951 return error(
"expected a machine basic block reference");
960 return error(
"expected an integer literal after '('");
994 bool ExplicitSuccessors =
false;
997 if (parseBasicBlockSuccessors(
MBB))
999 ExplicitSuccessors =
true;
1001 if (parseBasicBlockLiveins(
MBB))
1008 if (!Token.isNewlineOrEOF())
1009 return error(
"expected line break at the end of a list");
1014 bool IsInBundle =
false;
1038 return error(
"nested instruction bundles are not allowed");
1047 assert(Token.isNewlineOrEOF() &&
"MI is not fully parsed");
1052 if (!ExplicitSuccessors) {
1059 if (IsFallthrough) {
1060 AddFalthroughFrom = &
MBB;
1069bool MIParser::parseBasicBlocks() {
1074 if (Token.isErrorOrEOF())
1075 return Token.isError();
1084 if (AddFalthroughFrom) {
1088 AddFalthroughFrom =
nullptr;
1090 if (parseBasicBlock(*
MBB, AddFalthroughFrom))
1103 while (Token.isRegister() || Token.isRegisterFlag()) {
1104 auto Loc = Token.location();
1105 std::optional<unsigned> TiedDefIdx;
1106 if (parseRegisterOperand(MO, TiedDefIdx,
true))
1109 ParsedMachineOperand(MO,
Loc, Token.location(), TiedDefIdx));
1118 if (Token.isError() || parseInstruction(OpCode, Flags))
1131 auto Loc = Token.location();
1132 std::optional<unsigned> TiedDefIdx;
1133 if (parseMachineOperandAndTargetFlags(OpCode,
Operands.size(), MO, TiedDefIdx))
1136 ParsedMachineOperand(MO,
Loc, Token.location(), TiedDefIdx));
1141 return error(
"expected ',' before the next machine operand");
1145 MCSymbol *PreInstrSymbol =
nullptr;
1147 if (parsePreOrPostInstrSymbol(PreInstrSymbol))
1149 MCSymbol *PostInstrSymbol =
nullptr;
1151 if (parsePreOrPostInstrSymbol(PostInstrSymbol))
1153 MDNode *HeapAllocMarker =
nullptr;
1155 if (parseHeapAllocMarker(HeapAllocMarker))
1157 MDNode *PCSections =
nullptr;
1159 if (parsePCSections(PCSections))
1164 unsigned CFIType = 0;
1168 return error(
"expected an integer literal after 'cfi-type'");
1186 unsigned InstrNum = 0;
1190 return error(
"expected an integer literal after 'debug-instr-number'");
1207 if (parseDILocation(Node))
1210 return error(
"expected a metadata node after 'debug-location'");
1214 return error(
"referenced metadata is not a DILocation");
1221 while (!Token.isNewlineOrEOF()) {
1223 if (parseMachineMemoryOperand(
MemOp))
1226 if (Token.isNewlineOrEOF())
1231 return error(
"expected ',' before the next machine memory operand");
1236 const auto &
MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
1237 if (!
MCID.isVariadic()) {
1243 MI = MF.CreateMachineInstr(
MCID, DebugLocation,
true);
1244 MI->setFlags(Flags);
1248 for (
const auto &Operand :
Operands)
1249 MI->addOperand(MF, Operand.Operand);
1254 MI->setPreInstrSymbol(MF, PreInstrSymbol);
1255 if (PostInstrSymbol)
1256 MI->setPostInstrSymbol(MF, PostInstrSymbol);
1257 if (HeapAllocMarker)
1258 MI->setHeapAllocMarker(MF, HeapAllocMarker);
1260 MI->setPCSections(MF, PCSections);
1262 MI->setMMRAMetadata(MF, MMRA);
1264 MI->setCFIType(MF, CFIType);
1266 MI->setDeactivationSymbol(MF, DS);
1267 if (!MemOperands.
empty())
1268 MI->setMemRefs(MF, MemOperands);
1270 MI->setDebugInstrNum(InstrNum);
1277 return error(
"expected a machine basic block reference");
1283 "expected end of string after the machine basic block reference");
1287bool MIParser::parseStandaloneNamedRegister(
Register &
Reg) {
1290 return error(
"expected a named register");
1291 if (parseNamedRegister(
Reg))
1295 return error(
"expected end of string after the register reference");
1299bool MIParser::parseStandaloneVirtualRegister(
VRegInfo *&Info) {
1302 return error(
"expected a virtual register");
1303 if (parseVirtualRegister(Info))
1307 return error(
"expected end of string after the register reference");
1311bool MIParser::parseStandaloneRegister(
Register &
Reg) {
1315 return error(
"expected either a named or virtual register");
1318 if (parseRegister(
Reg, Info))
1323 return error(
"expected end of string after the register reference");
1327bool MIParser::parseStandaloneStackObject(
int &FI) {
1330 return error(
"expected a stack object");
1331 if (parseStackFrameIndex(FI))
1334 return error(
"expected end of string after the stack object reference");
1338bool MIParser::parseStandaloneMDNode(
MDNode *&Node) {
1344 if (parseDIExpression(Node))
1347 if (parseDILocation(Node))
1350 return error(
"expected a metadata node");
1353 return error(
"expected end of string after the metadata node");
1359 return MO.
isDef() ?
"implicit-def" :
"implicit";
1364 assert(
Reg.isPhysical() &&
"expected phys reg");
1392 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
1393 assert(
TRI &&
"Expected target register info");
1394 for (
const auto &
I : ImplicitOperands) {
1398 Twine(
"missing implicit register operand '") +
1405bool MIParser::parseInstruction(
unsigned &OpCode,
unsigned &Flags) {
1480 return error(
"expected a machine instruction");
1481 StringRef InstrName = Token.stringValue();
1482 if (PFS.Target.parseInstrName(InstrName, OpCode))
1483 return error(
Twine(
"unknown machine instruction name '") + InstrName +
"'");
1491 if (PFS.Target.getRegisterByName(Name,
Reg))
1492 return error(
Twine(
"unknown register name '") + Name +
"'");
1496bool MIParser::parseNamedVirtualRegister(
VRegInfo *&Info) {
1501 Info = &PFS.getVRegInfoNamed(Name);
1505bool MIParser::parseVirtualRegister(
VRegInfo *&Info) {
1507 return parseNamedVirtualRegister(Info);
1512 Info = &PFS.getVRegInfo(ID);
1517 switch (Token.kind()) {
1522 return parseNamedRegister(
Reg);
1525 if (parseVirtualRegister(Info))
1535bool MIParser::parseRegisterClassOrBank(
VRegInfo &RegInfo) {
1537 return error(
"expected '_', register class, or register bank name");
1546 switch (RegInfo.
Kind) {
1552 return error(
Loc,
Twine(
"conflicting register classes, previously: ") +
1561 return error(
Loc,
"register class specification on generic register");
1569 RegBank = PFS.Target.getRegBank(Name);
1571 return error(
Loc,
"expected '_', register class, or register bank name");
1576 switch (RegInfo.
Kind) {
1582 return error(
Loc,
"conflicting generic register banks");
1588 return error(
Loc,
"register bank specification on normal register");
1593bool MIParser::parseRegisterFlag(
RegState &Flags) {
1595 switch (Token.kind()) {
1629 if (OldFlags == Flags)
1632 return error(
"duplicate '" + Token.stringValue() +
"' register flag");
1637bool MIParser::parseSubRegisterIndex(
unsigned &SubReg) {
1641 return error(
"expected a subregister index after '.'");
1642 auto Name = Token.stringValue();
1643 SubReg = PFS.Target.getSubRegIndex(Name);
1645 return error(
Twine(
"use of unknown subregister index '") + Name +
"'");
1650bool MIParser::parseRegisterTiedDefIndex(
unsigned &TiedDefIdx) {
1654 return error(
"expected an integer literal after 'tied-def'");
1669 unsigned DefIdx = *
Operands[
I].TiedDefIdx;
1672 Twine(
"use of invalid tied-def operand index '" +
1673 Twine(DefIdx) +
"'; instruction has only ") +
1675 const auto &DefOperand =
Operands[DefIdx].Operand;
1676 if (!DefOperand.isReg() || !DefOperand.isDef())
1679 Twine(
"use of invalid tied-def operand index '") +
1680 Twine(DefIdx) +
"'; the operand #" +
Twine(DefIdx) +
1681 " isn't a defined register");
1683 for (
const auto &TiedPair : TiedRegisterPairs) {
1684 if (TiedPair.first == DefIdx)
1686 Twine(
"the tied-def operand #") +
Twine(DefIdx) +
1687 " is already tied with another register operand");
1689 TiedRegisterPairs.push_back(std::make_pair(DefIdx,
I));
1693 for (
const auto &TiedPair : TiedRegisterPairs)
1694 MI.tieOperands(TiedPair.first, TiedPair.second);
1699 std::optional<unsigned> &TiedDefIdx,
1702 while (Token.isRegisterFlag()) {
1703 if (parseRegisterFlag(Flags))
1708 if (!Token.isRegister())
1709 return error(
"expected a register after register flags");
1712 if (parseRegister(
Reg, RegInfo))
1715 unsigned SubReg = 0;
1717 if (parseSubRegisterIndex(SubReg))
1720 return error(
"subregister index expects a virtual register");
1724 return error(
"register class specification expects a virtual register");
1726 if (parseRegisterClassOrBank(*RegInfo))
1735 return error(
"tied-def not supported for defs");
1737 if (parseRegisterTiedDefIndex(Idx))
1742 return error(
"unexpected type on physical register");
1746 if (parseLowLevelType(Token.location(), Ty))
1748 :
error(
"expected tied-def or low-level type after '('");
1755 return error(
"inconsistent type for generic virtual register");
1765 return error(
"generic virtual registers must have a type");
1770 return error(
"cannot have a killed def operand");
1773 return error(
"cannot have a dead use operand");
1790 const APSInt &
Int = Token.integerValue();
1791 if (
auto SImm =
Int.trySExtValue();
Int.isSigned() && SImm.has_value())
1793 else if (
auto UImm =
Int.tryZExtValue(); !
Int.isSigned() && UImm.has_value())
1796 return error(
"integer literal is too large to be an immediate operand");
1801bool MIParser::parseSymbolicInlineAsmOperand(
unsigned OpIdx,
1805 "expected symbolic inline asm operand");
1809 unsigned ExtraInfo = 0;
1814 StringRef FlagName = Token.stringValue();
1822 .
Case(
"attdialect", 0)
1826 return error(
"unknown inline asm extra info flag '" + FlagName +
"'");
1837 StringRef KindStr = Token.stringValue();
1848 if (K == InvalidKind)
1849 return error(
"unknown inline asm operand kind '" + KindStr +
"'");
1860 return error(
"expected ':' after 'tiedto'");
1863 return error(
"expected '$N' operand number after 'tiedto:'");
1865 if (Token.stringValue().getAsInteger(10, OperandNo))
1866 return error(
"invalid operand number in tiedto constraint");
1869 F.setMatchingOp(OperandNo);
1881 "expected register class or memory constraint name after ':'");
1883 StringRef ConstraintStr = Token.stringValue();
1884 if (
F.isMemKind()) {
1917 return error(
"unknown memory constraint '" + ConstraintStr +
"'");
1918 F.setMemConstraint(CC);
1919 }
else if (
F.isRegDefKind() ||
F.isRegUseKind() ||
1920 F.isRegDefEarlyClobberKind()) {
1922 PFS.Target.getRegClass(ConstraintStr.
lower());
1924 return error(
"unknown register class '" + ConstraintStr +
"'");
1925 F.setRegClass(RC->
getID());
1935 if (!
F.isRegDefKind() && !
F.isRegUseKind() && !
F.isRegDefEarlyClobberKind())
1936 return error(
"only a register operand can be 'foldable'");
1938 F.setRegMayBeFolded(
true);
1946bool MIParser::parseTargetImmMnemonic(
const unsigned OpCode,
1947 const unsigned OpIdx,
1951 auto Loc = Token.location();
1957 Len += Token.range().size();
1966 Src =
StringRef(
Loc, Len + Token.stringValue().size());
1971 ->
bool { return error(Loc, Msg); }))
1983 auto Source = StringValue.
str();
1988 return ErrCB(
Loc + Err.getColumnNo(), Err.getMessage());
1994 return ::parseIRConstant(
1995 Loc, StringValue, PFS,
C,
2015 return NumElts != 0 && (HasVScale || NumElts != 1) &&
isUInt<16>(NumElts);
2029 "expected integers after 's'/'i'/'f'/'bf'/'p' type identifier");
2032 bool Scalar = Token.range().starts_with(
"s");
2033 if (Scalar || Token.range().starts_with(
"i")) {
2042 return error(
"invalid size for scalar type");
2049 if (Token.range().starts_with(
"p")) {
2053 return error(
"invalid address space number");
2060 if (Token.range().starts_with(
"f") || Token.range().starts_with(
"bf")) {
2063 return error(
"invalid size for scalar type");
2065 if (Token.range().starts_with(
"bf") && ScalarSize != 16)
2066 return error(
"invalid size for bfloat");
2069 :
LLT::floatIEEE(ScalarSize);
2076 return error(
Loc,
"expected tN, pA, <M x tN>, <M x pA>, <vscale x M x tN>, "
2077 "or <vscale x M x pA> for GlobalISel type, "
2078 "where t = {'s', 'i', 'f', 'bf'}");
2087 "expected <vscale x M x tN>, where t = {'s', 'i', 'f', 'bf', 'p'}");
2091 auto GetError = [
this, &HasVScale,
Loc]() {
2093 return error(
Loc,
"expected <vscale x M x tN> for vector type, where t = "
2094 "{'s', 'i', 'f', 'bf', 'p'}");
2095 return error(
Loc,
"expected <M x tN> for vector type, where t = {'s', 'i', "
2101 uint64_t NumElements = Token.integerValue().getZExtValue();
2103 return error(
"invalid number of vector elements");
2111 StringRef VectorTyDigits = Token.range();
2120 "expected integers after 's'/'i'/'f'/'bf'/'p' type identifier");
2122 Scalar = Token.range().starts_with(
"s");
2123 if (Scalar || Token.range().starts_with(
"i")) {
2126 return error(
"invalid size for scalar element in vector");
2128 }
else if (Token.range().starts_with(
"p")) {
2132 return error(
"invalid address space number");
2135 }
else if (Token.range().starts_with(
"f")) {
2138 return error(
"invalid size for float element in vector");
2140 }
else if (Token.range().starts_with(
"bf")) {
2143 return error(
"invalid size for bfloat element in vector");
2165 return error(
"a typed immediate operand should start with one of 'i', "
2166 "'s', 'f', 'bf', or 'p'");
2169 "expected integers after 'i'/'s'/'f'/'bf'/'p' type identifier");
2171 auto Loc = Token.location();
2175 !(Token.range() ==
"true" || Token.range() ==
"false"))
2176 return error(
"expected an integer literal");
2186 auto Loc = Token.location();
2190 return error(
"expected a floating point literal");
2201 assert(S[0] ==
'0' && tolower(S[1]) ==
'x');
2203 if (!isxdigit(S[2]))
2206 APInt A(V.size()*4, V, 16);
2210 unsigned NumBits = (
A == 0) ? 32 :
A.getActiveBits();
2221 return ErrCB(Token.
location(),
"expected unsigned integer");
2224 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2232 if (
A.getBitWidth() > 32)
2233 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2234 Result =
A.getZExtValue();
2240bool MIParser::getUnsigned(
unsigned &Result) {
2241 return ::getUnsigned(
2253 auto MBBInfo = PFS.MBBSlots.find(
Number);
2254 if (MBBInfo == PFS.MBBSlots.end())
2255 return error(
Twine(
"use of undefined machine basic block #") +
2257 MBB = MBBInfo->second;
2260 if (!Token.stringValue().empty() && Token.stringValue() !=
MBB->
getName())
2262 " isn't '" + Token.stringValue() +
"'");
2275bool MIParser::parseStackFrameIndex(
int &FI) {
2280 auto ObjectInfo = PFS.StackObjectSlots.find(ID);
2281 if (ObjectInfo == PFS.StackObjectSlots.end())
2282 return error(
Twine(
"use of undefined stack object '%stack.") +
Twine(ID) +
2285 if (
const auto *Alloca =
2286 MF.getFrameInfo().getObjectAllocation(ObjectInfo->second))
2287 Name = Alloca->getName();
2288 if (!Token.stringValue().empty() && Token.stringValue() != Name)
2289 return error(
Twine(
"the name of the stack object '%stack.") +
Twine(ID) +
2290 "' isn't '" + Token.stringValue() +
"'");
2292 FI = ObjectInfo->second;
2298 if (parseStackFrameIndex(FI))
2304bool MIParser::parseFixedStackFrameIndex(
int &FI) {
2309 auto ObjectInfo = PFS.FixedStackObjectSlots.find(ID);
2310 if (ObjectInfo == PFS.FixedStackObjectSlots.end())
2311 return error(
Twine(
"use of undefined fixed stack object '%fixed-stack.") +
2314 FI = ObjectInfo->second;
2318bool MIParser::parseFixedStackObjectOperand(
MachineOperand &Dest) {
2320 if (parseFixedStackFrameIndex(FI))
2329 switch (Token.
kind()) {
2334 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '") +
2335 Token.
range() +
"'");
2344 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '@") +
2345 Twine(GVIdx) +
"'");
2354bool MIParser::parseGlobalValue(
GlobalValue *&GV) {
2355 return ::parseGlobalValue(
2368 if (parseOperandsOffset(Dest))
2373bool MIParser::parseConstantPoolIndexOperand(
MachineOperand &Dest) {
2380 return error(
"use of undefined constant '%const." +
Twine(ID) +
"'");
2383 if (parseOperandsOffset(Dest))
2393 auto JumpTableEntryInfo = PFS.JumpTableSlots.find(ID);
2394 if (JumpTableEntryInfo == PFS.JumpTableSlots.end())
2395 return error(
"use of undefined jump table '%jump-table." +
Twine(ID) +
"'");
2403 const char *
Symbol = MF.createExternalSymbolName(Token.stringValue());
2406 if (parseOperandsOffset(Dest))
2416 if (parseOperandsOffset(Dest))
2421bool MIParser::parseSubRegisterIndexOperand(
MachineOperand &Dest) {
2424 unsigned SubRegIndex = PFS.Target.getSubRegIndex(Token.stringValue());
2425 if (SubRegIndex == 0)
2426 return error(
Twine(
"unknown subregister index '") + Name +
"'");
2432bool MIParser::parseMDNode(
MDNode *&Node) {
2435 auto Loc = Token.location();
2438 return error(
"expected metadata id after '!'");
2442 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(ID);
2443 if (NodeInfo == PFS.IRSlots.MetadataNodes.end()) {
2444 NodeInfo = PFS.MachineMetadataNodes.find(ID);
2445 if (NodeInfo == PFS.MachineMetadataNodes.end())
2446 return error(
Loc,
"use of undefined metadata '!" +
Twine(ID) +
"'");
2449 Node = NodeInfo->second.get();
2453bool MIParser::parseDIExpression(
MDNode *&Expr) {
2456 CurrentSource,
Read,
Error, *PFS.MF.getFunction().getParent(),
2458 CurrentSource = CurrentSource.substr(
Read);
2465bool MIParser::parseDILocation(
MDNode *&
Loc) {
2469 bool HaveLine =
false;
2471 unsigned Column = 0;
2473 MDNode *InlinedAt =
nullptr;
2474 bool ImplicitCode =
false;
2477 MDNode *IRLayers =
nullptr;
2485 if (Token.stringValue() ==
"line") {
2490 Token.integerValue().isSigned())
2491 return error(
"expected unsigned integer");
2492 Line = Token.integerValue().getZExtValue();
2497 if (Token.stringValue() ==
"column") {
2502 Token.integerValue().isSigned())
2503 return error(
"expected unsigned integer");
2504 Column = Token.integerValue().getZExtValue();
2508 if (Token.stringValue() ==
"scope") {
2513 return error(
"expected metadata node");
2515 return error(
"expected DIScope node");
2518 if (Token.stringValue() ==
"inlinedAt") {
2526 if (parseDILocation(InlinedAt))
2529 return error(
"expected metadata node");
2532 return error(
"expected DILocation node");
2535 if (Token.stringValue() ==
"isImplicitCode") {
2540 return error(
"expected true/false");
2544 if (Token.stringValue() ==
"true")
2545 ImplicitCode =
true;
2546 else if (Token.stringValue() ==
"false")
2547 ImplicitCode =
false;
2549 return error(
"expected true/false");
2553 if (Token.stringValue() ==
"atomGroup") {
2558 Token.integerValue().isSigned())
2559 return error(
"expected unsigned integer");
2560 AtomGroup = Token.integerValue().getZExtValue();
2564 if (Token.stringValue() ==
"atomRank") {
2569 Token.integerValue().isSigned())
2570 return error(
"expected unsigned integer");
2571 AtomRank = Token.integerValue().getZExtValue();
2575 if (Token.stringValue() ==
"irlayers") {
2580 return error(
"expected metadata node");
2582 return error(
"expected DILayerLocList node");
2586 return error(
Twine(
"invalid DILocation argument '") +
2587 Token.stringValue() +
"'");
2595 return error(
"DILocation requires line number");
2597 return error(
"DILocation requires a scope");
2600 InlinedAt, ImplicitCode, AtomGroup, AtomRank, IRLayers);
2610 if (parseDIExpression(Node))
2617bool MIParser::parseCFIOffset(
int &
Offset) {
2619 return error(
"expected a cfi offset");
2620 if (Token.integerValue().getSignificantBits() > 32)
2621 return error(
"expected a 32 bit integer (the cfi offset is too large)");
2622 Offset = (int)Token.integerValue().getExtValue();
2627bool MIParser::parseCFIUnsigned(
unsigned &
Value) {
2634bool MIParser::parseCFIRegister(
unsigned &
Reg) {
2636 return error(
"expected a cfi register");
2638 if (parseNamedRegister(LLVMReg))
2640 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
2641 assert(
TRI &&
"Expected target register info");
2642 int DwarfReg =
TRI->getDwarfRegNum(LLVMReg,
true);
2644 return error(
"invalid DWARF register");
2645 Reg = (unsigned)DwarfReg;
2650bool MIParser::parseCFIAddressSpace(
unsigned &
AddressSpace) {
2652 return error(
"expected a cfi address space literal");
2653 if (Token.integerValue().isSigned())
2654 return error(
"expected an unsigned integer (cfi address space)");
2660bool MIParser::parseCFIEscapeValues(std::string &
Values) {
2663 return error(
"expected a hexadecimal literal");
2667 if (
Value > UINT8_MAX)
2668 return error(
"expected a 8-bit integer (too large)");
2676 auto Kind = Token.kind();
2684 if (parseCFIRegister(
Reg))
2699 CFIIndex = MF.addFrameInst(
2703 if (parseCFIRegister(
Reg))
2709 if (parseCFIOffset(
Offset))
2715 if (parseCFIOffset(
Offset))
2717 CFIIndex = MF.addFrameInst(
2739 if (parseCFIRegister(
Reg))
2747 if (parseCFIRegister(
Reg))
2754 parseCFIRegister(Reg2))
2777 PACSym = getOrCreateMCSymbol(Token.stringValue());
2779 CFIIndex = MF.addFrameInst(
2783 if (parseCFIOffset(
Offset))
2785 CFIIndex = MF.addFrameInst(
2788 return error(
"expected '<mcsymbol ...>' or integer offset for "
2789 "cfi_set_ra_state");
2794 unsigned Reg, R1,
R2;
2795 unsigned R1Size, R2Size;
2800 parseCFIUnsigned(R2Size))
2804 nullptr,
Reg, R1, R1Size,
R2, R2Size));
2808 std::vector<MCCFIInstruction::VectorRegisterWithLane> VectorRegisters;
2813 unsigned Lane,
Size;
2816 parseCFIUnsigned(
Size))
2818 VectorRegisters.push_back({VR, Lane,
Size});
2822 nullptr,
Reg, std::move(VectorRegisters)));
2826 unsigned Reg, MaskReg;
2827 unsigned RegSize, MaskRegSize;
2833 parseCFIUnsigned(MaskRegSize) || expectAndConsume(
MIToken::comma) ||
2842 unsigned Reg, SpillReg, MaskReg;
2843 unsigned SpillRegLaneSize, MaskRegSize;
2846 parseCFIRegister(SpillReg) || expectAndConsume(
MIToken::comma) ||
2847 parseCFIUnsigned(SpillRegLaneSize) ||
2849 expectAndConsume(
MIToken::comma) || parseCFIUnsigned(MaskRegSize))
2853 nullptr,
Reg, SpillReg, SpillRegLaneSize, MaskReg, MaskRegSize));
2858 if (parseCFIEscapeValues(
Values))
2872 switch (Token.kind()) {
2875 F.getValueSymbolTable()->lookup(Token.stringValue()));
2877 return error(
Twine(
"use of undefined IR block '") + Token.range() +
"'");
2881 unsigned SlotNumber = 0;
2884 BB =
const_cast<BasicBlock *
>(getIRBlock(SlotNumber,
F));
2886 return error(
Twine(
"use of undefined IR block '%ir-block.") +
2887 Twine(SlotNumber) +
"'");
2903 return error(
"expected a global value");
2909 return error(
"expected an IR function reference");
2915 return error(
"expected an IR block reference");
2916 if (parseIRBlock(BB, *
F))
2922 if (parseOperandsOffset(Dest))
2931 return error(
"expected syntax intrinsic(@llvm.whatever)");
2934 return error(
"expected syntax intrinsic(@llvm.whatever)");
2936 std::string
Name = std::string(Token.stringValue());
2940 return error(
"expected ')' to terminate intrinsic name");
2945 return error(
"unknown intrinsic name");
2957 return error(
"expected syntax intpred(whatever) or floatpred(whatever");
2960 return error(
"whatever");
2983 return error(
"invalid floating-point predicate");
2998 return error(
"invalid integer predicate");
3004 return error(
"predicate should be terminated by ')'.");
3014 return error(
"expected syntax shufflemask(<integer or undef>, ...)");
3021 const APSInt &
Int = Token.integerValue();
3024 return error(
"expected integer constant");
3031 return error(
"shufflemask should be terminated by ')'.");
3033 if (ShufMask.
size() < 2)
3034 return error(
"shufflemask should have > 1 element");
3046 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
3049 return error(
"expected unsigned integer for instruction index");
3050 uint64_t InstrIdx = Token.integerValue().getZExtValue();
3051 assert(InstrIdx <= std::numeric_limits<unsigned>::max() &&
3052 "Instruction reference's instruction index is too large");
3056 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
3059 return error(
"expected unsigned integer for operand index");
3060 uint64_t OpIdx = Token.integerValue().getZExtValue();
3061 assert(OpIdx <= std::numeric_limits<unsigned>::max() &&
3062 "Instruction reference's operand index is too large");
3066 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
3078 return error(
"expected the name of the target index");
3080 if (PFS.Target.getTargetIndex(Token.stringValue(), Index))
3081 return error(
"use of undefined target index '" + Token.stringValue() +
"'");
3086 if (parseOperandsOffset(Dest))
3091bool MIParser::parseCustomRegisterMaskOperand(
MachineOperand &Dest) {
3092 assert(Token.stringValue() ==
"CustomRegMask" &&
"Expected a custom RegMask");
3097 uint32_t *
Mask = MF.allocateRegMask();
3101 return error(
"expected a named register");
3103 if (parseNamedRegister(
Reg))
3127 return error(
"expected a valid lane mask value");
3129 "Use correct get-function for lane mask.");
3143bool MIParser::parseLiveoutRegisterMaskOperand(
MachineOperand &Dest) {
3145 uint32_t *
Mask = MF.allocateRegMask();
3151 return error(
"expected a named register");
3153 if (parseNamedRegister(
Reg))
3168bool MIParser::parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
3170 std::optional<unsigned> &TiedDefIdx) {
3171 switch (Token.kind()) {
3186 return parseRegisterOperand(Dest, TiedDefIdx);
3190 return parseImmediateOperand(Dest);
3198 return parseFPImmediateOperand(Dest);
3200 return parseMBBOperand(Dest);
3202 return parseStackObjectOperand(Dest);
3204 return parseFixedStackObjectOperand(Dest);
3207 return parseGlobalAddressOperand(Dest);
3209 return parseConstantPoolIndexOperand(Dest);
3211 return parseJumpTableIndexOperand(Dest);
3213 return parseExternalSymbolOperand(Dest);
3215 return parseMCSymbolOperand(Dest);
3217 return parseSubRegisterIndexOperand(Dest);
3220 return parseMetadataOperand(Dest);
3243 return parseCFIOperand(Dest);
3245 return parseBlockAddressOperand(Dest);
3247 return parseIntrinsicOperand(Dest);
3249 return parseTargetIndexOperand(Dest);
3251 return parseLaneMaskOperand(Dest);
3253 return parseLiveoutRegisterMaskOperand(Dest);
3256 return parsePredicateOperand(Dest);
3258 return parseShuffleMaskOperand(Dest);
3260 return parseDbgInstrRefOperand(Dest);
3264 bool IsInlineAsm =
OpCode == TargetOpcode::INLINEASM ||
3265 OpCode == TargetOpcode::INLINEASM_BR;
3267 return parseSymbolicInlineAsmOperand(OpIdx, Dest);
3270 if (
const auto *RegMask = PFS.Target.getRegMask(Id)) {
3274 }
else if (Id ==
"CustomRegMask") {
3275 return parseCustomRegisterMaskOperand(Dest);
3277 return parseTypedImmediateOperand(Dest);
3281 const auto *
TII = MF.getSubtarget().getInstrInfo();
3282 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3283 return parseTargetImmMnemonic(OpCode, OpIdx, Dest, *Formatter);
3289 return error(
"expected a machine operand");
3294bool MIParser::parseMachineOperandAndTargetFlags(
3295 const unsigned OpCode,
const unsigned OpIdx,
MachineOperand &Dest,
3296 std::optional<unsigned> &TiedDefIdx) {
3298 bool HasTargetFlags =
false;
3300 HasTargetFlags =
true;
3305 return error(
"expected the name of the target flag");
3306 if (PFS.Target.getDirectTargetFlag(Token.stringValue(), TF)) {
3307 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), TF))
3308 return error(
"use of undefined target flag '" + Token.stringValue() +
3315 return error(
"expected the name of the target flag");
3316 unsigned BitFlag = 0;
3317 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), BitFlag))
3318 return error(
"use of undefined target flag '" + Token.stringValue() +
3327 auto Loc = Token.location();
3328 if (parseMachineOperand(OpCode, OpIdx, Dest, TiedDefIdx))
3330 if (!HasTargetFlags)
3333 return error(
Loc,
"register operands can't have target flags");
3338bool MIParser::parseOffset(int64_t &
Offset) {
3345 return error(
"expected an integer literal after '" + Sign +
"'");
3346 if (Token.integerValue().getSignificantBits() > 64)
3347 return error(
"expected 64-bit integer (too large)");
3348 Offset = Token.integerValue().getExtValue();
3355bool MIParser::parseIRBlockAddressTaken(
BasicBlock *&BB) {
3359 return error(
"expected basic block after 'ir_block_address_taken'");
3361 if (parseIRBlock(BB, MF.getFunction()))
3368bool MIParser::parseAlignment(
uint64_t &Alignment) {
3372 return error(
"expected an integer literal after 'align'");
3373 if (getUint64(Alignment))
3378 return error(
"expected a power-of-2 literal after 'align'");
3383bool MIParser::parseAddrspace(
unsigned &Addrspace) {
3387 return error(
"expected an integer literal after 'addrspace'");
3404 switch (Token.
kind()) {
3410 unsigned SlotNumber = 0;
3438 return ErrCB(Token.
location(),
Twine(
"use of undefined IR value '") + Token.
range() +
"'");
3442bool MIParser::parseIRValue(
const Value *&V) {
3443 return ::parseIRValue(
3449bool MIParser::getUint64(
uint64_t &Result) {
3450 if (Token.hasIntegerValue()) {
3451 if (Token.integerValue().getActiveBits() > 64)
3452 return error(
"expected 64-bit integer (too large)");
3453 Result = Token.integerValue().getZExtValue();
3460 if (
A.getBitWidth() > 64)
3461 return error(
"expected 64-bit integer (too large)");
3468bool MIParser::getHexUint(
APInt &Result) {
3469 return ::getHexUint(Token, Result);
3473 const auto OldFlags =
Flags;
3474 switch (Token.kind()) {
3489 if (PFS.Target.getMMOTargetFlag(Token.stringValue(), TF))
3490 return error(
"use of undefined target MMO flag '" + Token.stringValue() +
3498 if (OldFlags == Flags)
3501 return error(
"duplicate '" + Token.stringValue() +
"' memory operand flag");
3507 switch (Token.kind()) {
3509 PSV = MF.getPSVManager().getStack();
3512 PSV = MF.getPSVManager().getGOT();
3515 PSV = MF.getPSVManager().getJumpTable();
3518 PSV = MF.getPSVManager().getConstantPool();
3522 if (parseFixedStackFrameIndex(FI))
3524 PSV = MF.getPSVManager().getFixedStack(FI);
3530 if (parseStackFrameIndex(FI))
3532 PSV = MF.getPSVManager().getFixedStack(FI);
3538 switch (Token.kind()) {
3544 PSV = MF.getPSVManager().getGlobalValueCallEntry(GV);
3548 PSV = MF.getPSVManager().getExternalSymbolCallEntry(
3549 MF.createExternalSymbolName(Token.stringValue()));
3553 "expected a global value or an external symbol after 'call-entry'");
3558 const auto *
TII = MF.getSubtarget().getInstrInfo();
3559 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3560 if (Formatter->parseCustomPseudoSourceValue(
3561 Token.stringValue(), MF, PFS, PSV,
3563 return error(Loc, Msg);
3567 return error(
"unable to parse target custom pseudo source value");
3584 if (parseMemoryPseudoSourceValue(PSV))
3597 return error(
"expected an IR value reference");
3598 const Value *
V =
nullptr;
3601 if (V && !
V->getType()->isPointerTy())
3602 return error(
"expected a pointer IR value");
3617 return error(
"expected '(' in syncscope");
3620 if (parseStringConstant(SSN))
3623 SSID =
Context.getOrInsertSyncScopeID(SSN);
3625 return error(
"expected ')' in syncscope");
3631bool MIParser::parseOptionalAtomicOrdering(
AtomicOrdering &Order) {
3650 return error(
"expected an atomic scope, ordering or a size specification");
3657 while (Token.isMemoryOperandFlag()) {
3658 if (parseMemoryOperandFlag(Flags))
3662 (Token.stringValue() !=
"load" && Token.stringValue() !=
"store"))
3663 return error(
"expected 'load' or 'store' memory operation");
3664 if (Token.stringValue() ==
"load")
3678 if (parseOptionalScope(MF.getFunction().getContext(), SSID))
3683 if (parseOptionalAtomicOrdering(Order))
3686 if (parseOptionalAtomicOrdering(FailureOrder))
3692 return error(
"expected memory LLT, the size integer literal or 'unknown-size' after "
3693 "memory operation");
3698 if (getUint64(
Size))
3709 if (parseLowLevelType(Token.location(), MemoryType))
3722 if (Token.stringValue() != Word)
3723 return error(
Twine(
"expected '") + Word +
"'");
3726 if (parseMachinePointerInfo(Ptr))
3735 MDNode *MemCacheHint =
nullptr;
3737 switch (Token.kind()) {
3743 if (Ptr.
Offset & (Alignment - 1)) {
3748 return error(
"specified alignment is more aligned than offset");
3794 return error(
"expected 'align' or '!tbaa' or '!alias.scope' or "
3795 "'!noalias' or '!range' or '!mem.cache_hint' or "
3796 "'!noalias.addrspace'");
3801 Dest = MF.getMachineMemOperand(Ptr, Flags, MemoryType,
Align(BaseAlignment),
3803 Order, FailureOrder);
3807bool MIParser::parsePreOrPostInstrSymbol(
MCSymbol *&Symbol) {
3810 "Invalid token for a pre- post-instruction symbol!");
3813 return error(
"expected a symbol after 'pre-instr-symbol'");
3814 Symbol = getOrCreateMCSymbol(Token.stringValue());
3820 return error(
"expected ',' before the next machine operand");
3825bool MIParser::parseHeapAllocMarker(
MDNode *&Node) {
3827 "Invalid token for a heap alloc marker!");
3832 return error(
"expected a MDNode after 'heap-alloc-marker'");
3837 return error(
"expected ',' before the next machine operand");
3842bool MIParser::parsePCSections(
MDNode *&Node) {
3844 "Invalid token for a PC sections!");
3849 return error(
"expected a MDNode after 'pcsections'");
3854 return error(
"expected ',' before the next machine operand");
3859bool MIParser::parseMMRA(
MDNode *&Node) {
3868 return error(
"expected ',' before the next machine operand");
3878 for (
const auto &BB :
F) {
3884 Slots2BasicBlocks.
insert(std::make_pair(
unsigned(Slot), &BB));
3891 return Slots2BasicBlocks.
lookup(Slot);
3894const BasicBlock *MIParser::getIRBlock(
unsigned Slot) {
3895 if (Slots2BasicBlocks.empty())
3901 if (&
F == &MF.getFunction())
3902 return getIRBlock(Slot);
3914 return MF.getContext().getOrCreateSymbol(Name);
3917bool MIParser::parseStringConstant(std::string &Result) {
3919 return error(
"expected string constant");
3920 Result = std::string(Token.stringValue());
3928 return MIParser(PFS,
Error, Src).parseBasicBlockDefinitions(PFS.
MBBSlots);
3933 return MIParser(PFS,
Error, Src).parseBasicBlocks();
3939 return MIParser(PFS,
Error, Src).parseStandaloneMBB(
MBB);
3945 return MIParser(PFS,
Error, Src).parseStandaloneRegister(Reg);
3951 return MIParser(PFS,
Error, Src).parseStandaloneNamedRegister(Reg);
3957 return MIParser(PFS,
Error, Src).parseStandaloneVirtualRegister(Info);
3962 return MIParser(PFS,
Error, Src).parseStandaloneStackObject(FI);
3968 return MIParser(PFS,
Error, Src).parsePrefetchTarget(
Target);
3972 return MIParser(PFS,
Error, Src).parseStandaloneMDNode(
Node);
3984 return ::parseIRValue(Token, PFS, V, ErrorCallback);
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file defines the StringMap class.
This file implements a class to represent arbitrary precision integral constant values and operations...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Atomic ordering constants.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack", "Very portable GC for uncooperative code generators")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static Error parseAlignment(StringRef Str, Align &Alignment, StringRef Name, bool AllowZero=false)
Attempts to parse an alignment component of a specification.
This file defines the DenseMap class.
const HexagonInstrInfo * TII
Module.h This file contains the declarations for the Module class.
A common definition of LaneBitmask for use in TableGen and CodeGen.
static llvm::Error parse(GsymDataExtractor &Data, uint64_t BaseAddr, LineEntryCallback const &Callback)
Implement a low-level type suitable for MachineInstr level instruction selection.
static const char * printImplicitRegisterFlag(const MachineOperand &MO)
static bool verifyVectorElementCount(uint64_t NumElts, bool HasVScale)
static const BasicBlock * getIRBlockFromSlot(unsigned Slot, const DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
static bool parseIRConstant(StringRef::iterator Loc, StringRef StringValue, PerFunctionMIParsingState &PFS, const Constant *&C, ErrorCallbackType ErrCB)
static void initSlots2Values(const Function &F, DenseMap< unsigned, const Value * > &Slots2Values)
Creates the mapping from slot numbers to function's unnamed IR values.
static bool parseIRValue(const MIToken &Token, PerFunctionMIParsingState &PFS, const Value *&V, ErrorCallbackType ErrCB)
static bool verifyScalarSize(uint64_t Size)
static bool getUnsigned(const MIToken &Token, unsigned &Result, ErrorCallbackType ErrCB)
static bool getHexUint(const MIToken &Token, APInt &Result)
static void mapValueToSlot(const Value *V, ModuleSlotTracker &MST, DenseMap< unsigned, const Value * > &Slots2Values)
static void initSlots2BasicBlocks(const Function &F, DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
function_ref< bool(StringRef::iterator Loc, const Twine &)> ErrorCallbackType
static bool isImplicitOperandIn(const MachineOperand &ImplicitOperand, ArrayRef< ParsedMachineOperand > Operands)
Return true if the parsed machine operands contain a given machine operand.
static bool parseGlobalValue(const MIToken &Token, PerFunctionMIParsingState &PFS, GlobalValue *&GV, ErrorCallbackType ErrCB)
static bool verifyAddrSpace(uint64_t AddrSpace)
Register const TargetRegisterInfo * TRI
Promote Memory to Register
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value.
An arbitrary precision integer that knows its signedness.
bool isNegative() const
Determine sign of this APSInt.
Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
Get the array size.
LLVM Basic Block Representation.
static LLVM_ABI BlockAddress * get(Function *F, BasicBlock *BB)
Return a BlockAddress for the specified function and basic block.
static constexpr BranchProbability getRaw(uint32_t N)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
@ ICMP_SLT
signed less than
@ ICMP_SLE
signed less or equal
@ FCMP_OLT
0 1 0 0 True if ordered and less than
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
@ ICMP_UGE
unsigned greater or equal
@ ICMP_UGT
unsigned greater than
@ ICMP_SGT
signed greater than
@ FCMP_ULT
1 1 0 0 True if unordered or less than
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
@ ICMP_ULT
unsigned less than
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
@ ICMP_SGE
signed greater or equal
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
@ ICMP_ULE
unsigned less or equal
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
static bool isFPPredicate(Predicate P)
static bool isIntPredicate(Predicate P)
This is an important base class in LLVM.
A parsed version of the target data layout string in and methods for querying it.
ValueT lookup(const_arg_type_t< KeyT > Val) const
Return the entry for the specified key, or a default constructed value if no such entry exists.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
Lightweight error class with error context and mandatory checking.
ValueSymbolTable * getValueSymbolTable()
getSymbolTable() - Return the symbol table if any, otherwise nullptr.
Module * getParent()
Get the module that this global value is contained inside of...
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT token()
Get a low-level token; just a scalar with zero bits (or no size).
static constexpr LLT bfloat16()
static LLT floatIEEE(unsigned SizeInBits)
This is an important class for using LLVM in a threaded context.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_def_cfa_register modifies a rule for computing CFA.
static MCCFIInstruction createLLVMVectorOffset(MCSymbol *L, unsigned Register, unsigned RegisterSizeInBits, unsigned MaskRegister, unsigned MaskRegisterSizeInBits, int64_t Offset, SMLoc Loc={})
.cfi_llvm_vector_offset Previous value of Register is saved at Offset from CFA.
static MCCFIInstruction createUndefined(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_undefined From now on the previous value of Register can't be restored anymore.
static MCCFIInstruction createLLVMVectorRegisters(MCSymbol *L, unsigned Register, ArrayRef< VectorRegisterWithLane > VectorRegisters, SMLoc Loc={})
.cfi_llvm_vector_registers Previous value of Register is saved in lanes of vector registers.
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
static MCCFIInstruction createSetRAState(MCSymbol *L, unsigned State, MCSymbol *PACSym=nullptr, SMLoc Loc={})
.cfi_set_ra_state AArch64 set RA sign state,
static MCCFIInstruction createLLVMDefAspaceCfa(MCSymbol *L, unsigned Register, int64_t Offset, unsigned AddressSpace, SMLoc Loc)
.cfi_llvm_def_aspace_cfa defines the rule for computing the CFA to be the result of evaluating the DW...
static MCCFIInstruction createLLVMVectorRegisterMask(MCSymbol *L, unsigned Register, unsigned SpillRegister, unsigned SpillRegisterLaneSizeInBits, unsigned MaskRegister, unsigned MaskRegisterSizeInBits, SMLoc Loc={})
.cfi_llvm_vector_register_mask Previous value of Register is saved in SpillRegister,...
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2, SMLoc Loc={})
.cfi_register Previous value of Register1 is saved in register Register2.
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction createNegateRAStateWithPC(MCSymbol *L, SMLoc Loc={})
.cfi_negate_ra_state_with_pc AArch64 negate RA state with PC.
static MCCFIInstruction createNegateRAState(MCSymbol *L, SMLoc Loc={})
.cfi_negate_ra_state AArch64 negate RA state.
static MCCFIInstruction createRememberState(MCSymbol *L, SMLoc Loc={})
.cfi_remember_state Save all current rules for all registers.
static MCCFIInstruction createLLVMRegisterPair(MCSymbol *L, unsigned Register, unsigned R1, unsigned R1SizeInBits, unsigned R2, unsigned R2SizeInBits, SMLoc Loc={})
.cfi_llvm_register_pair Previous value of Register is saved in R1:R2.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals, SMLoc Loc={}, StringRef Comment="")
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
static MCCFIInstruction createWindowSave(MCSymbol *L, SMLoc Loc={})
.cfi_window_save SPARC register window is saved.
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int64_t Adjustment, SMLoc Loc={})
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
static MCCFIInstruction createRestoreState(MCSymbol *L, SMLoc Loc={})
.cfi_restore_state Restore the previously saved state.
static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_same_value Current value of Register is the same as in the previous frame.
static MCCFIInstruction createRelOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_rel_offset Previous value of Register is saved at offset Offset from the current CFA register.
Describe properties that are true of each instruction in the target description file.
unsigned getID() const
getID() - Return the register class ID number.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
void setAddressTakenIRBlock(BasicBlock *BB)
Set this block to reflect that it corresponds to an IR-level basic block with a BlockAddress.
void setIsCleanupFuncletEntry(bool V=true)
Indicates if this is the entry block of a cleanup funclet.
LLVM_ABI instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
void setCallFrameSize(unsigned N)
Set the call frame size on entry to this basic block.
void setMaxBytesForAlignment(unsigned MaxBytes)
Set the maximum amount of padding allowed for aligning the basic block.
void setAlignment(Align A)
Set alignment of the basic block.
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void setSectionID(MBBSectionID V)
Sets the section ID for this basic block.
void setIsInlineAsmBrIndirectTarget(bool V=true)
Indicates if this is the indirect dest of an INLINEASM_BR.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
void setIsEHContTarget(bool V=true)
Indicates if this is a target of Windows EH Continuation Guard.
void setIsEHFuncletEntry(bool V=true)
Indicates if this is the entry block of an EH funclet.
LLVM_ABI bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
LLVM_ABI StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
void setIsEHScopeEntry(bool V=true)
Indicates if this is the entry block of an EH scope, i.e., the block that that used to have a catchpa...
void setMachineBlockAddressTaken()
Set this block to indicate that its address is used as something other than the target of a terminato...
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
void setFlag(MIFlag Flag)
Set a MI flag.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
static MachineOperand CreateFPImm(const ConstantFP *CFP)
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static MachineOperand CreateCImm(const ConstantInt *CI)
static MachineOperand CreateMetadata(const MDNode *Meta)
static MachineOperand CreatePredicate(unsigned Pred)
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx)
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
void setTargetFlags(unsigned F)
static MachineOperand CreateLaneMask(LaneBitmask LaneMask)
LLVM_ABI bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
static MachineOperand CreateFI(int Idx)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
LLVM_ABI Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
LLVM_ABI void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
void noteNewVirtualRegister(Register Reg)
This interface provides simple read-only access to a block of memory, and provides simple methods for...
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
const char * getBufferEnd() const
const char * getBufferStart() const
Manage lifetime of a slot tracker for printing IR.
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
void incorporateFunction(const Function &F)
Incorporate the given function.
A Module instance is used to store all the information related to an LLVM module.
Special value supplied for machine level alias analysis.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getNumRegBanks() const
Get the total number of register banks.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr unsigned id() const
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a location in source code.
static SMLoc getFromPointer(const char *Ptr)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This owns the files read by a parser, handles include stacks, and handles diagnostic wrangling.
unsigned getMainFileID() const
const MemoryBuffer * getMemoryBuffer(unsigned i) const
LLVM_ABI SMDiagnostic GetMessage(SMLoc Loc, DiagKind Kind, const Twine &Msg, ArrayRef< SMRange > Ranges={}, ArrayRef< SMFixIt > FixIts={}) const
Return an SMDiagnostic at the specified location with the specified string.
bool insert(MapEntryTy *KeyValue)
insert - Insert the specified key/value pair into the map.
Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
std::string str() const
Get the contents as an std::string.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
constexpr bool empty() const
Check if the string is empty.
LLVM_ABI std::string lower() const
bool consume_front(char Prefix)
Returns true if this StringRef has the given prefix and removes that prefix.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const =0
Return the target's register information.
Target - Wrapper for Target specific information.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Value * lookup(StringRef Name) const
This method finds the value with the given Name in the the symbol table.
LLVM Value Representation.
An efficient, type-erasing, non-owning reference to a callable.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ BasicBlock
Various leaf nodes.
LLVM_ABI ID lookupIntrinsicID(StringRef Name)
This does the actual lookup of an intrinsic ID which matches the given function name.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
@ System
Synchronized with respect to all concurrently executing threads.
support::ulittle32_t Word
Scope
Defines the scope in which this symbol should be visible: Default – Visible in the public interface o...
NodeAddr< NodeBase * > Node
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ABI bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI, StringRef Src, SMDiagnostic &Error)
LLVM_ABI bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src, SMDiagnostic &Error)
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
RelativeUniformCounterPtr Values
RegState
Flags to represent properties of register accesses.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Kill
The last use of a register.
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
@ Undef
Value of the register doesn't matter.
@ EarlyClobber
Register definition happens before uses.
@ Define
Register definition.
@ Renamable
Register that may be renamed.
@ Debug
Register 'use' is for debugging purpose.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
StringRef lexMIToken(StringRef Source, MIToken &Token, function_ref< void(StringRef::iterator, const Twine &)> ErrorCallback)
Consume a single machine instruction token in the given source and return the remaining source string...
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
LLVM_ABI bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine basic block definitions, and skip the machine instructions.
LLVM_ABI bool parsePrefetchTarget(PerFunctionMIParsingState &PFS, CallsiteID &Target, StringRef Src, SMDiagnostic &Error)
LLVM_ABI void guessSuccessors(const MachineBasicBlock &MBB, SmallVectorImpl< MachineBasicBlock * > &Result, bool &IsFallthrough)
Determine a possible list of successors of a basic block based on the basic block machine operand bei...
RelativeUniformCounterPtr ValuesPtrExpr VTableAddr Value
LLVM_ABI bool parseMBBReference(PerFunctionMIParsingState &PFS, MachineBasicBlock *&MBB, StringRef Src, SMDiagnostic &Error)
uint64_t PowerOf2Ceil(uint64_t A)
Returns the power of two which is greater than or equal to the given value.
auto dyn_cast_or_null(const Y &Val)
LLVM_ABI DIExpression * parseDIExpressionBodyAtBeginning(StringRef Asm, unsigned &Read, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots)
constexpr RegState getDefRegState(bool B)
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
constexpr bool hasRegState(RegState Value, RegState Test)
AtomicOrdering
Atomic ordering for LLVM's memory model.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
DWARFExpression::Operation Op
ArrayRef(const T &OneElt) -> ArrayRef< T >
std::string toString(const APInt &I, unsigned Radix, bool Signed, bool formatAsCLiteral=false, bool UpperCase=true, bool InsertSeparators=false)
LLVM_ABI bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine instructions.
LLVM_ABI bool parseRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
LLVM_ABI Constant * parseConstantValue(StringRef Asm, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots=nullptr)
Parse a type and a constant value in the given string.
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
LLVM_ABI bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS, VRegInfo *&Info, StringRef Src, SMDiagnostic &Error)
@ End
Run the machine verifier once, at the end of the pipeline.
LLVM_ABI bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
MCRegisterClass TargetRegisterClass
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * NoAliasAddrSpace
The tag specifying the noalias address spaces.
MDNode * Scope
The tag for alias scope specification (used with noalias).
MDNode * TBAA
The tag for type-based alias analysis.
MDNode * NoAlias
The tag specifying the noalias scope.
This struct is a compact representation of a valid (non-zero power of two) alignment.
static constexpr LaneBitmask getAll()
LLVM_ABI static const MBBSectionID ExceptionSectionID
LLVM_ABI static const MBBSectionID ColdSectionID
A token produced by the machine instruction lexer.
bool hasIntegerValue() const
bool is(TokenKind K) const
StringRef stringValue() const
Return the token's string value.
@ kw_cfi_aarch64_negate_ra_sign_state
@ kw_cfi_llvm_def_aspace_cfa
@ kw_cleanup_funclet_entry
@ kw_cfi_llvm_register_pair
@ kw_cfi_llvm_vector_offset
@ kw_inlineasm_br_indirect_target
@ kw_cfi_llvm_vector_registers
@ kw_cfi_llvm_vector_register_mask
@ kw_cfi_aarch64_negate_ra_sign_state_with_pc
@ kw_cfi_def_cfa_register
@ kw_cfi_adjust_cfa_offset
@ kw_max_bytes_for_alignment
@ kw_machine_block_address_taken
@ kw_ir_block_address_taken
StringRef::iterator location() const
const APSInt & integerValue() const
This class contains a discriminated union of information about pointers in memory operands,...
int64_t Offset
Offset - This is an offset from the base Value*.
LLVM_ABI VRegInfo & getVRegInfo(Register Num)
const SlotMapping & IRSlots
LLVM_ABI const Value * getIRValue(unsigned Slot)
DenseMap< unsigned, MachineBasicBlock * > MBBSlots
StringMap< VRegInfo * > VRegInfosNamed
DenseMap< unsigned, const Value * > Slots2Values
Maps from slot numbers to function's unnamed values.
LLVM_ABI PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM, const SlotMapping &IRSlots, PerTargetMIParsingState &Target)
PerTargetMIParsingState & Target
DenseMap< Register, VRegInfo * > VRegInfos
LLVM_ABI VRegInfo & getVRegInfoNamed(StringRef RegName)
BumpPtrAllocator Allocator
LLVM_ABI bool getVRegFlagValue(StringRef FlagName, uint8_t &FlagValue) const
LLVM_ABI bool getDirectTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a direct target flag to the corresponding target flag.
LLVM_ABI const RegisterBank * getRegBank(StringRef Name)
Check if the given identifier is a name of a register bank.
LLVM_ABI bool parseInstrName(StringRef InstrName, unsigned &OpCode)
Try to convert an instruction name to an opcode.
LLVM_ABI unsigned getSubRegIndex(StringRef Name)
Check if the given identifier is a name of a subregister index.
LLVM_ABI bool getTargetIndex(StringRef Name, int &Index)
Try to convert a name of target index to the corresponding target index.
LLVM_ABI void setTarget(const TargetSubtargetInfo &NewSubtarget)
LLVM_ABI bool getRegisterByName(StringRef RegName, Register &Reg)
Try to convert a register name to a register number.
LLVM_ABI bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag)
Try to convert a name of a MachineMemOperand target flag to the corresponding target flag.
LLVM_ABI bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a bitmask target flag to the corresponding target flag.
LLVM_ABI const TargetRegisterClass * getRegClass(StringRef Name)
Check if the given identifier is a name of a register class.
LLVM_ABI const uint32_t * getRegMask(StringRef Identifier)
Check if the given identifier is a name of a register mask.
This struct contains the mappings from the slot numbers to unnamed metadata nodes,...
NumberedValues< GlobalValue * > GlobalValues
const RegisterBank * RegBank
union llvm::VRegInfo::@127225073067155374133234315364317264041071000132 D
const TargetRegisterClass * RC
enum llvm::VRegInfo::@374354327266250320012227113300214031244227062232 Kind
bool Explicit
VReg was explicitly specified in the .mir file.