LLVM  14.0.0git
HexagonRegisterInfo.h
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1 //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Hexagon implementation of the TargetRegisterInfo
10 // class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
16 
18 
19 #define GET_REGINFO_HEADER
20 #include "HexagonGenRegisterInfo.inc"
21 
22 namespace llvm {
23 
24 namespace Hexagon {
25  // Generic (pseudo) subreg indices for use with getHexagonSubRegIndex.
26  enum { ps_sub_lo = 0, ps_sub_hi = 1 };
27 }
28 
30 public:
31  HexagonRegisterInfo(unsigned HwMode);
32 
33  /// Code Generation virtual methods...
35  const override;
37  CallingConv::ID) const override;
38 
39  BitVector getReservedRegs(const MachineFunction &MF) const override;
40 
42  unsigned FIOperandNum, RegScavenger *RS = nullptr) const override;
43 
44  /// Returns true since we may need scavenging for a temporary register
45  /// when generating hardware loop instructions.
46  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
47  return true;
48  }
49 
50  /// Returns true. Spill code for predicate registers might need an extra
51  /// register.
52  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
53  return true;
54  }
55 
56  /// Returns true if the frame pointer is valid.
57  bool useFPForScavengingIndex(const MachineFunction &MF) const override;
58 
60  unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
61  const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
62 
63  // Debug information queries.
64  unsigned getRARegister() const;
65  Register getFrameRegister(const MachineFunction &MF) const override;
66  unsigned getFrameRegister() const;
67  unsigned getStackRegister() const;
68 
69  unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
70  unsigned GenIdx) const;
71 
73  const TargetRegisterClass *RC) const;
74 
75  unsigned getFirstCallerSavedNonParamReg() const;
76 
77  const TargetRegisterClass *
79  unsigned Kind = 0) const override;
80 
81  bool isEHReturnCalleeSaveReg(unsigned Reg) const;
82 };
83 
84 } // end namespace llvm
85 
86 #endif
llvm::Hexagon::ps_sub_lo
@ ps_sub_lo
Definition: HexagonRegisterInfo.h:26
llvm::HexagonRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: HexagonRegisterInfo.cpp:147
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::HexagonRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: HexagonRegisterInfo.cpp:119
llvm::HexagonRegisterInfo::getStackRegister
unsigned getStackRegister() const
Definition: HexagonRegisterInfo.cpp:415
llvm::HexagonRegisterInfo::isEHReturnCalleeSaveReg
bool isEHReturnCalleeSaveReg(unsigned Reg) const
Definition: HexagonRegisterInfo.cpp:61
llvm::HexagonRegisterInfo::getFirstCallerSavedNonParamReg
unsigned getFirstCallerSavedNonParamReg() const
Definition: HexagonRegisterInfo.cpp:455
llvm::HexagonRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: HexagonRegisterInfo.cpp:203
llvm::HexagonRegisterInfo::getFrameRegister
unsigned getFrameRegister() const
Definition: HexagonRegisterInfo.cpp:410
llvm::HexagonRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: HexagonRegisterInfo.cpp:450
llvm::HexagonRegisterInfo::getCallerSavedRegs
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF, const TargetRegisterClass *RC) const
Definition: HexagonRegisterInfo.cpp:67
llvm::HexagonRegisterInfo::HexagonRegisterInfo
HexagonRegisterInfo(unsigned HwMode)
Definition: HexagonRegisterInfo.cpp:56
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::BitVector
Definition: BitVector.h:74
llvm::HexagonRegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Returns true.
Definition: HexagonRegisterInfo.h:52
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
HexagonGenRegisterInfo
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::HexagonRegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Returns true since we may need scavenging for a temporary register when generating hardware loop inst...
Definition: HexagonRegisterInfo.h:46
llvm::MachineFunction
Definition: MachineFunction.h:230
uint32_t
llvm::HexagonRegisterInfo::shouldCoalesce
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
Definition: HexagonRegisterInfo.cpp:347
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::HexagonRegisterInfo::useFPForScavengingIndex
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Returns true if the frame pointer is valid.
Definition: HexagonRegisterInfo.cpp:444
uint16_t
llvm::Hexagon::ps_sub_hi
@ ps_sub_hi
Definition: HexagonRegisterInfo.h:26
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::HexagonRegisterInfo::getHexagonSubRegIndex
unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC, unsigned GenIdx) const
Definition: HexagonRegisterInfo.cpp:420
llvm::HexagonRegisterInfo
Definition: HexagonRegisterInfo.h:29
llvm::MachineInstrBundleIterator< MachineInstr >
TargetRegisterInfo.h
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::HexagonRegisterInfo::getRARegister
unsigned getRARegister() const
Definition: HexagonRegisterInfo.cpp:396
llvm::HexagonRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: HexagonRegisterInfo.cpp:141