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HexagonRegisterInfo.cpp
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1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Hexagon implementation of the TargetRegisterInfo
10 // class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonRegisterInfo.h"
15 #include "Hexagon.h"
17 #include "HexagonSubtarget.h"
18 #include "HexagonTargetMachine.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
36 #include "llvm/Support/Debug.h"
41 
42 #define GET_REGINFO_TARGET_DESC
43 #include "HexagonGenRegisterInfo.inc"
44 
45 using namespace llvm;
46 
48  "hexagon-frame-index-search-range", cl::init(32), cl::Hidden,
49  cl::desc("Limit on instruction search range in frame index elimination"));
50 
52  "hexagon-frame-index-reuse-limit", cl::init(~0), cl::Hidden,
53  cl::desc("Limit on the number of reused registers in frame index "
54  "elimination"));
55 
57  : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/,
58  0/*PC*/, HwMode) {}
59 
60 
62  return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
63  R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
64 }
65 
66 const MCPhysReg *
68  const TargetRegisterClass *RC) const {
69  using namespace Hexagon;
70 
71  static const MCPhysReg Int32[] = {
72  R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0
73  };
74  static const MCPhysReg Int64[] = {
75  D0, D1, D2, D3, D4, D5, D6, D7, 0
76  };
77  static const MCPhysReg Pred[] = {
78  P0, P1, P2, P3, 0
79  };
80  static const MCPhysReg VecSgl[] = {
81  V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13,
82  V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27,
83  V28, V29, V30, V31, 0
84  };
85  static const MCPhysReg VecDbl[] = {
86  W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0
87  };
88  static const MCPhysReg VecPred[] = {
89  Q0, Q1, Q2, Q3, 0
90  };
91 
92  switch (RC->getID()) {
93  case IntRegsRegClassID:
94  return Int32;
95  case DoubleRegsRegClassID:
96  return Int64;
97  case PredRegsRegClassID:
98  return Pred;
99  case HvxVRRegClassID:
100  return VecSgl;
101  case HvxWRRegClassID:
102  return VecDbl;
103  case HvxQRRegClassID:
104  return VecPred;
105  default:
106  break;
107  }
108 
109  static const MCPhysReg Empty[] = { 0 };
110 #ifndef NDEBUG
111  dbgs() << "Register class: " << getRegClassName(RC) << "\n";
112 #endif
113  llvm_unreachable("Unexpected register class");
114  return Empty;
115 }
116 
117 
118 const MCPhysReg *
120  static const MCPhysReg CalleeSavedRegsV3[] = {
121  Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
122  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
123  Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
124  };
125 
126  // Functions that contain a call to __builtin_eh_return also save the first 4
127  // parameter registers.
128  static const MCPhysReg CalleeSavedRegsV3EHReturn[] = {
129  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
130  Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
131  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
132  Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
133  };
134 
135  bool HasEHReturn = MF->getInfo<HexagonMachineFunctionInfo>()->hasEHReturn();
136 
137  return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3;
138 }
139 
140 
142  const MachineFunction &MF, CallingConv::ID) const {
143  return HexagonCSR_RegMask;
144 }
145 
146 
148  const {
149  BitVector Reserved(getNumRegs());
150  Reserved.set(Hexagon::R29);
151  Reserved.set(Hexagon::R30);
152  Reserved.set(Hexagon::R31);
153  Reserved.set(Hexagon::VTMP);
154 
155  // Guest registers.
156  Reserved.set(Hexagon::GELR); // G0
157  Reserved.set(Hexagon::GSR); // G1
158  Reserved.set(Hexagon::GOSP); // G2
159  Reserved.set(Hexagon::G3); // G3
160 
161  // Control registers.
162  Reserved.set(Hexagon::SA0); // C0
163  Reserved.set(Hexagon::LC0); // C1
164  Reserved.set(Hexagon::SA1); // C2
165  Reserved.set(Hexagon::LC1); // C3
166  Reserved.set(Hexagon::P3_0); // C4
167  Reserved.set(Hexagon::USR); // C8
168  Reserved.set(Hexagon::PC); // C9
169  Reserved.set(Hexagon::UGP); // C10
170  Reserved.set(Hexagon::GP); // C11
171  Reserved.set(Hexagon::CS0); // C12
172  Reserved.set(Hexagon::CS1); // C13
173  Reserved.set(Hexagon::UPCYCLELO); // C14
174  Reserved.set(Hexagon::UPCYCLEHI); // C15
175  Reserved.set(Hexagon::FRAMELIMIT); // C16
176  Reserved.set(Hexagon::FRAMEKEY); // C17
177  Reserved.set(Hexagon::PKTCOUNTLO); // C18
178  Reserved.set(Hexagon::PKTCOUNTHI); // C19
179  Reserved.set(Hexagon::UTIMERLO); // C30
180  Reserved.set(Hexagon::UTIMERHI); // C31
181  // Out of the control registers, only C8 is explicitly defined in
182  // HexagonRegisterInfo.td. If others are defined, make sure to add
183  // them here as well.
184  Reserved.set(Hexagon::C8);
185  Reserved.set(Hexagon::USR_OVF);
186 
187  // Leveraging these registers will require more work to recognize
188  // the new semantics posed, Hi/LoVec patterns, etc.
189  // Note well: if enabled, they should be restricted to only
190  // where `HST.useHVXOps() && HST.hasV67Ops()` is true.
191  for (auto Reg : Hexagon_MC::GetVectRegRev())
192  Reserved.set(Reg);
193 
195  Reserved.set(Hexagon::R19);
196 
197  for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x))
198  markSuperRegs(Reserved, x);
199 
200  return Reserved;
201 }
202 
204  int SPAdj, unsigned FIOp,
205  RegScavenger *RS) const {
206  static unsigned ReuseCount = 0;
207  //
208  // Hexagon_TODO: Do we need to enforce this for Hexagon?
209  assert(SPAdj == 0 && "Unexpected");
210 
211  MachineInstr &MI = *II;
212  MachineBasicBlock &MB = *MI.getParent();
213  MachineFunction &MF = *MB.getParent();
214  auto &HST = MF.getSubtarget<HexagonSubtarget>();
215  auto &HII = *HST.getInstrInfo();
216  auto &HFI = *HST.getFrameLowering();
217 
218  Register BP;
219  int FI = MI.getOperand(FIOp).getIndex();
220  // Select the base pointer (BP) and calculate the actual offset from BP
221  // to the beginning of the object at index FI.
222  int Offset = HFI.getFrameIndexReference(MF, FI, BP).getFixed();
223  // Add the offset from the instruction.
224  int RealOffset = Offset + MI.getOperand(FIOp+1).getImm();
225 
226  unsigned Opc = MI.getOpcode();
227  switch (Opc) {
228  case Hexagon::PS_fia:
229  MI.setDesc(HII.get(Hexagon::A2_addi));
230  MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
231  MI.RemoveOperand(FIOp+1);
232  return;
233  case Hexagon::PS_fi:
234  // Set up the instruction for updating below.
235  MI.setDesc(HII.get(Hexagon::A2_addi));
236  break;
237  }
238 
239  if (!HII.isValidOffset(Opc, RealOffset, this)) {
240  // If the offset is not valid, calculate the address in a temporary
241  // register and use it with offset 0.
242  int InstOffset = 0;
243  // The actual base register (BP) is typically shared between many
244  // instructions where frame indices are being replaced. In scalar
245  // instructions the offset range is large, and the need for an extra
246  // add instruction is infrequent. Vector loads/stores, however, have
247  // a much smaller offset range: [-8, 7), or #s4. In those cases it
248  // makes sense to "standardize" the immediate in the "addi" instruction
249  // so that multiple loads/stores could be based on it.
250  bool IsPair = false;
251  switch (MI.getOpcode()) {
252  // All of these instructions have the same format: base+#s4.
253  case Hexagon::PS_vloadrw_ai:
254  case Hexagon::PS_vloadrw_nt_ai:
255  case Hexagon::PS_vstorerw_ai:
256  case Hexagon::PS_vstorerw_nt_ai:
257  IsPair = true;
259  case Hexagon::PS_vloadrv_ai:
260  case Hexagon::PS_vloadrv_nt_ai:
261  case Hexagon::PS_vstorerv_ai:
262  case Hexagon::PS_vstorerv_nt_ai:
263  case Hexagon::V6_vL32b_ai:
264  case Hexagon::V6_vS32b_ai: {
265  unsigned HwLen = HST.getVectorLength();
266  if (RealOffset % HwLen == 0) {
267  int VecOffset = RealOffset / HwLen;
268  // Rewrite the offset as "base + [-8, 7)".
269  VecOffset += 8;
270  // Pairs are expanded into two instructions: make sure that both
271  // can use the same base (i.e. VecOffset+1 is not a different
272  // multiple of 16 than VecOffset).
273  if (!IsPair || (VecOffset + 1) % 16 != 0) {
274  RealOffset = (VecOffset & -16) * HwLen;
275  InstOffset = (VecOffset % 16 - 8) * HwLen;
276  }
277  }
278  }
279  }
280 
281  // Search backwards in the block for "Reg = A2_addi BP, RealOffset".
282  // This will give us a chance to avoid creating a new register.
283  Register ReuseBP;
284 
285  if (ReuseCount < FrameIndexReuseLimit) {
286  unsigned SearchCount = 0, SearchRange = FrameIndexSearchRange;
287  SmallSet<Register,2> SeenVRegs;
288  bool PassedCall = false;
289  LiveRegUnits Defs(*this), Uses(*this);
290 
291  for (auto I = std::next(II.getReverse()), E = MB.rend(); I != E; ++I) {
292  if (SearchCount == SearchRange)
293  break;
294  ++SearchCount;
295  const MachineInstr &BI = *I;
296  LiveRegUnits::accumulateUsedDefed(BI, Defs, Uses, this);
297  PassedCall |= BI.isCall();
298  for (const MachineOperand &Op : BI.operands()) {
299  if (SeenVRegs.size() > 1)
300  break;
301  if (Op.isReg() && Op.getReg().isVirtual())
302  SeenVRegs.insert(Op.getReg());
303  }
304  if (BI.getOpcode() != Hexagon::A2_addi)
305  continue;
306  if (BI.getOperand(1).getReg() != BP)
307  continue;
308  const auto &Op2 = BI.getOperand(2);
309  if (!Op2.isImm() || Op2.getImm() != RealOffset)
310  continue;
311 
312  Register R = BI.getOperand(0).getReg();
313  if (R.isPhysical()) {
314  if (Defs.available(R))
315  ReuseBP = R;
316  } else if (R.isVirtual()) {
317  // Extending a range of a virtual register can be dangerous,
318  // since the scavenger will need to find a physical register
319  // for it. Avoid extending the range past a function call,
320  // and avoid overlapping it with another virtual register.
321  if (!PassedCall && SeenVRegs.size() <= 1)
322  ReuseBP = R;
323  }
324  break;
325  }
326  if (ReuseBP)
327  ++ReuseCount;
328  }
329 
330  auto &MRI = MF.getRegInfo();
331  if (!ReuseBP) {
332  ReuseBP = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
333  const DebugLoc &DL = MI.getDebugLoc();
334  BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), ReuseBP)
335  .addReg(BP)
336  .addImm(RealOffset);
337  }
338  BP = ReuseBP;
339  RealOffset = InstOffset;
340  }
341 
342  MI.getOperand(FIOp).ChangeToRegister(BP, false, false, false);
343  MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
344 }
345 
346 
348  const TargetRegisterClass *SrcRC, unsigned SubReg,
349  const TargetRegisterClass *DstRC, unsigned DstSubReg,
350  const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
351  // Coalescing will extend the live interval of the destination register.
352  // If the destination register is a vector pair, avoid introducing function
353  // calls into the interval, since it could result in a spilling of a pair
354  // instead of a single vector.
355  MachineFunction &MF = *MI->getParent()->getParent();
357  if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID())
358  return true;
359  bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID();
360  bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID();
361  if (!SmallSrc && !SmallDst)
362  return true;
363 
364  Register DstReg = MI->getOperand(0).getReg();
365  Register SrcReg = MI->getOperand(1).getReg();
366  const SlotIndexes &Indexes = *LIS.getSlotIndexes();
367  auto HasCall = [&Indexes] (const LiveInterval::Segment &S) {
368  for (SlotIndex I = S.start.getBaseIndex(), E = S.end.getBaseIndex();
369  I != E; I = I.getNextIndex()) {
370  if (const MachineInstr *MI = Indexes.getInstructionFromIndex(I))
371  if (MI->isCall())
372  return true;
373  }
374  return false;
375  };
376 
377  if (SmallSrc == SmallDst) {
378  // Both must be true, because the case for both being false was
379  // checked earlier. Both registers will be coalesced into a register
380  // of a wider class (HvxWR), and we don't want its live range to
381  // span over calls.
382  return !any_of(LIS.getInterval(DstReg), HasCall) &&
383  !any_of(LIS.getInterval(SrcReg), HasCall);
384  }
385 
386  // If one register is large (HvxWR) and the other is small (HvxVR), then
387  // coalescing is ok if the large is already live across a function call,
388  // or if the small one is not.
389  unsigned SmallReg = SmallSrc ? SrcReg : DstReg;
390  unsigned LargeReg = SmallSrc ? DstReg : SrcReg;
391  return any_of(LIS.getInterval(LargeReg), HasCall) ||
392  !any_of(LIS.getInterval(SmallReg), HasCall);
393 }
394 
395 
397  return Hexagon::R31;
398 }
399 
400 
402  &MF) const {
403  const HexagonFrameLowering *TFI = getFrameLowering(MF);
404  if (TFI->hasFP(MF))
405  return getFrameRegister();
406  return getStackRegister();
407 }
408 
409 
411  return Hexagon::R30;
412 }
413 
414 
416  return Hexagon::R29;
417 }
418 
419 
421  const TargetRegisterClass &RC, unsigned GenIdx) const {
422  assert(GenIdx == Hexagon::ps_sub_lo || GenIdx == Hexagon::ps_sub_hi);
423 
424  static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
425  static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
426  static const unsigned WSub[] = { Hexagon::wsub_lo, Hexagon::wsub_hi };
427 
428  switch (RC.getID()) {
429  case Hexagon::CtrRegs64RegClassID:
430  case Hexagon::DoubleRegsRegClassID:
431  return ISub[GenIdx];
432  case Hexagon::HvxWRRegClassID:
433  return VSub[GenIdx];
434  case Hexagon::HvxVQRRegClassID:
435  return WSub[GenIdx];
436  }
437 
438  if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses())
439  return getHexagonSubRegIndex(*SuperRC, GenIdx);
440 
441  llvm_unreachable("Invalid register class");
442 }
443 
445  const {
446  return MF.getSubtarget<HexagonSubtarget>().getFrameLowering()->hasFP(MF);
447 }
448 
449 const TargetRegisterClass *
451  unsigned Kind) const {
452  return &Hexagon::IntRegsRegClass;
453 }
454 
456  return Hexagon::R6;
457 }
458 
llvm::Hexagon::ps_sub_lo
@ ps_sub_lo
Definition: HexagonRegisterInfo.h:26
llvm::HexagonRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: HexagonRegisterInfo.cpp:147
MI
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Definition: IRTranslator.cpp:102
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:69
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::HexagonRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: HexagonRegisterInfo.cpp:119
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SlotIndexes * getSlotIndexes() const
Definition: LiveIntervals.h:211
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::LiveRegUnits::accumulateUsedDefed
static void accumulateUsedDefed(const MachineInstr &MI, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits, const TargetRegisterInfo *TRI)
For a machine instruction MI, adds all register units used in UsedRegUnits and defined or clobbered i...
Definition: LiveRegUnits.h:47
HexagonSubtarget.h
ErrorHandling.h
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unsigned getStackRegister() const
Definition: HexagonRegisterInfo.cpp:415
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This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
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@ Hidden
Definition: CommandLine.h:143
R4
#define R4(n)
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bool isEHReturnCalleeSaveReg(unsigned Reg) const
Definition: HexagonRegisterInfo.cpp:61
llvm::HexagonRegisterInfo::getFirstCallerSavedNonParamReg
unsigned getFirstCallerSavedNonParamReg() const
Definition: HexagonRegisterInfo.cpp:455
TargetInstrInfo.h
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SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::HexagonRegisterInfo::eliminateFrameIndex
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Definition: HexagonRegisterInfo.cpp:203
Offset
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Definition: ELFObjHandler.cpp:81
STLExtras.h
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llvm::HexagonRegisterInfo::getFrameRegister
unsigned getFrameRegister() const
Definition: HexagonRegisterInfo.cpp:410
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const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: HexagonRegisterInfo.cpp:450
llvm::HexagonRegisterInfo::getCallerSavedRegs
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF, const TargetRegisterClass *RC) const
Definition: HexagonRegisterInfo.cpp:67
MachineRegisterInfo.h
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SmallPtrSet< MachineInstr *, 2 > Uses
Definition: ARMLowOverheadLoops.cpp:579
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bool hasReservedR19() const
Definition: HexagonSubtarget.h:229
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Definition: Debug.cpp:163
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Definition: HexagonRegisterInfo.cpp:56
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MachineRegisterInfo & getRegInfo()
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Definition: MachineFunction.h:632
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bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:823
TargetMachine.h
llvm::HexagonMachineFunctionInfo
Hexagon target-specific information for each MachineFunction.
Definition: HexagonMachineFunctionInfo.h:25
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This might compile to this xmm1 xorps xmm0 movss xmm0 ret Now consider if the code caused xmm1 to get spilled This might produce this xmm1 movaps xmm0 movaps xmm1 movss xmm0 ret since the reload is only used by these we could fold it into the producing something like xmm1 movaps xmm0 ret saving two instructions The basic idea is that a reload from a spill if only one byte chunk is bring in zeros the one element instead of elements This can be used to simplify a variety of shuffle where the elements are fixed zeros This code generates ugly probably due to costs being off or< 4 x float > * P2
Definition: README-SSE.txt:278
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Definition: MachineFunction.h:720
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const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
FrameIndexReuseLimit
static cl::opt< unsigned > FrameIndexReuseLimit("hexagon-frame-index-reuse-limit", cl::init(~0), cl::Hidden, cl::desc("Limit on the number of reused registers in frame index " "elimination"))
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Definition: TargetRegisterInfo.h:46
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Definition: HexagonFrameLowering.cpp:1142
FrameIndexSearchRange
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PseudoSourceValue.h
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MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
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bool useHVXOps() const
Definition: HexagonSubtarget.h:204
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Definition: MachineBasicBlock.h:278
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Definition: SlotIndexes.h:314
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Definition: BitVector.h:74
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A set of register units used to track register liveness.
Definition: LiveRegUnits.h:30
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MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
Definition: SlotIndexes.h:403
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Definition: SlotIndexes.h:83
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Definition: LLToken.h:18
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LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
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Definition: MachineBasicBlock.h:95
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const HexagonInstrInfo * getInstrInfo() const override
Definition: HexagonSubtarget.h:120
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:622
llvm::cl::opt
Definition: CommandLine.h:1422
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Definition: HexagonMCTargetDesc.cpp:548
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@ V4
Definition: NVPTX.h:124
HexagonGenRegisterInfo
llvm::MachineInstrBundleIterator::getReverse
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
Definition: MachineInstrBundleIterator.h:283
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Representation of each machine instruction.
Definition: MachineInstr.h:64
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I
#define I(x, y, z)
Definition: MD5.cpp:59
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Definition: RegisterScavenging.h:34
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Definition: CommandLine.h:443
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HexagonRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
R6
#define R6(n)
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:114
llvm::MachineFunction
Definition: MachineFunction.h:230
TargetOptions.h
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1554
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
MachineLocation.h
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
uint32_t
llvm::HexagonRegisterInfo::shouldCoalesce
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
Definition: HexagonRegisterInfo.cpp:347
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
LiveRegUnits.h
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::HexagonRegisterInfo::useFPForScavengingIndex
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Returns true if the frame pointer is valid.
Definition: HexagonRegisterInfo.cpp:444
llvm::NVPTX::PTXLdStInstCode::V2
@ V2
Definition: NVPTX.h:123
llvm::HexagonFrameLowering
Definition: HexagonFrameLowering.h:31
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::TargetRegisterClass::getSuperClasses
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
Definition: TargetRegisterInfo.h:174
MachineFrameInfo.h
llvm::Hexagon::ps_sub_hi
@ ps_sub_hi
Definition: HexagonRegisterInfo.h:26
Function.h
LC0
into eax xorps xmm0 xmm0 eax xmm0 eax xmm0 ret esp eax movdqa LC0
Definition: README-SSE.txt:632
x
TODO unsigned x
Definition: README.txt:10
llvm::LiveIntervals
Definition: LiveIntervals.h:54
MachineInstrBuilder.h
llvm::SmallSet::size
size_type size() const
Definition: SmallSet.h:159
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::PseudoProbeAttributes::Reserved
@ Reserved
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
llvm::HexagonRegisterInfo::getHexagonSubRegIndex
unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC, unsigned GenIdx) const
Definition: HexagonRegisterInfo.cpp:420
HexagonMachineFunctionInfo.h
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:414
RegisterScavenging.h
raw_ostream.h
MachineFunction.h
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:618
Debug.h
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::HexagonRegisterInfo::getRARegister
unsigned getRARegister() const
Definition: HexagonRegisterInfo.cpp:396
llvm::HexagonRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: HexagonRegisterInfo.cpp:141
SmallSet.h