LLVM  13.0.0git
Host.cpp
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1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the operating system Host concept.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/Support/Host.h"
14 #include "llvm/ADT/SmallSet.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringMap.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/Config/llvm-config.h"
21 #include "llvm/Support/BCD.h"
22 #include "llvm/Support/Debug.h"
27 #include <assert.h>
28 #include <string.h>
29 
30 // Include the platform-specific parts of this class.
31 #ifdef LLVM_ON_UNIX
32 #include "Unix/Host.inc"
33 #include <sched.h>
34 #endif
35 #ifdef _WIN32
36 #include "Windows/Host.inc"
37 #endif
38 #ifdef _MSC_VER
39 #include <intrin.h>
40 #endif
41 #if defined(__APPLE__) && (!defined(__x86_64__))
42 #include <mach/host_info.h>
43 #include <mach/mach.h>
44 #include <mach/mach_host.h>
45 #include <mach/machine.h>
46 #endif
47 #ifdef _AIX
48 #include <sys/systemcfg.h>
49 #endif
50 
51 #define DEBUG_TYPE "host-detection"
52 
53 //===----------------------------------------------------------------------===//
54 //
55 // Implementations of the CPU detection routines
56 //
57 //===----------------------------------------------------------------------===//
58 
59 using namespace llvm;
60 
61 static std::unique_ptr<llvm::MemoryBuffer>
64  llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
65  if (std::error_code EC = Text.getError()) {
66  llvm::errs() << "Can't read "
67  << "/proc/cpuinfo: " << EC.message() << "\n";
68  return nullptr;
69  }
70  return std::move(*Text);
71 }
72 
74  // Access to the Processor Version Register (PVR) on PowerPC is privileged,
75  // and so we must use an operating-system interface to determine the current
76  // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
77  const char *generic = "generic";
78 
79  // The cpu line is second (after the 'processor: 0' line), so if this
80  // buffer is too small then something has changed (or is wrong).
81  StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
82  StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
83 
84  StringRef::const_iterator CIP = CPUInfoStart;
85 
86  StringRef::const_iterator CPUStart = 0;
87  size_t CPULen = 0;
88 
89  // We need to find the first line which starts with cpu, spaces, and a colon.
90  // After the colon, there may be some additional spaces and then the cpu type.
91  while (CIP < CPUInfoEnd && CPUStart == 0) {
92  if (CIP < CPUInfoEnd && *CIP == '\n')
93  ++CIP;
94 
95  if (CIP < CPUInfoEnd && *CIP == 'c') {
96  ++CIP;
97  if (CIP < CPUInfoEnd && *CIP == 'p') {
98  ++CIP;
99  if (CIP < CPUInfoEnd && *CIP == 'u') {
100  ++CIP;
101  while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
102  ++CIP;
103 
104  if (CIP < CPUInfoEnd && *CIP == ':') {
105  ++CIP;
106  while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
107  ++CIP;
108 
109  if (CIP < CPUInfoEnd) {
110  CPUStart = CIP;
111  while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
112  *CIP != ',' && *CIP != '\n'))
113  ++CIP;
114  CPULen = CIP - CPUStart;
115  }
116  }
117  }
118  }
119  }
120 
121  if (CPUStart == 0)
122  while (CIP < CPUInfoEnd && *CIP != '\n')
123  ++CIP;
124  }
125 
126  if (CPUStart == 0)
127  return generic;
128 
129  return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
130  .Case("604e", "604e")
131  .Case("604", "604")
132  .Case("7400", "7400")
133  .Case("7410", "7400")
134  .Case("7447", "7400")
135  .Case("7455", "7450")
136  .Case("G4", "g4")
137  .Case("POWER4", "970")
138  .Case("PPC970FX", "970")
139  .Case("PPC970MP", "970")
140  .Case("G5", "g5")
141  .Case("POWER5", "g5")
142  .Case("A2", "a2")
143  .Case("POWER6", "pwr6")
144  .Case("POWER7", "pwr7")
145  .Case("POWER8", "pwr8")
146  .Case("POWER8E", "pwr8")
147  .Case("POWER8NVL", "pwr8")
148  .Case("POWER9", "pwr9")
149  .Case("POWER10", "pwr10")
150  // FIXME: If we get a simulator or machine with the capabilities of
151  // mcpu=future, we should revisit this and add the name reported by the
152  // simulator/machine.
153  .Default(generic);
154 }
155 
157  // The cpuid register on arm is not accessible from user space. On Linux,
158  // it is exposed through the /proc/cpuinfo file.
159 
160  // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
161  // in all cases.
163  ProcCpuinfoContent.split(Lines, "\n");
164 
165  // Look for the CPU implementer line.
166  StringRef Implementer;
167  StringRef Hardware;
168  StringRef Part;
169  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
170  if (Lines[I].startswith("CPU implementer"))
171  Implementer = Lines[I].substr(15).ltrim("\t :");
172  if (Lines[I].startswith("Hardware"))
173  Hardware = Lines[I].substr(8).ltrim("\t :");
174  if (Lines[I].startswith("CPU part"))
175  Part = Lines[I].substr(8).ltrim("\t :");
176  }
177 
178  if (Implementer == "0x41") { // ARM Ltd.
179  // MSM8992/8994 may give cpu part for the core that the kernel is running on,
180  // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
181  if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
182  return "cortex-a53";
183 
184 
185  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
186  // values correspond to the "Part number" in the CP15/c0 register. The
187  // contents are specified in the various processor manuals.
188  // This corresponds to the Main ID Register in Technical Reference Manuals.
189  // and is used in programs like sys-utils
190  return StringSwitch<const char *>(Part)
191  .Case("0x926", "arm926ej-s")
192  .Case("0xb02", "mpcore")
193  .Case("0xb36", "arm1136j-s")
194  .Case("0xb56", "arm1156t2-s")
195  .Case("0xb76", "arm1176jz-s")
196  .Case("0xc08", "cortex-a8")
197  .Case("0xc09", "cortex-a9")
198  .Case("0xc0f", "cortex-a15")
199  .Case("0xc20", "cortex-m0")
200  .Case("0xc23", "cortex-m3")
201  .Case("0xc24", "cortex-m4")
202  .Case("0xd22", "cortex-m55")
203  .Case("0xd02", "cortex-a34")
204  .Case("0xd04", "cortex-a35")
205  .Case("0xd03", "cortex-a53")
206  .Case("0xd07", "cortex-a57")
207  .Case("0xd08", "cortex-a72")
208  .Case("0xd09", "cortex-a73")
209  .Case("0xd0a", "cortex-a75")
210  .Case("0xd0b", "cortex-a76")
211  .Case("0xd0d", "cortex-a77")
212  .Case("0xd41", "cortex-a78")
213  .Case("0xd44", "cortex-x1")
214  .Case("0xd0c", "neoverse-n1")
215  .Case("0xd49", "neoverse-n2")
216  .Default("generic");
217  }
218 
219  if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium.
220  return StringSwitch<const char *>(Part)
221  .Case("0x516", "thunderx2t99")
222  .Case("0x0516", "thunderx2t99")
223  .Case("0xaf", "thunderx2t99")
224  .Case("0x0af", "thunderx2t99")
225  .Case("0xa1", "thunderxt88")
226  .Case("0x0a1", "thunderxt88")
227  .Default("generic");
228  }
229 
230  if (Implementer == "0x46") { // Fujitsu Ltd.
231  return StringSwitch<const char *>(Part)
232  .Case("0x001", "a64fx")
233  .Default("generic");
234  }
235 
236  if (Implementer == "0x4e") { // NVIDIA Corporation
237  return StringSwitch<const char *>(Part)
238  .Case("0x004", "carmel")
239  .Default("generic");
240  }
241 
242  if (Implementer == "0x48") // HiSilicon Technologies, Inc.
243  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
244  // values correspond to the "Part number" in the CP15/c0 register. The
245  // contents are specified in the various processor manuals.
246  return StringSwitch<const char *>(Part)
247  .Case("0xd01", "tsv110")
248  .Default("generic");
249 
250  if (Implementer == "0x51") // Qualcomm Technologies, Inc.
251  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
252  // values correspond to the "Part number" in the CP15/c0 register. The
253  // contents are specified in the various processor manuals.
254  return StringSwitch<const char *>(Part)
255  .Case("0x06f", "krait") // APQ8064
256  .Case("0x201", "kryo")
257  .Case("0x205", "kryo")
258  .Case("0x211", "kryo")
259  .Case("0x800", "cortex-a73") // Kryo 2xx Gold
260  .Case("0x801", "cortex-a73") // Kryo 2xx Silver
261  .Case("0x802", "cortex-a75") // Kryo 3xx Gold
262  .Case("0x803", "cortex-a75") // Kryo 3xx Silver
263  .Case("0x804", "cortex-a76") // Kryo 4xx Gold
264  .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver
265  .Case("0xc00", "falkor")
266  .Case("0xc01", "saphira")
267  .Default("generic");
268  if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
269  // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
270  // any predictive pattern across variants and parts.
271  unsigned Variant = 0, Part = 0;
272 
273  // Look for the CPU variant line, whose value is a 1 digit hexadecimal
274  // number, corresponding to the Variant bits in the CP15/C0 register.
275  for (auto I : Lines)
276  if (I.consume_front("CPU variant"))
277  I.ltrim("\t :").getAsInteger(0, Variant);
278 
279  // Look for the CPU part line, whose value is a 3 digit hexadecimal
280  // number, corresponding to the PartNum bits in the CP15/C0 register.
281  for (auto I : Lines)
282  if (I.consume_front("CPU part"))
283  I.ltrim("\t :").getAsInteger(0, Part);
284 
285  unsigned Exynos = (Variant << 12) | Part;
286  switch (Exynos) {
287  default:
288  // Default by falling through to Exynos M3.
290  case 0x1002:
291  return "exynos-m3";
292  case 0x1003:
293  return "exynos-m4";
294  }
295  }
296 
297  return "generic";
298 }
299 
300 namespace {
301 StringRef getCPUNameFromS390Model(unsigned int Id, bool HaveVectorSupport) {
302  if (Id >= 8561 && HaveVectorSupport)
303  return "z15";
304  if (Id >= 3906 && HaveVectorSupport)
305  return "z14";
306  if (Id >= 2964 && HaveVectorSupport)
307  return "z13";
308  if (Id >= 2827)
309  return "zEC12";
310  if (Id >= 2817)
311  return "z196";
312  return "generic";
313 }
314 } // end anonymous namespace
315 
317  // STIDP is a privileged operation, so use /proc/cpuinfo instead.
318 
319  // The "processor 0:" line comes after a fair amount of other information,
320  // including a cache breakdown, but this should be plenty.
322  ProcCpuinfoContent.split(Lines, "\n");
323 
324  // Look for the CPU features.
325  SmallVector<StringRef, 32> CPUFeatures;
326  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
327  if (Lines[I].startswith("features")) {
328  size_t Pos = Lines[I].find(':');
329  if (Pos != StringRef::npos) {
330  Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
331  break;
332  }
333  }
334 
335  // We need to check for the presence of vector support independently of
336  // the machine type, since we may only use the vector register set when
337  // supported by the kernel (and hypervisor).
338  bool HaveVectorSupport = false;
339  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
340  if (CPUFeatures[I] == "vx")
341  HaveVectorSupport = true;
342  }
343 
344  // Now check the processor machine type.
345  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
346  if (Lines[I].startswith("processor ")) {
347  size_t Pos = Lines[I].find("machine = ");
348  if (Pos != StringRef::npos) {
349  Pos += sizeof("machine = ") - 1;
350  unsigned int Id;
351  if (!Lines[I].drop_front(Pos).getAsInteger(10, Id))
352  return getCPUNameFromS390Model(Id, HaveVectorSupport);
353  }
354  break;
355  }
356  }
357 
358  return "generic";
359 }
360 
362 #if !defined(__linux__) || !defined(__x86_64__)
363  return "generic";
364 #else
365  uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
366  /* BPF_MOV64_IMM(BPF_REG_0, 0) */
367  { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
368  /* BPF_MOV64_IMM(BPF_REG_2, 1) */
369  0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
370  /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
371  0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
372  /* BPF_MOV64_IMM(BPF_REG_0, 1) */
373  0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
374  /* BPF_EXIT_INSN() */
375  0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
376 
377  uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
378  /* BPF_MOV64_IMM(BPF_REG_0, 0) */
379  { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
380  /* BPF_MOV64_IMM(BPF_REG_2, 1) */
381  0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
382  /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
383  0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
384  /* BPF_MOV64_IMM(BPF_REG_0, 1) */
385  0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
386  /* BPF_EXIT_INSN() */
387  0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
388 
389  struct bpf_prog_load_attr {
390  uint32_t prog_type;
391  uint32_t insn_cnt;
392  uint64_t insns;
393  uint64_t license;
394  uint32_t log_level;
395  uint32_t log_size;
396  uint64_t log_buf;
397  uint32_t kern_version;
398  uint32_t prog_flags;
399  } attr = {};
400  attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
401  attr.insn_cnt = 5;
402  attr.insns = (uint64_t)v3_insns;
403  attr.license = (uint64_t)"DUMMY";
404 
405  int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr,
406  sizeof(attr));
407  if (fd >= 0) {
408  close(fd);
409  return "v3";
410  }
411 
412  /* Clear the whole attr in case its content changed by syscall. */
413  memset(&attr, 0, sizeof(attr));
414  attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
415  attr.insn_cnt = 5;
416  attr.insns = (uint64_t)v2_insns;
417  attr.license = (uint64_t)"DUMMY";
418  fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
419  if (fd >= 0) {
420  close(fd);
421  return "v2";
422  }
423  return "v1";
424 #endif
425 }
426 
427 #if defined(__i386__) || defined(_M_IX86) || \
428  defined(__x86_64__) || defined(_M_X64)
429 
430 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
431 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
432 // support. Consequently, for i386, the presence of CPUID is checked first
433 // via the corresponding eflags bit.
434 // Removal of cpuid.h header motivated by PR30384
435 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
436 // or test-suite, but are used in external projects e.g. libstdcxx
437 static bool isCpuIdSupported() {
438 #if defined(__GNUC__) || defined(__clang__)
439 #if defined(__i386__)
440  int __cpuid_supported;
441  __asm__(" pushfl\n"
442  " popl %%eax\n"
443  " movl %%eax,%%ecx\n"
444  " xorl $0x00200000,%%eax\n"
445  " pushl %%eax\n"
446  " popfl\n"
447  " pushfl\n"
448  " popl %%eax\n"
449  " movl $0,%0\n"
450  " cmpl %%eax,%%ecx\n"
451  " je 1f\n"
452  " movl $1,%0\n"
453  "1:"
454  : "=r"(__cpuid_supported)
455  :
456  : "eax", "ecx");
457  if (!__cpuid_supported)
458  return false;
459 #endif
460  return true;
461 #endif
462  return true;
463 }
464 
465 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
466 /// the specified arguments. If we can't run cpuid on the host, return true.
467 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
468  unsigned *rECX, unsigned *rEDX) {
469 #if defined(__GNUC__) || defined(__clang__)
470 #if defined(__x86_64__)
471  // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
472  // FIXME: should we save this for Clang?
473  __asm__("movq\t%%rbx, %%rsi\n\t"
474  "cpuid\n\t"
475  "xchgq\t%%rbx, %%rsi\n\t"
476  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
477  : "a"(value));
478  return false;
479 #elif defined(__i386__)
480  __asm__("movl\t%%ebx, %%esi\n\t"
481  "cpuid\n\t"
482  "xchgl\t%%ebx, %%esi\n\t"
483  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
484  : "a"(value));
485  return false;
486 #else
487  return true;
488 #endif
489 #elif defined(_MSC_VER)
490  // The MSVC intrinsic is portable across x86 and x64.
491  int registers[4];
492  __cpuid(registers, value);
493  *rEAX = registers[0];
494  *rEBX = registers[1];
495  *rECX = registers[2];
496  *rEDX = registers[3];
497  return false;
498 #else
499  return true;
500 #endif
501 }
502 
503 namespace llvm {
504 namespace sys {
505 namespace detail {
506 namespace x86 {
507 
508 VendorSignatures getVendorSignature(unsigned *MaxLeaf) {
509  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
510  if (MaxLeaf == nullptr)
511  MaxLeaf = &EAX;
512  else
513  *MaxLeaf = 0;
514 
515  if (!isCpuIdSupported())
517 
518  if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)
520 
521  // "Genu ineI ntel"
522  if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)
523  return VendorSignatures::GENUINE_INTEL;
524 
525  // "Auth enti cAMD"
526  if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
527  return VendorSignatures::AUTHENTIC_AMD;
528 
530 }
531 
532 } // namespace x86
533 } // namespace detail
534 } // namespace sys
535 } // namespace llvm
536 
537 using namespace llvm::sys::detail::x86;
538 
539 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
540 /// the 4 values in the specified arguments. If we can't run cpuid on the host,
541 /// return true.
542 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
543  unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
544  unsigned *rEDX) {
545 #if defined(__GNUC__) || defined(__clang__)
546 #if defined(__x86_64__)
547  // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
548  // FIXME: should we save this for Clang?
549  __asm__("movq\t%%rbx, %%rsi\n\t"
550  "cpuid\n\t"
551  "xchgq\t%%rbx, %%rsi\n\t"
552  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
553  : "a"(value), "c"(subleaf));
554  return false;
555 #elif defined(__i386__)
556  __asm__("movl\t%%ebx, %%esi\n\t"
557  "cpuid\n\t"
558  "xchgl\t%%ebx, %%esi\n\t"
559  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
560  : "a"(value), "c"(subleaf));
561  return false;
562 #else
563  return true;
564 #endif
565 #elif defined(_MSC_VER)
566  int registers[4];
567  __cpuidex(registers, value, subleaf);
568  *rEAX = registers[0];
569  *rEBX = registers[1];
570  *rECX = registers[2];
571  *rEDX = registers[3];
572  return false;
573 #else
574  return true;
575 #endif
576 }
577 
578 // Read control register 0 (XCR0). Used to detect features such as AVX.
579 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
580 #if defined(__GNUC__) || defined(__clang__)
581  // Check xgetbv; this uses a .byte sequence instead of the instruction
582  // directly because older assemblers do not include support for xgetbv and
583  // there is no easy way to conditionally compile based on the assembler used.
584  __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
585  return false;
586 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
587  unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
588  *rEAX = Result;
589  *rEDX = Result >> 32;
590  return false;
591 #else
592  return true;
593 #endif
594 }
595 
596 static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
597  unsigned *Model) {
598  *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
599  *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
600  if (*Family == 6 || *Family == 0xf) {
601  if (*Family == 0xf)
602  // Examine extended family ID if family ID is F.
603  *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
604  // Examine extended model ID if family ID is 6 or F.
605  *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
606  }
607 }
608 
609 static StringRef
610 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
611  const unsigned *Features,
612  unsigned *Type, unsigned *Subtype) {
613  auto testFeature = [&](unsigned F) {
614  return (Features[F / 32] & (1U << (F % 32))) != 0;
615  };
616 
617  StringRef CPU;
618 
619  switch (Family) {
620  case 3:
621  CPU = "i386";
622  break;
623  case 4:
624  CPU = "i486";
625  break;
626  case 5:
627  if (testFeature(X86::FEATURE_MMX)) {
628  CPU = "pentium-mmx";
629  break;
630  }
631  CPU = "pentium";
632  break;
633  case 6:
634  switch (Model) {
635  case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
636  // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
637  // mobile processor, Intel Core 2 Extreme processor, Intel
638  // Pentium Dual-Core processor, Intel Xeon processor, model
639  // 0Fh. All processors are manufactured using the 65 nm process.
640  case 0x16: // Intel Celeron processor model 16h. All processors are
641  // manufactured using the 65 nm process
642  CPU = "core2";
643  *Type = X86::INTEL_CORE2;
644  break;
645  case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
646  // 17h. All processors are manufactured using the 45 nm process.
647  //
648  // 45nm: Penryn , Wolfdale, Yorkfield (XE)
649  case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
650  // the 45 nm process.
651  CPU = "penryn";
652  *Type = X86::INTEL_CORE2;
653  break;
654  case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
655  // processors are manufactured using the 45 nm process.
656  case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
657  // As found in a Summer 2010 model iMac.
658  case 0x1f:
659  case 0x2e: // Nehalem EX
660  CPU = "nehalem";
661  *Type = X86::INTEL_COREI7;
662  *Subtype = X86::INTEL_COREI7_NEHALEM;
663  break;
664  case 0x25: // Intel Core i7, laptop version.
665  case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
666  // processors are manufactured using the 32 nm process.
667  case 0x2f: // Westmere EX
668  CPU = "westmere";
669  *Type = X86::INTEL_COREI7;
670  *Subtype = X86::INTEL_COREI7_WESTMERE;
671  break;
672  case 0x2a: // Intel Core i7 processor. All processors are manufactured
673  // using the 32 nm process.
674  case 0x2d:
675  CPU = "sandybridge";
676  *Type = X86::INTEL_COREI7;
677  *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
678  break;
679  case 0x3a:
680  case 0x3e: // Ivy Bridge EP
681  CPU = "ivybridge";
682  *Type = X86::INTEL_COREI7;
683  *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
684  break;
685 
686  // Haswell:
687  case 0x3c:
688  case 0x3f:
689  case 0x45:
690  case 0x46:
691  CPU = "haswell";
692  *Type = X86::INTEL_COREI7;
693  *Subtype = X86::INTEL_COREI7_HASWELL;
694  break;
695 
696  // Broadwell:
697  case 0x3d:
698  case 0x47:
699  case 0x4f:
700  case 0x56:
701  CPU = "broadwell";
702  *Type = X86::INTEL_COREI7;
703  *Subtype = X86::INTEL_COREI7_BROADWELL;
704  break;
705 
706  // Skylake:
707  case 0x4e: // Skylake mobile
708  case 0x5e: // Skylake desktop
709  case 0x8e: // Kaby Lake mobile
710  case 0x9e: // Kaby Lake desktop
711  case 0xa5: // Comet Lake-H/S
712  case 0xa6: // Comet Lake-U
713  CPU = "skylake";
714  *Type = X86::INTEL_COREI7;
715  *Subtype = X86::INTEL_COREI7_SKYLAKE;
716  break;
717 
718  // Rocketlake:
719  case 0xa7:
720  CPU = "rocketlake";
721  *Type = X86::INTEL_COREI7;
722  *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
723  break;
724 
725  // Skylake Xeon:
726  case 0x55:
727  *Type = X86::INTEL_COREI7;
728  if (testFeature(X86::FEATURE_AVX512BF16)) {
729  CPU = "cooperlake";
730  *Subtype = X86::INTEL_COREI7_COOPERLAKE;
731  } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
732  CPU = "cascadelake";
733  *Subtype = X86::INTEL_COREI7_CASCADELAKE;
734  } else {
735  CPU = "skylake-avx512";
736  *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
737  }
738  break;
739 
740  // Cannonlake:
741  case 0x66:
742  CPU = "cannonlake";
743  *Type = X86::INTEL_COREI7;
744  *Subtype = X86::INTEL_COREI7_CANNONLAKE;
745  break;
746 
747  // Icelake:
748  case 0x7d:
749  case 0x7e:
750  CPU = "icelake-client";
751  *Type = X86::INTEL_COREI7;
752  *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
753  break;
754 
755  // Icelake Xeon:
756  case 0x6a:
757  case 0x6c:
758  CPU = "icelake-server";
759  *Type = X86::INTEL_COREI7;
760  *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
761  break;
762 
763  // Sapphire Rapids:
764  case 0x8f:
765  CPU = "sapphirerapids";
766  *Type = X86::INTEL_COREI7;
767  *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
768  break;
769 
770  case 0x1c: // Most 45 nm Intel Atom processors
771  case 0x26: // 45 nm Atom Lincroft
772  case 0x27: // 32 nm Atom Medfield
773  case 0x35: // 32 nm Atom Midview
774  case 0x36: // 32 nm Atom Midview
775  CPU = "bonnell";
776  *Type = X86::INTEL_BONNELL;
777  break;
778 
779  // Atom Silvermont codes from the Intel software optimization guide.
780  case 0x37:
781  case 0x4a:
782  case 0x4d:
783  case 0x5a:
784  case 0x5d:
785  case 0x4c: // really airmont
786  CPU = "silvermont";
787  *Type = X86::INTEL_SILVERMONT;
788  break;
789  // Goldmont:
790  case 0x5c: // Apollo Lake
791  case 0x5f: // Denverton
792  CPU = "goldmont";
793  *Type = X86::INTEL_GOLDMONT;
794  break;
795  case 0x7a:
796  CPU = "goldmont-plus";
797  *Type = X86::INTEL_GOLDMONT_PLUS;
798  break;
799  case 0x86:
800  CPU = "tremont";
801  *Type = X86::INTEL_TREMONT;
802  break;
803 
804  // Xeon Phi (Knights Landing + Knights Mill):
805  case 0x57:
806  CPU = "knl";
807  *Type = X86::INTEL_KNL;
808  break;
809  case 0x85:
810  CPU = "knm";
811  *Type = X86::INTEL_KNM;
812  break;
813 
814  default: // Unknown family 6 CPU, try to guess.
815  // Don't both with Type/Subtype here, they aren't used by the caller.
816  // They're used above to keep the code in sync with compiler-rt.
817  // TODO detect tigerlake host from model
818  if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
819  CPU = "tigerlake";
820  } else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
821  CPU = "icelake-client";
822  } else if (testFeature(X86::FEATURE_AVX512VBMI)) {
823  CPU = "cannonlake";
824  } else if (testFeature(X86::FEATURE_AVX512BF16)) {
825  CPU = "cooperlake";
826  } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
827  CPU = "cascadelake";
828  } else if (testFeature(X86::FEATURE_AVX512VL)) {
829  CPU = "skylake-avx512";
830  } else if (testFeature(X86::FEATURE_AVX512ER)) {
831  CPU = "knl";
832  } else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
833  if (testFeature(X86::FEATURE_SHA))
834  CPU = "goldmont";
835  else
836  CPU = "skylake";
837  } else if (testFeature(X86::FEATURE_ADX)) {
838  CPU = "broadwell";
839  } else if (testFeature(X86::FEATURE_AVX2)) {
840  CPU = "haswell";
841  } else if (testFeature(X86::FEATURE_AVX)) {
842  CPU = "sandybridge";
843  } else if (testFeature(X86::FEATURE_SSE4_2)) {
844  if (testFeature(X86::FEATURE_MOVBE))
845  CPU = "silvermont";
846  else
847  CPU = "nehalem";
848  } else if (testFeature(X86::FEATURE_SSE4_1)) {
849  CPU = "penryn";
850  } else if (testFeature(X86::FEATURE_SSSE3)) {
851  if (testFeature(X86::FEATURE_MOVBE))
852  CPU = "bonnell";
853  else
854  CPU = "core2";
855  } else if (testFeature(X86::FEATURE_64BIT)) {
856  CPU = "core2";
857  } else if (testFeature(X86::FEATURE_SSE3)) {
858  CPU = "yonah";
859  } else if (testFeature(X86::FEATURE_SSE2)) {
860  CPU = "pentium-m";
861  } else if (testFeature(X86::FEATURE_SSE)) {
862  CPU = "pentium3";
863  } else if (testFeature(X86::FEATURE_MMX)) {
864  CPU = "pentium2";
865  } else {
866  CPU = "pentiumpro";
867  }
868  break;
869  }
870  break;
871  case 15: {
872  if (testFeature(X86::FEATURE_64BIT)) {
873  CPU = "nocona";
874  break;
875  }
876  if (testFeature(X86::FEATURE_SSE3)) {
877  CPU = "prescott";
878  break;
879  }
880  CPU = "pentium4";
881  break;
882  }
883  default:
884  break; // Unknown.
885  }
886 
887  return CPU;
888 }
889 
890 static StringRef
891 getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
892  const unsigned *Features,
893  unsigned *Type, unsigned *Subtype) {
894  auto testFeature = [&](unsigned F) {
895  return (Features[F / 32] & (1U << (F % 32))) != 0;
896  };
897 
898  StringRef CPU;
899 
900  switch (Family) {
901  case 4:
902  CPU = "i486";
903  break;
904  case 5:
905  CPU = "pentium";
906  switch (Model) {
907  case 6:
908  case 7:
909  CPU = "k6";
910  break;
911  case 8:
912  CPU = "k6-2";
913  break;
914  case 9:
915  case 13:
916  CPU = "k6-3";
917  break;
918  case 10:
919  CPU = "geode";
920  break;
921  }
922  break;
923  case 6:
924  if (testFeature(X86::FEATURE_SSE)) {
925  CPU = "athlon-xp";
926  break;
927  }
928  CPU = "athlon";
929  break;
930  case 15:
931  if (testFeature(X86::FEATURE_SSE3)) {
932  CPU = "k8-sse3";
933  break;
934  }
935  CPU = "k8";
936  break;
937  case 16:
938  CPU = "amdfam10";
939  *Type = X86::AMDFAM10H; // "amdfam10"
940  switch (Model) {
941  case 2:
942  *Subtype = X86::AMDFAM10H_BARCELONA;
943  break;
944  case 4:
945  *Subtype = X86::AMDFAM10H_SHANGHAI;
946  break;
947  case 8:
948  *Subtype = X86::AMDFAM10H_ISTANBUL;
949  break;
950  }
951  break;
952  case 20:
953  CPU = "btver1";
954  *Type = X86::AMD_BTVER1;
955  break;
956  case 21:
957  CPU = "bdver1";
958  *Type = X86::AMDFAM15H;
959  if (Model >= 0x60 && Model <= 0x7f) {
960  CPU = "bdver4";
961  *Subtype = X86::AMDFAM15H_BDVER4;
962  break; // 60h-7Fh: Excavator
963  }
964  if (Model >= 0x30 && Model <= 0x3f) {
965  CPU = "bdver3";
966  *Subtype = X86::AMDFAM15H_BDVER3;
967  break; // 30h-3Fh: Steamroller
968  }
969  if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
970  CPU = "bdver2";
971  *Subtype = X86::AMDFAM15H_BDVER2;
972  break; // 02h, 10h-1Fh: Piledriver
973  }
974  if (Model <= 0x0f) {
975  *Subtype = X86::AMDFAM15H_BDVER1;
976  break; // 00h-0Fh: Bulldozer
977  }
978  break;
979  case 22:
980  CPU = "btver2";
981  *Type = X86::AMD_BTVER2;
982  break;
983  case 23:
984  CPU = "znver1";
985  *Type = X86::AMDFAM17H;
986  if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) {
987  CPU = "znver2";
988  *Subtype = X86::AMDFAM17H_ZNVER2;
989  break; // 30h-3fh, 71h: Zen2
990  }
991  if (Model <= 0x0f) {
992  *Subtype = X86::AMDFAM17H_ZNVER1;
993  break; // 00h-0Fh: Zen1
994  }
995  break;
996  case 25:
997  CPU = "znver3";
998  *Type = X86::AMDFAM19H;
999  if (Model <= 0x0f) {
1000  *Subtype = X86::AMDFAM19H_ZNVER3;
1001  break; // 00h-0Fh: Zen3
1002  }
1003  break;
1004  default:
1005  break; // Unknown AMD CPU.
1006  }
1007 
1008  return CPU;
1009 }
1010 
1011 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
1012  unsigned *Features) {
1013  unsigned EAX, EBX;
1014 
1015  auto setFeature = [&](unsigned F) {
1016  Features[F / 32] |= 1U << (F % 32);
1017  };
1018 
1019  if ((EDX >> 15) & 1)
1020  setFeature(X86::FEATURE_CMOV);
1021  if ((EDX >> 23) & 1)
1022  setFeature(X86::FEATURE_MMX);
1023  if ((EDX >> 25) & 1)
1024  setFeature(X86::FEATURE_SSE);
1025  if ((EDX >> 26) & 1)
1026  setFeature(X86::FEATURE_SSE2);
1027 
1028  if ((ECX >> 0) & 1)
1029  setFeature(X86::FEATURE_SSE3);
1030  if ((ECX >> 1) & 1)
1031  setFeature(X86::FEATURE_PCLMUL);
1032  if ((ECX >> 9) & 1)
1033  setFeature(X86::FEATURE_SSSE3);
1034  if ((ECX >> 12) & 1)
1035  setFeature(X86::FEATURE_FMA);
1036  if ((ECX >> 19) & 1)
1037  setFeature(X86::FEATURE_SSE4_1);
1038  if ((ECX >> 20) & 1)
1039  setFeature(X86::FEATURE_SSE4_2);
1040  if ((ECX >> 23) & 1)
1041  setFeature(X86::FEATURE_POPCNT);
1042  if ((ECX >> 25) & 1)
1043  setFeature(X86::FEATURE_AES);
1044 
1045  if ((ECX >> 22) & 1)
1046  setFeature(X86::FEATURE_MOVBE);
1047 
1048  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1049  // indicates that the AVX registers will be saved and restored on context
1050  // switch, then we have full AVX support.
1051  const unsigned AVXBits = (1 << 27) | (1 << 28);
1052  bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1053  ((EAX & 0x6) == 0x6);
1054 #if defined(__APPLE__)
1055  // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1056  // save the AVX512 context if we use AVX512 instructions, even the bit is not
1057  // set right now.
1058  bool HasAVX512Save = true;
1059 #else
1060  // AVX512 requires additional context to be saved by the OS.
1061  bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
1062 #endif
1063 
1064  if (HasAVX)
1065  setFeature(X86::FEATURE_AVX);
1066 
1067  bool HasLeaf7 =
1068  MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1069 
1070  if (HasLeaf7 && ((EBX >> 3) & 1))
1071  setFeature(X86::FEATURE_BMI);
1072  if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1073  setFeature(X86::FEATURE_AVX2);
1074  if (HasLeaf7 && ((EBX >> 8) & 1))
1075  setFeature(X86::FEATURE_BMI2);
1076  if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
1077  setFeature(X86::FEATURE_AVX512F);
1078  if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1079  setFeature(X86::FEATURE_AVX512DQ);
1080  if (HasLeaf7 && ((EBX >> 19) & 1))
1081  setFeature(X86::FEATURE_ADX);
1082  if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1083  setFeature(X86::FEATURE_AVX512IFMA);
1084  if (HasLeaf7 && ((EBX >> 23) & 1))
1085  setFeature(X86::FEATURE_CLFLUSHOPT);
1086  if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
1087  setFeature(X86::FEATURE_AVX512PF);
1088  if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
1089  setFeature(X86::FEATURE_AVX512ER);
1090  if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1091  setFeature(X86::FEATURE_AVX512CD);
1092  if (HasLeaf7 && ((EBX >> 29) & 1))
1093  setFeature(X86::FEATURE_SHA);
1094  if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1095  setFeature(X86::FEATURE_AVX512BW);
1096  if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1097  setFeature(X86::FEATURE_AVX512VL);
1098 
1099  if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1100  setFeature(X86::FEATURE_AVX512VBMI);
1101  if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1102  setFeature(X86::FEATURE_AVX512VBMI2);
1103  if (HasLeaf7 && ((ECX >> 8) & 1))
1104  setFeature(X86::FEATURE_GFNI);
1105  if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1106  setFeature(X86::FEATURE_VPCLMULQDQ);
1107  if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1108  setFeature(X86::FEATURE_AVX512VNNI);
1109  if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1110  setFeature(X86::FEATURE_AVX512BITALG);
1111  if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1112  setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1113 
1114  if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1115  setFeature(X86::FEATURE_AVX5124VNNIW);
1116  if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1117  setFeature(X86::FEATURE_AVX5124FMAPS);
1118  if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1119  setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1120 
1121  bool HasLeaf7Subleaf1 =
1122  MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1123  if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1124  setFeature(X86::FEATURE_AVX512BF16);
1125 
1126  unsigned MaxExtLevel;
1127  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1128 
1129  bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1130  !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1131  if (HasExtLeaf1 && ((ECX >> 6) & 1))
1132  setFeature(X86::FEATURE_SSE4_A);
1133  if (HasExtLeaf1 && ((ECX >> 11) & 1))
1134  setFeature(X86::FEATURE_XOP);
1135  if (HasExtLeaf1 && ((ECX >> 16) & 1))
1136  setFeature(X86::FEATURE_FMA4);
1137 
1138  if (HasExtLeaf1 && ((EDX >> 29) & 1))
1139  setFeature(X86::FEATURE_64BIT);
1140 }
1141 
1143  unsigned MaxLeaf = 0;
1144  const VendorSignatures Vendor = getVendorSignature(&MaxLeaf);
1145  if (Vendor == VendorSignatures::UNKNOWN)
1146  return "generic";
1147 
1148  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1149  getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1150 
1151  unsigned Family = 0, Model = 0;
1152  unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0};
1153  detectX86FamilyModel(EAX, &Family, &Model);
1154  getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1155 
1156  // These aren't consumed in this file, but we try to keep some source code the
1157  // same or similar to compiler-rt.
1158  unsigned Type = 0;
1159  unsigned Subtype = 0;
1160 
1161  StringRef CPU;
1162 
1163  if (Vendor == VendorSignatures::GENUINE_INTEL) {
1164  CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type,
1165  &Subtype);
1166  } else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
1167  CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type,
1168  &Subtype);
1169  }
1170 
1171  if (!CPU.empty())
1172  return CPU;
1173 
1174  return "generic";
1175 }
1176 
1177 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
1179  host_basic_info_data_t hostInfo;
1180  mach_msg_type_number_t infoCount;
1181 
1182  infoCount = HOST_BASIC_INFO_COUNT;
1183  mach_port_t hostPort = mach_host_self();
1184  host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1185  &infoCount);
1186  mach_port_deallocate(mach_task_self(), hostPort);
1187 
1188  if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1189  return "generic";
1190 
1191  switch (hostInfo.cpu_subtype) {
1193  return "601";
1195  return "602";
1197  return "603";
1199  return "603e";
1201  return "603ev";
1203  return "604";
1205  return "604e";
1207  return "620";
1209  return "750";
1211  return "7400";
1213  return "7450";
1215  return "970";
1216  default:;
1217  }
1218 
1219  return "generic";
1220 }
1221 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
1223  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1224  StringRef Content = P ? P->getBuffer() : "";
1226 }
1227 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1229  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1230  StringRef Content = P ? P->getBuffer() : "";
1232 }
1233 #elif defined(__linux__) && defined(__s390x__)
1235  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1236  StringRef Content = P ? P->getBuffer() : "";
1238 }
1239 #elif defined(__MVS__)
1241  // Get pointer to Communications Vector Table (CVT).
1242  // The pointer is located at offset 16 of the Prefixed Save Area (PSA).
1243  // It is stored as 31 bit pointer and will be zero-extended to 64 bit.
1244  int *StartToCVTOffset = reinterpret_cast<int *>(0x10);
1245  // Since its stored as a 31-bit pointer, get the 4 bytes from the start
1246  // of address.
1247  int ReadValue = *StartToCVTOffset;
1248  // Explicitly clear the high order bit.
1249  ReadValue = (ReadValue & 0x7FFFFFFF);
1250  char *CVT = reinterpret_cast<char *>(ReadValue);
1251  // The model number is located in the CVT prefix at offset -6 and stored as
1252  // signless packed decimal.
1253  uint16_t Id = *(uint16_t *)&CVT[-6];
1254  // Convert number to integer.
1255  Id = decodePackedBCD<uint16_t>(Id, false);
1256  // Check for vector support. It's stored in field CVTFLAG5 (offset 244),
1257  // bit CVTVEF (X'80'). The facilities list is part of the PSA but the vector
1258  // extension can only be used if bit CVTVEF is on.
1259  bool HaveVectorSupport = CVT[244] & 0x80;
1260  return getCPUNameFromS390Model(Id, HaveVectorSupport);
1261 }
1262 #elif defined(__APPLE__) && defined(__aarch64__)
1264  return "cyclone";
1265 }
1266 #elif defined(__APPLE__) && defined(__arm__)
1268  host_basic_info_data_t hostInfo;
1269  mach_msg_type_number_t infoCount;
1270 
1271  infoCount = HOST_BASIC_INFO_COUNT;
1272  mach_port_t hostPort = mach_host_self();
1273  host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1274  &infoCount);
1275  mach_port_deallocate(mach_task_self(), hostPort);
1276 
1277  if (hostInfo.cpu_type != CPU_TYPE_ARM) {
1278  assert(false && "CPUType not equal to ARM should not be possible on ARM");
1279  return "generic";
1280  }
1281  switch (hostInfo.cpu_subtype) {
1282  case CPU_SUBTYPE_ARM_V7S:
1283  return "swift";
1284  default:;
1285  }
1286 
1287  return "generic";
1288 }
1289 #elif defined(_AIX)
1291  switch (_system_configuration.implementation) {
1292  case POWER_4:
1293  if (_system_configuration.version == PV_4_3)
1294  return "970";
1295  return "pwr4";
1296  case POWER_5:
1297  if (_system_configuration.version == PV_5)
1298  return "pwr5";
1299  return "pwr5x";
1300  case POWER_6:
1301  if (_system_configuration.version == PV_6_Compat)
1302  return "pwr6";
1303  return "pwr6x";
1304  case POWER_7:
1305  return "pwr7";
1306  case POWER_8:
1307  return "pwr8";
1308  case POWER_9:
1309  return "pwr9";
1310 // TODO: simplify this once the macro is available in all OS levels.
1311 #ifdef POWER_10
1312  case POWER_10:
1313 #else
1314  case 0x40000:
1315 #endif
1316  return "pwr10";
1317  default:
1318  return "generic";
1319  }
1320 }
1321 #else
1322 StringRef sys::getHostCPUName() { return "generic"; }
1323 namespace llvm {
1324 namespace sys {
1325 namespace detail {
1326 namespace x86 {
1327 
1330 }
1331 
1332 } // namespace x86
1333 } // namespace detail
1334 } // namespace sys
1335 } // namespace llvm
1336 #endif
1337 
1338 #if defined(__linux__) && (defined(__i386__) || defined(__x86_64__))
1339 // On Linux, the number of physical cores can be computed from /proc/cpuinfo,
1340 // using the number of unique physical/core id pairs. The following
1341 // implementation reads the /proc/cpuinfo format on an x86_64 system.
1343  // Enabled represents the number of physical id/core id pairs with at least
1344  // one processor id enabled by the CPU affinity mask.
1345  cpu_set_t Affinity, Enabled;
1346  if (sched_getaffinity(0, sizeof(Affinity), &Affinity) != 0)
1347  return -1;
1348  CPU_ZERO(&Enabled);
1349 
1350  // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be
1351  // mmapped because it appears to have 0 size.
1353  llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
1354  if (std::error_code EC = Text.getError()) {
1355  llvm::errs() << "Can't read "
1356  << "/proc/cpuinfo: " << EC.message() << "\n";
1357  return -1;
1358  }
1360  (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1,
1361  /*KeepEmpty=*/false);
1362  int CurProcessor = -1;
1363  int CurPhysicalId = -1;
1364  int CurSiblings = -1;
1365  int CurCoreId = -1;
1366  for (StringRef Line : strs) {
1367  std::pair<StringRef, StringRef> Data = Line.split(':');
1368  auto Name = Data.first.trim();
1369  auto Val = Data.second.trim();
1370  // These fields are available if the kernel is configured with CONFIG_SMP.
1371  if (Name == "processor")
1372  Val.getAsInteger(10, CurProcessor);
1373  else if (Name == "physical id")
1374  Val.getAsInteger(10, CurPhysicalId);
1375  else if (Name == "siblings")
1376  Val.getAsInteger(10, CurSiblings);
1377  else if (Name == "core id") {
1378  Val.getAsInteger(10, CurCoreId);
1379  // The processor id corresponds to an index into cpu_set_t.
1380  if (CPU_ISSET(CurProcessor, &Affinity))
1381  CPU_SET(CurPhysicalId * CurSiblings + CurCoreId, &Enabled);
1382  }
1383  }
1384  return CPU_COUNT(&Enabled);
1385 }
1386 #elif defined(__linux__) && defined(__powerpc__)
1388  cpu_set_t Affinity;
1389  if (sched_getaffinity(0, sizeof(Affinity), &Affinity) == 0)
1390  return CPU_COUNT(&Affinity);
1391 
1392  // The call to sched_getaffinity() may have failed because the Affinity
1393  // mask is too small for the number of CPU's on the system (i.e. the
1394  // system has more than 1024 CPUs). Allocate a mask large enough for
1395  // twice as many CPUs.
1396  cpu_set_t *DynAffinity;
1397  DynAffinity = CPU_ALLOC(2048);
1398  if (sched_getaffinity(0, CPU_ALLOC_SIZE(2048), DynAffinity) == 0) {
1399  int NumCPUs = CPU_COUNT(DynAffinity);
1400  CPU_FREE(DynAffinity);
1401  return NumCPUs;
1402  }
1403  return -1;
1404 }
1405 #elif defined(__linux__) && defined(__s390x__)
1406 int computeHostNumPhysicalCores() { return sysconf(_SC_NPROCESSORS_ONLN); }
1407 #elif defined(__APPLE__) && defined(__x86_64__)
1408 #include <sys/param.h>
1409 #include <sys/sysctl.h>
1410 
1411 // Gets the number of *physical cores* on the machine.
1413  uint32_t count;
1414  size_t len = sizeof(count);
1415  sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0);
1416  if (count < 1) {
1417  int nm[2];
1418  nm[0] = CTL_HW;
1419  nm[1] = HW_AVAILCPU;
1420  sysctl(nm, 2, &count, &len, NULL, 0);
1421  if (count < 1)
1422  return -1;
1423  }
1424  return count;
1425 }
1426 #elif defined(__MVS__)
1428  enum {
1429  // Byte offset of the pointer to the Communications Vector Table (CVT) in
1430  // the Prefixed Save Area (PSA). The table entry is a 31-bit pointer and
1431  // will be zero-extended to uintptr_t.
1432  FLCCVT = 16,
1433  // Byte offset of the pointer to the Common System Data Area (CSD) in the
1434  // CVT. The table entry is a 31-bit pointer and will be zero-extended to
1435  // uintptr_t.
1436  CVTCSD = 660,
1437  // Byte offset to the number of live CPs in the LPAR, stored as a signed
1438  // 32-bit value in the table.
1439  CSD_NUMBER_ONLINE_STANDARD_CPS = 264,
1440  };
1441  char *PSA = 0;
1442  char *CVT = reinterpret_cast<char *>(
1443  static_cast<uintptr_t>(reinterpret_cast<unsigned int &>(PSA[FLCCVT])));
1444  char *CSD = reinterpret_cast<char *>(
1445  static_cast<uintptr_t>(reinterpret_cast<unsigned int &>(CVT[CVTCSD])));
1446  return reinterpret_cast<int &>(CSD[CSD_NUMBER_ONLINE_STANDARD_CPS]);
1447 }
1448 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0
1449 // Defined in llvm/lib/Support/Windows/Threading.inc
1451 #else
1452 // On other systems, return -1 to indicate unknown.
1453 static int computeHostNumPhysicalCores() { return -1; }
1454 #endif
1455 
1457  static int NumCores = computeHostNumPhysicalCores();
1458  return NumCores;
1459 }
1460 
1461 #if defined(__i386__) || defined(_M_IX86) || \
1462  defined(__x86_64__) || defined(_M_X64)
1463 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1464  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1465  unsigned MaxLevel;
1466 
1467  if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
1468  return false;
1469 
1470  getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1471 
1472  Features["cx8"] = (EDX >> 8) & 1;
1473  Features["cmov"] = (EDX >> 15) & 1;
1474  Features["mmx"] = (EDX >> 23) & 1;
1475  Features["fxsr"] = (EDX >> 24) & 1;
1476  Features["sse"] = (EDX >> 25) & 1;
1477  Features["sse2"] = (EDX >> 26) & 1;
1478 
1479  Features["sse3"] = (ECX >> 0) & 1;
1480  Features["pclmul"] = (ECX >> 1) & 1;
1481  Features["ssse3"] = (ECX >> 9) & 1;
1482  Features["cx16"] = (ECX >> 13) & 1;
1483  Features["sse4.1"] = (ECX >> 19) & 1;
1484  Features["sse4.2"] = (ECX >> 20) & 1;
1485  Features["movbe"] = (ECX >> 22) & 1;
1486  Features["popcnt"] = (ECX >> 23) & 1;
1487  Features["aes"] = (ECX >> 25) & 1;
1488  Features["rdrnd"] = (ECX >> 30) & 1;
1489 
1490  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1491  // indicates that the AVX registers will be saved and restored on context
1492  // switch, then we have full AVX support.
1493  bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
1494  bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6);
1495 #if defined(__APPLE__)
1496  // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1497  // save the AVX512 context if we use AVX512 instructions, even the bit is not
1498  // set right now.
1499  bool HasAVX512Save = true;
1500 #else
1501  // AVX512 requires additional context to be saved by the OS.
1502  bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1503 #endif
1504  // AMX requires additional context to be saved by the OS.
1505  const unsigned AMXBits = (1 << 17) | (1 << 18);
1506  bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits);
1507 
1508  Features["avx"] = HasAVXSave;
1509  Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave;
1510  // Only enable XSAVE if OS has enabled support for saving YMM state.
1511  Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
1512  Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave;
1513 
1514  unsigned MaxExtLevel;
1515  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1516 
1517  bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1518  !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1519  Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1);
1520  Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
1521  Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
1522  Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
1523  Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1524  Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);
1525  Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1526  Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
1527  Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1528 
1529  Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1);
1530 
1531  // Miscellaneous memory related features, detected by
1532  // using the 0x80000008 leaf of the CPUID instruction
1533  bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1534  !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1535  Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
1536  Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
1537 
1538  bool HasLeaf7 =
1539  MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1540 
1541  Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
1542  Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
1543  Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1544  // AVX2 is only supported if we have the OS save support from AVX.
1545  Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave;
1546  Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
1547  Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
1548  Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
1549  // AVX512 is only supported if the OS supports the context save for it.
1550  Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1551  Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1552  Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
1553  Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
1554  Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1555  Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1556  Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
1557  Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
1558  Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
1559  Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1560  Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
1561  Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1562  Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1563 
1564  Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1);
1565  Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
1566  Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
1567  Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1);
1568  Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save;
1569  Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1);
1570  Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1);
1571  Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave;
1572  Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
1573  Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
1574  Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
1575  Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
1576  Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1);
1577  Features["kl"] = HasLeaf7 && ((ECX >> 23) & 1); // key locker
1578  Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1);
1579  Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);
1580  Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
1581  Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1);
1582 
1583  Features["uintr"] = HasLeaf7 && ((EDX >> 5) & 1);
1584  Features["avx512vp2intersect"] =
1585  HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save;
1586  Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1);
1587  Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1);
1588  // There are two CPUID leafs which information associated with the pconfig
1589  // instruction:
1590  // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
1591  // bit of EDX), while the EAX=0x1b leaf returns information on the
1592  // availability of specific pconfig leafs.
1593  // The target feature here only refers to the the first of these two.
1594  // Users might need to check for the availability of specific pconfig
1595  // leaves using cpuid, since that information is ignored while
1596  // detecting features using the "-march=native" flag.
1597  // For more info, see X86 ISA docs.
1598  Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
1599  Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;
1600  Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
1601  Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
1602  bool HasLeaf7Subleaf1 =
1603  MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1604  Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;
1605  Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
1606  Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1);
1607 
1608  bool HasLeafD = MaxLevel >= 0xd &&
1609  !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1610 
1611  // Only enable XSAVE if OS has enabled support for saving YMM state.
1612  Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
1613  Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
1614  Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
1615 
1616  bool HasLeaf14 = MaxLevel >= 0x14 &&
1617  !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1618 
1619  Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
1620 
1621  bool HasLeaf19 =
1622  MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
1623  Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1);
1624 
1625  return true;
1626 }
1627 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1628 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1629  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1630  if (!P)
1631  return false;
1632 
1634  P->getBuffer().split(Lines, "\n");
1635 
1636  SmallVector<StringRef, 32> CPUFeatures;
1637 
1638  // Look for the CPU features.
1639  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1640  if (Lines[I].startswith("Features")) {
1641  Lines[I].split(CPUFeatures, ' ');
1642  break;
1643  }
1644 
1645 #if defined(__aarch64__)
1646  // Keep track of which crypto features we have seen
1647  enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1648  uint32_t crypto = 0;
1649 #endif
1650 
1651  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1652  StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1653 #if defined(__aarch64__)
1654  .Case("asimd", "neon")
1655  .Case("fp", "fp-armv8")
1656  .Case("crc32", "crc")
1657 #else
1658  .Case("half", "fp16")
1659  .Case("neon", "neon")
1660  .Case("vfpv3", "vfp3")
1661  .Case("vfpv3d16", "d16")
1662  .Case("vfpv4", "vfp4")
1663  .Case("idiva", "hwdiv-arm")
1664  .Case("idivt", "hwdiv")
1665 #endif
1666  .Default("");
1667 
1668 #if defined(__aarch64__)
1669  // We need to check crypto separately since we need all of the crypto
1670  // extensions to enable the subtarget feature
1671  if (CPUFeatures[I] == "aes")
1672  crypto |= CAP_AES;
1673  else if (CPUFeatures[I] == "pmull")
1674  crypto |= CAP_PMULL;
1675  else if (CPUFeatures[I] == "sha1")
1676  crypto |= CAP_SHA1;
1677  else if (CPUFeatures[I] == "sha2")
1678  crypto |= CAP_SHA2;
1679 #endif
1680 
1681  if (LLVMFeatureStr != "")
1682  Features[LLVMFeatureStr] = true;
1683  }
1684 
1685 #if defined(__aarch64__)
1686  // If we have all crypto bits we can add the feature
1687  if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1688  Features["crypto"] = true;
1689 #endif
1690 
1691  return true;
1692 }
1693 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
1694 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1695  if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE))
1696  Features["neon"] = true;
1697  if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
1698  Features["crc"] = true;
1699  if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
1700  Features["crypto"] = true;
1701 
1702  return true;
1703 }
1704 #else
1705 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
1706 #endif
1707 
1708 std::string sys::getProcessTriple() {
1709  std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
1710  Triple PT(Triple::normalize(TargetTripleString));
1711 
1712  if (sizeof(void *) == 8 && PT.isArch32Bit())
1713  PT = PT.get64BitArchVariant();
1714  if (sizeof(void *) == 4 && PT.isArch64Bit())
1715  PT = PT.get32BitArchVariant();
1716 
1717  return PT.str();
1718 }
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
MemoryBuffer.h
llvm
Definition: AllocatorList.h:23
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
FileSystem.h
llvm::StringRef::endswith
LLVM_NODISCARD bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:297
llvm::N86::EBX
@ EBX
Definition: X86MCTargetDesc.h:51
llvm::sys::detail::x86::VendorSignatures::GENUINE_INTEL
@ GENUINE_INTEL
StringRef.h
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::MachO::CPU_SUBTYPE_POWERPC_603ev
@ CPU_SUBTYPE_POWERPC_603ev
Definition: MachO.h:1512
llvm::N86::EAX
@ EAX
Definition: X86MCTargetDesc.h:51
llvm::StringRef::npos
static constexpr size_t npos
Definition: StringRef.h:60
Host.h
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1167
llvm::N86::EDX
@ EDX
Definition: X86MCTargetDesc.h:51
Content
T Content
Definition: ELFObjHandler.cpp:90
llvm::Triple::get32BitArchVariant
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
Definition: Triple.cpp:1348
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::MachO::CPU_TYPE_ARM
@ CPU_TYPE_ARM
Definition: MachO.h:1425
Host.inc
startswith
static bool startswith(StringRef Magic, const char(&S)[N])
Definition: Magic.cpp:30
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::sys::getHostCPUFeatures
bool getHostCPUFeatures(StringMap< bool, MallocAllocator > &Features)
getHostCPUFeatures - Get the LLVM names for the host CPU features.
llvm::sys::detail::x86::VendorSignatures::UNKNOWN
@ UNKNOWN
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:892
llvm::MachO::CPU_SUBTYPE_POWERPC_7450
@ CPU_SUBTYPE_POWERPC_7450
Definition: MachO.h:1518
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:188
llvm::MachO::CPU_SUBTYPE_POWERPC_603
@ CPU_SUBTYPE_POWERPC_603
Definition: MachO.h:1510
x86
Note that only the low bits of effective_addr2 are used On bit we don t eliminate the computation of the top half of effective_addr2 because we don t have whole function selection dags On x86
Definition: README.txt:318
llvm::Data
@ Data
Definition: SIMachineScheduler.h:56
llvm::MachO::CPU_SUBTYPE_POWERPC_604e
@ CPU_SUBTYPE_POWERPC_604e
Definition: MachO.h:1514
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::Triple::isArch64Bit
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1336
llvm::MemoryBuffer::getFileAsStream
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
Definition: MemoryBuffer.cpp:528
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::sys::detail::x86
Helper functions to extract CPU details from CPUID on x86.
Definition: Host.h:70
llvm::Triple::get64BitArchVariant
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
Definition: Triple.cpp:1416
llvm::sys::detail::x86::VendorSignatures::AUTHENTIC_AMD
@ AUTHENTIC_AMD
llvm::Triple::str
const std::string & str() const
Definition: Triple.h:376
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::X86::CPU_FEATURE_MAX
@ CPU_FEATURE_MAX
Definition: X86TargetParser.h:59
llvm::StringRef::split
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:727
llvm::MachO::CPU_SUBTYPE_POWERPC_602
@ CPU_SUBTYPE_POWERPC_602
Definition: MachO.h:1509
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::MachO::CPU_TYPE_POWERPC
@ CPU_TYPE_POWERPC
Definition: MachO.h:1429
llvm::ErrorOr::getError
std::error_code getError() const
Definition: ErrorOr.h:153
BCD.h
computeHostNumPhysicalCores
static int computeHostNumPhysicalCores()
Definition: Host.cpp:1453
StringMap.h
llvm::StringMap< bool >
getProcCpuinfoContent
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
Definition: Host.cpp:62
X86TargetParser.h
llvm::AMDGPU::FEATURE_FMA
@ FEATURE_FMA
Definition: TargetParser.h:115
llvm::count
auto count(R &&Range, const E &Element)
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:1565
llvm::StringRef::end
iterator end() const
Definition: StringRef.h:130
llvm::Triple::normalize
std::string normalize() const
Return the normalized form of this triple's string.
Definition: Triple.h:300
llvm::Triple::isArch32Bit
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1340
llvm::MachO::CPU_SUBTYPE_ARM_V7S
@ CPU_SUBTYPE_ARM_V7S
Definition: MachO.h:1489
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MachO::CPU_SUBTYPE_POWERPC_620
@ CPU_SUBTYPE_POWERPC_620
Definition: MachO.h:1515
Host.inc
llvm::MachO::CPU_SUBTYPE_POWERPC_750
@ CPU_SUBTYPE_POWERPC_750
Definition: MachO.h:1516
I
#define I(x, y, z)
Definition: MD5.cpp:59
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::codeview::CompileSym2Flags::EC
@ EC
llvm::MachO::CPU_SUBTYPE_POWERPC_601
@ CPU_SUBTYPE_POWERPC_601
Definition: MachO.h:1508
Triple.h
llvm::sys::getHostNumPhysicalCores
int getHostNumPhysicalCores()
Get the number of physical cores (as opposed to logical cores returned from thread::hardware_concurre...
Definition: Host.cpp:1456
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachO::CPU_SUBTYPE_POWERPC_604
@ CPU_SUBTYPE_POWERPC_604
Definition: MachO.h:1513
llvm::sys::detail::getHostCPUNameForBPF
StringRef getHostCPUNameForBPF()
Definition: Host.cpp:361
uint32_t
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:281
llvm::LPAC::UNKNOWN
@ UNKNOWN
Definition: LanaiAluCode.h:40
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::MachO::CPU_SUBTYPE_POWERPC_7400
@ CPU_SUBTYPE_POWERPC_7400
Definition: MachO.h:1517
llvm::sys::detail::getHostCPUNameForS390x
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
Definition: Host.cpp:316
uint16_t
llvm::sys::detail::x86::VendorSignatures
VendorSignatures
Definition: Host.h:71
llvm::sys::getProcessTriple
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
Definition: Host.cpp:1708
llvm::MachO::CPU_SUBTYPE_POWERPC_603e
@ CPU_SUBTYPE_POWERPC_603e
Definition: MachO.h:1511
Enabled
static bool Enabled
Definition: Statistic.cpp:50
StringSwitch.h
llvm::N86::ECX
@ ECX
Definition: X86MCTargetDesc.h:51
llvm::support::aligned
@ aligned
Definition: Endian.h:30
SmallVector.h
llvm::sys::detail::getHostCPUNameForARM
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
Definition: Host.cpp:156
llvm::sys::detail::getHostCPUNameForPowerPC
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
Definition: Host.cpp:73
llvm::ErrorOr
Represents either an error or a value T.
Definition: ErrorOr.h:56
llvm::StringRef::const_iterator
const char * const_iterator
Definition: StringRef.h:63
llvm::sys::getHostCPUName
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
Definition: Host.cpp:1322
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::sys::detail::x86::getVendorSignature
VendorSignatures getVendorSignature(unsigned *MaxLeaf=nullptr)
Returns the host CPU's vendor.
Definition: Host.cpp:1328
raw_ostream.h
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:221
registers
Implement PPCInstrInfo::isLoadFromStackSlot isStoreToStackSlot for vector registers
Definition: README_ALTIVEC.txt:4
llvm::StringRef::begin
iterator begin() const
Definition: StringRef.h:128
Debug.h
SmallSet.h
llvm::MachO::CPU_SUBTYPE_POWERPC_970
@ CPU_SUBTYPE_POWERPC_970
Definition: MachO.h:1519