LLVM 19.0.0git
Host.cpp
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1//===-- Host.cpp - Implement OS Host Detection ------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the operating system Host detection.
10//
11//===----------------------------------------------------------------------===//
12
15#include "llvm/ADT/StringMap.h"
16#include "llvm/ADT/StringRef.h"
18#include "llvm/Config/llvm-config.h"
23#include <string.h>
24
25// Include the platform-specific parts of this class.
26#ifdef LLVM_ON_UNIX
27#include "Unix/Host.inc"
28#include <sched.h>
29#endif
30#ifdef _WIN32
31#include "Windows/Host.inc"
32#endif
33#ifdef _MSC_VER
34#include <intrin.h>
35#endif
36#ifdef __MVS__
37#include "llvm/Support/BCD.h"
38#endif
39#if defined(__APPLE__)
40#include <mach/host_info.h>
41#include <mach/mach.h>
42#include <mach/mach_host.h>
43#include <mach/machine.h>
44#include <sys/param.h>
45#include <sys/sysctl.h>
46#endif
47#ifdef _AIX
48#include <sys/systemcfg.h>
49#endif
50#if defined(__sun__) && defined(__svr4__)
51#include <kstat.h>
52#endif
53
54#define DEBUG_TYPE "host-detection"
55
56//===----------------------------------------------------------------------===//
57//
58// Implementations of the CPU detection routines
59//
60//===----------------------------------------------------------------------===//
61
62using namespace llvm;
63
64static std::unique_ptr<llvm::MemoryBuffer>
68 if (std::error_code EC = Text.getError()) {
69 llvm::errs() << "Can't read "
70 << "/proc/cpuinfo: " << EC.message() << "\n";
71 return nullptr;
72 }
73 return std::move(*Text);
74}
75
77 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
78 // and so we must use an operating-system interface to determine the current
79 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
80 const char *generic = "generic";
81
82 // The cpu line is second (after the 'processor: 0' line), so if this
83 // buffer is too small then something has changed (or is wrong).
84 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
85 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
86
87 StringRef::const_iterator CIP = CPUInfoStart;
88
89 StringRef::const_iterator CPUStart = nullptr;
90 size_t CPULen = 0;
91
92 // We need to find the first line which starts with cpu, spaces, and a colon.
93 // After the colon, there may be some additional spaces and then the cpu type.
94 while (CIP < CPUInfoEnd && CPUStart == nullptr) {
95 if (CIP < CPUInfoEnd && *CIP == '\n')
96 ++CIP;
97
98 if (CIP < CPUInfoEnd && *CIP == 'c') {
99 ++CIP;
100 if (CIP < CPUInfoEnd && *CIP == 'p') {
101 ++CIP;
102 if (CIP < CPUInfoEnd && *CIP == 'u') {
103 ++CIP;
104 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
105 ++CIP;
106
107 if (CIP < CPUInfoEnd && *CIP == ':') {
108 ++CIP;
109 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
110 ++CIP;
111
112 if (CIP < CPUInfoEnd) {
113 CPUStart = CIP;
114 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
115 *CIP != ',' && *CIP != '\n'))
116 ++CIP;
117 CPULen = CIP - CPUStart;
118 }
119 }
120 }
121 }
122 }
123
124 if (CPUStart == nullptr)
125 while (CIP < CPUInfoEnd && *CIP != '\n')
126 ++CIP;
127 }
128
129 if (CPUStart == nullptr)
130 return generic;
131
132 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
133 .Case("604e", "604e")
134 .Case("604", "604")
135 .Case("7400", "7400")
136 .Case("7410", "7400")
137 .Case("7447", "7400")
138 .Case("7455", "7450")
139 .Case("G4", "g4")
140 .Case("POWER4", "970")
141 .Case("PPC970FX", "970")
142 .Case("PPC970MP", "970")
143 .Case("G5", "g5")
144 .Case("POWER5", "g5")
145 .Case("A2", "a2")
146 .Case("POWER6", "pwr6")
147 .Case("POWER7", "pwr7")
148 .Case("POWER8", "pwr8")
149 .Case("POWER8E", "pwr8")
150 .Case("POWER8NVL", "pwr8")
151 .Case("POWER9", "pwr9")
152 .Case("POWER10", "pwr10")
153 // FIXME: If we get a simulator or machine with the capabilities of
154 // mcpu=future, we should revisit this and add the name reported by the
155 // simulator/machine.
156 .Default(generic);
157}
158
160 // The cpuid register on arm is not accessible from user space. On Linux,
161 // it is exposed through the /proc/cpuinfo file.
162
163 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
164 // in all cases.
166 ProcCpuinfoContent.split(Lines, "\n");
167
168 // Look for the CPU implementer line.
169 StringRef Implementer;
170 StringRef Hardware;
171 StringRef Part;
172 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
173 if (Lines[I].starts_with("CPU implementer"))
174 Implementer = Lines[I].substr(15).ltrim("\t :");
175 if (Lines[I].starts_with("Hardware"))
176 Hardware = Lines[I].substr(8).ltrim("\t :");
177 if (Lines[I].starts_with("CPU part"))
178 Part = Lines[I].substr(8).ltrim("\t :");
179 }
180
181 if (Implementer == "0x41") { // ARM Ltd.
182 // MSM8992/8994 may give cpu part for the core that the kernel is running on,
183 // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
184 if (Hardware.ends_with("MSM8994") || Hardware.ends_with("MSM8996"))
185 return "cortex-a53";
186
187
188 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
189 // values correspond to the "Part number" in the CP15/c0 register. The
190 // contents are specified in the various processor manuals.
191 // This corresponds to the Main ID Register in Technical Reference Manuals.
192 // and is used in programs like sys-utils
193 return StringSwitch<const char *>(Part)
194 .Case("0x926", "arm926ej-s")
195 .Case("0xb02", "mpcore")
196 .Case("0xb36", "arm1136j-s")
197 .Case("0xb56", "arm1156t2-s")
198 .Case("0xb76", "arm1176jz-s")
199 .Case("0xc08", "cortex-a8")
200 .Case("0xc09", "cortex-a9")
201 .Case("0xc0f", "cortex-a15")
202 .Case("0xc20", "cortex-m0")
203 .Case("0xc23", "cortex-m3")
204 .Case("0xc24", "cortex-m4")
205 .Case("0xd24", "cortex-m52")
206 .Case("0xd22", "cortex-m55")
207 .Case("0xd02", "cortex-a34")
208 .Case("0xd04", "cortex-a35")
209 .Case("0xd03", "cortex-a53")
210 .Case("0xd05", "cortex-a55")
211 .Case("0xd46", "cortex-a510")
212 .Case("0xd80", "cortex-a520")
213 .Case("0xd07", "cortex-a57")
214 .Case("0xd08", "cortex-a72")
215 .Case("0xd09", "cortex-a73")
216 .Case("0xd0a", "cortex-a75")
217 .Case("0xd0b", "cortex-a76")
218 .Case("0xd0d", "cortex-a77")
219 .Case("0xd41", "cortex-a78")
220 .Case("0xd47", "cortex-a710")
221 .Case("0xd4d", "cortex-a715")
222 .Case("0xd81", "cortex-a720")
223 .Case("0xd44", "cortex-x1")
224 .Case("0xd4c", "cortex-x1c")
225 .Case("0xd48", "cortex-x2")
226 .Case("0xd4e", "cortex-x3")
227 .Case("0xd82", "cortex-x4")
228 .Case("0xd0c", "neoverse-n1")
229 .Case("0xd49", "neoverse-n2")
230 .Case("0xd40", "neoverse-v1")
231 .Case("0xd4f", "neoverse-v2")
232 .Default("generic");
233 }
234
235 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium.
236 return StringSwitch<const char *>(Part)
237 .Case("0x516", "thunderx2t99")
238 .Case("0x0516", "thunderx2t99")
239 .Case("0xaf", "thunderx2t99")
240 .Case("0x0af", "thunderx2t99")
241 .Case("0xa1", "thunderxt88")
242 .Case("0x0a1", "thunderxt88")
243 .Default("generic");
244 }
245
246 if (Implementer == "0x46") { // Fujitsu Ltd.
247 return StringSwitch<const char *>(Part)
248 .Case("0x001", "a64fx")
249 .Default("generic");
250 }
251
252 if (Implementer == "0x4e") { // NVIDIA Corporation
253 return StringSwitch<const char *>(Part)
254 .Case("0x004", "carmel")
255 .Default("generic");
256 }
257
258 if (Implementer == "0x48") // HiSilicon Technologies, Inc.
259 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
260 // values correspond to the "Part number" in the CP15/c0 register. The
261 // contents are specified in the various processor manuals.
262 return StringSwitch<const char *>(Part)
263 .Case("0xd01", "tsv110")
264 .Default("generic");
265
266 if (Implementer == "0x51") // Qualcomm Technologies, Inc.
267 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
268 // values correspond to the "Part number" in the CP15/c0 register. The
269 // contents are specified in the various processor manuals.
270 return StringSwitch<const char *>(Part)
271 .Case("0x06f", "krait") // APQ8064
272 .Case("0x201", "kryo")
273 .Case("0x205", "kryo")
274 .Case("0x211", "kryo")
275 .Case("0x800", "cortex-a73") // Kryo 2xx Gold
276 .Case("0x801", "cortex-a73") // Kryo 2xx Silver
277 .Case("0x802", "cortex-a75") // Kryo 3xx Gold
278 .Case("0x803", "cortex-a75") // Kryo 3xx Silver
279 .Case("0x804", "cortex-a76") // Kryo 4xx Gold
280 .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver
281 .Case("0xc00", "falkor")
282 .Case("0xc01", "saphira")
283 .Default("generic");
284 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
285 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
286 // any predictive pattern across variants and parts.
287 unsigned Variant = 0, Part = 0;
288
289 // Look for the CPU variant line, whose value is a 1 digit hexadecimal
290 // number, corresponding to the Variant bits in the CP15/C0 register.
291 for (auto I : Lines)
292 if (I.consume_front("CPU variant"))
293 I.ltrim("\t :").getAsInteger(0, Variant);
294
295 // Look for the CPU part line, whose value is a 3 digit hexadecimal
296 // number, corresponding to the PartNum bits in the CP15/C0 register.
297 for (auto I : Lines)
298 if (I.consume_front("CPU part"))
299 I.ltrim("\t :").getAsInteger(0, Part);
300
301 unsigned Exynos = (Variant << 12) | Part;
302 switch (Exynos) {
303 default:
304 // Default by falling through to Exynos M3.
305 [[fallthrough]];
306 case 0x1002:
307 return "exynos-m3";
308 case 0x1003:
309 return "exynos-m4";
310 }
311 }
312
313 if (Implementer == "0x6d") { // Microsoft Corporation.
314 // The Microsoft Azure Cobalt 100 CPU is handled as a Neoverse N2.
315 return StringSwitch<const char *>(Part)
316 .Case("0xd49", "neoverse-n2")
317 .Default("generic");
318 }
319
320 if (Implementer == "0xc0") { // Ampere Computing
321 return StringSwitch<const char *>(Part)
322 .Case("0xac3", "ampere1")
323 .Case("0xac4", "ampere1a")
324 .Case("0xac5", "ampere1b")
325 .Default("generic");
326 }
327
328 return "generic";
329}
330
331namespace {
332StringRef getCPUNameFromS390Model(unsigned int Id, bool HaveVectorSupport) {
333 switch (Id) {
334 case 2064: // z900 not supported by LLVM
335 case 2066:
336 case 2084: // z990 not supported by LLVM
337 case 2086:
338 case 2094: // z9-109 not supported by LLVM
339 case 2096:
340 return "generic";
341 case 2097:
342 case 2098:
343 return "z10";
344 case 2817:
345 case 2818:
346 return "z196";
347 case 2827:
348 case 2828:
349 return "zEC12";
350 case 2964:
351 case 2965:
352 return HaveVectorSupport? "z13" : "zEC12";
353 case 3906:
354 case 3907:
355 return HaveVectorSupport? "z14" : "zEC12";
356 case 8561:
357 case 8562:
358 return HaveVectorSupport? "z15" : "zEC12";
359 case 3931:
360 case 3932:
361 default:
362 return HaveVectorSupport? "z16" : "zEC12";
363 }
364}
365} // end anonymous namespace
366
368 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
369
370 // The "processor 0:" line comes after a fair amount of other information,
371 // including a cache breakdown, but this should be plenty.
373 ProcCpuinfoContent.split(Lines, "\n");
374
375 // Look for the CPU features.
376 SmallVector<StringRef, 32> CPUFeatures;
377 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
378 if (Lines[I].starts_with("features")) {
379 size_t Pos = Lines[I].find(':');
380 if (Pos != StringRef::npos) {
381 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
382 break;
383 }
384 }
385
386 // We need to check for the presence of vector support independently of
387 // the machine type, since we may only use the vector register set when
388 // supported by the kernel (and hypervisor).
389 bool HaveVectorSupport = false;
390 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
391 if (CPUFeatures[I] == "vx")
392 HaveVectorSupport = true;
393 }
394
395 // Now check the processor machine type.
396 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
397 if (Lines[I].starts_with("processor ")) {
398 size_t Pos = Lines[I].find("machine = ");
399 if (Pos != StringRef::npos) {
400 Pos += sizeof("machine = ") - 1;
401 unsigned int Id;
402 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id))
403 return getCPUNameFromS390Model(Id, HaveVectorSupport);
404 }
405 break;
406 }
407 }
408
409 return "generic";
410}
411
413 // There are 24 lines in /proc/cpuinfo
415 ProcCpuinfoContent.split(Lines, "\n");
416
417 // Look for uarch line to determine cpu name
418 StringRef UArch;
419 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
420 if (Lines[I].starts_with("uarch")) {
421 UArch = Lines[I].substr(5).ltrim("\t :");
422 break;
423 }
424 }
425
426 return StringSwitch<const char *>(UArch)
427 .Case("sifive,u74-mc", "sifive-u74")
428 .Case("sifive,bullet0", "sifive-u74")
429 .Default("generic");
430}
431
433#if !defined(__linux__) || !defined(__x86_64__)
434 return "generic";
435#else
436 uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
437 /* BPF_MOV64_IMM(BPF_REG_0, 0) */
438 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
439 /* BPF_MOV64_IMM(BPF_REG_2, 1) */
440 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
441 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
442 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
443 /* BPF_MOV64_IMM(BPF_REG_0, 1) */
444 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
445 /* BPF_EXIT_INSN() */
446 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
447
448 uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
449 /* BPF_MOV64_IMM(BPF_REG_0, 0) */
450 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
451 /* BPF_MOV64_IMM(BPF_REG_2, 1) */
452 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
453 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
454 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
455 /* BPF_MOV64_IMM(BPF_REG_0, 1) */
456 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
457 /* BPF_EXIT_INSN() */
458 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
459
460 struct bpf_prog_load_attr {
461 uint32_t prog_type;
462 uint32_t insn_cnt;
463 uint64_t insns;
464 uint64_t license;
465 uint32_t log_level;
466 uint32_t log_size;
467 uint64_t log_buf;
468 uint32_t kern_version;
469 uint32_t prog_flags;
470 } attr = {};
471 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
472 attr.insn_cnt = 5;
473 attr.insns = (uint64_t)v3_insns;
474 attr.license = (uint64_t)"DUMMY";
475
476 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr,
477 sizeof(attr));
478 if (fd >= 0) {
479 close(fd);
480 return "v3";
481 }
482
483 /* Clear the whole attr in case its content changed by syscall. */
484 memset(&attr, 0, sizeof(attr));
485 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
486 attr.insn_cnt = 5;
487 attr.insns = (uint64_t)v2_insns;
488 attr.license = (uint64_t)"DUMMY";
489 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
490 if (fd >= 0) {
491 close(fd);
492 return "v2";
493 }
494 return "v1";
495#endif
496}
497
498#if defined(__i386__) || defined(_M_IX86) || \
499 defined(__x86_64__) || defined(_M_X64)
500
501// The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
502// Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
503// support. Consequently, for i386, the presence of CPUID is checked first
504// via the corresponding eflags bit.
505// Removal of cpuid.h header motivated by PR30384
506// Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
507// or test-suite, but are used in external projects e.g. libstdcxx
508static bool isCpuIdSupported() {
509#if defined(__GNUC__) || defined(__clang__)
510#if defined(__i386__)
511 int __cpuid_supported;
512 __asm__(" pushfl\n"
513 " popl %%eax\n"
514 " movl %%eax,%%ecx\n"
515 " xorl $0x00200000,%%eax\n"
516 " pushl %%eax\n"
517 " popfl\n"
518 " pushfl\n"
519 " popl %%eax\n"
520 " movl $0,%0\n"
521 " cmpl %%eax,%%ecx\n"
522 " je 1f\n"
523 " movl $1,%0\n"
524 "1:"
525 : "=r"(__cpuid_supported)
526 :
527 : "eax", "ecx");
528 if (!__cpuid_supported)
529 return false;
530#endif
531 return true;
532#endif
533 return true;
534}
535
536/// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
537/// the specified arguments. If we can't run cpuid on the host, return true.
538static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
539 unsigned *rECX, unsigned *rEDX) {
540#if defined(__GNUC__) || defined(__clang__)
541#if defined(__x86_64__)
542 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
543 // FIXME: should we save this for Clang?
544 __asm__("movq\t%%rbx, %%rsi\n\t"
545 "cpuid\n\t"
546 "xchgq\t%%rbx, %%rsi\n\t"
547 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
548 : "a"(value));
549 return false;
550#elif defined(__i386__)
551 __asm__("movl\t%%ebx, %%esi\n\t"
552 "cpuid\n\t"
553 "xchgl\t%%ebx, %%esi\n\t"
554 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
555 : "a"(value));
556 return false;
557#else
558 return true;
559#endif
560#elif defined(_MSC_VER)
561 // The MSVC intrinsic is portable across x86 and x64.
562 int registers[4];
563 __cpuid(registers, value);
564 *rEAX = registers[0];
565 *rEBX = registers[1];
566 *rECX = registers[2];
567 *rEDX = registers[3];
568 return false;
569#else
570 return true;
571#endif
572}
573
574namespace llvm {
575namespace sys {
576namespace detail {
577namespace x86 {
578
579VendorSignatures getVendorSignature(unsigned *MaxLeaf) {
580 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
581 if (MaxLeaf == nullptr)
582 MaxLeaf = &EAX;
583 else
584 *MaxLeaf = 0;
585
586 if (!isCpuIdSupported())
587 return VendorSignatures::UNKNOWN;
588
589 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)
590 return VendorSignatures::UNKNOWN;
591
592 // "Genu ineI ntel"
593 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)
594 return VendorSignatures::GENUINE_INTEL;
595
596 // "Auth enti cAMD"
597 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
598 return VendorSignatures::AUTHENTIC_AMD;
599
600 return VendorSignatures::UNKNOWN;
601}
602
603} // namespace x86
604} // namespace detail
605} // namespace sys
606} // namespace llvm
607
608using namespace llvm::sys::detail::x86;
609
610/// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
611/// the 4 values in the specified arguments. If we can't run cpuid on the host,
612/// return true.
613static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
614 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
615 unsigned *rEDX) {
616#if defined(__GNUC__) || defined(__clang__)
617#if defined(__x86_64__)
618 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
619 // FIXME: should we save this for Clang?
620 __asm__("movq\t%%rbx, %%rsi\n\t"
621 "cpuid\n\t"
622 "xchgq\t%%rbx, %%rsi\n\t"
623 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
624 : "a"(value), "c"(subleaf));
625 return false;
626#elif defined(__i386__)
627 __asm__("movl\t%%ebx, %%esi\n\t"
628 "cpuid\n\t"
629 "xchgl\t%%ebx, %%esi\n\t"
630 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
631 : "a"(value), "c"(subleaf));
632 return false;
633#else
634 return true;
635#endif
636#elif defined(_MSC_VER)
637 int registers[4];
638 __cpuidex(registers, value, subleaf);
639 *rEAX = registers[0];
640 *rEBX = registers[1];
641 *rECX = registers[2];
642 *rEDX = registers[3];
643 return false;
644#else
645 return true;
646#endif
647}
648
649// Read control register 0 (XCR0). Used to detect features such as AVX.
650static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
651#if defined(__GNUC__) || defined(__clang__)
652 // Check xgetbv; this uses a .byte sequence instead of the instruction
653 // directly because older assemblers do not include support for xgetbv and
654 // there is no easy way to conditionally compile based on the assembler used.
655 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
656 return false;
657#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
658 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
659 *rEAX = Result;
660 *rEDX = Result >> 32;
661 return false;
662#else
663 return true;
664#endif
665}
666
667static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
668 unsigned *Model) {
669 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
670 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
671 if (*Family == 6 || *Family == 0xf) {
672 if (*Family == 0xf)
673 // Examine extended family ID if family ID is F.
674 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
675 // Examine extended model ID if family ID is 6 or F.
676 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
677 }
678}
679
680static StringRef
681getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
682 const unsigned *Features,
683 unsigned *Type, unsigned *Subtype) {
684 auto testFeature = [&](unsigned F) {
685 return (Features[F / 32] & (1U << (F % 32))) != 0;
686 };
687
688 StringRef CPU;
689
690 switch (Family) {
691 case 3:
692 CPU = "i386";
693 break;
694 case 4:
695 CPU = "i486";
696 break;
697 case 5:
698 if (testFeature(X86::FEATURE_MMX)) {
699 CPU = "pentium-mmx";
700 break;
701 }
702 CPU = "pentium";
703 break;
704 case 6:
705 switch (Model) {
706 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
707 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
708 // mobile processor, Intel Core 2 Extreme processor, Intel
709 // Pentium Dual-Core processor, Intel Xeon processor, model
710 // 0Fh. All processors are manufactured using the 65 nm process.
711 case 0x16: // Intel Celeron processor model 16h. All processors are
712 // manufactured using the 65 nm process
713 CPU = "core2";
714 *Type = X86::INTEL_CORE2;
715 break;
716 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
717 // 17h. All processors are manufactured using the 45 nm process.
718 //
719 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
720 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
721 // the 45 nm process.
722 CPU = "penryn";
723 *Type = X86::INTEL_CORE2;
724 break;
725 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
726 // processors are manufactured using the 45 nm process.
727 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
728 // As found in a Summer 2010 model iMac.
729 case 0x1f:
730 case 0x2e: // Nehalem EX
731 CPU = "nehalem";
732 *Type = X86::INTEL_COREI7;
733 *Subtype = X86::INTEL_COREI7_NEHALEM;
734 break;
735 case 0x25: // Intel Core i7, laptop version.
736 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
737 // processors are manufactured using the 32 nm process.
738 case 0x2f: // Westmere EX
739 CPU = "westmere";
740 *Type = X86::INTEL_COREI7;
741 *Subtype = X86::INTEL_COREI7_WESTMERE;
742 break;
743 case 0x2a: // Intel Core i7 processor. All processors are manufactured
744 // using the 32 nm process.
745 case 0x2d:
746 CPU = "sandybridge";
747 *Type = X86::INTEL_COREI7;
748 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
749 break;
750 case 0x3a:
751 case 0x3e: // Ivy Bridge EP
752 CPU = "ivybridge";
753 *Type = X86::INTEL_COREI7;
754 *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
755 break;
756
757 // Haswell:
758 case 0x3c:
759 case 0x3f:
760 case 0x45:
761 case 0x46:
762 CPU = "haswell";
763 *Type = X86::INTEL_COREI7;
764 *Subtype = X86::INTEL_COREI7_HASWELL;
765 break;
766
767 // Broadwell:
768 case 0x3d:
769 case 0x47:
770 case 0x4f:
771 case 0x56:
772 CPU = "broadwell";
773 *Type = X86::INTEL_COREI7;
774 *Subtype = X86::INTEL_COREI7_BROADWELL;
775 break;
776
777 // Skylake:
778 case 0x4e: // Skylake mobile
779 case 0x5e: // Skylake desktop
780 case 0x8e: // Kaby Lake mobile
781 case 0x9e: // Kaby Lake desktop
782 case 0xa5: // Comet Lake-H/S
783 case 0xa6: // Comet Lake-U
784 CPU = "skylake";
785 *Type = X86::INTEL_COREI7;
786 *Subtype = X86::INTEL_COREI7_SKYLAKE;
787 break;
788
789 // Rocketlake:
790 case 0xa7:
791 CPU = "rocketlake";
792 *Type = X86::INTEL_COREI7;
793 *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
794 break;
795
796 // Skylake Xeon:
797 case 0x55:
798 *Type = X86::INTEL_COREI7;
799 if (testFeature(X86::FEATURE_AVX512BF16)) {
800 CPU = "cooperlake";
801 *Subtype = X86::INTEL_COREI7_COOPERLAKE;
802 } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
803 CPU = "cascadelake";
804 *Subtype = X86::INTEL_COREI7_CASCADELAKE;
805 } else {
806 CPU = "skylake-avx512";
807 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
808 }
809 break;
810
811 // Cannonlake:
812 case 0x66:
813 CPU = "cannonlake";
814 *Type = X86::INTEL_COREI7;
815 *Subtype = X86::INTEL_COREI7_CANNONLAKE;
816 break;
817
818 // Icelake:
819 case 0x7d:
820 case 0x7e:
821 CPU = "icelake-client";
822 *Type = X86::INTEL_COREI7;
823 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
824 break;
825
826 // Tigerlake:
827 case 0x8c:
828 case 0x8d:
829 CPU = "tigerlake";
830 *Type = X86::INTEL_COREI7;
831 *Subtype = X86::INTEL_COREI7_TIGERLAKE;
832 break;
833
834 // Alderlake:
835 case 0x97:
836 case 0x9a:
837 // Gracemont
838 case 0xbe:
839 // Raptorlake:
840 case 0xb7:
841 case 0xba:
842 case 0xbf:
843 // Meteorlake:
844 case 0xaa:
845 case 0xac:
846 CPU = "alderlake";
847 *Type = X86::INTEL_COREI7;
848 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
849 break;
850
851 // Arrowlake:
852 case 0xc5:
853 CPU = "arrowlake";
854 *Type = X86::INTEL_COREI7;
855 *Subtype = X86::INTEL_COREI7_ARROWLAKE;
856 break;
857
858 // Arrowlake S:
859 case 0xc6:
860 // Lunarlake:
861 case 0xbd:
862 CPU = "arrowlake-s";
863 *Type = X86::INTEL_COREI7;
864 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
865 break;
866
867 // Pantherlake:
868 case 0xcc:
869 CPU = "pantherlake";
870 *Type = X86::INTEL_COREI7;
871 *Subtype = X86::INTEL_COREI7_PANTHERLAKE;
872 break;
873
874 // Graniterapids:
875 case 0xad:
876 CPU = "graniterapids";
877 *Type = X86::INTEL_COREI7;
878 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
879 break;
880
881 // Granite Rapids D:
882 case 0xae:
883 CPU = "graniterapids-d";
884 *Type = X86::INTEL_COREI7;
885 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
886 break;
887
888 // Icelake Xeon:
889 case 0x6a:
890 case 0x6c:
891 CPU = "icelake-server";
892 *Type = X86::INTEL_COREI7;
893 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
894 break;
895
896 // Emerald Rapids:
897 case 0xcf:
898 // Sapphire Rapids:
899 case 0x8f:
900 CPU = "sapphirerapids";
901 *Type = X86::INTEL_COREI7;
902 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
903 break;
904
905 case 0x1c: // Most 45 nm Intel Atom processors
906 case 0x26: // 45 nm Atom Lincroft
907 case 0x27: // 32 nm Atom Medfield
908 case 0x35: // 32 nm Atom Midview
909 case 0x36: // 32 nm Atom Midview
910 CPU = "bonnell";
911 *Type = X86::INTEL_BONNELL;
912 break;
913
914 // Atom Silvermont codes from the Intel software optimization guide.
915 case 0x37:
916 case 0x4a:
917 case 0x4d:
918 case 0x5a:
919 case 0x5d:
920 case 0x4c: // really airmont
921 CPU = "silvermont";
922 *Type = X86::INTEL_SILVERMONT;
923 break;
924 // Goldmont:
925 case 0x5c: // Apollo Lake
926 case 0x5f: // Denverton
927 CPU = "goldmont";
928 *Type = X86::INTEL_GOLDMONT;
929 break;
930 case 0x7a:
931 CPU = "goldmont-plus";
932 *Type = X86::INTEL_GOLDMONT_PLUS;
933 break;
934 case 0x86:
935 case 0x8a: // Lakefield
936 case 0x96: // Elkhart Lake
937 case 0x9c: // Jasper Lake
938 CPU = "tremont";
939 *Type = X86::INTEL_TREMONT;
940 break;
941
942 // Sierraforest:
943 case 0xaf:
944 CPU = "sierraforest";
945 *Type = X86::INTEL_SIERRAFOREST;
946 break;
947
948 // Grandridge:
949 case 0xb6:
950 CPU = "grandridge";
951 *Type = X86::INTEL_GRANDRIDGE;
952 break;
953
954 // Clearwaterforest:
955 case 0xdd:
956 CPU = "clearwaterforest";
957 *Type = X86::INTEL_CLEARWATERFOREST;
958 break;
959
960 // Xeon Phi (Knights Landing + Knights Mill):
961 case 0x57:
962 CPU = "knl";
963 *Type = X86::INTEL_KNL;
964 break;
965 case 0x85:
966 CPU = "knm";
967 *Type = X86::INTEL_KNM;
968 break;
969
970 default: // Unknown family 6 CPU, try to guess.
971 // Don't both with Type/Subtype here, they aren't used by the caller.
972 // They're used above to keep the code in sync with compiler-rt.
973 // TODO detect tigerlake host from model
974 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
975 CPU = "tigerlake";
976 } else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
977 CPU = "icelake-client";
978 } else if (testFeature(X86::FEATURE_AVX512VBMI)) {
979 CPU = "cannonlake";
980 } else if (testFeature(X86::FEATURE_AVX512BF16)) {
981 CPU = "cooperlake";
982 } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
983 CPU = "cascadelake";
984 } else if (testFeature(X86::FEATURE_AVX512VL)) {
985 CPU = "skylake-avx512";
986 } else if (testFeature(X86::FEATURE_AVX512ER)) {
987 CPU = "knl";
988 } else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
989 if (testFeature(X86::FEATURE_SHA))
990 CPU = "goldmont";
991 else
992 CPU = "skylake";
993 } else if (testFeature(X86::FEATURE_ADX)) {
994 CPU = "broadwell";
995 } else if (testFeature(X86::FEATURE_AVX2)) {
996 CPU = "haswell";
997 } else if (testFeature(X86::FEATURE_AVX)) {
998 CPU = "sandybridge";
999 } else if (testFeature(X86::FEATURE_SSE4_2)) {
1000 if (testFeature(X86::FEATURE_MOVBE))
1001 CPU = "silvermont";
1002 else
1003 CPU = "nehalem";
1004 } else if (testFeature(X86::FEATURE_SSE4_1)) {
1005 CPU = "penryn";
1006 } else if (testFeature(X86::FEATURE_SSSE3)) {
1007 if (testFeature(X86::FEATURE_MOVBE))
1008 CPU = "bonnell";
1009 else
1010 CPU = "core2";
1011 } else if (testFeature(X86::FEATURE_64BIT)) {
1012 CPU = "core2";
1013 } else if (testFeature(X86::FEATURE_SSE3)) {
1014 CPU = "yonah";
1015 } else if (testFeature(X86::FEATURE_SSE2)) {
1016 CPU = "pentium-m";
1017 } else if (testFeature(X86::FEATURE_SSE)) {
1018 CPU = "pentium3";
1019 } else if (testFeature(X86::FEATURE_MMX)) {
1020 CPU = "pentium2";
1021 } else {
1022 CPU = "pentiumpro";
1023 }
1024 break;
1025 }
1026 break;
1027 case 15: {
1028 if (testFeature(X86::FEATURE_64BIT)) {
1029 CPU = "nocona";
1030 break;
1031 }
1032 if (testFeature(X86::FEATURE_SSE3)) {
1033 CPU = "prescott";
1034 break;
1035 }
1036 CPU = "pentium4";
1037 break;
1038 }
1039 default:
1040 break; // Unknown.
1041 }
1042
1043 return CPU;
1044}
1045
1046static StringRef
1047getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
1048 const unsigned *Features,
1049 unsigned *Type, unsigned *Subtype) {
1050 auto testFeature = [&](unsigned F) {
1051 return (Features[F / 32] & (1U << (F % 32))) != 0;
1052 };
1053
1054 StringRef CPU;
1055
1056 switch (Family) {
1057 case 4:
1058 CPU = "i486";
1059 break;
1060 case 5:
1061 CPU = "pentium";
1062 switch (Model) {
1063 case 6:
1064 case 7:
1065 CPU = "k6";
1066 break;
1067 case 8:
1068 CPU = "k6-2";
1069 break;
1070 case 9:
1071 case 13:
1072 CPU = "k6-3";
1073 break;
1074 case 10:
1075 CPU = "geode";
1076 break;
1077 }
1078 break;
1079 case 6:
1080 if (testFeature(X86::FEATURE_SSE)) {
1081 CPU = "athlon-xp";
1082 break;
1083 }
1084 CPU = "athlon";
1085 break;
1086 case 15:
1087 if (testFeature(X86::FEATURE_SSE3)) {
1088 CPU = "k8-sse3";
1089 break;
1090 }
1091 CPU = "k8";
1092 break;
1093 case 16:
1094 CPU = "amdfam10";
1095 *Type = X86::AMDFAM10H; // "amdfam10"
1096 switch (Model) {
1097 case 2:
1098 *Subtype = X86::AMDFAM10H_BARCELONA;
1099 break;
1100 case 4:
1101 *Subtype = X86::AMDFAM10H_SHANGHAI;
1102 break;
1103 case 8:
1104 *Subtype = X86::AMDFAM10H_ISTANBUL;
1105 break;
1106 }
1107 break;
1108 case 20:
1109 CPU = "btver1";
1110 *Type = X86::AMD_BTVER1;
1111 break;
1112 case 21:
1113 CPU = "bdver1";
1114 *Type = X86::AMDFAM15H;
1115 if (Model >= 0x60 && Model <= 0x7f) {
1116 CPU = "bdver4";
1117 *Subtype = X86::AMDFAM15H_BDVER4;
1118 break; // 60h-7Fh: Excavator
1119 }
1120 if (Model >= 0x30 && Model <= 0x3f) {
1121 CPU = "bdver3";
1122 *Subtype = X86::AMDFAM15H_BDVER3;
1123 break; // 30h-3Fh: Steamroller
1124 }
1125 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
1126 CPU = "bdver2";
1127 *Subtype = X86::AMDFAM15H_BDVER2;
1128 break; // 02h, 10h-1Fh: Piledriver
1129 }
1130 if (Model <= 0x0f) {
1131 *Subtype = X86::AMDFAM15H_BDVER1;
1132 break; // 00h-0Fh: Bulldozer
1133 }
1134 break;
1135 case 22:
1136 CPU = "btver2";
1137 *Type = X86::AMD_BTVER2;
1138 break;
1139 case 23:
1140 CPU = "znver1";
1141 *Type = X86::AMDFAM17H;
1142 if ((Model >= 0x30 && Model <= 0x3f) || (Model == 0x47) ||
1143 (Model >= 0x60 && Model <= 0x67) || (Model >= 0x68 && Model <= 0x6f) ||
1144 (Model >= 0x70 && Model <= 0x7f) || (Model >= 0x84 && Model <= 0x87) ||
1145 (Model >= 0x90 && Model <= 0x97) || (Model >= 0x98 && Model <= 0x9f) ||
1146 (Model >= 0xa0 && Model <= 0xaf)) {
1147 // Family 17h Models 30h-3Fh (Starship) Zen 2
1148 // Family 17h Models 47h (Cardinal) Zen 2
1149 // Family 17h Models 60h-67h (Renoir) Zen 2
1150 // Family 17h Models 68h-6Fh (Lucienne) Zen 2
1151 // Family 17h Models 70h-7Fh (Matisse) Zen 2
1152 // Family 17h Models 84h-87h (ProjectX) Zen 2
1153 // Family 17h Models 90h-97h (VanGogh) Zen 2
1154 // Family 17h Models 98h-9Fh (Mero) Zen 2
1155 // Family 17h Models A0h-AFh (Mendocino) Zen 2
1156 CPU = "znver2";
1157 *Subtype = X86::AMDFAM17H_ZNVER2;
1158 break;
1159 }
1160 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x20 && Model <= 0x2f)) {
1161 // Family 17h Models 10h-1Fh (Raven1) Zen
1162 // Family 17h Models 10h-1Fh (Picasso) Zen+
1163 // Family 17h Models 20h-2Fh (Raven2 x86) Zen
1164 *Subtype = X86::AMDFAM17H_ZNVER1;
1165 break;
1166 }
1167 break;
1168 case 25:
1169 CPU = "znver3";
1170 *Type = X86::AMDFAM19H;
1171 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x2f) ||
1172 (Model >= 0x30 && Model <= 0x3f) || (Model >= 0x40 && Model <= 0x4f) ||
1173 (Model >= 0x50 && Model <= 0x5f)) {
1174 // Family 19h Models 00h-0Fh (Genesis, Chagall) Zen 3
1175 // Family 19h Models 20h-2Fh (Vermeer) Zen 3
1176 // Family 19h Models 30h-3Fh (Badami) Zen 3
1177 // Family 19h Models 40h-4Fh (Rembrandt) Zen 3+
1178 // Family 19h Models 50h-5Fh (Cezanne) Zen 3
1179 *Subtype = X86::AMDFAM19H_ZNVER3;
1180 break;
1181 }
1182 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x60 && Model <= 0x6f) ||
1183 (Model >= 0x70 && Model <= 0x77) || (Model >= 0x78 && Model <= 0x7f) ||
1184 (Model >= 0xa0 && Model <= 0xaf)) {
1185 // Family 19h Models 10h-1Fh (Stones; Storm Peak) Zen 4
1186 // Family 19h Models 60h-6Fh (Raphael) Zen 4
1187 // Family 19h Models 70h-77h (Phoenix, Hawkpoint1) Zen 4
1188 // Family 19h Models 78h-7Fh (Phoenix 2, Hawkpoint2) Zen 4
1189 // Family 19h Models A0h-AFh (Stones-Dense) Zen 4
1190 CPU = "znver4";
1191 *Subtype = X86::AMDFAM19H_ZNVER4;
1192 break; // "znver4"
1193 }
1194 break;
1195 default:
1196 break; // Unknown AMD CPU.
1197 }
1198
1199 return CPU;
1200}
1201
1202static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
1203 unsigned *Features) {
1204 unsigned EAX, EBX;
1205
1206 auto setFeature = [&](unsigned F) {
1207 Features[F / 32] |= 1U << (F % 32);
1208 };
1209
1210 if ((EDX >> 15) & 1)
1211 setFeature(X86::FEATURE_CMOV);
1212 if ((EDX >> 23) & 1)
1213 setFeature(X86::FEATURE_MMX);
1214 if ((EDX >> 25) & 1)
1215 setFeature(X86::FEATURE_SSE);
1216 if ((EDX >> 26) & 1)
1217 setFeature(X86::FEATURE_SSE2);
1218
1219 if ((ECX >> 0) & 1)
1220 setFeature(X86::FEATURE_SSE3);
1221 if ((ECX >> 1) & 1)
1222 setFeature(X86::FEATURE_PCLMUL);
1223 if ((ECX >> 9) & 1)
1224 setFeature(X86::FEATURE_SSSE3);
1225 if ((ECX >> 12) & 1)
1226 setFeature(X86::FEATURE_FMA);
1227 if ((ECX >> 19) & 1)
1228 setFeature(X86::FEATURE_SSE4_1);
1229 if ((ECX >> 20) & 1) {
1230 setFeature(X86::FEATURE_SSE4_2);
1231 setFeature(X86::FEATURE_CRC32);
1232 }
1233 if ((ECX >> 23) & 1)
1234 setFeature(X86::FEATURE_POPCNT);
1235 if ((ECX >> 25) & 1)
1236 setFeature(X86::FEATURE_AES);
1237
1238 if ((ECX >> 22) & 1)
1239 setFeature(X86::FEATURE_MOVBE);
1240
1241 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1242 // indicates that the AVX registers will be saved and restored on context
1243 // switch, then we have full AVX support.
1244 const unsigned AVXBits = (1 << 27) | (1 << 28);
1245 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1246 ((EAX & 0x6) == 0x6);
1247#if defined(__APPLE__)
1248 // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1249 // save the AVX512 context if we use AVX512 instructions, even the bit is not
1250 // set right now.
1251 bool HasAVX512Save = true;
1252#else
1253 // AVX512 requires additional context to be saved by the OS.
1254 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
1255#endif
1256
1257 if (HasAVX)
1258 setFeature(X86::FEATURE_AVX);
1259
1260 bool HasLeaf7 =
1261 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1262
1263 if (HasLeaf7 && ((EBX >> 3) & 1))
1264 setFeature(X86::FEATURE_BMI);
1265 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1266 setFeature(X86::FEATURE_AVX2);
1267 if (HasLeaf7 && ((EBX >> 8) & 1))
1268 setFeature(X86::FEATURE_BMI2);
1269 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
1270 setFeature(X86::FEATURE_AVX512F);
1271 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1272 setFeature(X86::FEATURE_AVX512DQ);
1273 if (HasLeaf7 && ((EBX >> 19) & 1))
1274 setFeature(X86::FEATURE_ADX);
1275 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1276 setFeature(X86::FEATURE_AVX512IFMA);
1277 if (HasLeaf7 && ((EBX >> 23) & 1))
1278 setFeature(X86::FEATURE_CLFLUSHOPT);
1279 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
1280 setFeature(X86::FEATURE_AVX512PF);
1281 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
1282 setFeature(X86::FEATURE_AVX512ER);
1283 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1284 setFeature(X86::FEATURE_AVX512CD);
1285 if (HasLeaf7 && ((EBX >> 29) & 1))
1286 setFeature(X86::FEATURE_SHA);
1287 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1288 setFeature(X86::FEATURE_AVX512BW);
1289 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1290 setFeature(X86::FEATURE_AVX512VL);
1291
1292 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1293 setFeature(X86::FEATURE_AVX512VBMI);
1294 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1295 setFeature(X86::FEATURE_AVX512VBMI2);
1296 if (HasLeaf7 && ((ECX >> 8) & 1))
1297 setFeature(X86::FEATURE_GFNI);
1298 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1299 setFeature(X86::FEATURE_VPCLMULQDQ);
1300 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1301 setFeature(X86::FEATURE_AVX512VNNI);
1302 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1303 setFeature(X86::FEATURE_AVX512BITALG);
1304 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1305 setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1306
1307 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1308 setFeature(X86::FEATURE_AVX5124VNNIW);
1309 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1310 setFeature(X86::FEATURE_AVX5124FMAPS);
1311 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1312 setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1313
1314 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't
1315 // return all 0s for invalid subleaves so check the limit.
1316 bool HasLeaf7Subleaf1 =
1317 HasLeaf7 && EAX >= 1 &&
1318 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1319 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1320 setFeature(X86::FEATURE_AVX512BF16);
1321
1322 unsigned MaxExtLevel;
1323 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1324
1325 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1326 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1327 if (HasExtLeaf1 && ((ECX >> 6) & 1))
1328 setFeature(X86::FEATURE_SSE4_A);
1329 if (HasExtLeaf1 && ((ECX >> 11) & 1))
1330 setFeature(X86::FEATURE_XOP);
1331 if (HasExtLeaf1 && ((ECX >> 16) & 1))
1332 setFeature(X86::FEATURE_FMA4);
1333
1334 if (HasExtLeaf1 && ((EDX >> 29) & 1))
1335 setFeature(X86::FEATURE_64BIT);
1336}
1337
1339 unsigned MaxLeaf = 0;
1340 const VendorSignatures Vendor = getVendorSignature(&MaxLeaf);
1341 if (Vendor == VendorSignatures::UNKNOWN)
1342 return "generic";
1343
1344 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1345 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1346
1347 unsigned Family = 0, Model = 0;
1348 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0};
1349 detectX86FamilyModel(EAX, &Family, &Model);
1350 getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1351
1352 // These aren't consumed in this file, but we try to keep some source code the
1353 // same or similar to compiler-rt.
1354 unsigned Type = 0;
1355 unsigned Subtype = 0;
1356
1357 StringRef CPU;
1358
1359 if (Vendor == VendorSignatures::GENUINE_INTEL) {
1360 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type,
1361 &Subtype);
1362 } else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
1363 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type,
1364 &Subtype);
1365 }
1366
1367 if (!CPU.empty())
1368 return CPU;
1369
1370 return "generic";
1371}
1372
1373#elif defined(__APPLE__) && defined(__powerpc__)
1375 host_basic_info_data_t hostInfo;
1376 mach_msg_type_number_t infoCount;
1377
1378 infoCount = HOST_BASIC_INFO_COUNT;
1379 mach_port_t hostPort = mach_host_self();
1380 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1381 &infoCount);
1382 mach_port_deallocate(mach_task_self(), hostPort);
1383
1384 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1385 return "generic";
1386
1387 switch (hostInfo.cpu_subtype) {
1389 return "601";
1391 return "602";
1393 return "603";
1395 return "603e";
1397 return "603ev";
1399 return "604";
1401 return "604e";
1403 return "620";
1405 return "750";
1407 return "7400";
1409 return "7450";
1411 return "970";
1412 default:;
1413 }
1414
1415 return "generic";
1416}
1417#elif defined(__linux__) && defined(__powerpc__)
1419 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1420 StringRef Content = P ? P->getBuffer() : "";
1422}
1423#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1425 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1426 StringRef Content = P ? P->getBuffer() : "";
1428}
1429#elif defined(__linux__) && defined(__s390x__)
1431 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1432 StringRef Content = P ? P->getBuffer() : "";
1434}
1435#elif defined(__MVS__)
1437 // Get pointer to Communications Vector Table (CVT).
1438 // The pointer is located at offset 16 of the Prefixed Save Area (PSA).
1439 // It is stored as 31 bit pointer and will be zero-extended to 64 bit.
1440 int *StartToCVTOffset = reinterpret_cast<int *>(0x10);
1441 // Since its stored as a 31-bit pointer, get the 4 bytes from the start
1442 // of address.
1443 int ReadValue = *StartToCVTOffset;
1444 // Explicitly clear the high order bit.
1445 ReadValue = (ReadValue & 0x7FFFFFFF);
1446 char *CVT = reinterpret_cast<char *>(ReadValue);
1447 // The model number is located in the CVT prefix at offset -6 and stored as
1448 // signless packed decimal.
1449 uint16_t Id = *(uint16_t *)&CVT[-6];
1450 // Convert number to integer.
1451 Id = decodePackedBCD<uint16_t>(Id, false);
1452 // Check for vector support. It's stored in field CVTFLAG5 (offset 244),
1453 // bit CVTVEF (X'80'). The facilities list is part of the PSA but the vector
1454 // extension can only be used if bit CVTVEF is on.
1455 bool HaveVectorSupport = CVT[244] & 0x80;
1456 return getCPUNameFromS390Model(Id, HaveVectorSupport);
1457}
1458#elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
1459#define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1460#define CPUFAMILY_ARM_CYCLONE 0x37a09642
1461#define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1462#define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1463#define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1464#define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1465#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1466#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1467#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1468
1470 uint32_t Family;
1471 size_t Length = sizeof(Family);
1472 sysctlbyname("hw.cpufamily", &Family, &Length, NULL, 0);
1473
1474 switch (Family) {
1475 case CPUFAMILY_ARM_SWIFT:
1476 return "swift";
1477 case CPUFAMILY_ARM_CYCLONE:
1478 return "apple-a7";
1479 case CPUFAMILY_ARM_TYPHOON:
1480 return "apple-a8";
1481 case CPUFAMILY_ARM_TWISTER:
1482 return "apple-a9";
1483 case CPUFAMILY_ARM_HURRICANE:
1484 return "apple-a10";
1485 case CPUFAMILY_ARM_MONSOON_MISTRAL:
1486 return "apple-a11";
1487 case CPUFAMILY_ARM_VORTEX_TEMPEST:
1488 return "apple-a12";
1489 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
1490 return "apple-a13";
1491 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
1492 return "apple-m1";
1493 default:
1494 // Default to the newest CPU we know about.
1495 return "apple-m1";
1496 }
1497}
1498#elif defined(_AIX)
1500 switch (_system_configuration.implementation) {
1501 case POWER_4:
1502 if (_system_configuration.version == PV_4_3)
1503 return "970";
1504 return "pwr4";
1505 case POWER_5:
1506 if (_system_configuration.version == PV_5)
1507 return "pwr5";
1508 return "pwr5x";
1509 case POWER_6:
1510 if (_system_configuration.version == PV_6_Compat)
1511 return "pwr6";
1512 return "pwr6x";
1513 case POWER_7:
1514 return "pwr7";
1515 case POWER_8:
1516 return "pwr8";
1517 case POWER_9:
1518 return "pwr9";
1519// TODO: simplify this once the macro is available in all OS levels.
1520#ifdef POWER_10
1521 case POWER_10:
1522#else
1523 case 0x40000:
1524#endif
1525 return "pwr10";
1526 default:
1527 return "generic";
1528 }
1529}
1530#elif defined(__loongarch__)
1532 // Use processor id to detect cpu name.
1533 uint32_t processor_id;
1534 __asm__("cpucfg %[prid], $zero\n\t" : [prid] "=r"(processor_id));
1535 // Refer PRID_SERIES_MASK in linux kernel: arch/loongarch/include/asm/cpu.h.
1536 switch (processor_id & 0xf000) {
1537 case 0xc000: // Loongson 64bit, 4-issue
1538 return "la464";
1539 // TODO: Others.
1540 default:
1541 break;
1542 }
1543 return "generic";
1544}
1545#elif defined(__riscv)
1547#if defined(__linux__)
1548 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1549 StringRef Content = P ? P->getBuffer() : "";
1551#else
1552#if __riscv_xlen == 64
1553 return "generic-rv64";
1554#elif __riscv_xlen == 32
1555 return "generic-rv32";
1556#else
1557#error "Unhandled value of __riscv_xlen"
1558#endif
1559#endif
1560}
1561#elif defined(__sparc__)
1562#if defined(__linux__)
1565 ProcCpuinfoContent.split(Lines, "\n");
1566
1567 // Look for cpu line to determine cpu name
1568 StringRef Cpu;
1569 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
1570 if (Lines[I].starts_with("cpu")) {
1571 Cpu = Lines[I].substr(5).ltrim("\t :");
1572 break;
1573 }
1574 }
1575
1576 return StringSwitch<const char *>(Cpu)
1577 .StartsWith("SuperSparc", "supersparc")
1578 .StartsWith("HyperSparc", "hypersparc")
1579 .StartsWith("SpitFire", "ultrasparc")
1580 .StartsWith("BlackBird", "ultrasparc")
1581 .StartsWith("Sabre", " ultrasparc")
1582 .StartsWith("Hummingbird", "ultrasparc")
1583 .StartsWith("Cheetah", "ultrasparc3")
1584 .StartsWith("Jalapeno", "ultrasparc3")
1585 .StartsWith("Jaguar", "ultrasparc3")
1586 .StartsWith("Panther", "ultrasparc3")
1587 .StartsWith("Serrano", "ultrasparc3")
1588 .StartsWith("UltraSparc T1", "niagara")
1589 .StartsWith("UltraSparc T2", "niagara2")
1590 .StartsWith("UltraSparc T3", "niagara3")
1591 .StartsWith("UltraSparc T4", "niagara4")
1592 .StartsWith("UltraSparc T5", "niagara4")
1593 .StartsWith("LEON", "leon3")
1594 // niagara7/m8 not supported by LLVM yet.
1595 .StartsWith("SPARC-M7", "niagara4" /* "niagara7" */)
1596 .StartsWith("SPARC-S7", "niagara4" /* "niagara7" */)
1597 .StartsWith("SPARC-M8", "niagara4" /* "m8" */)
1598 .Default("generic");
1599}
1600#endif
1601
1603#if defined(__linux__)
1604 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1605 StringRef Content = P ? P->getBuffer() : "";
1607#elif defined(__sun__) && defined(__svr4__)
1608 char *buf = NULL;
1609 kstat_ctl_t *kc;
1610 kstat_t *ksp;
1611 kstat_named_t *brand = NULL;
1612
1613 kc = kstat_open();
1614 if (kc != NULL) {
1615 ksp = kstat_lookup(kc, const_cast<char *>("cpu_info"), -1, NULL);
1616 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1617 ksp->ks_type == KSTAT_TYPE_NAMED)
1618 brand =
1619 (kstat_named_t *)kstat_data_lookup(ksp, const_cast<char *>("brand"));
1620 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1621 buf = KSTAT_NAMED_STR_PTR(brand);
1622 }
1623 kstat_close(kc);
1624
1625 return StringSwitch<const char *>(buf)
1626 .Case("TMS390S10", "supersparc") // Texas Instruments microSPARC I
1627 .Case("TMS390Z50", "supersparc") // Texas Instruments SuperSPARC I
1628 .Case("TMS390Z55",
1629 "supersparc") // Texas Instruments SuperSPARC I with SuperCache
1630 .Case("MB86904", "supersparc") // Fujitsu microSPARC II
1631 .Case("MB86907", "supersparc") // Fujitsu TurboSPARC
1632 .Case("RT623", "hypersparc") // Ross hyperSPARC
1633 .Case("RT625", "hypersparc")
1634 .Case("RT626", "hypersparc")
1635 .Case("UltraSPARC-I", "ultrasparc")
1636 .Case("UltraSPARC-II", "ultrasparc")
1637 .Case("UltraSPARC-IIe", "ultrasparc")
1638 .Case("UltraSPARC-IIi", "ultrasparc")
1639 .Case("SPARC64-III", "ultrasparc")
1640 .Case("SPARC64-IV", "ultrasparc")
1641 .Case("UltraSPARC-III", "ultrasparc3")
1642 .Case("UltraSPARC-III+", "ultrasparc3")
1643 .Case("UltraSPARC-IIIi", "ultrasparc3")
1644 .Case("UltraSPARC-IIIi+", "ultrasparc3")
1645 .Case("UltraSPARC-IV", "ultrasparc3")
1646 .Case("UltraSPARC-IV+", "ultrasparc3")
1647 .Case("SPARC64-V", "ultrasparc3")
1648 .Case("SPARC64-VI", "ultrasparc3")
1649 .Case("SPARC64-VII", "ultrasparc3")
1650 .Case("UltraSPARC-T1", "niagara")
1651 .Case("UltraSPARC-T2", "niagara2")
1652 .Case("UltraSPARC-T2", "niagara2")
1653 .Case("UltraSPARC-T2+", "niagara2")
1654 .Case("SPARC-T3", "niagara3")
1655 .Case("SPARC-T4", "niagara4")
1656 .Case("SPARC-T5", "niagara4")
1657 // niagara7/m8 not supported by LLVM yet.
1658 .Case("SPARC-M7", "niagara4" /* "niagara7" */)
1659 .Case("SPARC-S7", "niagara4" /* "niagara7" */)
1660 .Case("SPARC-M8", "niagara4" /* "m8" */)
1661 .Default("generic");
1662#else
1663 return "generic";
1664#endif
1665}
1666#else
1667StringRef sys::getHostCPUName() { return "generic"; }
1668namespace llvm {
1669namespace sys {
1670namespace detail {
1671namespace x86 {
1672
1675}
1676
1677} // namespace x86
1678} // namespace detail
1679} // namespace sys
1680} // namespace llvm
1681#endif
1682
1683#if defined(__i386__) || defined(_M_IX86) || \
1684 defined(__x86_64__) || defined(_M_X64)
1686 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1687 unsigned MaxLevel;
1688
1689 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
1690 return false;
1691
1692 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1693
1694 Features["cx8"] = (EDX >> 8) & 1;
1695 Features["cmov"] = (EDX >> 15) & 1;
1696 Features["mmx"] = (EDX >> 23) & 1;
1697 Features["fxsr"] = (EDX >> 24) & 1;
1698 Features["sse"] = (EDX >> 25) & 1;
1699 Features["sse2"] = (EDX >> 26) & 1;
1700
1701 Features["sse3"] = (ECX >> 0) & 1;
1702 Features["pclmul"] = (ECX >> 1) & 1;
1703 Features["ssse3"] = (ECX >> 9) & 1;
1704 Features["cx16"] = (ECX >> 13) & 1;
1705 Features["sse4.1"] = (ECX >> 19) & 1;
1706 Features["sse4.2"] = (ECX >> 20) & 1;
1707 Features["crc32"] = Features["sse4.2"];
1708 Features["movbe"] = (ECX >> 22) & 1;
1709 Features["popcnt"] = (ECX >> 23) & 1;
1710 Features["aes"] = (ECX >> 25) & 1;
1711 Features["rdrnd"] = (ECX >> 30) & 1;
1712
1713 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1714 // indicates that the AVX registers will be saved and restored on context
1715 // switch, then we have full AVX support.
1716 bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
1717 bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6);
1718#if defined(__APPLE__)
1719 // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1720 // save the AVX512 context if we use AVX512 instructions, even the bit is not
1721 // set right now.
1722 bool HasAVX512Save = true;
1723#else
1724 // AVX512 requires additional context to be saved by the OS.
1725 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1726#endif
1727 // AMX requires additional context to be saved by the OS.
1728 const unsigned AMXBits = (1 << 17) | (1 << 18);
1729 bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits);
1730
1731 Features["avx"] = HasAVXSave;
1732 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave;
1733 // Only enable XSAVE if OS has enabled support for saving YMM state.
1734 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
1735 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave;
1736
1737 unsigned MaxExtLevel;
1738 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1739
1740 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1741 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1742 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1);
1743 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
1744 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
1745 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
1746 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1747 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);
1748 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1749 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
1750 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1751
1752 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1);
1753
1754 // Miscellaneous memory related features, detected by
1755 // using the 0x80000008 leaf of the CPUID instruction
1756 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1757 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1758 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
1759 Features["rdpru"] = HasExtLeaf8 && ((EBX >> 4) & 1);
1760 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
1761
1762 bool HasLeaf7 =
1763 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1764
1765 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
1766 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
1767 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1768 // AVX2 is only supported if we have the OS save support from AVX.
1769 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave;
1770 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
1771 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
1772 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
1773 // AVX512 is only supported if the OS supports the context save for it.
1774 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1775 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1776 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
1777 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
1778 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1779 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1780 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
1781 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
1782 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
1783 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1784 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
1785 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1786 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1787
1788 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1);
1789 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
1790 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
1791 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1);
1792 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save;
1793 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1);
1794 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1);
1795 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave;
1796 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
1797 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
1798 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
1799 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
1800 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1);
1801 Features["kl"] = HasLeaf7 && ((ECX >> 23) & 1); // key locker
1802 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1);
1803 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);
1804 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
1805 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1);
1806
1807 Features["uintr"] = HasLeaf7 && ((EDX >> 5) & 1);
1808 Features["avx512vp2intersect"] =
1809 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save;
1810 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1);
1811 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1);
1812 // There are two CPUID leafs which information associated with the pconfig
1813 // instruction:
1814 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
1815 // bit of EDX), while the EAX=0x1b leaf returns information on the
1816 // availability of specific pconfig leafs.
1817 // The target feature here only refers to the the first of these two.
1818 // Users might need to check for the availability of specific pconfig
1819 // leaves using cpuid, since that information is ignored while
1820 // detecting features using the "-march=native" flag.
1821 // For more info, see X86 ISA docs.
1822 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
1823 Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;
1824 Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save;
1825 Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
1826 Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
1827 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't
1828 // return all 0s for invalid subleaves so check the limit.
1829 bool HasLeaf7Subleaf1 =
1830 HasLeaf7 && EAX >= 1 &&
1831 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1832 Features["sha512"] = HasLeaf7Subleaf1 && ((EAX >> 0) & 1);
1833 Features["sm3"] = HasLeaf7Subleaf1 && ((EAX >> 1) & 1);
1834 Features["sm4"] = HasLeaf7Subleaf1 && ((EAX >> 2) & 1);
1835 Features["raoint"] = HasLeaf7Subleaf1 && ((EAX >> 3) & 1);
1836 Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;
1837 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
1838 Features["amx-fp16"] = HasLeaf7Subleaf1 && ((EAX >> 21) & 1) && HasAMXSave;
1839 Features["cmpccxadd"] = HasLeaf7Subleaf1 && ((EAX >> 7) & 1);
1840 Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1);
1841 Features["avxifma"] = HasLeaf7Subleaf1 && ((EAX >> 23) & 1) && HasAVXSave;
1842 Features["avxvnniint8"] = HasLeaf7Subleaf1 && ((EDX >> 4) & 1) && HasAVXSave;
1843 Features["avxneconvert"] = HasLeaf7Subleaf1 && ((EDX >> 5) & 1) && HasAVXSave;
1844 Features["amx-complex"] = HasLeaf7Subleaf1 && ((EDX >> 8) & 1) && HasAMXSave;
1845 Features["avxvnniint16"] = HasLeaf7Subleaf1 && ((EDX >> 10) & 1) && HasAVXSave;
1846 Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
1847 Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
1848 Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
1849 bool HasAPXF = HasLeaf7Subleaf1 && ((EDX >> 21) & 1);
1850 Features["egpr"] = HasAPXF;
1851 Features["push2pop2"] = HasAPXF;
1852 Features["ppx"] = HasAPXF;
1853 Features["ndd"] = HasAPXF;
1854 Features["ccmp"] = HasAPXF;
1855 Features["cf"] = HasAPXF;
1856
1857 bool HasLeafD = MaxLevel >= 0xd &&
1858 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1859
1860 // Only enable XSAVE if OS has enabled support for saving YMM state.
1861 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
1862 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
1863 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
1864
1865 bool HasLeaf14 = MaxLevel >= 0x14 &&
1866 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1867
1868 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
1869
1870 bool HasLeaf19 =
1871 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
1872 Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1);
1873
1874 bool HasLeaf24 =
1875 MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX);
1876 Features["avx10.1-512"] =
1877 Features["avx10.1-256"] && HasLeaf24 && ((EBX >> 18) & 1);
1878
1879 return true;
1880}
1881#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1883 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1884 if (!P)
1885 return false;
1886
1888 P->getBuffer().split(Lines, "\n");
1889
1891
1892 // Look for the CPU features.
1893 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1894 if (Lines[I].starts_with("Features")) {
1895 Lines[I].split(CPUFeatures, ' ');
1896 break;
1897 }
1898
1899#if defined(__aarch64__)
1900 // Keep track of which crypto features we have seen
1901 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1902 uint32_t crypto = 0;
1903#endif
1904
1905 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1906 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1907#if defined(__aarch64__)
1908 .Case("asimd", "neon")
1909 .Case("fp", "fp-armv8")
1910 .Case("crc32", "crc")
1911 .Case("atomics", "lse")
1912 .Case("sve", "sve")
1913 .Case("sve2", "sve2")
1914#else
1915 .Case("half", "fp16")
1916 .Case("neon", "neon")
1917 .Case("vfpv3", "vfp3")
1918 .Case("vfpv3d16", "vfp3d16")
1919 .Case("vfpv4", "vfp4")
1920 .Case("idiva", "hwdiv-arm")
1921 .Case("idivt", "hwdiv")
1922#endif
1923 .Default("");
1924
1925#if defined(__aarch64__)
1926 // We need to check crypto separately since we need all of the crypto
1927 // extensions to enable the subtarget feature
1928 if (CPUFeatures[I] == "aes")
1929 crypto |= CAP_AES;
1930 else if (CPUFeatures[I] == "pmull")
1931 crypto |= CAP_PMULL;
1932 else if (CPUFeatures[I] == "sha1")
1933 crypto |= CAP_SHA1;
1934 else if (CPUFeatures[I] == "sha2")
1935 crypto |= CAP_SHA2;
1936#endif
1937
1938 if (LLVMFeatureStr != "")
1939 Features[LLVMFeatureStr] = true;
1940 }
1941
1942#if defined(__aarch64__)
1943 // If we have all crypto bits we can add the feature
1944 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1945 Features["crypto"] = true;
1946#endif
1947
1948 return true;
1949}
1950#elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
1952 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE))
1953 Features["neon"] = true;
1954 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
1955 Features["crc"] = true;
1956 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
1957 Features["crypto"] = true;
1958
1959 return true;
1960}
1961#elif defined(__linux__) && defined(__loongarch__)
1962#include <sys/auxv.h>
1964 unsigned long hwcap = getauxval(AT_HWCAP);
1965 bool HasFPU = hwcap & (1UL << 3); // HWCAP_LOONGARCH_FPU
1966 uint32_t cpucfg2 = 0x2;
1967 __asm__("cpucfg %[cpucfg2], %[cpucfg2]\n\t" : [cpucfg2] "+r"(cpucfg2));
1968
1969 Features["f"] = HasFPU && (cpucfg2 & (1U << 1)); // CPUCFG.2.FP_SP
1970 Features["d"] = HasFPU && (cpucfg2 & (1U << 2)); // CPUCFG.2.FP_DP
1971
1972 Features["lsx"] = hwcap & (1UL << 4); // HWCAP_LOONGARCH_LSX
1973 Features["lasx"] = hwcap & (1UL << 5); // HWCAP_LOONGARCH_LASX
1974 Features["lvz"] = hwcap & (1UL << 9); // HWCAP_LOONGARCH_LVZ
1975
1976 return true;
1977}
1978#else
1979bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
1980#endif
1981
1982#if __APPLE__
1983/// \returns the \p triple, but with the Host's arch spliced in.
1984static Triple withHostArch(Triple T) {
1985#if defined(__arm__)
1986 T.setArch(Triple::arm);
1987 T.setArchName("arm");
1988#elif defined(__arm64e__)
1990 T.setArchName("arm64e");
1991#elif defined(__aarch64__)
1992 T.setArch(Triple::aarch64);
1993 T.setArchName("arm64");
1994#elif defined(__x86_64h__)
1995 T.setArch(Triple::x86_64);
1996 T.setArchName("x86_64h");
1997#elif defined(__x86_64__)
1998 T.setArch(Triple::x86_64);
1999 T.setArchName("x86_64");
2000#elif defined(__i386__)
2001 T.setArch(Triple::x86);
2002 T.setArchName("i386");
2003#elif defined(__powerpc__)
2004 T.setArch(Triple::ppc);
2005 T.setArchName("powerpc");
2006#else
2007# error "Unimplemented host arch fixup"
2008#endif
2009 return T;
2010}
2011#endif
2012
2014 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
2015 Triple PT(Triple::normalize(TargetTripleString));
2016
2017#if __APPLE__
2018 /// In Universal builds, LLVM_HOST_TRIPLE will have the wrong arch in one of
2019 /// the slices. This fixes that up.
2020 PT = withHostArch(PT);
2021#endif
2022
2023 if (sizeof(void *) == 8 && PT.isArch32Bit())
2024 PT = PT.get64BitArchVariant();
2025 if (sizeof(void *) == 4 && PT.isArch64Bit())
2026 PT = PT.get32BitArchVariant();
2027
2028 return PT.str();
2029}
2030
2032#if LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO
2033 std::string CPU = std::string(sys::getHostCPUName());
2034 if (CPU == "generic")
2035 CPU = "(unknown)";
2036 OS << " Default target: " << sys::getDefaultTargetTriple() << '\n'
2037 << " Host CPU: " << CPU << '\n';
2038#endif
2039}
This file defines the StringMap class.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:203
Given that RA is a live value
T Content
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
Definition: Host.cpp:65
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
#define P(N)
raw_pwrite_stream & OS
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
DEMANGLE_NAMESPACE_BEGIN bool starts_with(std::string_view self, char C) noexcept
Represents either an error or a value T.
Definition: ErrorOr.h:56
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
Definition: StringMap.h:128
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
iterator begin() const
Definition: StringRef.h:111
iterator end() const
Definition: StringRef.h:113
bool ends_with(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:271
static constexpr size_t npos
Definition: StringRef.h:52
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
StringSwitch & StartsWith(StringLiteral S, T Value)
Definition: StringSwitch.h:83
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
Definition: Triple.cpp:1550
std::string normalize() const
Return the normalized form of this triple's string.
Definition: Triple.h:354
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
Definition: Triple.cpp:1631
const std::string & str() const
Definition: Triple.h:424
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1538
@ AArch64SubArch_arm64e
Definition: Triple.h:149
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1542
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
@ CPU_SUBTYPE_POWERPC_970
Definition: MachO.h:1663
@ CPU_SUBTYPE_POWERPC_604e
Definition: MachO.h:1658
@ CPU_SUBTYPE_POWERPC_603e
Definition: MachO.h:1655
@ CPU_SUBTYPE_POWERPC_7400
Definition: MachO.h:1661
@ CPU_SUBTYPE_POWERPC_604
Definition: MachO.h:1657
@ CPU_SUBTYPE_POWERPC_750
Definition: MachO.h:1660
@ CPU_SUBTYPE_POWERPC_601
Definition: MachO.h:1652
@ CPU_SUBTYPE_POWERPC_620
Definition: MachO.h:1659
@ CPU_SUBTYPE_POWERPC_603ev
Definition: MachO.h:1656
@ CPU_SUBTYPE_POWERPC_603
Definition: MachO.h:1654
@ CPU_SUBTYPE_POWERPC_7450
Definition: MachO.h:1662
@ CPU_SUBTYPE_POWERPC_602
Definition: MachO.h:1653
Helper functions to extract CPU details from CPUID on x86.
Definition: Host.h:72
VendorSignatures getVendorSignature(unsigned *MaxLeaf=nullptr)
Returns the host CPU's vendor.
Definition: Host.cpp:1673
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
Definition: Host.cpp:367
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
Definition: Host.cpp:76
StringRef getHostCPUNameForBPF()
Definition: Host.cpp:432
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
Definition: Host.cpp:159
StringRef getHostCPUNameForRISCV(StringRef ProcCpuinfoContent)
Definition: Host.cpp:412
StringRef getHostCPUNameForSPARC(StringRef ProcCpuinfoContent)
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
Definition: Host.cpp:1667
void printDefaultTargetAndDetectedCPU(raw_ostream &OS)
This is a function compatible with cl::AddExtraVersionPrinter, which adds info about the current targ...
Definition: Host.cpp:2031
bool getHostCPUFeatures(StringMap< bool, MallocAllocator > &Features)
getHostCPUFeatures - Get the LLVM names for the host CPU features.
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
Definition: Host.cpp:2013
std::string getDefaultTargetTriple()
getDefaultTargetTriple() - Return the default target triple the compiler has been configured to produ...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Length
Definition: DWP.cpp:456
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.