LLVM 19.0.0git
Host.cpp
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1//===-- Host.cpp - Implement OS Host Detection ------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the operating system Host detection.
10//
11//===----------------------------------------------------------------------===//
12
15#include "llvm/ADT/StringMap.h"
16#include "llvm/ADT/StringRef.h"
18#include "llvm/Config/llvm-config.h"
23#include <string.h>
24
25// Include the platform-specific parts of this class.
26#ifdef LLVM_ON_UNIX
27#include "Unix/Host.inc"
28#include <sched.h>
29#endif
30#ifdef _WIN32
31#include "Windows/Host.inc"
32#endif
33#ifdef _MSC_VER
34#include <intrin.h>
35#endif
36#ifdef __MVS__
37#include "llvm/Support/BCD.h"
38#endif
39#if defined(__APPLE__)
40#include <mach/host_info.h>
41#include <mach/mach.h>
42#include <mach/mach_host.h>
43#include <mach/machine.h>
44#include <sys/param.h>
45#include <sys/sysctl.h>
46#endif
47#ifdef _AIX
48#include <sys/systemcfg.h>
49#endif
50#if defined(__sun__) && defined(__svr4__)
51#include <kstat.h>
52#endif
53
54#define DEBUG_TYPE "host-detection"
55
56//===----------------------------------------------------------------------===//
57//
58// Implementations of the CPU detection routines
59//
60//===----------------------------------------------------------------------===//
61
62using namespace llvm;
63
64static std::unique_ptr<llvm::MemoryBuffer>
68 if (std::error_code EC = Text.getError()) {
69 llvm::errs() << "Can't read "
70 << "/proc/cpuinfo: " << EC.message() << "\n";
71 return nullptr;
72 }
73 return std::move(*Text);
74}
75
77 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
78 // and so we must use an operating-system interface to determine the current
79 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
80 const char *generic = "generic";
81
82 // The cpu line is second (after the 'processor: 0' line), so if this
83 // buffer is too small then something has changed (or is wrong).
84 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
85 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
86
87 StringRef::const_iterator CIP = CPUInfoStart;
88
89 StringRef::const_iterator CPUStart = nullptr;
90 size_t CPULen = 0;
91
92 // We need to find the first line which starts with cpu, spaces, and a colon.
93 // After the colon, there may be some additional spaces and then the cpu type.
94 while (CIP < CPUInfoEnd && CPUStart == nullptr) {
95 if (CIP < CPUInfoEnd && *CIP == '\n')
96 ++CIP;
97
98 if (CIP < CPUInfoEnd && *CIP == 'c') {
99 ++CIP;
100 if (CIP < CPUInfoEnd && *CIP == 'p') {
101 ++CIP;
102 if (CIP < CPUInfoEnd && *CIP == 'u') {
103 ++CIP;
104 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
105 ++CIP;
106
107 if (CIP < CPUInfoEnd && *CIP == ':') {
108 ++CIP;
109 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
110 ++CIP;
111
112 if (CIP < CPUInfoEnd) {
113 CPUStart = CIP;
114 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
115 *CIP != ',' && *CIP != '\n'))
116 ++CIP;
117 CPULen = CIP - CPUStart;
118 }
119 }
120 }
121 }
122 }
123
124 if (CPUStart == nullptr)
125 while (CIP < CPUInfoEnd && *CIP != '\n')
126 ++CIP;
127 }
128
129 if (CPUStart == nullptr)
130 return generic;
131
132 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
133 .Case("604e", "604e")
134 .Case("604", "604")
135 .Case("7400", "7400")
136 .Case("7410", "7400")
137 .Case("7447", "7400")
138 .Case("7455", "7450")
139 .Case("G4", "g4")
140 .Case("POWER4", "970")
141 .Case("PPC970FX", "970")
142 .Case("PPC970MP", "970")
143 .Case("G5", "g5")
144 .Case("POWER5", "g5")
145 .Case("A2", "a2")
146 .Case("POWER6", "pwr6")
147 .Case("POWER7", "pwr7")
148 .Case("POWER8", "pwr8")
149 .Case("POWER8E", "pwr8")
150 .Case("POWER8NVL", "pwr8")
151 .Case("POWER9", "pwr9")
152 .Case("POWER10", "pwr10")
153 // FIXME: If we get a simulator or machine with the capabilities of
154 // mcpu=future, we should revisit this and add the name reported by the
155 // simulator/machine.
156 .Default(generic);
157}
158
160 // The cpuid register on arm is not accessible from user space. On Linux,
161 // it is exposed through the /proc/cpuinfo file.
162
163 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
164 // in all cases.
166 ProcCpuinfoContent.split(Lines, "\n");
167
168 // Look for the CPU implementer line.
169 StringRef Implementer;
170 StringRef Hardware;
171 StringRef Part;
172 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
173 if (Lines[I].starts_with("CPU implementer"))
174 Implementer = Lines[I].substr(15).ltrim("\t :");
175 if (Lines[I].starts_with("Hardware"))
176 Hardware = Lines[I].substr(8).ltrim("\t :");
177 if (Lines[I].starts_with("CPU part"))
178 Part = Lines[I].substr(8).ltrim("\t :");
179 }
180
181 if (Implementer == "0x41") { // ARM Ltd.
182 // MSM8992/8994 may give cpu part for the core that the kernel is running on,
183 // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
184 if (Hardware.ends_with("MSM8994") || Hardware.ends_with("MSM8996"))
185 return "cortex-a53";
186
187
188 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
189 // values correspond to the "Part number" in the CP15/c0 register. The
190 // contents are specified in the various processor manuals.
191 // This corresponds to the Main ID Register in Technical Reference Manuals.
192 // and is used in programs like sys-utils
193 return StringSwitch<const char *>(Part)
194 .Case("0x926", "arm926ej-s")
195 .Case("0xb02", "mpcore")
196 .Case("0xb36", "arm1136j-s")
197 .Case("0xb56", "arm1156t2-s")
198 .Case("0xb76", "arm1176jz-s")
199 .Case("0xc05", "cortex-a5")
200 .Case("0xc07", "cortex-a7")
201 .Case("0xc08", "cortex-a8")
202 .Case("0xc09", "cortex-a9")
203 .Case("0xc0f", "cortex-a15")
204 .Case("0xc0e", "cortex-a17")
205 .Case("0xc20", "cortex-m0")
206 .Case("0xc23", "cortex-m3")
207 .Case("0xc24", "cortex-m4")
208 .Case("0xc27", "cortex-m7")
209 .Case("0xd20", "cortex-m23")
210 .Case("0xd21", "cortex-m33")
211 .Case("0xd24", "cortex-m52")
212 .Case("0xd22", "cortex-m55")
213 .Case("0xd23", "cortex-m85")
214 .Case("0xc18", "cortex-r8")
215 .Case("0xd13", "cortex-r52")
216 .Case("0xd16", "cortex-r52plus")
217 .Case("0xd15", "cortex-r82")
218 .Case("0xd14", "cortex-r82ae")
219 .Case("0xd02", "cortex-a34")
220 .Case("0xd04", "cortex-a35")
221 .Case("0xd03", "cortex-a53")
222 .Case("0xd05", "cortex-a55")
223 .Case("0xd46", "cortex-a510")
224 .Case("0xd80", "cortex-a520")
225 .Case("0xd88", "cortex-a520ae")
226 .Case("0xd07", "cortex-a57")
227 .Case("0xd06", "cortex-a65")
228 .Case("0xd43", "cortex-a65ae")
229 .Case("0xd08", "cortex-a72")
230 .Case("0xd09", "cortex-a73")
231 .Case("0xd0a", "cortex-a75")
232 .Case("0xd0b", "cortex-a76")
233 .Case("0xd0e", "cortex-a76ae")
234 .Case("0xd0d", "cortex-a77")
235 .Case("0xd41", "cortex-a78")
236 .Case("0xd42", "cortex-a78ae")
237 .Case("0xd4b", "cortex-a78c")
238 .Case("0xd47", "cortex-a710")
239 .Case("0xd4d", "cortex-a715")
240 .Case("0xd81", "cortex-a720")
241 .Case("0xd89", "cortex-a720ae")
242 .Case("0xd87", "cortex-a725")
243 .Case("0xd44", "cortex-x1")
244 .Case("0xd4c", "cortex-x1c")
245 .Case("0xd48", "cortex-x2")
246 .Case("0xd4e", "cortex-x3")
247 .Case("0xd82", "cortex-x4")
248 .Case("0xd85", "cortex-x925")
249 .Case("0xd4a", "neoverse-e1")
250 .Case("0xd0c", "neoverse-n1")
251 .Case("0xd49", "neoverse-n2")
252 .Case("0xd8e", "neoverse-n3")
253 .Case("0xd40", "neoverse-v1")
254 .Case("0xd4f", "neoverse-v2")
255 .Case("0xd84", "neoverse-v3")
256 .Case("0xd83", "neoverse-v3ae")
257 .Default("generic");
258 }
259
260 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium.
261 return StringSwitch<const char *>(Part)
262 .Case("0x516", "thunderx2t99")
263 .Case("0x0516", "thunderx2t99")
264 .Case("0xaf", "thunderx2t99")
265 .Case("0x0af", "thunderx2t99")
266 .Case("0xa1", "thunderxt88")
267 .Case("0x0a1", "thunderxt88")
268 .Default("generic");
269 }
270
271 if (Implementer == "0x46") { // Fujitsu Ltd.
272 return StringSwitch<const char *>(Part)
273 .Case("0x001", "a64fx")
274 .Default("generic");
275 }
276
277 if (Implementer == "0x4e") { // NVIDIA Corporation
278 return StringSwitch<const char *>(Part)
279 .Case("0x004", "carmel")
280 .Default("generic");
281 }
282
283 if (Implementer == "0x48") // HiSilicon Technologies, Inc.
284 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
285 // values correspond to the "Part number" in the CP15/c0 register. The
286 // contents are specified in the various processor manuals.
287 return StringSwitch<const char *>(Part)
288 .Case("0xd01", "tsv110")
289 .Default("generic");
290
291 if (Implementer == "0x51") // Qualcomm Technologies, Inc.
292 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
293 // values correspond to the "Part number" in the CP15/c0 register. The
294 // contents are specified in the various processor manuals.
295 return StringSwitch<const char *>(Part)
296 .Case("0x06f", "krait") // APQ8064
297 .Case("0x201", "kryo")
298 .Case("0x205", "kryo")
299 .Case("0x211", "kryo")
300 .Case("0x800", "cortex-a73") // Kryo 2xx Gold
301 .Case("0x801", "cortex-a73") // Kryo 2xx Silver
302 .Case("0x802", "cortex-a75") // Kryo 3xx Gold
303 .Case("0x803", "cortex-a75") // Kryo 3xx Silver
304 .Case("0x804", "cortex-a76") // Kryo 4xx Gold
305 .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver
306 .Case("0xc00", "falkor")
307 .Case("0xc01", "saphira")
308 .Case("0x001", "oryon-1")
309 .Default("generic");
310 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
311 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
312 // any predictive pattern across variants and parts.
313 unsigned Variant = 0, Part = 0;
314
315 // Look for the CPU variant line, whose value is a 1 digit hexadecimal
316 // number, corresponding to the Variant bits in the CP15/C0 register.
317 for (auto I : Lines)
318 if (I.consume_front("CPU variant"))
319 I.ltrim("\t :").getAsInteger(0, Variant);
320
321 // Look for the CPU part line, whose value is a 3 digit hexadecimal
322 // number, corresponding to the PartNum bits in the CP15/C0 register.
323 for (auto I : Lines)
324 if (I.consume_front("CPU part"))
325 I.ltrim("\t :").getAsInteger(0, Part);
326
327 unsigned Exynos = (Variant << 12) | Part;
328 switch (Exynos) {
329 default:
330 // Default by falling through to Exynos M3.
331 [[fallthrough]];
332 case 0x1002:
333 return "exynos-m3";
334 case 0x1003:
335 return "exynos-m4";
336 }
337 }
338
339 if (Implementer == "0x6d") { // Microsoft Corporation.
340 // The Microsoft Azure Cobalt 100 CPU is handled as a Neoverse N2.
341 return StringSwitch<const char *>(Part)
342 .Case("0xd49", "neoverse-n2")
343 .Default("generic");
344 }
345
346 if (Implementer == "0xc0") { // Ampere Computing
347 return StringSwitch<const char *>(Part)
348 .Case("0xac3", "ampere1")
349 .Case("0xac4", "ampere1a")
350 .Case("0xac5", "ampere1b")
351 .Default("generic");
352 }
353
354 return "generic";
355}
356
357namespace {
358StringRef getCPUNameFromS390Model(unsigned int Id, bool HaveVectorSupport) {
359 switch (Id) {
360 case 2064: // z900 not supported by LLVM
361 case 2066:
362 case 2084: // z990 not supported by LLVM
363 case 2086:
364 case 2094: // z9-109 not supported by LLVM
365 case 2096:
366 return "generic";
367 case 2097:
368 case 2098:
369 return "z10";
370 case 2817:
371 case 2818:
372 return "z196";
373 case 2827:
374 case 2828:
375 return "zEC12";
376 case 2964:
377 case 2965:
378 return HaveVectorSupport? "z13" : "zEC12";
379 case 3906:
380 case 3907:
381 return HaveVectorSupport? "z14" : "zEC12";
382 case 8561:
383 case 8562:
384 return HaveVectorSupport? "z15" : "zEC12";
385 case 3931:
386 case 3932:
387 default:
388 return HaveVectorSupport? "z16" : "zEC12";
389 }
390}
391} // end anonymous namespace
392
394 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
395
396 // The "processor 0:" line comes after a fair amount of other information,
397 // including a cache breakdown, but this should be plenty.
399 ProcCpuinfoContent.split(Lines, "\n");
400
401 // Look for the CPU features.
402 SmallVector<StringRef, 32> CPUFeatures;
403 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
404 if (Lines[I].starts_with("features")) {
405 size_t Pos = Lines[I].find(':');
406 if (Pos != StringRef::npos) {
407 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
408 break;
409 }
410 }
411
412 // We need to check for the presence of vector support independently of
413 // the machine type, since we may only use the vector register set when
414 // supported by the kernel (and hypervisor).
415 bool HaveVectorSupport = false;
416 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
417 if (CPUFeatures[I] == "vx")
418 HaveVectorSupport = true;
419 }
420
421 // Now check the processor machine type.
422 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
423 if (Lines[I].starts_with("processor ")) {
424 size_t Pos = Lines[I].find("machine = ");
425 if (Pos != StringRef::npos) {
426 Pos += sizeof("machine = ") - 1;
427 unsigned int Id;
428 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id))
429 return getCPUNameFromS390Model(Id, HaveVectorSupport);
430 }
431 break;
432 }
433 }
434
435 return "generic";
436}
437
439 // There are 24 lines in /proc/cpuinfo
441 ProcCpuinfoContent.split(Lines, "\n");
442
443 // Look for uarch line to determine cpu name
444 StringRef UArch;
445 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
446 if (Lines[I].starts_with("uarch")) {
447 UArch = Lines[I].substr(5).ltrim("\t :");
448 break;
449 }
450 }
451
452 return StringSwitch<const char *>(UArch)
453 .Case("sifive,u74-mc", "sifive-u74")
454 .Case("sifive,bullet0", "sifive-u74")
455 .Default("generic");
456}
457
459#if !defined(__linux__) || !defined(__x86_64__)
460 return "generic";
461#else
462 uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
463 /* BPF_MOV64_IMM(BPF_REG_0, 0) */
464 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
465 /* BPF_MOV64_IMM(BPF_REG_2, 1) */
466 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
467 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
468 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
469 /* BPF_MOV64_IMM(BPF_REG_0, 1) */
470 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
471 /* BPF_EXIT_INSN() */
472 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
473
474 uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
475 /* BPF_MOV64_IMM(BPF_REG_0, 0) */
476 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
477 /* BPF_MOV64_IMM(BPF_REG_2, 1) */
478 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
479 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
480 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
481 /* BPF_MOV64_IMM(BPF_REG_0, 1) */
482 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
483 /* BPF_EXIT_INSN() */
484 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
485
486 struct bpf_prog_load_attr {
487 uint32_t prog_type;
488 uint32_t insn_cnt;
489 uint64_t insns;
490 uint64_t license;
491 uint32_t log_level;
492 uint32_t log_size;
493 uint64_t log_buf;
494 uint32_t kern_version;
495 uint32_t prog_flags;
496 } attr = {};
497 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
498 attr.insn_cnt = 5;
499 attr.insns = (uint64_t)v3_insns;
500 attr.license = (uint64_t)"DUMMY";
501
502 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr,
503 sizeof(attr));
504 if (fd >= 0) {
505 close(fd);
506 return "v3";
507 }
508
509 /* Clear the whole attr in case its content changed by syscall. */
510 memset(&attr, 0, sizeof(attr));
511 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
512 attr.insn_cnt = 5;
513 attr.insns = (uint64_t)v2_insns;
514 attr.license = (uint64_t)"DUMMY";
515 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
516 if (fd >= 0) {
517 close(fd);
518 return "v2";
519 }
520 return "v1";
521#endif
522}
523
524#if defined(__i386__) || defined(_M_IX86) || \
525 defined(__x86_64__) || defined(_M_X64)
526
527// The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
528// Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
529// support. Consequently, for i386, the presence of CPUID is checked first
530// via the corresponding eflags bit.
531// Removal of cpuid.h header motivated by PR30384
532// Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
533// or test-suite, but are used in external projects e.g. libstdcxx
534static bool isCpuIdSupported() {
535#if defined(__GNUC__) || defined(__clang__)
536#if defined(__i386__)
537 int __cpuid_supported;
538 __asm__(" pushfl\n"
539 " popl %%eax\n"
540 " movl %%eax,%%ecx\n"
541 " xorl $0x00200000,%%eax\n"
542 " pushl %%eax\n"
543 " popfl\n"
544 " pushfl\n"
545 " popl %%eax\n"
546 " movl $0,%0\n"
547 " cmpl %%eax,%%ecx\n"
548 " je 1f\n"
549 " movl $1,%0\n"
550 "1:"
551 : "=r"(__cpuid_supported)
552 :
553 : "eax", "ecx");
554 if (!__cpuid_supported)
555 return false;
556#endif
557 return true;
558#endif
559 return true;
560}
561
562/// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
563/// the specified arguments. If we can't run cpuid on the host, return true.
564static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
565 unsigned *rECX, unsigned *rEDX) {
566#if defined(__GNUC__) || defined(__clang__)
567#if defined(__x86_64__)
568 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
569 // FIXME: should we save this for Clang?
570 __asm__("movq\t%%rbx, %%rsi\n\t"
571 "cpuid\n\t"
572 "xchgq\t%%rbx, %%rsi\n\t"
573 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
574 : "a"(value));
575 return false;
576#elif defined(__i386__)
577 __asm__("movl\t%%ebx, %%esi\n\t"
578 "cpuid\n\t"
579 "xchgl\t%%ebx, %%esi\n\t"
580 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
581 : "a"(value));
582 return false;
583#else
584 return true;
585#endif
586#elif defined(_MSC_VER)
587 // The MSVC intrinsic is portable across x86 and x64.
588 int registers[4];
589 __cpuid(registers, value);
590 *rEAX = registers[0];
591 *rEBX = registers[1];
592 *rECX = registers[2];
593 *rEDX = registers[3];
594 return false;
595#else
596 return true;
597#endif
598}
599
600namespace llvm {
601namespace sys {
602namespace detail {
603namespace x86 {
604
605VendorSignatures getVendorSignature(unsigned *MaxLeaf) {
606 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
607 if (MaxLeaf == nullptr)
608 MaxLeaf = &EAX;
609 else
610 *MaxLeaf = 0;
611
612 if (!isCpuIdSupported())
613 return VendorSignatures::UNKNOWN;
614
615 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)
616 return VendorSignatures::UNKNOWN;
617
618 // "Genu ineI ntel"
619 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)
620 return VendorSignatures::GENUINE_INTEL;
621
622 // "Auth enti cAMD"
623 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
624 return VendorSignatures::AUTHENTIC_AMD;
625
626 return VendorSignatures::UNKNOWN;
627}
628
629} // namespace x86
630} // namespace detail
631} // namespace sys
632} // namespace llvm
633
634using namespace llvm::sys::detail::x86;
635
636/// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
637/// the 4 values in the specified arguments. If we can't run cpuid on the host,
638/// return true.
639static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
640 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
641 unsigned *rEDX) {
642#if defined(__GNUC__) || defined(__clang__)
643#if defined(__x86_64__)
644 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
645 // FIXME: should we save this for Clang?
646 __asm__("movq\t%%rbx, %%rsi\n\t"
647 "cpuid\n\t"
648 "xchgq\t%%rbx, %%rsi\n\t"
649 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
650 : "a"(value), "c"(subleaf));
651 return false;
652#elif defined(__i386__)
653 __asm__("movl\t%%ebx, %%esi\n\t"
654 "cpuid\n\t"
655 "xchgl\t%%ebx, %%esi\n\t"
656 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
657 : "a"(value), "c"(subleaf));
658 return false;
659#else
660 return true;
661#endif
662#elif defined(_MSC_VER)
663 int registers[4];
664 __cpuidex(registers, value, subleaf);
665 *rEAX = registers[0];
666 *rEBX = registers[1];
667 *rECX = registers[2];
668 *rEDX = registers[3];
669 return false;
670#else
671 return true;
672#endif
673}
674
675// Read control register 0 (XCR0). Used to detect features such as AVX.
676static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
677#if defined(__GNUC__) || defined(__clang__)
678 // Check xgetbv; this uses a .byte sequence instead of the instruction
679 // directly because older assemblers do not include support for xgetbv and
680 // there is no easy way to conditionally compile based on the assembler used.
681 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
682 return false;
683#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
684 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
685 *rEAX = Result;
686 *rEDX = Result >> 32;
687 return false;
688#else
689 return true;
690#endif
691}
692
693static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
694 unsigned *Model) {
695 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
696 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
697 if (*Family == 6 || *Family == 0xf) {
698 if (*Family == 0xf)
699 // Examine extended family ID if family ID is F.
700 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
701 // Examine extended model ID if family ID is 6 or F.
702 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
703 }
704}
705
706static StringRef
707getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
708 const unsigned *Features,
709 unsigned *Type, unsigned *Subtype) {
710 auto testFeature = [&](unsigned F) {
711 return (Features[F / 32] & (1U << (F % 32))) != 0;
712 };
713
714 StringRef CPU;
715
716 switch (Family) {
717 case 3:
718 CPU = "i386";
719 break;
720 case 4:
721 CPU = "i486";
722 break;
723 case 5:
724 if (testFeature(X86::FEATURE_MMX)) {
725 CPU = "pentium-mmx";
726 break;
727 }
728 CPU = "pentium";
729 break;
730 case 6:
731 switch (Model) {
732 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
733 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
734 // mobile processor, Intel Core 2 Extreme processor, Intel
735 // Pentium Dual-Core processor, Intel Xeon processor, model
736 // 0Fh. All processors are manufactured using the 65 nm process.
737 case 0x16: // Intel Celeron processor model 16h. All processors are
738 // manufactured using the 65 nm process
739 CPU = "core2";
740 *Type = X86::INTEL_CORE2;
741 break;
742 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
743 // 17h. All processors are manufactured using the 45 nm process.
744 //
745 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
746 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
747 // the 45 nm process.
748 CPU = "penryn";
749 *Type = X86::INTEL_CORE2;
750 break;
751 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
752 // processors are manufactured using the 45 nm process.
753 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
754 // As found in a Summer 2010 model iMac.
755 case 0x1f:
756 case 0x2e: // Nehalem EX
757 CPU = "nehalem";
758 *Type = X86::INTEL_COREI7;
759 *Subtype = X86::INTEL_COREI7_NEHALEM;
760 break;
761 case 0x25: // Intel Core i7, laptop version.
762 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
763 // processors are manufactured using the 32 nm process.
764 case 0x2f: // Westmere EX
765 CPU = "westmere";
766 *Type = X86::INTEL_COREI7;
767 *Subtype = X86::INTEL_COREI7_WESTMERE;
768 break;
769 case 0x2a: // Intel Core i7 processor. All processors are manufactured
770 // using the 32 nm process.
771 case 0x2d:
772 CPU = "sandybridge";
773 *Type = X86::INTEL_COREI7;
774 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
775 break;
776 case 0x3a:
777 case 0x3e: // Ivy Bridge EP
778 CPU = "ivybridge";
779 *Type = X86::INTEL_COREI7;
780 *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
781 break;
782
783 // Haswell:
784 case 0x3c:
785 case 0x3f:
786 case 0x45:
787 case 0x46:
788 CPU = "haswell";
789 *Type = X86::INTEL_COREI7;
790 *Subtype = X86::INTEL_COREI7_HASWELL;
791 break;
792
793 // Broadwell:
794 case 0x3d:
795 case 0x47:
796 case 0x4f:
797 case 0x56:
798 CPU = "broadwell";
799 *Type = X86::INTEL_COREI7;
800 *Subtype = X86::INTEL_COREI7_BROADWELL;
801 break;
802
803 // Skylake:
804 case 0x4e: // Skylake mobile
805 case 0x5e: // Skylake desktop
806 case 0x8e: // Kaby Lake mobile
807 case 0x9e: // Kaby Lake desktop
808 case 0xa5: // Comet Lake-H/S
809 case 0xa6: // Comet Lake-U
810 CPU = "skylake";
811 *Type = X86::INTEL_COREI7;
812 *Subtype = X86::INTEL_COREI7_SKYLAKE;
813 break;
814
815 // Rocketlake:
816 case 0xa7:
817 CPU = "rocketlake";
818 *Type = X86::INTEL_COREI7;
819 *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
820 break;
821
822 // Skylake Xeon:
823 case 0x55:
824 *Type = X86::INTEL_COREI7;
825 if (testFeature(X86::FEATURE_AVX512BF16)) {
826 CPU = "cooperlake";
827 *Subtype = X86::INTEL_COREI7_COOPERLAKE;
828 } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
829 CPU = "cascadelake";
830 *Subtype = X86::INTEL_COREI7_CASCADELAKE;
831 } else {
832 CPU = "skylake-avx512";
833 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
834 }
835 break;
836
837 // Cannonlake:
838 case 0x66:
839 CPU = "cannonlake";
840 *Type = X86::INTEL_COREI7;
841 *Subtype = X86::INTEL_COREI7_CANNONLAKE;
842 break;
843
844 // Icelake:
845 case 0x7d:
846 case 0x7e:
847 CPU = "icelake-client";
848 *Type = X86::INTEL_COREI7;
849 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
850 break;
851
852 // Tigerlake:
853 case 0x8c:
854 case 0x8d:
855 CPU = "tigerlake";
856 *Type = X86::INTEL_COREI7;
857 *Subtype = X86::INTEL_COREI7_TIGERLAKE;
858 break;
859
860 // Alderlake:
861 case 0x97:
862 case 0x9a:
863 // Gracemont
864 case 0xbe:
865 // Raptorlake:
866 case 0xb7:
867 case 0xba:
868 case 0xbf:
869 // Meteorlake:
870 case 0xaa:
871 case 0xac:
872 CPU = "alderlake";
873 *Type = X86::INTEL_COREI7;
874 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
875 break;
876
877 // Arrowlake:
878 case 0xc5:
879 CPU = "arrowlake";
880 *Type = X86::INTEL_COREI7;
881 *Subtype = X86::INTEL_COREI7_ARROWLAKE;
882 break;
883
884 // Arrowlake S:
885 case 0xc6:
886 // Lunarlake:
887 case 0xbd:
888 CPU = "arrowlake-s";
889 *Type = X86::INTEL_COREI7;
890 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
891 break;
892
893 // Pantherlake:
894 case 0xcc:
895 CPU = "pantherlake";
896 *Type = X86::INTEL_COREI7;
897 *Subtype = X86::INTEL_COREI7_PANTHERLAKE;
898 break;
899
900 // Graniterapids:
901 case 0xad:
902 CPU = "graniterapids";
903 *Type = X86::INTEL_COREI7;
904 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
905 break;
906
907 // Granite Rapids D:
908 case 0xae:
909 CPU = "graniterapids-d";
910 *Type = X86::INTEL_COREI7;
911 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
912 break;
913
914 // Icelake Xeon:
915 case 0x6a:
916 case 0x6c:
917 CPU = "icelake-server";
918 *Type = X86::INTEL_COREI7;
919 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
920 break;
921
922 // Emerald Rapids:
923 case 0xcf:
924 // Sapphire Rapids:
925 case 0x8f:
926 CPU = "sapphirerapids";
927 *Type = X86::INTEL_COREI7;
928 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
929 break;
930
931 case 0x1c: // Most 45 nm Intel Atom processors
932 case 0x26: // 45 nm Atom Lincroft
933 case 0x27: // 32 nm Atom Medfield
934 case 0x35: // 32 nm Atom Midview
935 case 0x36: // 32 nm Atom Midview
936 CPU = "bonnell";
937 *Type = X86::INTEL_BONNELL;
938 break;
939
940 // Atom Silvermont codes from the Intel software optimization guide.
941 case 0x37:
942 case 0x4a:
943 case 0x4d:
944 case 0x5a:
945 case 0x5d:
946 case 0x4c: // really airmont
947 CPU = "silvermont";
948 *Type = X86::INTEL_SILVERMONT;
949 break;
950 // Goldmont:
951 case 0x5c: // Apollo Lake
952 case 0x5f: // Denverton
953 CPU = "goldmont";
954 *Type = X86::INTEL_GOLDMONT;
955 break;
956 case 0x7a:
957 CPU = "goldmont-plus";
958 *Type = X86::INTEL_GOLDMONT_PLUS;
959 break;
960 case 0x86:
961 case 0x8a: // Lakefield
962 case 0x96: // Elkhart Lake
963 case 0x9c: // Jasper Lake
964 CPU = "tremont";
965 *Type = X86::INTEL_TREMONT;
966 break;
967
968 // Sierraforest:
969 case 0xaf:
970 CPU = "sierraforest";
971 *Type = X86::INTEL_SIERRAFOREST;
972 break;
973
974 // Grandridge:
975 case 0xb6:
976 CPU = "grandridge";
977 *Type = X86::INTEL_GRANDRIDGE;
978 break;
979
980 // Clearwaterforest:
981 case 0xdd:
982 CPU = "clearwaterforest";
983 *Type = X86::INTEL_CLEARWATERFOREST;
984 break;
985
986 // Xeon Phi (Knights Landing + Knights Mill):
987 case 0x57:
988 CPU = "knl";
989 *Type = X86::INTEL_KNL;
990 break;
991 case 0x85:
992 CPU = "knm";
993 *Type = X86::INTEL_KNM;
994 break;
995
996 default: // Unknown family 6 CPU, try to guess.
997 // Don't both with Type/Subtype here, they aren't used by the caller.
998 // They're used above to keep the code in sync with compiler-rt.
999 // TODO detect tigerlake host from model
1000 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
1001 CPU = "tigerlake";
1002 } else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
1003 CPU = "icelake-client";
1004 } else if (testFeature(X86::FEATURE_AVX512VBMI)) {
1005 CPU = "cannonlake";
1006 } else if (testFeature(X86::FEATURE_AVX512BF16)) {
1007 CPU = "cooperlake";
1008 } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
1009 CPU = "cascadelake";
1010 } else if (testFeature(X86::FEATURE_AVX512VL)) {
1011 CPU = "skylake-avx512";
1012 } else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
1013 if (testFeature(X86::FEATURE_SHA))
1014 CPU = "goldmont";
1015 else
1016 CPU = "skylake";
1017 } else if (testFeature(X86::FEATURE_ADX)) {
1018 CPU = "broadwell";
1019 } else if (testFeature(X86::FEATURE_AVX2)) {
1020 CPU = "haswell";
1021 } else if (testFeature(X86::FEATURE_AVX)) {
1022 CPU = "sandybridge";
1023 } else if (testFeature(X86::FEATURE_SSE4_2)) {
1024 if (testFeature(X86::FEATURE_MOVBE))
1025 CPU = "silvermont";
1026 else
1027 CPU = "nehalem";
1028 } else if (testFeature(X86::FEATURE_SSE4_1)) {
1029 CPU = "penryn";
1030 } else if (testFeature(X86::FEATURE_SSSE3)) {
1031 if (testFeature(X86::FEATURE_MOVBE))
1032 CPU = "bonnell";
1033 else
1034 CPU = "core2";
1035 } else if (testFeature(X86::FEATURE_64BIT)) {
1036 CPU = "core2";
1037 } else if (testFeature(X86::FEATURE_SSE3)) {
1038 CPU = "yonah";
1039 } else if (testFeature(X86::FEATURE_SSE2)) {
1040 CPU = "pentium-m";
1041 } else if (testFeature(X86::FEATURE_SSE)) {
1042 CPU = "pentium3";
1043 } else if (testFeature(X86::FEATURE_MMX)) {
1044 CPU = "pentium2";
1045 } else {
1046 CPU = "pentiumpro";
1047 }
1048 break;
1049 }
1050 break;
1051 case 15: {
1052 if (testFeature(X86::FEATURE_64BIT)) {
1053 CPU = "nocona";
1054 break;
1055 }
1056 if (testFeature(X86::FEATURE_SSE3)) {
1057 CPU = "prescott";
1058 break;
1059 }
1060 CPU = "pentium4";
1061 break;
1062 }
1063 default:
1064 break; // Unknown.
1065 }
1066
1067 return CPU;
1068}
1069
1070static StringRef
1071getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
1072 const unsigned *Features,
1073 unsigned *Type, unsigned *Subtype) {
1074 auto testFeature = [&](unsigned F) {
1075 return (Features[F / 32] & (1U << (F % 32))) != 0;
1076 };
1077
1078 StringRef CPU;
1079
1080 switch (Family) {
1081 case 4:
1082 CPU = "i486";
1083 break;
1084 case 5:
1085 CPU = "pentium";
1086 switch (Model) {
1087 case 6:
1088 case 7:
1089 CPU = "k6";
1090 break;
1091 case 8:
1092 CPU = "k6-2";
1093 break;
1094 case 9:
1095 case 13:
1096 CPU = "k6-3";
1097 break;
1098 case 10:
1099 CPU = "geode";
1100 break;
1101 }
1102 break;
1103 case 6:
1104 if (testFeature(X86::FEATURE_SSE)) {
1105 CPU = "athlon-xp";
1106 break;
1107 }
1108 CPU = "athlon";
1109 break;
1110 case 15:
1111 if (testFeature(X86::FEATURE_SSE3)) {
1112 CPU = "k8-sse3";
1113 break;
1114 }
1115 CPU = "k8";
1116 break;
1117 case 16:
1118 CPU = "amdfam10";
1119 *Type = X86::AMDFAM10H; // "amdfam10"
1120 switch (Model) {
1121 case 2:
1122 *Subtype = X86::AMDFAM10H_BARCELONA;
1123 break;
1124 case 4:
1125 *Subtype = X86::AMDFAM10H_SHANGHAI;
1126 break;
1127 case 8:
1128 *Subtype = X86::AMDFAM10H_ISTANBUL;
1129 break;
1130 }
1131 break;
1132 case 20:
1133 CPU = "btver1";
1134 *Type = X86::AMD_BTVER1;
1135 break;
1136 case 21:
1137 CPU = "bdver1";
1138 *Type = X86::AMDFAM15H;
1139 if (Model >= 0x60 && Model <= 0x7f) {
1140 CPU = "bdver4";
1141 *Subtype = X86::AMDFAM15H_BDVER4;
1142 break; // 60h-7Fh: Excavator
1143 }
1144 if (Model >= 0x30 && Model <= 0x3f) {
1145 CPU = "bdver3";
1146 *Subtype = X86::AMDFAM15H_BDVER3;
1147 break; // 30h-3Fh: Steamroller
1148 }
1149 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
1150 CPU = "bdver2";
1151 *Subtype = X86::AMDFAM15H_BDVER2;
1152 break; // 02h, 10h-1Fh: Piledriver
1153 }
1154 if (Model <= 0x0f) {
1155 *Subtype = X86::AMDFAM15H_BDVER1;
1156 break; // 00h-0Fh: Bulldozer
1157 }
1158 break;
1159 case 22:
1160 CPU = "btver2";
1161 *Type = X86::AMD_BTVER2;
1162 break;
1163 case 23:
1164 CPU = "znver1";
1165 *Type = X86::AMDFAM17H;
1166 if ((Model >= 0x30 && Model <= 0x3f) || (Model == 0x47) ||
1167 (Model >= 0x60 && Model <= 0x67) || (Model >= 0x68 && Model <= 0x6f) ||
1168 (Model >= 0x70 && Model <= 0x7f) || (Model >= 0x84 && Model <= 0x87) ||
1169 (Model >= 0x90 && Model <= 0x97) || (Model >= 0x98 && Model <= 0x9f) ||
1170 (Model >= 0xa0 && Model <= 0xaf)) {
1171 // Family 17h Models 30h-3Fh (Starship) Zen 2
1172 // Family 17h Models 47h (Cardinal) Zen 2
1173 // Family 17h Models 60h-67h (Renoir) Zen 2
1174 // Family 17h Models 68h-6Fh (Lucienne) Zen 2
1175 // Family 17h Models 70h-7Fh (Matisse) Zen 2
1176 // Family 17h Models 84h-87h (ProjectX) Zen 2
1177 // Family 17h Models 90h-97h (VanGogh) Zen 2
1178 // Family 17h Models 98h-9Fh (Mero) Zen 2
1179 // Family 17h Models A0h-AFh (Mendocino) Zen 2
1180 CPU = "znver2";
1181 *Subtype = X86::AMDFAM17H_ZNVER2;
1182 break;
1183 }
1184 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x20 && Model <= 0x2f)) {
1185 // Family 17h Models 10h-1Fh (Raven1) Zen
1186 // Family 17h Models 10h-1Fh (Picasso) Zen+
1187 // Family 17h Models 20h-2Fh (Raven2 x86) Zen
1188 *Subtype = X86::AMDFAM17H_ZNVER1;
1189 break;
1190 }
1191 break;
1192 case 25:
1193 CPU = "znver3";
1194 *Type = X86::AMDFAM19H;
1195 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x2f) ||
1196 (Model >= 0x30 && Model <= 0x3f) || (Model >= 0x40 && Model <= 0x4f) ||
1197 (Model >= 0x50 && Model <= 0x5f)) {
1198 // Family 19h Models 00h-0Fh (Genesis, Chagall) Zen 3
1199 // Family 19h Models 20h-2Fh (Vermeer) Zen 3
1200 // Family 19h Models 30h-3Fh (Badami) Zen 3
1201 // Family 19h Models 40h-4Fh (Rembrandt) Zen 3+
1202 // Family 19h Models 50h-5Fh (Cezanne) Zen 3
1203 *Subtype = X86::AMDFAM19H_ZNVER3;
1204 break;
1205 }
1206 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x60 && Model <= 0x6f) ||
1207 (Model >= 0x70 && Model <= 0x77) || (Model >= 0x78 && Model <= 0x7f) ||
1208 (Model >= 0xa0 && Model <= 0xaf)) {
1209 // Family 19h Models 10h-1Fh (Stones; Storm Peak) Zen 4
1210 // Family 19h Models 60h-6Fh (Raphael) Zen 4
1211 // Family 19h Models 70h-77h (Phoenix, Hawkpoint1) Zen 4
1212 // Family 19h Models 78h-7Fh (Phoenix 2, Hawkpoint2) Zen 4
1213 // Family 19h Models A0h-AFh (Stones-Dense) Zen 4
1214 CPU = "znver4";
1215 *Subtype = X86::AMDFAM19H_ZNVER4;
1216 break; // "znver4"
1217 }
1218 break;
1219 default:
1220 break; // Unknown AMD CPU.
1221 }
1222
1223 return CPU;
1224}
1225
1226static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
1227 unsigned *Features) {
1228 unsigned EAX, EBX;
1229
1230 auto setFeature = [&](unsigned F) {
1231 Features[F / 32] |= 1U << (F % 32);
1232 };
1233
1234 if ((EDX >> 15) & 1)
1235 setFeature(X86::FEATURE_CMOV);
1236 if ((EDX >> 23) & 1)
1237 setFeature(X86::FEATURE_MMX);
1238 if ((EDX >> 25) & 1)
1239 setFeature(X86::FEATURE_SSE);
1240 if ((EDX >> 26) & 1)
1241 setFeature(X86::FEATURE_SSE2);
1242
1243 if ((ECX >> 0) & 1)
1244 setFeature(X86::FEATURE_SSE3);
1245 if ((ECX >> 1) & 1)
1246 setFeature(X86::FEATURE_PCLMUL);
1247 if ((ECX >> 9) & 1)
1248 setFeature(X86::FEATURE_SSSE3);
1249 if ((ECX >> 12) & 1)
1250 setFeature(X86::FEATURE_FMA);
1251 if ((ECX >> 19) & 1)
1252 setFeature(X86::FEATURE_SSE4_1);
1253 if ((ECX >> 20) & 1) {
1254 setFeature(X86::FEATURE_SSE4_2);
1255 setFeature(X86::FEATURE_CRC32);
1256 }
1257 if ((ECX >> 23) & 1)
1258 setFeature(X86::FEATURE_POPCNT);
1259 if ((ECX >> 25) & 1)
1260 setFeature(X86::FEATURE_AES);
1261
1262 if ((ECX >> 22) & 1)
1263 setFeature(X86::FEATURE_MOVBE);
1264
1265 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1266 // indicates that the AVX registers will be saved and restored on context
1267 // switch, then we have full AVX support.
1268 const unsigned AVXBits = (1 << 27) | (1 << 28);
1269 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1270 ((EAX & 0x6) == 0x6);
1271#if defined(__APPLE__)
1272 // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1273 // save the AVX512 context if we use AVX512 instructions, even the bit is not
1274 // set right now.
1275 bool HasAVX512Save = true;
1276#else
1277 // AVX512 requires additional context to be saved by the OS.
1278 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
1279#endif
1280
1281 if (HasAVX)
1282 setFeature(X86::FEATURE_AVX);
1283
1284 bool HasLeaf7 =
1285 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1286
1287 if (HasLeaf7 && ((EBX >> 3) & 1))
1288 setFeature(X86::FEATURE_BMI);
1289 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1290 setFeature(X86::FEATURE_AVX2);
1291 if (HasLeaf7 && ((EBX >> 8) & 1))
1292 setFeature(X86::FEATURE_BMI2);
1293 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) {
1294 setFeature(X86::FEATURE_AVX512F);
1295 setFeature(X86::FEATURE_EVEX512);
1296 }
1297 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1298 setFeature(X86::FEATURE_AVX512DQ);
1299 if (HasLeaf7 && ((EBX >> 19) & 1))
1300 setFeature(X86::FEATURE_ADX);
1301 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1302 setFeature(X86::FEATURE_AVX512IFMA);
1303 if (HasLeaf7 && ((EBX >> 23) & 1))
1304 setFeature(X86::FEATURE_CLFLUSHOPT);
1305 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1306 setFeature(X86::FEATURE_AVX512CD);
1307 if (HasLeaf7 && ((EBX >> 29) & 1))
1308 setFeature(X86::FEATURE_SHA);
1309 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1310 setFeature(X86::FEATURE_AVX512BW);
1311 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1312 setFeature(X86::FEATURE_AVX512VL);
1313
1314 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1315 setFeature(X86::FEATURE_AVX512VBMI);
1316 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1317 setFeature(X86::FEATURE_AVX512VBMI2);
1318 if (HasLeaf7 && ((ECX >> 8) & 1))
1319 setFeature(X86::FEATURE_GFNI);
1320 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1321 setFeature(X86::FEATURE_VPCLMULQDQ);
1322 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1323 setFeature(X86::FEATURE_AVX512VNNI);
1324 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1325 setFeature(X86::FEATURE_AVX512BITALG);
1326 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1327 setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1328
1329 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1330 setFeature(X86::FEATURE_AVX5124VNNIW);
1331 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1332 setFeature(X86::FEATURE_AVX5124FMAPS);
1333 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1334 setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1335
1336 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't
1337 // return all 0s for invalid subleaves so check the limit.
1338 bool HasLeaf7Subleaf1 =
1339 HasLeaf7 && EAX >= 1 &&
1340 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1341 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1342 setFeature(X86::FEATURE_AVX512BF16);
1343
1344 unsigned MaxExtLevel;
1345 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1346
1347 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1348 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1349 if (HasExtLeaf1 && ((ECX >> 6) & 1))
1350 setFeature(X86::FEATURE_SSE4_A);
1351 if (HasExtLeaf1 && ((ECX >> 11) & 1))
1352 setFeature(X86::FEATURE_XOP);
1353 if (HasExtLeaf1 && ((ECX >> 16) & 1))
1354 setFeature(X86::FEATURE_FMA4);
1355
1356 if (HasExtLeaf1 && ((EDX >> 29) & 1))
1357 setFeature(X86::FEATURE_64BIT);
1358}
1359
1361 unsigned MaxLeaf = 0;
1362 const VendorSignatures Vendor = getVendorSignature(&MaxLeaf);
1363 if (Vendor == VendorSignatures::UNKNOWN)
1364 return "generic";
1365
1366 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1367 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1368
1369 unsigned Family = 0, Model = 0;
1370 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0};
1371 detectX86FamilyModel(EAX, &Family, &Model);
1372 getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1373
1374 // These aren't consumed in this file, but we try to keep some source code the
1375 // same or similar to compiler-rt.
1376 unsigned Type = 0;
1377 unsigned Subtype = 0;
1378
1379 StringRef CPU;
1380
1381 if (Vendor == VendorSignatures::GENUINE_INTEL) {
1382 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type,
1383 &Subtype);
1384 } else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
1385 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type,
1386 &Subtype);
1387 }
1388
1389 if (!CPU.empty())
1390 return CPU;
1391
1392 return "generic";
1393}
1394
1395#elif defined(__APPLE__) && defined(__powerpc__)
1397 host_basic_info_data_t hostInfo;
1398 mach_msg_type_number_t infoCount;
1399
1400 infoCount = HOST_BASIC_INFO_COUNT;
1401 mach_port_t hostPort = mach_host_self();
1402 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1403 &infoCount);
1404 mach_port_deallocate(mach_task_self(), hostPort);
1405
1406 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1407 return "generic";
1408
1409 switch (hostInfo.cpu_subtype) {
1411 return "601";
1413 return "602";
1415 return "603";
1417 return "603e";
1419 return "603ev";
1421 return "604";
1423 return "604e";
1425 return "620";
1427 return "750";
1429 return "7400";
1431 return "7450";
1433 return "970";
1434 default:;
1435 }
1436
1437 return "generic";
1438}
1439#elif defined(__linux__) && defined(__powerpc__)
1441 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1442 StringRef Content = P ? P->getBuffer() : "";
1443 return detail::getHostCPUNameForPowerPC(Content);
1444}
1445#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1447 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1448 StringRef Content = P ? P->getBuffer() : "";
1449 return detail::getHostCPUNameForARM(Content);
1450}
1451#elif defined(__linux__) && defined(__s390x__)
1453 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1454 StringRef Content = P ? P->getBuffer() : "";
1455 return detail::getHostCPUNameForS390x(Content);
1456}
1457#elif defined(__MVS__)
1459 // Get pointer to Communications Vector Table (CVT).
1460 // The pointer is located at offset 16 of the Prefixed Save Area (PSA).
1461 // It is stored as 31 bit pointer and will be zero-extended to 64 bit.
1462 int *StartToCVTOffset = reinterpret_cast<int *>(0x10);
1463 // Since its stored as a 31-bit pointer, get the 4 bytes from the start
1464 // of address.
1465 int ReadValue = *StartToCVTOffset;
1466 // Explicitly clear the high order bit.
1467 ReadValue = (ReadValue & 0x7FFFFFFF);
1468 char *CVT = reinterpret_cast<char *>(ReadValue);
1469 // The model number is located in the CVT prefix at offset -6 and stored as
1470 // signless packed decimal.
1471 uint16_t Id = *(uint16_t *)&CVT[-6];
1472 // Convert number to integer.
1473 Id = decodePackedBCD<uint16_t>(Id, false);
1474 // Check for vector support. It's stored in field CVTFLAG5 (offset 244),
1475 // bit CVTVEF (X'80'). The facilities list is part of the PSA but the vector
1476 // extension can only be used if bit CVTVEF is on.
1477 bool HaveVectorSupport = CVT[244] & 0x80;
1478 return getCPUNameFromS390Model(Id, HaveVectorSupport);
1479}
1480#elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
1481#define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1482#define CPUFAMILY_ARM_CYCLONE 0x37a09642
1483#define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1484#define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1485#define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1486#define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1487#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1488#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1489#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1490#define CPUFAMILY_ARM_BLIZZARD_AVALANCHE 0xda33d83d
1491#define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765edea
1492
1494 uint32_t Family;
1495 size_t Length = sizeof(Family);
1496 sysctlbyname("hw.cpufamily", &Family, &Length, NULL, 0);
1497
1498 switch (Family) {
1499 case CPUFAMILY_ARM_SWIFT:
1500 return "swift";
1501 case CPUFAMILY_ARM_CYCLONE:
1502 return "apple-a7";
1503 case CPUFAMILY_ARM_TYPHOON:
1504 return "apple-a8";
1505 case CPUFAMILY_ARM_TWISTER:
1506 return "apple-a9";
1507 case CPUFAMILY_ARM_HURRICANE:
1508 return "apple-a10";
1509 case CPUFAMILY_ARM_MONSOON_MISTRAL:
1510 return "apple-a11";
1511 case CPUFAMILY_ARM_VORTEX_TEMPEST:
1512 return "apple-a12";
1513 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
1514 return "apple-a13";
1515 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
1516 return "apple-m1";
1517 case CPUFAMILY_ARM_BLIZZARD_AVALANCHE:
1518 return "apple-m2";
1519 case CPUFAMILY_ARM_EVEREST_SAWTOOTH:
1520 return "apple-m3";
1521 default:
1522 // Default to the newest CPU we know about.
1523 return "apple-m3";
1524 }
1525}
1526#elif defined(_AIX)
1528 switch (_system_configuration.implementation) {
1529 case POWER_4:
1530 if (_system_configuration.version == PV_4_3)
1531 return "970";
1532 return "pwr4";
1533 case POWER_5:
1534 if (_system_configuration.version == PV_5)
1535 return "pwr5";
1536 return "pwr5x";
1537 case POWER_6:
1538 if (_system_configuration.version == PV_6_Compat)
1539 return "pwr6";
1540 return "pwr6x";
1541 case POWER_7:
1542 return "pwr7";
1543 case POWER_8:
1544 return "pwr8";
1545 case POWER_9:
1546 return "pwr9";
1547// TODO: simplify this once the macro is available in all OS levels.
1548#ifdef POWER_10
1549 case POWER_10:
1550#else
1551 case 0x40000:
1552#endif
1553 return "pwr10";
1554 default:
1555 return "generic";
1556 }
1557}
1558#elif defined(__loongarch__)
1560 // Use processor id to detect cpu name.
1561 uint32_t processor_id;
1562 __asm__("cpucfg %[prid], $zero\n\t" : [prid] "=r"(processor_id));
1563 // Refer PRID_SERIES_MASK in linux kernel: arch/loongarch/include/asm/cpu.h.
1564 switch (processor_id & 0xf000) {
1565 case 0xc000: // Loongson 64bit, 4-issue
1566 return "la464";
1567 // TODO: Others.
1568 default:
1569 break;
1570 }
1571 return "generic";
1572}
1573#elif defined(__riscv)
1575#if defined(__linux__)
1576 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1577 StringRef Content = P ? P->getBuffer() : "";
1578 return detail::getHostCPUNameForRISCV(Content);
1579#else
1580#if __riscv_xlen == 64
1581 return "generic-rv64";
1582#elif __riscv_xlen == 32
1583 return "generic-rv32";
1584#else
1585#error "Unhandled value of __riscv_xlen"
1586#endif
1587#endif
1588}
1589#elif defined(__sparc__)
1590#if defined(__linux__)
1593 ProcCpuinfoContent.split(Lines, "\n");
1594
1595 // Look for cpu line to determine cpu name
1596 StringRef Cpu;
1597 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
1598 if (Lines[I].starts_with("cpu")) {
1599 Cpu = Lines[I].substr(5).ltrim("\t :");
1600 break;
1601 }
1602 }
1603
1604 return StringSwitch<const char *>(Cpu)
1605 .StartsWith("SuperSparc", "supersparc")
1606 .StartsWith("HyperSparc", "hypersparc")
1607 .StartsWith("SpitFire", "ultrasparc")
1608 .StartsWith("BlackBird", "ultrasparc")
1609 .StartsWith("Sabre", " ultrasparc")
1610 .StartsWith("Hummingbird", "ultrasparc")
1611 .StartsWith("Cheetah", "ultrasparc3")
1612 .StartsWith("Jalapeno", "ultrasparc3")
1613 .StartsWith("Jaguar", "ultrasparc3")
1614 .StartsWith("Panther", "ultrasparc3")
1615 .StartsWith("Serrano", "ultrasparc3")
1616 .StartsWith("UltraSparc T1", "niagara")
1617 .StartsWith("UltraSparc T2", "niagara2")
1618 .StartsWith("UltraSparc T3", "niagara3")
1619 .StartsWith("UltraSparc T4", "niagara4")
1620 .StartsWith("UltraSparc T5", "niagara4")
1621 .StartsWith("LEON", "leon3")
1622 // niagara7/m8 not supported by LLVM yet.
1623 .StartsWith("SPARC-M7", "niagara4" /* "niagara7" */)
1624 .StartsWith("SPARC-S7", "niagara4" /* "niagara7" */)
1625 .StartsWith("SPARC-M8", "niagara4" /* "m8" */)
1626 .Default("generic");
1627}
1628#endif
1629
1631#if defined(__linux__)
1632 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1633 StringRef Content = P ? P->getBuffer() : "";
1634 return detail::getHostCPUNameForSPARC(Content);
1635#elif defined(__sun__) && defined(__svr4__)
1636 char *buf = NULL;
1637 kstat_ctl_t *kc;
1638 kstat_t *ksp;
1639 kstat_named_t *brand = NULL;
1640
1641 kc = kstat_open();
1642 if (kc != NULL) {
1643 ksp = kstat_lookup(kc, const_cast<char *>("cpu_info"), -1, NULL);
1644 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1645 ksp->ks_type == KSTAT_TYPE_NAMED)
1646 brand =
1647 (kstat_named_t *)kstat_data_lookup(ksp, const_cast<char *>("brand"));
1648 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1649 buf = KSTAT_NAMED_STR_PTR(brand);
1650 }
1651 kstat_close(kc);
1652
1653 return StringSwitch<const char *>(buf)
1654 .Case("TMS390S10", "supersparc") // Texas Instruments microSPARC I
1655 .Case("TMS390Z50", "supersparc") // Texas Instruments SuperSPARC I
1656 .Case("TMS390Z55",
1657 "supersparc") // Texas Instruments SuperSPARC I with SuperCache
1658 .Case("MB86904", "supersparc") // Fujitsu microSPARC II
1659 .Case("MB86907", "supersparc") // Fujitsu TurboSPARC
1660 .Case("RT623", "hypersparc") // Ross hyperSPARC
1661 .Case("RT625", "hypersparc")
1662 .Case("RT626", "hypersparc")
1663 .Case("UltraSPARC-I", "ultrasparc")
1664 .Case("UltraSPARC-II", "ultrasparc")
1665 .Case("UltraSPARC-IIe", "ultrasparc")
1666 .Case("UltraSPARC-IIi", "ultrasparc")
1667 .Case("SPARC64-III", "ultrasparc")
1668 .Case("SPARC64-IV", "ultrasparc")
1669 .Case("UltraSPARC-III", "ultrasparc3")
1670 .Case("UltraSPARC-III+", "ultrasparc3")
1671 .Case("UltraSPARC-IIIi", "ultrasparc3")
1672 .Case("UltraSPARC-IIIi+", "ultrasparc3")
1673 .Case("UltraSPARC-IV", "ultrasparc3")
1674 .Case("UltraSPARC-IV+", "ultrasparc3")
1675 .Case("SPARC64-V", "ultrasparc3")
1676 .Case("SPARC64-VI", "ultrasparc3")
1677 .Case("SPARC64-VII", "ultrasparc3")
1678 .Case("UltraSPARC-T1", "niagara")
1679 .Case("UltraSPARC-T2", "niagara2")
1680 .Case("UltraSPARC-T2", "niagara2")
1681 .Case("UltraSPARC-T2+", "niagara2")
1682 .Case("SPARC-T3", "niagara3")
1683 .Case("SPARC-T4", "niagara4")
1684 .Case("SPARC-T5", "niagara4")
1685 // niagara7/m8 not supported by LLVM yet.
1686 .Case("SPARC-M7", "niagara4" /* "niagara7" */)
1687 .Case("SPARC-S7", "niagara4" /* "niagara7" */)
1688 .Case("SPARC-M8", "niagara4" /* "m8" */)
1689 .Default("generic");
1690#else
1691 return "generic";
1692#endif
1693}
1694#else
1695StringRef sys::getHostCPUName() { return "generic"; }
1696namespace llvm {
1697namespace sys {
1698namespace detail {
1699namespace x86 {
1700
1703}
1704
1705} // namespace x86
1706} // namespace detail
1707} // namespace sys
1708} // namespace llvm
1709#endif
1710
1711#if defined(__i386__) || defined(_M_IX86) || \
1712 defined(__x86_64__) || defined(_M_X64)
1714 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1715 unsigned MaxLevel;
1716
1717 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
1718 return false;
1719
1720 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1721
1722 Features["cx8"] = (EDX >> 8) & 1;
1723 Features["cmov"] = (EDX >> 15) & 1;
1724 Features["mmx"] = (EDX >> 23) & 1;
1725 Features["fxsr"] = (EDX >> 24) & 1;
1726 Features["sse"] = (EDX >> 25) & 1;
1727 Features["sse2"] = (EDX >> 26) & 1;
1728
1729 Features["sse3"] = (ECX >> 0) & 1;
1730 Features["pclmul"] = (ECX >> 1) & 1;
1731 Features["ssse3"] = (ECX >> 9) & 1;
1732 Features["cx16"] = (ECX >> 13) & 1;
1733 Features["sse4.1"] = (ECX >> 19) & 1;
1734 Features["sse4.2"] = (ECX >> 20) & 1;
1735 Features["crc32"] = Features["sse4.2"];
1736 Features["movbe"] = (ECX >> 22) & 1;
1737 Features["popcnt"] = (ECX >> 23) & 1;
1738 Features["aes"] = (ECX >> 25) & 1;
1739 Features["rdrnd"] = (ECX >> 30) & 1;
1740
1741 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1742 // indicates that the AVX registers will be saved and restored on context
1743 // switch, then we have full AVX support.
1744 bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
1745 bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6);
1746#if defined(__APPLE__)
1747 // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1748 // save the AVX512 context if we use AVX512 instructions, even the bit is not
1749 // set right now.
1750 bool HasAVX512Save = true;
1751#else
1752 // AVX512 requires additional context to be saved by the OS.
1753 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1754#endif
1755 // AMX requires additional context to be saved by the OS.
1756 const unsigned AMXBits = (1 << 17) | (1 << 18);
1757 bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits);
1758
1759 Features["avx"] = HasAVXSave;
1760 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave;
1761 // Only enable XSAVE if OS has enabled support for saving YMM state.
1762 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
1763 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave;
1764
1765 unsigned MaxExtLevel;
1766 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1767
1768 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1769 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1770 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1);
1771 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
1772 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
1773 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
1774 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1775 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);
1776 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1777 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
1778 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1779
1780 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1);
1781
1782 // Miscellaneous memory related features, detected by
1783 // using the 0x80000008 leaf of the CPUID instruction
1784 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1785 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1786 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
1787 Features["rdpru"] = HasExtLeaf8 && ((EBX >> 4) & 1);
1788 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
1789
1790 bool HasLeaf7 =
1791 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1792
1793 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
1794 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
1795 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1796 // AVX2 is only supported if we have the OS save support from AVX.
1797 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave;
1798 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
1799 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
1800 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
1801 // AVX512 is only supported if the OS supports the context save for it.
1802 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1803 if (Features["avx512f"])
1804 Features["evex512"] = true;
1805 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1806 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
1807 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
1808 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1809 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1810 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
1811 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1812 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
1813 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1814 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1815
1816 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
1817 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
1818 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1);
1819 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save;
1820 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1);
1821 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1);
1822 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave;
1823 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
1824 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
1825 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
1826 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
1827 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1);
1828 Features["kl"] = HasLeaf7 && ((ECX >> 23) & 1); // key locker
1829 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1);
1830 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);
1831 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
1832 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1);
1833
1834 Features["uintr"] = HasLeaf7 && ((EDX >> 5) & 1);
1835 Features["avx512vp2intersect"] =
1836 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save;
1837 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1);
1838 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1);
1839 // There are two CPUID leafs which information associated with the pconfig
1840 // instruction:
1841 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
1842 // bit of EDX), while the EAX=0x1b leaf returns information on the
1843 // availability of specific pconfig leafs.
1844 // The target feature here only refers to the the first of these two.
1845 // Users might need to check for the availability of specific pconfig
1846 // leaves using cpuid, since that information is ignored while
1847 // detecting features using the "-march=native" flag.
1848 // For more info, see X86 ISA docs.
1849 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
1850 Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;
1851 Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save;
1852 Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
1853 Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
1854 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't
1855 // return all 0s for invalid subleaves so check the limit.
1856 bool HasLeaf7Subleaf1 =
1857 HasLeaf7 && EAX >= 1 &&
1858 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1859 Features["sha512"] = HasLeaf7Subleaf1 && ((EAX >> 0) & 1);
1860 Features["sm3"] = HasLeaf7Subleaf1 && ((EAX >> 1) & 1);
1861 Features["sm4"] = HasLeaf7Subleaf1 && ((EAX >> 2) & 1);
1862 Features["raoint"] = HasLeaf7Subleaf1 && ((EAX >> 3) & 1);
1863 Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;
1864 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
1865 Features["amx-fp16"] = HasLeaf7Subleaf1 && ((EAX >> 21) & 1) && HasAMXSave;
1866 Features["cmpccxadd"] = HasLeaf7Subleaf1 && ((EAX >> 7) & 1);
1867 Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1);
1868 Features["avxifma"] = HasLeaf7Subleaf1 && ((EAX >> 23) & 1) && HasAVXSave;
1869 Features["avxvnniint8"] = HasLeaf7Subleaf1 && ((EDX >> 4) & 1) && HasAVXSave;
1870 Features["avxneconvert"] = HasLeaf7Subleaf1 && ((EDX >> 5) & 1) && HasAVXSave;
1871 Features["amx-complex"] = HasLeaf7Subleaf1 && ((EDX >> 8) & 1) && HasAMXSave;
1872 Features["avxvnniint16"] = HasLeaf7Subleaf1 && ((EDX >> 10) & 1) && HasAVXSave;
1873 Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
1874 Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
1875 Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
1876 bool HasAPXF = HasLeaf7Subleaf1 && ((EDX >> 21) & 1);
1877 Features["egpr"] = HasAPXF;
1878 Features["push2pop2"] = HasAPXF;
1879 Features["ppx"] = HasAPXF;
1880 Features["ndd"] = HasAPXF;
1881 Features["ccmp"] = HasAPXF;
1882 Features["cf"] = HasAPXF;
1883
1884 bool HasLeafD = MaxLevel >= 0xd &&
1885 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1886
1887 // Only enable XSAVE if OS has enabled support for saving YMM state.
1888 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
1889 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
1890 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
1891
1892 bool HasLeaf14 = MaxLevel >= 0x14 &&
1893 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1894
1895 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
1896
1897 bool HasLeaf19 =
1898 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
1899 Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1);
1900
1901 bool HasLeaf24 =
1902 MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX);
1903 Features["avx10.1-512"] =
1904 Features["avx10.1-256"] && HasLeaf24 && ((EBX >> 18) & 1);
1905
1906 return true;
1907}
1908#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1910 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1911 if (!P)
1912 return false;
1913
1915 P->getBuffer().split(Lines, "\n");
1916
1918
1919 // Look for the CPU features.
1920 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1921 if (Lines[I].starts_with("Features")) {
1922 Lines[I].split(CPUFeatures, ' ');
1923 break;
1924 }
1925
1926#if defined(__aarch64__)
1927 // Keep track of which crypto features we have seen
1928 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1929 uint32_t crypto = 0;
1930#endif
1931
1932 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1933 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1934#if defined(__aarch64__)
1935 .Case("asimd", "neon")
1936 .Case("fp", "fp-armv8")
1937 .Case("crc32", "crc")
1938 .Case("atomics", "lse")
1939 .Case("sve", "sve")
1940 .Case("sve2", "sve2")
1941#else
1942 .Case("half", "fp16")
1943 .Case("neon", "neon")
1944 .Case("vfpv3", "vfp3")
1945 .Case("vfpv3d16", "vfp3d16")
1946 .Case("vfpv4", "vfp4")
1947 .Case("idiva", "hwdiv-arm")
1948 .Case("idivt", "hwdiv")
1949#endif
1950 .Default("");
1951
1952#if defined(__aarch64__)
1953 // We need to check crypto separately since we need all of the crypto
1954 // extensions to enable the subtarget feature
1955 if (CPUFeatures[I] == "aes")
1956 crypto |= CAP_AES;
1957 else if (CPUFeatures[I] == "pmull")
1958 crypto |= CAP_PMULL;
1959 else if (CPUFeatures[I] == "sha1")
1960 crypto |= CAP_SHA1;
1961 else if (CPUFeatures[I] == "sha2")
1962 crypto |= CAP_SHA2;
1963#endif
1964
1965 if (LLVMFeatureStr != "")
1966 Features[LLVMFeatureStr] = true;
1967 }
1968
1969#if defined(__aarch64__)
1970 // If we have all crypto bits we can add the feature
1971 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1972 Features["crypto"] = true;
1973#endif
1974
1975 return true;
1976}
1977#elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
1979 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE))
1980 Features["neon"] = true;
1981 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
1982 Features["crc"] = true;
1983 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
1984 Features["crypto"] = true;
1985
1986 return true;
1987}
1988#elif defined(__linux__) && defined(__loongarch__)
1989#include <sys/auxv.h>
1991 unsigned long hwcap = getauxval(AT_HWCAP);
1992 bool HasFPU = hwcap & (1UL << 3); // HWCAP_LOONGARCH_FPU
1993 uint32_t cpucfg2 = 0x2;
1994 __asm__("cpucfg %[cpucfg2], %[cpucfg2]\n\t" : [cpucfg2] "+r"(cpucfg2));
1995
1996 Features["f"] = HasFPU && (cpucfg2 & (1U << 1)); // CPUCFG.2.FP_SP
1997 Features["d"] = HasFPU && (cpucfg2 & (1U << 2)); // CPUCFG.2.FP_DP
1998
1999 Features["lsx"] = hwcap & (1UL << 4); // HWCAP_LOONGARCH_LSX
2000 Features["lasx"] = hwcap & (1UL << 5); // HWCAP_LOONGARCH_LASX
2001 Features["lvz"] = hwcap & (1UL << 9); // HWCAP_LOONGARCH_LVZ
2002
2003 return true;
2004}
2005#else
2006bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
2007#endif
2008
2009#if __APPLE__
2010/// \returns the \p triple, but with the Host's arch spliced in.
2011static Triple withHostArch(Triple T) {
2012#if defined(__arm__)
2013 T.setArch(Triple::arm);
2014 T.setArchName("arm");
2015#elif defined(__arm64e__)
2017 T.setArchName("arm64e");
2018#elif defined(__aarch64__)
2019 T.setArch(Triple::aarch64);
2020 T.setArchName("arm64");
2021#elif defined(__x86_64h__)
2022 T.setArch(Triple::x86_64);
2023 T.setArchName("x86_64h");
2024#elif defined(__x86_64__)
2025 T.setArch(Triple::x86_64);
2026 T.setArchName("x86_64");
2027#elif defined(__i386__)
2028 T.setArch(Triple::x86);
2029 T.setArchName("i386");
2030#elif defined(__powerpc__)
2031 T.setArch(Triple::ppc);
2032 T.setArchName("powerpc");
2033#else
2034# error "Unimplemented host arch fixup"
2035#endif
2036 return T;
2037}
2038#endif
2039
2041 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
2042 Triple PT(Triple::normalize(TargetTripleString));
2043
2044#if __APPLE__
2045 /// In Universal builds, LLVM_HOST_TRIPLE will have the wrong arch in one of
2046 /// the slices. This fixes that up.
2047 PT = withHostArch(PT);
2048#endif
2049
2050 if (sizeof(void *) == 8 && PT.isArch32Bit())
2051 PT = PT.get64BitArchVariant();
2052 if (sizeof(void *) == 4 && PT.isArch64Bit())
2053 PT = PT.get32BitArchVariant();
2054
2055 return PT.str();
2056}
2057
2059#if LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO
2060 std::string CPU = std::string(sys::getHostCPUName());
2061 if (CPU == "generic")
2062 CPU = "(unknown)";
2063 OS << " Default target: " << sys::getDefaultTargetTriple() << '\n'
2064 << " Host CPU: " << CPU << '\n';
2065#endif
2066}
This file defines the StringMap class.
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:203
Given that RA is a live value
T Content
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
Definition: Host.cpp:65
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
#define P(N)
raw_pwrite_stream & OS
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
DEMANGLE_NAMESPACE_BEGIN bool starts_with(std::string_view self, char C) noexcept
Represents either an error or a value T.
Definition: ErrorOr.h:56
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
Definition: StringMap.h:128
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:693
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
iterator begin() const
Definition: StringRef.h:111
iterator end() const
Definition: StringRef.h:113
bool ends_with(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:270
static constexpr size_t npos
Definition: StringRef.h:52
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
StringSwitch & StartsWith(StringLiteral S, T Value)
Definition: StringSwitch.h:83
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
Definition: Triple.cpp:1673
std::string normalize() const
Return the normalized form of this triple's string.
Definition: Triple.h:366
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
Definition: Triple.cpp:1754
const std::string & str() const
Definition: Triple.h:440
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1661
@ AArch64SubArch_arm64e
Definition: Triple.h:149
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1665
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
@ CPU_SUBTYPE_POWERPC_970
Definition: MachO.h:1663
@ CPU_SUBTYPE_POWERPC_604e
Definition: MachO.h:1658
@ CPU_SUBTYPE_POWERPC_603e
Definition: MachO.h:1655
@ CPU_SUBTYPE_POWERPC_7400
Definition: MachO.h:1661
@ CPU_SUBTYPE_POWERPC_604
Definition: MachO.h:1657
@ CPU_SUBTYPE_POWERPC_750
Definition: MachO.h:1660
@ CPU_SUBTYPE_POWERPC_601
Definition: MachO.h:1652
@ CPU_SUBTYPE_POWERPC_620
Definition: MachO.h:1659
@ CPU_SUBTYPE_POWERPC_603ev
Definition: MachO.h:1656
@ CPU_SUBTYPE_POWERPC_603
Definition: MachO.h:1654
@ CPU_SUBTYPE_POWERPC_7450
Definition: MachO.h:1662
@ CPU_SUBTYPE_POWERPC_602
Definition: MachO.h:1653
Helper functions to extract CPU details from CPUID on x86.
Definition: Host.h:72
VendorSignatures getVendorSignature(unsigned *MaxLeaf=nullptr)
Returns the host CPU's vendor.
Definition: Host.cpp:1701
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
Definition: Host.cpp:393
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
Definition: Host.cpp:76
StringRef getHostCPUNameForBPF()
Definition: Host.cpp:458
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
Definition: Host.cpp:159
StringRef getHostCPUNameForRISCV(StringRef ProcCpuinfoContent)
Definition: Host.cpp:438
StringRef getHostCPUNameForSPARC(StringRef ProcCpuinfoContent)
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
Definition: Host.cpp:1695
void printDefaultTargetAndDetectedCPU(raw_ostream &OS)
This is a function compatible with cl::AddExtraVersionPrinter, which adds info about the current targ...
Definition: Host.cpp:2058
bool getHostCPUFeatures(StringMap< bool, MallocAllocator > &Features)
getHostCPUFeatures - Get the LLVM names for the host CPU features.
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
Definition: Host.cpp:2040
std::string getDefaultTargetTriple()
getDefaultTargetTriple() - Return the default target triple the compiler has been configured to produ...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Length
Definition: DWP.cpp:456
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.