LLVM  16.0.0git
Host.cpp
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1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the operating system Host concept.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/Support/Host.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/StringMap.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Config/llvm-config.h"
23 #include <string.h>
24 
25 // Include the platform-specific parts of this class.
26 #ifdef LLVM_ON_UNIX
27 #include "Unix/Host.inc"
28 #include <sched.h>
29 #endif
30 #ifdef _WIN32
31 #include "Windows/Host.inc"
32 #endif
33 #ifdef _MSC_VER
34 #include <intrin.h>
35 #endif
36 #ifdef __MVS__
37 #include "llvm/Support/BCD.h"
38 #endif
39 #if defined(__APPLE__)
40 #include <mach/host_info.h>
41 #include <mach/mach.h>
42 #include <mach/mach_host.h>
43 #include <mach/machine.h>
44 #include <sys/param.h>
45 #include <sys/sysctl.h>
46 #endif
47 #ifdef _AIX
48 #include <sys/systemcfg.h>
49 #endif
50 #if defined(__sun__) && defined(__svr4__)
51 #include <kstat.h>
52 #endif
53 
54 #define DEBUG_TYPE "host-detection"
55 
56 //===----------------------------------------------------------------------===//
57 //
58 // Implementations of the CPU detection routines
59 //
60 //===----------------------------------------------------------------------===//
61 
62 using namespace llvm;
63 
64 static std::unique_ptr<llvm::MemoryBuffer>
67  llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
68  if (std::error_code EC = Text.getError()) {
69  llvm::errs() << "Can't read "
70  << "/proc/cpuinfo: " << EC.message() << "\n";
71  return nullptr;
72  }
73  return std::move(*Text);
74 }
75 
77  // Access to the Processor Version Register (PVR) on PowerPC is privileged,
78  // and so we must use an operating-system interface to determine the current
79  // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
80  const char *generic = "generic";
81 
82  // The cpu line is second (after the 'processor: 0' line), so if this
83  // buffer is too small then something has changed (or is wrong).
84  StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
85  StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
86 
87  StringRef::const_iterator CIP = CPUInfoStart;
88 
89  StringRef::const_iterator CPUStart = nullptr;
90  size_t CPULen = 0;
91 
92  // We need to find the first line which starts with cpu, spaces, and a colon.
93  // After the colon, there may be some additional spaces and then the cpu type.
94  while (CIP < CPUInfoEnd && CPUStart == nullptr) {
95  if (CIP < CPUInfoEnd && *CIP == '\n')
96  ++CIP;
97 
98  if (CIP < CPUInfoEnd && *CIP == 'c') {
99  ++CIP;
100  if (CIP < CPUInfoEnd && *CIP == 'p') {
101  ++CIP;
102  if (CIP < CPUInfoEnd && *CIP == 'u') {
103  ++CIP;
104  while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
105  ++CIP;
106 
107  if (CIP < CPUInfoEnd && *CIP == ':') {
108  ++CIP;
109  while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
110  ++CIP;
111 
112  if (CIP < CPUInfoEnd) {
113  CPUStart = CIP;
114  while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
115  *CIP != ',' && *CIP != '\n'))
116  ++CIP;
117  CPULen = CIP - CPUStart;
118  }
119  }
120  }
121  }
122  }
123 
124  if (CPUStart == nullptr)
125  while (CIP < CPUInfoEnd && *CIP != '\n')
126  ++CIP;
127  }
128 
129  if (CPUStart == nullptr)
130  return generic;
131 
132  return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
133  .Case("604e", "604e")
134  .Case("604", "604")
135  .Case("7400", "7400")
136  .Case("7410", "7400")
137  .Case("7447", "7400")
138  .Case("7455", "7450")
139  .Case("G4", "g4")
140  .Case("POWER4", "970")
141  .Case("PPC970FX", "970")
142  .Case("PPC970MP", "970")
143  .Case("G5", "g5")
144  .Case("POWER5", "g5")
145  .Case("A2", "a2")
146  .Case("POWER6", "pwr6")
147  .Case("POWER7", "pwr7")
148  .Case("POWER8", "pwr8")
149  .Case("POWER8E", "pwr8")
150  .Case("POWER8NVL", "pwr8")
151  .Case("POWER9", "pwr9")
152  .Case("POWER10", "pwr10")
153  // FIXME: If we get a simulator or machine with the capabilities of
154  // mcpu=future, we should revisit this and add the name reported by the
155  // simulator/machine.
156  .Default(generic);
157 }
158 
160  // The cpuid register on arm is not accessible from user space. On Linux,
161  // it is exposed through the /proc/cpuinfo file.
162 
163  // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
164  // in all cases.
166  ProcCpuinfoContent.split(Lines, "\n");
167 
168  // Look for the CPU implementer line.
169  StringRef Implementer;
170  StringRef Hardware;
171  StringRef Part;
172  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
173  if (Lines[I].startswith("CPU implementer"))
174  Implementer = Lines[I].substr(15).ltrim("\t :");
175  if (Lines[I].startswith("Hardware"))
176  Hardware = Lines[I].substr(8).ltrim("\t :");
177  if (Lines[I].startswith("CPU part"))
178  Part = Lines[I].substr(8).ltrim("\t :");
179  }
180 
181  if (Implementer == "0x41") { // ARM Ltd.
182  // MSM8992/8994 may give cpu part for the core that the kernel is running on,
183  // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
184  if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
185  return "cortex-a53";
186 
187 
188  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
189  // values correspond to the "Part number" in the CP15/c0 register. The
190  // contents are specified in the various processor manuals.
191  // This corresponds to the Main ID Register in Technical Reference Manuals.
192  // and is used in programs like sys-utils
193  return StringSwitch<const char *>(Part)
194  .Case("0x926", "arm926ej-s")
195  .Case("0xb02", "mpcore")
196  .Case("0xb36", "arm1136j-s")
197  .Case("0xb56", "arm1156t2-s")
198  .Case("0xb76", "arm1176jz-s")
199  .Case("0xc08", "cortex-a8")
200  .Case("0xc09", "cortex-a9")
201  .Case("0xc0f", "cortex-a15")
202  .Case("0xc20", "cortex-m0")
203  .Case("0xc23", "cortex-m3")
204  .Case("0xc24", "cortex-m4")
205  .Case("0xd22", "cortex-m55")
206  .Case("0xd02", "cortex-a34")
207  .Case("0xd04", "cortex-a35")
208  .Case("0xd03", "cortex-a53")
209  .Case("0xd05", "cortex-a55")
210  .Case("0xd46", "cortex-a510")
211  .Case("0xd07", "cortex-a57")
212  .Case("0xd08", "cortex-a72")
213  .Case("0xd09", "cortex-a73")
214  .Case("0xd0a", "cortex-a75")
215  .Case("0xd0b", "cortex-a76")
216  .Case("0xd0d", "cortex-a77")
217  .Case("0xd41", "cortex-a78")
218  .Case("0xd47", "cortex-a710")
219  .Case("0xd4d", "cortex-a715")
220  .Case("0xd44", "cortex-x1")
221  .Case("0xd4c", "cortex-x1c")
222  .Case("0xd48", "cortex-x2")
223  .Case("0xd4e", "cortex-x3")
224  .Case("0xd0c", "neoverse-n1")
225  .Case("0xd49", "neoverse-n2")
226  .Case("0xd40", "neoverse-v1")
227  .Case("0xd4f", "neoverse-v2")
228  .Default("generic");
229  }
230 
231  if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium.
232  return StringSwitch<const char *>(Part)
233  .Case("0x516", "thunderx2t99")
234  .Case("0x0516", "thunderx2t99")
235  .Case("0xaf", "thunderx2t99")
236  .Case("0x0af", "thunderx2t99")
237  .Case("0xa1", "thunderxt88")
238  .Case("0x0a1", "thunderxt88")
239  .Default("generic");
240  }
241 
242  if (Implementer == "0x46") { // Fujitsu Ltd.
243  return StringSwitch<const char *>(Part)
244  .Case("0x001", "a64fx")
245  .Default("generic");
246  }
247 
248  if (Implementer == "0x4e") { // NVIDIA Corporation
249  return StringSwitch<const char *>(Part)
250  .Case("0x004", "carmel")
251  .Default("generic");
252  }
253 
254  if (Implementer == "0x48") // HiSilicon Technologies, Inc.
255  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
256  // values correspond to the "Part number" in the CP15/c0 register. The
257  // contents are specified in the various processor manuals.
258  return StringSwitch<const char *>(Part)
259  .Case("0xd01", "tsv110")
260  .Default("generic");
261 
262  if (Implementer == "0x51") // Qualcomm Technologies, Inc.
263  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
264  // values correspond to the "Part number" in the CP15/c0 register. The
265  // contents are specified in the various processor manuals.
266  return StringSwitch<const char *>(Part)
267  .Case("0x06f", "krait") // APQ8064
268  .Case("0x201", "kryo")
269  .Case("0x205", "kryo")
270  .Case("0x211", "kryo")
271  .Case("0x800", "cortex-a73") // Kryo 2xx Gold
272  .Case("0x801", "cortex-a73") // Kryo 2xx Silver
273  .Case("0x802", "cortex-a75") // Kryo 3xx Gold
274  .Case("0x803", "cortex-a75") // Kryo 3xx Silver
275  .Case("0x804", "cortex-a76") // Kryo 4xx Gold
276  .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver
277  .Case("0xc00", "falkor")
278  .Case("0xc01", "saphira")
279  .Default("generic");
280  if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
281  // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
282  // any predictive pattern across variants and parts.
283  unsigned Variant = 0, Part = 0;
284 
285  // Look for the CPU variant line, whose value is a 1 digit hexadecimal
286  // number, corresponding to the Variant bits in the CP15/C0 register.
287  for (auto I : Lines)
288  if (I.consume_front("CPU variant"))
289  I.ltrim("\t :").getAsInteger(0, Variant);
290 
291  // Look for the CPU part line, whose value is a 3 digit hexadecimal
292  // number, corresponding to the PartNum bits in the CP15/C0 register.
293  for (auto I : Lines)
294  if (I.consume_front("CPU part"))
295  I.ltrim("\t :").getAsInteger(0, Part);
296 
297  unsigned Exynos = (Variant << 12) | Part;
298  switch (Exynos) {
299  default:
300  // Default by falling through to Exynos M3.
301  [[fallthrough]];
302  case 0x1002:
303  return "exynos-m3";
304  case 0x1003:
305  return "exynos-m4";
306  }
307  }
308 
309  if (Implementer == "0xc0") { // Ampere Computing
310  return StringSwitch<const char *>(Part)
311  .Case("0xac3", "ampere1")
312  .Default("generic");
313  }
314 
315  return "generic";
316 }
317 
318 namespace {
319 StringRef getCPUNameFromS390Model(unsigned int Id, bool HaveVectorSupport) {
320  switch (Id) {
321  case 2064: // z900 not supported by LLVM
322  case 2066:
323  case 2084: // z990 not supported by LLVM
324  case 2086:
325  case 2094: // z9-109 not supported by LLVM
326  case 2096:
327  return "generic";
328  case 2097:
329  case 2098:
330  return "z10";
331  case 2817:
332  case 2818:
333  return "z196";
334  case 2827:
335  case 2828:
336  return "zEC12";
337  case 2964:
338  case 2965:
339  return HaveVectorSupport? "z13" : "zEC12";
340  case 3906:
341  case 3907:
342  return HaveVectorSupport? "z14" : "zEC12";
343  case 8561:
344  case 8562:
345  return HaveVectorSupport? "z15" : "zEC12";
346  case 3931:
347  case 3932:
348  default:
349  return HaveVectorSupport? "z16" : "zEC12";
350  }
351 }
352 } // end anonymous namespace
353 
355  // STIDP is a privileged operation, so use /proc/cpuinfo instead.
356 
357  // The "processor 0:" line comes after a fair amount of other information,
358  // including a cache breakdown, but this should be plenty.
360  ProcCpuinfoContent.split(Lines, "\n");
361 
362  // Look for the CPU features.
363  SmallVector<StringRef, 32> CPUFeatures;
364  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
365  if (Lines[I].startswith("features")) {
366  size_t Pos = Lines[I].find(':');
367  if (Pos != StringRef::npos) {
368  Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
369  break;
370  }
371  }
372 
373  // We need to check for the presence of vector support independently of
374  // the machine type, since we may only use the vector register set when
375  // supported by the kernel (and hypervisor).
376  bool HaveVectorSupport = false;
377  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
378  if (CPUFeatures[I] == "vx")
379  HaveVectorSupport = true;
380  }
381 
382  // Now check the processor machine type.
383  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
384  if (Lines[I].startswith("processor ")) {
385  size_t Pos = Lines[I].find("machine = ");
386  if (Pos != StringRef::npos) {
387  Pos += sizeof("machine = ") - 1;
388  unsigned int Id;
389  if (!Lines[I].drop_front(Pos).getAsInteger(10, Id))
390  return getCPUNameFromS390Model(Id, HaveVectorSupport);
391  }
392  break;
393  }
394  }
395 
396  return "generic";
397 }
398 
400  // There are 24 lines in /proc/cpuinfo
402  ProcCpuinfoContent.split(Lines, "\n");
403 
404  // Look for uarch line to determine cpu name
405  StringRef UArch;
406  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
407  if (Lines[I].startswith("uarch")) {
408  UArch = Lines[I].substr(5).ltrim("\t :");
409  break;
410  }
411  }
412 
413  return StringSwitch<const char *>(UArch)
414  .Case("sifive,u74-mc", "sifive-u74")
415  .Case("sifive,bullet0", "sifive-u74")
416  .Default("generic");
417 }
418 
420 #if !defined(__linux__) || !defined(__x86_64__)
421  return "generic";
422 #else
423  uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
424  /* BPF_MOV64_IMM(BPF_REG_0, 0) */
425  { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
426  /* BPF_MOV64_IMM(BPF_REG_2, 1) */
427  0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
428  /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
429  0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
430  /* BPF_MOV64_IMM(BPF_REG_0, 1) */
431  0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
432  /* BPF_EXIT_INSN() */
433  0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
434 
435  uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
436  /* BPF_MOV64_IMM(BPF_REG_0, 0) */
437  { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
438  /* BPF_MOV64_IMM(BPF_REG_2, 1) */
439  0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
440  /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
441  0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
442  /* BPF_MOV64_IMM(BPF_REG_0, 1) */
443  0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
444  /* BPF_EXIT_INSN() */
445  0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
446 
447  struct bpf_prog_load_attr {
448  uint32_t prog_type;
449  uint32_t insn_cnt;
450  uint64_t insns;
451  uint64_t license;
452  uint32_t log_level;
453  uint32_t log_size;
454  uint64_t log_buf;
455  uint32_t kern_version;
456  uint32_t prog_flags;
457  } attr = {};
458  attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
459  attr.insn_cnt = 5;
460  attr.insns = (uint64_t)v3_insns;
461  attr.license = (uint64_t)"DUMMY";
462 
463  int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr,
464  sizeof(attr));
465  if (fd >= 0) {
466  close(fd);
467  return "v3";
468  }
469 
470  /* Clear the whole attr in case its content changed by syscall. */
471  memset(&attr, 0, sizeof(attr));
472  attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
473  attr.insn_cnt = 5;
474  attr.insns = (uint64_t)v2_insns;
475  attr.license = (uint64_t)"DUMMY";
476  fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
477  if (fd >= 0) {
478  close(fd);
479  return "v2";
480  }
481  return "v1";
482 #endif
483 }
484 
485 #if defined(__i386__) || defined(_M_IX86) || \
486  defined(__x86_64__) || defined(_M_X64)
487 
488 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
489 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
490 // support. Consequently, for i386, the presence of CPUID is checked first
491 // via the corresponding eflags bit.
492 // Removal of cpuid.h header motivated by PR30384
493 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
494 // or test-suite, but are used in external projects e.g. libstdcxx
495 static bool isCpuIdSupported() {
496 #if defined(__GNUC__) || defined(__clang__)
497 #if defined(__i386__)
498  int __cpuid_supported;
499  __asm__(" pushfl\n"
500  " popl %%eax\n"
501  " movl %%eax,%%ecx\n"
502  " xorl $0x00200000,%%eax\n"
503  " pushl %%eax\n"
504  " popfl\n"
505  " pushfl\n"
506  " popl %%eax\n"
507  " movl $0,%0\n"
508  " cmpl %%eax,%%ecx\n"
509  " je 1f\n"
510  " movl $1,%0\n"
511  "1:"
512  : "=r"(__cpuid_supported)
513  :
514  : "eax", "ecx");
515  if (!__cpuid_supported)
516  return false;
517 #endif
518  return true;
519 #endif
520  return true;
521 }
522 
523 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
524 /// the specified arguments. If we can't run cpuid on the host, return true.
525 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
526  unsigned *rECX, unsigned *rEDX) {
527 #if defined(__GNUC__) || defined(__clang__)
528 #if defined(__x86_64__)
529  // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
530  // FIXME: should we save this for Clang?
531  __asm__("movq\t%%rbx, %%rsi\n\t"
532  "cpuid\n\t"
533  "xchgq\t%%rbx, %%rsi\n\t"
534  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
535  : "a"(value));
536  return false;
537 #elif defined(__i386__)
538  __asm__("movl\t%%ebx, %%esi\n\t"
539  "cpuid\n\t"
540  "xchgl\t%%ebx, %%esi\n\t"
541  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
542  : "a"(value));
543  return false;
544 #else
545  return true;
546 #endif
547 #elif defined(_MSC_VER)
548  // The MSVC intrinsic is portable across x86 and x64.
549  int registers[4];
550  __cpuid(registers, value);
551  *rEAX = registers[0];
552  *rEBX = registers[1];
553  *rECX = registers[2];
554  *rEDX = registers[3];
555  return false;
556 #else
557  return true;
558 #endif
559 }
560 
561 namespace llvm {
562 namespace sys {
563 namespace detail {
564 namespace x86 {
565 
566 VendorSignatures getVendorSignature(unsigned *MaxLeaf) {
567  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
568  if (MaxLeaf == nullptr)
569  MaxLeaf = &EAX;
570  else
571  *MaxLeaf = 0;
572 
573  if (!isCpuIdSupported())
575 
576  if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)
578 
579  // "Genu ineI ntel"
580  if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)
581  return VendorSignatures::GENUINE_INTEL;
582 
583  // "Auth enti cAMD"
584  if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
585  return VendorSignatures::AUTHENTIC_AMD;
586 
588 }
589 
590 } // namespace x86
591 } // namespace detail
592 } // namespace sys
593 } // namespace llvm
594 
595 using namespace llvm::sys::detail::x86;
596 
597 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
598 /// the 4 values in the specified arguments. If we can't run cpuid on the host,
599 /// return true.
600 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
601  unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
602  unsigned *rEDX) {
603 #if defined(__GNUC__) || defined(__clang__)
604 #if defined(__x86_64__)
605  // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
606  // FIXME: should we save this for Clang?
607  __asm__("movq\t%%rbx, %%rsi\n\t"
608  "cpuid\n\t"
609  "xchgq\t%%rbx, %%rsi\n\t"
610  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
611  : "a"(value), "c"(subleaf));
612  return false;
613 #elif defined(__i386__)
614  __asm__("movl\t%%ebx, %%esi\n\t"
615  "cpuid\n\t"
616  "xchgl\t%%ebx, %%esi\n\t"
617  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
618  : "a"(value), "c"(subleaf));
619  return false;
620 #else
621  return true;
622 #endif
623 #elif defined(_MSC_VER)
624  int registers[4];
625  __cpuidex(registers, value, subleaf);
626  *rEAX = registers[0];
627  *rEBX = registers[1];
628  *rECX = registers[2];
629  *rEDX = registers[3];
630  return false;
631 #else
632  return true;
633 #endif
634 }
635 
636 // Read control register 0 (XCR0). Used to detect features such as AVX.
637 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
638 #if defined(__GNUC__) || defined(__clang__)
639  // Check xgetbv; this uses a .byte sequence instead of the instruction
640  // directly because older assemblers do not include support for xgetbv and
641  // there is no easy way to conditionally compile based on the assembler used.
642  __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
643  return false;
644 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
645  unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
646  *rEAX = Result;
647  *rEDX = Result >> 32;
648  return false;
649 #else
650  return true;
651 #endif
652 }
653 
654 static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
655  unsigned *Model) {
656  *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
657  *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
658  if (*Family == 6 || *Family == 0xf) {
659  if (*Family == 0xf)
660  // Examine extended family ID if family ID is F.
661  *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
662  // Examine extended model ID if family ID is 6 or F.
663  *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
664  }
665 }
666 
667 static StringRef
668 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
669  const unsigned *Features,
670  unsigned *Type, unsigned *Subtype) {
671  auto testFeature = [&](unsigned F) {
672  return (Features[F / 32] & (1U << (F % 32))) != 0;
673  };
674 
675  StringRef CPU;
676 
677  switch (Family) {
678  case 3:
679  CPU = "i386";
680  break;
681  case 4:
682  CPU = "i486";
683  break;
684  case 5:
685  if (testFeature(X86::FEATURE_MMX)) {
686  CPU = "pentium-mmx";
687  break;
688  }
689  CPU = "pentium";
690  break;
691  case 6:
692  switch (Model) {
693  case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
694  // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
695  // mobile processor, Intel Core 2 Extreme processor, Intel
696  // Pentium Dual-Core processor, Intel Xeon processor, model
697  // 0Fh. All processors are manufactured using the 65 nm process.
698  case 0x16: // Intel Celeron processor model 16h. All processors are
699  // manufactured using the 65 nm process
700  CPU = "core2";
701  *Type = X86::INTEL_CORE2;
702  break;
703  case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
704  // 17h. All processors are manufactured using the 45 nm process.
705  //
706  // 45nm: Penryn , Wolfdale, Yorkfield (XE)
707  case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
708  // the 45 nm process.
709  CPU = "penryn";
710  *Type = X86::INTEL_CORE2;
711  break;
712  case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
713  // processors are manufactured using the 45 nm process.
714  case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
715  // As found in a Summer 2010 model iMac.
716  case 0x1f:
717  case 0x2e: // Nehalem EX
718  CPU = "nehalem";
719  *Type = X86::INTEL_COREI7;
720  *Subtype = X86::INTEL_COREI7_NEHALEM;
721  break;
722  case 0x25: // Intel Core i7, laptop version.
723  case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
724  // processors are manufactured using the 32 nm process.
725  case 0x2f: // Westmere EX
726  CPU = "westmere";
727  *Type = X86::INTEL_COREI7;
728  *Subtype = X86::INTEL_COREI7_WESTMERE;
729  break;
730  case 0x2a: // Intel Core i7 processor. All processors are manufactured
731  // using the 32 nm process.
732  case 0x2d:
733  CPU = "sandybridge";
734  *Type = X86::INTEL_COREI7;
735  *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
736  break;
737  case 0x3a:
738  case 0x3e: // Ivy Bridge EP
739  CPU = "ivybridge";
740  *Type = X86::INTEL_COREI7;
741  *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
742  break;
743 
744  // Haswell:
745  case 0x3c:
746  case 0x3f:
747  case 0x45:
748  case 0x46:
749  CPU = "haswell";
750  *Type = X86::INTEL_COREI7;
751  *Subtype = X86::INTEL_COREI7_HASWELL;
752  break;
753 
754  // Broadwell:
755  case 0x3d:
756  case 0x47:
757  case 0x4f:
758  case 0x56:
759  CPU = "broadwell";
760  *Type = X86::INTEL_COREI7;
761  *Subtype = X86::INTEL_COREI7_BROADWELL;
762  break;
763 
764  // Skylake:
765  case 0x4e: // Skylake mobile
766  case 0x5e: // Skylake desktop
767  case 0x8e: // Kaby Lake mobile
768  case 0x9e: // Kaby Lake desktop
769  case 0xa5: // Comet Lake-H/S
770  case 0xa6: // Comet Lake-U
771  CPU = "skylake";
772  *Type = X86::INTEL_COREI7;
773  *Subtype = X86::INTEL_COREI7_SKYLAKE;
774  break;
775 
776  // Rocketlake:
777  case 0xa7:
778  CPU = "rocketlake";
779  *Type = X86::INTEL_COREI7;
780  *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
781  break;
782 
783  // Skylake Xeon:
784  case 0x55:
785  *Type = X86::INTEL_COREI7;
786  if (testFeature(X86::FEATURE_AVX512BF16)) {
787  CPU = "cooperlake";
788  *Subtype = X86::INTEL_COREI7_COOPERLAKE;
789  } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
790  CPU = "cascadelake";
791  *Subtype = X86::INTEL_COREI7_CASCADELAKE;
792  } else {
793  CPU = "skylake-avx512";
794  *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
795  }
796  break;
797 
798  // Cannonlake:
799  case 0x66:
800  CPU = "cannonlake";
801  *Type = X86::INTEL_COREI7;
802  *Subtype = X86::INTEL_COREI7_CANNONLAKE;
803  break;
804 
805  // Icelake:
806  case 0x7d:
807  case 0x7e:
808  CPU = "icelake-client";
809  *Type = X86::INTEL_COREI7;
810  *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
811  break;
812 
813  // Tigerlake:
814  case 0x8c:
815  case 0x8d:
816  CPU = "tigerlake";
817  *Type = X86::INTEL_COREI7;
818  *Subtype = X86::INTEL_COREI7_TIGERLAKE;
819  break;
820 
821  // Alderlake:
822  case 0x97:
823  case 0x9a:
824  // Raptorlake:
825  case 0xb7:
826  // Meteorlake:
827  case 0xb5:
828  case 0xaa:
829  case 0xac:
830  CPU = "alderlake";
831  *Type = X86::INTEL_COREI7;
832  *Subtype = X86::INTEL_COREI7_ALDERLAKE;
833  break;
834 
835  // Graniterapids:
836  case 0xae:
837  case 0xad:
838  CPU = "graniterapids";
839  *Type = X86::INTEL_COREI7;
840  *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
841  break;
842 
843  // Icelake Xeon:
844  case 0x6a:
845  case 0x6c:
846  CPU = "icelake-server";
847  *Type = X86::INTEL_COREI7;
848  *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
849  break;
850 
851  // Sapphire Rapids:
852  case 0x8f:
853  CPU = "sapphirerapids";
854  *Type = X86::INTEL_COREI7;
855  *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
856  break;
857 
858  case 0x1c: // Most 45 nm Intel Atom processors
859  case 0x26: // 45 nm Atom Lincroft
860  case 0x27: // 32 nm Atom Medfield
861  case 0x35: // 32 nm Atom Midview
862  case 0x36: // 32 nm Atom Midview
863  CPU = "bonnell";
864  *Type = X86::INTEL_BONNELL;
865  break;
866 
867  // Atom Silvermont codes from the Intel software optimization guide.
868  case 0x37:
869  case 0x4a:
870  case 0x4d:
871  case 0x5a:
872  case 0x5d:
873  case 0x4c: // really airmont
874  CPU = "silvermont";
875  *Type = X86::INTEL_SILVERMONT;
876  break;
877  // Goldmont:
878  case 0x5c: // Apollo Lake
879  case 0x5f: // Denverton
880  CPU = "goldmont";
881  *Type = X86::INTEL_GOLDMONT;
882  break;
883  case 0x7a:
884  CPU = "goldmont-plus";
885  *Type = X86::INTEL_GOLDMONT_PLUS;
886  break;
887  case 0x86:
888  CPU = "tremont";
889  *Type = X86::INTEL_TREMONT;
890  break;
891 
892  // Sierraforest:
893  case 0xaf:
894  CPU = "sierraforest";
895  *Type = X86::INTEL_SIERRAFOREST;
896  break;
897 
898  // Grandridge:
899  case 0xb6:
900  CPU = "grandridge";
901  *Type = X86::INTEL_GRANDRIDGE;
902  break;
903 
904  // Xeon Phi (Knights Landing + Knights Mill):
905  case 0x57:
906  CPU = "knl";
907  *Type = X86::INTEL_KNL;
908  break;
909  case 0x85:
910  CPU = "knm";
911  *Type = X86::INTEL_KNM;
912  break;
913 
914  default: // Unknown family 6 CPU, try to guess.
915  // Don't both with Type/Subtype here, they aren't used by the caller.
916  // They're used above to keep the code in sync with compiler-rt.
917  // TODO detect tigerlake host from model
918  if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
919  CPU = "tigerlake";
920  } else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
921  CPU = "icelake-client";
922  } else if (testFeature(X86::FEATURE_AVX512VBMI)) {
923  CPU = "cannonlake";
924  } else if (testFeature(X86::FEATURE_AVX512BF16)) {
925  CPU = "cooperlake";
926  } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
927  CPU = "cascadelake";
928  } else if (testFeature(X86::FEATURE_AVX512VL)) {
929  CPU = "skylake-avx512";
930  } else if (testFeature(X86::FEATURE_AVX512ER)) {
931  CPU = "knl";
932  } else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
933  if (testFeature(X86::FEATURE_SHA))
934  CPU = "goldmont";
935  else
936  CPU = "skylake";
937  } else if (testFeature(X86::FEATURE_ADX)) {
938  CPU = "broadwell";
939  } else if (testFeature(X86::FEATURE_AVX2)) {
940  CPU = "haswell";
941  } else if (testFeature(X86::FEATURE_AVX)) {
942  CPU = "sandybridge";
943  } else if (testFeature(X86::FEATURE_SSE4_2)) {
944  if (testFeature(X86::FEATURE_MOVBE))
945  CPU = "silvermont";
946  else
947  CPU = "nehalem";
948  } else if (testFeature(X86::FEATURE_SSE4_1)) {
949  CPU = "penryn";
950  } else if (testFeature(X86::FEATURE_SSSE3)) {
951  if (testFeature(X86::FEATURE_MOVBE))
952  CPU = "bonnell";
953  else
954  CPU = "core2";
955  } else if (testFeature(X86::FEATURE_64BIT)) {
956  CPU = "core2";
957  } else if (testFeature(X86::FEATURE_SSE3)) {
958  CPU = "yonah";
959  } else if (testFeature(X86::FEATURE_SSE2)) {
960  CPU = "pentium-m";
961  } else if (testFeature(X86::FEATURE_SSE)) {
962  CPU = "pentium3";
963  } else if (testFeature(X86::FEATURE_MMX)) {
964  CPU = "pentium2";
965  } else {
966  CPU = "pentiumpro";
967  }
968  break;
969  }
970  break;
971  case 15: {
972  if (testFeature(X86::FEATURE_64BIT)) {
973  CPU = "nocona";
974  break;
975  }
976  if (testFeature(X86::FEATURE_SSE3)) {
977  CPU = "prescott";
978  break;
979  }
980  CPU = "pentium4";
981  break;
982  }
983  default:
984  break; // Unknown.
985  }
986 
987  return CPU;
988 }
989 
990 static StringRef
991 getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
992  const unsigned *Features,
993  unsigned *Type, unsigned *Subtype) {
994  auto testFeature = [&](unsigned F) {
995  return (Features[F / 32] & (1U << (F % 32))) != 0;
996  };
997 
998  StringRef CPU;
999 
1000  switch (Family) {
1001  case 4:
1002  CPU = "i486";
1003  break;
1004  case 5:
1005  CPU = "pentium";
1006  switch (Model) {
1007  case 6:
1008  case 7:
1009  CPU = "k6";
1010  break;
1011  case 8:
1012  CPU = "k6-2";
1013  break;
1014  case 9:
1015  case 13:
1016  CPU = "k6-3";
1017  break;
1018  case 10:
1019  CPU = "geode";
1020  break;
1021  }
1022  break;
1023  case 6:
1024  if (testFeature(X86::FEATURE_SSE)) {
1025  CPU = "athlon-xp";
1026  break;
1027  }
1028  CPU = "athlon";
1029  break;
1030  case 15:
1031  if (testFeature(X86::FEATURE_SSE3)) {
1032  CPU = "k8-sse3";
1033  break;
1034  }
1035  CPU = "k8";
1036  break;
1037  case 16:
1038  CPU = "amdfam10";
1039  *Type = X86::AMDFAM10H; // "amdfam10"
1040  switch (Model) {
1041  case 2:
1042  *Subtype = X86::AMDFAM10H_BARCELONA;
1043  break;
1044  case 4:
1045  *Subtype = X86::AMDFAM10H_SHANGHAI;
1046  break;
1047  case 8:
1048  *Subtype = X86::AMDFAM10H_ISTANBUL;
1049  break;
1050  }
1051  break;
1052  case 20:
1053  CPU = "btver1";
1054  *Type = X86::AMD_BTVER1;
1055  break;
1056  case 21:
1057  CPU = "bdver1";
1058  *Type = X86::AMDFAM15H;
1059  if (Model >= 0x60 && Model <= 0x7f) {
1060  CPU = "bdver4";
1061  *Subtype = X86::AMDFAM15H_BDVER4;
1062  break; // 60h-7Fh: Excavator
1063  }
1064  if (Model >= 0x30 && Model <= 0x3f) {
1065  CPU = "bdver3";
1066  *Subtype = X86::AMDFAM15H_BDVER3;
1067  break; // 30h-3Fh: Steamroller
1068  }
1069  if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
1070  CPU = "bdver2";
1071  *Subtype = X86::AMDFAM15H_BDVER2;
1072  break; // 02h, 10h-1Fh: Piledriver
1073  }
1074  if (Model <= 0x0f) {
1075  *Subtype = X86::AMDFAM15H_BDVER1;
1076  break; // 00h-0Fh: Bulldozer
1077  }
1078  break;
1079  case 22:
1080  CPU = "btver2";
1081  *Type = X86::AMD_BTVER2;
1082  break;
1083  case 23:
1084  CPU = "znver1";
1085  *Type = X86::AMDFAM17H;
1086  if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) {
1087  CPU = "znver2";
1088  *Subtype = X86::AMDFAM17H_ZNVER2;
1089  break; // 30h-3fh, 71h: Zen2
1090  }
1091  if (Model <= 0x0f) {
1092  *Subtype = X86::AMDFAM17H_ZNVER1;
1093  break; // 00h-0Fh: Zen1
1094  }
1095  break;
1096  case 25:
1097  CPU = "znver3";
1098  *Type = X86::AMDFAM19H;
1099  if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x5f)) {
1100  // Family 19h Models 00h-0Fh - Zen3
1101  // Family 19h Models 20h-2Fh - Zen3
1102  // Family 19h Models 30h-3Fh - Zen3
1103  // Family 19h Models 40h-4Fh - Zen3+
1104  // Family 19h Models 50h-5Fh - Zen3+
1105  *Subtype = X86::AMDFAM19H_ZNVER3;
1106  break;
1107  }
1108  break;
1109  default:
1110  break; // Unknown AMD CPU.
1111  }
1112 
1113  return CPU;
1114 }
1115 
1116 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
1117  unsigned *Features) {
1118  unsigned EAX, EBX;
1119 
1120  auto setFeature = [&](unsigned F) {
1121  Features[F / 32] |= 1U << (F % 32);
1122  };
1123 
1124  if ((EDX >> 15) & 1)
1125  setFeature(X86::FEATURE_CMOV);
1126  if ((EDX >> 23) & 1)
1127  setFeature(X86::FEATURE_MMX);
1128  if ((EDX >> 25) & 1)
1129  setFeature(X86::FEATURE_SSE);
1130  if ((EDX >> 26) & 1)
1131  setFeature(X86::FEATURE_SSE2);
1132 
1133  if ((ECX >> 0) & 1)
1134  setFeature(X86::FEATURE_SSE3);
1135  if ((ECX >> 1) & 1)
1136  setFeature(X86::FEATURE_PCLMUL);
1137  if ((ECX >> 9) & 1)
1138  setFeature(X86::FEATURE_SSSE3);
1139  if ((ECX >> 12) & 1)
1140  setFeature(X86::FEATURE_FMA);
1141  if ((ECX >> 19) & 1)
1142  setFeature(X86::FEATURE_SSE4_1);
1143  if ((ECX >> 20) & 1) {
1144  setFeature(X86::FEATURE_SSE4_2);
1145  setFeature(X86::FEATURE_CRC32);
1146  }
1147  if ((ECX >> 23) & 1)
1148  setFeature(X86::FEATURE_POPCNT);
1149  if ((ECX >> 25) & 1)
1150  setFeature(X86::FEATURE_AES);
1151 
1152  if ((ECX >> 22) & 1)
1153  setFeature(X86::FEATURE_MOVBE);
1154 
1155  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1156  // indicates that the AVX registers will be saved and restored on context
1157  // switch, then we have full AVX support.
1158  const unsigned AVXBits = (1 << 27) | (1 << 28);
1159  bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1160  ((EAX & 0x6) == 0x6);
1161 #if defined(__APPLE__)
1162  // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1163  // save the AVX512 context if we use AVX512 instructions, even the bit is not
1164  // set right now.
1165  bool HasAVX512Save = true;
1166 #else
1167  // AVX512 requires additional context to be saved by the OS.
1168  bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
1169 #endif
1170 
1171  if (HasAVX)
1172  setFeature(X86::FEATURE_AVX);
1173 
1174  bool HasLeaf7 =
1175  MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1176 
1177  if (HasLeaf7 && ((EBX >> 3) & 1))
1178  setFeature(X86::FEATURE_BMI);
1179  if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1180  setFeature(X86::FEATURE_AVX2);
1181  if (HasLeaf7 && ((EBX >> 8) & 1))
1182  setFeature(X86::FEATURE_BMI2);
1183  if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
1184  setFeature(X86::FEATURE_AVX512F);
1185  if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1186  setFeature(X86::FEATURE_AVX512DQ);
1187  if (HasLeaf7 && ((EBX >> 19) & 1))
1188  setFeature(X86::FEATURE_ADX);
1189  if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1190  setFeature(X86::FEATURE_AVX512IFMA);
1191  if (HasLeaf7 && ((EBX >> 23) & 1))
1192  setFeature(X86::FEATURE_CLFLUSHOPT);
1193  if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
1194  setFeature(X86::FEATURE_AVX512PF);
1195  if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
1196  setFeature(X86::FEATURE_AVX512ER);
1197  if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1198  setFeature(X86::FEATURE_AVX512CD);
1199  if (HasLeaf7 && ((EBX >> 29) & 1))
1200  setFeature(X86::FEATURE_SHA);
1201  if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1202  setFeature(X86::FEATURE_AVX512BW);
1203  if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1204  setFeature(X86::FEATURE_AVX512VL);
1205 
1206  if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1207  setFeature(X86::FEATURE_AVX512VBMI);
1208  if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1209  setFeature(X86::FEATURE_AVX512VBMI2);
1210  if (HasLeaf7 && ((ECX >> 8) & 1))
1211  setFeature(X86::FEATURE_GFNI);
1212  if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1213  setFeature(X86::FEATURE_VPCLMULQDQ);
1214  if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1215  setFeature(X86::FEATURE_AVX512VNNI);
1216  if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1217  setFeature(X86::FEATURE_AVX512BITALG);
1218  if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1219  setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1220 
1221  if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1222  setFeature(X86::FEATURE_AVX5124VNNIW);
1223  if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1224  setFeature(X86::FEATURE_AVX5124FMAPS);
1225  if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1226  setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1227 
1228  bool HasLeaf7Subleaf1 =
1229  MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1230  if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1231  setFeature(X86::FEATURE_AVX512BF16);
1232 
1233  unsigned MaxExtLevel;
1234  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1235 
1236  bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1237  !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1238  if (HasExtLeaf1 && ((ECX >> 6) & 1))
1239  setFeature(X86::FEATURE_SSE4_A);
1240  if (HasExtLeaf1 && ((ECX >> 11) & 1))
1241  setFeature(X86::FEATURE_XOP);
1242  if (HasExtLeaf1 && ((ECX >> 16) & 1))
1243  setFeature(X86::FEATURE_FMA4);
1244 
1245  if (HasExtLeaf1 && ((EDX >> 29) & 1))
1246  setFeature(X86::FEATURE_64BIT);
1247 }
1248 
1250  unsigned MaxLeaf = 0;
1251  const VendorSignatures Vendor = getVendorSignature(&MaxLeaf);
1252  if (Vendor == VendorSignatures::UNKNOWN)
1253  return "generic";
1254 
1255  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1256  getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1257 
1258  unsigned Family = 0, Model = 0;
1259  unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0};
1260  detectX86FamilyModel(EAX, &Family, &Model);
1261  getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1262 
1263  // These aren't consumed in this file, but we try to keep some source code the
1264  // same or similar to compiler-rt.
1265  unsigned Type = 0;
1266  unsigned Subtype = 0;
1267 
1268  StringRef CPU;
1269 
1270  if (Vendor == VendorSignatures::GENUINE_INTEL) {
1271  CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type,
1272  &Subtype);
1273  } else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
1274  CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type,
1275  &Subtype);
1276  }
1277 
1278  if (!CPU.empty())
1279  return CPU;
1280 
1281  return "generic";
1282 }
1283 
1284 #elif defined(__APPLE__) && defined(__powerpc__)
1286  host_basic_info_data_t hostInfo;
1287  mach_msg_type_number_t infoCount;
1288 
1289  infoCount = HOST_BASIC_INFO_COUNT;
1290  mach_port_t hostPort = mach_host_self();
1291  host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1292  &infoCount);
1293  mach_port_deallocate(mach_task_self(), hostPort);
1294 
1295  if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1296  return "generic";
1297 
1298  switch (hostInfo.cpu_subtype) {
1300  return "601";
1302  return "602";
1304  return "603";
1306  return "603e";
1308  return "603ev";
1310  return "604";
1312  return "604e";
1314  return "620";
1316  return "750";
1318  return "7400";
1320  return "7450";
1322  return "970";
1323  default:;
1324  }
1325 
1326  return "generic";
1327 }
1328 #elif defined(__linux__) && defined(__powerpc__)
1330  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1331  StringRef Content = P ? P->getBuffer() : "";
1333 }
1334 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1336  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1337  StringRef Content = P ? P->getBuffer() : "";
1339 }
1340 #elif defined(__linux__) && defined(__s390x__)
1342  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1343  StringRef Content = P ? P->getBuffer() : "";
1345 }
1346 #elif defined(__MVS__)
1348  // Get pointer to Communications Vector Table (CVT).
1349  // The pointer is located at offset 16 of the Prefixed Save Area (PSA).
1350  // It is stored as 31 bit pointer and will be zero-extended to 64 bit.
1351  int *StartToCVTOffset = reinterpret_cast<int *>(0x10);
1352  // Since its stored as a 31-bit pointer, get the 4 bytes from the start
1353  // of address.
1354  int ReadValue = *StartToCVTOffset;
1355  // Explicitly clear the high order bit.
1356  ReadValue = (ReadValue & 0x7FFFFFFF);
1357  char *CVT = reinterpret_cast<char *>(ReadValue);
1358  // The model number is located in the CVT prefix at offset -6 and stored as
1359  // signless packed decimal.
1360  uint16_t Id = *(uint16_t *)&CVT[-6];
1361  // Convert number to integer.
1362  Id = decodePackedBCD<uint16_t>(Id, false);
1363  // Check for vector support. It's stored in field CVTFLAG5 (offset 244),
1364  // bit CVTVEF (X'80'). The facilities list is part of the PSA but the vector
1365  // extension can only be used if bit CVTVEF is on.
1366  bool HaveVectorSupport = CVT[244] & 0x80;
1367  return getCPUNameFromS390Model(Id, HaveVectorSupport);
1368 }
1369 #elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
1370 #define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1371 #define CPUFAMILY_ARM_CYCLONE 0x37a09642
1372 #define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1373 #define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1374 #define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1375 #define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1376 #define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1377 #define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1378 #define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1379 
1381  uint32_t Family;
1382  size_t Length = sizeof(Family);
1383  sysctlbyname("hw.cpufamily", &Family, &Length, NULL, 0);
1384 
1385  switch (Family) {
1386  case CPUFAMILY_ARM_SWIFT:
1387  return "swift";
1388  case CPUFAMILY_ARM_CYCLONE:
1389  return "apple-a7";
1390  case CPUFAMILY_ARM_TYPHOON:
1391  return "apple-a8";
1392  case CPUFAMILY_ARM_TWISTER:
1393  return "apple-a9";
1394  case CPUFAMILY_ARM_HURRICANE:
1395  return "apple-a10";
1396  case CPUFAMILY_ARM_MONSOON_MISTRAL:
1397  return "apple-a11";
1398  case CPUFAMILY_ARM_VORTEX_TEMPEST:
1399  return "apple-a12";
1400  case CPUFAMILY_ARM_LIGHTNING_THUNDER:
1401  return "apple-a13";
1402  case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
1403  return "apple-m1";
1404  default:
1405  // Default to the newest CPU we know about.
1406  return "apple-m1";
1407  }
1408 }
1409 #elif defined(_AIX)
1411  switch (_system_configuration.implementation) {
1412  case POWER_4:
1413  if (_system_configuration.version == PV_4_3)
1414  return "970";
1415  return "pwr4";
1416  case POWER_5:
1417  if (_system_configuration.version == PV_5)
1418  return "pwr5";
1419  return "pwr5x";
1420  case POWER_6:
1421  if (_system_configuration.version == PV_6_Compat)
1422  return "pwr6";
1423  return "pwr6x";
1424  case POWER_7:
1425  return "pwr7";
1426  case POWER_8:
1427  return "pwr8";
1428  case POWER_9:
1429  return "pwr9";
1430 // TODO: simplify this once the macro is available in all OS levels.
1431 #ifdef POWER_10
1432  case POWER_10:
1433 #else
1434  case 0x40000:
1435 #endif
1436  return "pwr10";
1437  default:
1438  return "generic";
1439  }
1440 }
1441 #elif defined(__riscv)
1443 #if defined(__linux__)
1444  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1445  StringRef Content = P ? P->getBuffer() : "";
1447 #else
1448 #if __riscv_xlen == 64
1449  return "generic-rv64";
1450 #elif __riscv_xlen == 32
1451  return "generic-rv32";
1452 #else
1453 #error "Unhandled value of __riscv_xlen"
1454 #endif
1455 #endif
1456 }
1457 #elif defined(__sparc__)
1458 #if defined(__linux__)
1461  ProcCpuinfoContent.split(Lines, "\n");
1462 
1463  // Look for cpu line to determine cpu name
1464  StringRef Cpu;
1465  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
1466  if (Lines[I].startswith("cpu")) {
1467  Cpu = Lines[I].substr(5).ltrim("\t :");
1468  break;
1469  }
1470  }
1471 
1472  return StringSwitch<const char *>(Cpu)
1473  .StartsWith("SuperSparc", "supersparc")
1474  .StartsWith("HyperSparc", "hypersparc")
1475  .StartsWith("SpitFire", "ultrasparc")
1476  .StartsWith("BlackBird", "ultrasparc")
1477  .StartsWith("Sabre", " ultrasparc")
1478  .StartsWith("Hummingbird", "ultrasparc")
1479  .StartsWith("Cheetah", "ultrasparc3")
1480  .StartsWith("Jalapeno", "ultrasparc3")
1481  .StartsWith("Jaguar", "ultrasparc3")
1482  .StartsWith("Panther", "ultrasparc3")
1483  .StartsWith("Serrano", "ultrasparc3")
1484  .StartsWith("UltraSparc T1", "niagara")
1485  .StartsWith("UltraSparc T2", "niagara2")
1486  .StartsWith("UltraSparc T3", "niagara3")
1487  .StartsWith("UltraSparc T4", "niagara4")
1488  .StartsWith("UltraSparc T5", "niagara4")
1489  .StartsWith("LEON", "leon3")
1490  // niagara7/m8 not supported by LLVM yet.
1491  .StartsWith("SPARC-M7", "niagara4" /* "niagara7" */)
1492  .StartsWith("SPARC-S7", "niagara4" /* "niagara7" */)
1493  .StartsWith("SPARC-M8", "niagara4" /* "m8" */)
1494  .Default("generic");
1495 }
1496 #endif
1497 
1499 #if defined(__linux__)
1500  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1501  StringRef Content = P ? P->getBuffer() : "";
1503 #elif defined(__sun__) && defined(__svr4__)
1504  char *buf = NULL;
1505  kstat_ctl_t *kc;
1506  kstat_t *ksp;
1507  kstat_named_t *brand = NULL;
1508 
1509  kc = kstat_open();
1510  if (kc != NULL) {
1511  ksp = kstat_lookup(kc, const_cast<char *>("cpu_info"), -1, NULL);
1512  if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1513  ksp->ks_type == KSTAT_TYPE_NAMED)
1514  brand =
1515  (kstat_named_t *)kstat_data_lookup(ksp, const_cast<char *>("brand"));
1516  if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1517  buf = KSTAT_NAMED_STR_PTR(brand);
1518  }
1519  kstat_close(kc);
1520 
1521  return StringSwitch<const char *>(buf)
1522  .Case("TMS390S10", "supersparc") // Texas Instruments microSPARC I
1523  .Case("TMS390Z50", "supersparc") // Texas Instruments SuperSPARC I
1524  .Case("TMS390Z55",
1525  "supersparc") // Texas Instruments SuperSPARC I with SuperCache
1526  .Case("MB86904", "supersparc") // Fujitsu microSPARC II
1527  .Case("MB86907", "supersparc") // Fujitsu TurboSPARC
1528  .Case("RT623", "hypersparc") // Ross hyperSPARC
1529  .Case("RT625", "hypersparc")
1530  .Case("RT626", "hypersparc")
1531  .Case("UltraSPARC-I", "ultrasparc")
1532  .Case("UltraSPARC-II", "ultrasparc")
1533  .Case("UltraSPARC-IIe", "ultrasparc")
1534  .Case("UltraSPARC-IIi", "ultrasparc")
1535  .Case("SPARC64-III", "ultrasparc")
1536  .Case("SPARC64-IV", "ultrasparc")
1537  .Case("UltraSPARC-III", "ultrasparc3")
1538  .Case("UltraSPARC-III+", "ultrasparc3")
1539  .Case("UltraSPARC-IIIi", "ultrasparc3")
1540  .Case("UltraSPARC-IIIi+", "ultrasparc3")
1541  .Case("UltraSPARC-IV", "ultrasparc3")
1542  .Case("UltraSPARC-IV+", "ultrasparc3")
1543  .Case("SPARC64-V", "ultrasparc3")
1544  .Case("SPARC64-VI", "ultrasparc3")
1545  .Case("SPARC64-VII", "ultrasparc3")
1546  .Case("UltraSPARC-T1", "niagara")
1547  .Case("UltraSPARC-T2", "niagara2")
1548  .Case("UltraSPARC-T2", "niagara2")
1549  .Case("UltraSPARC-T2+", "niagara2")
1550  .Case("SPARC-T3", "niagara3")
1551  .Case("SPARC-T4", "niagara4")
1552  .Case("SPARC-T5", "niagara4")
1553  // niagara7/m8 not supported by LLVM yet.
1554  .Case("SPARC-M7", "niagara4" /* "niagara7" */)
1555  .Case("SPARC-S7", "niagara4" /* "niagara7" */)
1556  .Case("SPARC-M8", "niagara4" /* "m8" */)
1557  .Default("generic");
1558 #else
1559  return "generic";
1560 #endif
1561 }
1562 #else
1563 StringRef sys::getHostCPUName() { return "generic"; }
1564 namespace llvm {
1565 namespace sys {
1566 namespace detail {
1567 namespace x86 {
1568 
1571 }
1572 
1573 } // namespace x86
1574 } // namespace detail
1575 } // namespace sys
1576 } // namespace llvm
1577 #endif
1578 
1579 #if defined(__linux__) && (defined(__i386__) || defined(__x86_64__))
1580 // On Linux, the number of physical cores can be computed from /proc/cpuinfo,
1581 // using the number of unique physical/core id pairs. The following
1582 // implementation reads the /proc/cpuinfo format on an x86_64 system.
1583 static int computeHostNumPhysicalCores() {
1584  // Enabled represents the number of physical id/core id pairs with at least
1585  // one processor id enabled by the CPU affinity mask.
1586  cpu_set_t Affinity, Enabled;
1587  if (sched_getaffinity(0, sizeof(Affinity), &Affinity) != 0)
1588  return -1;
1589  CPU_ZERO(&Enabled);
1590 
1591  // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be
1592  // mmapped because it appears to have 0 size.
1594  llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
1595  if (std::error_code EC = Text.getError()) {
1596  llvm::errs() << "Can't read "
1597  << "/proc/cpuinfo: " << EC.message() << "\n";
1598  return -1;
1599  }
1601  (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1,
1602  /*KeepEmpty=*/false);
1603  int CurProcessor = -1;
1604  int CurPhysicalId = -1;
1605  int CurSiblings = -1;
1606  int CurCoreId = -1;
1607  for (StringRef Line : strs) {
1608  std::pair<StringRef, StringRef> Data = Line.split(':');
1609  auto Name = Data.first.trim();
1610  auto Val = Data.second.trim();
1611  // These fields are available if the kernel is configured with CONFIG_SMP.
1612  if (Name == "processor")
1613  Val.getAsInteger(10, CurProcessor);
1614  else if (Name == "physical id")
1615  Val.getAsInteger(10, CurPhysicalId);
1616  else if (Name == "siblings")
1617  Val.getAsInteger(10, CurSiblings);
1618  else if (Name == "core id") {
1619  Val.getAsInteger(10, CurCoreId);
1620  // The processor id corresponds to an index into cpu_set_t.
1621  if (CPU_ISSET(CurProcessor, &Affinity))
1622  CPU_SET(CurPhysicalId * CurSiblings + CurCoreId, &Enabled);
1623  }
1624  }
1625  return CPU_COUNT(&Enabled);
1626 }
1627 #elif defined(__linux__) && defined(__s390x__)
1628 static int computeHostNumPhysicalCores() {
1629  return sysconf(_SC_NPROCESSORS_ONLN);
1630 }
1631 #elif defined(__linux__) && !defined(__ANDROID__)
1632 static int computeHostNumPhysicalCores() {
1633  cpu_set_t Affinity;
1634  if (sched_getaffinity(0, sizeof(Affinity), &Affinity) == 0)
1635  return CPU_COUNT(&Affinity);
1636 
1637  // The call to sched_getaffinity() may have failed because the Affinity
1638  // mask is too small for the number of CPU's on the system (i.e. the
1639  // system has more than 1024 CPUs). Allocate a mask large enough for
1640  // twice as many CPUs.
1641  cpu_set_t *DynAffinity;
1642  DynAffinity = CPU_ALLOC(2048);
1643  if (sched_getaffinity(0, CPU_ALLOC_SIZE(2048), DynAffinity) == 0) {
1644  int NumCPUs = CPU_COUNT(DynAffinity);
1645  CPU_FREE(DynAffinity);
1646  return NumCPUs;
1647  }
1648  return -1;
1649 }
1650 #elif defined(__APPLE__)
1651 // Gets the number of *physical cores* on the machine.
1652 static int computeHostNumPhysicalCores() {
1653  uint32_t count;
1654  size_t len = sizeof(count);
1655  sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0);
1656  if (count < 1) {
1657  int nm[2];
1658  nm[0] = CTL_HW;
1659  nm[1] = HW_AVAILCPU;
1660  sysctl(nm, 2, &count, &len, NULL, 0);
1661  if (count < 1)
1662  return -1;
1663  }
1664  return count;
1665 }
1666 #elif defined(__MVS__)
1667 static int computeHostNumPhysicalCores() {
1668  enum {
1669  // Byte offset of the pointer to the Communications Vector Table (CVT) in
1670  // the Prefixed Save Area (PSA). The table entry is a 31-bit pointer and
1671  // will be zero-extended to uintptr_t.
1672  FLCCVT = 16,
1673  // Byte offset of the pointer to the Common System Data Area (CSD) in the
1674  // CVT. The table entry is a 31-bit pointer and will be zero-extended to
1675  // uintptr_t.
1676  CVTCSD = 660,
1677  // Byte offset to the number of live CPs in the LPAR, stored as a signed
1678  // 32-bit value in the table.
1679  CSD_NUMBER_ONLINE_STANDARD_CPS = 264,
1680  };
1681  char *PSA = 0;
1682  char *CVT = reinterpret_cast<char *>(
1683  static_cast<uintptr_t>(reinterpret_cast<unsigned int &>(PSA[FLCCVT])));
1684  char *CSD = reinterpret_cast<char *>(
1685  static_cast<uintptr_t>(reinterpret_cast<unsigned int &>(CVT[CVTCSD])));
1686  return reinterpret_cast<int &>(CSD[CSD_NUMBER_ONLINE_STANDARD_CPS]);
1687 }
1688 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0
1689 // Defined in llvm/lib/Support/Windows/Threading.inc
1691 #else
1692 // On other systems, return -1 to indicate unknown.
1693 static int computeHostNumPhysicalCores() { return -1; }
1694 #endif
1695 
1697  static int NumCores = computeHostNumPhysicalCores();
1698  return NumCores;
1699 }
1700 
1701 #if defined(__i386__) || defined(_M_IX86) || \
1702  defined(__x86_64__) || defined(_M_X64)
1703 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1704  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1705  unsigned MaxLevel;
1706 
1707  if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
1708  return false;
1709 
1710  getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1711 
1712  Features["cx8"] = (EDX >> 8) & 1;
1713  Features["cmov"] = (EDX >> 15) & 1;
1714  Features["mmx"] = (EDX >> 23) & 1;
1715  Features["fxsr"] = (EDX >> 24) & 1;
1716  Features["sse"] = (EDX >> 25) & 1;
1717  Features["sse2"] = (EDX >> 26) & 1;
1718 
1719  Features["sse3"] = (ECX >> 0) & 1;
1720  Features["pclmul"] = (ECX >> 1) & 1;
1721  Features["ssse3"] = (ECX >> 9) & 1;
1722  Features["cx16"] = (ECX >> 13) & 1;
1723  Features["sse4.1"] = (ECX >> 19) & 1;
1724  Features["sse4.2"] = (ECX >> 20) & 1;
1725  Features["crc32"] = Features["sse4.2"];
1726  Features["movbe"] = (ECX >> 22) & 1;
1727  Features["popcnt"] = (ECX >> 23) & 1;
1728  Features["aes"] = (ECX >> 25) & 1;
1729  Features["rdrnd"] = (ECX >> 30) & 1;
1730 
1731  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1732  // indicates that the AVX registers will be saved and restored on context
1733  // switch, then we have full AVX support.
1734  bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
1735  bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6);
1736 #if defined(__APPLE__)
1737  // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1738  // save the AVX512 context if we use AVX512 instructions, even the bit is not
1739  // set right now.
1740  bool HasAVX512Save = true;
1741 #else
1742  // AVX512 requires additional context to be saved by the OS.
1743  bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1744 #endif
1745  // AMX requires additional context to be saved by the OS.
1746  const unsigned AMXBits = (1 << 17) | (1 << 18);
1747  bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits);
1748 
1749  Features["avx"] = HasAVXSave;
1750  Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave;
1751  // Only enable XSAVE if OS has enabled support for saving YMM state.
1752  Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
1753  Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave;
1754 
1755  unsigned MaxExtLevel;
1756  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1757 
1758  bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1759  !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1760  Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1);
1761  Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
1762  Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
1763  Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
1764  Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1765  Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);
1766  Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1767  Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
1768  Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1769 
1770  Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1);
1771 
1772  // Miscellaneous memory related features, detected by
1773  // using the 0x80000008 leaf of the CPUID instruction
1774  bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1775  !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1776  Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
1777  Features["rdpru"] = HasExtLeaf8 && ((EBX >> 4) & 1);
1778  Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
1779 
1780  bool HasLeaf7 =
1781  MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1782 
1783  Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
1784  Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
1785  Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1786  // AVX2 is only supported if we have the OS save support from AVX.
1787  Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave;
1788  Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
1789  Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
1790  Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
1791  // AVX512 is only supported if the OS supports the context save for it.
1792  Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1793  Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1794  Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
1795  Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
1796  Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1797  Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1798  Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
1799  Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
1800  Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
1801  Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1802  Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
1803  Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1804  Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1805 
1806  Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1);
1807  Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
1808  Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
1809  Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1);
1810  Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save;
1811  Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1);
1812  Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1);
1813  Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave;
1814  Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
1815  Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
1816  Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
1817  Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
1818  Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1);
1819  Features["kl"] = HasLeaf7 && ((ECX >> 23) & 1); // key locker
1820  Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1);
1821  Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);
1822  Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
1823  Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1);
1824 
1825  Features["uintr"] = HasLeaf7 && ((EDX >> 5) & 1);
1826  Features["avx512vp2intersect"] =
1827  HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save;
1828  Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1);
1829  Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1);
1830  // There are two CPUID leafs which information associated with the pconfig
1831  // instruction:
1832  // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
1833  // bit of EDX), while the EAX=0x1b leaf returns information on the
1834  // availability of specific pconfig leafs.
1835  // The target feature here only refers to the the first of these two.
1836  // Users might need to check for the availability of specific pconfig
1837  // leaves using cpuid, since that information is ignored while
1838  // detecting features using the "-march=native" flag.
1839  // For more info, see X86 ISA docs.
1840  Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
1841  Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;
1842  Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save;
1843  Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
1844  Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
1845  bool HasLeaf7Subleaf1 =
1846  MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1847  Features["raoint"] = HasLeaf7Subleaf1 && ((EAX >> 3) & 1);
1848  Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;
1849  Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
1850  Features["amx-fp16"] = HasLeaf7Subleaf1 && ((EAX >> 21) & 1) && HasAMXSave;
1851  Features["cmpccxadd"] = HasLeaf7Subleaf1 && ((EAX >> 7) & 1);
1852  Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1);
1853  Features["avxifma"] = HasLeaf7Subleaf1 && ((EAX >> 23) & 1) && HasAVXSave;
1854  Features["avxvnniint8"] = HasLeaf7Subleaf1 && ((EDX >> 4) & 1) && HasAVXSave;
1855  Features["avxneconvert"] = HasLeaf7Subleaf1 && ((EDX >> 5) & 1) && HasAVXSave;
1856  Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
1857 
1858  bool HasLeafD = MaxLevel >= 0xd &&
1859  !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1860 
1861  // Only enable XSAVE if OS has enabled support for saving YMM state.
1862  Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
1863  Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
1864  Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
1865 
1866  bool HasLeaf14 = MaxLevel >= 0x14 &&
1867  !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1868 
1869  Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
1870 
1871  bool HasLeaf19 =
1872  MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
1873  Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1);
1874 
1875  return true;
1876 }
1877 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1878 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1879  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1880  if (!P)
1881  return false;
1882 
1884  P->getBuffer().split(Lines, "\n");
1885 
1886  SmallVector<StringRef, 32> CPUFeatures;
1887 
1888  // Look for the CPU features.
1889  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1890  if (Lines[I].startswith("Features")) {
1891  Lines[I].split(CPUFeatures, ' ');
1892  break;
1893  }
1894 
1895 #if defined(__aarch64__)
1896  // Keep track of which crypto features we have seen
1897  enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1898  uint32_t crypto = 0;
1899 #endif
1900 
1901  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1902  StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1903 #if defined(__aarch64__)
1904  .Case("asimd", "neon")
1905  .Case("fp", "fp-armv8")
1906  .Case("crc32", "crc")
1907  .Case("atomics", "lse")
1908  .Case("sve", "sve")
1909  .Case("sve2", "sve2")
1910 #else
1911  .Case("half", "fp16")
1912  .Case("neon", "neon")
1913  .Case("vfpv3", "vfp3")
1914  .Case("vfpv3d16", "d16")
1915  .Case("vfpv4", "vfp4")
1916  .Case("idiva", "hwdiv-arm")
1917  .Case("idivt", "hwdiv")
1918 #endif
1919  .Default("");
1920 
1921 #if defined(__aarch64__)
1922  // We need to check crypto separately since we need all of the crypto
1923  // extensions to enable the subtarget feature
1924  if (CPUFeatures[I] == "aes")
1925  crypto |= CAP_AES;
1926  else if (CPUFeatures[I] == "pmull")
1927  crypto |= CAP_PMULL;
1928  else if (CPUFeatures[I] == "sha1")
1929  crypto |= CAP_SHA1;
1930  else if (CPUFeatures[I] == "sha2")
1931  crypto |= CAP_SHA2;
1932 #endif
1933 
1934  if (LLVMFeatureStr != "")
1935  Features[LLVMFeatureStr] = true;
1936  }
1937 
1938 #if defined(__aarch64__)
1939  // If we have all crypto bits we can add the feature
1940  if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1941  Features["crypto"] = true;
1942 #endif
1943 
1944  return true;
1945 }
1946 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
1947 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1948  if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE))
1949  Features["neon"] = true;
1950  if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
1951  Features["crc"] = true;
1952  if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
1953  Features["crypto"] = true;
1954 
1955  return true;
1956 }
1957 #else
1958 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
1959 #endif
1960 
1961 std::string sys::getProcessTriple() {
1962  std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
1963  Triple PT(Triple::normalize(TargetTripleString));
1964 
1965  if (sizeof(void *) == 8 && PT.isArch32Bit())
1966  PT = PT.get64BitArchVariant();
1967  if (sizeof(void *) == 4 && PT.isArch64Bit())
1968  PT = PT.get32BitArchVariant();
1969 
1970  return PT.str();
1971 }
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
MemoryBuffer.h
llvm::StringSwitch::StartsWith
StringSwitch & StartsWith(StringLiteral S, T Value)
Definition: StringSwitch.h:83
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::N86::EDX
@ EDX
Definition: X86MCTargetDesc.h:51
llvm::codeview::DebugSubsectionKind::Lines
@ Lines
llvm::sys::detail::x86::VendorSignatures::GENUINE_INTEL
@ GENUINE_INTEL
StringRef.h
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::MachO::CPU_SUBTYPE_POWERPC_603ev
@ CPU_SUBTYPE_POWERPC_603ev
Definition: MachO.h:1654
llvm::StringRef::npos
static constexpr size_t npos
Definition: StringRef.h:52
Host.h
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
Content
T Content
Definition: ELFObjHandler.cpp:89
llvm::Triple::get32BitArchVariant
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
Definition: Triple.cpp:1474
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Host.inc
startswith
static bool startswith(StringRef Magic, const char(&S)[N])
Definition: Magic.cpp:28
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::sys::getHostCPUFeatures
bool getHostCPUFeatures(StringMap< bool, MallocAllocator > &Features)
getHostCPUFeatures - Get the LLVM names for the host CPU features.
llvm::sys::detail::x86::VendorSignatures::UNKNOWN
@ UNKNOWN
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:891
llvm::MachO::CPU_SUBTYPE_POWERPC_7450
@ CPU_SUBTYPE_POWERPC_7450
Definition: MachO.h:1660
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:172
llvm::MachO::CPU_SUBTYPE_POWERPC_603
@ CPU_SUBTYPE_POWERPC_603
Definition: MachO.h:1652
x86
Note that only the low bits of effective_addr2 are used On bit we don t eliminate the computation of the top half of effective_addr2 because we don t have whole function selection dags On x86
Definition: README.txt:318
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
llvm::MachO::CPU_SUBTYPE_POWERPC_604e
@ CPU_SUBTYPE_POWERPC_604e
Definition: MachO.h:1656
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::Triple::isArch64Bit
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1462
llvm::MemoryBuffer::getFileAsStream
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
Definition: MemoryBuffer.cpp:541
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::sys::detail::x86
Helper functions to extract CPU details from CPUID on x86.
Definition: Host.h:72
llvm::Triple::get64BitArchVariant
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
Definition: Triple.cpp:1553
llvm::sys::detail::x86::VendorSignatures::AUTHENTIC_AMD
@ AUTHENTIC_AMD
llvm::Triple::str
const std::string & str() const
Definition: Triple.h:413
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::X86::CPU_FEATURE_MAX
@ CPU_FEATURE_MAX
Definition: X86TargetParser.h:60
llvm::MachO::CPU_SUBTYPE_POWERPC_602
@ CPU_SUBTYPE_POWERPC_602
Definition: MachO.h:1651
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::MachO::CPU_TYPE_POWERPC
@ CPU_TYPE_POWERPC
Definition: MachO.h:1571
llvm::logicalview::LVSortMode::Line
@ Line
BCD.h
computeHostNumPhysicalCores
static int computeHostNumPhysicalCores()
Definition: Host.cpp:1693
llvm::StringMap< bool >
getProcCpuinfoContent
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
Definition: Host.cpp:65
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
X86TargetParser.h
llvm::AMDGPU::FEATURE_FMA
@ FEATURE_FMA
Definition: TargetParser.h:125
llvm::count
auto count(R &&Range, const E &Element)
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:1870
uint64_t
llvm::StringRef::end
iterator end() const
Definition: StringRef.h:113
llvm::Triple::normalize
std::string normalize() const
Return the normalized form of this triple's string.
Definition: Triple.h:347
llvm::Triple::isArch32Bit
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1466
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MachO::CPU_SUBTYPE_POWERPC_620
@ CPU_SUBTYPE_POWERPC_620
Definition: MachO.h:1657
Host.inc
llvm::MachO::CPU_SUBTYPE_POWERPC_750
@ CPU_SUBTYPE_POWERPC_750
Definition: MachO.h:1658
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::N86::ECX
@ ECX
Definition: X86MCTargetDesc.h:51
llvm::sys::detail::getHostCPUNameForRISCV
StringRef getHostCPUNameForRISCV(StringRef ProcCpuinfoContent)
Definition: Host.cpp:399
llvm::support::aligned
@ aligned
Definition: Endian.h:30
llvm::codeview::CompileSym2Flags::EC
@ EC
llvm::MachO::CPU_SUBTYPE_POWERPC_601
@ CPU_SUBTYPE_POWERPC_601
Definition: MachO.h:1650
llvm::N86::EAX
@ EAX
Definition: X86MCTargetDesc.h:51
Triple.h
llvm::sys::getHostNumPhysicalCores
int getHostNumPhysicalCores()
Get the number of physical cores (as opposed to logical cores returned from thread::hardware_concurre...
Definition: Host.cpp:1696
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::MachO::CPU_SUBTYPE_POWERPC_604
@ CPU_SUBTYPE_POWERPC_604
Definition: MachO.h:1655
llvm::sys::detail::getHostCPUNameForBPF
StringRef getHostCPUNameForBPF()
Definition: Host.cpp:419
uint32_t
llvm::LPAC::UNKNOWN
@ UNKNOWN
Definition: LanaiAluCode.h:40
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::N86::EBX
@ EBX
Definition: X86MCTargetDesc.h:51
llvm::MachO::CPU_SUBTYPE_POWERPC_7400
@ CPU_SUBTYPE_POWERPC_7400
Definition: MachO.h:1659
llvm::sys::detail::getHostCPUNameForS390x
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
Definition: Host.cpp:354
uint16_t
llvm::sys::detail::x86::VendorSignatures
VendorSignatures
Definition: Host.h:73
llvm::sys::getProcessTriple
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
Definition: Host.cpp:1961
llvm::MachO::CPU_SUBTYPE_POWERPC_603e
@ CPU_SUBTYPE_POWERPC_603e
Definition: MachO.h:1653
llvm::StringRef::endswith
bool endswith(StringRef Suffix) const
Definition: StringRef.h:276
Enabled
static bool Enabled
Definition: Statistic.cpp:46
StringSwitch.h
SmallVector.h
llvm::sys::detail::getHostCPUNameForARM
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
Definition: Host.cpp:159
llvm::sys::detail::getHostCPUNameForPowerPC
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
Definition: Host.cpp:76
llvm::ErrorOr
Represents either an error or a value T.
Definition: ErrorOr.h:56
llvm::StringRef::const_iterator
const char * const_iterator
Definition: StringRef.h:55
llvm::sys::getHostCPUName
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
Definition: Host.cpp:1563
llvm::sys::detail::getHostCPUNameForSPARC
StringRef getHostCPUNameForSPARC(StringRef ProcCpuinfoContent)
llvm::StringSwitch::Default
R Default(T Value)
Definition: StringSwitch.h:182
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
llvm::logicalview::LVOutputKind::Text
@ Text
StringMap.h
llvm::sys::detail::x86::getVendorSignature
VendorSignatures getVendorSignature(unsigned *MaxLeaf=nullptr)
Returns the host CPU's vendor.
Definition: Host.cpp:1569
raw_ostream.h
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:241
registers
Implement PPCInstrInfo::isLoadFromStackSlot isStoreToStackSlot for vector registers
Definition: README_ALTIVEC.txt:4
llvm::StringRef::begin
iterator begin() const
Definition: StringRef.h:111
llvm::StringRef::split
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:692
llvm::MachO::CPU_SUBTYPE_POWERPC_970
@ CPU_SUBTYPE_POWERPC_970
Definition: MachO.h:1661