LLVM 22.0.0git
Host.cpp
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1//===-- Host.cpp - Implement OS Host Detection ------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the operating system Host detection.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/TargetParser/Host.h"
14#include "llvm/ADT/Bitfields.h"
15#include "llvm/ADT/STLFunctionalExtras.h"
16#include "llvm/ADT/SmallVector.h"
17#include "llvm/ADT/StringExtras.h"
18#include "llvm/ADT/StringMap.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/ADT/StringSwitch.h"
21#include "llvm/Config/llvm-config.h"
22#include "llvm/Support/MemoryBuffer.h"
23#include "llvm/Support/raw_ostream.h"
24#include "llvm/TargetParser/RISCVTargetParser.h"
25#include "llvm/TargetParser/Triple.h"
26#include "llvm/TargetParser/X86TargetParser.h"
27#include <string.h>
28
29// Include the platform-specific parts of this class.
30#ifdef LLVM_ON_UNIX
31#include "Unix/Host.inc"
32#include <sched.h>
33#endif
34#ifdef _WIN32
35#include "Windows/Host.inc"
36#endif
37#ifdef _MSC_VER
38#include <intrin.h>
39#endif
40#ifdef __MVS__
41#include "llvm/Support/BCD.h"
42#endif
43#if defined(__APPLE__)
44#include <mach/host_info.h>
45#include <mach/mach.h>
46#include <mach/mach_host.h>
47#include <mach/machine.h>
48#include <sys/param.h>
49#include <sys/sysctl.h>
50#endif
51#ifdef _AIX
52#include <sys/systemcfg.h>
53#endif
54#if defined(__sun__) && defined(__svr4__)
55#include <kstat.h>
56#endif
57#if defined(__GNUC__) || defined(__clang__)
58#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)
59#include <cpuid.h>
60#endif
61#endif
62
63#define DEBUG_TYPE "host-detection"
64
65//===----------------------------------------------------------------------===//
66//
67// Implementations of the CPU detection routines
68//
69//===----------------------------------------------------------------------===//
70
71using namespace llvm;
72
73[[maybe_unused]] static std::unique_ptr<llvm::MemoryBuffer>
74getProcCpuinfoContent() {
75 const char *CPUInfoFile = "/proc/cpuinfo";
76 if (const char *CpuinfoIntercept = std::getenv("LLVM_CPUINFO"))
77 CPUInfoFile = CpuinfoIntercept;
78 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
79 llvm::MemoryBuffer::getFileAsStream(CPUInfoFile);
80
81 if (std::error_code EC = Text.getError()) {
82 llvm::errs() << "Can't read " << CPUInfoFile << ": " << EC.message()
83 << "\n";
84 return nullptr;
85 }
86 return std::move(*Text);
87}
88
89StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) {
90 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
91 // and so we must use an operating-system interface to determine the current
92 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
93 const char *generic = "generic";
94
95 // The cpu line is second (after the 'processor: 0' line), so if this
96 // buffer is too small then something has changed (or is wrong).
97 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
98 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
99
100 StringRef::const_iterator CIP = CPUInfoStart;
101
102 StringRef::const_iterator CPUStart = nullptr;
103 size_t CPULen = 0;
104
105 // We need to find the first line which starts with cpu, spaces, and a colon.
106 // After the colon, there may be some additional spaces and then the cpu type.
107 while (CIP < CPUInfoEnd && CPUStart == nullptr) {
108 if (CIP < CPUInfoEnd && *CIP == '\n')
109 ++CIP;
110
111 if (CIP < CPUInfoEnd && *CIP == 'c') {
112 ++CIP;
113 if (CIP < CPUInfoEnd && *CIP == 'p') {
114 ++CIP;
115 if (CIP < CPUInfoEnd && *CIP == 'u') {
116 ++CIP;
117 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
118 ++CIP;
119
120 if (CIP < CPUInfoEnd && *CIP == ':') {
121 ++CIP;
122 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
123 ++CIP;
124
125 if (CIP < CPUInfoEnd) {
126 CPUStart = CIP;
127 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
128 *CIP != ',' && *CIP != '\n'))
129 ++CIP;
130 CPULen = CIP - CPUStart;
131 }
132 }
133 }
134 }
135 }
136
137 if (CPUStart == nullptr)
138 while (CIP < CPUInfoEnd && *CIP != '\n')
139 ++CIP;
140 }
141
142 if (CPUStart == nullptr)
143 return generic;
144
145 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
146 .Case("604e", "604e")
147 .Case("604", "604")
148 .Case("7400", "7400")
149 .Case("7410", "7400")
150 .Case("7447", "7400")
151 .Case("7455", "7450")
152 .Case("G4", "g4")
153 .Case("POWER4", "970")
154 .Case("PPC970FX", "970")
155 .Case("PPC970MP", "970")
156 .Case("G5", "g5")
157 .Case("POWER5", "g5")
158 .Case("A2", "a2")
159 .Case("POWER6", "pwr6")
160 .Case("POWER7", "pwr7")
161 .Case("POWER8", "pwr8")
162 .Case("POWER8E", "pwr8")
163 .Case("POWER8NVL", "pwr8")
164 .Case("POWER9", "pwr9")
165 .Case("POWER10", "pwr10")
166 .Case("POWER11", "pwr11")
167 // FIXME: If we get a simulator or machine with the capabilities of
168 // mcpu=future, we should revisit this and add the name reported by the
169 // simulator/machine.
170 .Default(generic);
171}
172
173StringRef
174getHostCPUNameForARMFromComponents(StringRef Implementer, StringRef Hardware,
175 StringRef Part, ArrayRef<StringRef> Parts,
176 function_ref<unsigned()> GetVariant) {
177
178 auto MatchBigLittle = [](auto const &Parts, StringRef Big, StringRef Little) {
179 if (Parts.size() == 2)
180 return (Parts[0] == Big && Parts[1] == Little) ||
181 (Parts[1] == Big && Parts[0] == Little);
182 return false;
183 };
184
185 if (Implementer == "0x41") { // ARM Ltd.
186 // MSM8992/8994 may give cpu part for the core that the kernel is running on,
187 // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
188 if (Hardware.ends_with("MSM8994") || Hardware.ends_with("MSM8996"))
189 return "cortex-a53";
190
191 // Detect big.LITTLE systems.
192 if (MatchBigLittle(Parts, "0xd85", "0xd87"))
193 return "cortex-x925";
194
195 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
196 // values correspond to the "Part number" in the CP15/c0 register. The
197 // contents are specified in the various processor manuals.
198 // This corresponds to the Main ID Register in Technical Reference Manuals.
199 // and is used in programs like sys-utils
200 return StringSwitch<const char *>(Part)
201 .Case("0x926", "arm926ej-s")
202 .Case("0xb02", "mpcore")
203 .Case("0xb36", "arm1136j-s")
204 .Case("0xb56", "arm1156t2-s")
205 .Case("0xb76", "arm1176jz-s")
206 .Case("0xd8a", "c1-nano")
207 .Case("0xd90", "c1-premium")
208 .Case("0xd8b", "c1-pro")
209 .Case("0xd8c", "c1-ultra")
210 .Case("0xc05", "cortex-a5")
211 .Case("0xc07", "cortex-a7")
212 .Case("0xc08", "cortex-a8")
213 .Case("0xc09", "cortex-a9")
214 .Case("0xc0f", "cortex-a15")
215 .Case("0xc0e", "cortex-a17")
216 .Case("0xc20", "cortex-m0")
217 .Case("0xc23", "cortex-m3")
218 .Case("0xc24", "cortex-m4")
219 .Case("0xc27", "cortex-m7")
220 .Case("0xd20", "cortex-m23")
221 .Case("0xd21", "cortex-m33")
222 .Case("0xd24", "cortex-m52")
223 .Case("0xd22", "cortex-m55")
224 .Case("0xd23", "cortex-m85")
225 .Case("0xc18", "cortex-r8")
226 .Case("0xd13", "cortex-r52")
227 .Case("0xd16", "cortex-r52plus")
228 .Case("0xd15", "cortex-r82")
229 .Case("0xd14", "cortex-r82ae")
230 .Case("0xd02", "cortex-a34")
231 .Case("0xd04", "cortex-a35")
232 .Case("0xd8f", "cortex-a320")
233 .Case("0xd03", "cortex-a53")
234 .Case("0xd05", "cortex-a55")
235 .Case("0xd46", "cortex-a510")
236 .Case("0xd80", "cortex-a520")
237 .Case("0xd88", "cortex-a520ae")
238 .Case("0xd07", "cortex-a57")
239 .Case("0xd06", "cortex-a65")
240 .Case("0xd43", "cortex-a65ae")
241 .Case("0xd08", "cortex-a72")
242 .Case("0xd09", "cortex-a73")
243 .Case("0xd0a", "cortex-a75")
244 .Case("0xd0b", "cortex-a76")
245 .Case("0xd0e", "cortex-a76ae")
246 .Case("0xd0d", "cortex-a77")
247 .Case("0xd41", "cortex-a78")
248 .Case("0xd42", "cortex-a78ae")
249 .Case("0xd4b", "cortex-a78c")
250 .Case("0xd47", "cortex-a710")
251 .Case("0xd4d", "cortex-a715")
252 .Case("0xd81", "cortex-a720")
253 .Case("0xd89", "cortex-a720ae")
254 .Case("0xd87", "cortex-a725")
255 .Case("0xd44", "cortex-x1")
256 .Case("0xd4c", "cortex-x1c")
257 .Case("0xd48", "cortex-x2")
258 .Case("0xd4e", "cortex-x3")
259 .Case("0xd82", "cortex-x4")
260 .Case("0xd85", "cortex-x925")
261 .Case("0xd4a", "neoverse-e1")
262 .Case("0xd0c", "neoverse-n1")
263 .Case("0xd49", "neoverse-n2")
264 .Case("0xd8e", "neoverse-n3")
265 .Case("0xd40", "neoverse-v1")
266 .Case("0xd4f", "neoverse-v2")
267 .Case("0xd84", "neoverse-v3")
268 .Case("0xd83", "neoverse-v3ae")
269 .Default("generic");
270 }
271
272 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium.
273 return StringSwitch<const char *>(Part)
274 .Case("0x516", "thunderx2t99")
275 .Case("0x0516", "thunderx2t99")
276 .Case("0xaf", "thunderx2t99")
277 .Case("0x0af", "thunderx2t99")
278 .Case("0xa1", "thunderxt88")
279 .Case("0x0a1", "thunderxt88")
280 .Default("generic");
281 }
282
283 if (Implementer == "0x46") { // Fujitsu Ltd.
284 return StringSwitch<const char *>(Part)
285 .Case("0x001", "a64fx")
286 .Case("0x003", "fujitsu-monaka")
287 .Default("generic");
288 }
289
290 if (Implementer == "0x4e") { // NVIDIA Corporation
291 return StringSwitch<const char *>(Part)
292 .Case("0x004", "carmel")
293 .Case("0x10", "olympus")
294 .Case("0x010", "olympus")
295 .Default("generic");
296 }
297
298 if (Implementer == "0x48") // HiSilicon Technologies, Inc.
299 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
300 // values correspond to the "Part number" in the CP15/c0 register. The
301 // contents are specified in the various processor manuals.
302 return StringSwitch<const char *>(Part)
303 .Case("0xd01", "tsv110")
304 .Default("generic");
305
306 if (Implementer == "0x51") // Qualcomm Technologies, Inc.
307 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
308 // values correspond to the "Part number" in the CP15/c0 register. The
309 // contents are specified in the various processor manuals.
310 return StringSwitch<const char *>(Part)
311 .Case("0x06f", "krait") // APQ8064
312 .Case("0x201", "kryo")
313 .Case("0x205", "kryo")
314 .Case("0x211", "kryo")
315 .Case("0x800", "cortex-a73") // Kryo 2xx Gold
316 .Case("0x801", "cortex-a73") // Kryo 2xx Silver
317 .Case("0x802", "cortex-a75") // Kryo 3xx Gold
318 .Case("0x803", "cortex-a75") // Kryo 3xx Silver
319 .Case("0x804", "cortex-a76") // Kryo 4xx Gold
320 .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver
321 .Case("0xc00", "falkor")
322 .Case("0xc01", "saphira")
323 .Case("0x001", "oryon-1")
324 .Default("generic");
325 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
326 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
327 // any predictive pattern across variants and parts.
328
329 // Look for the CPU variant line, whose value is a 1 digit hexadecimal
330 // number, corresponding to the Variant bits in the CP15/C0 register.
331 unsigned Variant = GetVariant();
332
333 // Convert the CPU part line, whose value is a 3 digit hexadecimal number,
334 // corresponding to the PartNum bits in the CP15/C0 register.
335 unsigned PartAsInt;
336 Part.getAsInteger(0, PartAsInt);
337
338 unsigned Exynos = (Variant << 12) | PartAsInt;
339 switch (Exynos) {
340 default:
341 // Default by falling through to Exynos M3.
342 [[fallthrough]];
343 case 0x1002:
344 return "exynos-m3";
345 case 0x1003:
346 return "exynos-m4";
347 }
348 }
349
350 if (Implementer == "0x61") { // Apple
351 return StringSwitch<const char *>(Part)
352 .Case("0x020", "apple-m1")
353 .Case("0x021", "apple-m1")
354 .Case("0x022", "apple-m1")
355 .Case("0x023", "apple-m1")
356 .Case("0x024", "apple-m1")
357 .Case("0x025", "apple-m1")
358 .Case("0x028", "apple-m1")
359 .Case("0x029", "apple-m1")
360 .Case("0x030", "apple-m2")
361 .Case("0x031", "apple-m2")
362 .Case("0x032", "apple-m2")
363 .Case("0x033", "apple-m2")
364 .Case("0x034", "apple-m2")
365 .Case("0x035", "apple-m2")
366 .Case("0x038", "apple-m2")
367 .Case("0x039", "apple-m2")
368 .Case("0x049", "apple-m3")
369 .Case("0x048", "apple-m3")
370 .Default("generic");
371 }
372
373 if (Implementer == "0x63") { // Arm China.
374 return StringSwitch<const char *>(Part)
375 .Case("0x132", "star-mc1")
376 .Case("0xd25", "star-mc3")
377 .Default("generic");
378 }
379
380 if (Implementer == "0x6d") { // Microsoft Corporation.
381 // The Microsoft Azure Cobalt 100 CPU is handled as a Neoverse N2.
382 return StringSwitch<const char *>(Part)
383 .Case("0xd49", "neoverse-n2")
384 .Default("generic");
385 }
386
387 if (Implementer == "0xc0") { // Ampere Computing
388 return StringSwitch<const char *>(Part)
389 .Case("0xac3", "ampere1")
390 .Case("0xac4", "ampere1a")
391 .Case("0xac5", "ampere1b")
392 .Default("generic");
393 }
394
395 return "generic";
396}
397
398StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
399 // The cpuid register on arm is not accessible from user space. On Linux,
400 // it is exposed through the /proc/cpuinfo file.
401
402 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
403 // in all cases.
404 SmallVector<StringRef, 32> Lines;
405 ProcCpuinfoContent.split(Lines, '\n');
406
407 // Look for the CPU implementer and hardware lines, and store the CPU part
408 // numbers found.
409 StringRef Implementer;
410 StringRef Hardware;
411 SmallVector<StringRef, 32> Parts;
412 for (StringRef Line : Lines) {
413 if (Line.consume_front("CPU implementer"))
414 Implementer = Line.ltrim("\t :");
415 else if (Line.consume_front("Hardware"))
416 Hardware = Line.ltrim("\t :");
417 else if (Line.consume_front("CPU part"))
418 Parts.emplace_back(Line.ltrim("\t :"));
419 }
420
421 // Last `Part' seen, in case we don't analyse all `Parts' parsed.
422 StringRef Part = Parts.empty() ? StringRef() : Parts.back();
423
424 // Remove duplicate `Parts'.
425 llvm::sort(Parts);
426 Parts.erase(llvm::unique(Parts), Parts.end());
427
428 auto GetVariant = [&]() {
429 unsigned Variant = 0;
430 for (auto I : Lines)
431 if (I.consume_front("CPU variant"))
432 I.ltrim("\t :").getAsInteger(0, Variant);
433 return Variant;
434 };
435
436 return getHostCPUNameForARMFromComponents(Implementer, Hardware, Part, Parts,
437 GetVariant);
438}
439
440StringRef sys::detail::getHostCPUNameForARM(uint64_t PrimaryCpuInfo,
441 ArrayRef<uint64_t> UniqueCpuInfos) {
442 // On Windows, the registry provides cached copied of the MIDR_EL1 register.
443 using PartNum = Bitfield::Element<uint16_t, 4, 12>;
444 using Implementer = Bitfield::Element<uint16_t, 24, 8>;
445 using Variant = Bitfield::Element<uint16_t, 20, 4>;
446
447 SmallVector<std::string> PartsHolder;
448 PartsHolder.reserve(UniqueCpuInfos.size());
449 for (auto Info : UniqueCpuInfos)
450 PartsHolder.push_back("0x" + utohexstr(Bitfield::get<PartNum>(Info),
451 /*LowerCase*/ true,
452 /*Width*/ 3));
453
454 SmallVector<StringRef> Parts;
455 Parts.reserve(PartsHolder.size());
456 for (const auto &Part : PartsHolder)
457 Parts.push_back(Part);
458
459 return getHostCPUNameForARMFromComponents(
460 "0x" + utohexstr(Bitfield::get<Implementer>(PrimaryCpuInfo),
461 /*LowerCase*/ true,
462 /*Width*/ 2),
463 /*Hardware*/ "",
464 "0x" + utohexstr(Bitfield::get<PartNum>(PrimaryCpuInfo),
465 /*LowerCase*/ true,
466 /*Width*/ 3),
467 Parts, [=]() { return Bitfield::get<Variant>(PrimaryCpuInfo); });
468}
469
470namespace {
471StringRef getCPUNameFromS390Model(unsigned int Id, bool HaveVectorSupport) {
472 switch (Id) {
473 case 2064: // z900 not supported by LLVM
474 case 2066:
475 case 2084: // z990 not supported by LLVM
476 case 2086:
477 case 2094: // z9-109 not supported by LLVM
478 case 2096:
479 return "generic";
480 case 2097:
481 case 2098:
482 return "z10";
483 case 2817:
484 case 2818:
485 return "z196";
486 case 2827:
487 case 2828:
488 return "zEC12";
489 case 2964:
490 case 2965:
491 return HaveVectorSupport? "z13" : "zEC12";
492 case 3906:
493 case 3907:
494 return HaveVectorSupport? "z14" : "zEC12";
495 case 8561:
496 case 8562:
497 return HaveVectorSupport? "z15" : "zEC12";
498 case 3931:
499 case 3932:
500 return HaveVectorSupport? "z16" : "zEC12";
501 case 9175:
502 case 9176:
503 default:
504 return HaveVectorSupport? "z17" : "zEC12";
505 }
506}
507} // end anonymous namespace
508
509StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) {
510 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
511
512 // The "processor 0:" line comes after a fair amount of other information,
513 // including a cache breakdown, but this should be plenty.
514 SmallVector<StringRef, 32> Lines;
515 ProcCpuinfoContent.split(Lines, '\n');
516
517 // Look for the CPU features.
518 SmallVector<StringRef, 32> CPUFeatures;
519 for (StringRef Line : Lines)
520 if (Line.starts_with("features")) {
521 size_t Pos = Line.find(':');
522 if (Pos != StringRef::npos) {
523 Line.drop_front(Pos + 1).split(CPUFeatures, ' ');
524 break;
525 }
526 }
527
528 // We need to check for the presence of vector support independently of
529 // the machine type, since we may only use the vector register set when
530 // supported by the kernel (and hypervisor).
531 bool HaveVectorSupport = llvm::is_contained(CPUFeatures, "vx");
532
533 // Now check the processor machine type.
534 for (StringRef Line : Lines) {
535 if (Line.starts_with("processor ")) {
536 size_t Pos = Line.find("machine = ");
537 if (Pos != StringRef::npos) {
538 Pos += sizeof("machine = ") - 1;
539 unsigned int Id;
540 if (!Line.drop_front(Pos).getAsInteger(10, Id))
541 return getCPUNameFromS390Model(Id, HaveVectorSupport);
542 }
543 break;
544 }
545 }
546
547 return "generic";
548}
549
550StringRef sys::detail::getHostCPUNameForRISCV(StringRef ProcCpuinfoContent) {
551 // There are 24 lines in /proc/cpuinfo
552 SmallVector<StringRef> Lines;
553 ProcCpuinfoContent.split(Lines, '\n');
554
555 // Look for uarch line to determine cpu name
556 StringRef UArch;
557 for (StringRef Line : Lines) {
558 if (Line.starts_with("uarch")) {
559 UArch = Line.substr(5).ltrim("\t :");
560 break;
561 }
562 }
563
564 return StringSwitch<const char *>(UArch)
565 .Case("eswin,eic770x", "sifive-p550")
566 .Case("sifive,u74-mc", "sifive-u74")
567 .Case("sifive,bullet0", "sifive-u74")
568 .Default("");
569}
570
571StringRef sys::detail::getHostCPUNameForBPF() {
572#if !defined(__linux__) || !defined(__x86_64__)
573 return "generic";
574#else
575 uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
576 /* BPF_MOV64_IMM(BPF_REG_0, 0) */
577 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
578 /* BPF_MOV64_IMM(BPF_REG_2, 1) */
579 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
580 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
581 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
582 /* BPF_MOV64_IMM(BPF_REG_0, 1) */
583 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
584 /* BPF_EXIT_INSN() */
585 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
586
587 uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
588 /* BPF_MOV64_IMM(BPF_REG_0, 0) */
589 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
590 /* BPF_MOV64_IMM(BPF_REG_2, 1) */
591 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
592 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
593 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
594 /* BPF_MOV64_IMM(BPF_REG_0, 1) */
595 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
596 /* BPF_EXIT_INSN() */
597 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
598
599 struct bpf_prog_load_attr {
600 uint32_t prog_type;
601 uint32_t insn_cnt;
602 uint64_t insns;
603 uint64_t license;
604 uint32_t log_level;
605 uint32_t log_size;
606 uint64_t log_buf;
607 uint32_t kern_version;
608 uint32_t prog_flags;
609 } attr = {};
610 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
611 attr.insn_cnt = 5;
612 attr.insns = (uint64_t)v3_insns;
613 attr.license = (uint64_t)"DUMMY";
614
615 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr,
616 sizeof(attr));
617 if (fd >= 0) {
618 close(fd);
619 return "v3";
620 }
621
622 /* Clear the whole attr in case its content changed by syscall. */
623 memset(&attr, 0, sizeof(attr));
624 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
625 attr.insn_cnt = 5;
626 attr.insns = (uint64_t)v2_insns;
627 attr.license = (uint64_t)"DUMMY";
628 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
629 if (fd >= 0) {
630 close(fd);
631 return "v2";
632 }
633 return "v1";
634#endif
635}
636
637#if (defined(__i386__) || defined(_M_IX86) || defined(__x86_64__) || \
638 defined(_M_X64)) && \
639 !defined(_M_ARM64EC)
640
641/// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
642/// the specified arguments. If we can't run cpuid on the host, return true.
643static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
644 unsigned *rECX, unsigned *rEDX) {
645#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)
646 return !__get_cpuid(value, rEAX, rEBX, rECX, rEDX);
647#elif defined(_MSC_VER)
648 // The MSVC intrinsic is portable across x86 and x64.
649 int registers[4];
650 __cpuid(registers, value);
651 *rEAX = registers[0];
652 *rEBX = registers[1];
653 *rECX = registers[2];
654 *rEDX = registers[3];
655 return false;
656#else
657 return true;
658#endif
659}
660
661namespace llvm {
662namespace sys {
663namespace detail {
664namespace x86 {
665
666VendorSignatures getVendorSignature(unsigned *MaxLeaf) {
667 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
668 if (MaxLeaf == nullptr)
669 MaxLeaf = &EAX;
670 else
671 *MaxLeaf = 0;
672
673 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)
674 return VendorSignatures::UNKNOWN;
675
676 // "Genu ineI ntel"
677 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)
678 return VendorSignatures::GENUINE_INTEL;
679
680 // "Auth enti cAMD"
681 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
682 return VendorSignatures::AUTHENTIC_AMD;
683
684 return VendorSignatures::UNKNOWN;
685}
686
687} // namespace x86
688} // namespace detail
689} // namespace sys
690} // namespace llvm
691
692using namespace llvm::sys::detail::x86;
693
694/// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
695/// the 4 values in the specified arguments. If we can't run cpuid on the host,
696/// return true.
697static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
698 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
699 unsigned *rEDX) {
700 // TODO(boomanaiden154): When the minimum toolchain versions for gcc and clang
701 // are such that __cpuidex is defined within cpuid.h for both, we can remove
702 // the __get_cpuid_count function and share the MSVC implementation between
703 // all three.
704#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)
705 return !__get_cpuid_count(value, subleaf, rEAX, rEBX, rECX, rEDX);
706#elif defined(_MSC_VER)
707 int registers[4];
708 __cpuidex(registers, value, subleaf);
709 *rEAX = registers[0];
710 *rEBX = registers[1];
711 *rECX = registers[2];
712 *rEDX = registers[3];
713 return false;
714#else
715 return true;
716#endif
717}
718
719// Read control register 0 (XCR0). Used to detect features such as AVX.
720static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
721 // TODO(boomanaiden154): When the minimum toolchain versions for gcc and clang
722 // are such that _xgetbv is supported by both, we can unify the implementation
723 // with MSVC and remove all inline assembly.
724#if defined(__GNUC__) || defined(__clang__)
725 // Check xgetbv; this uses a .byte sequence instead of the instruction
726 // directly because older assemblers do not include support for xgetbv and
727 // there is no easy way to conditionally compile based on the assembler used.
728 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
729 return false;
730#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
731 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
732 *rEAX = Result;
733 *rEDX = Result >> 32;
734 return false;
735#else
736 return true;
737#endif
738}
739
740static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
741 unsigned *Model) {
742 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
743 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
744 if (*Family == 6 || *Family == 0xf) {
745 if (*Family == 0xf)
746 // Examine extended family ID if family ID is F.
747 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
748 // Examine extended model ID if family ID is 6 or F.
749 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
750 }
751}
752
753#define testFeature(F) (Features[F / 32] & (1 << (F % 32))) != 0
754
755static StringRef getIntelProcessorTypeAndSubtype(unsigned Family,
756 unsigned Model,
757 const unsigned *Features,
758 unsigned *Type,
759 unsigned *Subtype) {
760 StringRef CPU;
761
762 switch (Family) {
763 case 0x3:
764 CPU = "i386";
765 break;
766 case 0x4:
767 CPU = "i486";
768 break;
769 case 0x5:
770 if (testFeature(X86::FEATURE_MMX)) {
771 CPU = "pentium-mmx";
772 break;
773 }
774 CPU = "pentium";
775 break;
776 case 0x6:
777 switch (Model) {
778 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
779 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
780 // mobile processor, Intel Core 2 Extreme processor, Intel
781 // Pentium Dual-Core processor, Intel Xeon processor, model
782 // 0Fh. All processors are manufactured using the 65 nm process.
783 case 0x16: // Intel Celeron processor model 16h. All processors are
784 // manufactured using the 65 nm process
785 CPU = "core2";
786 *Type = X86::INTEL_CORE2;
787 break;
788 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
789 // 17h. All processors are manufactured using the 45 nm process.
790 //
791 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
792 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
793 // the 45 nm process.
794 CPU = "penryn";
795 *Type = X86::INTEL_CORE2;
796 break;
797 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
798 // processors are manufactured using the 45 nm process.
799 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
800 // As found in a Summer 2010 model iMac.
801 case 0x1f:
802 case 0x2e: // Nehalem EX
803 CPU = "nehalem";
804 *Type = X86::INTEL_COREI7;
805 *Subtype = X86::INTEL_COREI7_NEHALEM;
806 break;
807 case 0x25: // Intel Core i7, laptop version.
808 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
809 // processors are manufactured using the 32 nm process.
810 case 0x2f: // Westmere EX
811 CPU = "westmere";
812 *Type = X86::INTEL_COREI7;
813 *Subtype = X86::INTEL_COREI7_WESTMERE;
814 break;
815 case 0x2a: // Intel Core i7 processor. All processors are manufactured
816 // using the 32 nm process.
817 case 0x2d:
818 CPU = "sandybridge";
819 *Type = X86::INTEL_COREI7;
820 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
821 break;
822 case 0x3a:
823 case 0x3e: // Ivy Bridge EP
824 CPU = "ivybridge";
825 *Type = X86::INTEL_COREI7;
826 *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
827 break;
828
829 // Haswell:
830 case 0x3c:
831 case 0x3f:
832 case 0x45:
833 case 0x46:
834 CPU = "haswell";
835 *Type = X86::INTEL_COREI7;
836 *Subtype = X86::INTEL_COREI7_HASWELL;
837 break;
838
839 // Broadwell:
840 case 0x3d:
841 case 0x47:
842 case 0x4f:
843 case 0x56:
844 CPU = "broadwell";
845 *Type = X86::INTEL_COREI7;
846 *Subtype = X86::INTEL_COREI7_BROADWELL;
847 break;
848
849 // Skylake:
850 case 0x4e: // Skylake mobile
851 case 0x5e: // Skylake desktop
852 case 0x8e: // Kaby Lake mobile
853 case 0x9e: // Kaby Lake desktop
854 case 0xa5: // Comet Lake-H/S
855 case 0xa6: // Comet Lake-U
856 CPU = "skylake";
857 *Type = X86::INTEL_COREI7;
858 *Subtype = X86::INTEL_COREI7_SKYLAKE;
859 break;
860
861 // Rocketlake:
862 case 0xa7:
863 CPU = "rocketlake";
864 *Type = X86::INTEL_COREI7;
865 *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
866 break;
867
868 // Skylake Xeon:
869 case 0x55:
870 *Type = X86::INTEL_COREI7;
871 if (testFeature(X86::FEATURE_AVX512BF16)) {
872 CPU = "cooperlake";
873 *Subtype = X86::INTEL_COREI7_COOPERLAKE;
874 } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
875 CPU = "cascadelake";
876 *Subtype = X86::INTEL_COREI7_CASCADELAKE;
877 } else {
878 CPU = "skylake-avx512";
879 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
880 }
881 break;
882
883 // Cannonlake:
884 case 0x66:
885 CPU = "cannonlake";
886 *Type = X86::INTEL_COREI7;
887 *Subtype = X86::INTEL_COREI7_CANNONLAKE;
888 break;
889
890 // Icelake:
891 case 0x7d:
892 case 0x7e:
893 CPU = "icelake-client";
894 *Type = X86::INTEL_COREI7;
895 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
896 break;
897
898 // Tigerlake:
899 case 0x8c:
900 case 0x8d:
901 CPU = "tigerlake";
902 *Type = X86::INTEL_COREI7;
903 *Subtype = X86::INTEL_COREI7_TIGERLAKE;
904 break;
905
906 // Alderlake:
907 case 0x97:
908 case 0x9a:
909 CPU = "alderlake";
910 *Type = X86::INTEL_COREI7;
911 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
912 break;
913
914 // Gracemont
915 case 0xbe:
916 CPU = "gracemont";
917 *Type = X86::INTEL_COREI7;
918 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
919 break;
920
921 // Raptorlake:
922 case 0xb7:
923 case 0xba:
924 case 0xbf:
925 CPU = "raptorlake";
926 *Type = X86::INTEL_COREI7;
927 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
928 break;
929
930 // Meteorlake:
931 case 0xaa:
932 case 0xac:
933 CPU = "meteorlake";
934 *Type = X86::INTEL_COREI7;
935 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
936 break;
937
938 // Arrowlake:
939 case 0xc5:
940 // Arrowlake U:
941 case 0xb5:
942 CPU = "arrowlake";
943 *Type = X86::INTEL_COREI7;
944 *Subtype = X86::INTEL_COREI7_ARROWLAKE;
945 break;
946
947 // Arrowlake S:
948 case 0xc6:
949 CPU = "arrowlake-s";
950 *Type = X86::INTEL_COREI7;
951 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
952 break;
953
954 // Lunarlake:
955 case 0xbd:
956 CPU = "lunarlake";
957 *Type = X86::INTEL_COREI7;
958 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
959 break;
960
961 // Pantherlake:
962 case 0xcc:
963 CPU = "pantherlake";
964 *Type = X86::INTEL_COREI7;
965 *Subtype = X86::INTEL_COREI7_PANTHERLAKE;
966 break;
967
968 // Wildcatlake:
969 case 0xd5:
970 CPU = "wildcatlake";
971 *Type = X86::INTEL_COREI7;
972 *Subtype = X86::INTEL_COREI7_PANTHERLAKE;
973 break;
974
975 // Graniterapids:
976 case 0xad:
977 CPU = "graniterapids";
978 *Type = X86::INTEL_COREI7;
979 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
980 break;
981
982 // Granite Rapids D:
983 case 0xae:
984 CPU = "graniterapids-d";
985 *Type = X86::INTEL_COREI7;
986 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
987 break;
988
989 // Icelake Xeon:
990 case 0x6a:
991 case 0x6c:
992 CPU = "icelake-server";
993 *Type = X86::INTEL_COREI7;
994 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
995 break;
996
997 // Emerald Rapids:
998 case 0xcf:
999 CPU = "emeraldrapids";
1000 *Type = X86::INTEL_COREI7;
1001 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
1002 break;
1003
1004 // Sapphire Rapids:
1005 case 0x8f:
1006 CPU = "sapphirerapids";
1007 *Type = X86::INTEL_COREI7;
1008 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
1009 break;
1010
1011 case 0x1c: // Most 45 nm Intel Atom processors
1012 case 0x26: // 45 nm Atom Lincroft
1013 case 0x27: // 32 nm Atom Medfield
1014 case 0x35: // 32 nm Atom Midview
1015 case 0x36: // 32 nm Atom Midview
1016 CPU = "bonnell";
1017 *Type = X86::INTEL_BONNELL;
1018 break;
1019
1020 // Atom Silvermont codes from the Intel software optimization guide.
1021 case 0x37:
1022 case 0x4a:
1023 case 0x4d:
1024 case 0x5a:
1025 case 0x5d:
1026 case 0x4c: // really airmont
1027 CPU = "silvermont";
1028 *Type = X86::INTEL_SILVERMONT;
1029 break;
1030 // Goldmont:
1031 case 0x5c: // Apollo Lake
1032 case 0x5f: // Denverton
1033 CPU = "goldmont";
1034 *Type = X86::INTEL_GOLDMONT;
1035 break;
1036 case 0x7a:
1037 CPU = "goldmont-plus";
1038 *Type = X86::INTEL_GOLDMONT_PLUS;
1039 break;
1040 case 0x86:
1041 case 0x8a: // Lakefield
1042 case 0x96: // Elkhart Lake
1043 case 0x9c: // Jasper Lake
1044 CPU = "tremont";
1045 *Type = X86::INTEL_TREMONT;
1046 break;
1047
1048 // Sierraforest:
1049 case 0xaf:
1050 CPU = "sierraforest";
1051 *Type = X86::INTEL_SIERRAFOREST;
1052 break;
1053
1054 // Grandridge:
1055 case 0xb6:
1056 CPU = "grandridge";
1057 *Type = X86::INTEL_GRANDRIDGE;
1058 break;
1059
1060 // Clearwaterforest:
1061 case 0xdd:
1062 CPU = "clearwaterforest";
1063 *Type = X86::INTEL_CLEARWATERFOREST;
1064 break;
1065
1066 // Xeon Phi (Knights Landing + Knights Mill):
1067 case 0x57:
1068 CPU = "knl";
1069 *Type = X86::INTEL_KNL;
1070 break;
1071 case 0x85:
1072 CPU = "knm";
1073 *Type = X86::INTEL_KNM;
1074 break;
1075
1076 default: // Unknown family 6 CPU, try to guess.
1077 // Don't both with Type/Subtype here, they aren't used by the caller.
1078 // They're used above to keep the code in sync with compiler-rt.
1079 // TODO detect tigerlake host from model
1080 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
1081 CPU = "tigerlake";
1082 } else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
1083 CPU = "icelake-client";
1084 } else if (testFeature(X86::FEATURE_AVX512VBMI)) {
1085 CPU = "cannonlake";
1086 } else if (testFeature(X86::FEATURE_AVX512BF16)) {
1087 CPU = "cooperlake";
1088 } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
1089 CPU = "cascadelake";
1090 } else if (testFeature(X86::FEATURE_AVX512VL)) {
1091 CPU = "skylake-avx512";
1092 } else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
1093 if (testFeature(X86::FEATURE_SHA))
1094 CPU = "goldmont";
1095 else
1096 CPU = "skylake";
1097 } else if (testFeature(X86::FEATURE_ADX)) {
1098 CPU = "broadwell";
1099 } else if (testFeature(X86::FEATURE_AVX2)) {
1100 CPU = "haswell";
1101 } else if (testFeature(X86::FEATURE_AVX)) {
1102 CPU = "sandybridge";
1103 } else if (testFeature(X86::FEATURE_SSE4_2)) {
1104 if (testFeature(X86::FEATURE_MOVBE))
1105 CPU = "silvermont";
1106 else
1107 CPU = "nehalem";
1108 } else if (testFeature(X86::FEATURE_SSE4_1)) {
1109 CPU = "penryn";
1110 } else if (testFeature(X86::FEATURE_SSSE3)) {
1111 if (testFeature(X86::FEATURE_MOVBE))
1112 CPU = "bonnell";
1113 else
1114 CPU = "core2";
1115 } else if (testFeature(X86::FEATURE_64BIT)) {
1116 CPU = "core2";
1117 } else if (testFeature(X86::FEATURE_SSE3)) {
1118 CPU = "yonah";
1119 } else if (testFeature(X86::FEATURE_SSE2)) {
1120 CPU = "pentium-m";
1121 } else if (testFeature(X86::FEATURE_SSE)) {
1122 CPU = "pentium3";
1123 } else if (testFeature(X86::FEATURE_MMX)) {
1124 CPU = "pentium2";
1125 } else {
1126 CPU = "pentiumpro";
1127 }
1128 break;
1129 }
1130 break;
1131 case 0xf: {
1132 if (testFeature(X86::FEATURE_64BIT)) {
1133 CPU = "nocona";
1134 break;
1135 }
1136 if (testFeature(X86::FEATURE_SSE3)) {
1137 CPU = "prescott";
1138 break;
1139 }
1140 CPU = "pentium4";
1141 break;
1142 }
1143 case 0x13:
1144 switch (Model) {
1145 // Diamond Rapids:
1146 case 0x01:
1147 CPU = "diamondrapids";
1148 *Type = X86::INTEL_COREI7;
1149 *Subtype = X86::INTEL_COREI7_DIAMONDRAPIDS;
1150 break;
1151
1152 default: // Unknown family 19 CPU.
1153 break;
1154 }
1155 break;
1156 case 0x12:
1157 switch (Model) {
1158 // Novalake:
1159 case 0x1:
1160 case 0x3:
1161 CPU = "novalake";
1162 *Type = X86::INTEL_COREI7;
1163 *Subtype = X86::INTEL_COREI7_NOVALAKE;
1164 break;
1165 default: // Unknown family 0x12 CPU.
1166 break;
1167 }
1168 break;
1169
1170 default:
1171 break; // Unknown.
1172 }
1173
1174 return CPU;
1175}
1176
1177static const char *getAMDProcessorTypeAndSubtype(unsigned Family,
1178 unsigned Model,
1179 const unsigned *Features,
1180 unsigned *Type,
1181 unsigned *Subtype) {
1182 const char *CPU = nullptr;
1183
1184 switch (Family) {
1185 case 4:
1186 CPU = "i486";
1187 break;
1188 case 5:
1189 CPU = "pentium";
1190 switch (Model) {
1191 case 6:
1192 case 7:
1193 CPU = "k6";
1194 break;
1195 case 8:
1196 CPU = "k6-2";
1197 break;
1198 case 9:
1199 case 13:
1200 CPU = "k6-3";
1201 break;
1202 case 10:
1203 CPU = "geode";
1204 break;
1205 }
1206 break;
1207 case 6:
1208 if (testFeature(X86::FEATURE_SSE)) {
1209 CPU = "athlon-xp";
1210 break;
1211 }
1212 CPU = "athlon";
1213 break;
1214 case 15:
1215 if (testFeature(X86::FEATURE_SSE3)) {
1216 CPU = "k8-sse3";
1217 break;
1218 }
1219 CPU = "k8";
1220 break;
1221 case 16:
1222 case 18:
1223 CPU = "amdfam10";
1224 *Type = X86::AMDFAM10H; // "amdfam10"
1225 switch (Model) {
1226 case 2:
1227 *Subtype = X86::AMDFAM10H_BARCELONA;
1228 break;
1229 case 4:
1230 *Subtype = X86::AMDFAM10H_SHANGHAI;
1231 break;
1232 case 8:
1233 *Subtype = X86::AMDFAM10H_ISTANBUL;
1234 break;
1235 }
1236 break;
1237 case 20:
1238 CPU = "btver1";
1239 *Type = X86::AMD_BTVER1;
1240 break;
1241 case 21:
1242 CPU = "bdver1";
1243 *Type = X86::AMDFAM15H;
1244 if (Model >= 0x60 && Model <= 0x7f) {
1245 CPU = "bdver4";
1246 *Subtype = X86::AMDFAM15H_BDVER4;
1247 break; // 60h-7Fh: Excavator
1248 }
1249 if (Model >= 0x30 && Model <= 0x3f) {
1250 CPU = "bdver3";
1251 *Subtype = X86::AMDFAM15H_BDVER3;
1252 break; // 30h-3Fh: Steamroller
1253 }
1254 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
1255 CPU = "bdver2";
1256 *Subtype = X86::AMDFAM15H_BDVER2;
1257 break; // 02h, 10h-1Fh: Piledriver
1258 }
1259 if (Model <= 0x0f) {
1260 *Subtype = X86::AMDFAM15H_BDVER1;
1261 break; // 00h-0Fh: Bulldozer
1262 }
1263 break;
1264 case 22:
1265 CPU = "btver2";
1266 *Type = X86::AMD_BTVER2;
1267 break;
1268 case 23:
1269 CPU = "znver1";
1270 *Type = X86::AMDFAM17H;
1271 if ((Model >= 0x30 && Model <= 0x3f) || (Model == 0x47) ||
1272 (Model >= 0x60 && Model <= 0x67) || (Model >= 0x68 && Model <= 0x6f) ||
1273 (Model >= 0x70 && Model <= 0x7f) || (Model >= 0x84 && Model <= 0x87) ||
1274 (Model >= 0x90 && Model <= 0x97) || (Model >= 0x98 && Model <= 0x9f) ||
1275 (Model >= 0xa0 && Model <= 0xaf)) {
1276 // Family 17h Models 30h-3Fh (Starship) Zen 2
1277 // Family 17h Models 47h (Cardinal) Zen 2
1278 // Family 17h Models 60h-67h (Renoir) Zen 2
1279 // Family 17h Models 68h-6Fh (Lucienne) Zen 2
1280 // Family 17h Models 70h-7Fh (Matisse) Zen 2
1281 // Family 17h Models 84h-87h (ProjectX) Zen 2
1282 // Family 17h Models 90h-97h (VanGogh) Zen 2
1283 // Family 17h Models 98h-9Fh (Mero) Zen 2
1284 // Family 17h Models A0h-AFh (Mendocino) Zen 2
1285 CPU = "znver2";
1286 *Subtype = X86::AMDFAM17H_ZNVER2;
1287 break;
1288 }
1289 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x20 && Model <= 0x2f)) {
1290 // Family 17h Models 10h-1Fh (Raven1) Zen
1291 // Family 17h Models 10h-1Fh (Picasso) Zen+
1292 // Family 17h Models 20h-2Fh (Raven2 x86) Zen
1293 *Subtype = X86::AMDFAM17H_ZNVER1;
1294 break;
1295 }
1296 break;
1297 case 25:
1298 CPU = "znver3";
1299 *Type = X86::AMDFAM19H;
1300 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x2f) ||
1301 (Model >= 0x30 && Model <= 0x3f) || (Model >= 0x40 && Model <= 0x4f) ||
1302 (Model >= 0x50 && Model <= 0x5f)) {
1303 // Family 19h Models 00h-0Fh (Genesis, Chagall) Zen 3
1304 // Family 19h Models 20h-2Fh (Vermeer) Zen 3
1305 // Family 19h Models 30h-3Fh (Badami) Zen 3
1306 // Family 19h Models 40h-4Fh (Rembrandt) Zen 3+
1307 // Family 19h Models 50h-5Fh (Cezanne) Zen 3
1308 *Subtype = X86::AMDFAM19H_ZNVER3;
1309 break;
1310 }
1311 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x60 && Model <= 0x6f) ||
1312 (Model >= 0x70 && Model <= 0x77) || (Model >= 0x78 && Model <= 0x7f) ||
1313 (Model >= 0xa0 && Model <= 0xaf)) {
1314 // Family 19h Models 10h-1Fh (Stones; Storm Peak) Zen 4
1315 // Family 19h Models 60h-6Fh (Raphael) Zen 4
1316 // Family 19h Models 70h-77h (Phoenix, Hawkpoint1) Zen 4
1317 // Family 19h Models 78h-7Fh (Phoenix 2, Hawkpoint2) Zen 4
1318 // Family 19h Models A0h-AFh (Stones-Dense) Zen 4
1319 CPU = "znver4";
1320 *Subtype = X86::AMDFAM19H_ZNVER4;
1321 break; // "znver4"
1322 }
1323 break; // family 19h
1324 case 26:
1325 CPU = "znver5";
1326 *Type = X86::AMDFAM1AH;
1327 if (Model <= 0x4f || (Model >= 0x60 && Model <= 0x77) ||
1328 (Model >= 0xd0 && Model <= 0xd7)) {
1329 // Models 00h-0Fh (Breithorn).
1330 // Models 10h-1Fh (Breithorn-Dense).
1331 // Models 20h-2Fh (Strix 1).
1332 // Models 30h-37h (Strix 2).
1333 // Models 38h-3Fh (Strix 3).
1334 // Models 40h-4Fh (Granite Ridge).
1335 // Models 60h-6Fh (Krackan1).
1336 // Models 70h-77h (Sarlak).
1337 // Models D0h-D7h (Annapurna).
1338 CPU = "znver5";
1339 *Subtype = X86::AMDFAM1AH_ZNVER5;
1340 break; // "znver5"
1341 }
1342 break;
1343
1344 default:
1345 break; // Unknown AMD CPU.
1346 }
1347
1348 return CPU;
1349}
1350
1351#undef testFeature
1352
1353static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
1354 unsigned *Features) {
1355 unsigned EAX, EBX;
1356
1357 auto setFeature = [&](unsigned F) {
1358 Features[F / 32] |= 1U << (F % 32);
1359 };
1360
1361 if ((EDX >> 15) & 1)
1362 setFeature(X86::FEATURE_CMOV);
1363 if ((EDX >> 23) & 1)
1364 setFeature(X86::FEATURE_MMX);
1365 if ((EDX >> 25) & 1)
1366 setFeature(X86::FEATURE_SSE);
1367 if ((EDX >> 26) & 1)
1368 setFeature(X86::FEATURE_SSE2);
1369
1370 if ((ECX >> 0) & 1)
1371 setFeature(X86::FEATURE_SSE3);
1372 if ((ECX >> 1) & 1)
1373 setFeature(X86::FEATURE_PCLMUL);
1374 if ((ECX >> 9) & 1)
1375 setFeature(X86::FEATURE_SSSE3);
1376 if ((ECX >> 12) & 1)
1377 setFeature(X86::FEATURE_FMA);
1378 if ((ECX >> 19) & 1)
1379 setFeature(X86::FEATURE_SSE4_1);
1380 if ((ECX >> 20) & 1) {
1381 setFeature(X86::FEATURE_SSE4_2);
1382 setFeature(X86::FEATURE_CRC32);
1383 }
1384 if ((ECX >> 23) & 1)
1385 setFeature(X86::FEATURE_POPCNT);
1386 if ((ECX >> 25) & 1)
1387 setFeature(X86::FEATURE_AES);
1388
1389 if ((ECX >> 22) & 1)
1390 setFeature(X86::FEATURE_MOVBE);
1391
1392 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1393 // indicates that the AVX registers will be saved and restored on context
1394 // switch, then we have full AVX support.
1395 const unsigned AVXBits = (1 << 27) | (1 << 28);
1396 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1397 ((EAX & 0x6) == 0x6);
1398#if defined(__APPLE__)
1399 // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1400 // save the AVX512 context if we use AVX512 instructions, even the bit is not
1401 // set right now.
1402 bool HasAVX512Save = true;
1403#else
1404 // AVX512 requires additional context to be saved by the OS.
1405 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
1406#endif
1407
1408 if (HasAVX)
1409 setFeature(X86::FEATURE_AVX);
1410
1411 bool HasLeaf7 =
1412 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1413
1414 if (HasLeaf7 && ((EBX >> 3) & 1))
1415 setFeature(X86::FEATURE_BMI);
1416 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1417 setFeature(X86::FEATURE_AVX2);
1418 if (HasLeaf7 && ((EBX >> 8) & 1))
1419 setFeature(X86::FEATURE_BMI2);
1420 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) {
1421 setFeature(X86::FEATURE_AVX512F);
1422 }
1423 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1424 setFeature(X86::FEATURE_AVX512DQ);
1425 if (HasLeaf7 && ((EBX >> 19) & 1))
1426 setFeature(X86::FEATURE_ADX);
1427 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1428 setFeature(X86::FEATURE_AVX512IFMA);
1429 if (HasLeaf7 && ((EBX >> 23) & 1))
1430 setFeature(X86::FEATURE_CLFLUSHOPT);
1431 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1432 setFeature(X86::FEATURE_AVX512CD);
1433 if (HasLeaf7 && ((EBX >> 29) & 1))
1434 setFeature(X86::FEATURE_SHA);
1435 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1436 setFeature(X86::FEATURE_AVX512BW);
1437 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1438 setFeature(X86::FEATURE_AVX512VL);
1439
1440 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1441 setFeature(X86::FEATURE_AVX512VBMI);
1442 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1443 setFeature(X86::FEATURE_AVX512VBMI2);
1444 if (HasLeaf7 && ((ECX >> 8) & 1))
1445 setFeature(X86::FEATURE_GFNI);
1446 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1447 setFeature(X86::FEATURE_VPCLMULQDQ);
1448 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1449 setFeature(X86::FEATURE_AVX512VNNI);
1450 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1451 setFeature(X86::FEATURE_AVX512BITALG);
1452 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1453 setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1454
1455 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1456 setFeature(X86::FEATURE_AVX5124VNNIW);
1457 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1458 setFeature(X86::FEATURE_AVX5124FMAPS);
1459 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1460 setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1461
1462 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't
1463 // return all 0s for invalid subleaves so check the limit.
1464 bool HasLeaf7Subleaf1 =
1465 HasLeaf7 && EAX >= 1 &&
1466 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1467 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1468 setFeature(X86::FEATURE_AVX512BF16);
1469
1470 unsigned MaxExtLevel;
1471 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1472
1473 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1474 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1475 if (HasExtLeaf1 && ((ECX >> 6) & 1))
1476 setFeature(X86::FEATURE_SSE4_A);
1477 if (HasExtLeaf1 && ((ECX >> 11) & 1))
1478 setFeature(X86::FEATURE_XOP);
1479 if (HasExtLeaf1 && ((ECX >> 16) & 1))
1480 setFeature(X86::FEATURE_FMA4);
1481
1482 if (HasExtLeaf1 && ((EDX >> 29) & 1))
1483 setFeature(X86::FEATURE_64BIT);
1484}
1485
1486StringRef sys::getHostCPUName() {
1487 unsigned MaxLeaf = 0;
1488 const VendorSignatures Vendor = getVendorSignature(&MaxLeaf);
1489 if (Vendor == VendorSignatures::UNKNOWN)
1490 return "generic";
1491
1492 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1493 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1494
1495 unsigned Family = 0, Model = 0;
1496 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0};
1497 detectX86FamilyModel(EAX, &Family, &Model);
1498 getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1499
1500 // These aren't consumed in this file, but we try to keep some source code the
1501 // same or similar to compiler-rt.
1502 unsigned Type = 0;
1503 unsigned Subtype = 0;
1504
1505 StringRef CPU;
1506
1507 if (Vendor == VendorSignatures::GENUINE_INTEL) {
1508 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type,
1509 &Subtype);
1510 } else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
1511 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type,
1512 &Subtype);
1513 }
1514
1515 if (!CPU.empty())
1516 return CPU;
1517
1518 return "generic";
1519}
1520
1521#elif defined(_M_ARM64) || defined(_M_ARM64EC)
1522
1523StringRef sys::getHostCPUName() {
1524 constexpr char CentralProcessorKeyName[] =
1525 "HARDWARE\\DESCRIPTION\\System\\CentralProcessor";
1526 // Sub keys names are simple numbers ("0", "1", etc.) so 10 chars should be
1527 // enough for the slash and name.
1528 constexpr size_t SubKeyNameMaxSize = ARRAYSIZE(CentralProcessorKeyName) + 10;
1529
1530 SmallVector<uint64_t> Values;
1531 uint64_t PrimaryCpuInfo;
1532 char PrimaryPartKeyName[SubKeyNameMaxSize];
1533 DWORD PrimaryPartKeyNameSize = 0;
1534 HKEY CentralProcessorKey;
1535 if (RegOpenKeyExA(HKEY_LOCAL_MACHINE, CentralProcessorKeyName, 0, KEY_READ,
1536 &CentralProcessorKey) == ERROR_SUCCESS) {
1537 for (unsigned Index = 0; Index < UINT32_MAX; ++Index) {
1538 char SubKeyName[SubKeyNameMaxSize];
1539 DWORD SubKeySize = SubKeyNameMaxSize;
1540 HKEY SubKey;
1541 if ((RegEnumKeyExA(CentralProcessorKey, Index, SubKeyName, &SubKeySize,
1542 nullptr, nullptr, nullptr,
1543 nullptr) == ERROR_SUCCESS) &&
1544 (RegOpenKeyExA(CentralProcessorKey, SubKeyName, 0, KEY_READ,
1545 &SubKey) == ERROR_SUCCESS)) {
1546 // The "CP 4000" registry key contains a cached copy of the MIDR_EL1
1547 // register.
1548 uint64_t RegValue;
1549 DWORD ActualType;
1550 DWORD RegValueSize = sizeof(RegValue);
1551 if ((RegQueryValueExA(SubKey, "CP 4000", nullptr, &ActualType,
1552 (PBYTE)&RegValue,
1553 &RegValueSize) == ERROR_SUCCESS) &&
1554 (ActualType == REG_QWORD) && RegValueSize == sizeof(RegValue)) {
1555 // Assume that the part with the "highest" reg key name is the primary
1556 // part (to match the way that Linux's cpuinfo is written). Win32
1557 // makes no guarantees about the order of sub keys, so we have to
1558 // compare the names.
1559 if (PrimaryPartKeyNameSize < SubKeySize ||
1560 (PrimaryPartKeyNameSize == SubKeySize &&
1561 ::memcmp(SubKeyName, PrimaryPartKeyName, SubKeySize) > 0)) {
1562 PrimaryCpuInfo = RegValue;
1563 ::memcpy(PrimaryPartKeyName, SubKeyName, SubKeySize + 1);
1564 PrimaryPartKeyNameSize = SubKeySize;
1565 }
1566 if (!llvm::is_contained(Values, RegValue)) {
1567 Values.push_back(RegValue);
1568 }
1569 }
1570 RegCloseKey(SubKey);
1571 } else {
1572 // No more sub keys.
1573 break;
1574 }
1575 }
1576 RegCloseKey(CentralProcessorKey);
1577 }
1578
1579 if (Values.empty()) {
1580 return "generic";
1581 }
1582
1583 // Win32 makes no guarantees about the order of sub keys, so sort to ensure
1584 // reproducibility.
1585 llvm::sort(Values);
1586
1587 return detail::getHostCPUNameForARM(PrimaryCpuInfo, Values);
1588}
1589
1590#elif defined(__APPLE__) && defined(__powerpc__)
1591StringRef sys::getHostCPUName() {
1592 host_basic_info_data_t hostInfo;
1593 mach_msg_type_number_t infoCount;
1594
1595 infoCount = HOST_BASIC_INFO_COUNT;
1596 mach_port_t hostPort = mach_host_self();
1597 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1598 &infoCount);
1599 mach_port_deallocate(mach_task_self(), hostPort);
1600
1601 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1602 return "generic";
1603
1604 switch (hostInfo.cpu_subtype) {
1605 case CPU_SUBTYPE_POWERPC_601:
1606 return "601";
1607 case CPU_SUBTYPE_POWERPC_602:
1608 return "602";
1609 case CPU_SUBTYPE_POWERPC_603:
1610 return "603";
1611 case CPU_SUBTYPE_POWERPC_603e:
1612 return "603e";
1613 case CPU_SUBTYPE_POWERPC_603ev:
1614 return "603ev";
1615 case CPU_SUBTYPE_POWERPC_604:
1616 return "604";
1617 case CPU_SUBTYPE_POWERPC_604e:
1618 return "604e";
1619 case CPU_SUBTYPE_POWERPC_620:
1620 return "620";
1621 case CPU_SUBTYPE_POWERPC_750:
1622 return "750";
1623 case CPU_SUBTYPE_POWERPC_7400:
1624 return "7400";
1625 case CPU_SUBTYPE_POWERPC_7450:
1626 return "7450";
1627 case CPU_SUBTYPE_POWERPC_970:
1628 return "970";
1629 default:;
1630 }
1631
1632 return "generic";
1633}
1634#elif defined(__linux__) && defined(__powerpc__)
1635StringRef sys::getHostCPUName() {
1636 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1637 StringRef Content = P ? P->getBuffer() : "";
1638 return detail::getHostCPUNameForPowerPC(Content);
1639}
1640#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1641StringRef sys::getHostCPUName() {
1642 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1643 StringRef Content = P ? P->getBuffer() : "";
1644 return detail::getHostCPUNameForARM(Content);
1645}
1646#elif defined(__linux__) && defined(__s390x__)
1647StringRef sys::getHostCPUName() {
1648 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1649 StringRef Content = P ? P->getBuffer() : "";
1650 return detail::getHostCPUNameForS390x(Content);
1651}
1652#elif defined(__MVS__)
1653StringRef sys::getHostCPUName() {
1654 // Get pointer to Communications Vector Table (CVT).
1655 // The pointer is located at offset 16 of the Prefixed Save Area (PSA).
1656 // It is stored as 31 bit pointer and will be zero-extended to 64 bit.
1657 int *StartToCVTOffset = reinterpret_cast<int *>(0x10);
1658 // Since its stored as a 31-bit pointer, get the 4 bytes from the start
1659 // of address.
1660 int ReadValue = *StartToCVTOffset;
1661 // Explicitly clear the high order bit.
1662 ReadValue = (ReadValue & 0x7FFFFFFF);
1663 char *CVT = reinterpret_cast<char *>(ReadValue);
1664 // The model number is located in the CVT prefix at offset -6 and stored as
1665 // signless packed decimal.
1666 uint16_t Id = *(uint16_t *)&CVT[-6];
1667 // Convert number to integer.
1668 Id = decodePackedBCD<uint16_t>(Id, false);
1669 // Check for vector support. It's stored in field CVTFLAG5 (offset 244),
1670 // bit CVTVEF (X'80'). The facilities list is part of the PSA but the vector
1671 // extension can only be used if bit CVTVEF is on.
1672 bool HaveVectorSupport = CVT[244] & 0x80;
1673 return getCPUNameFromS390Model(Id, HaveVectorSupport);
1674}
1675#elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
1676// Copied from <mach/machine.h> in the macOS SDK.
1677//
1678// Also available here, though usually not as up-to-date:
1679// https://github.com/apple-oss-distributions/xnu/blob/xnu-11215.41.3/osfmk/mach/machine.h#L403-L452.
1680#define CPUFAMILY_UNKNOWN 0
1681#define CPUFAMILY_ARM_9 0xe73283ae
1682#define CPUFAMILY_ARM_11 0x8ff620d8
1683#define CPUFAMILY_ARM_XSCALE 0x53b005f5
1684#define CPUFAMILY_ARM_12 0xbd1b0ae9
1685#define CPUFAMILY_ARM_13 0x0cc90e64
1686#define CPUFAMILY_ARM_14 0x96077ef1
1687#define CPUFAMILY_ARM_15 0xa8511bca
1688#define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1689#define CPUFAMILY_ARM_CYCLONE 0x37a09642
1690#define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1691#define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1692#define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1693#define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1694#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1695#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1696#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1697#define CPUFAMILY_ARM_BLIZZARD_AVALANCHE 0xda33d83d
1698#define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765edea
1699#define CPUFAMILY_ARM_IBIZA 0xfa33415e
1700#define CPUFAMILY_ARM_PALMA 0x72015832
1701#define CPUFAMILY_ARM_COLL 0x2876f5b5
1702#define CPUFAMILY_ARM_LOBOS 0x5f4dea93
1703#define CPUFAMILY_ARM_DONAN 0x6f5129ac
1704#define CPUFAMILY_ARM_BRAVA 0x17d5b93a
1705#define CPUFAMILY_ARM_TAHITI 0x75d4acb9
1706#define CPUFAMILY_ARM_TUPAI 0x204526d0
1707
1708StringRef sys::getHostCPUName() {
1709 uint32_t Family;
1710 size_t Length = sizeof(Family);
1711 sysctlbyname("hw.cpufamily", &Family, &Length, NULL, 0);
1712
1713 // This is found by testing on actual hardware, and by looking at:
1714 // https://github.com/apple-oss-distributions/xnu/blob/xnu-11215.41.3/osfmk/arm/cpuid.c#L109-L231.
1715 //
1716 // Another great resource is
1717 // https://github.com/AsahiLinux/docs/wiki/Codenames.
1718 //
1719 // NOTE: We choose to return `apple-mX` instead of `apple-aX`, since the M1,
1720 // M2, M3 etc. aliases are more widely known to users than A14, A15, A16 etc.
1721 // (and this code is basically only used on host macOS anyways).
1722 switch (Family) {
1723 case CPUFAMILY_UNKNOWN:
1724 return "generic";
1725 case CPUFAMILY_ARM_9:
1726 return "arm920t"; // or arm926ej-s
1727 case CPUFAMILY_ARM_11:
1728 return "arm1136jf-s";
1729 case CPUFAMILY_ARM_XSCALE:
1730 return "xscale";
1731 case CPUFAMILY_ARM_12: // Seems unused by the kernel
1732 return "generic";
1733 case CPUFAMILY_ARM_13:
1734 return "cortex-a8";
1735 case CPUFAMILY_ARM_14:
1736 return "cortex-a9";
1737 case CPUFAMILY_ARM_15:
1738 return "cortex-a7";
1739 case CPUFAMILY_ARM_SWIFT:
1740 return "swift";
1741 case CPUFAMILY_ARM_CYCLONE:
1742 return "apple-a7";
1743 case CPUFAMILY_ARM_TYPHOON:
1744 return "apple-a8";
1745 case CPUFAMILY_ARM_TWISTER:
1746 return "apple-a9";
1747 case CPUFAMILY_ARM_HURRICANE:
1748 return "apple-a10";
1749 case CPUFAMILY_ARM_MONSOON_MISTRAL:
1750 return "apple-a11";
1751 case CPUFAMILY_ARM_VORTEX_TEMPEST:
1752 return "apple-a12";
1753 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
1754 return "apple-a13";
1755 case CPUFAMILY_ARM_FIRESTORM_ICESTORM: // A14 / M1
1756 return "apple-m1";
1757 case CPUFAMILY_ARM_BLIZZARD_AVALANCHE: // A15 / M2
1758 return "apple-m2";
1759 case CPUFAMILY_ARM_EVEREST_SAWTOOTH: // A16
1760 case CPUFAMILY_ARM_IBIZA: // M3
1761 case CPUFAMILY_ARM_PALMA: // M3 Max
1762 case CPUFAMILY_ARM_LOBOS: // M3 Pro
1763 return "apple-m3";
1764 case CPUFAMILY_ARM_COLL: // A17 Pro
1765 return "apple-a17";
1766 case CPUFAMILY_ARM_DONAN: // M4
1767 case CPUFAMILY_ARM_BRAVA: // M4 Max
1768 case CPUFAMILY_ARM_TAHITI: // A18 Pro
1769 case CPUFAMILY_ARM_TUPAI: // A18
1770 return "apple-m4";
1771 default:
1772 // Default to the newest CPU we know about.
1773 return "apple-m4";
1774 }
1775}
1776#elif defined(_AIX)
1777StringRef sys::getHostCPUName() {
1778 switch (_system_configuration.implementation) {
1779 case POWER_4:
1780 if (_system_configuration.version == PV_4_3)
1781 return "970";
1782 return "pwr4";
1783 case POWER_5:
1784 if (_system_configuration.version == PV_5)
1785 return "pwr5";
1786 return "pwr5x";
1787 case POWER_6:
1788 if (_system_configuration.version == PV_6_Compat)
1789 return "pwr6";
1790 return "pwr6x";
1791 case POWER_7:
1792 return "pwr7";
1793 case POWER_8:
1794 return "pwr8";
1795 case POWER_9:
1796 return "pwr9";
1797// TODO: simplify this once the macro is available in all OS levels.
1798#ifdef POWER_10
1799 case POWER_10:
1800#else
1801 case 0x40000:
1802#endif
1803 return "pwr10";
1804#ifdef POWER_11
1805 case POWER_11:
1806#else
1807 case 0x80000:
1808#endif
1809 return "pwr11";
1810 default:
1811 return "generic";
1812 }
1813}
1814#elif defined(__loongarch__)
1815StringRef sys::getHostCPUName() {
1816 // Use processor id to detect cpu name.
1817 uint32_t processor_id;
1818 __asm__("cpucfg %[prid], $zero\n\t" : [prid] "=r"(processor_id));
1819 // Refer PRID_SERIES_MASK in linux kernel: arch/loongarch/include/asm/cpu.h.
1820 switch (processor_id & 0xf000) {
1821 case 0xc000: // Loongson 64bit, 4-issue
1822 return "la464";
1823 case 0xd000: // Loongson 64bit, 6-issue
1824 return "la664";
1825 // TODO: Others.
1826 default:
1827 break;
1828 }
1829 return "generic";
1830}
1831#elif defined(__riscv)
1832#if defined(__linux__)
1833// struct riscv_hwprobe
1834struct RISCVHwProbe {
1835 int64_t Key;
1836 uint64_t Value;
1837};
1838#endif
1839
1840StringRef sys::getHostCPUName() {
1841#if defined(__linux__)
1842 // Try the hwprobe way first.
1843 RISCVHwProbe Query[]{{/*RISCV_HWPROBE_KEY_MVENDORID=*/0, 0},
1844 {/*RISCV_HWPROBE_KEY_MARCHID=*/1, 0},
1845 {/*RISCV_HWPROBE_KEY_MIMPID=*/2, 0}};
1846 int Ret = syscall(/*__NR_riscv_hwprobe=*/258, /*pairs=*/Query,
1847 /*pair_count=*/std::size(Query), /*cpu_count=*/0,
1848 /*cpus=*/0, /*flags=*/0);
1849 if (Ret == 0) {
1850 RISCV::CPUModel Model{static_cast<uint32_t>(Query[0].Value), Query[1].Value,
1851 Query[2].Value};
1852 StringRef Name = RISCV::getCPUNameFromCPUModel(Model);
1853 if (!Name.empty())
1854 return Name;
1855 }
1856
1857 // Then try the cpuinfo way.
1858 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1859 StringRef Content = P ? P->getBuffer() : "";
1860 StringRef Name = detail::getHostCPUNameForRISCV(Content);
1861 if (!Name.empty())
1862 return Name;
1863#endif
1864#if __riscv_xlen == 64
1865 return "generic-rv64";
1866#elif __riscv_xlen == 32
1867 return "generic-rv32";
1868#else
1869#error "Unhandled value of __riscv_xlen"
1870#endif
1871}
1872#elif defined(__sparc__)
1873#if defined(__linux__)
1874StringRef sys::detail::getHostCPUNameForSPARC(StringRef ProcCpuinfoContent) {
1875 SmallVector<StringRef> Lines;
1876 ProcCpuinfoContent.split(Lines, '\n');
1877
1878 // Look for cpu line to determine cpu name
1879 StringRef Cpu;
1880 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
1881 if (Lines[I].starts_with("cpu")) {
1882 Cpu = Lines[I].substr(5).ltrim("\t :");
1883 break;
1884 }
1885 }
1886
1887 return StringSwitch<const char *>(Cpu)
1888 .StartsWith("SuperSparc", "supersparc")
1889 .StartsWith("HyperSparc", "hypersparc")
1890 .StartsWith("SpitFire", "ultrasparc")
1891 .StartsWith("BlackBird", "ultrasparc")
1892 .StartsWith("Sabre", " ultrasparc")
1893 .StartsWith("Hummingbird", "ultrasparc")
1894 .StartsWith("Cheetah", "ultrasparc3")
1895 .StartsWith("Jalapeno", "ultrasparc3")
1896 .StartsWith("Jaguar", "ultrasparc3")
1897 .StartsWith("Panther", "ultrasparc3")
1898 .StartsWith("Serrano", "ultrasparc3")
1899 .StartsWith("UltraSparc T1", "niagara")
1900 .StartsWith("UltraSparc T2", "niagara2")
1901 .StartsWith("UltraSparc T3", "niagara3")
1902 .StartsWith("UltraSparc T4", "niagara4")
1903 .StartsWith("UltraSparc T5", "niagara4")
1904 .StartsWith("LEON", "leon3")
1905 // niagara7/m8 not supported by LLVM yet.
1906 .StartsWith("SPARC-M7", "niagara4" /* "niagara7" */)
1907 .StartsWith("SPARC-S7", "niagara4" /* "niagara7" */)
1908 .StartsWith("SPARC-M8", "niagara4" /* "m8" */)
1909 .Default("generic");
1910}
1911#endif
1912
1913StringRef sys::getHostCPUName() {
1914#if defined(__linux__)
1915 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1916 StringRef Content = P ? P->getBuffer() : "";
1917 return detail::getHostCPUNameForSPARC(Content);
1918#elif defined(__sun__) && defined(__svr4__)
1919 char *buf = NULL;
1920 kstat_ctl_t *kc;
1921 kstat_t *ksp;
1922 kstat_named_t *brand = NULL;
1923
1924 kc = kstat_open();
1925 if (kc != NULL) {
1926 ksp = kstat_lookup(kc, const_cast<char *>("cpu_info"), -1, NULL);
1927 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1928 ksp->ks_type == KSTAT_TYPE_NAMED)
1929 brand =
1930 (kstat_named_t *)kstat_data_lookup(ksp, const_cast<char *>("brand"));
1931 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1932 buf = KSTAT_NAMED_STR_PTR(brand);
1933 }
1934 kstat_close(kc);
1935
1936 return StringSwitch<const char *>(buf)
1937 .Case("TMS390S10", "supersparc") // Texas Instruments microSPARC I
1938 .Case("TMS390Z50", "supersparc") // Texas Instruments SuperSPARC I
1939 .Case("TMS390Z55",
1940 "supersparc") // Texas Instruments SuperSPARC I with SuperCache
1941 .Case("MB86904", "supersparc") // Fujitsu microSPARC II
1942 .Case("MB86907", "supersparc") // Fujitsu TurboSPARC
1943 .Case("RT623", "hypersparc") // Ross hyperSPARC
1944 .Case("RT625", "hypersparc")
1945 .Case("RT626", "hypersparc")
1946 .Case("UltraSPARC-I", "ultrasparc")
1947 .Case("UltraSPARC-II", "ultrasparc")
1948 .Case("UltraSPARC-IIe", "ultrasparc")
1949 .Case("UltraSPARC-IIi", "ultrasparc")
1950 .Case("SPARC64-III", "ultrasparc")
1951 .Case("SPARC64-IV", "ultrasparc")
1952 .Case("UltraSPARC-III", "ultrasparc3")
1953 .Case("UltraSPARC-III+", "ultrasparc3")
1954 .Case("UltraSPARC-IIIi", "ultrasparc3")
1955 .Case("UltraSPARC-IIIi+", "ultrasparc3")
1956 .Case("UltraSPARC-IV", "ultrasparc3")
1957 .Case("UltraSPARC-IV+", "ultrasparc3")
1958 .Case("SPARC64-V", "ultrasparc3")
1959 .Case("SPARC64-VI", "ultrasparc3")
1960 .Case("SPARC64-VII", "ultrasparc3")
1961 .Case("UltraSPARC-T1", "niagara")
1962 .Case("UltraSPARC-T2", "niagara2")
1963 .Case("UltraSPARC-T2", "niagara2")
1964 .Case("UltraSPARC-T2+", "niagara2")
1965 .Case("SPARC-T3", "niagara3")
1966 .Case("SPARC-T4", "niagara4")
1967 .Case("SPARC-T5", "niagara4")
1968 // niagara7/m8 not supported by LLVM yet.
1969 .Case("SPARC-M7", "niagara4" /* "niagara7" */)
1970 .Case("SPARC-S7", "niagara4" /* "niagara7" */)
1971 .Case("SPARC-M8", "niagara4" /* "m8" */)
1972 .Default("generic");
1973#else
1974 return "generic";
1975#endif
1976}
1977#else
1978StringRef sys::getHostCPUName() { return "generic"; }
1979namespace llvm {
1980namespace sys {
1981namespace detail {
1982namespace x86 {
1983
1984VendorSignatures getVendorSignature(unsigned *MaxLeaf) {
1985 return VendorSignatures::UNKNOWN;
1986}
1987
1988} // namespace x86
1989} // namespace detail
1990} // namespace sys
1991} // namespace llvm
1992#endif
1993
1994#if (defined(__i386__) || defined(_M_IX86) || defined(__x86_64__) || \
1995 defined(_M_X64)) && \
1996 !defined(_M_ARM64EC)
1997StringMap<bool> sys::getHostCPUFeatures() {
1998 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1999 unsigned MaxLevel;
2000 StringMap<bool> Features;
2001
2002 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
2003 return Features;
2004
2005 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
2006
2007 Features["cx8"] = (EDX >> 8) & 1;
2008 Features["cmov"] = (EDX >> 15) & 1;
2009 Features["mmx"] = (EDX >> 23) & 1;
2010 Features["fxsr"] = (EDX >> 24) & 1;
2011 Features["sse"] = (EDX >> 25) & 1;
2012 Features["sse2"] = (EDX >> 26) & 1;
2013
2014 Features["sse3"] = (ECX >> 0) & 1;
2015 Features["pclmul"] = (ECX >> 1) & 1;
2016 Features["ssse3"] = (ECX >> 9) & 1;
2017 Features["cx16"] = (ECX >> 13) & 1;
2018 Features["sse4.1"] = (ECX >> 19) & 1;
2019 Features["sse4.2"] = (ECX >> 20) & 1;
2020 Features["crc32"] = Features["sse4.2"];
2021 Features["movbe"] = (ECX >> 22) & 1;
2022 Features["popcnt"] = (ECX >> 23) & 1;
2023 Features["aes"] = (ECX >> 25) & 1;
2024 Features["rdrnd"] = (ECX >> 30) & 1;
2025
2026 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
2027 // indicates that the AVX registers will be saved and restored on context
2028 // switch, then we have full AVX support.
2029 bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
2030 bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6);
2031#if defined(__APPLE__)
2032 // Darwin lazily saves the AVX512 context on first use: trust that the OS will
2033 // save the AVX512 context if we use AVX512 instructions, even the bit is not
2034 // set right now.
2035 bool HasAVX512Save = true;
2036#else
2037 // AVX512 requires additional context to be saved by the OS.
2038 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
2039#endif
2040 // AMX requires additional context to be saved by the OS.
2041 const unsigned AMXBits = (1 << 17) | (1 << 18);
2042 bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits);
2043
2044 Features["avx"] = HasAVXSave;
2045 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave;
2046 // Only enable XSAVE if OS has enabled support for saving YMM state.
2047 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
2048 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave;
2049
2050 unsigned MaxExtLevel;
2051 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
2052
2053 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
2054 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
2055 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1);
2056 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
2057 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
2058 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
2059 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
2060 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);
2061 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
2062 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
2063 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
2064
2065 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1);
2066
2067 // Miscellaneous memory related features, detected by
2068 // using the 0x80000008 leaf of the CPUID instruction
2069 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
2070 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
2071 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
2072 Features["rdpru"] = HasExtLeaf8 && ((EBX >> 4) & 1);
2073 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
2074
2075 bool HasExtLeaf21 = MaxExtLevel >= 0x80000021 &&
2076 !getX86CpuIDAndInfo(0x80000021, &EAX, &EBX, &ECX, &EDX);
2077 // AMD cpuid bit for prefetchi is different from Intel
2078 Features["prefetchi"] = HasExtLeaf21 && ((EAX >> 20) & 1);
2079
2080 bool HasLeaf7 =
2081 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
2082
2083 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
2084 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
2085 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
2086 // AVX2 is only supported if we have the OS save support from AVX.
2087 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave;
2088 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
2089 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
2090 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
2091 // AVX512 is only supported if the OS supports the context save for it.
2092 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
2093 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
2094 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
2095 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
2096 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
2097 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
2098 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
2099 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
2100 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
2101 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
2102 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
2103
2104 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
2105 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
2106 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1);
2107 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save;
2108 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1);
2109 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1);
2110 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave;
2111 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
2112 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
2113 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
2114 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
2115 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1);
2116 Features["kl"] = HasLeaf7 && ((ECX >> 23) & 1); // key locker
2117 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1);
2118 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);
2119 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
2120 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1);
2121
2122 Features["uintr"] = HasLeaf7 && ((EDX >> 5) & 1);
2123 Features["avx512vp2intersect"] =
2124 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save;
2125 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1);
2126 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1);
2127 // There are two CPUID leafs which information associated with the pconfig
2128 // instruction:
2129 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
2130 // bit of EDX), while the EAX=0x1b leaf returns information on the
2131 // availability of specific pconfig leafs.
2132 // The target feature here only refers to the the first of these two.
2133 // Users might need to check for the availability of specific pconfig
2134 // leaves using cpuid, since that information is ignored while
2135 // detecting features using the "-march=native" flag.
2136 // For more info, see X86 ISA docs.
2137 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
2138 Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;
2139 Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save;
2140 Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
2141 Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
2142 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't
2143 // return all 0s for invalid subleaves so check the limit.
2144 bool HasLeaf7Subleaf1 =
2145 HasLeaf7 && EAX >= 1 &&
2146 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
2147 Features["sha512"] = HasLeaf7Subleaf1 && ((EAX >> 0) & 1);
2148 Features["sm3"] = HasLeaf7Subleaf1 && ((EAX >> 1) & 1);
2149 Features["sm4"] = HasLeaf7Subleaf1 && ((EAX >> 2) & 1);
2150 Features["raoint"] = HasLeaf7Subleaf1 && ((EAX >> 3) & 1);
2151 Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;
2152 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
2153 Features["amx-fp16"] = HasLeaf7Subleaf1 && ((EAX >> 21) & 1) && HasAMXSave;
2154 Features["cmpccxadd"] = HasLeaf7Subleaf1 && ((EAX >> 7) & 1);
2155 Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1);
2156 Features["avxifma"] = HasLeaf7Subleaf1 && ((EAX >> 23) & 1) && HasAVXSave;
2157 Features["movrs"] = HasLeaf7Subleaf1 && ((EAX >> 31) & 1);
2158 Features["avxvnniint8"] = HasLeaf7Subleaf1 && ((EDX >> 4) & 1) && HasAVXSave;
2159 Features["avxneconvert"] = HasLeaf7Subleaf1 && ((EDX >> 5) & 1) && HasAVXSave;
2160 Features["amx-complex"] = HasLeaf7Subleaf1 && ((EDX >> 8) & 1) && HasAMXSave;
2161 Features["avxvnniint16"] = HasLeaf7Subleaf1 && ((EDX >> 10) & 1) && HasAVXSave;
2162 Features["prefetchi"] |= HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
2163 Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
2164 bool HasAVX10 = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
2165 bool HasAPXF = HasLeaf7Subleaf1 && ((EDX >> 21) & 1);
2166 Features["egpr"] = HasAPXF;
2167 Features["push2pop2"] = HasAPXF;
2168 Features["ppx"] = HasAPXF;
2169 Features["ndd"] = HasAPXF;
2170 Features["ccmp"] = HasAPXF;
2171 Features["nf"] = HasAPXF;
2172 Features["cf"] = HasAPXF;
2173 Features["zu"] = HasAPXF;
2174
2175 bool HasLeafD = MaxLevel >= 0xd &&
2176 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
2177
2178 // Only enable XSAVE if OS has enabled support for saving YMM state.
2179 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
2180 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
2181 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
2182
2183 bool HasLeaf14 = MaxLevel >= 0x14 &&
2184 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
2185
2186 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
2187
2188 bool HasLeaf19 =
2189 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
2190 Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1);
2191
2192 bool HasLeaf1E = MaxLevel >= 0x1e &&
2193 !getX86CpuIDAndInfoEx(0x1e, 0x1, &EAX, &EBX, &ECX, &EDX);
2194 Features["amx-fp8"] = HasLeaf1E && ((EAX >> 4) & 1) && HasAMXSave;
2195 Features["amx-tf32"] = HasLeaf1E && ((EAX >> 6) & 1) && HasAMXSave;
2196 Features["amx-avx512"] = HasLeaf1E && ((EAX >> 7) & 1) && HasAMXSave;
2197 Features["amx-movrs"] = HasLeaf1E && ((EAX >> 8) & 1) && HasAMXSave;
2198
2199 bool HasLeaf24 = MaxLevel >= 0x24 &&
2200 !getX86CpuIDAndInfoEx(0x24, 0x0, &EAX, &EBX, &ECX, &EDX);
2201
2202 int AVX10Ver = HasLeaf24 ? (EBX & 0xff) : 0;
2203 Features["avx10.1"] = HasAVX10 && AVX10Ver >= 1;
2204 Features["avx10.2"] = HasAVX10 && AVX10Ver >= 2;
2205
2206 return Features;
2207}
2208#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
2209StringMap<bool> sys::getHostCPUFeatures() {
2210 StringMap<bool> Features;
2211 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
2212 if (!P)
2213 return Features;
2214
2215 SmallVector<StringRef, 32> Lines;
2216 P->getBuffer().split(Lines, '\n');
2217
2218 SmallVector<StringRef, 32> CPUFeatures;
2219
2220 // Look for the CPU features.
2221 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
2222 if (Lines[I].starts_with("Features")) {
2223 Lines[I].split(CPUFeatures, ' ');
2224 break;
2225 }
2226
2227#if defined(__aarch64__)
2228 // All of these are "crypto" features, but we must sift out actual features
2229 // as the former meaning of "crypto" as a single feature is no more.
2230 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
2231 uint32_t crypto = 0;
2232#endif
2233
2234 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
2235 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
2236#if defined(__aarch64__)
2237 .Case("asimd", "neon")
2238 .Case("fp", "fp-armv8")
2239 .Case("crc32", "crc")
2240 .Case("atomics", "lse")
2241 .Case("sha3", "sha3")
2242 .Case("sm4", "sm4")
2243 .Case("sve", "sve")
2244 .Case("sve2", "sve2")
2245 .Case("sveaes", "sve-aes")
2246 .Case("svesha3", "sve-sha3")
2247 .Case("svesm4", "sve-sm4")
2248#else
2249 .Case("half", "fp16")
2250 .Case("neon", "neon")
2251 .Case("vfpv3", "vfp3")
2252 .Case("vfpv3d16", "vfp3d16")
2253 .Case("vfpv4", "vfp4")
2254 .Case("idiva", "hwdiv-arm")
2255 .Case("idivt", "hwdiv")
2256#endif
2257 .Default("");
2258
2259#if defined(__aarch64__)
2260 // We need to check crypto separately since we need all of the crypto
2261 // extensions to enable the subtarget feature
2262 if (CPUFeatures[I] == "aes")
2263 crypto |= CAP_AES;
2264 else if (CPUFeatures[I] == "pmull")
2265 crypto |= CAP_PMULL;
2266 else if (CPUFeatures[I] == "sha1")
2267 crypto |= CAP_SHA1;
2268 else if (CPUFeatures[I] == "sha2")
2269 crypto |= CAP_SHA2;
2270#endif
2271
2272 if (LLVMFeatureStr != "")
2273 Features[LLVMFeatureStr] = true;
2274 }
2275
2276#if defined(__aarch64__)
2277 // LLVM has decided some AArch64 CPUs have all the instructions they _may_
2278 // have, as opposed to all the instructions they _must_ have, so allow runtime
2279 // information to correct us on that.
2280 uint32_t Aes = CAP_AES | CAP_PMULL;
2281 uint32_t Sha2 = CAP_SHA1 | CAP_SHA2;
2282 Features["aes"] = (crypto & Aes) == Aes;
2283 Features["sha2"] = (crypto & Sha2) == Sha2;
2284
2285 // Even if an underlying core supports SVE, it might not be available if
2286 // it's disabled by the OS, or some other layer. Disable SVE if we don't
2287 // detect support at runtime.
2288 if (!Features.contains("sve"))
2289 Features["sve"] = false;
2290#endif
2291
2292 return Features;
2293}
2294#elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64) || \
2295 defined(__arm64ec__) || defined(_M_ARM64EC))
2296#ifndef PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE
2297#define PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE 43
2298#endif
2299#ifndef PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE
2300#define PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE 44
2301#endif
2302#ifndef PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE
2303#define PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE 45
2304#endif
2305#ifndef PF_ARM_SVE_INSTRUCTIONS_AVAILABLE
2306#define PF_ARM_SVE_INSTRUCTIONS_AVAILABLE 46
2307#endif
2308#ifndef PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE
2309#define PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE 47
2310#endif
2311#ifndef PF_ARM_SVE2_1_INSTRUCTIONS_AVAILABLE
2312#define PF_ARM_SVE2_1_INSTRUCTIONS_AVAILABLE 48
2313#endif
2314#ifndef PF_ARM_SVE_PMULL128_INSTRUCTIONS_AVAILABLE
2315#define PF_ARM_SVE_PMULL128_INSTRUCTIONS_AVAILABLE 50
2316#endif
2317#ifndef PF_ARM_SVE_BITPERM_INSTRUCTIONS_AVAILABLE
2318#define PF_ARM_SVE_BITPERM_INSTRUCTIONS_AVAILABLE 51
2319#endif
2320#ifndef PF_ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE
2321#define PF_ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE 55
2322#endif
2323#ifndef PF_ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE
2324#define PF_ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE 56
2325#endif
2326#ifndef PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE
2327#define PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE 58
2328#endif
2329#ifndef PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE
2330#define PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE 59
2331#endif
2332#ifndef PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE
2333#define PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE 66
2334#endif
2335#ifndef PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE
2336#define PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE 67
2337#endif
2338#ifndef PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE
2339#define PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE 68
2340#endif
2341#ifndef PF_ARM_SME_INSTRUCTIONS_AVAILABLE
2342#define PF_ARM_SME_INSTRUCTIONS_AVAILABLE 70
2343#endif
2344#ifndef PF_ARM_SME2_INSTRUCTIONS_AVAILABLE
2345#define PF_ARM_SME2_INSTRUCTIONS_AVAILABLE 71
2346#endif
2347#ifndef PF_ARM_SME_F64F64_INSTRUCTIONS_AVAILABLE
2348#define PF_ARM_SME_F64F64_INSTRUCTIONS_AVAILABLE 85
2349#endif
2350#ifndef PF_ARM_SME_I16I64_INSTRUCTIONS_AVAILABLE
2351#define PF_ARM_SME_I16I64_INSTRUCTIONS_AVAILABLE 86
2352#endif
2353
2354StringMap<bool> sys::getHostCPUFeatures() {
2355 StringMap<bool> Features;
2356
2357 // If we're asking the OS at runtime, believe what the OS says
2358 Features["crc"] =
2359 IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE);
2360 Features["lse"] =
2361 IsProcessorFeaturePresent(PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE);
2362 Features["dotprod"] =
2363 IsProcessorFeaturePresent(PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE);
2364 Features["jsconv"] =
2365 IsProcessorFeaturePresent(PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE);
2366 Features["rcpc"] =
2367 IsProcessorFeaturePresent(PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE);
2368 Features["sve"] =
2369 IsProcessorFeaturePresent(PF_ARM_SVE_INSTRUCTIONS_AVAILABLE);
2370 Features["sve2"] =
2371 IsProcessorFeaturePresent(PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE);
2372 Features["sve2p1"] =
2373 IsProcessorFeaturePresent(PF_ARM_SVE2_1_INSTRUCTIONS_AVAILABLE);
2374 Features["sve-aes"] =
2375 IsProcessorFeaturePresent(PF_ARM_SVE_PMULL128_INSTRUCTIONS_AVAILABLE);
2376 Features["sve-bitperm"] =
2377 IsProcessorFeaturePresent(PF_ARM_SVE_BITPERM_INSTRUCTIONS_AVAILABLE);
2378 Features["sve-sha3"] =
2379 IsProcessorFeaturePresent(PF_ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE);
2380 Features["sve-sm4"] =
2381 IsProcessorFeaturePresent(PF_ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE);
2382 Features["f32mm"] =
2383 IsProcessorFeaturePresent(PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE);
2384 Features["f64mm"] =
2385 IsProcessorFeaturePresent(PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE);
2386 Features["i8mm"] =
2387 IsProcessorFeaturePresent(PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE);
2388 Features["fp16"] =
2389 IsProcessorFeaturePresent(PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE);
2390 Features["bf16"] =
2391 IsProcessorFeaturePresent(PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE);
2392 Features["sme"] =
2393 IsProcessorFeaturePresent(PF_ARM_SME_INSTRUCTIONS_AVAILABLE);
2394 Features["sme2"] =
2395 IsProcessorFeaturePresent(PF_ARM_SME2_INSTRUCTIONS_AVAILABLE);
2396 Features["sme-i16i64"] =
2397 IsProcessorFeaturePresent(PF_ARM_SME_I16I64_INSTRUCTIONS_AVAILABLE);
2398 Features["sme-f64f64"] =
2399 IsProcessorFeaturePresent(PF_ARM_SME_F64F64_INSTRUCTIONS_AVAILABLE);
2400
2401 // Avoid inferring "crypto" means more than the traditional AES + SHA2
2402 bool TradCrypto =
2403 IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE);
2404 Features["aes"] = TradCrypto;
2405 Features["sha2"] = TradCrypto;
2406
2407 return Features;
2408}
2409#elif defined(__linux__) && defined(__loongarch__)
2410#include <sys/auxv.h>
2411StringMap<bool> sys::getHostCPUFeatures() {
2412 unsigned long hwcap = getauxval(AT_HWCAP);
2413 bool HasFPU = hwcap & (1UL << 3); // HWCAP_LOONGARCH_FPU
2414 uint32_t cpucfg2 = 0x2, cpucfg3 = 0x3;
2415 __asm__("cpucfg %[cpucfg2], %[cpucfg2]\n\t" : [cpucfg2] "+r"(cpucfg2));
2416 __asm__("cpucfg %[cpucfg3], %[cpucfg3]\n\t" : [cpucfg3] "+r"(cpucfg3));
2417
2418 StringMap<bool> Features;
2419
2420 Features["f"] = HasFPU && (cpucfg2 & (1U << 1)); // CPUCFG.2.FP_SP
2421 Features["d"] = HasFPU && (cpucfg2 & (1U << 2)); // CPUCFG.2.FP_DP
2422
2423 Features["lsx"] = hwcap & (1UL << 4); // HWCAP_LOONGARCH_LSX
2424 Features["lasx"] = hwcap & (1UL << 5); // HWCAP_LOONGARCH_LASX
2425 Features["lvz"] = hwcap & (1UL << 9); // HWCAP_LOONGARCH_LVZ
2426
2427 Features["frecipe"] = cpucfg2 & (1U << 25); // CPUCFG.2.FRECIPE
2428 Features["div32"] = cpucfg2 & (1U << 26); // CPUCFG.2.DIV32
2429 Features["lam-bh"] = cpucfg2 & (1U << 27); // CPUCFG.2.LAM_BH
2430 Features["lamcas"] = cpucfg2 & (1U << 28); // CPUCFG.2.LAMCAS
2431 Features["scq"] = cpucfg2 & (1U << 30); // CPUCFG.2.SCQ
2432
2433 Features["ld-seq-sa"] = cpucfg3 & (1U << 23); // CPUCFG.3.LD_SEQ_SA
2434
2435 // TODO: Need to complete.
2436 // Features["llacq-screl"] = cpucfg2 & (1U << 29); // CPUCFG.2.LLACQ_SCREL
2437 return Features;
2438}
2439#elif defined(__linux__) && defined(__riscv)
2440StringMap<bool> sys::getHostCPUFeatures() {
2441 RISCVHwProbe Query[]{{/*RISCV_HWPROBE_KEY_BASE_BEHAVIOR=*/3, 0},
2442 {/*RISCV_HWPROBE_KEY_IMA_EXT_0=*/4, 0},
2443 {/*RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF=*/9, 0}};
2444 int Ret = syscall(/*__NR_riscv_hwprobe=*/258, /*pairs=*/Query,
2445 /*pair_count=*/std::size(Query), /*cpu_count=*/0,
2446 /*cpus=*/0, /*flags=*/0);
2447 if (Ret != 0)
2448 return {};
2449
2450 StringMap<bool> Features;
2451 uint64_t BaseMask = Query[0].Value;
2452 // Check whether RISCV_HWPROBE_BASE_BEHAVIOR_IMA is set.
2453 if (BaseMask & 1) {
2454 Features["i"] = true;
2455 Features["m"] = true;
2456 Features["a"] = true;
2457 }
2458
2459 uint64_t ExtMask = Query[1].Value;
2460 Features["f"] = ExtMask & (1 << 0); // RISCV_HWPROBE_IMA_FD
2461 Features["d"] = ExtMask & (1 << 0); // RISCV_HWPROBE_IMA_FD
2462 Features["c"] = ExtMask & (1 << 1); // RISCV_HWPROBE_IMA_C
2463 Features["v"] = ExtMask & (1 << 2); // RISCV_HWPROBE_IMA_V
2464 Features["zba"] = ExtMask & (1 << 3); // RISCV_HWPROBE_EXT_ZBA
2465 Features["zbb"] = ExtMask & (1 << 4); // RISCV_HWPROBE_EXT_ZBB
2466 Features["zbs"] = ExtMask & (1 << 5); // RISCV_HWPROBE_EXT_ZBS
2467 Features["zicboz"] = ExtMask & (1 << 6); // RISCV_HWPROBE_EXT_ZICBOZ
2468 Features["zbc"] = ExtMask & (1 << 7); // RISCV_HWPROBE_EXT_ZBC
2469 Features["zbkb"] = ExtMask & (1 << 8); // RISCV_HWPROBE_EXT_ZBKB
2470 Features["zbkc"] = ExtMask & (1 << 9); // RISCV_HWPROBE_EXT_ZBKC
2471 Features["zbkx"] = ExtMask & (1 << 10); // RISCV_HWPROBE_EXT_ZBKX
2472 Features["zknd"] = ExtMask & (1 << 11); // RISCV_HWPROBE_EXT_ZKND
2473 Features["zkne"] = ExtMask & (1 << 12); // RISCV_HWPROBE_EXT_ZKNE
2474 Features["zknh"] = ExtMask & (1 << 13); // RISCV_HWPROBE_EXT_ZKNH
2475 Features["zksed"] = ExtMask & (1 << 14); // RISCV_HWPROBE_EXT_ZKSED
2476 Features["zksh"] = ExtMask & (1 << 15); // RISCV_HWPROBE_EXT_ZKSH
2477 Features["zkt"] = ExtMask & (1 << 16); // RISCV_HWPROBE_EXT_ZKT
2478 Features["zvbb"] = ExtMask & (1 << 17); // RISCV_HWPROBE_EXT_ZVBB
2479 Features["zvbc"] = ExtMask & (1 << 18); // RISCV_HWPROBE_EXT_ZVBC
2480 Features["zvkb"] = ExtMask & (1 << 19); // RISCV_HWPROBE_EXT_ZVKB
2481 Features["zvkg"] = ExtMask & (1 << 20); // RISCV_HWPROBE_EXT_ZVKG
2482 Features["zvkned"] = ExtMask & (1 << 21); // RISCV_HWPROBE_EXT_ZVKNED
2483 Features["zvknha"] = ExtMask & (1 << 22); // RISCV_HWPROBE_EXT_ZVKNHA
2484 Features["zvknhb"] = ExtMask & (1 << 23); // RISCV_HWPROBE_EXT_ZVKNHB
2485 Features["zvksed"] = ExtMask & (1 << 24); // RISCV_HWPROBE_EXT_ZVKSED
2486 Features["zvksh"] = ExtMask & (1 << 25); // RISCV_HWPROBE_EXT_ZVKSH
2487 Features["zvkt"] = ExtMask & (1 << 26); // RISCV_HWPROBE_EXT_ZVKT
2488 Features["zfh"] = ExtMask & (1 << 27); // RISCV_HWPROBE_EXT_ZFH
2489 Features["zfhmin"] = ExtMask & (1 << 28); // RISCV_HWPROBE_EXT_ZFHMIN
2490 Features["zihintntl"] = ExtMask & (1 << 29); // RISCV_HWPROBE_EXT_ZIHINTNTL
2491 Features["zvfh"] = ExtMask & (1 << 30); // RISCV_HWPROBE_EXT_ZVFH
2492 Features["zvfhmin"] = ExtMask & (1ULL << 31); // RISCV_HWPROBE_EXT_ZVFHMIN
2493 Features["zfa"] = ExtMask & (1ULL << 32); // RISCV_HWPROBE_EXT_ZFA
2494 Features["ztso"] = ExtMask & (1ULL << 33); // RISCV_HWPROBE_EXT_ZTSO
2495 Features["zacas"] = ExtMask & (1ULL << 34); // RISCV_HWPROBE_EXT_ZACAS
2496 Features["zicond"] = ExtMask & (1ULL << 35); // RISCV_HWPROBE_EXT_ZICOND
2497 Features["zihintpause"] =
2498 ExtMask & (1ULL << 36); // RISCV_HWPROBE_EXT_ZIHINTPAUSE
2499 Features["zve32x"] = ExtMask & (1ULL << 37); // RISCV_HWPROBE_EXT_ZVE32X
2500 Features["zve32f"] = ExtMask & (1ULL << 38); // RISCV_HWPROBE_EXT_ZVE32F
2501 Features["zve64x"] = ExtMask & (1ULL << 39); // RISCV_HWPROBE_EXT_ZVE64X
2502 Features["zve64f"] = ExtMask & (1ULL << 40); // RISCV_HWPROBE_EXT_ZVE64F
2503 Features["zve64d"] = ExtMask & (1ULL << 41); // RISCV_HWPROBE_EXT_ZVE64D
2504 Features["zimop"] = ExtMask & (1ULL << 42); // RISCV_HWPROBE_EXT_ZIMOP
2505 Features["zca"] = ExtMask & (1ULL << 43); // RISCV_HWPROBE_EXT_ZCA
2506 Features["zcb"] = ExtMask & (1ULL << 44); // RISCV_HWPROBE_EXT_ZCB
2507 Features["zcd"] = ExtMask & (1ULL << 45); // RISCV_HWPROBE_EXT_ZCD
2508 Features["zcf"] = ExtMask & (1ULL << 46); // RISCV_HWPROBE_EXT_ZCF
2509 Features["zcmop"] = ExtMask & (1ULL << 47); // RISCV_HWPROBE_EXT_ZCMOP
2510 Features["zawrs"] = ExtMask & (1ULL << 48); // RISCV_HWPROBE_EXT_ZAWRS
2511
2512 // Check whether the processor supports fast misaligned scalar memory access.
2513 // NOTE: RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF is only available on
2514 // Linux 6.11 or later. If it is not recognized, the key field will be cleared
2515 // to -1.
2516 if (Query[2].Key != -1 &&
2517 Query[2].Value == /*RISCV_HWPROBE_MISALIGNED_SCALAR_FAST=*/3)
2518 Features["unaligned-scalar-mem"] = true;
2519
2520 return Features;
2521}
2522#else
2523StringMap<bool> sys::getHostCPUFeatures() { return {}; }
2524#endif
2525
2526#if __APPLE__
2527/// \returns the \p triple, but with the Host's arch spliced in.
2528static Triple withHostArch(Triple T) {
2529#if defined(__arm__)
2530 T.setArch(Triple::arm);
2531 T.setArchName("arm");
2532#elif defined(__arm64e__)
2533 T.setArch(Triple::aarch64, Triple::AArch64SubArch_arm64e);
2534 T.setArchName("arm64e");
2535#elif defined(__aarch64__)
2536 T.setArch(Triple::aarch64);
2537 T.setArchName("arm64");
2538#elif defined(__x86_64h__)
2539 T.setArch(Triple::x86_64);
2540 T.setArchName("x86_64h");
2541#elif defined(__x86_64__)
2542 T.setArch(Triple::x86_64);
2543 T.setArchName("x86_64");
2544#elif defined(__i386__)
2545 T.setArch(Triple::x86);
2546 T.setArchName("i386");
2547#elif defined(__powerpc__)
2548 T.setArch(Triple::ppc);
2549 T.setArchName("powerpc");
2550#else
2551# error "Unimplemented host arch fixup"
2552#endif
2553 return T;
2554}
2555#endif
2556
2557std::string sys::getProcessTriple() {
2558 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
2559 Triple PT(Triple::normalize(TargetTripleString));
2560
2561#if __APPLE__
2562 /// In Universal builds, LLVM_HOST_TRIPLE will have the wrong arch in one of
2563 /// the slices. This fixes that up.
2564 PT = withHostArch(PT);
2565#endif
2566
2567 if (sizeof(void *) == 8 && PT.isArch32Bit())
2568 PT = PT.get64BitArchVariant();
2569 if (sizeof(void *) == 4 && PT.isArch64Bit())
2570 PT = PT.get32BitArchVariant();
2571
2572 return PT.str();
2573}
2574
2575void sys::printDefaultTargetAndDetectedCPU(raw_ostream &OS) {
2576#if LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO
2577 std::string CPU = std::string(sys::getHostCPUName());
2578 if (CPU == "generic")
2579 CPU = "(unknown)";
2580 OS << " Default target: " << sys::getDefaultTargetTriple() << '\n'
2581 << " Host CPU: " << CPU << '\n';
2582#endif
2583}
StringMap.h
This file defines the StringMap class.
Bitfields.h
This file implements methods to test, set and extract typed bits from packed unsigned integers.
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
getHostCPUNameForARMFromComponents
StringRef getHostCPUNameForARMFromComponents(StringRef Implementer, StringRef Hardware, StringRef Part, ArrayRef< StringRef > Parts, function_ref< unsigned()> GetVariant)
Definition Host.cpp:174
getProcCpuinfoContent
static std::unique_ptr< llvm::MemoryBuffer > getProcCpuinfoContent()
Definition Host.cpp:74
F
#define F(x, y, z)
Definition MD5.cpp:54
I
#define I(x, y, z)
Definition MD5.cpp:57
memcmp
Merge contiguous icmps into a memcmp
Definition MergeICmps.cpp:957
T
#define T
Definition Mips16ISelLowering.cpp:282
P
#define P(N)
SmallVector.h
This file defines the SmallVector class.
StringExtras.h
This file contains some functions that are useful when dealing with strings.
StringSwitch.h
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
starts_with
DEMANGLE_NAMESPACE_BEGIN bool starts_with(std::string_view self, char C) noexcept
Definition StringViewExtras.h:24
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition ArrayRef.h:142
llvm::ErrorOr
Represents either an error or a value T.
Definition ErrorOr.h:56
llvm::MemoryBuffer::getFileAsStream
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
Definition MemoryBuffer.cpp:603
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition SmallVector.h:944
llvm::SmallVectorImpl::reserve
void reserve(size_type N)
Definition SmallVector.h:664
llvm::SmallVectorImpl::erase
iterator erase(const_iterator CI)
Definition SmallVector.h:744
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition SmallVector.h:417
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1203
llvm::StringMap
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
Definition StringMap.h:133
llvm::StringMap::contains
bool contains(StringRef Key) const
contains - Return true if the element is in the map, false otherwise.
Definition StringMap.h:280
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
llvm::StringRef::split
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition StringRef.h:702
llvm::StringRef::npos
static constexpr size_t npos
Definition StringRef.h:57
llvm::StringRef::getAsInteger
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition StringRef.h:472
llvm::StringRef::substr
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition StringRef.h:573
llvm::StringRef::begin
iterator begin() const
Definition StringRef.h:112
llvm::StringRef::const_iterator
const char * const_iterator
Definition StringRef.h:60
llvm::StringRef::ltrim
StringRef ltrim(char Char) const
Return string with consecutive Char characters starting from the the left removed.
Definition StringRef.h:792
llvm::StringRef::end
iterator end() const
Definition StringRef.h:114
llvm::StringRef::ends_with
bool ends_with(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition StringRef.h:273
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition StringSwitch.h:47
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition StringSwitch.h:69
llvm::StringSwitch::StartsWith
StringSwitch & StartsWith(StringLiteral S, T Value)
Definition StringSwitch.h:81
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition Triple.h:47
llvm::Triple::get32BitArchVariant
LLVM_ABI llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
Definition Triple.cpp:1809
llvm::Triple::get64BitArchVariant
LLVM_ABI llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
Definition Triple.cpp:1892
llvm::Triple::normalize
static LLVM_ABI std::string normalize(StringRef Str, CanonicalForm Form=CanonicalForm::ANY)
Turn an arbitrary machine specification into the canonical triple form (or something sensible that th...
Definition Triple.cpp:1178
llvm::Triple::str
const std::string & str() const
Definition Triple.h:481
llvm::Triple::isArch64Bit
LLVM_ABI bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition Triple.cpp:1797
llvm::Triple::AArch64SubArch_arm64e
@ AArch64SubArch_arm64e
Definition Triple.h:154
llvm::Triple::isArch32Bit
LLVM_ABI bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition Triple.cpp:1801
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:45
llvm::Value
LLVM Value Representation.
Definition Value.h:75
llvm::function_ref
An efficient, type-erasing, non-owning reference to a callable.
Definition STLFunctionalExtras.h:37
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
uint16_t
uint32_t
uint64_t
uint8_t
llvm::MachO::CPU_SUBTYPE_POWERPC_970
@ CPU_SUBTYPE_POWERPC_970
Definition MachO.h:1697
llvm::MachO::CPU_SUBTYPE_POWERPC_604e
@ CPU_SUBTYPE_POWERPC_604e
Definition MachO.h:1692
llvm::MachO::CPU_SUBTYPE_POWERPC_603e
@ CPU_SUBTYPE_POWERPC_603e
Definition MachO.h:1689
llvm::MachO::CPU_SUBTYPE_POWERPC_7400
@ CPU_SUBTYPE_POWERPC_7400
Definition MachO.h:1695
llvm::MachO::CPU_SUBTYPE_POWERPC_604
@ CPU_SUBTYPE_POWERPC_604
Definition MachO.h:1691
llvm::MachO::CPU_SUBTYPE_POWERPC_750
@ CPU_SUBTYPE_POWERPC_750
Definition MachO.h:1694
llvm::MachO::CPU_SUBTYPE_POWERPC_601
@ CPU_SUBTYPE_POWERPC_601
Definition MachO.h:1686
llvm::MachO::CPU_SUBTYPE_POWERPC_620
@ CPU_SUBTYPE_POWERPC_620
Definition MachO.h:1693
llvm::MachO::CPU_SUBTYPE_POWERPC_603ev
@ CPU_SUBTYPE_POWERPC_603ev
Definition MachO.h:1690
llvm::MachO::CPU_SUBTYPE_POWERPC_603
@ CPU_SUBTYPE_POWERPC_603
Definition MachO.h:1688
llvm::MachO::CPU_SUBTYPE_POWERPC_7450
@ CPU_SUBTYPE_POWERPC_7450
Definition MachO.h:1696
llvm::MachO::CPU_SUBTYPE_POWERPC_602
@ CPU_SUBTYPE_POWERPC_602
Definition MachO.h:1687
llvm::RISCV::getCPUNameFromCPUModel
LLVM_ABI StringRef getCPUNameFromCPUModel(const CPUModel &Model)
Definition RISCVTargetParser.cpp:69
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
Definition MicrosoftDemangle.h:132
llvm::sys::detail::x86
Helper functions to extract CPU details from CPUID on x86.
Definition Host.h:75
llvm::sys::detail::x86::getVendorSignature
LLVM_ABI VendorSignatures getVendorSignature(unsigned *MaxLeaf=nullptr)
Returns the host CPU's vendor.
Definition Host.cpp:1984
llvm::sys::detail::getHostCPUNameForSPARC
LLVM_ABI StringRef getHostCPUNameForSPARC(StringRef ProcCpuinfoContent)
llvm::sys::detail::getHostCPUNameForS390x
LLVM_ABI StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
Definition Host.cpp:509
llvm::sys::detail::getHostCPUNameForPowerPC
LLVM_ABI StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
Definition Host.cpp:89
llvm::sys::detail::getHostCPUNameForBPF
LLVM_ABI StringRef getHostCPUNameForBPF()
Definition Host.cpp:571
llvm::sys::detail::getHostCPUNameForARM
LLVM_ABI StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
Definition Host.cpp:398
llvm::sys::detail::getHostCPUNameForRISCV
LLVM_ABI StringRef getHostCPUNameForRISCV(StringRef ProcCpuinfoContent)
Definition Host.cpp:550
llvm::sys::getHostCPUFeatures
LLVM_ABI StringMap< bool, MallocAllocator > getHostCPUFeatures()
getHostCPUFeatures - Get the LLVM names for the host CPU features.
Definition Host.cpp:2523
llvm::sys::getHostCPUName
LLVM_ABI StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
Definition Host.cpp:1978
llvm::sys::printDefaultTargetAndDetectedCPU
LLVM_ABI void printDefaultTargetAndDetectedCPU(raw_ostream &OS)
This is a function compatible with cl::AddExtraVersionPrinter, which adds info about the current targ...
Definition Host.cpp:2575
llvm::sys::getDefaultTargetTriple
LLVM_ABI std::string getDefaultTargetTriple()
getDefaultTargetTriple() - Return the default target triple the compiler has been configured to produ...
llvm::sys::getProcessTriple
LLVM_ABI std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
Definition Host.cpp:2557
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition AddressRanges.h:18
llvm::Length
@ Length
Definition DWP.cpp:532
llvm::Value
FunctionAddr VTableAddr Value
Definition InstrProf.h:137
llvm::utohexstr
std::string utohexstr(uint64_t X, bool LowerCase=false, unsigned Width=0)
Definition StringExtras.h:177
llvm::decodePackedBCD
int64_t decodePackedBCD(const uint8_t *Ptr, size_t ByteLen, bool IsSigned=true)
Definition BCD.h:26
llvm::unique
auto unique(Range &&R, Predicate P)
Definition STLExtras.h:2097
llvm::sort
void sort(IteratorTy Start, IteratorTy End)
Definition STLExtras.h:1634
llvm::Key
LLVM_ATTRIBUTE_VISIBILITY_DEFAULT AnalysisKey InnerAnalysisManagerProxy< AnalysisManagerT, IRUnitT, ExtraArgTs... >::Key
Definition PassManager.h:667
llvm::errs
LLVM_ABI raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition raw_ostream.cpp:904
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition STLExtras.h:1918
raw_ostream.h
llvm::Bitfield::Element
Describes an element of a Bitfield.
Definition Bitfields.h:176
llvm::Bitfield::get
static Bitfield::Type get(StorageType Packed)
Unpacks the field from the Packed value.
Definition Bitfields.h:207
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