18#include "llvm/Config/llvm-config.h"
40#include <mach/host_info.h>
42#include <mach/mach_host.h>
43#include <mach/machine.h>
45#include <sys/sysctl.h>
48#include <sys/systemcfg.h>
50#if defined(__sun__) && defined(__svr4__)
54#define DEBUG_TYPE "host-detection"
64static std::unique_ptr<llvm::MemoryBuffer>
68 if (std::error_code EC = Text.getError()) {
70 <<
"/proc/cpuinfo: " << EC.message() <<
"\n";
73 return std::move(*Text);
80 const char *
generic =
"generic";
94 while (CIP < CPUInfoEnd && CPUStart ==
nullptr) {
95 if (CIP < CPUInfoEnd && *CIP ==
'\n')
98 if (CIP < CPUInfoEnd && *CIP ==
'c') {
100 if (CIP < CPUInfoEnd && *CIP ==
'p') {
102 if (CIP < CPUInfoEnd && *CIP ==
'u') {
104 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
107 if (CIP < CPUInfoEnd && *CIP ==
':') {
109 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
112 if (CIP < CPUInfoEnd) {
114 while (CIP < CPUInfoEnd && (*CIP !=
' ' && *CIP !=
'\t' &&
115 *CIP !=
',' && *CIP !=
'\n'))
117 CPULen = CIP - CPUStart;
124 if (CPUStart ==
nullptr)
125 while (CIP < CPUInfoEnd && *CIP !=
'\n')
129 if (CPUStart ==
nullptr)
133 .
Case(
"604e",
"604e")
135 .
Case(
"7400",
"7400")
136 .
Case(
"7410",
"7400")
137 .
Case(
"7447",
"7400")
138 .
Case(
"7455",
"7450")
140 .
Case(
"POWER4",
"970")
141 .
Case(
"PPC970FX",
"970")
142 .
Case(
"PPC970MP",
"970")
144 .
Case(
"POWER5",
"g5")
146 .
Case(
"POWER6",
"pwr6")
147 .
Case(
"POWER7",
"pwr7")
148 .
Case(
"POWER8",
"pwr8")
149 .
Case(
"POWER8E",
"pwr8")
150 .
Case(
"POWER8NVL",
"pwr8")
151 .
Case(
"POWER9",
"pwr9")
152 .
Case(
"POWER10",
"pwr10")
166 ProcCpuinfoContent.
split(Lines,
"\n");
172 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I) {
174 Implementer = Lines[
I].substr(15).ltrim(
"\t :");
176 Hardware = Lines[
I].substr(8).ltrim(
"\t :");
178 Part = Lines[
I].substr(8).ltrim(
"\t :");
181 if (Implementer ==
"0x41") {
194 .
Case(
"0x926",
"arm926ej-s")
195 .
Case(
"0xb02",
"mpcore")
196 .
Case(
"0xb36",
"arm1136j-s")
197 .
Case(
"0xb56",
"arm1156t2-s")
198 .
Case(
"0xb76",
"arm1176jz-s")
199 .
Case(
"0xc08",
"cortex-a8")
200 .
Case(
"0xc09",
"cortex-a9")
201 .
Case(
"0xc0f",
"cortex-a15")
202 .
Case(
"0xc20",
"cortex-m0")
203 .
Case(
"0xc23",
"cortex-m3")
204 .
Case(
"0xc24",
"cortex-m4")
205 .
Case(
"0xd22",
"cortex-m55")
206 .
Case(
"0xd02",
"cortex-a34")
207 .
Case(
"0xd04",
"cortex-a35")
208 .
Case(
"0xd03",
"cortex-a53")
209 .
Case(
"0xd05",
"cortex-a55")
210 .
Case(
"0xd46",
"cortex-a510")
211 .
Case(
"0xd07",
"cortex-a57")
212 .
Case(
"0xd08",
"cortex-a72")
213 .
Case(
"0xd09",
"cortex-a73")
214 .
Case(
"0xd0a",
"cortex-a75")
215 .
Case(
"0xd0b",
"cortex-a76")
216 .
Case(
"0xd0d",
"cortex-a77")
217 .
Case(
"0xd41",
"cortex-a78")
218 .
Case(
"0xd47",
"cortex-a710")
219 .
Case(
"0xd4d",
"cortex-a715")
220 .
Case(
"0xd44",
"cortex-x1")
221 .
Case(
"0xd4c",
"cortex-x1c")
222 .
Case(
"0xd48",
"cortex-x2")
223 .
Case(
"0xd4e",
"cortex-x3")
224 .
Case(
"0xd0c",
"neoverse-n1")
225 .
Case(
"0xd49",
"neoverse-n2")
226 .
Case(
"0xd40",
"neoverse-v1")
227 .
Case(
"0xd4f",
"neoverse-v2")
231 if (Implementer ==
"0x42" || Implementer ==
"0x43") {
233 .
Case(
"0x516",
"thunderx2t99")
234 .
Case(
"0x0516",
"thunderx2t99")
235 .
Case(
"0xaf",
"thunderx2t99")
236 .
Case(
"0x0af",
"thunderx2t99")
237 .
Case(
"0xa1",
"thunderxt88")
238 .
Case(
"0x0a1",
"thunderxt88")
242 if (Implementer ==
"0x46") {
244 .
Case(
"0x001",
"a64fx")
248 if (Implementer ==
"0x4e") {
250 .
Case(
"0x004",
"carmel")
254 if (Implementer ==
"0x48")
259 .
Case(
"0xd01",
"tsv110")
262 if (Implementer ==
"0x51")
267 .
Case(
"0x06f",
"krait")
268 .
Case(
"0x201",
"kryo")
269 .
Case(
"0x205",
"kryo")
270 .
Case(
"0x211",
"kryo")
271 .
Case(
"0x800",
"cortex-a73")
272 .
Case(
"0x801",
"cortex-a73")
273 .
Case(
"0x802",
"cortex-a75")
274 .
Case(
"0x803",
"cortex-a75")
275 .
Case(
"0x804",
"cortex-a76")
276 .
Case(
"0x805",
"cortex-a76")
277 .
Case(
"0xc00",
"falkor")
278 .
Case(
"0xc01",
"saphira")
280 if (Implementer ==
"0x53") {
283 unsigned Variant = 0, Part = 0;
288 if (
I.consume_front(
"CPU variant"))
289 I.ltrim(
"\t :").getAsInteger(0, Variant);
294 if (
I.consume_front(
"CPU part"))
295 I.ltrim(
"\t :").getAsInteger(0, Part);
297 unsigned Exynos = (Variant << 12) | Part;
309 if (Implementer ==
"0xc0") {
311 .
Case(
"0xac3",
"ampere1")
312 .
Case(
"0xac4",
"ampere1a")
320StringRef getCPUNameFromS390Model(
unsigned int Id,
bool HaveVectorSupport) {
340 return HaveVectorSupport?
"z13" :
"zEC12";
343 return HaveVectorSupport?
"z14" :
"zEC12";
346 return HaveVectorSupport?
"z15" :
"zEC12";
350 return HaveVectorSupport?
"z16" :
"zEC12";
361 ProcCpuinfoContent.
split(Lines,
"\n");
365 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I)
367 size_t Pos = Lines[
I].find(
':');
369 Lines[
I].drop_front(Pos + 1).split(CPUFeatures,
' ');
377 bool HaveVectorSupport =
false;
378 for (
unsigned I = 0,
E = CPUFeatures.size();
I !=
E; ++
I) {
379 if (CPUFeatures[
I] ==
"vx")
380 HaveVectorSupport =
true;
384 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I) {
386 size_t Pos = Lines[
I].find(
"machine = ");
388 Pos +=
sizeof(
"machine = ") - 1;
390 if (!Lines[
I].drop_front(Pos).getAsInteger(10, Id))
391 return getCPUNameFromS390Model(Id, HaveVectorSupport);
403 ProcCpuinfoContent.
split(Lines,
"\n");
407 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I) {
409 UArch = Lines[
I].substr(5).ltrim(
"\t :");
415 .
Case(
"sifive,u74-mc",
"sifive-u74")
416 .
Case(
"sifive,bullet0",
"sifive-u74")
421#if !defined(__linux__) || !defined(__x86_64__)
424 uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
426 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
428 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
430 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
432 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
434 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
436 uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
438 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
440 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
442 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
444 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
446 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
448 struct bpf_prog_load_attr {
464 int fd = syscall(321 , 5 , &attr,
472 memset(&attr, 0,
sizeof(attr));
477 fd = syscall(321 , 5 , &attr,
sizeof(attr));
486#if defined(__i386__) || defined(_M_IX86) || \
487 defined(__x86_64__) || defined(_M_X64)
496static bool isCpuIdSupported() {
497#if defined(__GNUC__) || defined(__clang__)
499 int __cpuid_supported;
502 " movl %%eax,%%ecx\n"
503 " xorl $0x00200000,%%eax\n"
509 " cmpl %%eax,%%ecx\n"
513 :
"=r"(__cpuid_supported)
516 if (!__cpuid_supported)
526static bool getX86CpuIDAndInfo(
unsigned value,
unsigned *rEAX,
unsigned *rEBX,
527 unsigned *rECX,
unsigned *rEDX) {
528#if defined(__GNUC__) || defined(__clang__)
529#if defined(__x86_64__)
532 __asm__(
"movq\t%%rbx, %%rsi\n\t"
534 "xchgq\t%%rbx, %%rsi\n\t"
535 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
538#elif defined(__i386__)
539 __asm__(
"movl\t%%ebx, %%esi\n\t"
541 "xchgl\t%%ebx, %%esi\n\t"
542 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
548#elif defined(_MSC_VER)
551 __cpuid(registers,
value);
552 *rEAX = registers[0];
553 *rEBX = registers[1];
554 *rECX = registers[2];
555 *rEDX = registers[3];
567VendorSignatures getVendorSignature(
unsigned *MaxLeaf) {
568 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
569 if (MaxLeaf ==
nullptr)
574 if (!isCpuIdSupported())
575 return VendorSignatures::UNKNOWN;
577 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)
578 return VendorSignatures::UNKNOWN;
581 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)
582 return VendorSignatures::GENUINE_INTEL;
585 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
586 return VendorSignatures::AUTHENTIC_AMD;
588 return VendorSignatures::UNKNOWN;
601static bool getX86CpuIDAndInfoEx(
unsigned value,
unsigned subleaf,
602 unsigned *rEAX,
unsigned *rEBX,
unsigned *rECX,
604#if defined(__GNUC__) || defined(__clang__)
605#if defined(__x86_64__)
608 __asm__(
"movq\t%%rbx, %%rsi\n\t"
610 "xchgq\t%%rbx, %%rsi\n\t"
611 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
612 :
"a"(
value),
"c"(subleaf));
614#elif defined(__i386__)
615 __asm__(
"movl\t%%ebx, %%esi\n\t"
617 "xchgl\t%%ebx, %%esi\n\t"
618 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
619 :
"a"(
value),
"c"(subleaf));
624#elif defined(_MSC_VER)
626 __cpuidex(registers,
value, subleaf);
627 *rEAX = registers[0];
628 *rEBX = registers[1];
629 *rECX = registers[2];
630 *rEDX = registers[3];
638static bool getX86XCR0(
unsigned *rEAX,
unsigned *rEDX) {
639#if defined(__GNUC__) || defined(__clang__)
643 __asm__(
".byte 0x0f, 0x01, 0xd0" :
"=a"(*rEAX),
"=d"(*rEDX) :
"c"(0));
645#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
646 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
655static void detectX86FamilyModel(
unsigned EAX,
unsigned *Family,
657 *Family = (
EAX >> 8) & 0xf;
659 if (*Family == 6 || *Family == 0xf) {
662 *Family += (
EAX >> 20) & 0xff;
669getIntelProcessorTypeAndSubtype(
unsigned Family,
unsigned Model,
670 const unsigned *Features,
671 unsigned *
Type,
unsigned *Subtype) {
672 auto testFeature = [&](
unsigned F) {
673 return (Features[
F / 32] & (1U << (
F % 32))) != 0;
686 if (testFeature(X86::FEATURE_MMX)) {
702 *
Type = X86::INTEL_CORE2;
711 *
Type = X86::INTEL_CORE2;
720 *
Type = X86::INTEL_COREI7;
721 *Subtype = X86::INTEL_COREI7_NEHALEM;
728 *
Type = X86::INTEL_COREI7;
729 *Subtype = X86::INTEL_COREI7_WESTMERE;
735 *
Type = X86::INTEL_COREI7;
736 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
741 *
Type = X86::INTEL_COREI7;
742 *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
751 *
Type = X86::INTEL_COREI7;
752 *Subtype = X86::INTEL_COREI7_HASWELL;
761 *
Type = X86::INTEL_COREI7;
762 *Subtype = X86::INTEL_COREI7_BROADWELL;
773 *
Type = X86::INTEL_COREI7;
774 *Subtype = X86::INTEL_COREI7_SKYLAKE;
780 *
Type = X86::INTEL_COREI7;
781 *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
786 *
Type = X86::INTEL_COREI7;
787 if (testFeature(X86::FEATURE_AVX512BF16)) {
789 *Subtype = X86::INTEL_COREI7_COOPERLAKE;
790 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
792 *Subtype = X86::INTEL_COREI7_CASCADELAKE;
794 CPU =
"skylake-avx512";
795 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
802 *
Type = X86::INTEL_COREI7;
803 *Subtype = X86::INTEL_COREI7_CANNONLAKE;
809 CPU =
"icelake-client";
810 *
Type = X86::INTEL_COREI7;
811 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
818 *
Type = X86::INTEL_COREI7;
819 *Subtype = X86::INTEL_COREI7_TIGERLAKE;
835 *
Type = X86::INTEL_COREI7;
836 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
842 *
Type = X86::INTEL_COREI7;
843 *Subtype = X86::INTEL_COREI7_ARROWLAKE;
851 *
Type = X86::INTEL_COREI7;
852 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
857 CPU =
"graniterapids";
858 *
Type = X86::INTEL_COREI7;
859 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
864 CPU =
"graniterapids-d";
865 *
Type = X86::INTEL_COREI7;
866 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
872 CPU =
"icelake-server";
873 *
Type = X86::INTEL_COREI7;
874 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
881 CPU =
"sapphirerapids";
882 *
Type = X86::INTEL_COREI7;
883 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
892 *
Type = X86::INTEL_BONNELL;
903 *
Type = X86::INTEL_SILVERMONT;
909 *
Type = X86::INTEL_GOLDMONT;
912 CPU =
"goldmont-plus";
913 *
Type = X86::INTEL_GOLDMONT_PLUS;
920 *
Type = X86::INTEL_TREMONT;
925 CPU =
"sierraforest";
926 *
Type = X86::INTEL_SIERRAFOREST;
932 *
Type = X86::INTEL_GRANDRIDGE;
938 *
Type = X86::INTEL_KNL;
942 *
Type = X86::INTEL_KNM;
949 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
951 }
else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
952 CPU =
"icelake-client";
953 }
else if (testFeature(X86::FEATURE_AVX512VBMI)) {
955 }
else if (testFeature(X86::FEATURE_AVX512BF16)) {
957 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
959 }
else if (testFeature(X86::FEATURE_AVX512VL)) {
960 CPU =
"skylake-avx512";
961 }
else if (testFeature(X86::FEATURE_AVX512ER)) {
963 }
else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
964 if (testFeature(X86::FEATURE_SHA))
968 }
else if (testFeature(X86::FEATURE_ADX)) {
970 }
else if (testFeature(X86::FEATURE_AVX2)) {
972 }
else if (testFeature(X86::FEATURE_AVX)) {
974 }
else if (testFeature(X86::FEATURE_SSE4_2)) {
975 if (testFeature(X86::FEATURE_MOVBE))
979 }
else if (testFeature(X86::FEATURE_SSE4_1)) {
981 }
else if (testFeature(X86::FEATURE_SSSE3)) {
982 if (testFeature(X86::FEATURE_MOVBE))
986 }
else if (testFeature(X86::FEATURE_64BIT)) {
988 }
else if (testFeature(X86::FEATURE_SSE3)) {
990 }
else if (testFeature(X86::FEATURE_SSE2)) {
992 }
else if (testFeature(X86::FEATURE_SSE)) {
994 }
else if (testFeature(X86::FEATURE_MMX)) {
1003 if (testFeature(X86::FEATURE_64BIT)) {
1007 if (testFeature(X86::FEATURE_SSE3)) {
1022getAMDProcessorTypeAndSubtype(
unsigned Family,
unsigned Model,
1023 const unsigned *Features,
1024 unsigned *
Type,
unsigned *Subtype) {
1025 auto testFeature = [&](
unsigned F) {
1026 return (Features[
F / 32] & (1U << (
F % 32))) != 0;
1055 if (testFeature(X86::FEATURE_SSE)) {
1062 if (testFeature(X86::FEATURE_SSE3)) {
1070 *
Type = X86::AMDFAM10H;
1073 *Subtype = X86::AMDFAM10H_BARCELONA;
1076 *Subtype = X86::AMDFAM10H_SHANGHAI;
1079 *Subtype = X86::AMDFAM10H_ISTANBUL;
1085 *
Type = X86::AMD_BTVER1;
1089 *
Type = X86::AMDFAM15H;
1090 if (Model >= 0x60 && Model <= 0x7f) {
1092 *Subtype = X86::AMDFAM15H_BDVER4;
1095 if (Model >= 0x30 && Model <= 0x3f) {
1097 *Subtype = X86::AMDFAM15H_BDVER3;
1100 if ((Model >= 0x10 && Model <= 0x1f) ||
Model == 0x02) {
1102 *Subtype = X86::AMDFAM15H_BDVER2;
1105 if (Model <= 0x0f) {
1106 *Subtype = X86::AMDFAM15H_BDVER1;
1112 *
Type = X86::AMD_BTVER2;
1116 *
Type = X86::AMDFAM17H;
1117 if ((Model >= 0x30 && Model <= 0x3f) ||
Model == 0x71) {
1119 *Subtype = X86::AMDFAM17H_ZNVER2;
1122 if (Model <= 0x0f) {
1123 *Subtype = X86::AMDFAM17H_ZNVER1;
1129 *
Type = X86::AMDFAM19H;
1130 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x5f)) {
1136 *Subtype = X86::AMDFAM19H_ZNVER3;
1139 if ((Model >= 0x10 && Model <= 0x1f) ||
1141 (Model >= 0x78 && Model <= 0x7b) ||
1144 *Subtype = X86::AMDFAM19H_ZNVER4;
1155static void getAvailableFeatures(
unsigned ECX,
unsigned EDX,
unsigned MaxLeaf,
1156 unsigned *Features) {
1159 auto setFeature = [&](
unsigned F) {
1160 Features[
F / 32] |= 1U << (
F % 32);
1163 if ((EDX >> 15) & 1)
1164 setFeature(X86::FEATURE_CMOV);
1165 if ((EDX >> 23) & 1)
1166 setFeature(X86::FEATURE_MMX);
1167 if ((EDX >> 25) & 1)
1168 setFeature(X86::FEATURE_SSE);
1169 if ((EDX >> 26) & 1)
1170 setFeature(X86::FEATURE_SSE2);
1173 setFeature(X86::FEATURE_SSE3);
1175 setFeature(X86::FEATURE_PCLMUL);
1177 setFeature(X86::FEATURE_SSSE3);
1178 if ((ECX >> 12) & 1)
1179 setFeature(X86::FEATURE_FMA);
1180 if ((ECX >> 19) & 1)
1181 setFeature(X86::FEATURE_SSE4_1);
1182 if ((ECX >> 20) & 1) {
1183 setFeature(X86::FEATURE_SSE4_2);
1184 setFeature(X86::FEATURE_CRC32);
1186 if ((ECX >> 23) & 1)
1187 setFeature(X86::FEATURE_POPCNT);
1188 if ((ECX >> 25) & 1)
1189 setFeature(X86::FEATURE_AES);
1191 if ((ECX >> 22) & 1)
1192 setFeature(X86::FEATURE_MOVBE);
1197 const unsigned AVXBits = (1 << 27) | (1 << 28);
1198 bool HasAVX = ((
ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1199 ((
EAX & 0x6) == 0x6);
1200#if defined(__APPLE__)
1204 bool HasAVX512Save =
true;
1207 bool HasAVX512Save = HasAVX && ((
EAX & 0xe0) == 0xe0);
1211 setFeature(X86::FEATURE_AVX);
1214 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1216 if (HasLeaf7 && ((EBX >> 3) & 1))
1217 setFeature(X86::FEATURE_BMI);
1218 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1219 setFeature(X86::FEATURE_AVX2);
1220 if (HasLeaf7 && ((EBX >> 8) & 1))
1221 setFeature(X86::FEATURE_BMI2);
1222 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
1223 setFeature(X86::FEATURE_AVX512F);
1224 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1225 setFeature(X86::FEATURE_AVX512DQ);
1226 if (HasLeaf7 && ((EBX >> 19) & 1))
1227 setFeature(X86::FEATURE_ADX);
1228 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1229 setFeature(X86::FEATURE_AVX512IFMA);
1230 if (HasLeaf7 && ((EBX >> 23) & 1))
1231 setFeature(X86::FEATURE_CLFLUSHOPT);
1232 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
1233 setFeature(X86::FEATURE_AVX512PF);
1234 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
1235 setFeature(X86::FEATURE_AVX512ER);
1236 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1237 setFeature(X86::FEATURE_AVX512CD);
1238 if (HasLeaf7 && ((EBX >> 29) & 1))
1239 setFeature(X86::FEATURE_SHA);
1240 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1241 setFeature(X86::FEATURE_AVX512BW);
1242 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1243 setFeature(X86::FEATURE_AVX512VL);
1245 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1246 setFeature(X86::FEATURE_AVX512VBMI);
1247 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1248 setFeature(X86::FEATURE_AVX512VBMI2);
1249 if (HasLeaf7 && ((ECX >> 8) & 1))
1250 setFeature(X86::FEATURE_GFNI);
1251 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1252 setFeature(X86::FEATURE_VPCLMULQDQ);
1253 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1254 setFeature(X86::FEATURE_AVX512VNNI);
1255 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1256 setFeature(X86::FEATURE_AVX512BITALG);
1257 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1258 setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1260 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1261 setFeature(X86::FEATURE_AVX5124VNNIW);
1262 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1263 setFeature(X86::FEATURE_AVX5124FMAPS);
1264 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1265 setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1269 bool HasLeaf7Subleaf1 =
1270 HasLeaf7 &&
EAX >= 1 &&
1271 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1272 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1273 setFeature(X86::FEATURE_AVX512BF16);
1275 unsigned MaxExtLevel;
1276 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1278 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1279 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1280 if (HasExtLeaf1 && ((ECX >> 6) & 1))
1281 setFeature(X86::FEATURE_SSE4_A);
1282 if (HasExtLeaf1 && ((ECX >> 11) & 1))
1283 setFeature(X86::FEATURE_XOP);
1284 if (HasExtLeaf1 && ((ECX >> 16) & 1))
1285 setFeature(X86::FEATURE_FMA4);
1287 if (HasExtLeaf1 && ((EDX >> 29) & 1))
1288 setFeature(X86::FEATURE_64BIT);
1292 unsigned MaxLeaf = 0;
1294 if (Vendor == VendorSignatures::UNKNOWN)
1298 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1300 unsigned Family = 0,
Model = 0;
1302 detectX86FamilyModel(EAX, &Family, &Model);
1303 getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1308 unsigned Subtype = 0;
1312 if (Vendor == VendorSignatures::GENUINE_INTEL) {
1313 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &
Type,
1315 }
else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
1316 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &
Type,
1326#elif defined(__APPLE__) && defined(__powerpc__)
1328 host_basic_info_data_t hostInfo;
1329 mach_msg_type_number_t infoCount;
1331 infoCount = HOST_BASIC_INFO_COUNT;
1332 mach_port_t hostPort = mach_host_self();
1333 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1335 mach_port_deallocate(mach_task_self(), hostPort);
1337 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1340 switch (hostInfo.cpu_subtype) {
1370#elif defined(__linux__) && defined(__powerpc__)
1376#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1382#elif defined(__linux__) && defined(__s390x__)
1388#elif defined(__MVS__)
1393 int *StartToCVTOffset =
reinterpret_cast<int *
>(0x10);
1396 int ReadValue = *StartToCVTOffset;
1398 ReadValue = (ReadValue & 0x7FFFFFFF);
1399 char *CVT =
reinterpret_cast<char *
>(ReadValue);
1404 Id = decodePackedBCD<uint16_t>(Id,
false);
1408 bool HaveVectorSupport = CVT[244] & 0x80;
1409 return getCPUNameFromS390Model(Id, HaveVectorSupport);
1411#elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
1412#define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1413#define CPUFAMILY_ARM_CYCLONE 0x37a09642
1414#define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1415#define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1416#define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1417#define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1418#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1419#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1420#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1424 size_t Length =
sizeof(Family);
1425 sysctlbyname(
"hw.cpufamily", &Family, &
Length, NULL, 0);
1428 case CPUFAMILY_ARM_SWIFT:
1430 case CPUFAMILY_ARM_CYCLONE:
1432 case CPUFAMILY_ARM_TYPHOON:
1434 case CPUFAMILY_ARM_TWISTER:
1436 case CPUFAMILY_ARM_HURRICANE:
1438 case CPUFAMILY_ARM_MONSOON_MISTRAL:
1440 case CPUFAMILY_ARM_VORTEX_TEMPEST:
1442 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
1444 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
1453 switch (_system_configuration.implementation) {
1455 if (_system_configuration.version == PV_4_3)
1459 if (_system_configuration.version == PV_5)
1463 if (_system_configuration.version == PV_6_Compat)
1483#elif defined(__loongarch__)
1487 __asm__(
"cpucfg %[prid], $zero\n\t" : [prid]
"=r"(processor_id));
1488 switch (processor_id & 0xff00) {
1497#elif defined(__riscv)
1499#if defined(__linux__)
1504#if __riscv_xlen == 64
1505 return "generic-rv64";
1506#elif __riscv_xlen == 32
1507 return "generic-rv32";
1509#error "Unhandled value of __riscv_xlen"
1513#elif defined(__sparc__)
1514#if defined(__linux__)
1517 ProcCpuinfoContent.
split(Lines,
"\n");
1521 for (
unsigned I = 0,
E =
Lines.size();
I !=
E; ++
I) {
1523 Cpu =
Lines[
I].substr(5).ltrim(
"\t :");
1555#if defined(__linux__)
1559#elif defined(__sun__) && defined(__svr4__)
1563 kstat_named_t *brand = NULL;
1567 ksp = kstat_lookup(kc,
const_cast<char *
>(
"cpu_info"), -1, NULL);
1568 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1569 ksp->ks_type == KSTAT_TYPE_NAMED)
1571 (kstat_named_t *)kstat_data_lookup(ksp,
const_cast<char *
>(
"brand"));
1572 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1573 buf = KSTAT_NAMED_STR_PTR(brand);
1578 .
Case(
"TMS390S10",
"supersparc")
1579 .
Case(
"TMS390Z50",
"supersparc")
1582 .
Case(
"MB86904",
"supersparc")
1583 .
Case(
"MB86907",
"supersparc")
1584 .
Case(
"RT623",
"hypersparc")
1585 .
Case(
"RT625",
"hypersparc")
1586 .
Case(
"RT626",
"hypersparc")
1587 .
Case(
"UltraSPARC-I",
"ultrasparc")
1588 .
Case(
"UltraSPARC-II",
"ultrasparc")
1589 .
Case(
"UltraSPARC-IIe",
"ultrasparc")
1590 .
Case(
"UltraSPARC-IIi",
"ultrasparc")
1591 .
Case(
"SPARC64-III",
"ultrasparc")
1592 .
Case(
"SPARC64-IV",
"ultrasparc")
1593 .
Case(
"UltraSPARC-III",
"ultrasparc3")
1594 .
Case(
"UltraSPARC-III+",
"ultrasparc3")
1595 .
Case(
"UltraSPARC-IIIi",
"ultrasparc3")
1596 .
Case(
"UltraSPARC-IIIi+",
"ultrasparc3")
1597 .
Case(
"UltraSPARC-IV",
"ultrasparc3")
1598 .
Case(
"UltraSPARC-IV+",
"ultrasparc3")
1599 .
Case(
"SPARC64-V",
"ultrasparc3")
1600 .
Case(
"SPARC64-VI",
"ultrasparc3")
1601 .
Case(
"SPARC64-VII",
"ultrasparc3")
1602 .
Case(
"UltraSPARC-T1",
"niagara")
1603 .
Case(
"UltraSPARC-T2",
"niagara2")
1604 .
Case(
"UltraSPARC-T2",
"niagara2")
1605 .
Case(
"UltraSPARC-T2+",
"niagara2")
1606 .
Case(
"SPARC-T3",
"niagara3")
1607 .
Case(
"SPARC-T4",
"niagara4")
1608 .
Case(
"SPARC-T5",
"niagara4")
1610 .
Case(
"SPARC-M7",
"niagara4" )
1611 .
Case(
"SPARC-S7",
"niagara4" )
1612 .
Case(
"SPARC-M8",
"niagara4" )
1635#if defined(__i386__) || defined(_M_IX86) || \
1636 defined(__x86_64__) || defined(_M_X64)
1641 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
1644 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1646 Features[
"cx8"] = (
EDX >> 8) & 1;
1647 Features[
"cmov"] = (
EDX >> 15) & 1;
1648 Features[
"mmx"] = (
EDX >> 23) & 1;
1649 Features[
"fxsr"] = (
EDX >> 24) & 1;
1650 Features[
"sse"] = (
EDX >> 25) & 1;
1651 Features[
"sse2"] = (
EDX >> 26) & 1;
1653 Features[
"sse3"] = (
ECX >> 0) & 1;
1654 Features[
"pclmul"] = (
ECX >> 1) & 1;
1655 Features[
"ssse3"] = (
ECX >> 9) & 1;
1656 Features[
"cx16"] = (
ECX >> 13) & 1;
1657 Features[
"sse4.1"] = (
ECX >> 19) & 1;
1658 Features[
"sse4.2"] = (
ECX >> 20) & 1;
1659 Features[
"crc32"] = Features[
"sse4.2"];
1660 Features[
"movbe"] = (
ECX >> 22) & 1;
1661 Features[
"popcnt"] = (
ECX >> 23) & 1;
1662 Features[
"aes"] = (
ECX >> 25) & 1;
1663 Features[
"rdrnd"] = (
ECX >> 30) & 1;
1668 bool HasXSave = ((
ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
1669 bool HasAVXSave = HasXSave && ((
ECX >> 28) & 1) && ((
EAX & 0x6) == 0x6);
1670#if defined(__APPLE__)
1674 bool HasAVX512Save =
true;
1677 bool HasAVX512Save = HasAVXSave && ((
EAX & 0xe0) == 0xe0);
1680 const unsigned AMXBits = (1 << 17) | (1 << 18);
1681 bool HasAMXSave = HasXSave && ((
EAX & AMXBits) == AMXBits);
1683 Features[
"avx"] = HasAVXSave;
1684 Features[
"fma"] = ((
ECX >> 12) & 1) && HasAVXSave;
1686 Features[
"xsave"] = ((
ECX >> 26) & 1) && HasAVXSave;
1687 Features[
"f16c"] = ((
ECX >> 29) & 1) && HasAVXSave;
1689 unsigned MaxExtLevel;
1690 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1692 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1693 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1694 Features[
"sahf"] = HasExtLeaf1 && ((
ECX >> 0) & 1);
1695 Features[
"lzcnt"] = HasExtLeaf1 && ((
ECX >> 5) & 1);
1696 Features[
"sse4a"] = HasExtLeaf1 && ((
ECX >> 6) & 1);
1697 Features[
"prfchw"] = HasExtLeaf1 && ((
ECX >> 8) & 1);
1698 Features[
"xop"] = HasExtLeaf1 && ((
ECX >> 11) & 1) && HasAVXSave;
1699 Features[
"lwp"] = HasExtLeaf1 && ((
ECX >> 15) & 1);
1700 Features[
"fma4"] = HasExtLeaf1 && ((
ECX >> 16) & 1) && HasAVXSave;
1701 Features[
"tbm"] = HasExtLeaf1 && ((
ECX >> 21) & 1);
1702 Features[
"mwaitx"] = HasExtLeaf1 && ((
ECX >> 29) & 1);
1704 Features[
"64bit"] = HasExtLeaf1 && ((
EDX >> 29) & 1);
1708 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1709 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1710 Features[
"clzero"] = HasExtLeaf8 && ((
EBX >> 0) & 1);
1711 Features[
"rdpru"] = HasExtLeaf8 && ((
EBX >> 4) & 1);
1712 Features[
"wbnoinvd"] = HasExtLeaf8 && ((
EBX >> 9) & 1);
1715 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1717 Features[
"fsgsbase"] = HasLeaf7 && ((
EBX >> 0) & 1);
1718 Features[
"sgx"] = HasLeaf7 && ((
EBX >> 2) & 1);
1719 Features[
"bmi"] = HasLeaf7 && ((
EBX >> 3) & 1);
1721 Features[
"avx2"] = HasLeaf7 && ((
EBX >> 5) & 1) && HasAVXSave;
1722 Features[
"bmi2"] = HasLeaf7 && ((
EBX >> 8) & 1);
1723 Features[
"invpcid"] = HasLeaf7 && ((
EBX >> 10) & 1);
1724 Features[
"rtm"] = HasLeaf7 && ((
EBX >> 11) & 1);
1726 Features[
"avx512f"] = HasLeaf7 && ((
EBX >> 16) & 1) && HasAVX512Save;
1727 Features[
"avx512dq"] = HasLeaf7 && ((
EBX >> 17) & 1) && HasAVX512Save;
1728 Features[
"rdseed"] = HasLeaf7 && ((
EBX >> 18) & 1);
1729 Features[
"adx"] = HasLeaf7 && ((
EBX >> 19) & 1);
1730 Features[
"avx512ifma"] = HasLeaf7 && ((
EBX >> 21) & 1) && HasAVX512Save;
1731 Features[
"clflushopt"] = HasLeaf7 && ((
EBX >> 23) & 1);
1732 Features[
"clwb"] = HasLeaf7 && ((
EBX >> 24) & 1);
1733 Features[
"avx512pf"] = HasLeaf7 && ((
EBX >> 26) & 1) && HasAVX512Save;
1734 Features[
"avx512er"] = HasLeaf7 && ((
EBX >> 27) & 1) && HasAVX512Save;
1735 Features[
"avx512cd"] = HasLeaf7 && ((
EBX >> 28) & 1) && HasAVX512Save;
1736 Features[
"sha"] = HasLeaf7 && ((
EBX >> 29) & 1);
1737 Features[
"avx512bw"] = HasLeaf7 && ((
EBX >> 30) & 1) && HasAVX512Save;
1738 Features[
"avx512vl"] = HasLeaf7 && ((
EBX >> 31) & 1) && HasAVX512Save;
1740 Features[
"prefetchwt1"] = HasLeaf7 && ((
ECX >> 0) & 1);
1741 Features[
"avx512vbmi"] = HasLeaf7 && ((
ECX >> 1) & 1) && HasAVX512Save;
1742 Features[
"pku"] = HasLeaf7 && ((
ECX >> 4) & 1);
1743 Features[
"waitpkg"] = HasLeaf7 && ((
ECX >> 5) & 1);
1744 Features[
"avx512vbmi2"] = HasLeaf7 && ((
ECX >> 6) & 1) && HasAVX512Save;
1745 Features[
"shstk"] = HasLeaf7 && ((
ECX >> 7) & 1);
1746 Features[
"gfni"] = HasLeaf7 && ((
ECX >> 8) & 1);
1747 Features[
"vaes"] = HasLeaf7 && ((
ECX >> 9) & 1) && HasAVXSave;
1748 Features[
"vpclmulqdq"] = HasLeaf7 && ((
ECX >> 10) & 1) && HasAVXSave;
1749 Features[
"avx512vnni"] = HasLeaf7 && ((
ECX >> 11) & 1) && HasAVX512Save;
1750 Features[
"avx512bitalg"] = HasLeaf7 && ((
ECX >> 12) & 1) && HasAVX512Save;
1751 Features[
"avx512vpopcntdq"] = HasLeaf7 && ((
ECX >> 14) & 1) && HasAVX512Save;
1752 Features[
"rdpid"] = HasLeaf7 && ((
ECX >> 22) & 1);
1753 Features[
"kl"] = HasLeaf7 && ((
ECX >> 23) & 1);
1754 Features[
"cldemote"] = HasLeaf7 && ((
ECX >> 25) & 1);
1755 Features[
"movdiri"] = HasLeaf7 && ((
ECX >> 27) & 1);
1756 Features[
"movdir64b"] = HasLeaf7 && ((
ECX >> 28) & 1);
1757 Features[
"enqcmd"] = HasLeaf7 && ((
ECX >> 29) & 1);
1759 Features[
"uintr"] = HasLeaf7 && ((
EDX >> 5) & 1);
1760 Features[
"avx512vp2intersect"] =
1761 HasLeaf7 && ((
EDX >> 8) & 1) && HasAVX512Save;
1762 Features[
"serialize"] = HasLeaf7 && ((
EDX >> 14) & 1);
1763 Features[
"tsxldtrk"] = HasLeaf7 && ((
EDX >> 16) & 1);
1774 Features[
"pconfig"] = HasLeaf7 && ((
EDX >> 18) & 1);
1775 Features[
"amx-bf16"] = HasLeaf7 && ((
EDX >> 22) & 1) && HasAMXSave;
1776 Features[
"avx512fp16"] = HasLeaf7 && ((
EDX >> 23) & 1) && HasAVX512Save;
1777 Features[
"amx-tile"] = HasLeaf7 && ((
EDX >> 24) & 1) && HasAMXSave;
1778 Features[
"amx-int8"] = HasLeaf7 && ((
EDX >> 25) & 1) && HasAMXSave;
1781 bool HasLeaf7Subleaf1 =
1782 HasLeaf7 &&
EAX >= 1 &&
1783 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1784 Features[
"sha512"] = HasLeaf7Subleaf1 && ((
EAX >> 0) & 1);
1785 Features[
"sm3"] = HasLeaf7Subleaf1 && ((
EAX >> 1) & 1);
1786 Features[
"sm4"] = HasLeaf7Subleaf1 && ((
EAX >> 2) & 1);
1787 Features[
"raoint"] = HasLeaf7Subleaf1 && ((
EAX >> 3) & 1);
1788 Features[
"avxvnni"] = HasLeaf7Subleaf1 && ((
EAX >> 4) & 1) && HasAVXSave;
1789 Features[
"avx512bf16"] = HasLeaf7Subleaf1 && ((
EAX >> 5) & 1) && HasAVX512Save;
1790 Features[
"amx-fp16"] = HasLeaf7Subleaf1 && ((
EAX >> 21) & 1) && HasAMXSave;
1791 Features[
"cmpccxadd"] = HasLeaf7Subleaf1 && ((
EAX >> 7) & 1);
1792 Features[
"hreset"] = HasLeaf7Subleaf1 && ((
EAX >> 22) & 1);
1793 Features[
"avxifma"] = HasLeaf7Subleaf1 && ((
EAX >> 23) & 1) && HasAVXSave;
1794 Features[
"avxvnniint8"] = HasLeaf7Subleaf1 && ((
EDX >> 4) & 1) && HasAVXSave;
1795 Features[
"avxneconvert"] = HasLeaf7Subleaf1 && ((
EDX >> 5) & 1) && HasAVXSave;
1796 Features[
"amx-complex"] = HasLeaf7Subleaf1 && ((
EDX >> 8) & 1) && HasAMXSave;
1797 Features[
"avxvnniint16"] = HasLeaf7Subleaf1 && ((
EDX >> 10) & 1) && HasAVXSave;
1798 Features[
"prefetchi"] = HasLeaf7Subleaf1 && ((
EDX >> 14) & 1);
1800 bool HasLeafD = MaxLevel >= 0xd &&
1801 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1804 Features[
"xsaveopt"] = HasLeafD && ((
EAX >> 0) & 1) && HasAVXSave;
1805 Features[
"xsavec"] = HasLeafD && ((
EAX >> 1) & 1) && HasAVXSave;
1806 Features[
"xsaves"] = HasLeafD && ((
EAX >> 3) & 1) && HasAVXSave;
1808 bool HasLeaf14 = MaxLevel >= 0x14 &&
1809 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1811 Features[
"ptwrite"] = HasLeaf14 && ((
EBX >> 4) & 1);
1814 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
1815 Features[
"widekl"] = HasLeaf7 && HasLeaf19 && ((
EBX >> 2) & 1);
1819#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1826 P->getBuffer().split(Lines,
"\n");
1831 for (
unsigned I = 0,
E =
Lines.size();
I !=
E; ++
I)
1833 Lines[
I].split(CPUFeatures,
' ');
1837#if defined(__aarch64__)
1839 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1845#if defined(__aarch64__)
1846 .
Case(
"asimd",
"neon")
1847 .
Case(
"fp",
"fp-armv8")
1848 .
Case(
"crc32",
"crc")
1849 .
Case(
"atomics",
"lse")
1851 .
Case(
"sve2",
"sve2")
1853 .
Case(
"half",
"fp16")
1854 .
Case(
"neon",
"neon")
1855 .
Case(
"vfpv3",
"vfp3")
1856 .
Case(
"vfpv3d16",
"vfp3d16")
1857 .
Case(
"vfpv4",
"vfp4")
1858 .
Case(
"idiva",
"hwdiv-arm")
1859 .
Case(
"idivt",
"hwdiv")
1863#if defined(__aarch64__)
1866 if (CPUFeatures[
I] ==
"aes")
1868 else if (CPUFeatures[
I] ==
"pmull")
1869 crypto |= CAP_PMULL;
1870 else if (CPUFeatures[
I] ==
"sha1")
1872 else if (CPUFeatures[
I] ==
"sha2")
1876 if (LLVMFeatureStr !=
"")
1877 Features[LLVMFeatureStr] =
true;
1880#if defined(__aarch64__)
1882 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1883 Features[
"crypto"] =
true;
1888#elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
1890 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE))
1891 Features[
"neon"] =
true;
1892 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
1893 Features[
"crc"] =
true;
1894 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
1895 Features[
"crypto"] =
true;
1899#elif defined(__linux__) && defined(__loongarch__)
1900#include <sys/auxv.h>
1902 unsigned long hwcap = getauxval(AT_HWCAP);
1903 bool HasFPU = hwcap & (1UL << 3);
1905 __asm__(
"cpucfg %[cpucfg2], %[cpucfg2]\n\t" : [cpucfg2]
"+r"(cpucfg2));
1907 Features[
"f"] = HasFPU && (cpucfg2 & (1U << 1));
1908 Features[
"d"] = HasFPU && (cpucfg2 & (1U << 2));
1910 Features[
"lsx"] = hwcap & (1UL << 4);
1911 Features[
"lasx"] = hwcap & (1UL << 5);
1912 Features[
"lvz"] = hwcap & (1UL << 9);
1925 T.setArchName(
"arm");
1926#elif defined(__arm64e__)
1928 T.setArchName(
"arm64e");
1929#elif defined(__aarch64__)
1931 T.setArchName(
"arm64");
1932#elif defined(__x86_64h__)
1934 T.setArchName(
"x86_64h");
1935#elif defined(__x86_64__)
1937 T.setArchName(
"x86_64");
1938#elif defined(__i386__)
1940 T.setArchName(
"i386");
1941#elif defined(__powerpc__)
1943 T.setArchName(
"powerpc");
1945# error "Unimplemented host arch fixup"
1952 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
1958 PT = withHostArch(PT);
1970#if LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO
1972 if (CPU ==
"generic")
1975 <<
" Host CPU: " << CPU <<
'\n';
This file defines the StringMap class.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_ATTRIBUTE_UNUSED
Given that RA is a live value
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
static bool startswith(StringRef Magic, const char(&S)[N])
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Represents either an error or a value T.
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
constexpr bool empty() const
empty - Check if the string is empty.
bool endswith(StringRef Suffix) const
static constexpr size_t npos
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
StringSwitch & StartsWith(StringLiteral S, T Value)
Triple - Helper class for working with autoconf configuration names.
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
std::string normalize() const
Return the normalized form of this triple's string.
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
const std::string & str() const
bool isArch64Bit() const
Test whether the architecture is 64-bit.
bool isArch32Bit() const
Test whether the architecture is 32-bit.
The instances of the Type class are immutable: once they are created, they are never changed.
This class implements an extremely fast bulk output stream that can only output to a stream.
@ CPU_SUBTYPE_POWERPC_970
@ CPU_SUBTYPE_POWERPC_604e
@ CPU_SUBTYPE_POWERPC_603e
@ CPU_SUBTYPE_POWERPC_7400
@ CPU_SUBTYPE_POWERPC_604
@ CPU_SUBTYPE_POWERPC_750
@ CPU_SUBTYPE_POWERPC_601
@ CPU_SUBTYPE_POWERPC_620
@ CPU_SUBTYPE_POWERPC_603ev
@ CPU_SUBTYPE_POWERPC_603
@ CPU_SUBTYPE_POWERPC_7450
@ CPU_SUBTYPE_POWERPC_602
Helper functions to extract CPU details from CPUID on x86.
VendorSignatures getVendorSignature(unsigned *MaxLeaf=nullptr)
Returns the host CPU's vendor.
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
StringRef getHostCPUNameForBPF()
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForRISCV(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForSPARC(StringRef ProcCpuinfoContent)
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
void printDefaultTargetAndDetectedCPU(raw_ostream &OS)
This is a function compatible with cl::AddExtraVersionPrinter, which adds info about the current targ...
bool getHostCPUFeatures(StringMap< bool, MallocAllocator > &Features)
getHostCPUFeatures - Get the LLVM names for the host CPU features.
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
std::string getDefaultTargetTriple()
getDefaultTargetTriple() - Return the default target triple the compiler has been configured to produ...
This is an optimization pass for GlobalISel generic memory operations.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.