LLVM 18.0.0git
MipsISelLowering.h
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1//===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that Mips uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
15#define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16
20#include "Mips.h"
29#include "llvm/IR/CallingConv.h"
30#include "llvm/IR/InlineAsm.h"
31#include "llvm/IR/Type.h"
33#include <algorithm>
34#include <cassert>
35#include <deque>
36#include <utility>
37#include <vector>
38
39namespace llvm {
40
41class Argument;
42class FastISel;
43class FunctionLoweringInfo;
44class MachineBasicBlock;
45class MachineFrameInfo;
46class MachineInstr;
47class MipsCCState;
48class MipsFunctionInfo;
49class MipsSubtarget;
50class MipsTargetMachine;
51class TargetLibraryInfo;
52class TargetRegisterClass;
53
54 namespace MipsISD {
55
56 enum NodeType : unsigned {
57 // Start the numbering from where ISD NodeType finishes.
59
60 // Jump and link (call)
62
63 // Tail call
65
66 // Get the Highest (63-48) 16 bits from a 64-bit immediate
68
69 // Get the Higher (47-32) 16 bits from a 64-bit immediate
71
72 // Get the High 16 bits from a 32/64-bit immediate
73 // No relation with Mips Hi register
75
76 // Get the Lower 16 bits from a 32/64-bit immediate
77 // No relation with Mips Lo register
79
80 // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
82
83 // Get the High 16 bits from a 32-bit immediate for accessing TLS.
85
86 // Handle gp_rel (small data/bss sections) relocation.
88
89 // Thread Pointer
91
92 // Vector Floating Point Multiply and Subtract
94
95 // Floating Point Branch Conditional
97
98 // Floating Point Compare
100
101 // Floating point Abs
103
104 // Floating point select
106
107 // Node used to generate an MTC1 i32 to f64 instruction
109
110 // Floating Point Conditional Moves
113
114 // FP-to-int truncation node.
116
117 // Return
119
120 // Interrupt, exception, error trap Return
122
123 // Software Exception Return.
125
126 // Node used to extract integer from accumulator.
129
130 // Node used to insert integers to accumulator.
132
133 // Mult nodes.
136
137 // MAdd/Sub nodes
142
143 // DivRem(u)
148
151
153
155
157
161
162 // EXTR.W intrinsic nodes.
171
172 // DPA.W intrinsic nodes.
195
202
203 // DSP shift nodes.
207
208 // DSP setcc and select_cc nodes.
211
212 // Vector comparisons.
213 // These take a vector and return a boolean.
218
219 // These take a vector and return a vector bitmask.
225
226 // Vector Shuffle with mask as an operand
227 VSHF, // Generic shuffle
228 SHF, // 4-element set shuffle.
229 ILVEV, // Interleave even elements
230 ILVOD, // Interleave odd elements
231 ILVL, // Interleave left elements
232 ILVR, // Interleave right elements
233 PCKEV, // Pack even elements
234 PCKOD, // Pack odd elements
235
236 // Vector Lane Copy
237 INSVE, // Copy element from one vector to another
238
239 // Combined (XOR (OR $a, $b), -1)
241
242 // Extended vector element extraction
245
246 // Load/Store Left/Right nodes.
254 SDR
255 };
256
257 } // ene namespace MipsISD
258
259 //===--------------------------------------------------------------------===//
260 // TargetLowering Implementation
261 //===--------------------------------------------------------------------===//
262
264 bool isMicroMips;
265
266 public:
268 const MipsSubtarget &STI);
269
270 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
271 const MipsSubtarget &STI);
272
273 /// createFastISel - This method returns a target specific FastISel object,
274 /// or null if the target does not support "fast" ISel.
276 const TargetLibraryInfo *libInfo) const override;
277
278 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
279 return MVT::i32;
280 }
281
283 ISD::NodeType) const override;
284
285 bool isCheapToSpeculateCttz(Type *Ty) const override;
286 bool isCheapToSpeculateCtlz(Type *Ty) const override;
287 bool hasBitTest(SDValue X, SDValue Y) const override;
289 CombineLevel Level) const override;
290
291 /// Return the register type for a given MVT, ensuring vectors are treated
292 /// as a series of gpr sized integers.
294 EVT VT) const override;
295
296 /// Return the number of registers for a given MVT, ensuring vectors are
297 /// treated as a series of gpr sized integers.
300 EVT VT) const override;
301
302 /// Break down vectors to the correct number of gpr sized integers.
304 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
305 unsigned &NumIntermediates, MVT &RegisterVT) const override;
306
307 /// Return the correct alignment for the current calling convention.
309 const DataLayout &DL) const override {
310 const Align ABIAlign = DL.getABITypeAlign(ArgTy);
311 if (ArgTy->isVectorTy())
312 return std::min(ABIAlign, Align(8));
313 return ABIAlign;
314 }
315
317 return ISD::SIGN_EXTEND;
318 }
319
320 /// LowerOperation - Provide custom lowering hooks for some operations.
321 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
322
323 /// ReplaceNodeResults - Replace the results of node with an illegal result
324 /// type with new values built out of custom code.
325 ///
327 SelectionDAG &DAG) const override;
328
329 /// getTargetNodeName - This method returns the name of a target specific
330 // DAG node.
331 const char *getTargetNodeName(unsigned Opcode) const override;
332
333 /// getSetCCResultType - get the ISD::SETCC result ValueType
335 EVT VT) const override;
336
337 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
338
341 MachineBasicBlock *MBB) const override;
342
344 SDNode *Node) const override;
345
346 void HandleByVal(CCState *, unsigned &, Align) const override;
347
348 Register getRegisterByName(const char* RegName, LLT VT,
349 const MachineFunction &MF) const override;
350
351 /// If a physical register, this returns the register that receives the
352 /// exception address on entry to an EH pad.
354 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
355 return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
356 }
357
358 /// If a physical register, this returns the register that receives the
359 /// exception typeid on entry to a landing pad.
361 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
362 return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
363 }
364
365 bool isJumpTableRelative() const override {
367 }
368
370
372
373 protected:
374 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
375
376 // This method creates the following nodes, which are necessary for
377 // computing a local symbol's address:
378 //
379 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
380 template <class NodeTy>
381 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
382 bool IsN32OrN64) const {
383 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
384 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
385 getTargetNode(N, Ty, DAG, GOTFlag));
386 SDValue Load =
387 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
389 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
390 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
391 getTargetNode(N, Ty, DAG, LoFlag));
392 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
393 }
394
395 // This method creates the following nodes, which are necessary for
396 // computing a global symbol's address:
397 //
398 // (load (wrapper $gp, %got(sym)))
399 template <class NodeTy>
400 SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
401 unsigned Flag, SDValue Chain,
402 const MachinePointerInfo &PtrInfo) const {
403 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
404 getTargetNode(N, Ty, DAG, Flag));
405 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
406 }
407
408 // This method creates the following nodes, which are necessary for
409 // computing a global symbol's address in large-GOT mode:
410 //
411 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
412 template <class NodeTy>
414 SelectionDAG &DAG, unsigned HiFlag,
415 unsigned LoFlag, SDValue Chain,
416 const MachinePointerInfo &PtrInfo) const {
418 getTargetNode(N, Ty, DAG, HiFlag));
419 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
421 getTargetNode(N, Ty, DAG, LoFlag));
422 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
423 }
424
425 // This method creates the following nodes, which are necessary for
426 // computing a symbol's address in non-PIC mode:
427 //
428 // (add %hi(sym), %lo(sym))
429 //
430 // This method covers O32, N32 and N64 in sym32 mode.
431 template <class NodeTy>
432 SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
433 SelectionDAG &DAG) const {
434 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
435 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
436 return DAG.getNode(ISD::ADD, DL, Ty,
437 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
438 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
439 }
440
441 // This method creates the following nodes, which are necessary for
442 // computing a symbol's address in non-PIC mode for N64.
443 //
444 // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
445 // 16), %lo(%sym))
446 //
447 // FIXME: This method is not efficent for (micro)MIPS64R6.
448 template <class NodeTy>
449 SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
450 SelectionDAG &DAG) const {
451 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
452 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
453
454 SDValue Highest =
455 DAG.getNode(MipsISD::Highest, DL, Ty,
456 getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
457 SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER);
458 SDValue HigherPart =
459 DAG.getNode(ISD::ADD, DL, Ty, Highest,
460 DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
461 SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
462 SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
463 SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
464 DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
465 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
466
467 return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
468 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
469 }
470
471 // This method creates the following nodes, which are necessary for
472 // computing a symbol's address using gp-relative addressing:
473 //
474 // (add $gp, %gp_rel(sym))
475 template <class NodeTy>
476 SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
477 SelectionDAG &DAG, bool IsN64) const {
478 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
479 return DAG.getNode(
480 ISD::ADD, DL, Ty,
481 DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
482 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
483 }
484
485 /// This function fills Ops, which is the list of operands that will later
486 /// be used when a function call node is created. It also generates
487 /// copyToReg nodes to set up argument registers.
488 virtual void
490 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
491 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
492 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
493 SDValue Chain) const;
494
495 protected:
498
499 // Subtarget Info
501 // Cache the ABI from the TargetMachine, we use it everywhere.
503
504 private:
505 // Create a TargetGlobalAddress node.
506 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
507 unsigned Flag) const;
508
509 // Create a TargetExternalSymbol node.
510 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
511 unsigned Flag) const;
512
513 // Create a TargetBlockAddress node.
514 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
515 unsigned Flag) const;
516
517 // Create a TargetJumpTable node.
518 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
519 unsigned Flag) const;
520
521 // Create a TargetConstantPool node.
522 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
523 unsigned Flag) const;
524
525 // Lower Operand helpers
526 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
527 CallingConv::ID CallConv, bool isVarArg,
529 const SDLoc &dl, SelectionDAG &DAG,
532
533 // Lower Operand specifics
534 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
535 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
536 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
537 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
538 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
539 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
540 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
541 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
542 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
543 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
544 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
545 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
546 SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG,
547 bool HasExtractInsert) const;
548 SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG,
549 bool HasExtractInsert) const;
550 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
551 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
552 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
553 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
554 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
555 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
556 bool IsSRA) const;
557 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
558 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
559
560 /// isEligibleForTailCallOptimization - Check whether the call is eligible
561 /// for tail call optimization.
562 virtual bool
563 isEligibleForTailCallOptimization(const CCState &CCInfo,
564 unsigned NextStackOffset,
565 const MipsFunctionInfo &FI) const = 0;
566
567 /// copyByValArg - Copy argument registers which were used to pass a byval
568 /// argument to the stack. Create a stack frame object for the byval
569 /// argument.
570 void copyByValRegs(SDValue Chain, const SDLoc &DL,
571 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
572 const ISD::ArgFlagsTy &Flags,
574 const Argument *FuncArg, unsigned FirstReg,
575 unsigned LastReg, const CCValAssign &VA,
576 MipsCCState &State) const;
577
578 /// passByValArg - Pass a byval argument in registers or on stack.
579 void passByValArg(SDValue Chain, const SDLoc &DL,
580 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
581 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
582 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg,
583 unsigned FirstReg, unsigned LastReg,
584 const ISD::ArgFlagsTy &Flags, bool isLittle,
585 const CCValAssign &VA) const;
586
587 /// writeVarArgRegs - Write variable function arguments passed in registers
588 /// to the stack. Also create a stack frame object for the first variable
589 /// argument.
590 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
591 const SDLoc &DL, SelectionDAG &DAG,
592 CCState &State) const;
593
594 SDValue
595 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
597 const SDLoc &dl, SelectionDAG &DAG,
598 SmallVectorImpl<SDValue> &InVals) const override;
599
600 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
601 SDValue Arg, const SDLoc &DL, bool IsTailCall,
602 SelectionDAG &DAG) const;
603
605 SmallVectorImpl<SDValue> &InVals) const override;
606
607 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
608 bool isVarArg,
610 LLVMContext &Context) const override;
611
612 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
614 const SmallVectorImpl<SDValue> &OutVals,
615 const SDLoc &dl, SelectionDAG &DAG) const override;
616
617 SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
618 const SDLoc &DL, SelectionDAG &DAG) const;
619
620 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
621
622 // Inline asm support
623 ConstraintType getConstraintType(StringRef Constraint) const override;
624
625 /// Examine constraint string and operand type and determine a weight value.
626 /// The operand object must already have been set up with the operand type.
627 ConstraintWeight getSingleConstraintMatchWeight(
628 AsmOperandInfo &info, const char *constraint) const override;
629
630 /// This function parses registers that appear in inline-asm constraints.
631 /// It returns pair (0, 0) on failure.
632 std::pair<unsigned, const TargetRegisterClass *>
633 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
634
635 std::pair<unsigned, const TargetRegisterClass *>
636 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
637 StringRef Constraint, MVT VT) const override;
638
639 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
640 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
641 /// true it means one of the asm constraint of the inline asm instruction
642 /// being processed is 'm'.
643 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
644 std::vector<SDValue> &Ops,
645 SelectionDAG &DAG) const override;
646
648 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
649 if (ConstraintCode == "o")
651 if (ConstraintCode == "R")
653 if (ConstraintCode == "ZC")
655 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
656 }
657
658 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
659 Type *Ty, unsigned AS,
660 Instruction *I = nullptr) const override;
661
662 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
663
664 EVT getOptimalMemOpType(const MemOp &Op,
665 const AttributeList &FuncAttributes) const override;
666
667 /// isFPImmLegal - Returns true if the target can instruction select the
668 /// specified FP immediate natively. If false, the legalizer will
669 /// materialize the FP immediate as a load from a constant pool.
670 bool isFPImmLegal(const APFloat &Imm, EVT VT,
671 bool ForCodeSize) const override;
672
673 unsigned getJumpTableEncoding() const override;
674 bool useSoftFloat() const override;
675
676 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
677 return true;
678 }
679
680 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
681 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
682 MachineBasicBlock *BB,
683 unsigned Size, unsigned DstReg,
684 unsigned SrcRec) const;
685
686 MachineBasicBlock *emitAtomicBinary(MachineInstr &MI,
687 MachineBasicBlock *BB) const;
688 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
689 MachineBasicBlock *BB,
690 unsigned Size) const;
691 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
692 MachineBasicBlock *BB) const;
693 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
694 MachineBasicBlock *BB,
695 unsigned Size) const;
696 MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
697 MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
698 bool isFPCmp, unsigned Opc) const;
699 MachineBasicBlock *emitPseudoD_SELECT(MachineInstr &MI,
700 MachineBasicBlock *BB) const;
701 MachineBasicBlock *emitLDR_W(MachineInstr &MI, MachineBasicBlock *BB) const;
702 MachineBasicBlock *emitLDR_D(MachineInstr &MI, MachineBasicBlock *BB) const;
703 MachineBasicBlock *emitSTR_W(MachineInstr &MI, MachineBasicBlock *BB) const;
704 MachineBasicBlock *emitSTR_D(MachineInstr &MI, MachineBasicBlock *BB) const;
705 };
706
707 /// Create MipsTargetLowering objects.
708 const MipsTargetLowering *
709 createMips16TargetLowering(const MipsTargetMachine &TM,
710 const MipsSubtarget &STI);
711 const MipsTargetLowering *
712 createMipsSETargetLowering(const MipsTargetMachine &TM,
713 const MipsSubtarget &STI);
714
715namespace Mips {
716
717FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
718 const TargetLibraryInfo *libInfo);
719
720} // end namespace Mips
721
722} // end namespace llvm
723
724#endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu aa AMDGPU Address space based Alias Analysis Wrapper
Function Alias Analysis Results
uint64_t Size
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
IRTranslator LLVM IR MI
#define RegName(no)
lazy value info
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
static constexpr uint32_t Opcode
Definition: aarch32.h:200
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
CCState - This class holds information needed while lowering arguments and return values.
CCValAssign - Represent assignment of one arg/retval to a location.
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Machine Value Type.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Representation of each machine instruction.
Definition: MachineInstr.h:68
bool IsN64() const
Definition: MipsABIInfo.h:42
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Break down vectors to the correct number of gpr sized integers.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
const MipsABIInfo & ABI
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
CCAssignFn * CCAssignFnForReturn() const
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
CCAssignFn * CCAssignFnForCall() const
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
const MipsSubtarget & Subtarget
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
void HandleByVal(CCState *, unsigned &, Align) const override
Target-specific cleanup for formal ByVal parameters.
bool isJumpTableRelative() const override
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const override
Return the correct alignment for the current calling convention.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:469
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:554
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Provides information about what library functions are available for the current target.
const TargetMachine & getTargetMachine() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
bool isPositionIndependent() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:265
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1383
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:774
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:705
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1395
@ MO_GOT
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
@ MO_ABS_HI
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
@ MO_GPREL
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Definition: MipsBaseInfo.h:48
@ MO_HIGHER
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address.
Definition: MipsBaseInfo.h:85
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
CombineLevel
Definition: DAGCombine.h:15
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
@ Add
Sum of integers.
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
This contains information for each constraint that we are lowering.
This structure contains all information that is necessary for lowering calls.