LLVM  13.0.0git
MipsISelLowering.h
Go to the documentation of this file.
1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that Mips uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 
20 #include "Mips.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/IR/Type.h"
33 #include <algorithm>
34 #include <cassert>
35 #include <deque>
36 #include <string>
37 #include <utility>
38 #include <vector>
39 
40 namespace llvm {
41 
42 class Argument;
43 class FastISel;
44 class FunctionLoweringInfo;
45 class MachineBasicBlock;
46 class MachineFrameInfo;
47 class MachineInstr;
48 class MipsCCState;
49 class MipsFunctionInfo;
50 class MipsSubtarget;
51 class MipsTargetMachine;
52 class TargetLibraryInfo;
53 class TargetRegisterClass;
54 
55  namespace MipsISD {
56 
57  enum NodeType : unsigned {
58  // Start the numbering from where ISD NodeType finishes.
60 
61  // Jump and link (call)
63 
64  // Tail call
66 
67  // Get the Highest (63-48) 16 bits from a 64-bit immediate
69 
70  // Get the Higher (47-32) 16 bits from a 64-bit immediate
72 
73  // Get the High 16 bits from a 32/64-bit immediate
74  // No relation with Mips Hi register
75  Hi,
76 
77  // Get the Lower 16 bits from a 32/64-bit immediate
78  // No relation with Mips Lo register
79  Lo,
80 
81  // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
83 
84  // Get the High 16 bits from a 32-bit immediate for accessing TLS.
86 
87  // Handle gp_rel (small data/bss sections) relocation.
89 
90  // Thread Pointer
92 
93  // Vector Floating Point Multiply and Subtract
94  FMS,
95 
96  // Floating Point Branch Conditional
98 
99  // Floating Point Compare
101 
102  // Floating point select
104 
105  // Node used to generate an MTC1 i32 to f64 instruction
107 
108  // Floating Point Conditional Moves
111 
112  // FP-to-int truncation node.
114 
115  // Return
117 
118  // Interrupt, exception, error trap Return
120 
121  // Software Exception Return.
123 
124  // Node used to extract integer from accumulator.
127 
128  // Node used to insert integers to accumulator.
130 
131  // Mult nodes.
134 
135  // MAdd/Sub nodes
140 
141  // DivRem(u)
146 
149 
151 
153 
155 
159 
160  // EXTR.W instrinsic nodes.
169 
170  // DPA.W intrinsic nodes.
193 
200 
201  // DSP shift nodes.
205 
206  // DSP setcc and select_cc nodes.
209 
210  // Vector comparisons.
211  // These take a vector and return a boolean.
216 
217  // These take a vector and return a vector bitmask.
223 
224  // Vector Shuffle with mask as an operand
225  VSHF, // Generic shuffle
226  SHF, // 4-element set shuffle.
227  ILVEV, // Interleave even elements
228  ILVOD, // Interleave odd elements
229  ILVL, // Interleave left elements
230  ILVR, // Interleave right elements
231  PCKEV, // Pack even elements
232  PCKOD, // Pack odd elements
233 
234  // Vector Lane Copy
235  INSVE, // Copy element from one vector to another
236 
237  // Combined (XOR (OR $a, $b), -1)
239 
240  // Extended vector element extraction
243 
244  // Load/Store Left/Right nodes.
253  };
254 
255  } // ene namespace MipsISD
256 
257  //===--------------------------------------------------------------------===//
258  // TargetLowering Implementation
259  //===--------------------------------------------------------------------===//
260 
262  bool isMicroMips;
263 
264  public:
265  explicit MipsTargetLowering(const MipsTargetMachine &TM,
266  const MipsSubtarget &STI);
267 
268  static const MipsTargetLowering *create(const MipsTargetMachine &TM,
269  const MipsSubtarget &STI);
270 
271  /// createFastISel - This method returns a target specific FastISel object,
272  /// or null if the target does not support "fast" ISel.
274  const TargetLibraryInfo *libInfo) const override;
275 
276  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
277  return MVT::i32;
278  }
279 
281  ISD::NodeType) const override;
282 
283  bool isCheapToSpeculateCttz() const override;
284  bool isCheapToSpeculateCtlz() const override;
286  CombineLevel Level) const override;
287 
288  /// Return the register type for a given MVT, ensuring vectors are treated
289  /// as a series of gpr sized integers.
291  EVT VT) const override;
292 
293  /// Return the number of registers for a given MVT, ensuring vectors are
294  /// treated as a series of gpr sized integers.
296  CallingConv::ID CC,
297  EVT VT) const override;
298 
299  /// Break down vectors to the correct number of gpr sized integers.
301  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
302  unsigned &NumIntermediates, MVT &RegisterVT) const override;
303 
304  /// Return the correct alignment for the current calling convention.
306  DataLayout DL) const override {
307  const Align ABIAlign = DL.getABITypeAlign(ArgTy);
308  if (ArgTy->isVectorTy())
309  return std::min(ABIAlign, Align(8));
310  return ABIAlign;
311  }
312 
314  return ISD::SIGN_EXTEND;
315  }
316 
317  /// LowerOperation - Provide custom lowering hooks for some operations.
318  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
319 
320  /// ReplaceNodeResults - Replace the results of node with an illegal result
321  /// type with new values built out of custom code.
322  ///
324  SelectionDAG &DAG) const override;
325 
326  /// getTargetNodeName - This method returns the name of a target specific
327  // DAG node.
328  const char *getTargetNodeName(unsigned Opcode) const override;
329 
330  /// getSetCCResultType - get the ISD::SETCC result ValueType
332  EVT VT) const override;
333 
334  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
335 
338  MachineBasicBlock *MBB) const override;
339 
341  SDNode *Node) const override;
342 
343  void HandleByVal(CCState *, unsigned &, Align) const override;
344 
345  Register getRegisterByName(const char* RegName, LLT VT,
346  const MachineFunction &MF) const override;
347 
348  /// If a physical register, this returns the register that receives the
349  /// exception address on entry to an EH pad.
350  Register
351  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
352  return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
353  }
354 
355  /// If a physical register, this returns the register that receives the
356  /// exception typeid on entry to a landing pad.
357  Register
358  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
359  return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
360  }
361 
362  bool isJumpTableRelative() const override {
364  }
365 
366  CCAssignFn *CCAssignFnForCall() const;
367 
369 
370  protected:
371  SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
372 
373  // This method creates the following nodes, which are necessary for
374  // computing a local symbol's address:
375  //
376  // (add (load (wrapper $gp, %got(sym)), %lo(sym))
377  template <class NodeTy>
378  SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
379  bool IsN32OrN64) const {
380  unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
381  SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
382  getTargetNode(N, Ty, DAG, GOTFlag));
383  SDValue Load =
384  DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
386  unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
387  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
388  getTargetNode(N, Ty, DAG, LoFlag));
389  return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
390  }
391 
392  // This method creates the following nodes, which are necessary for
393  // computing a global symbol's address:
394  //
395  // (load (wrapper $gp, %got(sym)))
396  template <class NodeTy>
397  SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
398  unsigned Flag, SDValue Chain,
399  const MachinePointerInfo &PtrInfo) const {
400  SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
401  getTargetNode(N, Ty, DAG, Flag));
402  return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
403  }
404 
405  // This method creates the following nodes, which are necessary for
406  // computing a global symbol's address in large-GOT mode:
407  //
408  // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
409  template <class NodeTy>
410  SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
411  SelectionDAG &DAG, unsigned HiFlag,
412  unsigned LoFlag, SDValue Chain,
413  const MachinePointerInfo &PtrInfo) const {
414  SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
415  getTargetNode(N, Ty, DAG, HiFlag));
416  Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
418  getTargetNode(N, Ty, DAG, LoFlag));
419  return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
420  }
421 
422  // This method creates the following nodes, which are necessary for
423  // computing a symbol's address in non-PIC mode:
424  //
425  // (add %hi(sym), %lo(sym))
426  //
427  // This method covers O32, N32 and N64 in sym32 mode.
428  template <class NodeTy>
429  SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
430  SelectionDAG &DAG) const {
431  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
432  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
433  return DAG.getNode(ISD::ADD, DL, Ty,
434  DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
435  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
436  }
437 
438  // This method creates the following nodes, which are necessary for
439  // computing a symbol's address in non-PIC mode for N64.
440  //
441  // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
442  // 16), %lo(%sym))
443  //
444  // FIXME: This method is not efficent for (micro)MIPS64R6.
445  template <class NodeTy>
446  SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
447  SelectionDAG &DAG) const {
448  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
449  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
450 
451  SDValue Highest =
452  DAG.getNode(MipsISD::Highest, DL, Ty,
453  getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
454  SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER);
455  SDValue HigherPart =
456  DAG.getNode(ISD::ADD, DL, Ty, Highest,
457  DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
458  SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
459  SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
460  SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
461  DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
462  SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
463 
464  return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
465  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
466  }
467 
468  // This method creates the following nodes, which are necessary for
469  // computing a symbol's address using gp-relative addressing:
470  //
471  // (add $gp, %gp_rel(sym))
472  template <class NodeTy>
473  SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
474  SelectionDAG &DAG, bool IsN64) const {
475  SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
476  return DAG.getNode(
477  ISD::ADD, DL, Ty,
478  DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
479  DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
480  }
481 
482  /// This function fills Ops, which is the list of operands that will later
483  /// be used when a function call node is created. It also generates
484  /// copyToReg nodes to set up argument registers.
485  virtual void
487  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
488  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
489  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
490  SDValue Chain) const;
491 
492  protected:
493  SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
495 
496  // Subtarget Info
498  // Cache the ABI from the TargetMachine, we use it everywhere.
499  const MipsABIInfo &ABI;
500 
501  private:
502  // Create a TargetGlobalAddress node.
503  SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
504  unsigned Flag) const;
505 
506  // Create a TargetExternalSymbol node.
507  SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
508  unsigned Flag) const;
509 
510  // Create a TargetBlockAddress node.
511  SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
512  unsigned Flag) const;
513 
514  // Create a TargetJumpTable node.
515  SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
516  unsigned Flag) const;
517 
518  // Create a TargetConstantPool node.
519  SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
520  unsigned Flag) const;
521 
522  // Lower Operand helpers
523  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
524  CallingConv::ID CallConv, bool isVarArg,
526  const SDLoc &dl, SelectionDAG &DAG,
527  SmallVectorImpl<SDValue> &InVals,
529 
530  // Lower Operand specifics
531  SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
532  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
533  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
534  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
535  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
536  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
537  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
538  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
539  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
540  SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
541  SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
542  SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
543  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
544  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
545  SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
546  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
547  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
548  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
549  bool IsSRA) const;
550  SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
551  SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
552 
553  /// isEligibleForTailCallOptimization - Check whether the call is eligible
554  /// for tail call optimization.
555  virtual bool
556  isEligibleForTailCallOptimization(const CCState &CCInfo,
557  unsigned NextStackOffset,
558  const MipsFunctionInfo &FI) const = 0;
559 
560  /// copyByValArg - Copy argument registers which were used to pass a byval
561  /// argument to the stack. Create a stack frame object for the byval
562  /// argument.
563  void copyByValRegs(SDValue Chain, const SDLoc &DL,
564  std::vector<SDValue> &OutChains, SelectionDAG &DAG,
565  const ISD::ArgFlagsTy &Flags,
566  SmallVectorImpl<SDValue> &InVals,
567  const Argument *FuncArg, unsigned FirstReg,
568  unsigned LastReg, const CCValAssign &VA,
569  MipsCCState &State) const;
570 
571  /// passByValArg - Pass a byval argument in registers or on stack.
572  void passByValArg(SDValue Chain, const SDLoc &DL,
573  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
574  SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
576  unsigned FirstReg, unsigned LastReg,
577  const ISD::ArgFlagsTy &Flags, bool isLittle,
578  const CCValAssign &VA) const;
579 
580  /// writeVarArgRegs - Write variable function arguments passed in registers
581  /// to the stack. Also create a stack frame object for the first variable
582  /// argument.
583  void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
584  const SDLoc &DL, SelectionDAG &DAG,
585  CCState &State) const;
586 
587  SDValue
588  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
590  const SDLoc &dl, SelectionDAG &DAG,
591  SmallVectorImpl<SDValue> &InVals) const override;
592 
593  SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
594  SDValue Arg, const SDLoc &DL, bool IsTailCall,
595  SelectionDAG &DAG) const;
596 
598  SmallVectorImpl<SDValue> &InVals) const override;
599 
600  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
601  bool isVarArg,
603  LLVMContext &Context) const override;
604 
605  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
607  const SmallVectorImpl<SDValue> &OutVals,
608  const SDLoc &dl, SelectionDAG &DAG) const override;
609 
610  SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
611  const SDLoc &DL, SelectionDAG &DAG) const;
612 
613  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
614 
615  // Inline asm support
616  ConstraintType getConstraintType(StringRef Constraint) const override;
617 
618  /// Examine constraint string and operand type and determine a weight value.
619  /// The operand object must already have been set up with the operand type.
620  ConstraintWeight getSingleConstraintMatchWeight(
621  AsmOperandInfo &info, const char *constraint) const override;
622 
623  /// This function parses registers that appear in inline-asm constraints.
624  /// It returns pair (0, 0) on failure.
625  std::pair<unsigned, const TargetRegisterClass *>
626  parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
627 
628  std::pair<unsigned, const TargetRegisterClass *>
629  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
630  StringRef Constraint, MVT VT) const override;
631 
632  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
633  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
634  /// true it means one of the asm constraint of the inline asm instruction
635  /// being processed is 'm'.
636  void LowerAsmOperandForConstraint(SDValue Op,
637  std::string &Constraint,
638  std::vector<SDValue> &Ops,
639  SelectionDAG &DAG) const override;
640 
641  unsigned
642  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
643  if (ConstraintCode == "o")
645  if (ConstraintCode == "R")
647  if (ConstraintCode == "ZC")
649  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
650  }
651 
652  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
653  Type *Ty, unsigned AS,
654  Instruction *I = nullptr) const override;
655 
656  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
657 
658  EVT getOptimalMemOpType(const MemOp &Op,
659  const AttributeList &FuncAttributes) const override;
660 
661  /// isFPImmLegal - Returns true if the target can instruction select the
662  /// specified FP immediate natively. If false, the legalizer will
663  /// materialize the FP immediate as a load from a constant pool.
664  bool isFPImmLegal(const APFloat &Imm, EVT VT,
665  bool ForCodeSize) const override;
666 
667  unsigned getJumpTableEncoding() const override;
668  bool useSoftFloat() const override;
669 
670  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
671  return true;
672  }
673 
674  /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
675  MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
676  MachineBasicBlock *BB,
677  unsigned Size, unsigned DstReg,
678  unsigned SrcRec) const;
679 
680  MachineBasicBlock *emitAtomicBinary(MachineInstr &MI,
681  MachineBasicBlock *BB) const;
682  MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
683  MachineBasicBlock *BB,
684  unsigned Size) const;
685  MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
686  MachineBasicBlock *BB) const;
687  MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
688  MachineBasicBlock *BB,
689  unsigned Size) const;
690  MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
691  MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
692  bool isFPCmp, unsigned Opc) const;
693  MachineBasicBlock *emitPseudoD_SELECT(MachineInstr &MI,
694  MachineBasicBlock *BB) const;
695  MachineBasicBlock *emitLDR_W(MachineInstr &MI, MachineBasicBlock *BB) const;
696  MachineBasicBlock *emitLDR_D(MachineInstr &MI, MachineBasicBlock *BB) const;
697  MachineBasicBlock *emitSTR_W(MachineInstr &MI, MachineBasicBlock *BB) const;
698  MachineBasicBlock *emitSTR_D(MachineInstr &MI, MachineBasicBlock *BB) const;
699  };
700 
701  /// Create MipsTargetLowering objects.
702  const MipsTargetLowering *
703  createMips16TargetLowering(const MipsTargetMachine &TM,
704  const MipsSubtarget &STI);
705  const MipsTargetLowering *
706  createMipsSETargetLowering(const MipsTargetMachine &TM,
707  const MipsSubtarget &STI);
708 
709 namespace Mips {
710 
711 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
712  const TargetLibraryInfo *libInfo);
713 
714 } // end namespace Mips
715 
716 } // end namespace llvm
717 
718 #endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
ValueTypes.h
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::MipsTargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
Definition: MipsISelLowering.cpp:111
llvm::MipsABIInfo::IsN64
bool IsN64() const
Definition: MipsABIInfo.h:42
llvm::MipsTargetMachine
Definition: MipsTargetMachine.h:27
llvm::MipsISD::EH_RETURN
@ EH_RETURN
Definition: MipsISelLowering.h:122
MipsBaseInfo.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
llvm::MipsISD::VEXTRACT_SEXT_ELT
@ VEXTRACT_SEXT_ELT
Definition: MipsISelLowering.h:241
llvm::MipsISD::JmpLink
@ JmpLink
Definition: MipsISelLowering.h:62
llvm::MipsISD::DPSU_H_QBL
@ DPSU_H_QBL
Definition: MipsISelLowering.h:178
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::MipsISD::VALL_ZERO
@ VALL_ZERO
Definition: MipsISelLowering.h:212
llvm::InlineAsm::Constraint_o
@ Constraint_o
Definition: InlineAsm.h:246
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4101
llvm::MipsTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: MipsISelLowering.h:358
llvm::MipsTargetLowering::HandleByVal
void HandleByVal(CCState *, unsigned &, Align) const override
Target-specific cleanup for formal ByVal parameters.
Definition: MipsISelLowering.cpp:4511
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::MipsISD::VCLT_U
@ VCLT_U
Definition: MipsISelLowering.h:222
llvm::MipsABIInfo
Definition: MipsABIInfo.h:22
llvm::MipsISD::NodeType
NodeType
Definition: MipsISelLowering.h:57
llvm::MipsTargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
Definition: MipsISelLowering.cpp:121
llvm::Mips::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Definition: MipsFastISel.cpp:2149
llvm::MipsTargetLowering::getAddrGlobalLargeGOT
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
Definition: MipsISelLowering.h:410
llvm::MipsISD::FPBrcond
@ FPBrcond
Definition: MipsISelLowering.h:97
llvm::MipsISD::LDL
@ LDL
Definition: MipsISelLowering.h:249
Wrapper
amdgpu aa AMDGPU Address space based Alias Analysis Wrapper
Definition: AMDGPUAliasAnalysis.cpp:30
InlineAsm.h
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:7967
llvm::MipsISD::PCKEV
@ PCKEV
Definition: MipsISelLowering.h:231
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
llvm::MipsISD::VANY_NONZERO
@ VANY_NONZERO
Definition: MipsISelLowering.h:215
llvm::MipsISD::ILVR
@ ILVR
Definition: MipsISelLowering.h:230
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::MemOp
Definition: TargetLowering.h:108
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::MipsISD::MULTU
@ MULTU
Definition: MipsISelLowering.h:195
Shift
bool Shift
Definition: README.txt:468
llvm::MipsISD::ExtractElementF64
@ ExtractElementF64
Definition: MipsISelLowering.h:148
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::AttributeList
Definition: Attributes.h:385
llvm::MipsTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: MipsISelLowering.cpp:1183
llvm::MipsTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: MipsISelLowering.cpp:1153
llvm::MipsISD::SDL
@ SDL
Definition: MipsISelLowering.h:251
llvm::MipsTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: MipsISelLowering.h:351
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:849
llvm::MipsISD::Multu
@ Multu
Definition: MipsISelLowering.h:133
llvm::MipsTargetLowering::MipsTargetLowering
MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Definition: MipsISelLowering.cpp:298
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::MipsISD::LWR
@ LWR
Definition: MipsISelLowering.h:246
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2106
llvm::MipsISD::MFHI
@ MFHI
Definition: MipsISelLowering.h:125
SelectionDAG.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MipsTargetLowering::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
Definition: MipsISelLowering.cpp:539
llvm::MipsISD::MAQ_SA_W_PHL
@ MAQ_SA_W_PHL
Definition: MipsISelLowering.h:174
llvm::MipsISD::MFLO
@ MFLO
Definition: MipsISelLowering.h:126
llvm::MipsFunctionInfo
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
Definition: MipsMachineFunction.h:25
llvm::MipsTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: MipsISelLowering.cpp:1283
llvm::MipsTargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: MipsISelLowering.h:313
llvm::MipsISD::MAdd
@ MAdd
Definition: MipsISelLowering.h:136
llvm::MipsTargetLowering::getAddrGlobal
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
Definition: MipsISelLowering.h:397
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:1952
llvm::MipsISD::Hi
@ Hi
Definition: MipsISelLowering.h:75
MachineValueType.h
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::MipsTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
Definition: MipsISelLowering.cpp:1199
llvm::MipsTargetLowering::lowerSTORE
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
Definition: MipsISelLowering.cpp:2791
TargetLowering.h
llvm::MipsISD::EXTR_RS_W
@ EXTR_RS_W
Definition: MipsISelLowering.h:166
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7246
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2148
llvm::MipsII::MO_GOT_OFST
@ MO_GOT_OFST
Definition: MipsBaseInfo.h:81
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
TargetMachine.h
llvm::MipsISD::DPSU_H_QBR
@ DPSU_H_QBR
Definition: MipsISelLowering.h:179
llvm::MipsISD::MTHLIP
@ MTHLIP
Definition: MipsISelLowering.h:168
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
SelectionDAGNodes.h
llvm::MipsISD::MULT
@ MULT
Definition: MipsISelLowering.h:194
llvm::MipsTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: MipsISelLowering.cpp:4713
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::MipsISD::MADD_DSP
@ MADD_DSP
Definition: MipsISelLowering.h:196
llvm::MipsISD::VEXTRACT_ZEXT_ELT
@ VEXTRACT_ZEXT_ELT
Definition: MipsISelLowering.h:242
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1346
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1795
llvm::MipsTargetLowering::getAddrGPRel
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
Definition: MipsISelLowering.h:473
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3141
llvm::MipsTargetLowering::getOpndList
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue >> &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
Definition: MipsISelLowering.cpp:3020
llvm::MipsISD::VCLE_S
@ VCLE_S
Definition: MipsISelLowering.h:219
Mips.h
llvm::MipsISD::MADDU_DSP
@ MADDU_DSP
Definition: MipsISelLowering.h:197
llvm::MipsISD::CMovFP_T
@ CMovFP_T
Definition: MipsISelLowering.h:109
llvm::Type::isVectorTy
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:235
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition: MachineOperand.cpp:1004
llvm::InlineAsm::Constraint_R
@ Constraint_R
Definition: InlineAsm.h:250
llvm::MipsII::MO_HIGHEST
@ MO_HIGHEST
Definition: MipsBaseInfo.h:86
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::MipsISD::DPAU_H_QBR
@ DPAU_H_QBR
Definition: MipsISelLowering.h:177
llvm::MipsISD::LWL
@ LWL
Definition: MipsISelLowering.h:245
llvm::Instruction
Definition: Instruction.h:45
llvm::MipsISD::Highest
@ Highest
Definition: MipsISelLowering.h:68
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::MipsISD::DPAX_W_PH
@ DPAX_W_PH
Definition: MipsISelLowering.h:188
llvm::MipsISD::DivRem
@ DivRem
Definition: MipsISelLowering.h:142
llvm::MipsISD::DynAlloc
@ DynAlloc
Definition: MipsISelLowering.h:152
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MipsII::MO_ABS_LO
@ MO_ABS_LO
Definition: MipsBaseInfo.h:53
llvm::MipsISD::ThreadPointer
@ ThreadPointer
Definition: MipsISelLowering.h:91
llvm::MipsISD::MTLOHI
@ MTLOHI
Definition: MipsISelLowering.h:129
llvm::MipsISD::MSUBU_DSP
@ MSUBU_DSP
Definition: MipsISelLowering.h:199
llvm::MipsTargetLowering::getAddrNonPIC
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
Definition: MipsISelLowering.h:429
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MipsISD::FSELECT
@ FSELECT
Definition: MipsISelLowering.h:103
Type.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MipsTargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Definition: MipsISelLowering.h:276
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:44
llvm::MipsISD::SHLL_DSP
@ SHLL_DSP
Definition: MipsISelLowering.h:202
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::MipsISD::PCKOD
@ PCKOD
Definition: MipsISelLowering.h:232
llvm::APFloat
Definition: APFloat.h:701
llvm::MipsISD::MSub
@ MSub
Definition: MipsISelLowering.h:138
llvm::MipsISD::Ext
@ Ext
Definition: MipsISelLowering.h:156
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::MipsTargetLowering::shouldFoldConstantShiftPairToMask
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
Definition: MipsISelLowering.cpp:1191
llvm::MipsISD::ILVL
@ ILVL
Definition: MipsISelLowering.h:229
llvm::MipsISD::CIns
@ CIns
Definition: MipsISelLowering.h:158
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Break down vectors to the correct number of gpr sized integers.
Definition: MipsISelLowering.cpp:129
llvm::MipsTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
Definition: MipsISelLowering.cpp:1206
llvm::MipsTargetLowering::lowerLOAD
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
Definition: MipsISelLowering.cpp:2665
llvm::MipsTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: MipsISelLowering.cpp:1187
llvm::MipsTargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall() const
Definition: MipsISelLowering.cpp:2984
llvm::MipsTargetLowering::getAddrNonPICSym64
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
Definition: MipsISelLowering.h:446
llvm::MipsTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
Definition: MipsISelLowering.cpp:558
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:37
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::MipsISD::VALL_NONZERO
@ VALL_NONZERO
Definition: MipsISelLowering.h:214
llvm::MipsTargetLowering::getTypeForExtReturn
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
Definition: MipsISelLowering.cpp:4009
llvm::MipsISD::DPSX_W_PH
@ DPSX_W_PH
Definition: MipsISelLowering.h:189
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:7732
llvm::MipsISD::MAQ_S_W_PHL
@ MAQ_S_W_PHL
Definition: MipsISelLowering.h:172
llvm::TargetLowering::AsmOperandInfo
This contains information for each constraint that we are lowering.
Definition: TargetLowering.h:4127
llvm::MipsISD::DPSQ_SA_L_W
@ DPSQ_SA_L_W
Definition: MipsISelLowering.h:183
llvm::MipsTargetLowering::getABIAlignmentForCallingConv
Align getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override
Return the correct alignment for the current calling convention.
Definition: MipsISelLowering.h:305
llvm::MipsISD::VSHF
@ VSHF
Definition: MipsISelLowering.h:225
llvm::createMipsSETargetLowering
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Definition: MipsSEISelLowering.cpp:303
llvm::MipsISD::ILVOD
@ ILVOD
Definition: MipsISelLowering.h:228
llvm::MipsISD::MAQ_SA_W_PHR
@ MAQ_SA_W_PHR
Definition: MipsISelLowering.h:175
llvm::MipsISD::SWR
@ SWR
Definition: MipsISelLowering.h:248
llvm::MipsISD::DivRem16
@ DivRem16
Definition: MipsISelLowering.h:144
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3692
llvm::MipsTargetLowering::isJumpTableRelative
bool isJumpTableRelative() const override
Definition: MipsISelLowering.h:362
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::MipsISD::VCLE_U
@ VCLE_U
Definition: MipsISelLowering.h:220
MipsMCTargetDesc.h
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::MipsISD::Sync
@ Sync
Definition: MipsISelLowering.h:154
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::MipsISD::SHRL_DSP
@ SHRL_DSP
Definition: MipsISelLowering.h:204
llvm::MipsTargetLowering::getAddrLocal
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
Definition: MipsISelLowering.h:378
info
lazy value info
Definition: LazyValueInfo.cpp:59
llvm::MipsISD::ILVEV
@ ILVEV
Definition: MipsISelLowering.h:227
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::MipsISD::DPAQX_S_W_PH
@ DPAQX_S_W_PH
Definition: MipsISelLowering.h:186
llvm::MipsISD::SHRA_DSP
@ SHRA_DSP
Definition: MipsISelLowering.h:203
llvm::MipsISD::DPSQX_S_W_PH
@ DPSQX_S_W_PH
Definition: MipsISelLowering.h:190
llvm::MipsISD::INSVE
@ INSVE
Definition: MipsISelLowering.h:235
llvm::MipsII::MO_GOT
@ MO_GOT
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
llvm::MipsISD::EXTP
@ EXTP
Definition: MipsISelLowering.h:161
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::MipsISD::EXTR_W
@ EXTR_W
Definition: MipsISelLowering.h:164
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1816
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MipsISD::GPRel
@ GPRel
Definition: MipsISelLowering.h:88
llvm::MipsTargetLowering::AdjustInstrPostInstrSelection
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
Definition: MipsISelLowering.cpp:3079
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::MipsISD::SETCC_DSP
@ SETCC_DSP
Definition: MipsISelLowering.h:207
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::MipsISD::MULSAQ_S_W_PH
@ MULSAQ_S_W_PH
Definition: MipsISelLowering.h:171
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1230
llvm::MipsISD::SELECT_CC_DSP
@ SELECT_CC_DSP
Definition: MipsISelLowering.h:208
Node
Definition: ItaniumDemangle.h:114
llvm::MipsSubtarget
Definition: MipsSubtarget.h:39
llvm::MipsISD::TailCall
@ TailCall
Definition: MipsISelLowering.h:65
llvm::MipsTargetLowering
Definition: MipsISelLowering.h:261
llvm::MipsISD::CMovFP_F
@ CMovFP_F
Definition: MipsISelLowering.h:110
llvm::MipsISD::SWL
@ SWL
Definition: MipsISelLowering.h:247
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MipsISD::MAQ_S_W_PHR
@ MAQ_S_W_PHR
Definition: MipsISelLowering.h:173
llvm::MipsISD::VCEQ
@ VCEQ
Definition: MipsISelLowering.h:218
llvm::MipsTargetLowering::create
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Definition: MipsISelLowering.cpp:529
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:335
llvm::MipsISD::GotHi
@ GotHi
Definition: MipsISelLowering.h:82
llvm::MipsISD::VNOR
@ VNOR
Definition: MipsISelLowering.h:238
llvm::MipsISD::Wrapper
@ Wrapper
Definition: MipsISelLowering.h:150
llvm::MipsISD::Mult
@ Mult
Definition: MipsISelLowering.h:132
llvm::MipsTargetLowering::Subtarget
const MipsSubtarget & Subtarget
Definition: MipsISelLowering.h:497
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1692
llvm::MipsISD::DPSQX_SA_W_PH
@ DPSQX_SA_W_PH
Definition: MipsISelLowering.h:191
CallingConvLower.h
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:516
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4110
MipsABIInfo.h
llvm::MipsISD::DPAQX_SA_W_PH
@ DPAQX_SA_W_PH
Definition: MipsISelLowering.h:187
ISDOpcodes.h
llvm::MipsISD::MTC1_D64
@ MTC1_D64
Definition: MipsISelLowering.h:106
llvm::MipsISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: MipsISelLowering.h:59
llvm::MipsISD::LDR
@ LDR
Definition: MipsISelLowering.h:250
llvm::MipsISD::EXTR_R_W
@ EXTR_R_W
Definition: MipsISelLowering.h:165
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:43
llvm::MipsISD::DivRemU
@ DivRemU
Definition: MipsISelLowering.h:143
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:207
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::MipsISD::SDR
@ SDR
Definition: MipsISelLowering.h:252
llvm::MipsISD::EXTR_S_H
@ EXTR_S_H
Definition: MipsISelLowering.h:163
llvm::MipsISD::BuildPairF64
@ BuildPairF64
Definition: MipsISelLowering.h:147
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:232
llvm::MipsISD::DPS_W_PH
@ DPS_W_PH
Definition: MipsISelLowering.h:185
llvm::MipsISD::SHILO
@ SHILO
Definition: MipsISelLowering.h:167
llvm::createMips16TargetLowering
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
Definition: Mips16ISelLowering.cpp:153
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::MipsISD::EXTPDP
@ EXTPDP
Definition: MipsISelLowering.h:162
llvm::MipsII::MO_ABS_HI
@ MO_ABS_HI
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
llvm::MipsISD::MSubu
@ MSubu
Definition: MipsISelLowering.h:139
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:642
llvm::MipsISD::DPA_W_PH
@ DPA_W_PH
Definition: MipsISelLowering.h:184
llvm::MipsISD::DPSQ_S_W_PH
@ DPSQ_S_W_PH
Definition: MipsISelLowering.h:181
llvm::MipsISD::Higher
@ Higher
Definition: MipsISelLowering.h:71
llvm::MipsISD::DPAU_H_QBL
@ DPAU_H_QBL
Definition: MipsISelLowering.h:176
llvm::MipsII::MO_GPREL
@ MO_GPREL
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Definition: MipsBaseInfo.h:48
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1242
llvm::MipsTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
Definition: MipsISelLowering.cpp:179
llvm::MipsISD::DPAQ_SA_L_W
@ DPAQ_SA_L_W
Definition: MipsISelLowering.h:182
N
#define N
llvm::MipsISD::MULSA_W_PH
@ MULSA_W_PH
Definition: MipsISelLowering.h:192
llvm::MipsISD::VCLT_S
@ VCLT_S
Definition: MipsISelLowering.h:221
llvm::MipsISD::DPAQ_S_W_PH
@ DPAQ_S_W_PH
Definition: MipsISelLowering.h:180
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4202
llvm::MipsISD::FPCmp
@ FPCmp
Definition: MipsISelLowering.h:100
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
RegName
#define RegName(no)
llvm::InlineAsm::Constraint_ZC
@ Constraint_ZC
Definition: InlineAsm.h:262
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:437
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MipsCCState
Definition: MipsCCState.h:20
llvm::MipsISD::MAddu
@ MAddu
Definition: MipsISelLowering.h:137
llvm::MipsISD::MSUB_DSP
@ MSUB_DSP
Definition: MipsISelLowering.h:198
llvm::MipsII::MO_HIGHER
@ MO_HIGHER
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address.
Definition: MipsBaseInfo.h:85
llvm::MipsTargetLowering::getGlobalReg
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
Definition: MipsISelLowering.cpp:142
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:711
llvm::MipsISD::TlsHi
@ TlsHi
Definition: MipsISelLowering.h:85
llvm::MipsISD::SHF
@ SHF
Definition: MipsISelLowering.h:226
llvm::MipsISD::FMS
@ FMS
Definition: MipsISelLowering.h:94
llvm::MipsII::MO_GOT_PAGE
@ MO_GOT_PAGE
Definition: MipsBaseInfo.h:80
llvm::MipsISD::DivRemU16
@ DivRemU16
Definition: MipsISelLowering.h:145
llvm::MipsISD::ERet
@ ERet
Definition: MipsISelLowering.h:119
llvm::MipsTargetLowering::CCAssignFnForReturn
CCAssignFn * CCAssignFnForReturn() const
Definition: MipsISelLowering.cpp:2988
llvm::MipsTargetLowering::ABI
const MipsABIInfo & ABI
Definition: MipsISelLowering.h:499
llvm::MipsISD::TruncIntFP
@ TruncIntFP
Definition: MipsISelLowering.h:113
llvm::MipsISD::VANY_ZERO
@ VANY_ZERO
Definition: MipsISelLowering.h:213
llvm::LLT
Definition: LowLevelTypeImpl.h:40