14#ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
15#define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
43class FunctionLoweringInfo;
44class MachineBasicBlock;
45class MachineFrameInfo;
48class MipsFunctionInfo;
50class MipsTargetMachine;
51class TargetLibraryInfo;
52class TargetRegisterClass;
294 EVT VT)
const override;
300 EVT VT)
const override;
305 unsigned &NumIntermediates,
MVT &RegisterVT)
const override;
310 const Align ABIAlign =
DL.getABITypeAlign(ArgTy);
312 return std::min(ABIAlign,
Align(8));
335 EVT VT)
const override;
355 return ABI.
IsN64() ? Mips::A0_64 : Mips::A0;
362 return ABI.
IsN64() ? Mips::A1_64 : Mips::A1;
380 template <
class NodeTy>
382 bool IsN32OrN64)
const {
385 getTargetNode(
N, Ty, DAG, GOTFlag));
391 getTargetNode(
N, Ty, DAG, LoFlag));
399 template <
class NodeTy>
404 getTargetNode(
N, Ty, DAG, Flag));
405 return DAG.
getLoad(Ty,
DL, Chain, Tgt, PtrInfo);
412 template <
class NodeTy>
415 unsigned LoFlag,
SDValue Chain,
418 getTargetNode(
N, Ty, DAG, HiFlag));
421 getTargetNode(
N, Ty, DAG, LoFlag));
431 template <
class NodeTy>
448 template <
class NodeTy>
475 template <
class NodeTy>
481 DAG.
getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
490 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
491 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
492 bool IsCallReloc, CallLoweringInfo &CLI,
SDValue Callee,
507 unsigned Flag)
const;
511 unsigned Flag)
const;
515 unsigned Flag)
const;
519 unsigned Flag)
const;
523 unsigned Flag)
const;
547 bool HasExtractInsert)
const;
549 bool HasExtractInsert)
const;
563 isEligibleForTailCallOptimization(
const CCState &CCInfo,
564 unsigned NextStackOffset,
574 const Argument *FuncArg,
unsigned FirstReg,
580 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
583 unsigned FirstReg,
unsigned LastReg,
590 void writeVarArgRegs(std::vector<SDValue> &OutChains,
SDValue Chain,
620 bool shouldSignExtendTypeInLibCall(
EVT Type,
bool IsSigned)
const override;
632 std::pair<unsigned, const TargetRegisterClass *>
635 std::pair<unsigned, const TargetRegisterClass *>
644 std::vector<SDValue> &Ops,
648 getInlineAsmMemConstraint(
StringRef ConstraintCode)
const override {
649 if (ConstraintCode ==
"o")
651 if (ConstraintCode ==
"R")
653 if (ConstraintCode ==
"ZC")
659 Type *Ty,
unsigned AS,
671 bool ForCodeSize)
const override;
673 unsigned getJumpTableEncoding()
const override;
674 bool useSoftFloat()
const override;
676 bool shouldInsertFencesForAtomic(
const Instruction *
I)
const override {
681 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &
MI,
682 MachineBasicBlock *BB,
683 unsigned Size,
unsigned DstReg,
684 unsigned SrcRec)
const;
686 MachineBasicBlock *emitAtomicBinary(MachineInstr &
MI,
687 MachineBasicBlock *BB)
const;
688 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &
MI,
689 MachineBasicBlock *BB,
690 unsigned Size)
const;
691 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &
MI,
692 MachineBasicBlock *BB)
const;
693 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &
MI,
694 MachineBasicBlock *BB,
695 unsigned Size)
const;
696 MachineBasicBlock *emitSEL_D(MachineInstr &
MI, MachineBasicBlock *BB)
const;
697 MachineBasicBlock *emitPseudoSELECT(MachineInstr &
MI, MachineBasicBlock *BB,
698 bool isFPCmp,
unsigned Opc)
const;
699 MachineBasicBlock *emitPseudoD_SELECT(MachineInstr &
MI,
700 MachineBasicBlock *BB)
const;
701 MachineBasicBlock *emitLDR_W(MachineInstr &
MI, MachineBasicBlock *BB)
const;
702 MachineBasicBlock *emitLDR_D(MachineInstr &
MI, MachineBasicBlock *BB)
const;
703 MachineBasicBlock *emitSTR_W(MachineInstr &
MI, MachineBasicBlock *BB)
const;
704 MachineBasicBlock *emitSTR_D(MachineInstr &
MI, MachineBasicBlock *BB)
const;
708 const MipsTargetLowering *
710 const MipsSubtarget &STI);
711 const MipsTargetLowering *
713 const MipsSubtarget &STI);
718 const TargetLibraryInfo *libInfo);
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu aa AMDGPU Address space based Alias Analysis Wrapper
Function Alias Analysis Results
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
static constexpr uint32_t Opcode
This class represents an incoming formal argument to a Function.
CCState - This class holds information needed while lowering arguments and return values.
CCValAssign - Represent assignment of one arg/retval to a location.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
This is an important class for using LLVM in a threaded context.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Representation of each machine instruction.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Break down vectors to the correct number of gpr sized integers.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
CCAssignFn * CCAssignFnForReturn() const
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
CCAssignFn * CCAssignFnForCall() const
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
const MipsSubtarget & Subtarget
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
void HandleByVal(CCState *, unsigned &, Align) const override
Target-specific cleanup for formal ByVal parameters.
bool isJumpTableRelative() const override
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const override
Return the correct alignment for the current calling convention.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
MachineFunction & getMachineFunction() const
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
StringRef - Represent a constant reference to a string, i.e.
Provides information about what library functions are available for the current target.
const TargetMachine & getTargetMachine() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
bool isPositionIndependent() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
@ C
The default llvm calling convention, compatible with C.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ ADD
Simple integer binary arithmetic operators.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SIGN_EXTEND
Conversion operators.
@ SHL
Shift and rotation operations.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
@ MO_GOT
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
@ MO_ABS_HI
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
@ MO_GPREL
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
@ MO_HIGHER
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
This is an optimization pass for GlobalISel generic memory operations.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
This struct is a compact representation of a valid (non-zero power of two) alignment.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
This contains information for each constraint that we are lowering.
This structure contains all information that is necessary for lowering calls.