LLVM 19.0.0git
X86MCTargetDesc.h
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1//===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides X86 specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
14#define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
15
16#include <memory>
17#include <string>
18
19namespace llvm {
20class formatted_raw_ostream;
21class MCAsmBackend;
22class MCCodeEmitter;
23class MCContext;
24class MCInst;
25class MCInstPrinter;
26class MCInstrInfo;
27class MCObjectTargetWriter;
28class MCObjectWriter;
29class MCRegister;
30class MCRegisterInfo;
31class MCStreamer;
32class MCSubtargetInfo;
33class MCTargetOptions;
34class MCTargetStreamer;
35class Target;
36class Triple;
37class StringRef;
38
39/// Flavour of dwarf regnumbers
40///
41namespace DWARFFlavour {
42 enum {
44 };
45}
46
47/// Native X86 register numbers
48///
49namespace N86 {
50 enum {
51 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
52 };
53}
54
55namespace X86_MC {
56std::string ParseX86Triple(const Triple &TT);
57
58unsigned getDwarfRegFlavour(const Triple &TT, bool isEH);
59
60void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI);
61
62
63/// Returns true if this instruction has a LOCK prefix.
64bool hasLockPrefix(const MCInst &MI);
65
66/// \param Op operand # of the memory operand.
67///
68/// \returns true if the specified instruction has a 16-bit memory operand.
69bool is16BitMemOperand(const MCInst &MI, unsigned Op,
70 const MCSubtargetInfo &STI);
71
72/// \param Op operand # of the memory operand.
73///
74/// \returns true if the specified instruction has a 32-bit memory operand.
75bool is32BitMemOperand(const MCInst &MI, unsigned Op);
76
77/// \param Op operand # of the memory operand.
78///
79/// \returns true if the specified instruction has a 64-bit memory operand.
80#ifndef NDEBUG
81bool is64BitMemOperand(const MCInst &MI, unsigned Op);
82#endif
83
84/// Returns true if this instruction needs an Address-Size override prefix.
85bool needsAddressSizeOverride(const MCInst &MI, const MCSubtargetInfo &STI,
86 int MemoryOperand, uint64_t TSFlags);
87
88/// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc.
89/// do not need to go through TargetRegistry.
90MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU,
91 StringRef FS);
92}
93
94MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
95 MCContext &Ctx);
96
97MCAsmBackend *createX86_32AsmBackend(const Target &T,
98 const MCSubtargetInfo &STI,
99 const MCRegisterInfo &MRI,
100 const MCTargetOptions &Options);
101MCAsmBackend *createX86_64AsmBackend(const Target &T,
102 const MCSubtargetInfo &STI,
103 const MCRegisterInfo &MRI,
104 const MCTargetOptions &Options);
105
106/// Implements X86-only directives for assembly emission.
107MCTargetStreamer *createX86AsmTargetStreamer(MCStreamer &S,
108 formatted_raw_ostream &OS,
109 MCInstPrinter *InstPrinter,
110 bool IsVerboseAsm);
111
112/// Implements X86-only directives for object files.
113MCTargetStreamer *createX86ObjectTargetStreamer(MCStreamer &S,
114 const MCSubtargetInfo &STI);
115
116/// Construct an X86 Windows COFF machine code streamer which will generate
117/// PE/COFF format object files.
118///
119/// Takes ownership of \p AB and \p CE.
120MCStreamer *createX86WinCOFFStreamer(MCContext &C,
121 std::unique_ptr<MCAsmBackend> &&AB,
122 std::unique_ptr<MCObjectWriter> &&OW,
123 std::unique_ptr<MCCodeEmitter> &&CE,
124 bool RelaxAll,
125 bool IncrementalLinkerCompatible);
126
127/// Construct an X86 Mach-O object writer.
128std::unique_ptr<MCObjectTargetWriter>
129createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype);
130
131/// Construct an X86 ELF object writer.
132std::unique_ptr<MCObjectTargetWriter>
133createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine);
134/// Construct an X86 Win COFF object writer.
135std::unique_ptr<MCObjectTargetWriter>
136createX86WinCOFFObjectWriter(bool Is64Bit);
137
138/// \param Reg speicifed register.
139/// \param Size the bit size of returned register.
140/// \param High requires the high register.
141///
142/// \returns the sub or super register of a specific X86 register.
143MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size,
144 bool High = false);
145} // End llvm namespace
146
147
148// Defines symbolic names for X86 registers. This defines a mapping from
149// register name to register number.
150//
151#define GET_REGINFO_ENUM
152#include "X86GenRegisterInfo.inc"
153
154// Defines symbolic names for the X86 instructions.
155//
156#define GET_INSTRINFO_ENUM
157#define GET_INSTRINFO_MC_HELPER_DECLS
158#include "X86GenInstrInfo.inc"
159
160#define GET_SUBTARGETINFO_ENUM
161#include "X86GenSubtargetInfo.inc"
162
163#define GET_X86_MNEMONIC_TABLES_H
164#include "X86GenMnemonicTables.inc"
165
166#endif
unsigned const MachineRegisterInfo * MRI
uint64_t Size
IRTranslator LLVM IR MI
static LVOptions Options
Definition: LVOptions.cpp:25
unsigned Reg
uint64_t High
raw_pwrite_stream & OS
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
bool is32BitMemOperand(const MCInst &MI, unsigned Op)
bool is16BitMemOperand(const MCInst &MI, unsigned Op, const MCSubtargetInfo &STI)
bool hasLockPrefix(const MCInst &MI)
Returns true if this instruction has a LOCK prefix.
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
bool needsAddressSizeOverride(const MCInst &MI, const MCSubtargetInfo &STI, int MemoryOperand, uint64_t TSFlags)
Returns true if this instruction needs an Address-Size override prefix.
std::string ParseX86Triple(const Triple &TT)
MCSubtargetInfo * createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a X86 MCSubtargetInfo instance.
bool is64BitMemOperand(const MCInst &MI, unsigned Op)
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCTargetStreamer * createX86ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Implements X86-only directives for object files.
MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High=false)
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createX86WinCOFFObjectWriter(bool Is64Bit)
Construct an X86 Win COFF object writer.
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
MCStreamer * createX86WinCOFFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > &&AB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool IncrementalLinkerCompatible)
Construct an X86 Windows COFF machine code streamer which will generate PE/COFF format object files.
std::unique_ptr< MCObjectTargetWriter > createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an X86 Mach-O object writer.
DWARFExpression::Operation Op
MCTargetStreamer * createX86AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrinter, bool IsVerboseAsm)
Implements X86-only directives for assembly emission.
std::unique_ptr< MCObjectTargetWriter > createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine)
Construct an X86 ELF object writer.
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)