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InstructionSelector.h
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1 //===- llvm/CodeGen/GlobalISel/InstructionSelector.h ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API for the instruction selector.
10 /// This class is responsible for selecting machine instructions.
11 /// It's implemented by the target. It's used by the InstructionSelect pass.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
16 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
17 
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/Optional.h"
20 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/IR/Function.h"
25 #include <bitset>
26 #include <cstddef>
27 #include <cstdint>
28 #include <functional>
29 #include <initializer_list>
30 #include <vector>
31 
32 namespace llvm {
33 
34 class BlockFrequencyInfo;
35 class CodeGenCoverage;
36 class MachineBasicBlock;
37 class ProfileSummaryInfo;
38 class APInt;
39 class APFloat;
40 class GISelKnownBits;
41 class MachineInstr;
42 class MachineInstrBuilder;
43 class MachineFunction;
44 class MachineOperand;
45 class MachineRegisterInfo;
46 class RegisterBankInfo;
47 class TargetInstrInfo;
48 class TargetRegisterInfo;
49 
50 /// Container class for CodeGen predicate results.
51 /// This is convenient because std::bitset does not have a constructor
52 /// with an initializer list of set bits.
53 ///
54 /// Each InstructionSelector subclass should define a PredicateBitset class
55 /// with:
56 /// const unsigned MAX_SUBTARGET_PREDICATES = 192;
57 /// using PredicateBitset = PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
58 /// and updating the constant to suit the target. Tablegen provides a suitable
59 /// definition for the predicates in use in <Target>GenGlobalISel.inc when
60 /// GET_GLOBALISEL_PREDICATE_BITSET is defined.
61 template <std::size_t MaxPredicates>
62 class PredicateBitsetImpl : public std::bitset<MaxPredicates> {
63 public:
64  // Cannot inherit constructors because it's not supported by VC++..
65  PredicateBitsetImpl() = default;
66 
67  PredicateBitsetImpl(const std::bitset<MaxPredicates> &B)
68  : std::bitset<MaxPredicates>(B) {}
69 
70  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
71  for (auto I : Init)
73  }
74 };
75 
76 enum {
77  /// Begin a try-block to attempt a match and jump to OnFail if it is
78  /// unsuccessful.
79  /// - OnFail - The MatchTable entry at which to resume if the match fails.
80  ///
81  /// FIXME: This ought to take an argument indicating the number of try-blocks
82  /// to exit on failure. It's usually one but the last match attempt of
83  /// a block will need more. The (implemented) alternative is to tack a
84  /// GIM_Reject on the end of each try-block which is simpler but
85  /// requires an extra opcode and iteration in the interpreter on each
86  /// failed match.
88 
89  /// Switch over the opcode on the specified instruction
90  /// - InsnID - Instruction ID
91  /// - LowerBound - numerically minimum opcode supported
92  /// - UpperBound - numerically maximum + 1 opcode supported
93  /// - Default - failure jump target
94  /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
96 
97  /// Switch over the LLT on the specified instruction operand
98  /// - InsnID - Instruction ID
99  /// - OpIdx - Operand index
100  /// - LowerBound - numerically minimum Type ID supported
101  /// - UpperBound - numerically maximum + 1 Type ID supported
102  /// - Default - failure jump target
103  /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
105 
106  /// Record the specified instruction
107  /// - NewInsnID - Instruction ID to define
108  /// - InsnID - Instruction ID
109  /// - OpIdx - Operand index
111 
112  /// Check the feature bits
113  /// - Expected features
115 
116  /// Check the opcode on the specified instruction
117  /// - InsnID - Instruction ID
118  /// - Expected opcode
120 
121  /// Check the opcode on the specified instruction, checking 2 acceptable
122  /// alternatives.
123  /// - InsnID - Instruction ID
124  /// - Expected opcode
125  /// - Alternative expected opcode
127 
128  /// Check the instruction has the right number of operands
129  /// - InsnID - Instruction ID
130  /// - Expected number of operands
132  /// Check an immediate predicate on the specified instruction
133  /// - InsnID - Instruction ID
134  /// - The predicate to test
136  /// Check an immediate predicate on the specified instruction via an APInt.
137  /// - InsnID - Instruction ID
138  /// - The predicate to test
140  /// Check a floating point immediate predicate on the specified instruction.
141  /// - InsnID - Instruction ID
142  /// - The predicate to test
144  /// Check an immediate predicate on the specified instruction
145  /// - InsnID - Instruction ID
146  /// - OpIdx - Operand index
147  /// - The predicate to test
149  /// Check a memory operation has the specified atomic ordering.
150  /// - InsnID - Instruction ID
151  /// - Ordering - The AtomicOrdering value
155  /// Check the size of the memory access for the given machine memory operand.
156  /// - InsnID - Instruction ID
157  /// - MMOIdx - MMO index
158  /// - Size - The size in bytes of the memory access
160 
161  /// Check the address space of the memory access for the given machine memory
162  /// operand.
163  /// - InsnID - Instruction ID
164  /// - MMOIdx - MMO index
165  /// - NumAddrSpace - Number of valid address spaces
166  /// - AddrSpaceN - An allowed space of the memory access
167  /// - AddrSpaceN+1 ...
169 
170  /// Check the minimum alignment of the memory access for the given machine
171  /// memory operand.
172  /// - InsnID - Instruction ID
173  /// - MMOIdx - MMO index
174  /// - MinAlign - Minimum acceptable alignment
176 
177  /// Check the size of the memory access for the given machine memory operand
178  /// against the size of an operand.
179  /// - InsnID - Instruction ID
180  /// - MMOIdx - MMO index
181  /// - OpIdx - The operand index to compare the MMO against
185 
186  /// Check if this is a vector that can be treated as a vector splat
187  /// constant. This is valid for both G_BUILD_VECTOR as well as
188  /// G_BUILD_VECTOR_TRUNC. For AllOnes refers to individual bits, so a -1
189  /// element.
190  /// - InsnID - Instruction ID
193 
194  /// Check a generic C++ instruction predicate
195  /// - InsnID - Instruction ID
196  /// - PredicateID - The ID of the predicate function to call
198 
199  /// Check the type for the specified operand
200  /// - InsnID - Instruction ID
201  /// - OpIdx - Operand index
202  /// - Expected type
204  /// Check the type of a pointer to any address space.
205  /// - InsnID - Instruction ID
206  /// - OpIdx - Operand index
207  /// - SizeInBits - The size of the pointer value in bits.
209  /// Check the register bank for the specified operand
210  /// - InsnID - Instruction ID
211  /// - OpIdx - Operand index
212  /// - Expected register bank (specified as a register class)
214 
215  /// Check the operand matches a complex predicate
216  /// - InsnID - Instruction ID
217  /// - OpIdx - Operand index
218  /// - RendererID - The renderer to hold the result
219  /// - Complex predicate ID
221 
222  /// Check the operand is a specific integer
223  /// - InsnID - Instruction ID
224  /// - OpIdx - Operand index
225  /// - Expected integer
227  /// Check the operand is a specific literal integer (i.e. MO.isImm() or
228  /// MO.isCImm() is true).
229  /// - InsnID - Instruction ID
230  /// - OpIdx - Operand index
231  /// - Expected integer
233  /// Check the operand is a specific intrinsic ID
234  /// - InsnID - Instruction ID
235  /// - OpIdx - Operand index
236  /// - Expected Intrinsic ID
238 
239  /// Check the operand is a specific predicate
240  /// - InsnID - Instruction ID
241  /// - OpIdx - Operand index
242  /// - Expected predicate
244 
245  /// Check the specified operand is an MBB
246  /// - InsnID - Instruction ID
247  /// - OpIdx - Operand index
249 
250  /// Check the specified operand is an Imm
251  /// - InsnID - Instruction ID
252  /// - OpIdx - Operand index
254 
255  /// Check if the specified operand is safe to fold into the current
256  /// instruction.
257  /// - InsnID - Instruction ID
259 
260  /// Check the specified operands are identical.
261  /// - InsnID - Instruction ID
262  /// - OpIdx - Operand index
263  /// - OtherInsnID - Other instruction ID
264  /// - OtherOpIdx - Other operand index
266 
267  /// Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some
268  /// named operands that will be recorded in RecordedOperands. Names of these
269  /// operands are referenced in predicate argument list. Emitter determines
270  /// StoreIdx(corresponds to the order in which names appear in argument list).
271  /// - InsnID - Instruction ID
272  /// - OpIdx - Operand index
273  /// - StoreIdx - Store location in RecordedOperands.
275 
276  /// Fail the current try-block, or completely fail to match if there is no
277  /// current try-block.
279 
280  //=== Renderers ===
281 
282  /// Mutate an instruction
283  /// - NewInsnID - Instruction ID to define
284  /// - OldInsnID - Instruction ID to mutate
285  /// - NewOpcode - The new opcode to use
287 
288  /// Build a new instruction
289  /// - InsnID - Instruction ID to define
290  /// - Opcode - The new opcode to use
292 
293  /// Copy an operand to the specified instruction
294  /// - NewInsnID - Instruction ID to modify
295  /// - OldInsnID - Instruction ID to copy from
296  /// - OpIdx - The operand to copy
298 
299  /// Copy an operand to the specified instruction or add a zero register if the
300  /// operand is a zero immediate.
301  /// - NewInsnID - Instruction ID to modify
302  /// - OldInsnID - Instruction ID to copy from
303  /// - OpIdx - The operand to copy
304  /// - ZeroReg - The zero register to use
306  /// Copy an operand to the specified instruction
307  /// - NewInsnID - Instruction ID to modify
308  /// - OldInsnID - Instruction ID to copy from
309  /// - OpIdx - The operand to copy
310  /// - SubRegIdx - The subregister to copy
312 
313  /// Add an implicit register def to the specified instruction
314  /// - InsnID - Instruction ID to modify
315  /// - RegNum - The register to add
317  /// Add an implicit register use to the specified instruction
318  /// - InsnID - Instruction ID to modify
319  /// - RegNum - The register to add
321  /// Add an register to the specified instruction
322  /// - InsnID - Instruction ID to modify
323  /// - RegNum - The register to add
325 
326  /// Add a temporary register to the specified instruction
327  /// - InsnID - Instruction ID to modify
328  /// - TempRegID - The temporary register ID to add
329  /// - TempRegFlags - The register flags to set
331 
332  /// Add a temporary register to the specified instruction
333  /// - InsnID - Instruction ID to modify
334  /// - TempRegID - The temporary register ID to add
335  /// - TempRegFlags - The register flags to set
336  /// - SubRegIndex - The subregister index to set
338 
339  /// Add an immediate to the specified instruction
340  /// - InsnID - Instruction ID to modify
341  /// - Imm - The immediate to add
343  /// Render complex operands to the specified instruction
344  /// - InsnID - Instruction ID to modify
345  /// - RendererID - The renderer to call
347 
348  /// Render sub-operands of complex operands to the specified instruction
349  /// - InsnID - Instruction ID to modify
350  /// - RendererID - The renderer to call
351  /// - RenderOpID - The suboperand to render.
353  /// Render operands to the specified instruction using a custom function
354  /// - InsnID - Instruction ID to modify
355  /// - OldInsnID - Instruction ID to get the matched operand from
356  /// - RendererFnID - Custom renderer function to call
358 
359  /// Render operands to the specified instruction using a custom function,
360  /// reading from a specific operand.
361  /// - InsnID - Instruction ID to modify
362  /// - OldInsnID - Instruction ID to get the matched operand from
363  /// - OpIdx - Operand index in OldInsnID the render function should read from..
364  /// - RendererFnID - Custom renderer function to call
366 
367  /// Render a G_CONSTANT operator as a sign-extended immediate.
368  /// - NewInsnID - Instruction ID to modify
369  /// - OldInsnID - Instruction ID to copy from
370  /// The operand index is implicitly 1.
372 
373  /// Render a G_FCONSTANT operator as a sign-extended immediate.
374  /// - NewInsnID - Instruction ID to modify
375  /// - OldInsnID - Instruction ID to copy from
376  /// The operand index is implicitly 1.
378 
379  /// Constrain an instruction operand to a register class.
380  /// - InsnID - Instruction ID to modify
381  /// - OpIdx - Operand index
382  /// - RCEnum - Register class enumeration value
384 
385  /// Constrain an instructions operands according to the instruction
386  /// description.
387  /// - InsnID - Instruction ID to modify
389 
390  /// Merge all memory operands into instruction.
391  /// - InsnID - Instruction ID to modify
392  /// - MergeInsnID... - One or more Instruction ID to merge into the result.
393  /// - GIU_MergeMemOperands_EndOfList - Terminates the list of instructions to
394  /// merge.
396 
397  /// Erase from parent.
398  /// - InsnID - Instruction ID to erase
400 
401  /// Create a new temporary register that's not constrained.
402  /// - TempRegID - The temporary register ID to initialize.
403  /// - Expected type
405 
406  /// A successful emission
408 
409  /// Increment the rule coverage counter.
410  /// - RuleID - The ID of the rule that was covered.
412 
413  /// Keeping track of the number of the GI opcodes. Must be the last entry.
415 };
416 
417 enum {
418  /// Indicates the end of the variable-length MergeInsnID list in a
419  /// GIR_MergeMemOperands opcode.
421 };
422 
423 /// Provides the logic to select generic machine instructions.
425 public:
426  virtual ~InstructionSelector() = default;
427 
428  /// Select the (possibly generic) instruction \p I to only use target-specific
429  /// opcodes. It is OK to insert multiple instructions, but they cannot be
430  /// generic pre-isel instructions.
431  ///
432  /// \returns whether selection succeeded.
433  /// \pre I.getParent() && I.getParent()->getParent()
434  /// \post
435  /// if returns true:
436  /// for I in all mutated/inserted instructions:
437  /// !isPreISelGenericOpcode(I.getOpcode())
438  virtual bool select(MachineInstr &I) = 0;
439 
442  MachineFunction *MF = nullptr;
445  // For some predicates, we need to track the current MBB.
447 
449  llvm_unreachable("TableGen should have emitted implementation");
450  }
451 
452  /// Setup per-MF selector state.
453  virtual void setupMF(MachineFunction &mf, GISelKnownBits *KB,
454  CodeGenCoverage &covinfo, ProfileSummaryInfo *psi,
456  CoverageInfo = &covinfo;
457  KnownBits = KB;
458  MF = &mf;
459  PSI = psi;
460  BFI = bfi;
461  CurMBB = nullptr;
463  }
464 
465 protected:
466  using ComplexRendererFns =
470 
471  struct MatcherState {
472  std::vector<ComplexRendererFns::value_type> Renderers;
475  /// Named operands that predicate with 'let PredicateCodeUsesOperands = 1'
476  /// referenced in its argument list. Operands are inserted at index set by
477  /// emitter, it corresponds to the order in which names appear in argument
478  /// list. Currently such predicates don't have more then 3 arguments.
479  std::array<const MachineOperand *, 3> RecordedOperands;
480 
481  MatcherState(unsigned MaxRenderers);
482  };
483 
484  bool shouldOptForSize(const MachineFunction *MF) const {
485  const auto &F = MF->getFunction();
486  return F.hasOptSize() || F.hasMinSize() ||
488  }
489 
490 public:
491  template <class PredicateBitset, class ComplexMatcherMemFn,
492  class CustomRendererFn>
493  struct ISelInfoTy {
494  ISelInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
495  const PredicateBitset *FeatureBitsets,
496  const ComplexMatcherMemFn *ComplexPredicates,
497  const CustomRendererFn *CustomRenderers)
502 
503  for (size_t I = 0; I < NumTypeObjects; ++I)
504  TypeIDMap[TypeObjects[I]] = I;
505  }
506  const LLT *TypeObjects;
507  const PredicateBitset *FeatureBitsets;
508  const ComplexMatcherMemFn *ComplexPredicates;
509  const CustomRendererFn *CustomRenderers;
510 
512  };
513 
514 protected:
516 
517  /// Execute a given matcher table and return true if the match was successful
518  /// and false otherwise.
519  template <class TgtInstructionSelector, class PredicateBitset,
520  class ComplexMatcherMemFn, class CustomRendererFn>
521  bool executeMatchTable(
522  TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
524  &ISelInfo,
525  const int64_t *MatchTable, const TargetInstrInfo &TII,
527  const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
529 
530  virtual const int64_t *getMatchTable() const {
531  llvm_unreachable("Should have been overridden by tablegen if used");
532  }
533 
534  virtual bool testImmPredicate_I64(unsigned, int64_t) const {
536  "Subclasses must override this with a tablegen-erated function");
537  }
538  virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
540  "Subclasses must override this with a tablegen-erated function");
541  }
542  virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
544  "Subclasses must override this with a tablegen-erated function");
545  }
546  virtual bool testMIPredicate_MI(
547  unsigned, const MachineInstr &,
548  const std::array<const MachineOperand *, 3> &Operands) const {
550  "Subclasses must override this with a tablegen-erated function");
551  }
552 
553  bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
554  const MachineRegisterInfo &MRI) const;
555 
556  /// Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the
557  /// right-hand side. GlobalISel's separation of pointer and integer types
558  /// means that we don't need to worry about G_OR with equivalent semantics.
559  bool isBaseWithConstantOffset(const MachineOperand &Root,
560  const MachineRegisterInfo &MRI) const;
561 
562  /// Return true if MI can obviously be folded into IntoMI.
563  /// MI and IntoMI do not need to be in the same basic blocks, but MI must
564  /// preceed IntoMI.
565  bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const;
566 };
567 
568 } // end namespace llvm
569 
570 #endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:425
set
We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 atomic and others It is also currently not done for read modify write instructions It is also current not done if the OF or CF flags are needed The shift operators have the complication that when the shift count is EFLAGS is not set
Definition: README.txt:1277
llvm::InstructionSelector::MatcherState::Renderers
std::vector< ComplexRendererFns::value_type > Renderers
Definition: InstructionSelector.h:472
llvm::GIR_ComplexRenderer
@ GIR_ComplexRenderer
Render complex operands to the specified instruction.
Definition: InstructionSelector.h:346
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::GIR_MutateOpcode
@ GIR_MutateOpcode
Mutate an instruction.
Definition: InstructionSelector.h:286
llvm::GIR_EraseFromParent
@ GIR_EraseFromParent
Erase from parent.
Definition: InstructionSelector.h:399
Optional.h
llvm::InstructionSelector::testMIPredicate_MI
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &, const std::array< const MachineOperand *, 3 > &Operands) const
Definition: InstructionSelector.h:546
llvm::GIM_CheckIsImm
@ GIM_CheckIsImm
Check the specified operand is an Imm.
Definition: InstructionSelector.h:253
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::GIM_CheckComplexPattern
@ GIM_CheckComplexPattern
Check the operand matches a complex predicate.
Definition: InstructionSelector.h:220
llvm::GIR_Coverage
@ GIR_Coverage
Increment the rule coverage counter.
Definition: InstructionSelector.h:411
llvm::InstructionSelector::getMatchTable
virtual const int64_t * getMatchTable() const
Definition: InstructionSelector.h:530
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::GIM_CheckAtomicOrderingWeakerThan
@ GIM_CheckAtomicOrderingWeakerThan
Definition: InstructionSelector.h:154
llvm::GIR_AddImplicitUse
@ GIR_AddImplicitUse
Add an implicit register use to the specified instruction.
Definition: InstructionSelector.h:320
llvm::GIR_AddImplicitDef
@ GIR_AddImplicitDef
Add an implicit register def to the specified instruction.
Definition: InstructionSelector.h:316
llvm::GIR_Done
@ GIR_Done
A successful emission.
Definition: InstructionSelector.h:407
llvm::GIR_CopyConstantAsSImm
@ GIR_CopyConstantAsSImm
Render a G_CONSTANT operator as a sign-extended immediate.
Definition: InstructionSelector.h:371
llvm::GIM_CheckIntrinsicID
@ GIM_CheckIntrinsicID
Check the operand is a specific intrinsic ID.
Definition: InstructionSelector.h:237
llvm::GIR_CustomRenderer
@ GIR_CustomRenderer
Render operands to the specified instruction using a custom function.
Definition: InstructionSelector.h:357
llvm::GIR_ConstrainSelectedInstOperands
@ GIR_ConstrainSelectedInstOperands
Constrain an instructions operands according to the instruction description.
Definition: InstructionSelector.h:388
llvm::GIM_CheckNumOperands
@ GIM_CheckNumOperands
Check the instruction has the right number of operands.
Definition: InstructionSelector.h:131
llvm::SmallDenseMap
Definition: DenseMap.h:882
llvm::InstructionSelector::MatcherState
Definition: InstructionSelector.h:471
llvm::InstructionSelector::setupMF
virtual void setupMF(MachineFunction &mf, GISelKnownBits *KB, CodeGenCoverage &covinfo, ProfileSummaryInfo *psi, BlockFrequencyInfo *bfi)
Setup per-MF selector state.
Definition: InstructionSelector.h:453
llvm::GIR_AddTempRegister
@ GIR_AddTempRegister
Add a temporary register to the specified instruction.
Definition: InstructionSelector.h:330
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::shouldOptForSize
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:1299
DenseMap.h
llvm::InstructionSelector::MatcherState::MIs
RecordedMIVector MIs
Definition: InstructionSelector.h:473
llvm::Optional
Definition: APInt.h:33
llvm::InstructionSelector::testImmPredicate_I64
virtual bool testImmPredicate_I64(unsigned, int64_t) const
Definition: InstructionSelector.h:534
llvm::GIM_CheckMemorySizeEqualTo
@ GIM_CheckMemorySizeEqualTo
Check the size of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:159
llvm::GIM_SwitchType
@ GIM_SwitchType
Switch over the LLT on the specified instruction operand.
Definition: InstructionSelector.h:104
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::InstructionSelector::ISelInfoTy::ISelInfoTy
ISelInfoTy(const LLT *TypeObjects, size_t NumTypeObjects, const PredicateBitset *FeatureBitsets, const ComplexMatcherMemFn *ComplexPredicates, const CustomRendererFn *CustomRenderers)
Definition: InstructionSelector.h:494
llvm::InstructionSelector::MatcherState::TempRegisters
DenseMap< unsigned, unsigned > TempRegisters
Definition: InstructionSelector.h:474
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::GIM_CheckIsSameOperand
@ GIM_CheckIsSameOperand
Check the specified operands are identical.
Definition: InstructionSelector.h:265
llvm::GIM_CheckOpcodeIsEither
@ GIM_CheckOpcodeIsEither
Check the opcode on the specified instruction, checking 2 acceptable alternatives.
Definition: InstructionSelector.h:126
llvm::GIR_AddRegister
@ GIR_AddRegister
Add an register to the specified instruction.
Definition: InstructionSelector.h:324
llvm::GIM_CheckAPIntImmPredicate
@ GIM_CheckAPIntImmPredicate
Check an immediate predicate on the specified instruction via an APInt.
Definition: InstructionSelector.h:139
llvm::GIR_CopySubReg
@ GIR_CopySubReg
Copy an operand to the specified instruction.
Definition: InstructionSelector.h:311
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::InstructionSelector::ISelInfoTy::CustomRenderers
const CustomRendererFn * CustomRenderers
Definition: InstructionSelector.h:509
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::InstructionSelector::~InstructionSelector
virtual ~InstructionSelector()=default
llvm::GIM_SwitchOpcode
@ GIM_SwitchOpcode
Switch over the opcode on the specified instruction.
Definition: InstructionSelector.h:95
llvm::GIM_RecordNamedOperand
@ GIM_RecordNamedOperand
Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some named operands that will be ...
Definition: InstructionSelector.h:274
llvm::GIM_CheckMemorySizeGreaterThanLLT
@ GIM_CheckMemorySizeGreaterThanLLT
Definition: InstructionSelector.h:184
llvm::InstructionSelector::CoverageInfo
CodeGenCoverage * CoverageInfo
Definition: InstructionSelector.h:440
Utils.h
llvm::GIM_CheckPointerToAny
@ GIM_CheckPointerToAny
Check the type of a pointer to any address space.
Definition: InstructionSelector.h:208
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::GIR_MakeTempReg
@ GIR_MakeTempReg
Create a new temporary register that's not constrained.
Definition: InstructionSelector.h:404
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::GIM_CheckOpcode
@ GIM_CheckOpcode
Check the opcode on the specified instruction.
Definition: InstructionSelector.h:119
llvm::InstructionSelector::MatcherState::RecordedOperands
std::array< const MachineOperand *, 3 > RecordedOperands
Named operands that predicate with 'let PredicateCodeUsesOperands = 1' referenced in its argument lis...
Definition: InstructionSelector.h:479
llvm::InstructionSelector::InstructionSelector
InstructionSelector()
llvm::GIM_CheckCxxInsnPredicate
@ GIM_CheckCxxInsnPredicate
Check a generic C++ instruction predicate.
Definition: InstructionSelector.h:197
llvm::GIM_CheckI64ImmPredicate
@ GIM_CheckI64ImmPredicate
Check an immediate predicate on the specified instruction.
Definition: InstructionSelector.h:135
llvm::GIR_ConstrainOperandRC
@ GIR_ConstrainOperandRC
Constrain an instruction operand to a register class.
Definition: InstructionSelector.h:383
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
LowLevelTypeImpl.h
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::InstructionSelector::MF
MachineFunction * MF
Definition: InstructionSelector.h:442
llvm::InstructionSelector::isOperandImmEqual
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
Definition: InstructionSelector.cpp:29
llvm::APFloat
Definition: APFloat.h:700
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::InstructionSelector::ISelInfoTy::TypeIDMap
SmallDenseMap< LLT, unsigned, 64 > TypeIDMap
Definition: InstructionSelector.h:511
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:424
llvm::CodeGenCoverage
Definition: CodeGenCoverage.h:19
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::GIM_CheckRegBankForClass
@ GIM_CheckRegBankForClass
Check the register bank for the specified operand.
Definition: InstructionSelector.h:213
llvm::DenseMap< unsigned, unsigned >
llvm::InstructionSelector::shouldOptForSize
bool shouldOptForSize(const MachineFunction *MF) const
Definition: InstructionSelector.h:484
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::GIM_CheckIsBuildVectorAllOnes
@ GIM_CheckIsBuildVectorAllOnes
Check if this is a vector that can be treated as a vector splat constant.
Definition: InstructionSelector.h:191
llvm::InstructionSelector::ISelInfoTy::TypeObjects
const LLT * TypeObjects
Definition: InstructionSelector.h:506
llvm::PredicateBitsetImpl
Container class for CodeGen predicate results.
Definition: InstructionSelector.h:62
llvm::GIR_CopyOrAddZeroReg
@ GIR_CopyOrAddZeroReg
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
Definition: InstructionSelector.h:305
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::InstructionSelector::ComplexRendererFns
Optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
Definition: InstructionSelector.h:467
llvm::GIM_CheckMemorySizeLessThanLLT
@ GIM_CheckMemorySizeLessThanLLT
Definition: InstructionSelector.h:183
llvm::InstructionSelector::MatcherState::MatcherState
MatcherState(unsigned MaxRenderers)
Definition: InstructionSelector.cpp:24
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::GIM_CheckMemoryAddressSpace
@ GIM_CheckMemoryAddressSpace
Check the address space of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:168
llvm::GIR_CopyFConstantAsFPImm
@ GIR_CopyFConstantAsFPImm
Render a G_FCONSTANT operator as a sign-extended immediate.
Definition: InstructionSelector.h:377
llvm::InstructionSelector::testImmPredicate_APFloat
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
Definition: InstructionSelector.h:542
llvm::GIM_CheckMemoryAlignment
@ GIM_CheckMemoryAlignment
Check the minimum alignment of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:175
llvm::GIR_AddImm
@ GIR_AddImm
Add an immediate to the specified instruction.
Definition: InstructionSelector.h:342
llvm::GIM_CheckIsSafeToFold
@ GIM_CheckIsSafeToFold
Check if the specified operand is safe to fold into the current instruction.
Definition: InstructionSelector.h:258
llvm::GIU_MergeMemOperands_EndOfList
@ GIU_MergeMemOperands_EndOfList
Indicates the end of the variable-length MergeInsnID list in a GIR_MergeMemOperands opcode.
Definition: InstructionSelector.h:420
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::InstructionSelector::isBaseWithConstantOffset
bool isBaseWithConstantOffset(const MachineOperand &Root, const MachineRegisterInfo &MRI) const
Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the right-hand side.
Definition: InstructionSelector.cpp:38
llvm::GIR_AddTempSubRegister
@ GIR_AddTempSubRegister
Add a temporary register to the specified instruction.
Definition: InstructionSelector.h:337
llvm::GIM_RecordInsn
@ GIM_RecordInsn
Record the specified instruction.
Definition: InstructionSelector.h:110
llvm::InstructionSelector::BFI
BlockFrequencyInfo * BFI
Definition: InstructionSelector.h:444
llvm::Init
Definition: Record.h:281
llvm::InstructionSelector::ISelInfoTy::ComplexPredicates
const ComplexMatcherMemFn * ComplexPredicates
Definition: InstructionSelector.h:508
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::GIR_Copy
@ GIR_Copy
Copy an operand to the specified instruction.
Definition: InstructionSelector.h:297
llvm::InstructionSelector::ISelInfoTy::FeatureBitsets
const PredicateBitset * FeatureBitsets
Definition: InstructionSelector.h:507
std
Definition: BitVector.h:851
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
llvm::InstructionSelector::PSI
ProfileSummaryInfo * PSI
Definition: InstructionSelector.h:443
llvm::PredicateBitsetImpl::PredicateBitsetImpl
PredicateBitsetImpl()=default
llvm::GIU_NumOpcodes
@ GIU_NumOpcodes
Keeping track of the number of the GI opcodes. Must be the last entry.
Definition: InstructionSelector.h:414
llvm::GIR_BuildMI
@ GIR_BuildMI
Build a new instruction.
Definition: InstructionSelector.h:291
Function.h
llvm::GIM_CheckConstantInt
@ GIM_CheckConstantInt
Check the operand is a specific integer.
Definition: InstructionSelector.h:226
llvm::GIM_CheckAPFloatImmPredicate
@ GIM_CheckAPFloatImmPredicate
Check a floating point immediate predicate on the specified instruction.
Definition: InstructionSelector.h:143
llvm::PredicateBitsetImpl::PredicateBitsetImpl
PredicateBitsetImpl(const std::bitset< MaxPredicates > &B)
Definition: InstructionSelector.h:67
llvm::GIM_CheckAtomicOrderingOrStrongerThan
@ GIM_CheckAtomicOrderingOrStrongerThan
Definition: InstructionSelector.h:153
llvm::InstructionSelector::isObviouslySafeToFold
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
Definition: InstructionSelector.cpp:55
llvm::GIM_CheckAtomicOrdering
@ GIM_CheckAtomicOrdering
Check a memory operation has the specified atomic ordering.
Definition: InstructionSelector.h:152
llvm::GIR_MergeMemOperands
@ GIR_MergeMemOperands
Merge all memory operands into instruction.
Definition: InstructionSelector.h:395
llvm::GIR_CustomOperandRenderer
@ GIR_CustomOperandRenderer
Render operands to the specified instruction using a custom function, reading from a specific operand...
Definition: InstructionSelector.h:365
llvm::GIM_CheckMemorySizeEqualToLLT
@ GIM_CheckMemorySizeEqualToLLT
Check the size of the memory access for the given machine memory operand against the size of an opera...
Definition: InstructionSelector.h:182
llvm::GIM_CheckFeatures
@ GIM_CheckFeatures
Check the feature bits.
Definition: InstructionSelector.h:114
SmallVector.h
llvm::GIM_CheckIsMBB
@ GIM_CheckIsMBB
Check the specified operand is an MBB.
Definition: InstructionSelector.h:248
llvm::GIM_Reject
@ GIM_Reject
Fail the current try-block, or completely fail to match if there is no current try-block.
Definition: InstructionSelector.h:278
llvm::InstructionSelector::testImmPredicate_APInt
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
Definition: InstructionSelector.h:538
bfi
< i32 > ret i32 conv5 And the following x86 eax movsbl ecx cmpl ecx sete al movzbl eax ret It should be possible to eliminate the sign extensions LLVM misses a load store narrowing opportunity in this i32 bfi
Definition: README.txt:1495
llvm::GIM_CheckCmpPredicate
@ GIM_CheckCmpPredicate
Check the operand is a specific predicate.
Definition: InstructionSelector.h:243
llvm::InstructionSelector::ISelInfoTy
Definition: InstructionSelector.h:493
llvm::InstructionSelector::CurMBB
MachineBasicBlock * CurMBB
Definition: InstructionSelector.h:446
llvm::GIM_CheckLiteralInt
@ GIM_CheckLiteralInt
Check the operand is a specific literal integer (i.e.
Definition: InstructionSelector.h:232
llvm::GIM_CheckIsBuildVectorAllZeros
@ GIM_CheckIsBuildVectorAllZeros
Definition: InstructionSelector.h:192
llvm::GIR_ComplexSubOperandRenderer
@ GIR_ComplexSubOperandRenderer
Render sub-operands of complex operands to the specified instruction.
Definition: InstructionSelector.h:352
llvm::InstructionSelector::executeMatchTable
bool executeMatchTable(TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State, const ISelInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ISelInfo, const int64_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage &CoverageInfo) const
Execute a given matcher table and return true if the match was successful and false otherwise.
Definition: InstructionSelectorImpl.h:50
llvm::GIM_CheckType
@ GIM_CheckType
Check the type for the specified operand.
Definition: InstructionSelector.h:203
llvm::GIM_CheckImmOperandPredicate
@ GIM_CheckImmOperandPredicate
Check an immediate predicate on the specified instruction.
Definition: InstructionSelector.h:148
MachineFunction.h
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::GIM_Try
@ GIM_Try
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
Definition: InstructionSelector.h:87
llvm::InstructionSelector::setupGeneratedPerFunctionState
virtual void setupGeneratedPerFunctionState(MachineFunction &MF)
Definition: InstructionSelector.h:448
llvm::InstructionSelector::select
virtual bool select(MachineInstr &I)=0
Select the (possibly generic) instruction I to only use target-specific opcodes.
llvm::PredicateBitsetImpl::PredicateBitsetImpl
PredicateBitsetImpl(std::initializer_list< unsigned > Init)
Definition: InstructionSelector.h:70
llvm::LLT
Definition: LowLevelTypeImpl.h:39