LLVM 17.0.0git
InstructionSelector.h
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1//===- llvm/CodeGen/GlobalISel/InstructionSelector.h ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file declares the API for the instruction selector.
10/// This class is responsible for selecting machine instructions.
11/// It's implemented by the target. It's used by the InstructionSelect pass.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
16#define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
17
18#include "llvm/ADT/DenseMap.h"
22#include "llvm/IR/Function.h"
24#include <bitset>
25#include <cstddef>
26#include <cstdint>
27#include <functional>
28#include <initializer_list>
29#include <optional>
30#include <vector>
31
32namespace llvm {
33
34class BlockFrequencyInfo;
35class CodeGenCoverage;
36class MachineBasicBlock;
37class ProfileSummaryInfo;
38class APInt;
39class APFloat;
40class GISelKnownBits;
41class MachineInstr;
42class MachineInstrBuilder;
43class MachineFunction;
44class MachineOperand;
45class MachineRegisterInfo;
46class RegisterBankInfo;
47class TargetInstrInfo;
48class TargetRegisterInfo;
49
50/// Container class for CodeGen predicate results.
51/// This is convenient because std::bitset does not have a constructor
52/// with an initializer list of set bits.
53///
54/// Each InstructionSelector subclass should define a PredicateBitset class
55/// with:
56/// const unsigned MAX_SUBTARGET_PREDICATES = 192;
57/// using PredicateBitset = PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
58/// and updating the constant to suit the target. Tablegen provides a suitable
59/// definition for the predicates in use in <Target>GenGlobalISel.inc when
60/// GET_GLOBALISEL_PREDICATE_BITSET is defined.
61template <std::size_t MaxPredicates>
62class PredicateBitsetImpl : public std::bitset<MaxPredicates> {
63public:
64 // Cannot inherit constructors because it's not supported by VC++..
66
67 PredicateBitsetImpl(const std::bitset<MaxPredicates> &B)
68 : std::bitset<MaxPredicates>(B) {}
69
70 PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
71 for (auto I : Init)
72 std::bitset<MaxPredicates>::set(I);
73 }
74};
75
76enum {
77 /// Begin a try-block to attempt a match and jump to OnFail if it is
78 /// unsuccessful.
79 /// - OnFail - The MatchTable entry at which to resume if the match fails.
80 ///
81 /// FIXME: This ought to take an argument indicating the number of try-blocks
82 /// to exit on failure. It's usually one but the last match attempt of
83 /// a block will need more. The (implemented) alternative is to tack a
84 /// GIM_Reject on the end of each try-block which is simpler but
85 /// requires an extra opcode and iteration in the interpreter on each
86 /// failed match.
88
89 /// Switch over the opcode on the specified instruction
90 /// - InsnID - Instruction ID
91 /// - LowerBound - numerically minimum opcode supported
92 /// - UpperBound - numerically maximum + 1 opcode supported
93 /// - Default - failure jump target
94 /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
96
97 /// Switch over the LLT on the specified instruction operand
98 /// - InsnID - Instruction ID
99 /// - OpIdx - Operand index
100 /// - LowerBound - numerically minimum Type ID supported
101 /// - UpperBound - numerically maximum + 1 Type ID supported
102 /// - Default - failure jump target
103 /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
105
106 /// Record the specified instruction.
107 /// The IgnoreCopies variant ignores COPY instructions.
108 /// - NewInsnID - Instruction ID to define
109 /// - InsnID - Instruction ID
110 /// - OpIdx - Operand index
113
114 /// Check the feature bits
115 /// - Expected features
117
118 /// Check the opcode on the specified instruction
119 /// - InsnID - Instruction ID
120 /// - Expected opcode
122
123 /// Check the opcode on the specified instruction, checking 2 acceptable
124 /// alternatives.
125 /// - InsnID - Instruction ID
126 /// - Expected opcode
127 /// - Alternative expected opcode
129
130 /// Check the instruction has the right number of operands
131 /// - InsnID - Instruction ID
132 /// - Expected number of operands
134 /// Check an immediate predicate on the specified instruction
135 /// - InsnID - Instruction ID
136 /// - The predicate to test
138 /// Check an immediate predicate on the specified instruction via an APInt.
139 /// - InsnID - Instruction ID
140 /// - The predicate to test
142 /// Check a floating point immediate predicate on the specified instruction.
143 /// - InsnID - Instruction ID
144 /// - The predicate to test
146 /// Check an immediate predicate on the specified instruction
147 /// - InsnID - Instruction ID
148 /// - OpIdx - Operand index
149 /// - The predicate to test
151 /// Check a memory operation has the specified atomic ordering.
152 /// - InsnID - Instruction ID
153 /// - Ordering - The AtomicOrdering value
157 /// Check the size of the memory access for the given machine memory operand.
158 /// - InsnID - Instruction ID
159 /// - MMOIdx - MMO index
160 /// - Size - The size in bytes of the memory access
162
163 /// Check the address space of the memory access for the given machine memory
164 /// operand.
165 /// - InsnID - Instruction ID
166 /// - MMOIdx - MMO index
167 /// - NumAddrSpace - Number of valid address spaces
168 /// - AddrSpaceN - An allowed space of the memory access
169 /// - AddrSpaceN+1 ...
171
172 /// Check the minimum alignment of the memory access for the given machine
173 /// memory operand.
174 /// - InsnID - Instruction ID
175 /// - MMOIdx - MMO index
176 /// - MinAlign - Minimum acceptable alignment
178
179 /// Check the size of the memory access for the given machine memory operand
180 /// against the size of an operand.
181 /// - InsnID - Instruction ID
182 /// - MMOIdx - MMO index
183 /// - OpIdx - The operand index to compare the MMO against
187
188 /// Check if this is a vector that can be treated as a vector splat
189 /// constant. This is valid for both G_BUILD_VECTOR as well as
190 /// G_BUILD_VECTOR_TRUNC. For AllOnes refers to individual bits, so a -1
191 /// element.
192 /// - InsnID - Instruction ID
195
196 /// Check a generic C++ instruction predicate
197 /// - InsnID - Instruction ID
198 /// - PredicateID - The ID of the predicate function to call
200
201 /// Check if there's no use of the first result.
202 /// - InsnID - Instruction ID
204
205 /// Check the type for the specified operand
206 /// - InsnID - Instruction ID
207 /// - OpIdx - Operand index
208 /// - Expected type
210 /// Check the type of a pointer to any address space.
211 /// - InsnID - Instruction ID
212 /// - OpIdx - Operand index
213 /// - SizeInBits - The size of the pointer value in bits.
215 /// Check the register bank for the specified operand
216 /// - InsnID - Instruction ID
217 /// - OpIdx - Operand index
218 /// - Expected register bank (specified as a register class)
220
221 /// Check the operand matches a complex predicate
222 /// - InsnID - Instruction ID
223 /// - OpIdx - Operand index
224 /// - RendererID - The renderer to hold the result
225 /// - Complex predicate ID
227
228 /// Check the operand is a specific integer
229 /// - InsnID - Instruction ID
230 /// - OpIdx - Operand index
231 /// - Expected integer
233 /// Check the operand is a specific literal integer (i.e. MO.isImm() or
234 /// MO.isCImm() is true).
235 /// - InsnID - Instruction ID
236 /// - OpIdx - Operand index
237 /// - Expected integer
239 /// Check the operand is a specific intrinsic ID
240 /// - InsnID - Instruction ID
241 /// - OpIdx - Operand index
242 /// - Expected Intrinsic ID
244
245 /// Check the operand is a specific predicate
246 /// - InsnID - Instruction ID
247 /// - OpIdx - Operand index
248 /// - Expected predicate
250
251 /// Check the specified operand is an MBB
252 /// - InsnID - Instruction ID
253 /// - OpIdx - Operand index
255
256 /// Check the specified operand is an Imm
257 /// - InsnID - Instruction ID
258 /// - OpIdx - Operand index
260
261 /// Check if the specified operand is safe to fold into the current
262 /// instruction.
263 /// - InsnID - Instruction ID
265
266 /// Check the specified operands are identical.
267 /// The IgnoreCopies variant looks through COPY instructions before
268 /// comparing the operands.
269 /// - InsnID - Instruction ID
270 /// - OpIdx - Operand index
271 /// - OtherInsnID - Other instruction ID
272 /// - OtherOpIdx - Other operand index
275
276 /// Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some
277 /// named operands that will be recorded in RecordedOperands. Names of these
278 /// operands are referenced in predicate argument list. Emitter determines
279 /// StoreIdx(corresponds to the order in which names appear in argument list).
280 /// - InsnID - Instruction ID
281 /// - OpIdx - Operand index
282 /// - StoreIdx - Store location in RecordedOperands.
284
285 /// Fail the current try-block, or completely fail to match if there is no
286 /// current try-block.
288
289 //=== Renderers ===
290
291 /// Mutate an instruction
292 /// - NewInsnID - Instruction ID to define
293 /// - OldInsnID - Instruction ID to mutate
294 /// - NewOpcode - The new opcode to use
296
297 /// Build a new instruction
298 /// - InsnID - Instruction ID to define
299 /// - Opcode - The new opcode to use
301
302 /// Copy an operand to the specified instruction
303 /// - NewInsnID - Instruction ID to modify
304 /// - OldInsnID - Instruction ID to copy from
305 /// - OpIdx - The operand to copy
307
308 /// Copy an operand to the specified instruction or add a zero register if the
309 /// operand is a zero immediate.
310 /// - NewInsnID - Instruction ID to modify
311 /// - OldInsnID - Instruction ID to copy from
312 /// - OpIdx - The operand to copy
313 /// - ZeroReg - The zero register to use
315 /// Copy an operand to the specified instruction
316 /// - NewInsnID - Instruction ID to modify
317 /// - OldInsnID - Instruction ID to copy from
318 /// - OpIdx - The operand to copy
319 /// - SubRegIdx - The subregister to copy
321
322 /// Add an implicit register def to the specified instruction
323 /// - InsnID - Instruction ID to modify
324 /// - RegNum - The register to add
326 /// Add an implicit register use to the specified instruction
327 /// - InsnID - Instruction ID to modify
328 /// - RegNum - The register to add
330 /// Add an register to the specified instruction
331 /// - InsnID - Instruction ID to modify
332 /// - RegNum - The register to add
334
335 /// Add a temporary register to the specified instruction
336 /// - InsnID - Instruction ID to modify
337 /// - TempRegID - The temporary register ID to add
338 /// - TempRegFlags - The register flags to set
340
341 /// Add a temporary register to the specified instruction
342 /// - InsnID - Instruction ID to modify
343 /// - TempRegID - The temporary register ID to add
344 /// - TempRegFlags - The register flags to set
345 /// - SubRegIndex - The subregister index to set
347
348 /// Add an immediate to the specified instruction
349 /// - InsnID - Instruction ID to modify
350 /// - Imm - The immediate to add
352
353 /// Render complex operands to the specified instruction
354 /// - InsnID - Instruction ID to modify
355 /// - RendererID - The renderer to call
357 /// Render sub-operands of complex operands to the specified instruction
358 /// - InsnID - Instruction ID to modify
359 /// - RendererID - The renderer to call
360 /// - RenderOpID - The suboperand to render.
362 /// Render subregisters of suboperands of complex operands to the
363 /// specified instruction
364 /// - InsnID - Instruction ID to modify
365 /// - RendererID - The renderer to call
366 /// - RenderOpID - The suboperand to render
367 /// - SubRegIdx - The subregister to extract
369
370 /// Render operands to the specified instruction using a custom function
371 /// - InsnID - Instruction ID to modify
372 /// - OldInsnID - Instruction ID to get the matched operand from
373 /// - RendererFnID - Custom renderer function to call
375
376 /// Render operands to the specified instruction using a custom function,
377 /// reading from a specific operand.
378 /// - InsnID - Instruction ID to modify
379 /// - OldInsnID - Instruction ID to get the matched operand from
380 /// - OpIdx - Operand index in OldInsnID the render function should read
381 /// from..
382 /// - RendererFnID - Custom renderer function to call
384
385 /// Render a G_CONSTANT operator as a sign-extended immediate.
386 /// - NewInsnID - Instruction ID to modify
387 /// - OldInsnID - Instruction ID to copy from
388 /// The operand index is implicitly 1.
390
391 /// Render a G_FCONSTANT operator as a sign-extended immediate.
392 /// - NewInsnID - Instruction ID to modify
393 /// - OldInsnID - Instruction ID to copy from
394 /// The operand index is implicitly 1.
396
397 /// Constrain an instruction operand to a register class.
398 /// - InsnID - Instruction ID to modify
399 /// - OpIdx - Operand index
400 /// - RCEnum - Register class enumeration value
402
403 /// Constrain an instructions operands according to the instruction
404 /// description.
405 /// - InsnID - Instruction ID to modify
407
408 /// Merge all memory operands into instruction.
409 /// - InsnID - Instruction ID to modify
410 /// - MergeInsnID... - One or more Instruction ID to merge into the result.
411 /// - GIU_MergeMemOperands_EndOfList - Terminates the list of instructions to
412 /// merge.
414
415 /// Erase from parent.
416 /// - InsnID - Instruction ID to erase
418
419 /// Create a new temporary register that's not constrained.
420 /// - TempRegID - The temporary register ID to initialize.
421 /// - Expected type
423
424 /// A successful emission
426
427 /// Increment the rule coverage counter.
428 /// - RuleID - The ID of the rule that was covered.
430
431 /// Keeping track of the number of the GI opcodes. Must be the last entry.
433};
434
435enum {
436 /// Indicates the end of the variable-length MergeInsnID list in a
437 /// GIR_MergeMemOperands opcode.
439};
440
441/// Provides the logic to select generic machine instructions.
443public:
444 virtual ~InstructionSelector() = default;
445
446 /// Select the (possibly generic) instruction \p I to only use target-specific
447 /// opcodes. It is OK to insert multiple instructions, but they cannot be
448 /// generic pre-isel instructions.
449 ///
450 /// \returns whether selection succeeded.
451 /// \pre I.getParent() && I.getParent()->getParent()
452 /// \post
453 /// if returns true:
454 /// for I in all mutated/inserted instructions:
455 /// !isPreISelGenericOpcode(I.getOpcode())
456 virtual bool select(MachineInstr &I) = 0;
457
460 MachineFunction *MF = nullptr;
463 // For some predicates, we need to track the current MBB.
465
467 llvm_unreachable("TableGen should have emitted implementation");
468 }
469
470 /// Setup per-MF selector state.
472 CodeGenCoverage &covinfo, ProfileSummaryInfo *psi,
473 BlockFrequencyInfo *bfi) {
474 CoverageInfo = &covinfo;
475 KnownBits = KB;
476 MF = &mf;
477 PSI = psi;
478 BFI = bfi;
479 CurMBB = nullptr;
481 }
482
483protected:
485 std::optional<SmallVector<std::function<void(MachineInstrBuilder &)>, 4>>;
488
490 std::vector<ComplexRendererFns::value_type> Renderers;
493 /// Named operands that predicate with 'let PredicateCodeUsesOperands = 1'
494 /// referenced in its argument list. Operands are inserted at index set by
495 /// emitter, it corresponds to the order in which names appear in argument
496 /// list. Currently such predicates don't have more then 3 arguments.
497 std::array<const MachineOperand *, 3> RecordedOperands;
498
499 MatcherState(unsigned MaxRenderers);
500 };
501
503 const auto &F = MF->getFunction();
504 return F.hasOptSize() || F.hasMinSize() ||
506 }
507
508public:
509 template <class PredicateBitset, class ComplexMatcherMemFn,
510 class CustomRendererFn>
511 struct ISelInfoTy {
512 ISelInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
513 const PredicateBitset *FeatureBitsets,
514 const ComplexMatcherMemFn *ComplexPredicates,
515 const CustomRendererFn *CustomRenderers)
520
521 for (size_t I = 0; I < NumTypeObjects; ++I)
523 }
525 const PredicateBitset *FeatureBitsets;
526 const ComplexMatcherMemFn *ComplexPredicates;
527 const CustomRendererFn *CustomRenderers;
528
530 };
531
532protected:
534
535 /// Execute a given matcher table and return true if the match was successful
536 /// and false otherwise.
537 template <class TgtInstructionSelector, class PredicateBitset,
538 class ComplexMatcherMemFn, class CustomRendererFn>
540 TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
542 &ISelInfo,
543 const int64_t *MatchTable, const TargetInstrInfo &TII,
545 const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
547
548 virtual const int64_t *getMatchTable() const {
549 llvm_unreachable("Should have been overridden by tablegen if used");
550 }
551
552 virtual bool testImmPredicate_I64(unsigned, int64_t) const {
554 "Subclasses must override this with a tablegen-erated function");
555 }
556 virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
558 "Subclasses must override this with a tablegen-erated function");
559 }
560 virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
562 "Subclasses must override this with a tablegen-erated function");
563 }
564 virtual bool testMIPredicate_MI(
565 unsigned, const MachineInstr &,
566 const std::array<const MachineOperand *, 3> &Operands) const {
568 "Subclasses must override this with a tablegen-erated function");
569 }
570
571 bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
572 const MachineRegisterInfo &MRI) const;
573
574 /// Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the
575 /// right-hand side. GlobalISel's separation of pointer and integer types
576 /// means that we don't need to worry about G_OR with equivalent semantics.
578 const MachineRegisterInfo &MRI) const;
579
580 /// Return true if MI can obviously be folded into IntoMI.
581 /// MI and IntoMI do not need to be in the same basic blocks, but MI must
582 /// preceed IntoMI.
584};
585
586} // end namespace llvm
587
588#endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
This file defines the DenseMap class.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
Implement a low-level type suitable for MachineInstr level instruction selection.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
unsigned const TargetRegisterInfo * TRI
This file defines the SmallVector class.
Class for arbitrary precision integers.
Definition: APInt.h:75
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Provides the logic to select generic machine instructions.
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
virtual bool testImmPredicate_I64(unsigned, int64_t) const
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
bool isBaseWithConstantOffset(const MachineOperand &Root, const MachineRegisterInfo &MRI) const
Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the right-hand side.
bool shouldOptForSize(const MachineFunction *MF) const
virtual bool select(MachineInstr &I)=0
Select the (possibly generic) instruction I to only use target-specific opcodes.
virtual ~InstructionSelector()=default
virtual void setupMF(MachineFunction &mf, GISelKnownBits *KB, CodeGenCoverage &covinfo, ProfileSummaryInfo *psi, BlockFrequencyInfo *bfi)
Setup per-MF selector state.
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
virtual const int64_t * getMatchTable() const
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &, const std::array< const MachineOperand *, 3 > &Operands) const
bool executeMatchTable(TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State, const ISelInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ISelInfo, const int64_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage &CoverageInfo) const
Execute a given matcher table and return true if the match was successful and false otherwise.
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
virtual void setupGeneratedPerFunctionState(MachineFunction &MF)
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Container class for CodeGen predicate results.
PredicateBitsetImpl(std::initializer_list< unsigned > Init)
PredicateBitsetImpl(const std::bitset< MaxPredicates > &B)
Analysis providing profile information.
Holds all the information related to register banks.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ GIU_MergeMemOperands_EndOfList
Indicates the end of the variable-length MergeInsnID list in a GIR_MergeMemOperands opcode.
@ GIR_ComplexRenderer
Render complex operands to the specified instruction.
@ GIR_ComplexSubOperandRenderer
Render sub-operands of complex operands to the specified instruction.
@ GIR_MakeTempReg
Create a new temporary register that's not constrained.
@ GIM_CheckMemorySizeEqualTo
Check the size of the memory access for the given machine memory operand.
@ GIR_Done
A successful emission.
@ GIM_RecordNamedOperand
Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some named operands that will be ...
@ GIM_Try
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
@ GIM_CheckIsBuildVectorAllOnes
Check if this is a vector that can be treated as a vector splat constant.
@ GIM_CheckNumOperands
Check the instruction has the right number of operands.
@ GIR_ConstrainOperandRC
Constrain an instruction operand to a register class.
@ GIM_CheckI64ImmPredicate
Check an immediate predicate on the specified instruction.
@ GIR_AddImplicitDef
Add an implicit register def to the specified instruction.
@ GIM_CheckAPIntImmPredicate
Check an immediate predicate on the specified instruction via an APInt.
@ GIM_CheckHasNoUse
Check if there's no use of the first result.
@ GIM_CheckPointerToAny
Check the type of a pointer to any address space.
@ GIM_CheckMemorySizeEqualToLLT
Check the size of the memory access for the given machine memory operand against the size of an opera...
@ GIM_CheckComplexPattern
Check the operand matches a complex predicate.
@ GIR_CopyConstantAsSImm
Render a G_CONSTANT operator as a sign-extended immediate.
@ GIR_EraseFromParent
Erase from parent.
@ GIM_SwitchType
Switch over the LLT on the specified instruction operand.
@ GIR_CopySubReg
Copy an operand to the specified instruction.
@ GIR_MutateOpcode
Mutate an instruction.
@ GIM_CheckIsBuildVectorAllZeros
@ GIM_CheckAtomicOrderingOrStrongerThan
@ GIR_AddRegister
Add an register to the specified instruction.
@ GIR_AddTempSubRegister
Add a temporary register to the specified instruction.
@ GIM_CheckIsSafeToFold
Check if the specified operand is safe to fold into the current instruction.
@ GIM_CheckOpcode
Check the opcode on the specified instruction.
@ GIM_SwitchOpcode
Switch over the opcode on the specified instruction.
@ GIM_CheckAPFloatImmPredicate
Check a floating point immediate predicate on the specified instruction.
@ GIM_Reject
Fail the current try-block, or completely fail to match if there is no current try-block.
@ GIR_AddTempRegister
Add a temporary register to the specified instruction.
@ GIR_Copy
Copy an operand to the specified instruction.
@ GIR_AddImm
Add an immediate to the specified instruction.
@ GIR_CopyFConstantAsFPImm
Render a G_FCONSTANT operator as a sign-extended immediate.
@ GIU_NumOpcodes
Keeping track of the number of the GI opcodes. Must be the last entry.
@ GIR_CopyOrAddZeroReg
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
@ GIM_CheckMemoryAlignment
Check the minimum alignment of the memory access for the given machine memory operand.
@ GIM_CheckIsSameOperand
Check the specified operands are identical.
@ GIM_CheckIsSameOperandIgnoreCopies
@ GIM_CheckIsMBB
Check the specified operand is an MBB.
@ GIM_CheckMemorySizeGreaterThanLLT
@ GIM_CheckRegBankForClass
Check the register bank for the specified operand.
@ GIM_CheckLiteralInt
Check the operand is a specific literal integer (i.e.
@ GIM_CheckMemorySizeLessThanLLT
@ GIR_BuildMI
Build a new instruction.
@ GIM_RecordInsn
Record the specified instruction.
@ GIM_CheckIsImm
Check the specified operand is an Imm.
@ GIM_CheckFeatures
Check the feature bits.
@ GIM_CheckMemoryAddressSpace
Check the address space of the memory access for the given machine memory operand.
@ GIR_CustomRenderer
Render operands to the specified instruction using a custom function.
@ GIM_CheckAtomicOrdering
Check a memory operation has the specified atomic ordering.
@ GIM_CheckType
Check the type for the specified operand.
@ GIM_CheckCmpPredicate
Check the operand is a specific predicate.
@ GIM_CheckOpcodeIsEither
Check the opcode on the specified instruction, checking 2 acceptable alternatives.
@ GIR_AddImplicitUse
Add an implicit register use to the specified instruction.
@ GIR_Coverage
Increment the rule coverage counter.
@ GIR_MergeMemOperands
Merge all memory operands into instruction.
@ GIM_CheckImmOperandPredicate
Check an immediate predicate on the specified instruction.
@ GIM_CheckAtomicOrderingWeakerThan
@ GIM_CheckIntrinsicID
Check the operand is a specific intrinsic ID.
@ GIM_CheckConstantInt
Check the operand is a specific integer.
@ GIR_ComplexSubOperandSubRegRenderer
Render subregisters of suboperands of complex operands to the specified instruction.
@ GIM_RecordInsnIgnoreCopies
@ GIR_CustomOperandRenderer
Render operands to the specified instruction using a custom function, reading from a specific operand...
@ GIR_ConstrainSelectedInstOperands
Constrain an instructions operands according to the instruction description.
@ GIM_CheckCxxInsnPredicate
Check a generic C++ instruction predicate.
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:1326
Definition: BitVector.h:858
const ComplexMatcherMemFn * ComplexPredicates
SmallDenseMap< LLT, unsigned, 64 > TypeIDMap
ISelInfoTy(const LLT *TypeObjects, size_t NumTypeObjects, const PredicateBitset *FeatureBitsets, const ComplexMatcherMemFn *ComplexPredicates, const CustomRendererFn *CustomRenderers)
std::array< const MachineOperand *, 3 > RecordedOperands
Named operands that predicate with 'let PredicateCodeUsesOperands = 1' referenced in its argument lis...
std::vector< ComplexRendererFns::value_type > Renderers
DenseMap< unsigned, unsigned > TempRegisters