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InstructionSelector.h
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1 //===- llvm/CodeGen/GlobalISel/InstructionSelector.h ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API for the instruction selector.
10 /// This class is responsible for selecting machine instructions.
11 /// It's implemented by the target. It's used by the InstructionSelect pass.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
16 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
17 
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/Optional.h"
20 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/IR/Function.h"
25 #include <bitset>
26 #include <cstddef>
27 #include <cstdint>
28 #include <functional>
29 #include <initializer_list>
30 #include <vector>
31 
32 namespace llvm {
33 
34 class BlockFrequencyInfo;
35 class CodeGenCoverage;
36 class MachineBasicBlock;
37 class ProfileSummaryInfo;
38 class APInt;
39 class APFloat;
40 class GISelKnownBits;
41 class MachineInstr;
42 class MachineInstrBuilder;
43 class MachineFunction;
44 class MachineOperand;
45 class MachineRegisterInfo;
46 class RegisterBankInfo;
47 class TargetInstrInfo;
48 class TargetRegisterInfo;
49 
50 /// Container class for CodeGen predicate results.
51 /// This is convenient because std::bitset does not have a constructor
52 /// with an initializer list of set bits.
53 ///
54 /// Each InstructionSelector subclass should define a PredicateBitset class
55 /// with:
56 /// const unsigned MAX_SUBTARGET_PREDICATES = 192;
57 /// using PredicateBitset = PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
58 /// and updating the constant to suit the target. Tablegen provides a suitable
59 /// definition for the predicates in use in <Target>GenGlobalISel.inc when
60 /// GET_GLOBALISEL_PREDICATE_BITSET is defined.
61 template <std::size_t MaxPredicates>
62 class PredicateBitsetImpl : public std::bitset<MaxPredicates> {
63 public:
64  // Cannot inherit constructors because it's not supported by VC++..
65  PredicateBitsetImpl() = default;
66 
67  PredicateBitsetImpl(const std::bitset<MaxPredicates> &B)
68  : std::bitset<MaxPredicates>(B) {}
69 
70  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
71  for (auto I : Init)
73  }
74 };
75 
76 enum {
77  /// Begin a try-block to attempt a match and jump to OnFail if it is
78  /// unsuccessful.
79  /// - OnFail - The MatchTable entry at which to resume if the match fails.
80  ///
81  /// FIXME: This ought to take an argument indicating the number of try-blocks
82  /// to exit on failure. It's usually one but the last match attempt of
83  /// a block will need more. The (implemented) alternative is to tack a
84  /// GIM_Reject on the end of each try-block which is simpler but
85  /// requires an extra opcode and iteration in the interpreter on each
86  /// failed match.
88 
89  /// Switch over the opcode on the specified instruction
90  /// - InsnID - Instruction ID
91  /// - LowerBound - numerically minimum opcode supported
92  /// - UpperBound - numerically maximum + 1 opcode supported
93  /// - Default - failure jump target
94  /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
96 
97  /// Switch over the LLT on the specified instruction operand
98  /// - InsnID - Instruction ID
99  /// - OpIdx - Operand index
100  /// - LowerBound - numerically minimum Type ID supported
101  /// - UpperBound - numerically maximum + 1 Type ID supported
102  /// - Default - failure jump target
103  /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
105 
106  /// Record the specified instruction
107  /// - NewInsnID - Instruction ID to define
108  /// - InsnID - Instruction ID
109  /// - OpIdx - Operand index
111 
112  /// Check the feature bits
113  /// - Expected features
115 
116  /// Check the opcode on the specified instruction
117  /// - InsnID - Instruction ID
118  /// - Expected opcode
120 
121  /// Check the opcode on the specified instruction, checking 2 acceptable
122  /// alternatives.
123  /// - InsnID - Instruction ID
124  /// - Expected opcode
125  /// - Alternative expected opcode
127 
128  /// Check the instruction has the right number of operands
129  /// - InsnID - Instruction ID
130  /// - Expected number of operands
132  /// Check an immediate predicate on the specified instruction
133  /// - InsnID - Instruction ID
134  /// - The predicate to test
136  /// Check an immediate predicate on the specified instruction via an APInt.
137  /// - InsnID - Instruction ID
138  /// - The predicate to test
140  /// Check a floating point immediate predicate on the specified instruction.
141  /// - InsnID - Instruction ID
142  /// - The predicate to test
144  /// Check an immediate predicate on the specified instruction
145  /// - InsnID - Instruction ID
146  /// - OpIdx - Operand index
147  /// - The predicate to test
149  /// Check a memory operation has the specified atomic ordering.
150  /// - InsnID - Instruction ID
151  /// - Ordering - The AtomicOrdering value
155  /// Check the size of the memory access for the given machine memory operand.
156  /// - InsnID - Instruction ID
157  /// - MMOIdx - MMO index
158  /// - Size - The size in bytes of the memory access
160 
161  /// Check the address space of the memory access for the given machine memory
162  /// operand.
163  /// - InsnID - Instruction ID
164  /// - MMOIdx - MMO index
165  /// - NumAddrSpace - Number of valid address spaces
166  /// - AddrSpaceN - An allowed space of the memory access
167  /// - AddrSpaceN+1 ...
169 
170  /// Check the minimum alignment of the memory access for the given machine
171  /// memory operand.
172  /// - InsnID - Instruction ID
173  /// - MMOIdx - MMO index
174  /// - MinAlign - Minimum acceptable alignment
176 
177  /// Check the size of the memory access for the given machine memory operand
178  /// against the size of an operand.
179  /// - InsnID - Instruction ID
180  /// - MMOIdx - MMO index
181  /// - OpIdx - The operand index to compare the MMO against
185 
186  /// Check if this is a vector that can be treated as a vector splat
187  /// constant. This is valid for both G_BUILD_VECTOR as well as
188  /// G_BUILD_VECTOR_TRUNC. For AllOnes refers to individual bits, so a -1
189  /// element.
190  /// - InsnID - Instruction ID
193 
194  /// Check a generic C++ instruction predicate
195  /// - InsnID - Instruction ID
196  /// - PredicateID - The ID of the predicate function to call
198 
199  /// Check if there's no use of the first result.
200  /// - InsnID - Instruction ID
202 
203  /// Check the type for the specified operand
204  /// - InsnID - Instruction ID
205  /// - OpIdx - Operand index
206  /// - Expected type
208  /// Check the type of a pointer to any address space.
209  /// - InsnID - Instruction ID
210  /// - OpIdx - Operand index
211  /// - SizeInBits - The size of the pointer value in bits.
213  /// Check the register bank for the specified operand
214  /// - InsnID - Instruction ID
215  /// - OpIdx - Operand index
216  /// - Expected register bank (specified as a register class)
218 
219  /// Check the operand matches a complex predicate
220  /// - InsnID - Instruction ID
221  /// - OpIdx - Operand index
222  /// - RendererID - The renderer to hold the result
223  /// - Complex predicate ID
225 
226  /// Check the operand is a specific integer
227  /// - InsnID - Instruction ID
228  /// - OpIdx - Operand index
229  /// - Expected integer
231  /// Check the operand is a specific literal integer (i.e. MO.isImm() or
232  /// MO.isCImm() is true).
233  /// - InsnID - Instruction ID
234  /// - OpIdx - Operand index
235  /// - Expected integer
237  /// Check the operand is a specific intrinsic ID
238  /// - InsnID - Instruction ID
239  /// - OpIdx - Operand index
240  /// - Expected Intrinsic ID
242 
243  /// Check the operand is a specific predicate
244  /// - InsnID - Instruction ID
245  /// - OpIdx - Operand index
246  /// - Expected predicate
248 
249  /// Check the specified operand is an MBB
250  /// - InsnID - Instruction ID
251  /// - OpIdx - Operand index
253 
254  /// Check the specified operand is an Imm
255  /// - InsnID - Instruction ID
256  /// - OpIdx - Operand index
258 
259  /// Check if the specified operand is safe to fold into the current
260  /// instruction.
261  /// - InsnID - Instruction ID
263 
264  /// Check the specified operands are identical.
265  /// - InsnID - Instruction ID
266  /// - OpIdx - Operand index
267  /// - OtherInsnID - Other instruction ID
268  /// - OtherOpIdx - Other operand index
270 
271  /// Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some
272  /// named operands that will be recorded in RecordedOperands. Names of these
273  /// operands are referenced in predicate argument list. Emitter determines
274  /// StoreIdx(corresponds to the order in which names appear in argument list).
275  /// - InsnID - Instruction ID
276  /// - OpIdx - Operand index
277  /// - StoreIdx - Store location in RecordedOperands.
279 
280  /// Fail the current try-block, or completely fail to match if there is no
281  /// current try-block.
283 
284  //=== Renderers ===
285 
286  /// Mutate an instruction
287  /// - NewInsnID - Instruction ID to define
288  /// - OldInsnID - Instruction ID to mutate
289  /// - NewOpcode - The new opcode to use
291 
292  /// Build a new instruction
293  /// - InsnID - Instruction ID to define
294  /// - Opcode - The new opcode to use
296 
297  /// Copy an operand to the specified instruction
298  /// - NewInsnID - Instruction ID to modify
299  /// - OldInsnID - Instruction ID to copy from
300  /// - OpIdx - The operand to copy
302 
303  /// Copy an operand to the specified instruction or add a zero register if the
304  /// operand is a zero immediate.
305  /// - NewInsnID - Instruction ID to modify
306  /// - OldInsnID - Instruction ID to copy from
307  /// - OpIdx - The operand to copy
308  /// - ZeroReg - The zero register to use
310  /// Copy an operand to the specified instruction
311  /// - NewInsnID - Instruction ID to modify
312  /// - OldInsnID - Instruction ID to copy from
313  /// - OpIdx - The operand to copy
314  /// - SubRegIdx - The subregister to copy
316 
317  /// Add an implicit register def to the specified instruction
318  /// - InsnID - Instruction ID to modify
319  /// - RegNum - The register to add
321  /// Add an implicit register use to the specified instruction
322  /// - InsnID - Instruction ID to modify
323  /// - RegNum - The register to add
325  /// Add an register to the specified instruction
326  /// - InsnID - Instruction ID to modify
327  /// - RegNum - The register to add
329 
330  /// Add a temporary register to the specified instruction
331  /// - InsnID - Instruction ID to modify
332  /// - TempRegID - The temporary register ID to add
333  /// - TempRegFlags - The register flags to set
335 
336  /// Add a temporary register to the specified instruction
337  /// - InsnID - Instruction ID to modify
338  /// - TempRegID - The temporary register ID to add
339  /// - TempRegFlags - The register flags to set
340  /// - SubRegIndex - The subregister index to set
342 
343  /// Add an immediate to the specified instruction
344  /// - InsnID - Instruction ID to modify
345  /// - Imm - The immediate to add
347  /// Render complex operands to the specified instruction
348  /// - InsnID - Instruction ID to modify
349  /// - RendererID - The renderer to call
351 
352  /// Render sub-operands of complex operands to the specified instruction
353  /// - InsnID - Instruction ID to modify
354  /// - RendererID - The renderer to call
355  /// - RenderOpID - The suboperand to render.
357  /// Render operands to the specified instruction using a custom function
358  /// - InsnID - Instruction ID to modify
359  /// - OldInsnID - Instruction ID to get the matched operand from
360  /// - RendererFnID - Custom renderer function to call
362 
363  /// Render operands to the specified instruction using a custom function,
364  /// reading from a specific operand.
365  /// - InsnID - Instruction ID to modify
366  /// - OldInsnID - Instruction ID to get the matched operand from
367  /// - OpIdx - Operand index in OldInsnID the render function should read from..
368  /// - RendererFnID - Custom renderer function to call
370 
371  /// Render a G_CONSTANT operator as a sign-extended immediate.
372  /// - NewInsnID - Instruction ID to modify
373  /// - OldInsnID - Instruction ID to copy from
374  /// The operand index is implicitly 1.
376 
377  /// Render a G_FCONSTANT operator as a sign-extended immediate.
378  /// - NewInsnID - Instruction ID to modify
379  /// - OldInsnID - Instruction ID to copy from
380  /// The operand index is implicitly 1.
382 
383  /// Constrain an instruction operand to a register class.
384  /// - InsnID - Instruction ID to modify
385  /// - OpIdx - Operand index
386  /// - RCEnum - Register class enumeration value
388 
389  /// Constrain an instructions operands according to the instruction
390  /// description.
391  /// - InsnID - Instruction ID to modify
393 
394  /// Merge all memory operands into instruction.
395  /// - InsnID - Instruction ID to modify
396  /// - MergeInsnID... - One or more Instruction ID to merge into the result.
397  /// - GIU_MergeMemOperands_EndOfList - Terminates the list of instructions to
398  /// merge.
400 
401  /// Erase from parent.
402  /// - InsnID - Instruction ID to erase
404 
405  /// Create a new temporary register that's not constrained.
406  /// - TempRegID - The temporary register ID to initialize.
407  /// - Expected type
409 
410  /// A successful emission
412 
413  /// Increment the rule coverage counter.
414  /// - RuleID - The ID of the rule that was covered.
416 
417  /// Keeping track of the number of the GI opcodes. Must be the last entry.
419 };
420 
421 enum {
422  /// Indicates the end of the variable-length MergeInsnID list in a
423  /// GIR_MergeMemOperands opcode.
425 };
426 
427 /// Provides the logic to select generic machine instructions.
429 public:
430  virtual ~InstructionSelector() = default;
431 
432  /// Select the (possibly generic) instruction \p I to only use target-specific
433  /// opcodes. It is OK to insert multiple instructions, but they cannot be
434  /// generic pre-isel instructions.
435  ///
436  /// \returns whether selection succeeded.
437  /// \pre I.getParent() && I.getParent()->getParent()
438  /// \post
439  /// if returns true:
440  /// for I in all mutated/inserted instructions:
441  /// !isPreISelGenericOpcode(I.getOpcode())
442  virtual bool select(MachineInstr &I) = 0;
443 
446  MachineFunction *MF = nullptr;
449  // For some predicates, we need to track the current MBB.
451 
453  llvm_unreachable("TableGen should have emitted implementation");
454  }
455 
456  /// Setup per-MF selector state.
457  virtual void setupMF(MachineFunction &mf, GISelKnownBits *KB,
458  CodeGenCoverage &covinfo, ProfileSummaryInfo *psi,
460  CoverageInfo = &covinfo;
461  KnownBits = KB;
462  MF = &mf;
463  PSI = psi;
464  BFI = bfi;
465  CurMBB = nullptr;
467  }
468 
469 protected:
470  using ComplexRendererFns =
474 
475  struct MatcherState {
476  std::vector<ComplexRendererFns::value_type> Renderers;
479  /// Named operands that predicate with 'let PredicateCodeUsesOperands = 1'
480  /// referenced in its argument list. Operands are inserted at index set by
481  /// emitter, it corresponds to the order in which names appear in argument
482  /// list. Currently such predicates don't have more then 3 arguments.
483  std::array<const MachineOperand *, 3> RecordedOperands;
484 
485  MatcherState(unsigned MaxRenderers);
486  };
487 
488  bool shouldOptForSize(const MachineFunction *MF) const {
489  const auto &F = MF->getFunction();
490  return F.hasOptSize() || F.hasMinSize() ||
492  }
493 
494 public:
495  template <class PredicateBitset, class ComplexMatcherMemFn,
496  class CustomRendererFn>
497  struct ISelInfoTy {
498  ISelInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
499  const PredicateBitset *FeatureBitsets,
500  const ComplexMatcherMemFn *ComplexPredicates,
501  const CustomRendererFn *CustomRenderers)
506 
507  for (size_t I = 0; I < NumTypeObjects; ++I)
508  TypeIDMap[TypeObjects[I]] = I;
509  }
510  const LLT *TypeObjects;
511  const PredicateBitset *FeatureBitsets;
512  const ComplexMatcherMemFn *ComplexPredicates;
513  const CustomRendererFn *CustomRenderers;
514 
516  };
517 
518 protected:
520 
521  /// Execute a given matcher table and return true if the match was successful
522  /// and false otherwise.
523  template <class TgtInstructionSelector, class PredicateBitset,
524  class ComplexMatcherMemFn, class CustomRendererFn>
525  bool executeMatchTable(
526  TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
528  &ISelInfo,
529  const int64_t *MatchTable, const TargetInstrInfo &TII,
531  const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
533 
534  virtual const int64_t *getMatchTable() const {
535  llvm_unreachable("Should have been overridden by tablegen if used");
536  }
537 
538  virtual bool testImmPredicate_I64(unsigned, int64_t) const {
540  "Subclasses must override this with a tablegen-erated function");
541  }
542  virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
544  "Subclasses must override this with a tablegen-erated function");
545  }
546  virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
548  "Subclasses must override this with a tablegen-erated function");
549  }
550  virtual bool testMIPredicate_MI(
551  unsigned, const MachineInstr &,
552  const std::array<const MachineOperand *, 3> &Operands) const {
554  "Subclasses must override this with a tablegen-erated function");
555  }
556 
557  bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
558  const MachineRegisterInfo &MRI) const;
559 
560  /// Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the
561  /// right-hand side. GlobalISel's separation of pointer and integer types
562  /// means that we don't need to worry about G_OR with equivalent semantics.
563  bool isBaseWithConstantOffset(const MachineOperand &Root,
564  const MachineRegisterInfo &MRI) const;
565 
566  /// Return true if MI can obviously be folded into IntoMI.
567  /// MI and IntoMI do not need to be in the same basic blocks, but MI must
568  /// preceed IntoMI.
569  bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const;
570 };
571 
572 } // end namespace llvm
573 
574 #endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:459
set
We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 atomic and others It is also currently not done for read modify write instructions It is also current not done if the OF or CF flags are needed The shift operators have the complication that when the shift count is EFLAGS is not set
Definition: README.txt:1277
llvm::InstructionSelector::MatcherState::Renderers
std::vector< ComplexRendererFns::value_type > Renderers
Definition: InstructionSelector.h:476
llvm::GIM_RecordInsn
@ GIM_RecordInsn
Record the specified instruction.
Definition: InstructionSelector.h:110
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm::GIR_CopyOrAddZeroReg
@ GIR_CopyOrAddZeroReg
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
Definition: InstructionSelector.h:309
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::GIM_CheckIsSafeToFold
@ GIM_CheckIsSafeToFold
Check if the specified operand is safe to fold into the current instruction.
Definition: InstructionSelector.h:262
Optional.h
llvm::GIR_ComplexRenderer
@ GIR_ComplexRenderer
Render complex operands to the specified instruction.
Definition: InstructionSelector.h:350
llvm::GIM_CheckAtomicOrdering
@ GIM_CheckAtomicOrdering
Check a memory operation has the specified atomic ordering.
Definition: InstructionSelector.h:152
llvm::GIR_EraseFromParent
@ GIR_EraseFromParent
Erase from parent.
Definition: InstructionSelector.h:403
llvm::InstructionSelector::testMIPredicate_MI
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &, const std::array< const MachineOperand *, 3 > &Operands) const
Definition: InstructionSelector.h:550
llvm::GIR_CustomRenderer
@ GIR_CustomRenderer
Render operands to the specified instruction using a custom function.
Definition: InstructionSelector.h:361
llvm::GIM_Try
@ GIM_Try
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
Definition: InstructionSelector.h:87
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::GIM_CheckIsSameOperand
@ GIM_CheckIsSameOperand
Check the specified operands are identical.
Definition: InstructionSelector.h:269
llvm::InstructionSelector::getMatchTable
virtual const int64_t * getMatchTable() const
Definition: InstructionSelector.h:534
llvm::GIM_CheckLiteralInt
@ GIM_CheckLiteralInt
Check the operand is a specific literal integer (i.e.
Definition: InstructionSelector.h:236
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::GIM_CheckI64ImmPredicate
@ GIM_CheckI64ImmPredicate
Check an immediate predicate on the specified instruction.
Definition: InstructionSelector.h:135
llvm::GIR_ConstrainOperandRC
@ GIR_ConstrainOperandRC
Constrain an instruction operand to a register class.
Definition: InstructionSelector.h:387
llvm::SmallDenseMap
Definition: DenseMap.h:880
llvm::InstructionSelector::MatcherState
Definition: InstructionSelector.h:475
llvm::InstructionSelector::setupMF
virtual void setupMF(MachineFunction &mf, GISelKnownBits *KB, CodeGenCoverage &covinfo, ProfileSummaryInfo *psi, BlockFrequencyInfo *bfi)
Setup per-MF selector state.
Definition: InstructionSelector.h:457
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
llvm::shouldOptForSize
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:1320
DenseMap.h
llvm::GIM_CheckPointerToAny
@ GIM_CheckPointerToAny
Check the type of a pointer to any address space.
Definition: InstructionSelector.h:212
llvm::InstructionSelector::MatcherState::MIs
RecordedMIVector MIs
Definition: InstructionSelector.h:477
llvm::Optional
Definition: APInt.h:33
llvm::GIM_CheckHasNoUse
@ GIM_CheckHasNoUse
Check if there's no use of the first result.
Definition: InstructionSelector.h:201
llvm::InstructionSelector::testImmPredicate_I64
virtual bool testImmPredicate_I64(unsigned, int64_t) const
Definition: InstructionSelector.h:538
llvm::GIM_CheckMemoryAlignment
@ GIM_CheckMemoryAlignment
Check the minimum alignment of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:175
llvm::GIM_CheckIntrinsicID
@ GIM_CheckIntrinsicID
Check the operand is a specific intrinsic ID.
Definition: InstructionSelector.h:241
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::InstructionSelector::ISelInfoTy::ISelInfoTy
ISelInfoTy(const LLT *TypeObjects, size_t NumTypeObjects, const PredicateBitset *FeatureBitsets, const ComplexMatcherMemFn *ComplexPredicates, const CustomRendererFn *CustomRenderers)
Definition: InstructionSelector.h:498
llvm::GIM_CheckType
@ GIM_CheckType
Check the type for the specified operand.
Definition: InstructionSelector.h:207
llvm::InstructionSelector::MatcherState::TempRegisters
DenseMap< unsigned, unsigned > TempRegisters
Definition: InstructionSelector.h:478
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::GIR_CopyConstantAsSImm
@ GIR_CopyConstantAsSImm
Render a G_CONSTANT operator as a sign-extended immediate.
Definition: InstructionSelector.h:375
llvm::GIU_NumOpcodes
@ GIU_NumOpcodes
Keeping track of the number of the GI opcodes. Must be the last entry.
Definition: InstructionSelector.h:418
llvm::GIR_AddTempSubRegister
@ GIR_AddTempSubRegister
Add a temporary register to the specified instruction.
Definition: InstructionSelector.h:341
llvm::GIM_CheckAtomicOrderingWeakerThan
@ GIM_CheckAtomicOrderingWeakerThan
Definition: InstructionSelector.h:154
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::InstructionSelector::ISelInfoTy::CustomRenderers
const CustomRendererFn * CustomRenderers
Definition: InstructionSelector.h:513
llvm::GIR_ComplexSubOperandRenderer
@ GIR_ComplexSubOperandRenderer
Render sub-operands of complex operands to the specified instruction.
Definition: InstructionSelector.h:356
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::InstructionSelector::~InstructionSelector
virtual ~InstructionSelector()=default
llvm::GIM_CheckCmpPredicate
@ GIM_CheckCmpPredicate
Check the operand is a specific predicate.
Definition: InstructionSelector.h:247
llvm::GIM_Reject
@ GIM_Reject
Fail the current try-block, or completely fail to match if there is no current try-block.
Definition: InstructionSelector.h:282
llvm::InstructionSelector::CoverageInfo
CodeGenCoverage * CoverageInfo
Definition: InstructionSelector.h:444
Utils.h
llvm::GIR_AddRegister
@ GIR_AddRegister
Add an register to the specified instruction.
Definition: InstructionSelector.h:328
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::GIR_MutateOpcode
@ GIR_MutateOpcode
Mutate an instruction.
Definition: InstructionSelector.h:290
llvm::InstructionSelector::MatcherState::RecordedOperands
std::array< const MachineOperand *, 3 > RecordedOperands
Named operands that predicate with 'let PredicateCodeUsesOperands = 1' referenced in its argument lis...
Definition: InstructionSelector.h:483
llvm::GIR_Copy
@ GIR_Copy
Copy an operand to the specified instruction.
Definition: InstructionSelector.h:301
llvm::GIM_CheckComplexPattern
@ GIM_CheckComplexPattern
Check the operand matches a complex predicate.
Definition: InstructionSelector.h:224
llvm::GIR_MakeTempReg
@ GIR_MakeTempReg
Create a new temporary register that's not constrained.
Definition: InstructionSelector.h:408
llvm::InstructionSelector::InstructionSelector
InstructionSelector()
llvm::GIR_AddImplicitUse
@ GIR_AddImplicitUse
Add an implicit register use to the specified instruction.
Definition: InstructionSelector.h:324
llvm::GIR_Coverage
@ GIR_Coverage
Increment the rule coverage counter.
Definition: InstructionSelector.h:415
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
LowLevelTypeImpl.h
llvm::GIM_CheckMemorySizeEqualToLLT
@ GIM_CheckMemorySizeEqualToLLT
Check the size of the memory access for the given machine memory operand against the size of an opera...
Definition: InstructionSelector.h:182
llvm::GIM_CheckAPFloatImmPredicate
@ GIM_CheckAPFloatImmPredicate
Check a floating point immediate predicate on the specified instruction.
Definition: InstructionSelector.h:143
llvm::GIR_BuildMI
@ GIR_BuildMI
Build a new instruction.
Definition: InstructionSelector.h:295
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:40
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::InstructionSelector::MF
MachineFunction * MF
Definition: InstructionSelector.h:446
llvm::InstructionSelector::isOperandImmEqual
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
Definition: InstructionSelector.cpp:29
llvm::APFloat
Definition: APFloat.h:716
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::InstructionSelector::ISelInfoTy::TypeIDMap
SmallDenseMap< LLT, unsigned, 64 > TypeIDMap
Definition: InstructionSelector.h:515
llvm::GIM_CheckCxxInsnPredicate
@ GIM_CheckCxxInsnPredicate
Check a generic C++ instruction predicate.
Definition: InstructionSelector.h:197
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:428
llvm::CodeGenCoverage
Definition: CodeGenCoverage.h:19
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::DenseMap< unsigned, unsigned >
llvm::GIM_CheckMemorySizeLessThanLLT
@ GIM_CheckMemorySizeLessThanLLT
Definition: InstructionSelector.h:183
llvm::GIM_CheckIsMBB
@ GIM_CheckIsMBB
Check the specified operand is an MBB.
Definition: InstructionSelector.h:252
llvm::InstructionSelector::shouldOptForSize
bool shouldOptForSize(const MachineFunction *MF) const
Definition: InstructionSelector.h:488
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::GIM_CheckFeatures
@ GIM_CheckFeatures
Check the feature bits.
Definition: InstructionSelector.h:114
llvm::InstructionSelector::ISelInfoTy::TypeObjects
const LLT * TypeObjects
Definition: InstructionSelector.h:510
llvm::GIR_AddImm
@ GIR_AddImm
Add an immediate to the specified instruction.
Definition: InstructionSelector.h:346
llvm::PredicateBitsetImpl
Container class for CodeGen predicate results.
Definition: InstructionSelector.h:62
llvm::GIM_CheckNumOperands
@ GIM_CheckNumOperands
Check the instruction has the right number of operands.
Definition: InstructionSelector.h:131
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::InstructionSelector::ComplexRendererFns
Optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
Definition: InstructionSelector.h:471
llvm::GIR_CopyFConstantAsFPImm
@ GIR_CopyFConstantAsFPImm
Render a G_FCONSTANT operator as a sign-extended immediate.
Definition: InstructionSelector.h:381
llvm::GIM_SwitchType
@ GIM_SwitchType
Switch over the LLT on the specified instruction operand.
Definition: InstructionSelector.h:104
llvm::GIM_CheckOpcode
@ GIM_CheckOpcode
Check the opcode on the specified instruction.
Definition: InstructionSelector.h:119
llvm::GIM_CheckMemorySizeEqualTo
@ GIM_CheckMemorySizeEqualTo
Check the size of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:159
llvm::InstructionSelector::MatcherState::MatcherState
MatcherState(unsigned MaxRenderers)
Definition: InstructionSelector.cpp:24
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::GIR_ConstrainSelectedInstOperands
@ GIR_ConstrainSelectedInstOperands
Constrain an instructions operands according to the instruction description.
Definition: InstructionSelector.h:392
llvm::GIM_CheckAPIntImmPredicate
@ GIM_CheckAPIntImmPredicate
Check an immediate predicate on the specified instruction via an APInt.
Definition: InstructionSelector.h:139
llvm::InstructionSelector::testImmPredicate_APFloat
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
Definition: InstructionSelector.h:546
llvm::GIM_CheckIsImm
@ GIM_CheckIsImm
Check the specified operand is an Imm.
Definition: InstructionSelector.h:257
llvm::GIR_CopySubReg
@ GIR_CopySubReg
Copy an operand to the specified instruction.
Definition: InstructionSelector.h:315
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::InstructionSelector::isBaseWithConstantOffset
bool isBaseWithConstantOffset(const MachineOperand &Root, const MachineRegisterInfo &MRI) const
Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the right-hand side.
Definition: InstructionSelector.cpp:38
llvm::GIR_AddImplicitDef
@ GIR_AddImplicitDef
Add an implicit register def to the specified instruction.
Definition: InstructionSelector.h:320
llvm::InstructionSelector::BFI
BlockFrequencyInfo * BFI
Definition: InstructionSelector.h:448
llvm::GIR_Done
@ GIR_Done
A successful emission.
Definition: InstructionSelector.h:411
llvm::Init
Definition: Record.h:282
llvm::InstructionSelector::ISelInfoTy::ComplexPredicates
const ComplexMatcherMemFn * ComplexPredicates
Definition: InstructionSelector.h:512
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::GIM_CheckRegBankForClass
@ GIM_CheckRegBankForClass
Check the register bank for the specified operand.
Definition: InstructionSelector.h:217
llvm::InstructionSelector::ISelInfoTy::FeatureBitsets
const PredicateBitset * FeatureBitsets
Definition: InstructionSelector.h:511
llvm::GIM_SwitchOpcode
@ GIM_SwitchOpcode
Switch over the opcode on the specified instruction.
Definition: InstructionSelector.h:95
std
Definition: BitVector.h:851
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::InstructionSelector::PSI
ProfileSummaryInfo * PSI
Definition: InstructionSelector.h:447
llvm::PredicateBitsetImpl::PredicateBitsetImpl
PredicateBitsetImpl()=default
llvm::GIM_CheckConstantInt
@ GIM_CheckConstantInt
Check the operand is a specific integer.
Definition: InstructionSelector.h:230
Function.h
llvm::GIR_CustomOperandRenderer
@ GIR_CustomOperandRenderer
Render operands to the specified instruction using a custom function, reading from a specific operand...
Definition: InstructionSelector.h:369
llvm::GIR_AddTempRegister
@ GIR_AddTempRegister
Add a temporary register to the specified instruction.
Definition: InstructionSelector.h:334
llvm::GIM_CheckAtomicOrderingOrStrongerThan
@ GIM_CheckAtomicOrderingOrStrongerThan
Definition: InstructionSelector.h:153
llvm::PredicateBitsetImpl::PredicateBitsetImpl
PredicateBitsetImpl(const std::bitset< MaxPredicates > &B)
Definition: InstructionSelector.h:67
llvm::InstructionSelector::isObviouslySafeToFold
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
Definition: InstructionSelector.cpp:55
llvm::GIM_CheckMemorySizeGreaterThanLLT
@ GIM_CheckMemorySizeGreaterThanLLT
Definition: InstructionSelector.h:184
llvm::GIM_CheckOpcodeIsEither
@ GIM_CheckOpcodeIsEither
Check the opcode on the specified instruction, checking 2 acceptable alternatives.
Definition: InstructionSelector.h:126
SmallVector.h
llvm::GIU_MergeMemOperands_EndOfList
@ GIU_MergeMemOperands_EndOfList
Indicates the end of the variable-length MergeInsnID list in a GIR_MergeMemOperands opcode.
Definition: InstructionSelector.h:424
llvm::InstructionSelector::testImmPredicate_APInt
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
Definition: InstructionSelector.h:542
bfi
< i32 > ret i32 conv5 And the following x86 eax movsbl ecx cmpl ecx sete al movzbl eax ret It should be possible to eliminate the sign extensions LLVM misses a load store narrowing opportunity in this i32 bfi
Definition: README.txt:1495
llvm::InstructionSelector::ISelInfoTy
Definition: InstructionSelector.h:497
llvm::InstructionSelector::CurMBB
MachineBasicBlock * CurMBB
Definition: InstructionSelector.h:450
llvm::GIM_CheckMemoryAddressSpace
@ GIM_CheckMemoryAddressSpace
Check the address space of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:168
llvm::InstructionSelector::executeMatchTable
bool executeMatchTable(TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State, const ISelInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ISelInfo, const int64_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage &CoverageInfo) const
Execute a given matcher table and return true if the match was successful and false otherwise.
Definition: InstructionSelectorImpl.h:50
MachineFunction.h
llvm::GIM_RecordNamedOperand
@ GIM_RecordNamedOperand
Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some named operands that will be ...
Definition: InstructionSelector.h:278
llvm::GIR_MergeMemOperands
@ GIR_MergeMemOperands
Merge all memory operands into instruction.
Definition: InstructionSelector.h:399
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::InstructionSelector::setupGeneratedPerFunctionState
virtual void setupGeneratedPerFunctionState(MachineFunction &MF)
Definition: InstructionSelector.h:452
llvm::GIM_CheckIsBuildVectorAllZeros
@ GIM_CheckIsBuildVectorAllZeros
Definition: InstructionSelector.h:192
llvm::InstructionSelector::select
virtual bool select(MachineInstr &I)=0
Select the (possibly generic) instruction I to only use target-specific opcodes.
llvm::GIM_CheckImmOperandPredicate
@ GIM_CheckImmOperandPredicate
Check an immediate predicate on the specified instruction.
Definition: InstructionSelector.h:148
llvm::GIM_CheckIsBuildVectorAllOnes
@ GIM_CheckIsBuildVectorAllOnes
Check if this is a vector that can be treated as a vector splat constant.
Definition: InstructionSelector.h:191
llvm::PredicateBitsetImpl::PredicateBitsetImpl
PredicateBitsetImpl(std::initializer_list< unsigned > Init)
Definition: InstructionSelector.h:70
llvm::LLT
Definition: LowLevelTypeImpl.h:39