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15 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
16 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
29 #include <initializer_list>
34 class BlockFrequencyInfo;
35 class CodeGenCoverage;
36 class MachineBasicBlock;
37 class ProfileSummaryInfo;
42 class MachineInstrBuilder;
43 class MachineFunction;
45 class MachineRegisterInfo;
46 class RegisterBankInfo;
47 class TargetInstrInfo;
48 class TargetRegisterInfo;
61 template <std::
size_t MaxPredicates>
68 :
std::bitset<MaxPredicates>(
B) {}
486 return F.hasOptSize() ||
F.hasMinSize() ||
491 template <
class PredicateBitset,
class ComplexMatcherMemFn,
492 class CustomRendererFn>
503 for (
size_t I = 0;
I < NumTypeObjects; ++
I)
519 template <
class TgtInstructionSelector,
class PredicateBitset,
520 class ComplexMatcherMemFn,
class CustomRendererFn>
536 "Subclasses must override this with a tablegen-erated function");
540 "Subclasses must override this with a tablegen-erated function");
544 "Subclasses must override this with a tablegen-erated function");
548 const std::array<const MachineOperand *, 3> &
Operands)
const {
550 "Subclasses must override this with a tablegen-erated function");
570 #endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 atomic and others It is also currently not done for read modify write instructions It is also current not done if the OF or CF flags are needed The shift operators have the complication that when the shift count is EFLAGS is not set
std::vector< ComplexRendererFns::value_type > Renderers
@ GIR_ComplexRenderer
Render complex operands to the specified instruction.
This is an optimization pass for GlobalISel generic memory operations.
@ GIR_MutateOpcode
Mutate an instruction.
@ GIR_EraseFromParent
Erase from parent.
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &, const std::array< const MachineOperand *, 3 > &Operands) const
@ GIM_CheckIsImm
Check the specified operand is an Imm.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
@ GIM_CheckComplexPattern
Check the operand matches a complex predicate.
@ GIR_Coverage
Increment the rule coverage counter.
virtual const int64_t * getMatchTable() const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
@ GIM_CheckAtomicOrderingWeakerThan
@ GIR_AddImplicitUse
Add an implicit register use to the specified instruction.
@ GIR_AddImplicitDef
Add an implicit register def to the specified instruction.
@ GIR_Done
A successful emission.
@ GIR_CopyConstantAsSImm
Render a G_CONSTANT operator as a sign-extended immediate.
@ GIM_CheckIntrinsicID
Check the operand is a specific intrinsic ID.
@ GIR_CustomRenderer
Render operands to the specified instruction using a custom function.
@ GIR_ConstrainSelectedInstOperands
Constrain an instructions operands according to the instruction description.
@ GIM_CheckNumOperands
Check the instruction has the right number of operands.
virtual void setupMF(MachineFunction &mf, GISelKnownBits *KB, CodeGenCoverage &covinfo, ProfileSummaryInfo *psi, BlockFrequencyInfo *bfi)
Setup per-MF selector state.
@ GIR_AddTempRegister
Add a temporary register to the specified instruction.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
virtual bool testImmPredicate_I64(unsigned, int64_t) const
@ GIM_CheckMemorySizeEqualTo
Check the size of the memory access for the given machine memory operand.
@ GIM_SwitchType
Switch over the LLT on the specified instruction operand.
unsigned const TargetRegisterInfo * TRI
ISelInfoTy(const LLT *TypeObjects, size_t NumTypeObjects, const PredicateBitset *FeatureBitsets, const ComplexMatcherMemFn *ComplexPredicates, const CustomRendererFn *CustomRenderers)
DenseMap< unsigned, unsigned > TempRegisters
@ GIM_CheckIsSameOperand
Check the specified operands are identical.
@ GIM_CheckOpcodeIsEither
Check the opcode on the specified instruction, checking 2 acceptable alternatives.
@ GIR_AddRegister
Add an register to the specified instruction.
@ GIM_CheckAPIntImmPredicate
Check an immediate predicate on the specified instruction via an APInt.
@ GIR_CopySubReg
Copy an operand to the specified instruction.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
const CustomRendererFn * CustomRenderers
TargetInstrInfo - Interface to description of machine instruction set.
virtual ~InstructionSelector()=default
@ GIM_SwitchOpcode
Switch over the opcode on the specified instruction.
@ GIM_RecordNamedOperand
Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some named operands that will be ...
@ GIM_CheckMemorySizeGreaterThanLLT
CodeGenCoverage * CoverageInfo
@ GIM_CheckPointerToAny
Check the type of a pointer to any address space.
const HexagonInstrInfo * TII
@ GIR_MakeTempReg
Create a new temporary register that's not constrained.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineOperand class - Representation of each machine instruction operand.
@ GIM_CheckOpcode
Check the opcode on the specified instruction.
std::array< const MachineOperand *, 3 > RecordedOperands
Named operands that predicate with 'let PredicateCodeUsesOperands = 1' referenced in its argument lis...
@ GIM_CheckCxxInsnPredicate
Check a generic C++ instruction predicate.
@ GIM_CheckI64ImmPredicate
Check an immediate predicate on the specified instruction.
@ GIR_ConstrainOperandRC
Constrain an instruction operand to a register class.
Analysis providing profile information.
mir Rename Register Operands
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
Holds all the information related to register banks.
SmallDenseMap< LLT, unsigned, 64 > TypeIDMap
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
@ GIM_CheckRegBankForClass
Check the register bank for the specified operand.
bool shouldOptForSize(const MachineFunction *MF) const
@ GIM_CheckIsBuildVectorAllOnes
Check if this is a vector that can be treated as a vector splat constant.
Container class for CodeGen predicate results.
@ GIR_CopyOrAddZeroReg
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
print Print MemDeps of function
Optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
@ GIM_CheckMemorySizeLessThanLLT
MatcherState(unsigned MaxRenderers)
Class for arbitrary precision integers.
@ GIM_CheckMemoryAddressSpace
Check the address space of the memory access for the given machine memory operand.
@ GIR_CopyFConstantAsFPImm
Render a G_FCONSTANT operator as a sign-extended immediate.
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
@ GIM_CheckMemoryAlignment
Check the minimum alignment of the memory access for the given machine memory operand.
@ GIR_AddImm
Add an immediate to the specified instruction.
@ GIM_CheckIsSafeToFold
Check if the specified operand is safe to fold into the current instruction.
@ GIU_MergeMemOperands_EndOfList
Indicates the end of the variable-length MergeInsnID list in a GIR_MergeMemOperands opcode.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isBaseWithConstantOffset(const MachineOperand &Root, const MachineRegisterInfo &MRI) const
Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the right-hand side.
@ GIR_AddTempSubRegister
Add a temporary register to the specified instruction.
@ GIM_RecordInsn
Record the specified instruction.
const ComplexMatcherMemFn * ComplexPredicates
unsigned const MachineRegisterInfo * MRI
@ GIR_Copy
Copy an operand to the specified instruction.
const PredicateBitset * FeatureBitsets
Function & getFunction()
Return the LLVM function that this machine code represents.
PredicateBitsetImpl()=default
@ GIU_NumOpcodes
Keeping track of the number of the GI opcodes. Must be the last entry.
@ GIR_BuildMI
Build a new instruction.
@ GIM_CheckConstantInt
Check the operand is a specific integer.
@ GIM_CheckAPFloatImmPredicate
Check a floating point immediate predicate on the specified instruction.
PredicateBitsetImpl(const std::bitset< MaxPredicates > &B)
@ GIM_CheckAtomicOrderingOrStrongerThan
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
@ GIM_CheckAtomicOrdering
Check a memory operation has the specified atomic ordering.
@ GIR_MergeMemOperands
Merge all memory operands into instruction.
@ GIR_CustomOperandRenderer
Render operands to the specified instruction using a custom function, reading from a specific operand...
@ GIM_CheckMemorySizeEqualToLLT
Check the size of the memory access for the given machine memory operand against the size of an opera...
@ GIM_CheckFeatures
Check the feature bits.
@ GIM_CheckIsMBB
Check the specified operand is an MBB.
@ GIM_Reject
Fail the current try-block, or completely fail to match if there is no current try-block.
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
< i32 > ret i32 conv5 And the following x86 eax movsbl ecx cmpl ecx sete al movzbl eax ret It should be possible to eliminate the sign extensions LLVM misses a load store narrowing opportunity in this i32 bfi
@ GIM_CheckCmpPredicate
Check the operand is a specific predicate.
MachineBasicBlock * CurMBB
@ GIM_CheckLiteralInt
Check the operand is a specific literal integer (i.e.
@ GIM_CheckIsBuildVectorAllZeros
@ GIR_ComplexSubOperandRenderer
Render sub-operands of complex operands to the specified instruction.
bool executeMatchTable(TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State, const ISelInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ISelInfo, const int64_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage &CoverageInfo) const
Execute a given matcher table and return true if the match was successful and false otherwise.
@ GIM_CheckType
Check the type for the specified operand.
@ GIM_CheckImmOperandPredicate
Check an immediate predicate on the specified instruction.
LLVM Value Representation.
@ GIM_Try
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
virtual void setupGeneratedPerFunctionState(MachineFunction &MF)
virtual bool select(MachineInstr &I)=0
Select the (possibly generic) instruction I to only use target-specific opcodes.
PredicateBitsetImpl(std::initializer_list< unsigned > Init)