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InstructionSelector.h
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1 //===- llvm/CodeGen/GlobalISel/InstructionSelector.h ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API for the instruction selector.
10 /// This class is responsible for selecting machine instructions.
11 /// It's implemented by the target. It's used by the InstructionSelect pass.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
16 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
17 
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/Optional.h"
20 #include "llvm/ADT/SmallVector.h"
28 #include <bitset>
29 #include <cstddef>
30 #include <cstdint>
31 #include <functional>
32 #include <initializer_list>
33 #include <vector>
34 
35 namespace llvm {
36 
37 class APInt;
38 class APFloat;
39 class GISelKnownBits;
40 class MachineInstr;
41 class MachineInstrBuilder;
42 class MachineFunction;
43 class MachineOperand;
44 class MachineRegisterInfo;
45 class RegisterBankInfo;
46 class TargetInstrInfo;
47 class TargetRegisterInfo;
48 
49 /// Container class for CodeGen predicate results.
50 /// This is convenient because std::bitset does not have a constructor
51 /// with an initializer list of set bits.
52 ///
53 /// Each InstructionSelector subclass should define a PredicateBitset class
54 /// with:
55 /// const unsigned MAX_SUBTARGET_PREDICATES = 192;
56 /// using PredicateBitset = PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
57 /// and updating the constant to suit the target. Tablegen provides a suitable
58 /// definition for the predicates in use in <Target>GenGlobalISel.inc when
59 /// GET_GLOBALISEL_PREDICATE_BITSET is defined.
60 template <std::size_t MaxPredicates>
61 class PredicateBitsetImpl : public std::bitset<MaxPredicates> {
62 public:
63  // Cannot inherit constructors because it's not supported by VC++..
64  PredicateBitsetImpl() = default;
65 
66  PredicateBitsetImpl(const std::bitset<MaxPredicates> &B)
67  : std::bitset<MaxPredicates>(B) {}
68 
69  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
70  for (auto I : Init)
72  }
73 };
74 
75 enum {
76  /// Begin a try-block to attempt a match and jump to OnFail if it is
77  /// unsuccessful.
78  /// - OnFail - The MatchTable entry at which to resume if the match fails.
79  ///
80  /// FIXME: This ought to take an argument indicating the number of try-blocks
81  /// to exit on failure. It's usually one but the last match attempt of
82  /// a block will need more. The (implemented) alternative is to tack a
83  /// GIM_Reject on the end of each try-block which is simpler but
84  /// requires an extra opcode and iteration in the interpreter on each
85  /// failed match.
87 
88  /// Switch over the opcode on the specified instruction
89  /// - InsnID - Instruction ID
90  /// - LowerBound - numerically minimum opcode supported
91  /// - UpperBound - numerically maximum + 1 opcode supported
92  /// - Default - failure jump target
93  /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
95 
96  /// Switch over the LLT on the specified instruction operand
97  /// - InsnID - Instruction ID
98  /// - OpIdx - Operand index
99  /// - LowerBound - numerically minimum Type ID supported
100  /// - UpperBound - numerically maximum + 1 Type ID supported
101  /// - Default - failure jump target
102  /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
104 
105  /// Record the specified instruction
106  /// - NewInsnID - Instruction ID to define
107  /// - InsnID - Instruction ID
108  /// - OpIdx - Operand index
110 
111  /// Check the feature bits
112  /// - Expected features
114 
115  /// Check the opcode on the specified instruction
116  /// - InsnID - Instruction ID
117  /// - Expected opcode
119 
120  /// Check the opcode on the specified instruction, checking 2 acceptable
121  /// alternatives.
122  /// - InsnID - Instruction ID
123  /// - Expected opcode
124  /// - Alternative expected opcode
126 
127  /// Check the instruction has the right number of operands
128  /// - InsnID - Instruction ID
129  /// - Expected number of operands
131  /// Check an immediate predicate on the specified instruction
132  /// - InsnID - Instruction ID
133  /// - The predicate to test
135  /// Check an immediate predicate on the specified instruction via an APInt.
136  /// - InsnID - Instruction ID
137  /// - The predicate to test
139  /// Check a floating point immediate predicate on the specified instruction.
140  /// - InsnID - Instruction ID
141  /// - The predicate to test
143  /// Check an immediate predicate on the specified instruction
144  /// - InsnID - Instruction ID
145  /// - OpIdx - Operand index
146  /// - The predicate to test
148  /// Check a memory operation has the specified atomic ordering.
149  /// - InsnID - Instruction ID
150  /// - Ordering - The AtomicOrdering value
154  /// Check the size of the memory access for the given machine memory operand.
155  /// - InsnID - Instruction ID
156  /// - MMOIdx - MMO index
157  /// - Size - The size in bytes of the memory access
159 
160  /// Check the address space of the memory access for the given machine memory
161  /// operand.
162  /// - InsnID - Instruction ID
163  /// - MMOIdx - MMO index
164  /// - NumAddrSpace - Number of valid address spaces
165  /// - AddrSpaceN - An allowed space of the memory access
166  /// - AddrSpaceN+1 ...
168 
169  /// Check the minimum alignment of the memory access for the given machine
170  /// memory operand.
171  /// - InsnID - Instruction ID
172  /// - MMOIdx - MMO index
173  /// - MinAlign - Minimum acceptable alignment
175 
176  /// Check the size of the memory access for the given machine memory operand
177  /// against the size of an operand.
178  /// - InsnID - Instruction ID
179  /// - MMOIdx - MMO index
180  /// - OpIdx - The operand index to compare the MMO against
184 
185  /// Check if this is a vector that can be treated as a vector splat
186  /// constant. This is valid for both G_BUILD_VECTOR as well as
187  /// G_BUILD_VECTOR_TRUNC. For AllOnes refers to individual bits, so a -1
188  /// element.
189  /// - InsnID - Instruction ID
192 
193  /// Check a generic C++ instruction predicate
194  /// - InsnID - Instruction ID
195  /// - PredicateID - The ID of the predicate function to call
197 
198  /// Check the type for the specified operand
199  /// - InsnID - Instruction ID
200  /// - OpIdx - Operand index
201  /// - Expected type
203  /// Check the type of a pointer to any address space.
204  /// - InsnID - Instruction ID
205  /// - OpIdx - Operand index
206  /// - SizeInBits - The size of the pointer value in bits.
208  /// Check the register bank for the specified operand
209  /// - InsnID - Instruction ID
210  /// - OpIdx - Operand index
211  /// - Expected register bank (specified as a register class)
213 
214  /// Check the operand matches a complex predicate
215  /// - InsnID - Instruction ID
216  /// - OpIdx - Operand index
217  /// - RendererID - The renderer to hold the result
218  /// - Complex predicate ID
220 
221  /// Check the operand is a specific integer
222  /// - InsnID - Instruction ID
223  /// - OpIdx - Operand index
224  /// - Expected integer
226  /// Check the operand is a specific literal integer (i.e. MO.isImm() or
227  /// MO.isCImm() is true).
228  /// - InsnID - Instruction ID
229  /// - OpIdx - Operand index
230  /// - Expected integer
232  /// Check the operand is a specific intrinsic ID
233  /// - InsnID - Instruction ID
234  /// - OpIdx - Operand index
235  /// - Expected Intrinsic ID
237 
238  /// Check the operand is a specific predicate
239  /// - InsnID - Instruction ID
240  /// - OpIdx - Operand index
241  /// - Expected predicate
243 
244  /// Check the specified operand is an MBB
245  /// - InsnID - Instruction ID
246  /// - OpIdx - Operand index
248 
249  /// Check the specified operand is an Imm
250  /// - InsnID - Instruction ID
251  /// - OpIdx - Operand index
253 
254  /// Check if the specified operand is safe to fold into the current
255  /// instruction.
256  /// - InsnID - Instruction ID
258 
259  /// Check the specified operands are identical.
260  /// - InsnID - Instruction ID
261  /// - OpIdx - Operand index
262  /// - OtherInsnID - Other instruction ID
263  /// - OtherOpIdx - Other operand index
265 
266  /// Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some
267  /// named operands that will be recorded in RecordedOperands. Names of these
268  /// operands are referenced in predicate argument list. Emitter determines
269  /// StoreIdx(corresponds to the order in which names appear in argument list).
270  /// - InsnID - Instruction ID
271  /// - OpIdx - Operand index
272  /// - StoreIdx - Store location in RecordedOperands.
274 
275  /// Fail the current try-block, or completely fail to match if there is no
276  /// current try-block.
278 
279  //=== Renderers ===
280 
281  /// Mutate an instruction
282  /// - NewInsnID - Instruction ID to define
283  /// - OldInsnID - Instruction ID to mutate
284  /// - NewOpcode - The new opcode to use
286 
287  /// Build a new instruction
288  /// - InsnID - Instruction ID to define
289  /// - Opcode - The new opcode to use
291 
292  /// Copy an operand to the specified instruction
293  /// - NewInsnID - Instruction ID to modify
294  /// - OldInsnID - Instruction ID to copy from
295  /// - OpIdx - The operand to copy
297 
298  /// Copy an operand to the specified instruction or add a zero register if the
299  /// operand is a zero immediate.
300  /// - NewInsnID - Instruction ID to modify
301  /// - OldInsnID - Instruction ID to copy from
302  /// - OpIdx - The operand to copy
303  /// - ZeroReg - The zero register to use
305  /// Copy an operand to the specified instruction
306  /// - NewInsnID - Instruction ID to modify
307  /// - OldInsnID - Instruction ID to copy from
308  /// - OpIdx - The operand to copy
309  /// - SubRegIdx - The subregister to copy
311 
312  /// Add an implicit register def to the specified instruction
313  /// - InsnID - Instruction ID to modify
314  /// - RegNum - The register to add
316  /// Add an implicit register use to the specified instruction
317  /// - InsnID - Instruction ID to modify
318  /// - RegNum - The register to add
320  /// Add an register to the specified instruction
321  /// - InsnID - Instruction ID to modify
322  /// - RegNum - The register to add
324 
325  /// Add a temporary register to the specified instruction
326  /// - InsnID - Instruction ID to modify
327  /// - TempRegID - The temporary register ID to add
328  /// - TempRegFlags - The register flags to set
330 
331  /// Add a temporary register to the specified instruction
332  /// - InsnID - Instruction ID to modify
333  /// - TempRegID - The temporary register ID to add
334  /// - TempRegFlags - The register flags to set
335  /// - SubRegIndex - The subregister index to set
337 
338  /// Add an immediate to the specified instruction
339  /// - InsnID - Instruction ID to modify
340  /// - Imm - The immediate to add
342  /// Render complex operands to the specified instruction
343  /// - InsnID - Instruction ID to modify
344  /// - RendererID - The renderer to call
346 
347  /// Render sub-operands of complex operands to the specified instruction
348  /// - InsnID - Instruction ID to modify
349  /// - RendererID - The renderer to call
350  /// - RenderOpID - The suboperand to render.
352  /// Render operands to the specified instruction using a custom function
353  /// - InsnID - Instruction ID to modify
354  /// - OldInsnID - Instruction ID to get the matched operand from
355  /// - RendererFnID - Custom renderer function to call
357 
358  /// Render operands to the specified instruction using a custom function,
359  /// reading from a specific operand.
360  /// - InsnID - Instruction ID to modify
361  /// - OldInsnID - Instruction ID to get the matched operand from
362  /// - OpIdx - Operand index in OldInsnID the render function should read from..
363  /// - RendererFnID - Custom renderer function to call
365 
366  /// Render a G_CONSTANT operator as a sign-extended immediate.
367  /// - NewInsnID - Instruction ID to modify
368  /// - OldInsnID - Instruction ID to copy from
369  /// The operand index is implicitly 1.
371 
372  /// Render a G_FCONSTANT operator as a sign-extended immediate.
373  /// - NewInsnID - Instruction ID to modify
374  /// - OldInsnID - Instruction ID to copy from
375  /// The operand index is implicitly 1.
377 
378  /// Constrain an instruction operand to a register class.
379  /// - InsnID - Instruction ID to modify
380  /// - OpIdx - Operand index
381  /// - RCEnum - Register class enumeration value
383 
384  /// Constrain an instructions operands according to the instruction
385  /// description.
386  /// - InsnID - Instruction ID to modify
388 
389  /// Merge all memory operands into instruction.
390  /// - InsnID - Instruction ID to modify
391  /// - MergeInsnID... - One or more Instruction ID to merge into the result.
392  /// - GIU_MergeMemOperands_EndOfList - Terminates the list of instructions to
393  /// merge.
395 
396  /// Erase from parent.
397  /// - InsnID - Instruction ID to erase
399 
400  /// Create a new temporary register that's not constrained.
401  /// - TempRegID - The temporary register ID to initialize.
402  /// - Expected type
404 
405  /// A successful emission
407 
408  /// Increment the rule coverage counter.
409  /// - RuleID - The ID of the rule that was covered.
411 
412  /// Keeping track of the number of the GI opcodes. Must be the last entry.
414 };
415 
416 enum {
417  /// Indicates the end of the variable-length MergeInsnID list in a
418  /// GIR_MergeMemOperands opcode.
420 };
421 
422 /// Provides the logic to select generic machine instructions.
424 public:
425  virtual ~InstructionSelector() = default;
426 
427  /// Select the (possibly generic) instruction \p I to only use target-specific
428  /// opcodes. It is OK to insert multiple instructions, but they cannot be
429  /// generic pre-isel instructions.
430  ///
431  /// \returns whether selection succeeded.
432  /// \pre I.getParent() && I.getParent()->getParent()
433  /// \post
434  /// if returns true:
435  /// for I in all mutated/inserted instructions:
436  /// !isPreISelGenericOpcode(I.getOpcode())
437  virtual bool select(MachineInstr &I) = 0;
438 
441  MachineFunction *MF = nullptr;
444  // For some predicates, we need to track the current MBB.
446 
448  llvm_unreachable("TableGen should have emitted implementation");
449  }
450 
451  /// Setup per-MF selector state.
452  virtual void setupMF(MachineFunction &mf, GISelKnownBits *KB,
453  CodeGenCoverage &covinfo, ProfileSummaryInfo *psi,
455  CoverageInfo = &covinfo;
456  KnownBits = KB;
457  MF = &mf;
458  PSI = psi;
459  BFI = bfi;
460  CurMBB = nullptr;
462  }
463 
464 protected:
465  using ComplexRendererFns =
469 
470  struct MatcherState {
471  std::vector<ComplexRendererFns::value_type> Renderers;
474  /// Named operands that predicate with 'let PredicateCodeUsesOperands = 1'
475  /// referenced in its argument list. Operands are inserted at index set by
476  /// emitter, it corresponds to the order in which names appear in argument
477  /// list. Currently such predicates don't have more then 3 arguments.
478  std::array<const MachineOperand *, 3> RecordedOperands;
479 
480  MatcherState(unsigned MaxRenderers);
481  };
482 
483  bool shouldOptForSize(const MachineFunction *MF) const {
484  const auto &F = MF->getFunction();
485  return F.hasOptSize() || F.hasMinSize() ||
487  }
488 
489 public:
490  template <class PredicateBitset, class ComplexMatcherMemFn,
491  class CustomRendererFn>
492  struct ISelInfoTy {
493  ISelInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
494  const PredicateBitset *FeatureBitsets,
495  const ComplexMatcherMemFn *ComplexPredicates,
496  const CustomRendererFn *CustomRenderers)
501 
502  for (size_t I = 0; I < NumTypeObjects; ++I)
503  TypeIDMap[TypeObjects[I]] = I;
504  }
505  const LLT *TypeObjects;
506  const PredicateBitset *FeatureBitsets;
507  const ComplexMatcherMemFn *ComplexPredicates;
508  const CustomRendererFn *CustomRenderers;
509 
511  };
512 
513 protected:
515 
516  /// Execute a given matcher table and return true if the match was successful
517  /// and false otherwise.
518  template <class TgtInstructionSelector, class PredicateBitset,
519  class ComplexMatcherMemFn, class CustomRendererFn>
520  bool executeMatchTable(
521  TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
523  &ISelInfo,
524  const int64_t *MatchTable, const TargetInstrInfo &TII,
526  const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
528 
529  virtual const int64_t *getMatchTable() const {
530  llvm_unreachable("Should have been overridden by tablegen if used");
531  }
532 
533  virtual bool testImmPredicate_I64(unsigned, int64_t) const {
535  "Subclasses must override this with a tablegen-erated function");
536  }
537  virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
539  "Subclasses must override this with a tablegen-erated function");
540  }
541  virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
543  "Subclasses must override this with a tablegen-erated function");
544  }
545  virtual bool testMIPredicate_MI(
546  unsigned, const MachineInstr &,
547  const std::array<const MachineOperand *, 3> &Operands) const {
549  "Subclasses must override this with a tablegen-erated function");
550  }
551 
552  bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
553  const MachineRegisterInfo &MRI) const;
554 
555  /// Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the
556  /// right-hand side. GlobalISel's separation of pointer and integer types
557  /// means that we don't need to worry about G_OR with equivalent semantics.
558  bool isBaseWithConstantOffset(const MachineOperand &Root,
559  const MachineRegisterInfo &MRI) const;
560 
561  /// Return true if MI can obviously be folded into IntoMI.
562  /// MI and IntoMI do not need to be in the same basic blocks, but MI must
563  /// preceed IntoMI.
564  bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const;
565 };
566 
567 } // end namespace llvm
568 
569 #endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:489
llvm::GIM_CheckIsBuildVectorAllOnes
@ GIM_CheckIsBuildVectorAllOnes
Check if this is a vector that can be treated as a vector splat constant.
Definition: InstructionSelector.h:190
set
We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 atomic and others It is also currently not done for read modify write instructions It is also current not done if the OF or CF flags are needed The shift operators have the complication that when the shift count is EFLAGS is not set
Definition: README.txt:1277
llvm::InstructionSelector::MatcherState::Renderers
std::vector< ComplexRendererFns::value_type > Renderers
Definition: InstructionSelector.h:471
llvm::GIM_CheckMemoryAddressSpace
@ GIM_CheckMemoryAddressSpace
Check the address space of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:167
llvm::GIM_CheckPointerToAny
@ GIM_CheckPointerToAny
Check the type of a pointer to any address space.
Definition: InstructionSelector.h:207
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
llvm::GIM_CheckCmpPredicate
@ GIM_CheckCmpPredicate
Check the operand is a specific predicate.
Definition: InstructionSelector.h:242
llvm::GIM_CheckImmOperandPredicate
@ GIM_CheckImmOperandPredicate
Check an immediate predicate on the specified instruction.
Definition: InstructionSelector.h:147
Optional.h
llvm::InstructionSelector::testMIPredicate_MI
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &, const std::array< const MachineOperand *, 3 > &Operands) const
Definition: InstructionSelector.h:545
llvm::GIM_CheckType
@ GIM_CheckType
Check the type for the specified operand.
Definition: InstructionSelector.h:202
llvm::GIM_RecordNamedOperand
@ GIM_RecordNamedOperand
Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some named operands that will be ...
Definition: InstructionSelector.h:273
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::InstructionSelector::getMatchTable
virtual const int64_t * getMatchTable() const
Definition: InstructionSelector.h:529
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::GIM_CheckNumOperands
@ GIM_CheckNumOperands
Check the instruction has the right number of operands.
Definition: InstructionSelector.h:130
llvm::GIM_CheckIsBuildVectorAllZeros
@ GIM_CheckIsBuildVectorAllZeros
Definition: InstructionSelector.h:191
llvm::GIM_CheckIsSameOperand
@ GIM_CheckIsSameOperand
Check the specified operands are identical.
Definition: InstructionSelector.h:264
llvm::SmallDenseMap
Definition: DenseMap.h:880
llvm::InstructionSelector::MatcherState
Definition: InstructionSelector.h:470
llvm::InstructionSelector::setupMF
virtual void setupMF(MachineFunction &mf, GISelKnownBits *KB, CodeGenCoverage &covinfo, ProfileSummaryInfo *psi, BlockFrequencyInfo *bfi)
Setup per-MF selector state.
Definition: InstructionSelector.h:452
MachineBasicBlock.h
llvm::GIM_CheckCxxInsnPredicate
@ GIM_CheckCxxInsnPredicate
Check a generic C++ instruction predicate.
Definition: InstructionSelector.h:196
llvm::GIM_CheckIsImm
@ GIM_CheckIsImm
Check the specified operand is an Imm.
Definition: InstructionSelector.h:252
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::GIR_AddTempRegister
@ GIR_AddTempRegister
Add a temporary register to the specified instruction.
Definition: InstructionSelector.h:329
llvm::shouldOptForSize
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:994
DenseMap.h
llvm::GIR_AddRegister
@ GIR_AddRegister
Add an register to the specified instruction.
Definition: InstructionSelector.h:323
llvm::GIR_ConstrainSelectedInstOperands
@ GIR_ConstrainSelectedInstOperands
Constrain an instructions operands according to the instruction description.
Definition: InstructionSelector.h:387
llvm::InstructionSelector::MatcherState::MIs
RecordedMIVector MIs
Definition: InstructionSelector.h:472
llvm::Optional
Definition: APInt.h:33
llvm::InstructionSelector::testImmPredicate_I64
virtual bool testImmPredicate_I64(unsigned, int64_t) const
Definition: InstructionSelector.h:533
llvm::GIM_CheckComplexPattern
@ GIM_CheckComplexPattern
Check the operand matches a complex predicate.
Definition: InstructionSelector.h:219
llvm::GIM_Reject
@ GIM_Reject
Fail the current try-block, or completely fail to match if there is no current try-block.
Definition: InstructionSelector.h:277
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::GIR_AddImplicitUse
@ GIR_AddImplicitUse
Add an implicit register use to the specified instruction.
Definition: InstructionSelector.h:319
llvm::InstructionSelector::ISelInfoTy::ISelInfoTy
ISelInfoTy(const LLT *TypeObjects, size_t NumTypeObjects, const PredicateBitset *FeatureBitsets, const ComplexMatcherMemFn *ComplexPredicates, const CustomRendererFn *CustomRenderers)
Definition: InstructionSelector.h:493
llvm::InstructionSelector::MatcherState::TempRegisters
DenseMap< unsigned, unsigned > TempRegisters
Definition: InstructionSelector.h:473
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::InstructionSelector::ISelInfoTy::CustomRenderers
const CustomRendererFn * CustomRenderers
Definition: InstructionSelector.h:508
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::InstructionSelector::~InstructionSelector
virtual ~InstructionSelector()=default
llvm::GIR_Copy
@ GIR_Copy
Copy an operand to the specified instruction.
Definition: InstructionSelector.h:296
llvm::InstructionSelector::CoverageInfo
CodeGenCoverage * CoverageInfo
Definition: InstructionSelector.h:439
Utils.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::GIM_CheckI64ImmPredicate
@ GIM_CheckI64ImmPredicate
Check an immediate predicate on the specified instruction.
Definition: InstructionSelector.h:134
llvm::GIM_CheckAtomicOrderingOrStrongerThan
@ GIM_CheckAtomicOrderingOrStrongerThan
Definition: InstructionSelector.h:152
llvm::GIR_ConstrainOperandRC
@ GIR_ConstrainOperandRC
Constrain an instruction operand to a register class.
Definition: InstructionSelector.h:382
llvm::InstructionSelector::MatcherState::RecordedOperands
std::array< const MachineOperand *, 3 > RecordedOperands
Named operands that predicate with 'let PredicateCodeUsesOperands = 1' referenced in its argument lis...
Definition: InstructionSelector.h:478
llvm::GIM_CheckAPIntImmPredicate
@ GIM_CheckAPIntImmPredicate
Check an immediate predicate on the specified instruction via an APInt.
Definition: InstructionSelector.h:138
llvm::InstructionSelector::InstructionSelector
InstructionSelector()
llvm::GIM_CheckLiteralInt
@ GIM_CheckLiteralInt
Check the operand is a specific literal integer (i.e.
Definition: InstructionSelector.h:231
llvm::GIR_CustomOperandRenderer
@ GIR_CustomOperandRenderer
Render operands to the specified instruction using a custom function, reading from a specific operand...
Definition: InstructionSelector.h:364
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
LowLevelTypeImpl.h
llvm::GIR_BuildMI
@ GIR_BuildMI
Build a new instruction.
Definition: InstructionSelector.h:290
llvm::GIR_MutateOpcode
@ GIR_MutateOpcode
Mutate an instruction.
Definition: InstructionSelector.h:285
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::GIM_CheckAPFloatImmPredicate
@ GIM_CheckAPFloatImmPredicate
Check a floating point immediate predicate on the specified instruction.
Definition: InstructionSelector.h:142
llvm::InstructionSelector::MF
MachineFunction * MF
Definition: InstructionSelector.h:441
llvm::GIR_MergeMemOperands
@ GIR_MergeMemOperands
Merge all memory operands into instruction.
Definition: InstructionSelector.h:394
llvm::InstructionSelector::isOperandImmEqual
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
Definition: InstructionSelector.cpp:36
llvm::APFloat
Definition: APFloat.h:701
llvm::GIM_CheckMemorySizeLessThanLLT
@ GIM_CheckMemorySizeLessThanLLT
Definition: InstructionSelector.h:182
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::InstructionSelector::ISelInfoTy::TypeIDMap
SmallDenseMap< LLT, unsigned, 64 > TypeIDMap
Definition: InstructionSelector.h:510
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:423
llvm::GIR_CopyOrAddZeroReg
@ GIR_CopyOrAddZeroReg
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
Definition: InstructionSelector.h:304
llvm::GIR_Coverage
@ GIR_Coverage
Increment the rule coverage counter.
Definition: InstructionSelector.h:410
llvm::CodeGenCoverage
Definition: CodeGenCoverage.h:20
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
ProfileSummaryInfo.h
llvm::GIR_Done
@ GIR_Done
A successful emission.
Definition: InstructionSelector.h:406
llvm::GIR_AddImplicitDef
@ GIR_AddImplicitDef
Add an implicit register def to the specified instruction.
Definition: InstructionSelector.h:315
llvm::GIR_CopyFConstantAsFPImm
@ GIR_CopyFConstantAsFPImm
Render a G_FCONSTANT operator as a sign-extended immediate.
Definition: InstructionSelector.h:376
llvm::DenseMap< unsigned, unsigned >
llvm::GIM_CheckIsSafeToFold
@ GIM_CheckIsSafeToFold
Check if the specified operand is safe to fold into the current instruction.
Definition: InstructionSelector.h:257
llvm::InstructionSelector::shouldOptForSize
bool shouldOptForSize(const MachineFunction *MF) const
Definition: InstructionSelector.h:483
I
#define I(x, y, z)
Definition: MD5.cpp:59
CodeGenCoverage.h
llvm::GIM_CheckOpcode
@ GIM_CheckOpcode
Check the opcode on the specified instruction.
Definition: InstructionSelector.h:118
llvm::InstructionSelector::ISelInfoTy::TypeObjects
const LLT * TypeObjects
Definition: InstructionSelector.h:505
llvm::GIM_RecordInsn
@ GIM_RecordInsn
Record the specified instruction.
Definition: InstructionSelector.h:109
llvm::PredicateBitsetImpl
Container class for CodeGen predicate results.
Definition: InstructionSelector.h:61
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::InstructionSelector::ComplexRendererFns
Optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
Definition: InstructionSelector.h:466
llvm::InstructionSelector::MatcherState::MatcherState
MatcherState(unsigned MaxRenderers)
Definition: InstructionSelector.cpp:31
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::GIR_ComplexSubOperandRenderer
@ GIR_ComplexSubOperandRenderer
Render sub-operands of complex operands to the specified instruction.
Definition: InstructionSelector.h:351
llvm::GIR_AddTempSubRegister
@ GIR_AddTempSubRegister
Add a temporary register to the specified instruction.
Definition: InstructionSelector.h:336
llvm::GIU_NumOpcodes
@ GIU_NumOpcodes
Keeping track of the number of the GI opcodes. Must be the last entry.
Definition: InstructionSelector.h:413
llvm::InstructionSelector::testImmPredicate_APFloat
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
Definition: InstructionSelector.h:541
llvm::GIM_Try
@ GIM_Try
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
Definition: InstructionSelector.h:86
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::InstructionSelector::isBaseWithConstantOffset
bool isBaseWithConstantOffset(const MachineOperand &Root, const MachineRegisterInfo &MRI) const
Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the right-hand side.
Definition: InstructionSelector.cpp:45
llvm::GIM_CheckFeatures
@ GIM_CheckFeatures
Check the feature bits.
Definition: InstructionSelector.h:113
BlockFrequencyInfo.h
llvm::GIM_CheckAtomicOrderingWeakerThan
@ GIM_CheckAtomicOrderingWeakerThan
Definition: InstructionSelector.h:153
llvm::InstructionSelector::BFI
BlockFrequencyInfo * BFI
Definition: InstructionSelector.h:443
llvm::GIM_SwitchType
@ GIM_SwitchType
Switch over the LLT on the specified instruction operand.
Definition: InstructionSelector.h:103
llvm::GIR_MakeTempReg
@ GIR_MakeTempReg
Create a new temporary register that's not constrained.
Definition: InstructionSelector.h:403
llvm::Init
Definition: Record.h:271
llvm::InstructionSelector::ISelInfoTy::ComplexPredicates
const ComplexMatcherMemFn * ComplexPredicates
Definition: InstructionSelector.h:507
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::InstructionSelector::ISelInfoTy::FeatureBitsets
const PredicateBitset * FeatureBitsets
Definition: InstructionSelector.h:506
llvm::GIM_CheckAtomicOrdering
@ GIM_CheckAtomicOrdering
Check a memory operation has the specified atomic ordering.
Definition: InstructionSelector.h:151
llvm::GIM_CheckOpcodeIsEither
@ GIM_CheckOpcodeIsEither
Check the opcode on the specified instruction, checking 2 acceptable alternatives.
Definition: InstructionSelector.h:125
std
Definition: BitVector.h:838
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:524
llvm::InstructionSelector::PSI
ProfileSummaryInfo * PSI
Definition: InstructionSelector.h:442
llvm::PredicateBitsetImpl::PredicateBitsetImpl
PredicateBitsetImpl()=default
llvm::GIM_CheckRegBankForClass
@ GIM_CheckRegBankForClass
Check the register bank for the specified operand.
Definition: InstructionSelector.h:212
llvm::GIM_CheckIsMBB
@ GIM_CheckIsMBB
Check the specified operand is an MBB.
Definition: InstructionSelector.h:247
llvm::GIM_CheckIntrinsicID
@ GIM_CheckIntrinsicID
Check the operand is a specific intrinsic ID.
Definition: InstructionSelector.h:236
llvm::GIM_CheckMemorySizeGreaterThanLLT
@ GIM_CheckMemorySizeGreaterThanLLT
Definition: InstructionSelector.h:183
llvm::PredicateBitsetImpl::PredicateBitsetImpl
PredicateBitsetImpl(const std::bitset< MaxPredicates > &B)
Definition: InstructionSelector.h:66
llvm::InstructionSelector::isObviouslySafeToFold
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
Definition: InstructionSelector.cpp:62
llvm::GIM_CheckConstantInt
@ GIM_CheckConstantInt
Check the operand is a specific integer.
Definition: InstructionSelector.h:225
llvm::GIR_EraseFromParent
@ GIR_EraseFromParent
Erase from parent.
Definition: InstructionSelector.h:398
SmallVector.h
llvm::InstructionSelector::testImmPredicate_APInt
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
Definition: InstructionSelector.h:537
bfi
< i32 > ret i32 conv5 And the following x86 eax movsbl ecx cmpl ecx sete al movzbl eax ret It should be possible to eliminate the sign extensions LLVM misses a load store narrowing opportunity in this i32 bfi
Definition: README.txt:1495
llvm::GIM_CheckMemorySizeEqualToLLT
@ GIM_CheckMemorySizeEqualToLLT
Check the size of the memory access for the given machine memory operand against the size of an opera...
Definition: InstructionSelector.h:181
llvm::InstructionSelector::ISelInfoTy
Definition: InstructionSelector.h:492
llvm::InstructionSelector::CurMBB
MachineBasicBlock * CurMBB
Definition: InstructionSelector.h:445
llvm::GIR_CustomRenderer
@ GIR_CustomRenderer
Render operands to the specified instruction using a custom function.
Definition: InstructionSelector.h:356
llvm::GIU_MergeMemOperands_EndOfList
@ GIU_MergeMemOperands_EndOfList
Indicates the end of the variable-length MergeInsnID list in a GIR_MergeMemOperands opcode.
Definition: InstructionSelector.h:419
llvm::GIM_CheckMemoryAlignment
@ GIM_CheckMemoryAlignment
Check the minimum alignment of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:174
llvm::InstructionSelector::executeMatchTable
bool executeMatchTable(TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State, const ISelInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ISelInfo, const int64_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage &CoverageInfo) const
Execute a given matcher table and return true if the match was successful and false otherwise.
Definition: InstructionSelectorImpl.h:49
llvm::GIR_CopySubReg
@ GIR_CopySubReg
Copy an operand to the specified instruction.
Definition: InstructionSelector.h:310
llvm::GIR_ComplexRenderer
@ GIR_ComplexRenderer
Render complex operands to the specified instruction.
Definition: InstructionSelector.h:345
MachineFunction.h
llvm::GIR_AddImm
@ GIR_AddImm
Add an immediate to the specified instruction.
Definition: InstructionSelector.h:341
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::GIM_SwitchOpcode
@ GIM_SwitchOpcode
Switch over the opcode on the specified instruction.
Definition: InstructionSelector.h:94
llvm::InstructionSelector::setupGeneratedPerFunctionState
virtual void setupGeneratedPerFunctionState(MachineFunction &MF)
Definition: InstructionSelector.h:447
llvm::GIM_CheckMemorySizeEqualTo
@ GIM_CheckMemorySizeEqualTo
Check the size of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:158
llvm::InstructionSelector::select
virtual bool select(MachineInstr &I)=0
Select the (possibly generic) instruction I to only use target-specific opcodes.
llvm::GIR_CopyConstantAsSImm
@ GIR_CopyConstantAsSImm
Render a G_CONSTANT operator as a sign-extended immediate.
Definition: InstructionSelector.h:370
llvm::PredicateBitsetImpl::PredicateBitsetImpl
PredicateBitsetImpl(std::initializer_list< unsigned > Init)
Definition: InstructionSelector.h:69
llvm::LLT
Definition: LowLevelTypeImpl.h:40