LLVM 23.0.0git
GIMatchTableExecutor.h
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1//===- llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file declares the GIMatchTableExecutor API, the opcodes supported
10/// by the match table, and some associated data structures used by the
11/// executor's implementation (see `GIMatchTableExecutorImpl.h`).
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
16#define LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
17
18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/ADT/Bitset.h"
20#include "llvm/ADT/DenseMap.h"
21#include "llvm/ADT/DenseSet.h"
27#include "llvm/IR/Function.h"
30#include <bitset>
31#include <cstddef>
32#include <cstdint>
33#include <functional>
34#include <initializer_list>
35#include <optional>
36#include <vector>
37
38namespace llvm {
39
41class CodeGenCoverage;
44class APInt;
45class APFloat;
47class MachineInstr;
50class MachineFunction;
51class MachineOperand;
54class TargetInstrInfo;
56
57enum {
60};
61
62/// The MatchTable is encoded as an array of bytes.
63/// Thus, opcodes are expected to be <255.
64///
65/// Operands can be variable-sized, their size is always after their name
66/// in the docs, e.g. "Foo(4)" means that "Foo" takes 4 entries in the table,
67/// so 4 bytes. "Foo()"
68///
69/// As a general rule of thumb:
70/// - Instruction & Operand IDs are ULEB128
71/// - LLT IDs are 1 byte
72/// - Predicates and target opcodes, register and register class IDs are 2
73/// bytes.
74/// - Indexes into the table are 4 bytes.
75/// - Inline constants are 8 bytes
76///
77/// Design notes:
78/// - Inst/Op IDs have to be LEB128 because some targets generate
79/// extremely long patterns which need more than 255 temporaries.
80/// We could just use 2 bytes everytime, but then some targets like
81/// X86/AMDGPU that have no need for it will pay the price all the time.
82enum {
83 /// Begin a try-block to attempt a match and jump to OnFail if it is
84 /// unsuccessful.
85 /// - OnFail(4) - The MatchTable entry at which to resume if the match fails.
86 ///
87 /// FIXME: This ought to take an argument indicating the number of try-blocks
88 /// to exit on failure. It's usually one but the last match attempt of
89 /// a block will need more. The (implemented) alternative is to tack a
90 /// GIM_Reject on the end of each try-block which is simpler but
91 /// requires an extra opcode and iteration in the interpreter on each
92 /// failed match.
94
95 /// GIM_Try only if the feature bits match.
96 /// - OnFail(4) - The MatchTable entry at which to resume if the match fails.
97 /// - Feature(2) - Expected features
99
100 /// Switch over the opcode on the specified instruction
101 /// - InsnID(ULEB128) - Instruction ID
102 /// - LowerBound(2) - numerically minimum opcode supported
103 /// - UpperBound(2) - numerically maximum + 1 opcode supported
104 /// - Default(4) - failure jump target
105 /// - JumpTable(4)... - (UpperBound - LowerBound) (at least 2) jump targets
107
108 /// Switch over the LLT on the specified instruction operand
109 /// - InsnID(ULEB128) - Instruction ID
110 /// - OpIdx(ULEB128) - Operand index
111 /// - LowerBound(2) - numerically minimum Type ID supported
112 /// - UpperBound(2) - numerically maximum + 1 Type ID supported
113 /// - Default(4) - failure jump target
114 /// - JumpTable(4)... - (UpperBound - LowerBound) (at least 2) jump targets
116
117 /// Switch over the shape of an LLT on the specified instruction operand
118 /// - InsnID(ULEB128) - Instruction ID
119 /// - OpIdx(ULEB128) - Operand index
120 /// - LowerBound(2) - numerically minimum Type ID supported
121 /// - UpperBound(2) - numerically maximum + 1 Type ID supported
122 /// - Default(4) - failure jump target
123 /// - JumpTable(4)... - (UpperBound - LowerBound) (at least 2) jump targets
125
126 /// Record the specified instruction.
127 /// The IgnoreCopies variant ignores COPY instructions.
128 /// - NewInsnID(ULEB128) - Instruction ID to define
129 /// - InsnID(ULEB128) - Instruction ID
130 /// - OpIdx(ULEB128) - Operand index
133
134 /// Check the opcode on the specified instruction
135 /// - InsnID(ULEB128) - Instruction ID
136 /// - Opc(2) - Expected opcode
138
139 /// Check the opcode on the specified instruction, checking 2 acceptable
140 /// alternatives.
141 /// - InsnID(ULEB128) - Instruction ID
142 /// - Opc(2) - Expected opcode
143 /// - Opc(2) - Alternative expected opcode
145
146 /// Check the instruction has the right number of operands
147 /// - InsnID(ULEB128) - Instruction ID
148 /// - Ops(ULEB128) - Expected number of operands
150
151 /// Check the instruction has a number of operands <= or >= than given number.
152 /// - InsnID(ULEB128) - Instruction ID
153 /// - Ops(ULEB128) - Number of operands
156
157 /// Check an immediate predicate on the specified instruction
158 /// - InsnID(ULEB128) - Instruction ID
159 /// - Pred(2) - The predicate to test
161 /// Check an immediate predicate on the specified instruction via an APInt.
162 /// - InsnID(ULEB128) - Instruction ID
163 /// - Pred(2) - The predicate to test
165 /// Check a floating point immediate predicate on the specified instruction.
166 /// - InsnID(ULEB128) - Instruction ID
167 /// - Pred(2) - The predicate to test
169 /// Check an immediate predicate on the specified instruction
170 /// - InsnID(ULEB128) - Instruction ID
171 /// - OpIdx(ULEB128) - Operand index
172 /// - Pred(2) - The predicate to test
174
175 /// Check a leaf predicate on the specified instruction.
176 /// - InsnID(ULEB128) - Instruction ID
177 /// - OpIdx(ULEB128) - Operand index
178 /// - Pred(2) - The predicate to test
180
181 /// Check a memory operation has the specified atomic ordering.
182 /// - InsnID(ULEB128) - Instruction ID
183 /// - Ordering(ULEB128) - The AtomicOrdering value
187
188 /// Check the size of the memory access for the given machine memory operand.
189 /// - InsnID(ULEB128) - Instruction ID
190 /// - MMOIdx(ULEB128) - MMO index
191 /// - Size(4) - The size in bytes of the memory access
193
194 /// Check the address space of the memory access for the given machine memory
195 /// operand.
196 /// - InsnID(ULEB128) - Instruction ID
197 /// - MMOIdx(ULEB128) - MMO index
198 /// - NumAddrSpace(1) - Number of valid address spaces
199 /// - AddrSpaceN(ULEB128) - An allowed space of the memory access
200 /// - AddrSpaceN+1 ...
202
203 /// Check the minimum alignment of the memory access for the given machine
204 /// memory operand.
205 /// - InsnID(ULEB128) - Instruction ID
206 /// - MMOIdx(ULEB128) - MMO index
207 /// - MinAlign(1) - Minimum acceptable alignment
209
210 /// Check the size of the memory access for the given machine memory operand
211 /// against the size of an operand.
212 /// - InsnID(ULEB128) - Instruction ID
213 /// - MMOIdx(ULEB128) - MMO index
214 /// - OpIdx(ULEB128) - The operand index to compare the MMO against
218
219 /// Check if this is a vector that can be treated as a vector splat
220 /// constant. This is valid for both G_BUILD_VECTOR as well as
221 /// G_BUILD_VECTOR_TRUNC. For AllOnes refers to individual bits, so a -1
222 /// element.
223 /// - InsnID(ULEB128) - Instruction ID
226
227 /// Check a trivial predicate which takes no arguments.
228 /// This can be used by executors to implement custom flags that don't fit in
229 /// target features.
230 /// - Pred(2) - Predicate ID to check.
232
233 /// Check a generic C++ instruction predicate
234 /// - InsnID(ULEB128) - Instruction ID
235 /// - PredicateID(2) - The ID of the predicate function to call
237
238 /// Check if there's no use of the first result.
239 /// - InsnID(ULEB128) - Instruction ID
241
242 /// Check if there's one use of the first result.
243 /// - InsnID(ULEB128) - Instruction ID
245
246 /// Check the type for the specified operand
247 /// - InsnID(ULEB128) - Instruction ID
248 /// - OpIdx(ULEB128) - Operand index
249 /// - Ty(1) - Expected type
251 /// GIM_CheckType but InsnID is omitted and defaults to zero.
253
254 /// Check the type of a pointer to any address space.
255 /// - InsnID(ULEB128) - Instruction ID
256 /// - OpIdx(ULEB128) - Operand index
257 /// - SizeInBits(ULEB128) - The size of the pointer value in bits.
259
260 /// Check the register bank for the specified operand
261 /// - InsnID(ULEB128) - Instruction ID
262 /// - OpIdx(ULEB128) - Operand index
263 /// - RC(2) - Expected register bank (specified as a register class)
265 /// GIM_CheckRegBankForClass but InsnID is omitted and defaults to zero.
267
268 /// Check the operand matches a complex predicate
269 /// - InsnID(ULEB128) - Instruction ID
270 /// - OpIdx(ULEB128) - Operand index
271 /// - RendererID(2) - The renderer to hold the result
272 /// - Pred(2) - Complex predicate ID
274
275 /// Check the operand is a specific integer
276 /// - InsnID(ULEB128) - Instruction ID
277 /// - OpIdx(ULEB128) - Operand index
278 /// - Val(8) Expected integer
280
281 /// Check the operand is a specific 8-bit signed integer
282 /// - InsnID(ULEB128) - Instruction ID
283 /// - OpIdx(ULEB128) - Operand index
284 /// - Val(1) Expected integer
286
287 /// Check the operand is a specific literal integer (i.e. MO.isImm() or
288 /// MO.isCImm() is true).
289 /// - InsnID(ULEB128) - Instruction ID
290 /// - OpIdx(ULEB128) - Operand index
291 /// - Val(8) - Expected integer
293
294 /// Check the operand is a specific intrinsic ID
295 /// - InsnID(ULEB128) - Instruction ID
296 /// - OpIdx(ULEB128) - Operand index
297 /// - IID(2) - Expected Intrinsic ID
299
300 /// Check the operand is a specific predicate
301 /// - InsnID(ULEB128) - Instruction ID
302 /// - OpIdx(ULEB128) - Operand index
303 /// - Pred(2) - Expected predicate
305
306 /// Check the specified operand is an MBB
307 /// - InsnID(ULEB128) - Instruction ID
308 /// - OpIdx(ULEB128) - Operand index
310
311 /// Check the specified operand is an Imm
312 /// - InsnID(ULEB128) - Instruction ID
313 /// - OpIdx(ULEB128) - Operand index
315
316 /// Checks if the matched instructions numbered [1, 1+N) can
317 /// be folded into the root (inst 0).
318 /// - Num(1)
320
321 /// Check the specified operands are identical.
322 /// The IgnoreCopies variant looks through COPY instructions before
323 /// comparing the operands.
324 /// The "All" variants check all operands starting from the index.
325 /// - InsnID(ULEB128) - Instruction ID
326 /// - OpIdx(ULEB128) - Operand index
327 /// - OtherInsnID(ULEB128) - Other instruction ID
328 /// - OtherOpIdx(ULEB128) - Other operand index
333
334 /// Check we can replace all uses of a register with another.
335 /// - OldInsnID(ULEB128)
336 /// - OldOpIdx(ULEB128)
337 /// - NewInsnID(ULEB128)
338 /// - NewOpIdx(ULEB128)
340
341 /// Check that a matched instruction has, or doesn't have a MIFlag.
342 ///
343 /// - InsnID(ULEB128) - Instruction to check.
344 /// - Flags(4) - (can be one or more flags OR'd together)
347
348 /// Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some
349 /// named operands that will be recorded in RecordedOperands. Names of these
350 /// operands are referenced in predicate argument list. Emitter determines
351 /// StoreIdx(corresponds to the order in which names appear in argument list).
352 /// - InsnID(ULEB128) - Instruction ID
353 /// - OpIdx(ULEB128) - Operand index
354 /// - StoreIdx(ULEB128) - Store location in RecordedOperands.
356
357 /// Records an operand's register type into the set of temporary types.
358 /// - InsnID(ULEB128) - Instruction ID
359 /// - OpIdx(ULEB128) - Operand index
360 /// - TempTypeIdx(1) - Temp Type Index, always negative.
362
363 /// Fail the current try-block, or completely fail to match if there is no
364 /// current try-block.
366
367 //=== Renderers ===
368
369 /// Mutate an instruction
370 /// - NewInsnID(ULEB128) - Instruction ID to define
371 /// - OldInsnID(ULEB128) - Instruction ID to mutate
372 /// - NewOpcode(2) - The new opcode to use
374
375 /// Build a new instruction
376 /// - InsnID(ULEB128) - Instruction ID to define
377 /// - Opcode(2) - The new opcode to use
379 /// GIR_BuildMI but InsnID is omitted and defaults to zero.
381
382 /// Builds a constant and stores its result in a TempReg.
383 /// - TempRegID(ULEB128) - Temp Register to define.
384 /// - Imm(8) - The immediate to add
386
387 /// Copy an operand to the specified instruction
388 /// - NewInsnID(ULEB128) - Instruction ID to modify
389 /// - OldInsnID(ULEB128) - Instruction ID to copy from
390 /// - OpIdx(ULEB128) - The operand to copy
392 /// GIR_Copy but with both New/OldInsnIDs omitted and defaulting to zero.
394
395 /// Copies all operand starting from OpIdx in OldInsnID into the new
396 /// instruction NewInsnID.
397 /// - NewInsnID(ULEB128) - Instruction ID to modify
398 /// - OldInsnID(ULEB128) - Instruction ID to copy from
399 /// - OpIdx(ULEB128) - The first operand to copy
401
402 /// Copy an operand to the specified instruction or add a zero register if the
403 /// operand is a zero immediate.
404 /// - NewInsnID(ULEB128) - Instruction ID to modify
405 /// - OldInsnID(ULEB128) - Instruction ID to copy from
406 /// - OpIdx(ULEB128) - The operand to copy
407 /// - ZeroReg(2) - The zero register to use
409 /// Copy an operand to the specified instruction
410 /// - NewInsnID(ULEB128) - Instruction ID to modify
411 /// - OldInsnID(ULEB128) - Instruction ID to copy from
412 /// - OpIdx(ULEB128) - The operand to copy
413 /// - SubRegIdx(2) - The subregister to copy
415
416 /// Add an implicit register def to the specified instruction
417 /// - InsnID(ULEB128) - Instruction ID to modify
418 /// - RegNum(2) - The register to add
419 /// - Flags(2) - Register Flags
421 /// Add an implicit register use to the specified instruction
422 /// - InsnID(ULEB128) - Instruction ID to modify
423 /// - RegNum(2) - The register to add
425 /// Add an register to the specified instruction
426 /// - InsnID(ULEB128) - Instruction ID to modify
427 /// - RegNum(2) - The register to add
428 /// - Flags(2) - Register Flags
430
431 /// Adds an intrinsic ID to the specified instruction.
432 /// - InsnID(ULEB128) - Instruction ID to modify
433 /// - IID(2) - Intrinsic ID
435
436 /// Marks the implicit def of a register as dead.
437 /// - InsnID(ULEB128) - Instruction ID to modify
438 /// - OpIdx(ULEB128) - The implicit def operand index
439 ///
440 /// OpIdx starts at 0 for the first implicit def.
442
443 /// Set or unset a MIFlag on an instruction.
444 ///
445 /// - InsnID(ULEB128) - Instruction to modify.
446 /// - Flags(4) - (can be one or more flags OR'd together)
449
450 /// Copy the MIFlags of a matched instruction into an
451 /// output instruction. The flags are OR'd together.
452 ///
453 /// - InsnID(ULEB128) - Instruction to modify.
454 /// - OldInsnID(ULEB128) - Matched instruction to copy flags from.
456
457 /// Add a temporary register to the specified instruction
458 /// - InsnID(ULEB128) - Instruction ID to modify
459 /// - TempRegID(ULEB128) - The temporary register ID to add
460 /// - TempRegFlags(2) - The register flags to set
462
463 /// Add a temporary register to the specified instruction without
464 /// setting any flags.
465 /// - InsnID(ULEB128) - Instruction ID to modify
466 /// - TempRegID(ULEB128) - The temporary register ID to add
468
469 /// Add a temporary register to the specified instruction
470 /// - InsnID(ULEB128) - Instruction ID to modify
471 /// - TempRegID(ULEB128) - The temporary register ID to add
472 /// - TempRegFlags(2) - The register flags to set
473 /// - SubRegIndex(2) - The subregister index to set
475
476 /// Add an immediate to the specified instruction
477 /// - InsnID(ULEB128) - Instruction ID to modify
478 /// - Imm(8) - The immediate to add
480
481 /// Add signed 8 bit immediate to the specified instruction
482 /// - InsnID(ULEB128) - Instruction ID to modify
483 /// - Imm(1) - The immediate to add
485
486 /// Add an CImm to the specified instruction
487 /// - InsnID(ULEB128) - Instruction ID to modify
488 /// - Ty(1) - Type of the constant immediate.
489 /// - Imm(8) - The immediate to add
491
492 /// Render complex operands to the specified instruction
493 /// - InsnID(ULEB128) - Instruction ID to modify
494 /// - RendererID(2) - The renderer to call
496 /// Render sub-operands of complex operands to the specified instruction
497 /// - InsnID(ULEB128) - Instruction ID to modify
498 /// - RendererID(2) - The renderer to call
499 /// - RenderOpID(ULEB128) - The suboperand to render.
501 /// Render subregisters of suboperands of complex operands to the
502 /// specified instruction
503 /// - InsnID(ULEB128) - Instruction ID to modify
504 /// - RendererID(2) - The renderer to call
505 /// - RenderOpID(ULEB128) - The suboperand to render
506 /// - SubRegIdx(2) - The subregister to extract
508
509 /// Render operands to the specified instruction using a custom function
510 /// - InsnID(ULEB128) - Instruction ID to modify
511 /// - OldInsnID(ULEB128) - Instruction ID to get the matched operand from
512 /// - RendererFnID(2) - Custom renderer function to call
514
515 /// Calls a C++ function that concludes the current match.
516 /// The C++ function is free to return false and reject the match, or
517 /// return true and mutate the instruction(s) (or do nothing, even).
518 /// - FnID(2) - The function to call.
520
521 /// Render operands to the specified instruction using a custom function,
522 /// reading from a specific operand.
523 /// - InsnID(ULEB128) - Instruction ID to modify
524 /// - OldInsnID(ULEB128) - Instruction ID to get the matched operand from
525 /// - OpIdx(ULEB128) - Operand index in OldInsnID the render function should
526 /// read
527 /// from..
528 /// - RendererFnID(2) - Custom renderer function to call
530
531 /// Render a G_CONSTANT operator as a sign-extended immediate.
532 /// - NewInsnID(ULEB128) - Instruction ID to modify
533 /// - OldInsnID(ULEB128) - Instruction ID to copy from
534 /// The operand index is implicitly 1.
536
537 /// Render a G_FCONSTANT operator as a sign-extended immediate.
538 /// - NewInsnID(ULEB128) - Instruction ID to modify
539 /// - OldInsnID(ULEB128) - Instruction ID to copy from
540 /// The operand index is implicitly 1.
542
543 /// Constrain an instruction operand to a register class.
544 /// - InsnID(ULEB128) - Instruction ID to modify
545 /// - OpIdx(ULEB128) - Operand index
546 /// - RCEnum(2) - Register class enumeration value
548
549 /// Constrain an instructions operands according to the instruction
550 /// description.
551 /// - InsnID(ULEB128) - Instruction ID to modify
553 /// GIR_ConstrainSelectedInstOperands but InsnID is omitted and defaults to
554 /// zero.
556
557 /// Merge all memory operands into instruction.
558 /// - InsnID(ULEB128) - Instruction ID to modify
559 /// - NumInsnID(1) - Number of instruction IDs following this argument
560 /// - MergeInsnID(ULEB128)... - One or more Instruction ID to merge into the
561 /// result.
563
564 /// Erase from parent.
565 /// - InsnID(ULEB128) - Instruction ID to erase
567
568 /// Combines both a GIR_EraseFromParent 0 + GIR_Done
570
571 /// Create a new temporary register that's not constrained.
572 /// - TempRegID(ULEB128) - The temporary register ID to initialize.
573 /// - Ty(1) - Expected type
575
576 /// Replaces all references to a register from an instruction
577 /// with another register from another instruction.
578 /// - OldInsnID(ULEB128)
579 /// - OldOpIdx(ULEB128)
580 /// - NewInsnID(ULEB128)
581 /// - NewOpIdx(ULEB128)
583
584 /// Replaces all references to a register with a temporary register.
585 /// - OldInsnID(ULEB128)
586 /// - OldOpIdx(ULEB128)
587 /// - TempRegIdx(ULEB128)
589
590 /// A successful emission
592
593 /// Increment the rule coverage counter.
594 /// - RuleID(4) - The ID of the rule that was covered.
596
597 /// Keeping track of the number of the GI opcodes. Must be the last entry.
599};
600
601/// Provides the logic to execute GlobalISel match tables, which are used by the
602/// instruction selector and instruction combiners as their engine to match and
603/// apply MIR patterns.
605public:
606 virtual ~GIMatchTableExecutor() = default;
607
610 MachineFunction *MF = nullptr;
613 // For some predicates, we need to track the current MBB.
615
617
618 /// Setup per-MF executor state.
620 CodeGenCoverage *covinfo = nullptr,
621 ProfileSummaryInfo *psi = nullptr,
622 BlockFrequencyInfo *bfi = nullptr) {
623 CoverageInfo = covinfo;
624 VT = vt;
625 MF = &mf;
626 PSI = psi;
627 BFI = bfi;
628 CurMBB = nullptr;
630 }
631
632protected:
634 std::optional<SmallVector<std::function<void(MachineInstrBuilder &)>, 4>>;
637
639 std::vector<ComplexRendererFns::value_type> Renderers;
642 /// Named operands that predicate with 'let PredicateCodeUsesOperands = 1'
643 /// referenced in its argument list. Operands are inserted at index set by
644 /// emitter, it corresponds to the order in which names appear in argument
645 /// list. Currently such predicates don't have more then 3 arguments.
646 std::array<const MachineOperand *, 3> RecordedOperands;
647
648 /// Types extracted from an instruction's operand.
649 /// Whenever a type index is negative, we look here instead.
651
652 LLVM_ABI MatcherState(unsigned MaxRenderers);
653 };
654
656 const auto &F = MF->getFunction();
657 if (F.hasOptSize())
658 return true;
659 if (CurMBB)
660 if (auto *BB = CurMBB->getBasicBlock())
662 return false;
663 }
664
665public:
666 template <class PredicateBitset, class ComplexMatcherMemFn,
667 class CustomRendererFn>
668 struct ExecInfoTy {
669 ExecInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
670 const PredicateBitset *FeatureBitsets,
671 const ComplexMatcherMemFn *ComplexPredicates,
672 const CustomRendererFn *CustomRenderers)
676
677 for (size_t I = 0; I < NumTypeObjects; ++I)
678 TypeIDMap[TypeObjects[I].getUniqueRAWLLTData()] = I;
679 }
681 const PredicateBitset *FeatureBitsets;
682 const ComplexMatcherMemFn *ComplexPredicates;
683 const CustomRendererFn *CustomRenderers;
684
686 };
687
688protected:
690
691 /// Execute a given matcher table and return true if the match was successful
692 /// and false otherwise.
693 template <class TgtExecutor, class PredicateBitset, class ComplexMatcherMemFn,
694 class CustomRendererFn>
695 bool executeMatchTable(TgtExecutor &Exec, MatcherState &State,
696 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn,
697 CustomRendererFn> &ExecInfo,
698 MachineIRBuilder &Builder, const uint8_t *MatchTable,
700 const TargetRegisterInfo &TRI,
701 const RegisterBankInfo &RBI,
702 const PredicateBitset &AvailableFeatures,
704
705 virtual const uint8_t *getMatchTable() const {
706 llvm_unreachable("Should have been overridden by tablegen if used");
707 }
708
709 virtual bool testImmPredicate_I64(unsigned, int64_t) const {
711 "Subclasses must override this with a tablegen-erated function");
712 }
713 virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
715 "Subclasses must override this with a tablegen-erated function");
716 }
717 virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
719 "Subclasses must override this with a tablegen-erated function");
720 }
721 virtual bool testMIPredicate_MI(unsigned, const MachineInstr &,
722 const MatcherState &State) const {
724 "Subclasses must override this with a tablegen-erated function");
725 }
726
727 virtual bool testMOPredicate_MO(unsigned, const MachineOperand &,
728 const MatcherState &State) const {
730 "Subclasses must override this with a tablegen-erated function");
731 }
732
733 virtual bool testSimplePredicate(unsigned) const {
734 llvm_unreachable("Subclass does not implement testSimplePredicate!");
735 }
736
737 virtual bool runCustomAction(unsigned, const MatcherState &State,
738 NewMIVector &OutMIs) const {
739 llvm_unreachable("Subclass does not implement runCustomAction!");
740 }
741
742 LLVM_ABI bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
743 const MachineRegisterInfo &MRI,
744 bool Splat = false) const;
745
746 /// Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on
747 /// the right-hand side. GlobalISel's separation of pointer and integer types
748 /// means that we don't need to worry about G_OR with equivalent semantics.
750 const MachineRegisterInfo &MRI) const;
751
752 /// Return true if MI can obviously be folded into IntoMI.
753 /// MI and IntoMI do not need to be in the same basic blocks, but MI must
754 /// preceed IntoMI.
756 MachineInstr &IntoMI) const;
757
758 template <typename Ty> static Ty readBytesAs(const uint8_t *MatchTable) {
759 Ty Ret;
760 memcpy(&Ret, MatchTable, sizeof(Ret));
761 return Ret;
762 }
763
765 unsigned FirstVarOp) {
766 auto Operands = drop_begin(MI.operands(), FirstVarOp);
767 return {Operands.begin(), Operands.end()};
768 }
769
770public:
771 // Faster ULEB128 decoder tailored for the Match Table Executor.
772 //
773 // - Arguments are fixed to avoid mid-function checks.
774 // - Unchecked execution, assumes no error.
775 // - Fast common case handling (1 byte values).
778 uint64_t &CurrentIdx) {
779 uint64_t Value = MatchTable[CurrentIdx++];
780 if (LLVM_UNLIKELY(Value >= 128)) {
781 Value &= 0x7f;
782 unsigned Shift = 7;
783 do {
784 uint64_t Slice = MatchTable[CurrentIdx] & 0x7f;
785 Value += Slice << Shift;
786 Shift += 7;
787 } while (MatchTable[CurrentIdx++] >= 128);
788 }
789 return Value;
790 }
791};
792
793} // end namespace llvm
794
795#endif // LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
#define LLVM_UNLIKELY(EXPR)
Definition Compiler.h:336
#define LLVM_ATTRIBUTE_ALWAYS_INLINE
LLVM_ATTRIBUTE_ALWAYS_INLINE - On compilers where we have a directive to do so, mark a method "always...
Definition Compiler.h:356
#define LLVM_ATTRIBUTE_RESTRICT
LLVM_ATTRIBUTE_RESTRICT - Annotates a pointer to tell the compiler that it is not aliased in the curr...
Definition Compiler.h:381
#define LLVM_ABI
Definition Compiler.h:213
This file defines the DenseMap class.
This file defines the DenseSet and SmallDenseSet classes.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
Implement a low-level type suitable for MachineInstr level instruction selection.
#define F(x, y, z)
Definition MD5.cpp:54
#define I(x, y, z)
Definition MD5.cpp:57
Register const TargetRegisterInfo * TRI
This file defines the SmallVector class.
Class for arbitrary precision integers.
Definition APInt.h:78
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
virtual bool testSimplePredicate(unsigned) const
bool executeMatchTable(TgtExecutor &Exec, MatcherState &State, const ExecInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ExecInfo, MachineIRBuilder &Builder, const uint8_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage *CoverageInfo) const
Execute a given matcher table and return true if the match was successful and false otherwise.
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
virtual bool testMOPredicate_MO(unsigned, const MachineOperand &, const MatcherState &State) const
virtual const uint8_t * getMatchTable() const
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &, const MatcherState &State) const
LLVM_ABI bool isBaseWithConstantOffset(const MachineOperand &Root, const MachineRegisterInfo &MRI) const
Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the right-hand side.
virtual bool testImmPredicate_I64(unsigned, int64_t) const
SmallVector< MachineInstrBuilder, 4 > NewMIVector
static Ty readBytesAs(const uint8_t *MatchTable)
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
SmallVector< MachineInstr *, 4 > RecordedMIVector
bool shouldOptForSize(const MachineFunction *MF) const
static LLVM_ATTRIBUTE_ALWAYS_INLINE uint64_t fastDecodeULEB128(const uint8_t *LLVM_ATTRIBUTE_RESTRICT MatchTable, uint64_t &CurrentIdx)
LLVM_ABI bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI, bool Splat=false) const
virtual ~GIMatchTableExecutor()=default
LLVM_ABI bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
virtual void setupMF(MachineFunction &mf, GISelValueTracking *vt, CodeGenCoverage *covinfo=nullptr, ProfileSummaryInfo *psi=nullptr, BlockFrequencyInfo *bfi=nullptr)
Setup per-MF executor state.
virtual bool runCustomAction(unsigned, const MatcherState &State, NewMIVector &OutMIs) const
static ArrayRef< MachineOperand > getRemainingOperands(const MachineInstr &MI, unsigned FirstVarOp)
virtual void setupGeneratedPerFunctionState(MachineFunction &MF)=0
Helper class to build MachineInstr.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Analysis providing profile information.
Holds all the information related to register banks.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
Definition Value.h:75
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition STLExtras.h:315
LLVM_ABI bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
@ GICXXCustomAction_Invalid
@ GIR_AddIntrinsicID
Adds an intrinsic ID to the specified instruction.
@ GIR_ComplexRenderer
Render complex operands to the specified instruction.
@ GIR_ReplaceRegWithTempReg
Replaces all references to a register with a temporary register.
@ GIR_ComplexSubOperandRenderer
Render sub-operands of complex operands to the specified instruction.
@ GIR_MakeTempReg
Create a new temporary register that's not constrained.
@ GIM_CheckMemorySizeEqualTo
Check the size of the memory access for the given machine memory operand.
@ GIM_RootCheckType
GIM_CheckType but InsnID is omitted and defaults to zero.
@ GIM_RootCheckRegBankForClass
GIM_CheckRegBankForClass but InsnID is omitted and defaults to zero.
@ GIR_Done
A successful emission.
@ GIM_RecordNamedOperand
Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some named operands that will be ...
@ GIM_Try
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
@ GIR_RootConstrainSelectedInstOperands
GIR_ConstrainSelectedInstOperands but InsnID is omitted and defaults to zero.
@ GIM_CheckIsBuildVectorAllOnes
Check if this is a vector that can be treated as a vector splat constant.
@ GIM_CheckNumOperands
Check the instruction has the right number of operands.
@ GIR_AddCImm
Add an CImm to the specified instruction.
@ GIR_ConstrainOperandRC
Constrain an instruction operand to a register class.
@ GIM_CheckI64ImmPredicate
Check an immediate predicate on the specified instruction.
@ GIR_AddImplicitDef
Add an implicit register def to the specified instruction.
@ GIM_CheckAPIntImmPredicate
Check an immediate predicate on the specified instruction via an APInt.
@ GIM_CheckHasNoUse
Check if there's no use of the first result.
@ GIM_CheckPointerToAny
Check the type of a pointer to any address space.
@ GIM_CheckMemorySizeEqualToLLT
Check the size of the memory access for the given machine memory operand against the size of an opera...
@ GIM_CheckComplexPattern
Check the operand matches a complex predicate.
@ GIR_CopyConstantAsSImm
Render a G_CONSTANT operator as a sign-extended immediate.
@ GIR_EraseFromParent
Erase from parent.
@ GIM_SwitchType
Switch over the LLT on the specified instruction operand.
@ GIR_CopySubReg
Copy an operand to the specified instruction.
@ GIR_MutateOpcode
Mutate an instruction.
@ GIM_CheckIsBuildVectorAllZeros
@ GIM_CheckAtomicOrderingOrStrongerThan
@ GIR_AddRegister
Add an register to the specified instruction.
@ GIR_AddTempSubRegister
Add a temporary register to the specified instruction.
@ GIM_CheckIsSafeToFold
Checks if the matched instructions numbered [1, 1+N) can be folded into the root (inst 0).
@ GIM_CheckOpcode
Check the opcode on the specified instruction.
@ GIR_ReplaceReg
Replaces all references to a register from an instruction with another register from another instruct...
@ GIM_SwitchOpcode
Switch over the opcode on the specified instruction.
@ GIM_CheckAPFloatImmPredicate
Check a floating point immediate predicate on the specified instruction.
@ GIM_CheckAllSameOperandIgnoreCopies
@ GIM_Reject
Fail the current try-block, or completely fail to match if there is no current try-block.
@ GIR_AddSimpleTempRegister
Add a temporary register to the specified instruction without setting any flags.
@ GIR_AddTempRegister
Add a temporary register to the specified instruction.
@ GIR_Copy
Copy an operand to the specified instruction.
@ GIR_AddImm
Add an immediate to the specified instruction.
@ GIR_CopyFConstantAsFPImm
Render a G_FCONSTANT operator as a sign-extended immediate.
@ GIU_NumOpcodes
Keeping track of the number of the GI opcodes. Must be the last entry.
@ GIR_CopyRemaining
Copies all operand starting from OpIdx in OldInsnID into the new instruction NewInsnID.
@ GIM_MIFlags
Check that a matched instruction has, or doesn't have a MIFlag.
@ GIR_CopyOrAddZeroReg
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
@ GIM_CheckMemoryAlignment
Check the minimum alignment of the memory access for the given machine memory operand.
@ GIM_CheckIsSameOperand
Check the specified operands are identical.
@ GIR_AddImm8
Add signed 8 bit immediate to the specified instruction.
@ GIM_CheckIsSameOperandIgnoreCopies
@ GIM_CheckIsMBB
Check the specified operand is an MBB.
@ GIM_CheckNumOperandsLE
Check the instruction has a number of operands <= or >= than given number.
@ GIM_Try_CheckFeatures
GIM_Try only if the feature bits match.
@ GIM_CheckMemorySizeGreaterThanLLT
@ GIM_CheckRegBankForClass
Check the register bank for the specified operand.
@ GIM_CheckLiteralInt
Check the operand is a specific literal integer (i.e.
@ GIM_CheckMemorySizeLessThanLLT
@ GIM_RecordRegType
Records an operand's register type into the set of temporary types.
@ GIM_CheckLeafOperandPredicate
Check a leaf predicate on the specified instruction.
@ GIM_CheckHasOneUse
Check if there's one use of the first result.
@ GIR_EraseRootFromParent_Done
Combines both a GIR_EraseFromParent 0 + GIR_Done.
@ GIR_CopyMIFlags
Copy the MIFlags of a matched instruction into an output instruction.
@ GIR_DoneWithCustomAction
Calls a C++ function that concludes the current match.
@ GIR_BuildMI
Build a new instruction.
@ GIM_RecordInsn
Record the specified instruction.
@ GIM_CheckIsImm
Check the specified operand is an Imm.
@ GIR_BuildRootMI
GIR_BuildMI but InsnID is omitted and defaults to zero.
@ GIM_CheckCanReplaceReg
Check we can replace all uses of a register with another.
@ GIM_CheckMemoryAddressSpace
Check the address space of the memory access for the given machine memory operand.
@ GIR_CustomRenderer
Render operands to the specified instruction using a custom function.
@ GIM_CheckAtomicOrdering
Check a memory operation has the specified atomic ordering.
@ GIM_CheckType
Check the type for the specified operand.
@ GIM_CheckConstantInt8
Check the operand is a specific 8-bit signed integer.
@ GIM_CheckCmpPredicate
Check the operand is a specific predicate.
@ GIM_CheckOpcodeIsEither
Check the opcode on the specified instruction, checking 2 acceptable alternatives.
@ GIR_SetImplicitDefDead
Marks the implicit def of a register as dead.
@ GIR_BuildConstant
Builds a constant and stores its result in a TempReg.
@ GIR_AddImplicitUse
Add an implicit register use to the specified instruction.
@ GIR_Coverage
Increment the rule coverage counter.
@ GIR_MergeMemOperands
Merge all memory operands into instruction.
@ GIM_CheckImmOperandPredicate
Check an immediate predicate on the specified instruction.
@ GIM_CheckAtomicOrderingWeakerThan
@ GIR_SetMIFlags
Set or unset a MIFlag on an instruction.
@ GIM_CheckIntrinsicID
Check the operand is a specific intrinsic ID.
@ GIM_CheckConstantInt
Check the operand is a specific integer.
@ GIM_SwitchTypeShape
Switch over the shape of an LLT on the specified instruction operand.
@ GIR_RootToRootCopy
GIR_Copy but with both New/OldInsnIDs omitted and defaulting to zero.
@ GIR_ComplexSubOperandSubRegRenderer
Render subregisters of suboperands of complex operands to the specified instruction.
@ GIM_RecordInsnIgnoreCopies
@ GIR_CustomOperandRenderer
Render operands to the specified instruction using a custom function, reading from a specific operand...
@ GIR_ConstrainSelectedInstOperands
Constrain an instructions operands according to the instruction description.
@ GIM_CheckCxxInsnPredicate
Check a generic C++ instruction predicate.
@ GIM_CheckSimplePredicate
Check a trivial predicate which takes no arguments.
SmallDenseMap< uint64_t, unsigned, 64 > TypeIDMap
ExecInfoTy(const LLT *TypeObjects, size_t NumTypeObjects, const PredicateBitset *FeatureBitsets, const ComplexMatcherMemFn *ComplexPredicates, const CustomRendererFn *CustomRenderers)
const ComplexMatcherMemFn * ComplexPredicates
std::array< const MachineOperand *, 3 > RecordedOperands
Named operands that predicate with 'let PredicateCodeUsesOperands = 1' referenced in its argument lis...
SmallVector< LLT, 4 > RecordedTypes
Types extracted from an instruction's operand.
LLVM_ABI MatcherState(unsigned MaxRenderers)
DenseMap< unsigned, Register > TempRegisters
std::vector< ComplexRendererFns::value_type > Renderers