LLVM 23.0.0git
GIMatchTableExecutor.h
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1//===- llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file declares the GIMatchTableExecutor API, the opcodes supported
10/// by the match table, and some associated data structures used by the
11/// executor's implementation (see `GIMatchTableExecutorImpl.h`).
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
16#define LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
17
18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/ADT/Bitset.h"
20#include "llvm/ADT/DenseMap.h"
21#include "llvm/ADT/DenseSet.h"
27#include "llvm/IR/Function.h"
30#include <bitset>
31#include <cstddef>
32#include <cstdint>
33#include <functional>
34#include <initializer_list>
35#include <optional>
36#include <vector>
37
38namespace llvm {
39
41class CodeGenCoverage;
44class APInt;
45class APFloat;
47class MachineInstr;
50class MachineFunction;
51class MachineOperand;
54class TargetInstrInfo;
56
57enum {
60};
61
62/// The MatchTable is encoded as an array of bytes.
63/// Thus, opcodes are expected to be <255.
64///
65/// Operands can be variable-sized, their size is always after their name
66/// in the docs, e.g. "Foo(4)" means that "Foo" takes 4 entries in the table,
67/// so 4 bytes. "Foo()"
68///
69/// As a general rule of thumb:
70/// - Instruction & Operand IDs are ULEB128
71/// - LLT IDs are 1 byte
72/// - Predicates and target opcodes, register and register class IDs are 2
73/// bytes.
74/// - Indexes into the table are 4 bytes.
75/// - Inline constants are 8 bytes
76///
77/// Design notes:
78/// - Inst/Op IDs have to be LEB128 because some targets generate
79/// extremely long patterns which need more than 255 temporaries.
80/// We could just use 2 bytes everytime, but then some targets like
81/// X86/AMDGPU that have no need for it will pay the price all the time.
82enum {
83 /// Begin a try-block to attempt a match and jump to OnFail if it is
84 /// unsuccessful.
85 /// - OnFail(4) - The MatchTable entry at which to resume if the match fails.
86 ///
87 /// FIXME: This ought to take an argument indicating the number of try-blocks
88 /// to exit on failure. It's usually one but the last match attempt of
89 /// a block will need more. The (implemented) alternative is to tack a
90 /// GIM_Reject on the end of each try-block which is simpler but
91 /// requires an extra opcode and iteration in the interpreter on each
92 /// failed match.
94
95 /// Switch over the opcode on the specified instruction
96 /// - InsnID(ULEB128) - Instruction ID
97 /// - LowerBound(2) - numerically minimum opcode supported
98 /// - UpperBound(2) - numerically maximum + 1 opcode supported
99 /// - Default(4) - failure jump target
100 /// - JumpTable(4)... - (UpperBound - LowerBound) (at least 2) jump targets
102
103 /// Switch over the LLT on the specified instruction operand
104 /// - InsnID(ULEB128) - Instruction ID
105 /// - OpIdx(ULEB128) - Operand index
106 /// - LowerBound(2) - numerically minimum Type ID supported
107 /// - UpperBound(2) - numerically maximum + 1 Type ID supported
108 /// - Default(4) - failure jump target
109 /// - JumpTable(4)... - (UpperBound - LowerBound) (at least 2) jump targets
111
112 /// Switch over the shape of an LLT on the specified instruction operand
113 /// - InsnID(ULEB128) - Instruction ID
114 /// - OpIdx(ULEB128) - Operand index
115 /// - LowerBound(2) - numerically minimum Type ID supported
116 /// - UpperBound(2) - numerically maximum + 1 Type ID supported
117 /// - Default(4) - failure jump target
118 /// - JumpTable(4)... - (UpperBound - LowerBound) (at least 2) jump targets
120
121 /// Record the specified instruction.
122 /// The IgnoreCopies variant ignores COPY instructions.
123 /// - NewInsnID(ULEB128) - Instruction ID to define
124 /// - InsnID(ULEB128) - Instruction ID
125 /// - OpIdx(ULEB128) - Operand index
128
129 /// Check the feature bits
130 /// Feature(2) - Expected features
132
133 /// Check the opcode on the specified instruction
134 /// - InsnID(ULEB128) - Instruction ID
135 /// - Opc(2) - Expected opcode
137
138 /// Check the opcode on the specified instruction, checking 2 acceptable
139 /// alternatives.
140 /// - InsnID(ULEB128) - Instruction ID
141 /// - Opc(2) - Expected opcode
142 /// - Opc(2) - Alternative expected opcode
144
145 /// Check the instruction has the right number of operands
146 /// - InsnID(ULEB128) - Instruction ID
147 /// - Ops(ULEB128) - Expected number of operands
149
150 /// Check the instruction has a number of operands <= or >= than given number.
151 /// - InsnID(ULEB128) - Instruction ID
152 /// - Ops(ULEB128) - Number of operands
155
156 /// Check an immediate predicate on the specified instruction
157 /// - InsnID(ULEB128) - Instruction ID
158 /// - Pred(2) - The predicate to test
160 /// Check an immediate predicate on the specified instruction via an APInt.
161 /// - InsnID(ULEB128) - Instruction ID
162 /// - Pred(2) - The predicate to test
164 /// Check a floating point immediate predicate on the specified instruction.
165 /// - InsnID(ULEB128) - Instruction ID
166 /// - Pred(2) - The predicate to test
168 /// Check an immediate predicate on the specified instruction
169 /// - InsnID(ULEB128) - Instruction ID
170 /// - OpIdx(ULEB128) - Operand index
171 /// - Pred(2) - The predicate to test
173
174 /// Check a leaf predicate on the specified instruction.
175 /// - InsnID(ULEB128) - Instruction ID
176 /// - OpIdx(ULEB128) - Operand index
177 /// - Pred(2) - The predicate to test
179
180 /// Check a memory operation has the specified atomic ordering.
181 /// - InsnID(ULEB128) - Instruction ID
182 /// - Ordering(ULEB128) - The AtomicOrdering value
186
187 /// Check the size of the memory access for the given machine memory operand.
188 /// - InsnID(ULEB128) - Instruction ID
189 /// - MMOIdx(ULEB128) - MMO index
190 /// - Size(4) - The size in bytes of the memory access
192
193 /// Check the address space of the memory access for the given machine memory
194 /// operand.
195 /// - InsnID(ULEB128) - Instruction ID
196 /// - MMOIdx(ULEB128) - MMO index
197 /// - NumAddrSpace(1) - Number of valid address spaces
198 /// - AddrSpaceN(ULEB128) - An allowed space of the memory access
199 /// - AddrSpaceN+1 ...
201
202 /// Check the minimum alignment of the memory access for the given machine
203 /// memory operand.
204 /// - InsnID(ULEB128) - Instruction ID
205 /// - MMOIdx(ULEB128) - MMO index
206 /// - MinAlign(1) - Minimum acceptable alignment
208
209 /// Check the size of the memory access for the given machine memory operand
210 /// against the size of an operand.
211 /// - InsnID(ULEB128) - Instruction ID
212 /// - MMOIdx(ULEB128) - MMO index
213 /// - OpIdx(ULEB128) - The operand index to compare the MMO against
217
218 /// Check if this is a vector that can be treated as a vector splat
219 /// constant. This is valid for both G_BUILD_VECTOR as well as
220 /// G_BUILD_VECTOR_TRUNC. For AllOnes refers to individual bits, so a -1
221 /// element.
222 /// - InsnID(ULEB128) - Instruction ID
225
226 /// Check a trivial predicate which takes no arguments.
227 /// This can be used by executors to implement custom flags that don't fit in
228 /// target features.
229 /// - Pred(2) - Predicate ID to check.
231
232 /// Check a generic C++ instruction predicate
233 /// - InsnID(ULEB128) - Instruction ID
234 /// - PredicateID(2) - The ID of the predicate function to call
236
237 /// Check if there's no use of the first result.
238 /// - InsnID(ULEB128) - Instruction ID
240
241 /// Check if there's one use of the first result.
242 /// - InsnID(ULEB128) - Instruction ID
244
245 /// Check the type for the specified operand
246 /// - InsnID(ULEB128) - Instruction ID
247 /// - OpIdx(ULEB128) - Operand index
248 /// - Ty(1) - Expected type
250 /// GIM_CheckType but InsnID is omitted and defaults to zero.
252
253 /// Check the type of a pointer to any address space.
254 /// - InsnID(ULEB128) - Instruction ID
255 /// - OpIdx(ULEB128) - Operand index
256 /// - SizeInBits(ULEB128) - The size of the pointer value in bits.
258
259 /// Check the register bank for the specified operand
260 /// - InsnID(ULEB128) - Instruction ID
261 /// - OpIdx(ULEB128) - Operand index
262 /// - RC(2) - Expected register bank (specified as a register class)
264 /// GIM_CheckRegBankForClass but InsnID is omitted and defaults to zero.
266
267 /// Check the operand matches a complex predicate
268 /// - InsnID(ULEB128) - Instruction ID
269 /// - OpIdx(ULEB128) - Operand index
270 /// - RendererID(2) - The renderer to hold the result
271 /// - Pred(2) - Complex predicate ID
273
274 /// Check the operand is a specific integer
275 /// - InsnID(ULEB128) - Instruction ID
276 /// - OpIdx(ULEB128) - Operand index
277 /// - Val(8) Expected integer
279
280 /// Check the operand is a specific 8-bit signed integer
281 /// - InsnID(ULEB128) - Instruction ID
282 /// - OpIdx(ULEB128) - Operand index
283 /// - Val(1) Expected integer
285
286 /// Check the operand is a specific literal integer (i.e. MO.isImm() or
287 /// MO.isCImm() is true).
288 /// - InsnID(ULEB128) - Instruction ID
289 /// - OpIdx(ULEB128) - Operand index
290 /// - Val(8) - Expected integer
292
293 /// Check the operand is a specific intrinsic ID
294 /// - InsnID(ULEB128) - Instruction ID
295 /// - OpIdx(ULEB128) - Operand index
296 /// - IID(2) - Expected Intrinsic ID
298
299 /// Check the operand is a specific predicate
300 /// - InsnID(ULEB128) - Instruction ID
301 /// - OpIdx(ULEB128) - Operand index
302 /// - Pred(2) - Expected predicate
304
305 /// Check the specified operand is an MBB
306 /// - InsnID(ULEB128) - Instruction ID
307 /// - OpIdx(ULEB128) - Operand index
309
310 /// Check the specified operand is an Imm
311 /// - InsnID(ULEB128) - Instruction ID
312 /// - OpIdx(ULEB128) - Operand index
314
315 /// Checks if the matched instructions numbered [1, 1+N) can
316 /// be folded into the root (inst 0).
317 /// - Num(1)
319
320 /// Check the specified operands are identical.
321 /// The IgnoreCopies variant looks through COPY instructions before
322 /// comparing the operands.
323 /// The "All" variants check all operands starting from the index.
324 /// - InsnID(ULEB128) - Instruction ID
325 /// - OpIdx(ULEB128) - Operand index
326 /// - OtherInsnID(ULEB128) - Other instruction ID
327 /// - OtherOpIdx(ULEB128) - Other operand index
332
333 /// Check we can replace all uses of a register with another.
334 /// - OldInsnID(ULEB128)
335 /// - OldOpIdx(ULEB128)
336 /// - NewInsnID(ULEB128)
337 /// - NewOpIdx(ULEB128)
339
340 /// Check that a matched instruction has, or doesn't have a MIFlag.
341 ///
342 /// - InsnID(ULEB128) - Instruction to check.
343 /// - Flags(4) - (can be one or more flags OR'd together)
346
347 /// Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some
348 /// named operands that will be recorded in RecordedOperands. Names of these
349 /// operands are referenced in predicate argument list. Emitter determines
350 /// StoreIdx(corresponds to the order in which names appear in argument list).
351 /// - InsnID(ULEB128) - Instruction ID
352 /// - OpIdx(ULEB128) - Operand index
353 /// - StoreIdx(ULEB128) - Store location in RecordedOperands.
355
356 /// Records an operand's register type into the set of temporary types.
357 /// - InsnID(ULEB128) - Instruction ID
358 /// - OpIdx(ULEB128) - Operand index
359 /// - TempTypeIdx(1) - Temp Type Index, always negative.
361
362 /// Fail the current try-block, or completely fail to match if there is no
363 /// current try-block.
365
366 //=== Renderers ===
367
368 /// Mutate an instruction
369 /// - NewInsnID(ULEB128) - Instruction ID to define
370 /// - OldInsnID(ULEB128) - Instruction ID to mutate
371 /// - NewOpcode(2) - The new opcode to use
373
374 /// Build a new instruction
375 /// - InsnID(ULEB128) - Instruction ID to define
376 /// - Opcode(2) - The new opcode to use
378 /// GIR_BuildMI but InsnID is omitted and defaults to zero.
380
381 /// Builds a constant and stores its result in a TempReg.
382 /// - TempRegID(ULEB128) - Temp Register to define.
383 /// - Imm(8) - The immediate to add
385
386 /// Copy an operand to the specified instruction
387 /// - NewInsnID(ULEB128) - Instruction ID to modify
388 /// - OldInsnID(ULEB128) - Instruction ID to copy from
389 /// - OpIdx(ULEB128) - The operand to copy
391 /// GIR_Copy but with both New/OldInsnIDs omitted and defaulting to zero.
393
394 /// Copies all operand starting from OpIdx in OldInsnID into the new
395 /// instruction NewInsnID.
396 /// - NewInsnID(ULEB128) - Instruction ID to modify
397 /// - OldInsnID(ULEB128) - Instruction ID to copy from
398 /// - OpIdx(ULEB128) - The first operand to copy
400
401 /// Copy an operand to the specified instruction or add a zero register if the
402 /// operand is a zero immediate.
403 /// - NewInsnID(ULEB128) - Instruction ID to modify
404 /// - OldInsnID(ULEB128) - Instruction ID to copy from
405 /// - OpIdx(ULEB128) - The operand to copy
406 /// - ZeroReg(2) - The zero register to use
408 /// Copy an operand to the specified instruction
409 /// - NewInsnID(ULEB128) - Instruction ID to modify
410 /// - OldInsnID(ULEB128) - Instruction ID to copy from
411 /// - OpIdx(ULEB128) - The operand to copy
412 /// - SubRegIdx(2) - The subregister to copy
414
415 /// Add an implicit register def to the specified instruction
416 /// - InsnID(ULEB128) - Instruction ID to modify
417 /// - RegNum(2) - The register to add
418 /// - Flags(2) - Register Flags
420 /// Add an implicit register use to the specified instruction
421 /// - InsnID(ULEB128) - Instruction ID to modify
422 /// - RegNum(2) - The register to add
424 /// Add an register to the specified instruction
425 /// - InsnID(ULEB128) - Instruction ID to modify
426 /// - RegNum(2) - The register to add
427 /// - Flags(2) - Register Flags
429
430 /// Adds an intrinsic ID to the specified instruction.
431 /// - InsnID(ULEB128) - Instruction ID to modify
432 /// - IID(2) - Intrinsic ID
434
435 /// Marks the implicit def of a register as dead.
436 /// - InsnID(ULEB128) - Instruction ID to modify
437 /// - OpIdx(ULEB128) - The implicit def operand index
438 ///
439 /// OpIdx starts at 0 for the first implicit def.
441
442 /// Set or unset a MIFlag on an instruction.
443 ///
444 /// - InsnID(ULEB128) - Instruction to modify.
445 /// - Flags(4) - (can be one or more flags OR'd together)
448
449 /// Copy the MIFlags of a matched instruction into an
450 /// output instruction. The flags are OR'd together.
451 ///
452 /// - InsnID(ULEB128) - Instruction to modify.
453 /// - OldInsnID(ULEB128) - Matched instruction to copy flags from.
455
456 /// Add a temporary register to the specified instruction
457 /// - InsnID(ULEB128) - Instruction ID to modify
458 /// - TempRegID(ULEB128) - The temporary register ID to add
459 /// - TempRegFlags(2) - The register flags to set
461
462 /// Add a temporary register to the specified instruction without
463 /// setting any flags.
464 /// - InsnID(ULEB128) - Instruction ID to modify
465 /// - TempRegID(ULEB128) - The temporary register ID to add
467
468 /// Add a temporary register to the specified instruction
469 /// - InsnID(ULEB128) - Instruction ID to modify
470 /// - TempRegID(ULEB128) - The temporary register ID to add
471 /// - TempRegFlags(2) - The register flags to set
472 /// - SubRegIndex(2) - The subregister index to set
474
475 /// Add an immediate to the specified instruction
476 /// - InsnID(ULEB128) - Instruction ID to modify
477 /// - Imm(8) - The immediate to add
479
480 /// Add signed 8 bit immediate to the specified instruction
481 /// - InsnID(ULEB128) - Instruction ID to modify
482 /// - Imm(1) - The immediate to add
484
485 /// Add an CImm to the specified instruction
486 /// - InsnID(ULEB128) - Instruction ID to modify
487 /// - Ty(1) - Type of the constant immediate.
488 /// - Imm(8) - The immediate to add
490
491 /// Render complex operands to the specified instruction
492 /// - InsnID(ULEB128) - Instruction ID to modify
493 /// - RendererID(2) - The renderer to call
495 /// Render sub-operands of complex operands to the specified instruction
496 /// - InsnID(ULEB128) - Instruction ID to modify
497 /// - RendererID(2) - The renderer to call
498 /// - RenderOpID(ULEB128) - The suboperand to render.
500 /// Render subregisters of suboperands of complex operands to the
501 /// specified instruction
502 /// - InsnID(ULEB128) - Instruction ID to modify
503 /// - RendererID(2) - The renderer to call
504 /// - RenderOpID(ULEB128) - The suboperand to render
505 /// - SubRegIdx(2) - The subregister to extract
507
508 /// Render operands to the specified instruction using a custom function
509 /// - InsnID(ULEB128) - Instruction ID to modify
510 /// - OldInsnID(ULEB128) - Instruction ID to get the matched operand from
511 /// - RendererFnID(2) - Custom renderer function to call
513
514 /// Calls a C++ function that concludes the current match.
515 /// The C++ function is free to return false and reject the match, or
516 /// return true and mutate the instruction(s) (or do nothing, even).
517 /// - FnID(2) - The function to call.
519
520 /// Render operands to the specified instruction using a custom function,
521 /// reading from a specific operand.
522 /// - InsnID(ULEB128) - Instruction ID to modify
523 /// - OldInsnID(ULEB128) - Instruction ID to get the matched operand from
524 /// - OpIdx(ULEB128) - Operand index in OldInsnID the render function should
525 /// read
526 /// from..
527 /// - RendererFnID(2) - Custom renderer function to call
529
530 /// Render a G_CONSTANT operator as a sign-extended immediate.
531 /// - NewInsnID(ULEB128) - Instruction ID to modify
532 /// - OldInsnID(ULEB128) - Instruction ID to copy from
533 /// The operand index is implicitly 1.
535
536 /// Render a G_FCONSTANT operator as a sign-extended immediate.
537 /// - NewInsnID(ULEB128) - Instruction ID to modify
538 /// - OldInsnID(ULEB128) - Instruction ID to copy from
539 /// The operand index is implicitly 1.
541
542 /// Constrain an instruction operand to a register class.
543 /// - InsnID(ULEB128) - Instruction ID to modify
544 /// - OpIdx(ULEB128) - Operand index
545 /// - RCEnum(2) - Register class enumeration value
547
548 /// Constrain an instructions operands according to the instruction
549 /// description.
550 /// - InsnID(ULEB128) - Instruction ID to modify
552 /// GIR_ConstrainSelectedInstOperands but InsnID is omitted and defaults to
553 /// zero.
555
556 /// Merge all memory operands into instruction.
557 /// - InsnID(ULEB128) - Instruction ID to modify
558 /// - NumInsnID(1) - Number of instruction IDs following this argument
559 /// - MergeInsnID(ULEB128)... - One or more Instruction ID to merge into the
560 /// result.
562
563 /// Erase from parent.
564 /// - InsnID(ULEB128) - Instruction ID to erase
566
567 /// Combines both a GIR_EraseFromParent 0 + GIR_Done
569
570 /// Create a new temporary register that's not constrained.
571 /// - TempRegID(ULEB128) - The temporary register ID to initialize.
572 /// - Ty(1) - Expected type
574
575 /// Replaces all references to a register from an instruction
576 /// with another register from another instruction.
577 /// - OldInsnID(ULEB128)
578 /// - OldOpIdx(ULEB128)
579 /// - NewInsnID(ULEB128)
580 /// - NewOpIdx(ULEB128)
582
583 /// Replaces all references to a register with a temporary register.
584 /// - OldInsnID(ULEB128)
585 /// - OldOpIdx(ULEB128)
586 /// - TempRegIdx(ULEB128)
588
589 /// A successful emission
591
592 /// Increment the rule coverage counter.
593 /// - RuleID(4) - The ID of the rule that was covered.
595
596 /// Keeping track of the number of the GI opcodes. Must be the last entry.
598};
599
600/// Provides the logic to execute GlobalISel match tables, which are used by the
601/// instruction selector and instruction combiners as their engine to match and
602/// apply MIR patterns.
604public:
605 virtual ~GIMatchTableExecutor() = default;
606
609 MachineFunction *MF = nullptr;
612 // For some predicates, we need to track the current MBB.
614
616
617 /// Setup per-MF executor state.
619 CodeGenCoverage *covinfo = nullptr,
620 ProfileSummaryInfo *psi = nullptr,
621 BlockFrequencyInfo *bfi = nullptr) {
622 CoverageInfo = covinfo;
623 VT = vt;
624 MF = &mf;
625 PSI = psi;
626 BFI = bfi;
627 CurMBB = nullptr;
629 }
630
631protected:
633 std::optional<SmallVector<std::function<void(MachineInstrBuilder &)>, 4>>;
636
638 std::vector<ComplexRendererFns::value_type> Renderers;
641 /// Named operands that predicate with 'let PredicateCodeUsesOperands = 1'
642 /// referenced in its argument list. Operands are inserted at index set by
643 /// emitter, it corresponds to the order in which names appear in argument
644 /// list. Currently such predicates don't have more then 3 arguments.
645 std::array<const MachineOperand *, 3> RecordedOperands;
646
647 /// Types extracted from an instruction's operand.
648 /// Whenever a type index is negative, we look here instead.
650
651 LLVM_ABI MatcherState(unsigned MaxRenderers);
652 };
653
655 const auto &F = MF->getFunction();
656 if (F.hasOptSize())
657 return true;
658 if (CurMBB)
659 if (auto *BB = CurMBB->getBasicBlock())
661 return false;
662 }
663
664public:
665 template <class PredicateBitset, class ComplexMatcherMemFn,
666 class CustomRendererFn>
667 struct ExecInfoTy {
668 ExecInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
669 const PredicateBitset *FeatureBitsets,
670 const ComplexMatcherMemFn *ComplexPredicates,
671 const CustomRendererFn *CustomRenderers)
675
676 for (size_t I = 0; I < NumTypeObjects; ++I)
677 TypeIDMap[TypeObjects[I].getUniqueRAWLLTData()] = I;
678 }
680 const PredicateBitset *FeatureBitsets;
681 const ComplexMatcherMemFn *ComplexPredicates;
682 const CustomRendererFn *CustomRenderers;
683
685 };
686
687protected:
689
690 /// Execute a given matcher table and return true if the match was successful
691 /// and false otherwise.
692 template <class TgtExecutor, class PredicateBitset, class ComplexMatcherMemFn,
693 class CustomRendererFn>
694 bool executeMatchTable(TgtExecutor &Exec, MatcherState &State,
695 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn,
696 CustomRendererFn> &ExecInfo,
697 MachineIRBuilder &Builder, const uint8_t *MatchTable,
699 const TargetRegisterInfo &TRI,
700 const RegisterBankInfo &RBI,
701 const PredicateBitset &AvailableFeatures,
703
704 virtual const uint8_t *getMatchTable() const {
705 llvm_unreachable("Should have been overridden by tablegen if used");
706 }
707
708 virtual bool testImmPredicate_I64(unsigned, int64_t) const {
710 "Subclasses must override this with a tablegen-erated function");
711 }
712 virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
714 "Subclasses must override this with a tablegen-erated function");
715 }
716 virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
718 "Subclasses must override this with a tablegen-erated function");
719 }
720 virtual bool testMIPredicate_MI(unsigned, const MachineInstr &,
721 const MatcherState &State) const {
723 "Subclasses must override this with a tablegen-erated function");
724 }
725
726 virtual bool testMOPredicate_MO(unsigned, const MachineOperand &,
727 const MatcherState &State) const {
729 "Subclasses must override this with a tablegen-erated function");
730 }
731
732 virtual bool testSimplePredicate(unsigned) const {
733 llvm_unreachable("Subclass does not implement testSimplePredicate!");
734 }
735
736 virtual bool runCustomAction(unsigned, const MatcherState &State,
737 NewMIVector &OutMIs) const {
738 llvm_unreachable("Subclass does not implement runCustomAction!");
739 }
740
741 LLVM_ABI bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
742 const MachineRegisterInfo &MRI,
743 bool Splat = false) const;
744
745 /// Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on
746 /// the right-hand side. GlobalISel's separation of pointer and integer types
747 /// means that we don't need to worry about G_OR with equivalent semantics.
749 const MachineRegisterInfo &MRI) const;
750
751 /// Return true if MI can obviously be folded into IntoMI.
752 /// MI and IntoMI do not need to be in the same basic blocks, but MI must
753 /// preceed IntoMI.
755 MachineInstr &IntoMI) const;
756
757 template <typename Ty> static Ty readBytesAs(const uint8_t *MatchTable) {
758 Ty Ret;
759 memcpy(&Ret, MatchTable, sizeof(Ret));
760 return Ret;
761 }
762
764 unsigned FirstVarOp) {
765 auto Operands = drop_begin(MI.operands(), FirstVarOp);
766 return {Operands.begin(), Operands.end()};
767 }
768
769public:
770 // Faster ULEB128 decoder tailored for the Match Table Executor.
771 //
772 // - Arguments are fixed to avoid mid-function checks.
773 // - Unchecked execution, assumes no error.
774 // - Fast common case handling (1 byte values).
777 uint64_t &CurrentIdx) {
778 uint64_t Value = MatchTable[CurrentIdx++];
779 if (LLVM_UNLIKELY(Value >= 128)) {
780 Value &= 0x7f;
781 unsigned Shift = 7;
782 do {
783 uint64_t Slice = MatchTable[CurrentIdx] & 0x7f;
784 Value += Slice << Shift;
785 Shift += 7;
786 } while (MatchTable[CurrentIdx++] >= 128);
787 }
788 return Value;
789 }
790};
791
792} // end namespace llvm
793
794#endif // LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
#define LLVM_UNLIKELY(EXPR)
Definition Compiler.h:336
#define LLVM_ATTRIBUTE_ALWAYS_INLINE
LLVM_ATTRIBUTE_ALWAYS_INLINE - On compilers where we have a directive to do so, mark a method "always...
Definition Compiler.h:356
#define LLVM_ATTRIBUTE_RESTRICT
LLVM_ATTRIBUTE_RESTRICT - Annotates a pointer to tell the compiler that it is not aliased in the curr...
Definition Compiler.h:381
#define LLVM_ABI
Definition Compiler.h:213
This file defines the DenseMap class.
This file defines the DenseSet and SmallDenseSet classes.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
Implement a low-level type suitable for MachineInstr level instruction selection.
#define F(x, y, z)
Definition MD5.cpp:54
#define I(x, y, z)
Definition MD5.cpp:57
Register const TargetRegisterInfo * TRI
This file defines the SmallVector class.
Class for arbitrary precision integers.
Definition APInt.h:78
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
virtual bool testSimplePredicate(unsigned) const
bool executeMatchTable(TgtExecutor &Exec, MatcherState &State, const ExecInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ExecInfo, MachineIRBuilder &Builder, const uint8_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage *CoverageInfo) const
Execute a given matcher table and return true if the match was successful and false otherwise.
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
virtual bool testMOPredicate_MO(unsigned, const MachineOperand &, const MatcherState &State) const
virtual const uint8_t * getMatchTable() const
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &, const MatcherState &State) const
LLVM_ABI bool isBaseWithConstantOffset(const MachineOperand &Root, const MachineRegisterInfo &MRI) const
Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the right-hand side.
virtual bool testImmPredicate_I64(unsigned, int64_t) const
SmallVector< MachineInstrBuilder, 4 > NewMIVector
static Ty readBytesAs(const uint8_t *MatchTable)
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
SmallVector< MachineInstr *, 4 > RecordedMIVector
bool shouldOptForSize(const MachineFunction *MF) const
static LLVM_ATTRIBUTE_ALWAYS_INLINE uint64_t fastDecodeULEB128(const uint8_t *LLVM_ATTRIBUTE_RESTRICT MatchTable, uint64_t &CurrentIdx)
LLVM_ABI bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI, bool Splat=false) const
virtual ~GIMatchTableExecutor()=default
LLVM_ABI bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
virtual void setupMF(MachineFunction &mf, GISelValueTracking *vt, CodeGenCoverage *covinfo=nullptr, ProfileSummaryInfo *psi=nullptr, BlockFrequencyInfo *bfi=nullptr)
Setup per-MF executor state.
virtual bool runCustomAction(unsigned, const MatcherState &State, NewMIVector &OutMIs) const
static ArrayRef< MachineOperand > getRemainingOperands(const MachineInstr &MI, unsigned FirstVarOp)
virtual void setupGeneratedPerFunctionState(MachineFunction &MF)=0
Helper class to build MachineInstr.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Analysis providing profile information.
Holds all the information related to register banks.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
Definition Value.h:75
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition STLExtras.h:316
LLVM_ABI bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
@ GICXXCustomAction_Invalid
@ GIR_AddIntrinsicID
Adds an intrinsic ID to the specified instruction.
@ GIR_ComplexRenderer
Render complex operands to the specified instruction.
@ GIR_ReplaceRegWithTempReg
Replaces all references to a register with a temporary register.
@ GIR_ComplexSubOperandRenderer
Render sub-operands of complex operands to the specified instruction.
@ GIR_MakeTempReg
Create a new temporary register that's not constrained.
@ GIM_CheckMemorySizeEqualTo
Check the size of the memory access for the given machine memory operand.
@ GIM_RootCheckType
GIM_CheckType but InsnID is omitted and defaults to zero.
@ GIM_RootCheckRegBankForClass
GIM_CheckRegBankForClass but InsnID is omitted and defaults to zero.
@ GIR_Done
A successful emission.
@ GIM_RecordNamedOperand
Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some named operands that will be ...
@ GIM_Try
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
@ GIR_RootConstrainSelectedInstOperands
GIR_ConstrainSelectedInstOperands but InsnID is omitted and defaults to zero.
@ GIM_CheckIsBuildVectorAllOnes
Check if this is a vector that can be treated as a vector splat constant.
@ GIM_CheckNumOperands
Check the instruction has the right number of operands.
@ GIR_AddCImm
Add an CImm to the specified instruction.
@ GIR_ConstrainOperandRC
Constrain an instruction operand to a register class.
@ GIM_CheckI64ImmPredicate
Check an immediate predicate on the specified instruction.
@ GIR_AddImplicitDef
Add an implicit register def to the specified instruction.
@ GIM_CheckAPIntImmPredicate
Check an immediate predicate on the specified instruction via an APInt.
@ GIM_CheckHasNoUse
Check if there's no use of the first result.
@ GIM_CheckPointerToAny
Check the type of a pointer to any address space.
@ GIM_CheckMemorySizeEqualToLLT
Check the size of the memory access for the given machine memory operand against the size of an opera...
@ GIM_CheckComplexPattern
Check the operand matches a complex predicate.
@ GIR_CopyConstantAsSImm
Render a G_CONSTANT operator as a sign-extended immediate.
@ GIR_EraseFromParent
Erase from parent.
@ GIM_SwitchType
Switch over the LLT on the specified instruction operand.
@ GIR_CopySubReg
Copy an operand to the specified instruction.
@ GIR_MutateOpcode
Mutate an instruction.
@ GIM_CheckIsBuildVectorAllZeros
@ GIM_CheckAtomicOrderingOrStrongerThan
@ GIR_AddRegister
Add an register to the specified instruction.
@ GIR_AddTempSubRegister
Add a temporary register to the specified instruction.
@ GIM_CheckIsSafeToFold
Checks if the matched instructions numbered [1, 1+N) can be folded into the root (inst 0).
@ GIM_CheckOpcode
Check the opcode on the specified instruction.
@ GIR_ReplaceReg
Replaces all references to a register from an instruction with another register from another instruct...
@ GIM_SwitchOpcode
Switch over the opcode on the specified instruction.
@ GIM_CheckAPFloatImmPredicate
Check a floating point immediate predicate on the specified instruction.
@ GIM_CheckAllSameOperandIgnoreCopies
@ GIM_Reject
Fail the current try-block, or completely fail to match if there is no current try-block.
@ GIR_AddSimpleTempRegister
Add a temporary register to the specified instruction without setting any flags.
@ GIR_AddTempRegister
Add a temporary register to the specified instruction.
@ GIR_Copy
Copy an operand to the specified instruction.
@ GIR_AddImm
Add an immediate to the specified instruction.
@ GIR_CopyFConstantAsFPImm
Render a G_FCONSTANT operator as a sign-extended immediate.
@ GIU_NumOpcodes
Keeping track of the number of the GI opcodes. Must be the last entry.
@ GIR_CopyRemaining
Copies all operand starting from OpIdx in OldInsnID into the new instruction NewInsnID.
@ GIM_MIFlags
Check that a matched instruction has, or doesn't have a MIFlag.
@ GIR_CopyOrAddZeroReg
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
@ GIM_CheckMemoryAlignment
Check the minimum alignment of the memory access for the given machine memory operand.
@ GIM_CheckIsSameOperand
Check the specified operands are identical.
@ GIR_AddImm8
Add signed 8 bit immediate to the specified instruction.
@ GIM_CheckIsSameOperandIgnoreCopies
@ GIM_CheckIsMBB
Check the specified operand is an MBB.
@ GIM_CheckNumOperandsLE
Check the instruction has a number of operands <= or >= than given number.
@ GIM_CheckMemorySizeGreaterThanLLT
@ GIM_CheckRegBankForClass
Check the register bank for the specified operand.
@ GIM_CheckLiteralInt
Check the operand is a specific literal integer (i.e.
@ GIM_CheckMemorySizeLessThanLLT
@ GIM_RecordRegType
Records an operand's register type into the set of temporary types.
@ GIM_CheckLeafOperandPredicate
Check a leaf predicate on the specified instruction.
@ GIM_CheckHasOneUse
Check if there's one use of the first result.
@ GIR_EraseRootFromParent_Done
Combines both a GIR_EraseFromParent 0 + GIR_Done.
@ GIR_CopyMIFlags
Copy the MIFlags of a matched instruction into an output instruction.
@ GIR_DoneWithCustomAction
Calls a C++ function that concludes the current match.
@ GIR_BuildMI
Build a new instruction.
@ GIM_RecordInsn
Record the specified instruction.
@ GIM_CheckIsImm
Check the specified operand is an Imm.
@ GIR_BuildRootMI
GIR_BuildMI but InsnID is omitted and defaults to zero.
@ GIM_CheckFeatures
Check the feature bits Feature(2) - Expected features.
@ GIM_CheckCanReplaceReg
Check we can replace all uses of a register with another.
@ GIM_CheckMemoryAddressSpace
Check the address space of the memory access for the given machine memory operand.
@ GIR_CustomRenderer
Render operands to the specified instruction using a custom function.
@ GIM_CheckAtomicOrdering
Check a memory operation has the specified atomic ordering.
@ GIM_CheckType
Check the type for the specified operand.
@ GIM_CheckConstantInt8
Check the operand is a specific 8-bit signed integer.
@ GIM_CheckCmpPredicate
Check the operand is a specific predicate.
@ GIM_CheckOpcodeIsEither
Check the opcode on the specified instruction, checking 2 acceptable alternatives.
@ GIR_SetImplicitDefDead
Marks the implicit def of a register as dead.
@ GIR_BuildConstant
Builds a constant and stores its result in a TempReg.
@ GIR_AddImplicitUse
Add an implicit register use to the specified instruction.
@ GIR_Coverage
Increment the rule coverage counter.
@ GIR_MergeMemOperands
Merge all memory operands into instruction.
@ GIM_CheckImmOperandPredicate
Check an immediate predicate on the specified instruction.
@ GIM_CheckAtomicOrderingWeakerThan
@ GIR_SetMIFlags
Set or unset a MIFlag on an instruction.
@ GIM_CheckIntrinsicID
Check the operand is a specific intrinsic ID.
@ GIM_CheckConstantInt
Check the operand is a specific integer.
@ GIM_SwitchTypeShape
Switch over the shape of an LLT on the specified instruction operand.
@ GIR_RootToRootCopy
GIR_Copy but with both New/OldInsnIDs omitted and defaulting to zero.
@ GIR_ComplexSubOperandSubRegRenderer
Render subregisters of suboperands of complex operands to the specified instruction.
@ GIM_RecordInsnIgnoreCopies
@ GIR_CustomOperandRenderer
Render operands to the specified instruction using a custom function, reading from a specific operand...
@ GIR_ConstrainSelectedInstOperands
Constrain an instructions operands according to the instruction description.
@ GIM_CheckCxxInsnPredicate
Check a generic C++ instruction predicate.
@ GIM_CheckSimplePredicate
Check a trivial predicate which takes no arguments.
SmallDenseMap< uint64_t, unsigned, 64 > TypeIDMap
ExecInfoTy(const LLT *TypeObjects, size_t NumTypeObjects, const PredicateBitset *FeatureBitsets, const ComplexMatcherMemFn *ComplexPredicates, const CustomRendererFn *CustomRenderers)
const ComplexMatcherMemFn * ComplexPredicates
std::array< const MachineOperand *, 3 > RecordedOperands
Named operands that predicate with 'let PredicateCodeUsesOperands = 1' referenced in its argument lis...
SmallVector< LLT, 4 > RecordedTypes
Types extracted from an instruction's operand.
LLVM_ABI MatcherState(unsigned MaxRenderers)
DenseMap< unsigned, Register > TempRegisters
std::vector< ComplexRendererFns::value_type > Renderers