LLVM 19.0.0git
LanaiISelLowering.h
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1//===-- LanaiISelLowering.h - Lanai DAG Lowering Interface -....-*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that Lanai uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
15#define LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
16
17#include "Lanai.h"
18#include "LanaiRegisterInfo.h"
21
22namespace llvm {
23namespace LanaiISD {
24enum {
26
28
29 // Return with a glue operand. Operand 0 is the chain operand.
31
32 // CALL - These operations represent an abstract call instruction, which
33 // includes a bunch of information.
35
36 // SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
37 // is condition code and operand 4 is flag operand.
39
40 // SETCC - Store the conditional code to a register.
42
43 // SET_FLAG - Set flag compare.
45
46 // SUBBF - Subtract with borrow that sets flags.
48
49 // BR_CC - Used to glue together a conditional branch and comparison
51
52 // Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
53 // and TargetGlobalAddress.
55
56 // Get the Higher/Lower 16 bits from a 32-bit immediate.
59
60 // Small 21-bit immediate in global memory.
61 SMALL
62};
63} // namespace LanaiISD
64
65class LanaiSubtarget;
66
68public:
70
71 // LowerOperation - Provide custom lowering hooks for some operations.
72 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
73
74 // getTargetNodeName - This method returns the name of a target specific
75 // DAG node.
76 const char *getTargetNodeName(unsigned Opcode) const override;
77
92
94 bool IsVarArg,
96 LLVMContext &Context) const override;
97
98 Register getRegisterByName(const char *RegName, LLT VT,
99 const MachineFunction &MF) const override;
100 std::pair<unsigned, const TargetRegisterClass *>
102 StringRef Constraint, MVT VT) const override;
105 const char *Constraint) const override;
107 std::vector<SDValue> &Ops,
108 SelectionDAG &DAG) const override;
109
110 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
111
113 const APInt &DemandedElts,
114 const SelectionDAG &DAG,
115 unsigned Depth = 0) const override;
116
117private:
118 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
119 CallingConv::ID CallConv, bool IsVarArg,
120 bool IsTailCall,
122 const SmallVectorImpl<SDValue> &OutVals,
124 const SDLoc &dl, SelectionDAG &DAG,
125 SmallVectorImpl<SDValue> &InVals) const;
126
127 SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
128 bool IsVarArg,
130 const SDLoc &DL, SelectionDAG &DAG,
131 SmallVectorImpl<SDValue> &InVals) const;
132
133 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
134 CallingConv::ID CallConv, bool IsVarArg,
136 const SDLoc &DL, SelectionDAG &DAG,
137 SmallVectorImpl<SDValue> &InVals) const;
138
140 SmallVectorImpl<SDValue> &InVals) const override;
141
142 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
143 bool IsVarArg,
145 const SDLoc &DL, SelectionDAG &DAG,
146 SmallVectorImpl<SDValue> &InVals) const override;
147
148 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
150 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
151 SelectionDAG &DAG) const override;
152
153 const LanaiRegisterInfo *TRI;
154};
155} // namespace llvm
156
157#endif // LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define RegName(no)
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
Definition: APInt.h:78
This class represents an Operation in the Expression.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override
Examine constraint string and operand type and determine a weight value.
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Machine Value Type.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:227
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1451
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
#define N
This contains information for each constraint that we are lowering.
This structure contains all information that is necessary for lowering calls.