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LanaiISelLowering.h
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1 //===-- LanaiISelLowering.h - Lanai DAG Lowering Interface -....-*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that Lanai uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
15 #define LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
16 
17 #include "Lanai.h"
18 #include "LanaiRegisterInfo.h"
21 
22 namespace llvm {
23 namespace LanaiISD {
24 enum {
26 
28 
29  // Return with a flag operand. Operand 0 is the chain operand.
31 
32  // CALL - These operations represent an abstract call instruction, which
33  // includes a bunch of information.
35 
36  // SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
37  // is condition code and operand 4 is flag operand.
39 
40  // SETCC - Store the conditional code to a register.
42 
43  // SET_FLAG - Set flag compare.
45 
46  // SUBBF - Subtract with borrow that sets flags.
48 
49  // BR_CC - Used to glue together a conditional branch and comparison
51 
52  // Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
53  // and TargetGlobalAddress.
55 
56  // Get the Higher/Lower 16 bits from a 32-bit immediate.
57  HI,
58  LO,
59 
60  // Small 21-bit immediate in global memory.
62 };
63 } // namespace LanaiISD
64 
65 class LanaiSubtarget;
66 
68 public:
69  LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI);
70 
71  // LowerOperation - Provide custom lowering hooks for some operations.
72  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
73 
74  // getTargetNodeName - This method returns the name of a target specific
75  // DAG node.
76  const char *getTargetNodeName(unsigned Opcode) const override;
77 
85  SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
92 
93  Register getRegisterByName(const char *RegName, LLT VT,
94  const MachineFunction &MF) const override;
95  std::pair<unsigned, const TargetRegisterClass *>
97  StringRef Constraint, MVT VT) const override;
100  const char *Constraint) const override;
101  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
102  std::vector<SDValue> &Ops,
103  SelectionDAG &DAG) const override;
104 
105  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
106 
108  const APInt &DemandedElts,
109  const SelectionDAG &DAG,
110  unsigned Depth = 0) const override;
111 
112 private:
113  SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
114  CallingConv::ID CallConv, bool IsVarArg,
115  bool IsTailCall,
117  const SmallVectorImpl<SDValue> &OutVals,
119  const SDLoc &dl, SelectionDAG &DAG,
120  SmallVectorImpl<SDValue> &InVals) const;
121 
122  SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
123  bool IsVarArg,
125  const SDLoc &DL, SelectionDAG &DAG,
126  SmallVectorImpl<SDValue> &InVals) const;
127 
128  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
129  CallingConv::ID CallConv, bool IsVarArg,
131  const SDLoc &DL, SelectionDAG &DAG,
132  SmallVectorImpl<SDValue> &InVals) const;
133 
135  SmallVectorImpl<SDValue> &InVals) const override;
136 
137  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
138  bool IsVarArg,
140  const SDLoc &DL, SelectionDAG &DAG,
141  SmallVectorImpl<SDValue> &InVals) const override;
142 
143  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
145  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
146  SelectionDAG &DAG) const override;
147 
148  const LanaiRegisterInfo *TRI;
149 };
150 } // namespace llvm
151 
152 #endif // LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
llvm::LanaiTargetLowering::LowerBR_CC
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:866
llvm::LanaiTargetLowering::LowerBlockAddress
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1192
llvm
Definition: AllocatorList.h:23
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::LanaiTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: LanaiISelLowering.cpp:175
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:34
llvm::LanaiTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: LanaiISelLowering.cpp:1470
llvm::LanaiISD::ADJDYNALLOC
@ ADJDYNALLOC
Definition: LanaiISelLowering.h:27
llvm::LanaiTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: LanaiISelLowering.cpp:284
llvm::LanaiTargetLowering::LowerSHL_PARTS
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1235
Lanai.h
SelectionDAG.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
LanaiRegisterInfo.h
TargetLowering.h
llvm::LanaiISD::SETCC
@ SETCC
Definition: LanaiISelLowering.h:41
llvm::LanaiISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: LanaiISelLowering.h:25
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::LanaiTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: LanaiISelLowering.cpp:1094
llvm::LanaiTargetLowering::LowerMUL
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:883
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3143
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3491
llvm::LanaiISD::SUBBF
@ SUBBF
Definition: LanaiISelLowering.h:47
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::LanaiTargetLowering
Definition: LanaiISelLowering.h:67
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::LanaiISD::LO
@ LO
Definition: LanaiISelLowering.h:58
llvm::LanaiTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: LanaiISelLowering.cpp:236
llvm::LanaiTargetLowering::LowerVASTART
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1002
llvm::LanaiISD::Wrapper
@ Wrapper
Definition: LanaiISelLowering.h:54
llvm::LanaiISD::SET_FLAG
@ SET_FLAG
Definition: LanaiISelLowering.h:44
llvm::LanaiISD::RET_FLAG
@ RET_FLAG
Definition: LanaiISelLowering.h:30
llvm::LanaiTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: LanaiISelLowering.cpp:215
llvm::LanaiISD::BR_CC
@ BR_CC
Definition: LanaiISelLowering.h:50
llvm::LanaiTargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: LanaiISelLowering.cpp:255
llvm::TargetLowering::AsmOperandInfo
This contains information for each constraint that we are lowering.
Definition: TargetLowering.h:4129
llvm::LanaiTargetLowering::LowerGlobalAddress
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1158
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3694
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::LanaiISD::HI
@ HI
Definition: LanaiISelLowering.h:57
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::LanaiTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: LanaiISelLowering.cpp:1488
llvm::LanaiSubtarget
Definition: LanaiSubtarget.h:29
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::LanaiRegisterInfo
Definition: LanaiRegisterInfo.h:23
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1235
llvm::LanaiTargetLowering::LowerConstantPool
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1125
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::LanaiTargetLowering::LowerSRL_PARTS
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1284
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:205
llvm::LanaiISD::SELECT_CC
@ SELECT_CC
Definition: LanaiISelLowering.h:38
llvm::KnownBits
Definition: KnownBits.h:23
llvm::LanaiISD::SMALL
@ SMALL
Definition: LanaiISelLowering.h:61
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4112
llvm::LanaiTargetLowering::LowerRETURNADDR
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1052
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::LanaiTargetLowering::LowerSETCC
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:969
llvm::LanaiTargetLowering::LanaiTargetLowering
LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI)
Definition: LanaiISelLowering.cpp:73
N
#define N
llvm::LanaiTargetLowering::LowerJumpTable
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1208
llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1017
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
RegName
#define RegName(no)
llvm::LanaiISD::CALL
@ CALL
Definition: LanaiISelLowering.h:34
llvm::LanaiTargetLowering::LowerFRAMEADDR
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1075
llvm::LanaiTargetLowering::LowerSELECT_CC
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:983
llvm::LLT
Definition: LowLevelTypeImpl.h:40