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LanaiISelLowering.cpp
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1 //===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the LanaiTargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "LanaiISelLowering.h"
14 #include "Lanai.h"
15 #include "LanaiCondCode.h"
17 #include "LanaiSubtarget.h"
18 #include "LanaiTargetObjectFile.h"
20 #include "llvm/ADT/APInt.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/StringSwitch.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalValue.h"
39 #include "llvm/Support/Casting.h"
40 #include "llvm/Support/CodeGen.h"
42 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/KnownBits.h"
49 #include <cassert>
50 #include <cmath>
51 #include <cstdint>
52 #include <cstdlib>
53 #include <utility>
54 
55 #define DEBUG_TYPE "lanai-lower"
56 
57 using namespace llvm;
58 
59 // Limit on number of instructions the lowered multiplication may have before a
60 // call to the library function should be generated instead. The threshold is
61 // currently set to 14 as this was the smallest threshold that resulted in all
62 // constant multiplications being lowered. A threshold of 5 covered all cases
63 // except for one multiplication which required 14. mulsi3 requires 16
64 // instructions (including the prologue and epilogue but excluding instructions
65 // at call site). Until we can inline mulsi3, generating at most 14 instructions
66 // will be faster than invoking mulsi3.
68  "lanai-constant-mul-threshold", cl::Hidden,
69  cl::desc("Maximum number of instruction to generate when lowering constant "
70  "multiplication instead of calling library function [default=14]"),
71  cl::init(14));
72 
74  const LanaiSubtarget &STI)
75  : TargetLowering(TM) {
76  // Set up the register classes.
77  addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
78 
79  // Compute derived properties from the register classes
80  TRI = STI.getRegisterInfo();
82 
84 
91 
96 
100 
105 
112 
118 
124 
129 
133 
134  // Extended load operations for i1 types must be promoted
135  for (MVT VT : MVT::integer_valuetypes()) {
139  }
140 
146 
147  // Function alignments
150 
151  setJumpIsExpensive(true);
152 
153  // TODO: Setting the minimum jump table entries needed before a
154  // switch is transformed to a jump table to 100 to avoid creating jump tables
155  // as this was causing bad performance compared to a large group of if
156  // statements. Re-evaluate this on new benchmarks.
158 
159  // Use fast calling convention for library functions.
160  for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I) {
162  }
163 
164  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
166  MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
168  MaxStoresPerMemmove = 16; // For @llvm.memmove -> sequence of stores
170 
171  // Booleans always contain 0 or 1.
173 }
174 
176  SelectionDAG &DAG) const {
177  switch (Op.getOpcode()) {
178  case ISD::MUL:
179  return LowerMUL(Op, DAG);
180  case ISD::BR_CC:
181  return LowerBR_CC(Op, DAG);
182  case ISD::ConstantPool:
183  return LowerConstantPool(Op, DAG);
184  case ISD::GlobalAddress:
185  return LowerGlobalAddress(Op, DAG);
186  case ISD::BlockAddress:
187  return LowerBlockAddress(Op, DAG);
188  case ISD::JumpTable:
189  return LowerJumpTable(Op, DAG);
190  case ISD::SELECT_CC:
191  return LowerSELECT_CC(Op, DAG);
192  case ISD::SETCC:
193  return LowerSETCC(Op, DAG);
194  case ISD::SHL_PARTS:
195  return LowerSHL_PARTS(Op, DAG);
196  case ISD::SRL_PARTS:
197  return LowerSRL_PARTS(Op, DAG);
198  case ISD::VASTART:
199  return LowerVASTART(Op, DAG);
201  return LowerDYNAMIC_STACKALLOC(Op, DAG);
202  case ISD::RETURNADDR:
203  return LowerRETURNADDR(Op, DAG);
204  case ISD::FRAMEADDR:
205  return LowerFRAMEADDR(Op, DAG);
206  default:
207  llvm_unreachable("unimplemented operand");
208  }
209 }
210 
211 //===----------------------------------------------------------------------===//
212 // Lanai Inline Assembly Support
213 //===----------------------------------------------------------------------===//
214 
216  const char *RegName, LLT /*VT*/,
217  const MachineFunction & /*MF*/) const {
218  // Only unallocatable registers should be matched here.
220  .Case("pc", Lanai::PC)
221  .Case("sp", Lanai::SP)
222  .Case("fp", Lanai::FP)
223  .Case("rr1", Lanai::RR1)
224  .Case("r10", Lanai::R10)
225  .Case("rr2", Lanai::RR2)
226  .Case("r11", Lanai::R11)
227  .Case("rca", Lanai::RCA)
228  .Default(0);
229 
230  if (Reg)
231  return Reg;
232  report_fatal_error("Invalid register name global variable");
233 }
234 
235 std::pair<unsigned, const TargetRegisterClass *>
237  StringRef Constraint,
238  MVT VT) const {
239  if (Constraint.size() == 1)
240  // GCC Constraint Letters
241  switch (Constraint[0]) {
242  case 'r': // GENERAL_REGS
243  return std::make_pair(0U, &Lanai::GPRRegClass);
244  default:
245  break;
246  }
247 
248  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
249 }
250 
251 // Examine constraint type and operand type and determine a weight value.
252 // This object must already have been set up with the operand type
253 // and the current alternative constraint selected.
256  AsmOperandInfo &Info, const char *Constraint) const {
257  ConstraintWeight Weight = CW_Invalid;
258  Value *CallOperandVal = Info.CallOperandVal;
259  // If we don't have a value, we can't do a match,
260  // but allow it at the lowest weight.
261  if (CallOperandVal == nullptr)
262  return CW_Default;
263  // Look at the constraint type.
264  switch (*Constraint) {
265  case 'I': // signed 16 bit immediate
266  case 'J': // integer zero
267  case 'K': // unsigned 16 bit immediate
268  case 'L': // immediate in the range 0 to 31
269  case 'M': // signed 32 bit immediate where lower 16 bits are 0
270  case 'N': // signed 26 bit immediate
271  case 'O': // integer zero
272  if (isa<ConstantInt>(CallOperandVal))
273  Weight = CW_Constant;
274  break;
275  default:
277  break;
278  }
279  return Weight;
280 }
281 
282 // LowerAsmOperandForConstraint - Lower the specified operand into the Ops
283 // vector. If it is invalid, don't add anything to Ops.
285  SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
286  SelectionDAG &DAG) const {
287  SDValue Result(nullptr, 0);
288 
289  // Only support length 1 constraints for now.
290  if (Constraint.length() > 1)
291  return;
292 
293  char ConstraintLetter = Constraint[0];
294  switch (ConstraintLetter) {
295  case 'I': // Signed 16 bit constant
296  // If this fails, the parent routine will give an error
297  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
298  if (isInt<16>(C->getSExtValue())) {
299  Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
300  Op.getValueType());
301  break;
302  }
303  }
304  return;
305  case 'J': // integer zero
306  case 'O':
307  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
308  if (C->getZExtValue() == 0) {
309  Result = DAG.getTargetConstant(0, SDLoc(C), Op.getValueType());
310  break;
311  }
312  }
313  return;
314  case 'K': // unsigned 16 bit immediate
315  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
316  if (isUInt<16>(C->getZExtValue())) {
317  Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
318  Op.getValueType());
319  break;
320  }
321  }
322  return;
323  case 'L': // immediate in the range 0 to 31
324  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
325  if (C->getZExtValue() <= 31) {
326  Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(C),
327  Op.getValueType());
328  break;
329  }
330  }
331  return;
332  case 'M': // signed 32 bit immediate where lower 16 bits are 0
333  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
334  int64_t Val = C->getSExtValue();
335  if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)) {
336  Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
337  break;
338  }
339  }
340  return;
341  case 'N': // signed 26 bit immediate
342  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
343  int64_t Val = C->getSExtValue();
344  if ((Val >= -33554432) && (Val <= 33554431)) {
345  Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
346  break;
347  }
348  }
349  return;
350  default:
351  break; // This will fall through to the generic implementation
352  }
353 
354  if (Result.getNode()) {
355  Ops.push_back(Result);
356  return;
357  }
358 
359  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
360 }
361 
362 //===----------------------------------------------------------------------===//
363 // Calling Convention Implementation
364 //===----------------------------------------------------------------------===//
365 
366 #include "LanaiGenCallingConv.inc"
367 
368 static unsigned NumFixedArgs;
369 static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
370  CCValAssign::LocInfo LocInfo,
371  ISD::ArgFlagsTy ArgFlags, CCState &State) {
372  // Handle fixed arguments with default CC.
373  // Note: Both the default and fast CC handle VarArg the same and hence the
374  // calling convention of the function is not considered here.
375  if (ValNo < NumFixedArgs) {
376  return CC_Lanai32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
377  }
378 
379  // Promote i8/i16 args to i32
380  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
381  LocVT = MVT::i32;
382  if (ArgFlags.isSExt())
383  LocInfo = CCValAssign::SExt;
384  else if (ArgFlags.isZExt())
385  LocInfo = CCValAssign::ZExt;
386  else
387  LocInfo = CCValAssign::AExt;
388  }
389 
390  // VarArgs get passed on stack
391  unsigned Offset = State.AllocateStack(4, Align(4));
392  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
393  return false;
394 }
395 
396 SDValue LanaiTargetLowering::LowerFormalArguments(
397  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
399  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
400  switch (CallConv) {
401  case CallingConv::C:
402  case CallingConv::Fast:
403  return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals);
404  default:
405  report_fatal_error("Unsupported calling convention");
406  }
407 }
408 
409 SDValue LanaiTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
410  SmallVectorImpl<SDValue> &InVals) const {
411  SelectionDAG &DAG = CLI.DAG;
412  SDLoc &DL = CLI.DL;
414  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
416  SDValue Chain = CLI.Chain;
417  SDValue Callee = CLI.Callee;
418  bool &IsTailCall = CLI.IsTailCall;
419  CallingConv::ID CallConv = CLI.CallConv;
420  bool IsVarArg = CLI.IsVarArg;
421 
422  // Lanai target does not yet support tail call optimization.
423  IsTailCall = false;
424 
425  switch (CallConv) {
426  case CallingConv::Fast:
427  case CallingConv::C:
428  return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs,
429  OutVals, Ins, DL, DAG, InVals);
430  default:
431  report_fatal_error("Unsupported calling convention");
432  }
433 }
434 
435 // LowerCCCArguments - transform physical registers into virtual registers and
436 // generate load operations for arguments places on the stack.
437 SDValue LanaiTargetLowering::LowerCCCArguments(
438  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
440  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
442  MachineFrameInfo &MFI = MF.getFrameInfo();
443  MachineRegisterInfo &RegInfo = MF.getRegInfo();
445 
446  // Assign locations to all of the incoming arguments.
448  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
449  *DAG.getContext());
450  if (CallConv == CallingConv::Fast) {
451  CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32_Fast);
452  } else {
453  CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32);
454  }
455 
456  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
457  CCValAssign &VA = ArgLocs[i];
458  if (VA.isRegLoc()) {
459  // Arguments passed in registers
460  EVT RegVT = VA.getLocVT();
461  switch (RegVT.getSimpleVT().SimpleTy) {
462  case MVT::i32: {
463  Register VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass);
464  RegInfo.addLiveIn(VA.getLocReg(), VReg);
465  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
466 
467  // If this is an 8/16-bit value, it is really passed promoted to 32
468  // bits. Insert an assert[sz]ext to capture this, then truncate to the
469  // right size.
470  if (VA.getLocInfo() == CCValAssign::SExt)
471  ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
472  DAG.getValueType(VA.getValVT()));
473  else if (VA.getLocInfo() == CCValAssign::ZExt)
474  ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
475  DAG.getValueType(VA.getValVT()));
476 
477  if (VA.getLocInfo() != CCValAssign::Full)
478  ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
479 
480  InVals.push_back(ArgValue);
481  break;
482  }
483  default:
484  LLVM_DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: "
485  << RegVT.getEVTString() << "\n");
486  llvm_unreachable("unhandled argument type");
487  }
488  } else {
489  // Only arguments passed on the stack should make it here.
490  assert(VA.isMemLoc());
491  // Load the argument to a virtual register
492  unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
493  // Check that the argument fits in stack slot
494  if (ObjSize > 4) {
495  errs() << "LowerFormalArguments Unhandled argument type: "
496  << EVT(VA.getLocVT()).getEVTString() << "\n";
497  }
498  // Create the frame index object for this incoming parameter...
499  int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
500 
501  // Create the SelectionDAG nodes corresponding to a load
502  // from this parameter
503  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
504  InVals.push_back(DAG.getLoad(
505  VA.getLocVT(), DL, Chain, FIN,
507  }
508  }
509 
510  // The Lanai ABI for returning structs by value requires that we copy
511  // the sret argument into rv for the return. Save the argument into
512  // a virtual register so that we can access it from the return points.
513  if (MF.getFunction().hasStructRetAttr()) {
514  unsigned Reg = LanaiMFI->getSRetReturnReg();
515  if (!Reg) {
517  LanaiMFI->setSRetReturnReg(Reg);
518  }
519  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
520  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
521  }
522 
523  if (IsVarArg) {
524  // Record the frame index of the first variable argument
525  // which is a value necessary to VASTART.
526  int FI = MFI.CreateFixedObject(4, CCInfo.getNextStackOffset(), true);
527  LanaiMFI->setVarArgsFrameIndex(FI);
528  }
529 
530  return Chain;
531 }
532 
534  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
537  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
538 
539  return CCInfo.CheckReturn(Outs, RetCC_Lanai32);
540 }
541 
542 SDValue
543 LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
544  bool IsVarArg,
546  const SmallVectorImpl<SDValue> &OutVals,
547  const SDLoc &DL, SelectionDAG &DAG) const {
548  // CCValAssign - represent the assignment of the return value to a location
550 
551  // CCState - Info about the registers and stack slot.
552  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
553  *DAG.getContext());
554 
555  // Analize return values.
556  CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);
557 
558  SDValue Flag;
559  SmallVector<SDValue, 4> RetOps(1, Chain);
560 
561  // Copy the result values into the output registers.
562  for (unsigned i = 0; i != RVLocs.size(); ++i) {
563  CCValAssign &VA = RVLocs[i];
564  assert(VA.isRegLoc() && "Can only return in registers!");
565 
566  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
567 
568  // Guarantee that all emitted copies are stuck together with flags.
569  Flag = Chain.getValue(1);
570  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
571  }
572 
573  // The Lanai ABI for returning structs by value requires that we copy
574  // the sret argument into rv for the return. We saved the argument into
575  // a virtual register in the entry block, so now we copy the value out
576  // and into rv.
580  unsigned Reg = LanaiMFI->getSRetReturnReg();
581  assert(Reg &&
582  "SRetReturnReg should have been set in LowerFormalArguments().");
583  SDValue Val =
584  DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
585 
586  Chain = DAG.getCopyToReg(Chain, DL, Lanai::RV, Val, Flag);
587  Flag = Chain.getValue(1);
588  RetOps.push_back(
589  DAG.getRegister(Lanai::RV, getPointerTy(DAG.getDataLayout())));
590  }
591 
592  RetOps[0] = Chain; // Update chain
593 
594  unsigned Opc = LanaiISD::RET_FLAG;
595  if (Flag.getNode())
596  RetOps.push_back(Flag);
597 
598  // Return Void
599  return DAG.getNode(Opc, DL, MVT::Other,
600  ArrayRef<SDValue>(&RetOps[0], RetOps.size()));
601 }
602 
603 // LowerCCCCallTo - functions arguments are copied from virtual regs to
604 // (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
605 SDValue LanaiTargetLowering::LowerCCCCallTo(
606  SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg,
607  bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs,
608  const SmallVectorImpl<SDValue> &OutVals,
610  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
611  // Analyze operands of the call, assigning locations to each operand.
613  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
614  *DAG.getContext());
615  GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
617 
618  NumFixedArgs = 0;
619  if (IsVarArg && G) {
620  const Function *CalleeFn = dyn_cast<Function>(G->getGlobal());
621  if (CalleeFn)
622  NumFixedArgs = CalleeFn->getFunctionType()->getNumParams();
623  }
624  if (NumFixedArgs)
625  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg);
626  else {
627  if (CallConv == CallingConv::Fast)
628  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);
629  else
630  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32);
631  }
632 
633  // Get a count of how many bytes are to be pushed on the stack.
634  unsigned NumBytes = CCInfo.getNextStackOffset();
635 
636  // Create local copies for byval args.
637  SmallVector<SDValue, 8> ByValArgs;
638  for (unsigned I = 0, E = Outs.size(); I != E; ++I) {
639  ISD::ArgFlagsTy Flags = Outs[I].Flags;
640  if (!Flags.isByVal())
641  continue;
642 
643  SDValue Arg = OutVals[I];
644  unsigned Size = Flags.getByValSize();
645  Align Alignment = Flags.getNonZeroByValAlign();
646 
647  int FI = MFI.CreateStackObject(Size, Alignment, false);
648  SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
649  SDValue SizeNode = DAG.getConstant(Size, DL, MVT::i32);
650 
651  Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment,
652  /*IsVolatile=*/false,
653  /*AlwaysInline=*/false,
654  /*isTailCall=*/false, MachinePointerInfo(),
656  ByValArgs.push_back(FIPtr);
657  }
658 
659  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
660 
662  SmallVector<SDValue, 12> MemOpChains;
664 
665  // Walk the register/memloc assignments, inserting copies/loads.
666  for (unsigned I = 0, J = 0, E = ArgLocs.size(); I != E; ++I) {
667  CCValAssign &VA = ArgLocs[I];
668  SDValue Arg = OutVals[I];
669  ISD::ArgFlagsTy Flags = Outs[I].Flags;
670 
671  // Promote the value if needed.
672  switch (VA.getLocInfo()) {
673  case CCValAssign::Full:
674  break;
675  case CCValAssign::SExt:
676  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
677  break;
678  case CCValAssign::ZExt:
679  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
680  break;
681  case CCValAssign::AExt:
682  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
683  break;
684  default:
685  llvm_unreachable("Unknown loc info!");
686  }
687 
688  // Use local copy if it is a byval arg.
689  if (Flags.isByVal())
690  Arg = ByValArgs[J++];
691 
692  // Arguments that can be passed on register must be kept at RegsToPass
693  // vector
694  if (VA.isRegLoc()) {
695  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
696  } else {
697  assert(VA.isMemLoc());
698 
699  if (StackPtr.getNode() == nullptr)
700  StackPtr = DAG.getCopyFromReg(Chain, DL, Lanai::SP,
701  getPointerTy(DAG.getDataLayout()));
702 
703  SDValue PtrOff =
704  DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
706 
707  MemOpChains.push_back(
708  DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
709  }
710  }
711 
712  // Transform all store nodes into one single node because all store nodes are
713  // independent of each other.
714  if (!MemOpChains.empty())
715  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
716  ArrayRef<SDValue>(&MemOpChains[0], MemOpChains.size()));
717 
718  SDValue InFlag;
719 
720  // Build a sequence of copy-to-reg nodes chained together with token chain and
721  // flag operands which copy the outgoing args into registers. The InFlag in
722  // necessary since all emitted instructions must be stuck together.
723  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
724  Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
725  RegsToPass[I].second, InFlag);
726  InFlag = Chain.getValue(1);
727  }
728 
729  // If the callee is a GlobalAddress node (quite common, every direct call is)
730  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
731  // Likewise ExternalSymbol -> TargetExternalSymbol.
732  uint8_t OpFlag = LanaiII::MO_NO_FLAG;
733  if (G) {
735  G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, OpFlag);
736  } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
738  E->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlag);
739  }
740 
741  // Returns a chain & a flag for retval copy to use.
742  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
744  Ops.push_back(Chain);
745  Ops.push_back(Callee);
746 
747  // Add a register mask operand representing the call-preserved registers.
748  // TODO: Should return-twice functions be handled?
749  const uint32_t *Mask =
750  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
751  assert(Mask && "Missing call preserved mask for calling convention");
752  Ops.push_back(DAG.getRegisterMask(Mask));
753 
754  // Add argument registers to the end of the list so that they are
755  // known live into the call.
756  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
757  Ops.push_back(DAG.getRegister(RegsToPass[I].first,
758  RegsToPass[I].second.getValueType()));
759 
760  if (InFlag.getNode())
761  Ops.push_back(InFlag);
762 
763  Chain = DAG.getNode(LanaiISD::CALL, DL, NodeTys,
764  ArrayRef<SDValue>(&Ops[0], Ops.size()));
765  InFlag = Chain.getValue(1);
766 
767  // Create the CALLSEQ_END node.
768  Chain = DAG.getCALLSEQ_END(
769  Chain,
770  DAG.getConstant(NumBytes, DL, getPointerTy(DAG.getDataLayout()), true),
771  DAG.getConstant(0, DL, getPointerTy(DAG.getDataLayout()), true), InFlag,
772  DL);
773  InFlag = Chain.getValue(1);
774 
775  // Handle result values, copying them out of physregs into vregs that we
776  // return.
777  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
778  InVals);
779 }
780 
781 // LowerCallResult - Lower the result values of a call into the
782 // appropriate copies out of appropriate physical registers.
783 SDValue LanaiTargetLowering::LowerCallResult(
784  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
786  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
787  // Assign locations to each value returned by this call.
789  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
790  *DAG.getContext());
791 
792  CCInfo.AnalyzeCallResult(Ins, RetCC_Lanai32);
793 
794  // Copy all of the result registers out of their specified physreg.
795  for (unsigned I = 0; I != RVLocs.size(); ++I) {
796  Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
797  RVLocs[I].getValVT(), InFlag)
798  .getValue(1);
799  InFlag = Chain.getValue(2);
800  InVals.push_back(Chain.getValue(0));
801  }
802 
803  return Chain;
804 }
805 
806 //===----------------------------------------------------------------------===//
807 // Custom Lowerings
808 //===----------------------------------------------------------------------===//
809 
811  SDValue &RHS, SelectionDAG &DAG) {
812  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
813 
814  // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
815  // SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h)
816  // and Lanai only supports integer comparisons, so only provide definitions
817  // for them.
818  switch (SetCCOpcode) {
819  case ISD::SETEQ:
820  return LPCC::ICC_EQ;
821  case ISD::SETGT:
822  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
823  if (RHSC->getZExtValue() == 0xFFFFFFFF) {
824  // X > -1 -> X >= 0 -> is_plus(X)
825  RHS = DAG.getConstant(0, DL, RHS.getValueType());
826  return LPCC::ICC_PL;
827  }
828  return LPCC::ICC_GT;
829  case ISD::SETUGT:
830  return LPCC::ICC_UGT;
831  case ISD::SETLT:
832  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
833  if (RHSC->getZExtValue() == 0)
834  // X < 0 -> is_minus(X)
835  return LPCC::ICC_MI;
836  return LPCC::ICC_LT;
837  case ISD::SETULT:
838  return LPCC::ICC_ULT;
839  case ISD::SETLE:
840  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
841  if (RHSC->getZExtValue() == 0xFFFFFFFF) {
842  // X <= -1 -> X < 0 -> is_minus(X)
843  RHS = DAG.getConstant(0, DL, RHS.getValueType());
844  return LPCC::ICC_MI;
845  }
846  return LPCC::ICC_LE;
847  case ISD::SETULE:
848  return LPCC::ICC_ULE;
849  case ISD::SETGE:
850  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
851  if (RHSC->getZExtValue() == 0)
852  // X >= 0 -> is_plus(X)
853  return LPCC::ICC_PL;
854  return LPCC::ICC_GE;
855  case ISD::SETUGE:
856  return LPCC::ICC_UGE;
857  case ISD::SETNE:
858  return LPCC::ICC_NE;
859  case ISD::SETONE:
860  case ISD::SETUNE:
861  case ISD::SETOGE:
862  case ISD::SETOLE:
863  case ISD::SETOLT:
864  case ISD::SETOGT:
865  case ISD::SETOEQ:
866  case ISD::SETUEQ:
867  case ISD::SETO:
868  case ISD::SETUO:
869  llvm_unreachable("Unsupported comparison.");
870  default:
871  llvm_unreachable("Unknown integer condition code!");
872  }
873 }
874 
876  SDValue Chain = Op.getOperand(0);
877  SDValue Cond = Op.getOperand(1);
878  SDValue LHS = Op.getOperand(2);
879  SDValue RHS = Op.getOperand(3);
880  SDValue Dest = Op.getOperand(4);
881  SDLoc DL(Op);
882 
883  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
884  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
885  SDValue Flag =
886  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
887 
888  return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
889  TargetCC, Flag);
890 }
891 
893  EVT VT = Op->getValueType(0);
894  if (VT != MVT::i32)
895  return SDValue();
896 
897  ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
898  if (!C)
899  return SDValue();
900 
901  int64_t MulAmt = C->getSExtValue();
902  int32_t HighestOne = -1;
903  uint32_t NonzeroEntries = 0;
904  int SignedDigit[32] = {0};
905 
906  // Convert to non-adjacent form (NAF) signed-digit representation.
907  // NAF is a signed-digit form where no adjacent digits are non-zero. It is the
908  // minimal Hamming weight representation of a number (on average 1/3 of the
909  // digits will be non-zero vs 1/2 for regular binary representation). And as
910  // the non-zero digits will be the only digits contributing to the instruction
911  // count, this is desirable. The next loop converts it to NAF (following the
912  // approach in 'Guide to Elliptic Curve Cryptography' [ISBN: 038795273X]) by
913  // choosing the non-zero coefficients such that the resulting quotient is
914  // divisible by 2 which will cause the next coefficient to be zero.
915  int64_t E = std::abs(MulAmt);
916  int S = (MulAmt < 0 ? -1 : 1);
917  int I = 0;
918  while (E > 0) {
919  int ZI = 0;
920  if (E % 2 == 1) {
921  ZI = 2 - (E % 4);
922  if (ZI != 0)
923  ++NonzeroEntries;
924  }
925  SignedDigit[I] = S * ZI;
926  if (SignedDigit[I] == 1)
927  HighestOne = I;
928  E = (E - ZI) / 2;
929  ++I;
930  }
931 
932  // Compute number of instructions required. Due to differences in lowering
933  // between the different processors this count is not exact.
934  // Start by assuming a shift and a add/sub for every non-zero entry (hence
935  // every non-zero entry requires 1 shift and 1 add/sub except for the first
936  // entry).
937  int32_t InstrRequired = 2 * NonzeroEntries - 1;
938  // Correct possible over-adding due to shift by 0 (which is not emitted).
939  if (std::abs(MulAmt) % 2 == 1)
940  --InstrRequired;
941  // Return if the form generated would exceed the instruction threshold.
942  if (InstrRequired > LanaiLowerConstantMulThreshold)
943  return SDValue();
944 
945  SDValue Res;
946  SDLoc DL(Op);
947  SDValue V = Op->getOperand(0);
948 
949  // Initialize the running sum. Set the running sum to the maximal shifted
950  // positive value (i.e., largest i such that zi == 1 and MulAmt has V<<i as a
951  // term NAF).
952  if (HighestOne == -1)
953  Res = DAG.getConstant(0, DL, MVT::i32);
954  else {
955  Res = DAG.getNode(ISD::SHL, DL, VT, V,
956  DAG.getConstant(HighestOne, DL, MVT::i32));
957  SignedDigit[HighestOne] = 0;
958  }
959 
960  // Assemble multiplication from shift, add, sub using NAF form and running
961  // sum.
962  for (unsigned int I = 0; I < sizeof(SignedDigit) / sizeof(SignedDigit[0]);
963  ++I) {
964  if (SignedDigit[I] == 0)
965  continue;
966 
967  // Shifted multiplicand (v<<i).
968  SDValue Op =
969  DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32));
970  if (SignedDigit[I] == 1)
971  Res = DAG.getNode(ISD::ADD, DL, VT, Res, Op);
972  else if (SignedDigit[I] == -1)
973  Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op);
974  }
975  return Res;
976 }
977 
979  SDValue LHS = Op.getOperand(0);
980  SDValue RHS = Op.getOperand(1);
981  SDValue Cond = Op.getOperand(2);
982  SDLoc DL(Op);
983 
984  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
985  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
986  SDValue Flag =
987  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
988 
989  return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
990 }
991 
993  SelectionDAG &DAG) const {
994  SDValue LHS = Op.getOperand(0);
995  SDValue RHS = Op.getOperand(1);
996  SDValue TrueV = Op.getOperand(2);
997  SDValue FalseV = Op.getOperand(3);
998  SDValue Cond = Op.getOperand(4);
999  SDLoc DL(Op);
1000 
1001  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
1002  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
1003  SDValue Flag =
1004  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
1005 
1006  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1007  return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC,
1008  Flag);
1009 }
1010 
1012  MachineFunction &MF = DAG.getMachineFunction();
1014 
1015  SDLoc DL(Op);
1016  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1017  getPointerTy(DAG.getDataLayout()));
1018 
1019  // vastart just stores the address of the VarArgsFrameIndex slot into the
1020  // memory location argument.
1021  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1022  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1023  MachinePointerInfo(SV));
1024 }
1025 
1027  SelectionDAG &DAG) const {
1028  SDValue Chain = Op.getOperand(0);
1029  SDValue Size = Op.getOperand(1);
1030  SDLoc DL(Op);
1031 
1033 
1034  // Get a reference to the stack pointer.
1035  SDValue StackPointer = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32);
1036 
1037  // Subtract the dynamic size from the actual stack size to
1038  // obtain the new stack size.
1039  SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size);
1040 
1041  // For Lanai, the outgoing memory arguments area should be on top of the
1042  // alloca area on the stack i.e., the outgoing memory arguments should be
1043  // at a lower address than the alloca area. Move the alloca area down the
1044  // stack by adding back the space reserved for outgoing arguments to SP
1045  // here.
1046  //
1047  // We do not know what the size of the outgoing args is at this point.
1048  // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
1049  // stack pointer. We replace this instruction with on that has the correct,
1050  // known offset in emitPrologue().
1051  SDValue ArgAdjust = DAG.getNode(LanaiISD::ADJDYNALLOC, DL, MVT::i32, Sub);
1052 
1053  // The Sub result contains the new stack start address, so it
1054  // must be placed in the stack pointer register.
1055  SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub);
1056 
1057  SDValue Ops[2] = {ArgAdjust, CopyChain};
1058  return DAG.getMergeValues(Ops, DL);
1059 }
1060 
1062  SelectionDAG &DAG) const {
1063  MachineFunction &MF = DAG.getMachineFunction();
1064  MachineFrameInfo &MFI = MF.getFrameInfo();
1065  MFI.setReturnAddressIsTaken(true);
1066 
1067  EVT VT = Op.getValueType();
1068  SDLoc DL(Op);
1069  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1070  if (Depth) {
1071  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1072  const unsigned Offset = -4;
1073  SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1074  DAG.getIntPtrConstant(Offset, DL));
1075  return DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1076  }
1077 
1078  // Return the link register, which contains the return address.
1079  // Mark it an implicit live-in.
1080  unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
1081  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
1082 }
1083 
1085  SelectionDAG &DAG) const {
1087  MFI.setFrameAddressIsTaken(true);
1088 
1089  EVT VT = Op.getValueType();
1090  SDLoc DL(Op);
1091  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Lanai::FP, VT);
1092  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1093  while (Depth--) {
1094  const unsigned Offset = -8;
1095  SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1096  DAG.getIntPtrConstant(Offset, DL));
1097  FrameAddr =
1098  DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1099  }
1100  return FrameAddr;
1101 }
1102 
1103 const char *LanaiTargetLowering::getTargetNodeName(unsigned Opcode) const {
1104  switch (Opcode) {
1105  case LanaiISD::ADJDYNALLOC:
1106  return "LanaiISD::ADJDYNALLOC";
1107  case LanaiISD::RET_FLAG:
1108  return "LanaiISD::RET_FLAG";
1109  case LanaiISD::CALL:
1110  return "LanaiISD::CALL";
1111  case LanaiISD::SELECT_CC:
1112  return "LanaiISD::SELECT_CC";
1113  case LanaiISD::SETCC:
1114  return "LanaiISD::SETCC";
1115  case LanaiISD::SUBBF:
1116  return "LanaiISD::SUBBF";
1117  case LanaiISD::SET_FLAG:
1118  return "LanaiISD::SET_FLAG";
1119  case LanaiISD::BR_CC:
1120  return "LanaiISD::BR_CC";
1121  case LanaiISD::Wrapper:
1122  return "LanaiISD::Wrapper";
1123  case LanaiISD::HI:
1124  return "LanaiISD::HI";
1125  case LanaiISD::LO:
1126  return "LanaiISD::LO";
1127  case LanaiISD::SMALL:
1128  return "LanaiISD::SMALL";
1129  default:
1130  return nullptr;
1131  }
1132 }
1133 
1135  SelectionDAG &DAG) const {
1136  SDLoc DL(Op);
1137  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1138  const Constant *C = N->getConstVal();
1139  const LanaiTargetObjectFile *TLOF =
1140  static_cast<const LanaiTargetObjectFile *>(
1142 
1143  // If the code model is small or constant will be placed in the small section,
1144  // then assume address will fit in 21-bits.
1146  TLOF->isConstantInSmallSection(DAG.getDataLayout(), C)) {
1148  C, MVT::i32, N->getAlign(), N->getOffset(), LanaiII::MO_NO_FLAG);
1149  return DAG.getNode(ISD::OR, DL, MVT::i32,
1150  DAG.getRegister(Lanai::R0, MVT::i32),
1152  } else {
1153  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1154  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1155 
1156  SDValue Hi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(),
1157  N->getOffset(), OpFlagHi);
1158  SDValue Lo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(),
1159  N->getOffset(), OpFlagLo);
1160  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1161  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1162  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1163  return Result;
1164  }
1165 }
1166 
1168  SelectionDAG &DAG) const {
1169  SDLoc DL(Op);
1170  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1171  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1172 
1173  const LanaiTargetObjectFile *TLOF =
1174  static_cast<const LanaiTargetObjectFile *>(
1176 
1177  // If the code model is small or global variable will be placed in the small
1178  // section, then assume address will fit in 21-bits.
1179  const GlobalObject *GO = GV->getAliaseeObject();
1180  if (TLOF->isGlobalInSmallSection(GO, getTargetMachine())) {
1183  return DAG.getNode(ISD::OR, DL, MVT::i32,
1184  DAG.getRegister(Lanai::R0, MVT::i32),
1186  } else {
1187  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1188  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1189 
1190  // Create the TargetGlobalAddress node, folding in the constant offset.
1192  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagHi);
1194  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagLo);
1195  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1196  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1197  return DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1198  }
1199 }
1200 
1202  SelectionDAG &DAG) const {
1203  SDLoc DL(Op);
1204  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1205 
1206  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1207  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1208 
1209  SDValue Hi = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagHi);
1210  SDValue Lo = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagLo);
1211  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1212  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1213  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1214  return Result;
1215 }
1216 
1218  SelectionDAG &DAG) const {
1219  SDLoc DL(Op);
1220  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1221 
1222  // If the code model is small assume address will fit in 21-bits.
1225  JT->getIndex(), getPointerTy(DAG.getDataLayout()), LanaiII::MO_NO_FLAG);
1226  return DAG.getNode(ISD::OR, DL, MVT::i32,
1227  DAG.getRegister(Lanai::R0, MVT::i32),
1229  } else {
1230  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1231  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1232 
1234  JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagHi);
1236  JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagLo);
1237  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1238  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1239  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1240  return Result;
1241  }
1242 }
1243 
1245  SelectionDAG &DAG) const {
1246  EVT VT = Op.getValueType();
1247  unsigned VTBits = VT.getSizeInBits();
1248  SDLoc dl(Op);
1249  assert(Op.getNumOperands() == 3 && "Unexpected SHL!");
1250  SDValue ShOpLo = Op.getOperand(0);
1251  SDValue ShOpHi = Op.getOperand(1);
1252  SDValue ShAmt = Op.getOperand(2);
1253 
1254  // Performs the following for (ShOpLo + (ShOpHi << 32)) << ShAmt:
1255  // LoBitsForHi = (ShAmt == 0) ? 0 : (ShOpLo >> (32-ShAmt))
1256  // HiBitsForHi = ShOpHi << ShAmt
1257  // Hi = (ShAmt >= 32) ? (ShOpLo << (ShAmt-32)) : (LoBitsForHi | HiBitsForHi)
1258  // Lo = (ShAmt >= 32) ? 0 : (ShOpLo << ShAmt)
1259  // return (Hi << 32) | Lo;
1260 
1261  SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1262  DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1263  SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1264 
1265  // If ShAmt == 0, we just calculated "(SRL ShOpLo, 32)" which is "undef". We
1266  // wanted 0, so CSEL it directly.
1267  SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1268  SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1269  LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi);
1270 
1271  SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1272  DAG.getConstant(VTBits, dl, MVT::i32));
1273  SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1274  SDValue HiForNormalShift =
1275  DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
1276 
1277  SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1278 
1279  SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE);
1280  SDValue Hi =
1281  DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift);
1282 
1283  // Lanai shifts of larger than register sizes are wrapped rather than
1284  // clamped, so we can't just emit "lo << b" if b is too big.
1285  SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1286  SDValue Lo = DAG.getSelect(
1287  dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift);
1288 
1289  SDValue Ops[2] = {Lo, Hi};
1290  return DAG.getMergeValues(Ops, dl);
1291 }
1292 
1294  SelectionDAG &DAG) const {
1295  MVT VT = Op.getSimpleValueType();
1296  unsigned VTBits = VT.getSizeInBits();
1297  SDLoc dl(Op);
1298  SDValue ShOpLo = Op.getOperand(0);
1299  SDValue ShOpHi = Op.getOperand(1);
1300  SDValue ShAmt = Op.getOperand(2);
1301 
1302  // Performs the following for a >> b:
1303  // unsigned r_high = a_high >> b;
1304  // r_high = (32 - b <= 0) ? 0 : r_high;
1305  //
1306  // unsigned r_low = a_low >> b;
1307  // r_low = (32 - b <= 0) ? r_high : r_low;
1308  // r_low = (b == 0) ? r_low : r_low | (a_high << (32 - b));
1309  // return (unsigned long long)r_high << 32 | r_low;
1310  // Note: This takes advantage of Lanai's shift behavior to avoid needing to
1311  // mask the shift amount.
1312 
1313  SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1314  SDValue NegatedPlus32 = DAG.getNode(
1315  ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1316  SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE);
1317 
1318  SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpHi, ShAmt);
1319  Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi);
1320 
1321  SDValue Lo = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpLo, ShAmt);
1322  Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo);
1323  SDValue CarryBits =
1324  DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32);
1325  SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1326  Lo = DAG.getSelect(dl, MVT::i32, ShiftIsZero, Lo,
1327  DAG.getNode(ISD::OR, dl, MVT::i32, Lo, CarryBits));
1328 
1329  SDValue Ops[2] = {Lo, Hi};
1330  return DAG.getMergeValues(Ops, dl);
1331 }
1332 
1333 // Helper function that checks if N is a null or all ones constant.
1334 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
1335  return AllOnes ? isAllOnesConstant(N) : isNullConstant(N);
1336 }
1337 
1338 // Return true if N is conditionally 0 or all ones.
1339 // Detects these expressions where cc is an i1 value:
1340 //
1341 // (select cc 0, y) [AllOnes=0]
1342 // (select cc y, 0) [AllOnes=0]
1343 // (zext cc) [AllOnes=0]
1344 // (sext cc) [AllOnes=0/1]
1345 // (select cc -1, y) [AllOnes=1]
1346 // (select cc y, -1) [AllOnes=1]
1347 //
1348 // * AllOnes determines whether to check for an all zero (AllOnes false) or an
1349 // all ones operand (AllOnes true).
1350 // * Invert is set when N is the all zero/ones constant when CC is false.
1351 // * OtherOp is set to the alternative value of N.
1352 //
1353 // For example, for (select cc X, Y) and AllOnes = 0 if:
1354 // * X = 0, Invert = False and OtherOp = Y
1355 // * Y = 0, Invert = True and OtherOp = X
1356 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC,
1357  bool &Invert, SDValue &OtherOp,
1358  SelectionDAG &DAG) {
1359  switch (N->getOpcode()) {
1360  default:
1361  return false;
1362  case ISD::SELECT: {
1363  CC = N->getOperand(0);
1364  SDValue N1 = N->getOperand(1);
1365  SDValue N2 = N->getOperand(2);
1366  if (isZeroOrAllOnes(N1, AllOnes)) {
1367  Invert = false;
1368  OtherOp = N2;
1369  return true;
1370  }
1371  if (isZeroOrAllOnes(N2, AllOnes)) {
1372  Invert = true;
1373  OtherOp = N1;
1374  return true;
1375  }
1376  return false;
1377  }
1378  case ISD::ZERO_EXTEND: {
1379  // (zext cc) can never be the all ones value.
1380  if (AllOnes)
1381  return false;
1382  CC = N->getOperand(0);
1383  if (CC.getValueType() != MVT::i1)
1384  return false;
1385  SDLoc dl(N);
1386  EVT VT = N->getValueType(0);
1387  OtherOp = DAG.getConstant(1, dl, VT);
1388  Invert = true;
1389  return true;
1390  }
1391  case ISD::SIGN_EXTEND: {
1392  CC = N->getOperand(0);
1393  if (CC.getValueType() != MVT::i1)
1394  return false;
1395  SDLoc dl(N);
1396  EVT VT = N->getValueType(0);
1397  Invert = !AllOnes;
1398  if (AllOnes)
1399  // When looking for an AllOnes constant, N is an sext, and the 'other'
1400  // value is 0.
1401  OtherOp = DAG.getConstant(0, dl, VT);
1402  else
1403  OtherOp = DAG.getAllOnesConstant(dl, VT);
1404  return true;
1405  }
1406  }
1407 }
1408 
1409 // Combine a constant select operand into its use:
1410 //
1411 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1412 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1413 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
1414 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
1415 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
1416 //
1417 // The transform is rejected if the select doesn't have a constant operand that
1418 // is null, or all ones when AllOnes is set.
1419 //
1420 // Also recognize sext/zext from i1:
1421 //
1422 // (add (zext cc), x) -> (select cc (add x, 1), x)
1423 // (add (sext cc), x) -> (select cc (add x, -1), x)
1424 //
1425 // These transformations eventually create predicated instructions.
1428  bool AllOnes) {
1429  SelectionDAG &DAG = DCI.DAG;
1430  EVT VT = N->getValueType(0);
1431  SDValue NonConstantVal;
1432  SDValue CCOp;
1433  bool SwapSelectOps;
1434  if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
1435  NonConstantVal, DAG))
1436  return SDValue();
1437 
1438  // Slct is now know to be the desired identity constant when CC is true.
1439  SDValue TrueVal = OtherOp;
1440  SDValue FalseVal =
1441  DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);
1442  // Unless SwapSelectOps says CC should be false.
1443  if (SwapSelectOps)
1445 
1446  return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
1447 }
1448 
1449 // Attempt combineSelectAndUse on each operand of a commutative operator N.
1450 static SDValue
1452  bool AllOnes) {
1453  SDValue N0 = N->getOperand(0);
1454  SDValue N1 = N->getOperand(1);
1455  if (N0.getNode()->hasOneUse())
1456  if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
1457  return Result;
1458  if (N1.getNode()->hasOneUse())
1459  if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
1460  return Result;
1461  return SDValue();
1462 }
1463 
1464 // PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1467  SDValue N0 = N->getOperand(0);
1468  SDValue N1 = N->getOperand(1);
1469 
1470  // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1471  if (N1.getNode()->hasOneUse())
1472  if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false))
1473  return Result;
1474 
1475  return SDValue();
1476 }
1477 
1479  DAGCombinerInfo &DCI) const {
1480  switch (N->getOpcode()) {
1481  default:
1482  break;
1483  case ISD::ADD:
1484  case ISD::OR:
1485  case ISD::XOR:
1486  return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/false);
1487  case ISD::AND:
1488  return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/true);
1489  case ISD::SUB:
1490  return PerformSUBCombine(N, DCI);
1491  }
1492 
1493  return SDValue();
1494 }
1495 
1497  const SDValue Op, KnownBits &Known, const APInt &DemandedElts,
1498  const SelectionDAG &DAG, unsigned Depth) const {
1499  unsigned BitWidth = Known.getBitWidth();
1500  switch (Op.getOpcode()) {
1501  default:
1502  break;
1503  case LanaiISD::SETCC:
1504  Known = KnownBits(BitWidth);
1505  Known.Zero.setBits(1, BitWidth);
1506  break;
1507  case LanaiISD::SELECT_CC:
1508  KnownBits Known2;
1509  Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
1510  Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
1511  Known = KnownBits::commonBits(Known, Known2);
1512  break;
1513  }
1514 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
llvm::LPCC::ICC_UGT
@ ICC_UGT
Definition: LanaiCondCode.h:14
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:153
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:957
i
i
Definition: README.txt:29
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1379
llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3177
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:38
ValueTypes.h
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1555
llvm::LanaiTargetLowering::LowerBR_CC
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:875
llvm::LanaiTargetLowering::LowerBlockAddress
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1201
llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
Definition: TargetLowering.h:1755
llvm::SelectionDAG::getCALLSEQ_START
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:923
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1390
PerformSUBCombine
static SDValue PerformSUBCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
Definition: LanaiISelLowering.cpp:1465
llvm::ISD::SETO
@ SETO
Definition: ISDOpcodes.h:1375
MathExtras.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::ISD::JumpTable
@ JumpTable
Definition: ISDOpcodes.h:81
combineSelectAndUse
static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes)
Definition: LanaiISelLowering.cpp:1426
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1085
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:36
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:197
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:633
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1387
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1391
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::TargetLowering::getSingleConstraintMatchWeight
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Definition: TargetLowering.cpp:4940
llvm::MachineFrameInfo::setReturnAddressIsTaken
void setReturnAddressIsTaken(bool s)
Definition: MachineFrameInfo.h:375
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:946
llvm::LanaiISD::BR_CC
@ BR_CC
Definition: LanaiISelLowering.h:50
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:735
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:151
llvm::APInt::setBits
void setBits(unsigned loBit, unsigned hiBit)
Set the bits from loBit (inclusive) to hiBit (exclusive) to 1.
Definition: APInt.h:1316
llvm::Function
Definition: Function.h:62
llvm::LanaiTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: LanaiISelLowering.cpp:175
StringRef.h
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:666
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::LanaiRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: LanaiRegisterInfo.cpp:264
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:931
llvm::LPCC::ICC_LE
@ ICC_LE
Definition: LanaiCondCode.h:30
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1747
llvm::CCState::addLoc
void addLoc(const CCValAssign &V)
Definition: CallingConvLower.h:253
llvm::KnownBits::Zero
APInt Zero
Definition: KnownBits.h:24
llvm::TargetLoweringBase::MaxStoresPerMemset
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
Definition: TargetLowering.h:3175
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1628
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1386
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1012
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:8534
LanaiBaseInfo.h
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
ErrorHandling.h
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:732
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::TargetLowering::CW_Constant
@ CW_Constant
Definition: TargetLowering.h:4243
llvm::TargetLowering::DAGCombinerInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:3615
llvm::LanaiISD::LO
@ LO
Definition: LanaiISelLowering.h:58
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:262
APInt.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::LanaiMachineFunctionInfo
Definition: LanaiMachineFunctionInfo.h:24
llvm::ISD::ArgFlagsTy::isZExt
bool isZExt() const
Definition: TargetCallingConv.h:73
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1381
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:715
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Definition: SelectionDAG.cpp:7495
llvm::LanaiTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: LanaiISelLowering.cpp:1478
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:702
llvm::LanaiII::MO_ABS_LO
@ MO_ABS_LO
Definition: LanaiBaseInfo.h:36
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2316
llvm::LanaiISD::SUBBF
@ SUBBF
Definition: LanaiISelLowering.h:47
llvm::LanaiTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: LanaiISelLowering.cpp:284
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::tgtok::FalseVal
@ FalseVal
Definition: TGLexer.h:61
llvm::TargetLoweringBase::setLibcallCallingConv
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:2941
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:893
llvm::LanaiTargetLowering::LowerSHL_PARTS
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1244
llvm::codeview::EncodedFramePtrReg::StackPtr
@ StackPtr
llvm::FunctionType::getNumParams
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
Lanai.h
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1041
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1346
llvm::LPCC::ICC_UGE
@ ICC_UGE
Definition: LanaiCondCode.h:20
llvm::ISD::SETOEQ
@ SETOEQ
Definition: ISDOpcodes.h:1369
SelectionDAG.h
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::LanaiISD::SMALL
@ SMALL
Definition: LanaiISelLowering.h:61
llvm::ISD::SETUEQ
@ SETUEQ
Definition: ISDOpcodes.h:1377
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:447
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:956
MachineRegisterInfo.h
KnownBits.h
llvm::LanaiII::MO_NO_FLAG
@ MO_NO_FLAG
Definition: LanaiBaseInfo.h:31
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:2010
Context
ManagedStatic< detail::RecordContext > Context
Definition: Record.cpp:96
llvm::MipsISD::Hi
@ Hi
Definition: MipsISelLowering.h:75
MachineValueType.h
llvm::LPCC::ICC_EQ
@ ICC_EQ
Definition: LanaiCondCode.h:22
llvm::ISD::ROTL
@ ROTL
Definition: ISDOpcodes.h:660
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::MVT::integer_valuetypes
static auto integer_valuetypes()
Definition: MachineValueType.h:1412
CommandLine.h
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:963
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7445
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::TargetLowering::CallLoweringInfo::IsVarArg
bool IsVarArg
Definition: TargetLowering.h:3817
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:651
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:39
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:694
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2190
GlobalValue.h
llvm::LanaiISD::SET_FLAG
@ SET_FLAG
Definition: LanaiISelLowering.h:44
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1120
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
TargetMachine.h
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:668
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
SelectionDAGNodes.h
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:679
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::SDNode::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this node.
Definition: SelectionDAGNodes.h:699
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:729
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85
llvm::LanaiTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: LanaiISelLowering.cpp:1103
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1388
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:150
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:739
llvm::LanaiTargetLowering::LowerMUL
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:892
llvm::LanaiMachineFunctionInfo::setVarArgsFrameIndex
void setVarArgsFrameIndex(int Index)
Definition: LanaiMachineFunctionInfo.h:48
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:747
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1398
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1820
llvm::GlobalObject
Definition: GlobalObject.h:28
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3254
llvm::LPCC::CondCode
CondCode
Definition: LanaiCondCode.h:10
llvm::LPCC::ICC_GE
@ ICC_GE
Definition: LanaiCondCode.h:27
llvm::LanaiISD::SELECT_CC
@ SELECT_CC
Definition: LanaiISelLowering.h:38
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3609
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:735
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:321
LanaiCondCode.h
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:256
isZeroOrAllOnes
static bool isZeroOrAllOnes(SDValue N, bool AllOnes)
Definition: LanaiISelLowering.cpp:1334
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2198
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::LPCC::ICC_LT
@ ICC_LT
Definition: LanaiCondCode.h:28
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::TargetLoweringBase::MaxStoresPerMemcpy
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
Definition: TargetLowering.h:3190
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:632
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:155
llvm::ISD::SETOLT
@ SETOLT
Definition: ISDOpcodes.h:1372
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::LanaiISD::SETCC
@ SETCC
Definition: LanaiISelLowering.h:41
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:151
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::LPCC::ICC_GT
@ ICC_GT
Definition: LanaiCondCode.h:29
llvm::LanaiISD::ADJDYNALLOC
@ ADJDYNALLOC
Definition: LanaiISelLowering.h:27
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:145
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ISD::SETOLE
@ SETOLE
Definition: ISDOpcodes.h:1373
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1378
llvm::SelectionDAG::getTargetGlobalAddress
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:683
llvm::LanaiISD::RET_FLAG
@ RET_FLAG
Definition: LanaiISelLowering.h:30
CC_Lanai32_VarArg
static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
Definition: LanaiISelLowering.cpp:369
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
llvm::TargetLowering::CallLoweringInfo::Outs
SmallVector< ISD::OutputArg, 32 > Outs
Definition: TargetLowering.h:3840
llvm::ISD::SETUNE
@ SETUNE
Definition: ISDOpcodes.h:1382
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2215
llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3192
llvm::cl::opt
Definition: CommandLine.h:1432
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:35
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::LanaiTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: LanaiISelLowering.cpp:236
llvm::LPCC::ICC_ULT
@ ICC_ULT
Definition: LanaiCondCode.h:18
llvm::isInt< 32 >
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:373
TargetCallingConv.h
llvm::LanaiTargetLowering::LowerVASTART
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1011
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:341
llvm::LPCC::ICC_MI
@ ICC_MI
Definition: LanaiCondCode.h:26
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:37
llvm::isUInt< 16 >
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:408
RuntimeLibcalls.h
LanaiLowerConstantMulThreshold
static cl::opt< int > LanaiLowerConstantMulThreshold("lanai-constant-mul-threshold", cl::Hidden, cl::desc("Maximum number of instruction to generate when lowering constant " "multiplication instead of calling library function [default=14]"), cl::init(14))
combineSelectAndUseCommutative
static SDValue combineSelectAndUseCommutative(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes)
Definition: LanaiISelLowering.cpp:1451
llvm::TargetLowering::CallLoweringInfo::Chain
SDValue Chain
Definition: TargetLowering.h:3813
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Definition: SelectionDAG.cpp:1521
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:62
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:198
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::LanaiTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: LanaiISelLowering.cpp:215
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:761
llvm::TargetLowering::CallLoweringInfo::CallConv
CallingConv::ID CallConv
Definition: TargetLowering.h:3834
llvm::codeview::FrameCookieKind::Copy
@ Copy
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2164
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:8299
llvm::LanaiTargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: LanaiISelLowering.cpp:255
llvm::TargetLoweringBase::setPrefFunctionAlignment
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
Definition: TargetLowering.h:2322
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::TargetLowering::AsmOperandInfo
This contains information for each constraint that we are lowering.
Definition: TargetLowering.h:4248
llvm::TargetLowering::CallLoweringInfo::DL
SDLoc DL
Definition: TargetLowering.h:3838
llvm::Function::hasStructRetAttr
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:642
ArrayRef.h
llvm::CCValAssign::getMem
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:102
llvm::SelectionDAG::getAllOnesConstant
SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false)
Definition: SelectionDAG.h:622
llvm::LanaiTargetLowering::LowerGlobalAddress
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1167
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1346
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:171
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::ISD::SETOGT
@ SETOGT
Definition: ISDOpcodes.h:1370
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3812
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LPCC::ICC_PL
@ ICC_PL
Definition: LanaiCondCode.h:25
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:80
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:615
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:860
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:840
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:657
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1380
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1366
llvm::LanaiISD::Wrapper
@ Wrapper
Definition: LanaiISelLowering.h:54
llvm::ISD::RETURNADDR
@ RETURNADDR
Definition: ISDOpcodes.h:95
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::TargetMachine::getObjFileLowering
virtual TargetLoweringObjectFile * getObjFileLowering() const
Definition: TargetMachine.h:139
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:716
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1042
llvm::TargetLowering::CW_Default
@ CW_Default
Definition: TargetLowering.h:4244
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::LPCC::ICC_NE
@ ICC_NE
Definition: LanaiCondCode.h:21
llvm::SelectionDAG::getCALLSEQ_END
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
Definition: SelectionDAG.h:935
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:657
isConditionalZeroOrAllOnes
static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG)
Definition: LanaiISelLowering.cpp:1356
llvm::TargetLowering::CallLoweringInfo::Ins
SmallVector< ISD::InputArg, 32 > Ins
Definition: TargetLowering.h:3842
llvm::ISD::ConstantPool
@ ConstantPool
Definition: ISDOpcodes.h:82
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:848
llvm::TargetLowering::CallLoweringInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:3837
llvm::SelectionDAG::getTargetConstantPool
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:699
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1841
llvm::SelectionDAG::getSelect
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
Definition: SelectionDAG.h:1075
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::TargetLowering::LowerAsmOperandForConstraint
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
Definition: TargetLowering.cpp:4574
llvm::LanaiTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: LanaiISelLowering.cpp:1496
llvm::LanaiSubtarget
Definition: LanaiSubtarget.h:29
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::SelectionDAG::getBlockAddress
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0)
Definition: SelectionDAG.cpp:2063
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:251
uint32_t
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::LanaiMachineFunctionInfo::getVarArgsFrameIndex
int getVarArgsFrameIndex() const
Definition: LanaiMachineFunctionInfo.h:47
llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3227
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::LanaiTargetObjectFile::isConstantInSmallSection
bool isConstantInSmallSection(const DataLayout &DL, const Constant *CN) const
Return true if this constant should be placed into small data section.
Definition: LanaiTargetObjectFile.cpp:114
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Definition: TargetLowering.cpp:4653
llvm::LPCC::ICC_ULE
@ ICC_ULE
Definition: LanaiCondCode.h:16
llvm::CCState::CheckReturn
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
Definition: CallingConvLower.cpp:104
llvm::GlobalValue::getAliaseeObject
const GlobalObject * getAliaseeObject() const
Definition: Globals.cpp:316
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:78
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1346
llvm::LanaiTargetLowering::LowerConstantPool
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1134
LanaiTargetObjectFile.h
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:634
llvm::SelectionDAG::getTargetJumpTable
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:693
llvm::LanaiTargetLowering::LowerSRL_PARTS
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1293
NumFixedArgs
static unsigned NumFixedArgs
Definition: LanaiISelLowering.cpp:368
llvm::ISD::FRAMEADDR
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
Definition: ISDOpcodes.h:94
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:206
IntCondCCodeToICC
static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL, SDValue &RHS, SelectionDAG &DAG)
Definition: LanaiISelLowering.cpp:810
llvm::EVT::getEVTString
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:151
CallingConv.h
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:339
llvm::isInt< 16 >
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:370
llvm::TargetLowering::CallLoweringInfo::IsTailCall
bool IsTailCall
Definition: TargetLowering.h:3828
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1389
llvm::LanaiSubtarget::getRegisterInfo
const LanaiRegisterInfo * getRegisterInfo() const override
Definition: LanaiSubtarget.h:54
llvm::isAllOnesConstant
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
Definition: SelectionDAG.cpp:9920
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:146
llvm::ISD::ArgFlagsTy::getByValSize
unsigned getByValSize() const
Definition: TargetCallingConv.h:169
LanaiISelLowering.h
llvm::SelectionDAG::computeKnownBits
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
Definition: SelectionDAG.cpp:2771
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2222
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1717
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
CallingConvLower.h
llvm::isNullConstant
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
Definition: SelectionDAG.cpp:9910
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
MachineFrameInfo.h
llvm::LanaiMachineFunctionInfo::setSRetReturnReg
void setSRetReturnReg(Register Reg)
Definition: LanaiMachineFunctionInfo.h:45
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:516
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4231
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:440
llvm::LanaiTargetLowering::LowerRETURNADDR
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1061
Casting.h
llvm::ISD::ArgFlagsTy::isSExt
bool isSExt() const
Definition: TargetCallingConv.h:76
Function.h
llvm::CCState::AllocateStack
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Definition: CallingConvLower.h:425
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:201
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::SelectionDAG::getTargetExternalSymbol
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.cpp:1778
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::ISD::SETUO
@ SETUO
Definition: ISDOpcodes.h:1376
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
llvm::Function::getFunctionType
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:177
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Returns the code model.
Definition: TargetMachine.cpp:74
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:233
StringSwitch.h
llvm::TargetLowering::CW_Invalid
@ CW_Invalid
Definition: TargetLowering.h:4233
llvm::LanaiTargetLowering::LowerSETCC
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:978
llvm::TargetLoweringBase::setJumpIsExpensive
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
Definition: TargetLoweringBase.cpp:957
LanaiMachineFunctionInfo.h
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1037
llvm::LanaiTargetObjectFile
Definition: LanaiTargetObjectFile.h:15
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:717
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
CodeGen.h
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2132
llvm::ISD::SETOGE
@ SETOGE
Definition: ISDOpcodes.h:1371
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:657
SmallVector.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1008
llvm::LanaiTargetLowering::LanaiTargetLowering
LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI)
Definition: LanaiISelLowering.cpp:73
llvm::ISD::ArgFlagsTy::getNonZeroByValAlign
Align getNonZeroByValAlign() const
Definition: TargetCallingConv.h:153
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:199
llvm::TargetLoweringBase::setTargetDAGCombine
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
Definition: TargetLowering.h:2310
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:143
N
#define N
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1292
llvm::TargetLoweringBase::setMinimumJumpTableEntries
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
Definition: TargetLoweringBase.cpp:2017
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:659
llvm::LanaiTargetLowering::LowerJumpTable
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1217
llvm::KnownBits::commonBits
static KnownBits commonBits(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits common to LHS and RHS.
Definition: KnownBits.h:295
llvm::SelectionDAG::getRegisterMask
SDValue getRegisterMask(const uint32_t *RegMask)
Definition: SelectionDAG.cpp:2025
llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1026
llvm::ISD::CTTZ
@ CTTZ
Definition: ISDOpcodes.h:667
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:869
llvm::LanaiISD::CALL
@ CALL
Definition: LanaiISelLowering.h:34
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::ISD::MULHU
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:614
llvm::TargetLowering::CallLoweringInfo::OutVals
SmallVector< SDValue, 32 > OutVals
Definition: TargetLowering.h:3841
RegName
#define RegName(no)
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:637
DerivedTypes.h
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::ISD::SETONE
@ SETONE
Definition: ISDOpcodes.h:1374
llvm::LanaiTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: LanaiISelLowering.cpp:533
llvm::TargetLowering::CallLoweringInfo::Callee
SDValue Callee
Definition: TargetLowering.h:3835
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:437
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1032
llvm::KnownBits::getBitWidth
unsigned getBitWidth() const
Get the bit width of this value.
Definition: KnownBits.h:40
llvm::LanaiRegisterInfo::getRARegister
unsigned getRARegister() const
Definition: LanaiRegisterInfo.cpp:254
llvm::ISD::SDIVREM
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
llvm::MachineFrameInfo::setFrameAddressIsTaken
void setFrameAddressIsTaken(bool T)
Definition: MachineFrameInfo.h:369
llvm::cl::desc
Definition: CommandLine.h:412
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:726
raw_ostream.h
llvm::LanaiTargetLowering::LowerFRAMEADDR
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1084
llvm::SelectionDAG::getMemcpy
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
Definition: SelectionDAG.cpp:6820
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:156
MachineFunction.h
LanaiSubtarget.h
llvm::tgtok::TrueVal
@ TrueVal
Definition: TGLexer.h:61
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1282
llvm::ISD::STACKSAVE
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1008
llvm::TargetLoweringBase::MaxStoresPerMemmove
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
Definition: TargetLowering.h:3225
llvm::codegen::getCodeModel
CodeModel::Model getCodeModel()
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::ISD::ROTR
@ ROTR
Definition: ISDOpcodes.h:661
Debug.h
llvm::LanaiTargetLowering::LowerSELECT_CC
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:992
llvm::LanaiII::MO_ABS_HI
@ MO_ABS_HI
Definition: LanaiBaseInfo.h:35
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:346
llvm::ISD::CTPOP
@ CTPOP
Definition: ISDOpcodes.h:669
llvm::SelectionDAG::getSetCC
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:1058
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::LanaiMachineFunctionInfo::getSRetReturnReg
Register getSRetReturnReg() const
Definition: LanaiMachineFunctionInfo.h:44
llvm::SelectionDAG::getMergeValues
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
Definition: SelectionDAG.cpp:7211
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:289
llvm::LanaiISD::HI
@ HI
Definition: LanaiISelLowering.h:57
llvm::LLT
Definition: LowLevelTypeImpl.h:40