26 #define DEBUG_TYPE "regalloc"
40 while (SegPos.valid()) {
41 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
42 if (++RegPos == RegEnd)
44 SegPos.advanceTo(RegPos->start);
51 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
52 for (; RegPos != RegEnd; ++RegPos, ++SegPos)
53 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
69 assert(SegPos.value() == &VirtReg &&
"Inconsistent LiveInterval");
75 RegPos = Range.
advanceTo(RegPos, SegPos.start());
79 SegPos.advanceTo(RegPos->start);
90 OS <<
" [" <<
SI.start() <<
' ' <<
SI.stop()
100 VisitedVRegs.
set(
SI.value()->reg());
116 bool LiveIntervalUnion::Query::isSeenInterference(
131 LiveIntervalUnion::Query::collectInterferingVRegs(
unsigned MaxInterferingRegs) {
133 if (SeenAllInterferences || InterferingVRegs.size() >= MaxInterferingRegs)
134 return InterferingVRegs.size();
137 if (!CheckedFirstInterference) {
138 CheckedFirstInterference =
true;
141 if (LR->empty() || LiveUnion->empty()) {
142 SeenAllInterferences =
true;
148 LiveUnionI.setMap(LiveUnion->getMap());
149 LiveUnionI.find(LRI->start);
154 while (LiveUnionI.valid()) {
155 assert(LRI != LREnd &&
"Reached end of LR");
158 while (LRI->start < LiveUnionI.stop() && LRI->end > LiveUnionI.start()) {
161 if (VReg != RecentReg && !isSeenInterference(VReg)) {
163 InterferingVRegs.push_back(VReg);
164 if (InterferingVRegs.size() >= MaxInterferingRegs)
165 return InterferingVRegs.
size();
168 if (!(++LiveUnionI).valid()) {
169 SeenAllInterferences =
true;
170 return InterferingVRegs.size();
176 assert(LRI->end <= LiveUnionI.start() &&
"Expected non-overlap");
179 LRI = LR->advanceTo(LRI, LiveUnionI.start());
184 if (LRI->start < LiveUnionI.stop())
188 LiveUnionI.advanceTo(LRI->start);
190 SeenAllInterferences =
true;
191 return InterferingVRegs.size();
203 for (
unsigned i = 0;
i != Size; ++
i)
210 for (
unsigned i = 0;
i != Size; ++
i)