26#define DEBUG_TYPE "regalloc"
40 while (SegPos.valid()) {
41 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
42 if (++RegPos == RegEnd)
44 SegPos.advanceTo(RegPos->start);
51 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
52 for (; RegPos != RegEnd; ++RegPos, ++SegPos)
53 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
69 assert(SegPos.value() == &VirtReg &&
"Inconsistent LiveInterval");
75 RegPos = Range.advanceTo(RegPos, SegPos.start());
79 SegPos.advanceTo(RegPos->start);
90 OS <<
" [" << SI.start() <<
' ' << SI.stop()
100 VisitedVRegs.
set(SI.value()->reg());
116bool LiveIntervalUnion::Query::isSeenInterference(
131LiveIntervalUnion::Query::collectInterferingVRegs(
unsigned MaxInterferingRegs) {
133 if (SeenAllInterferences || InterferingVRegs.size() >= MaxInterferingRegs)
134 return InterferingVRegs.size();
137 if (!CheckedFirstInterference) {
138 CheckedFirstInterference =
true;
141 if (LR->empty() || LiveUnion->empty()) {
142 SeenAllInterferences =
true;
148 LiveUnionI.setMap(LiveUnion->getMap());
149 LiveUnionI.find(LRI->start);
154 while (LiveUnionI.valid()) {
155 assert(LRI != LREnd &&
"Reached end of LR");
158 while (LRI->start < LiveUnionI.stop() && LRI->end > LiveUnionI.start()) {
161 if (VReg != RecentReg && !isSeenInterference(VReg)) {
163 InterferingVRegs.push_back(VReg);
164 if (InterferingVRegs.size() >= MaxInterferingRegs)
165 return InterferingVRegs.
size();
168 if (!(++LiveUnionI).valid()) {
169 SeenAllInterferences =
true;
170 return InterferingVRegs.size();
176 assert(LRI->end <= LiveUnionI.start() &&
"Expected non-overlap");
179 LRI = LR->advanceTo(LRI, LiveUnionI.start());
184 if (LRI->start < LiveUnionI.stop())
188 LiveUnionI.advanceTo(LRI->start);
190 SeenAllInterferences =
true;
191 return InterferingVRegs.size();
203 for (
unsigned i = 0; i !=
Size; ++i)
210 for (
unsigned i = 0; i !=
Size; ++i)
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SparseBitVector class.
const_iterator begin() const
const_iterator find(KeyT x) const
find - Return an iterator pointing to the first interval ending at or after x, or end().
friend class const_iterator
void init(LiveIntervalUnion::Allocator &, unsigned Size)
Union of live intervals that are strong candidates for coalescing into a single register (either phys...
void unify(const LiveInterval &VirtReg, const LiveRange &Range)
const LiveInterval * getOneVReg() const
NDEBUG.
void extract(const LiveInterval &VirtReg, const LiveRange &Range)
LiveSegments::iterator SegmentIter
void verify(LiveVirtRegBitSet &VisitedVRegs)
void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const
LiveSegments::Allocator Allocator
LiveInterval - This class represents the liveness of a register, or stack slot.
This class represents the liveness of a register, stack slot, etc.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class implements an extremely fast bulk output stream that can only output to a stream.
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ATTRIBUTE_RETURNS_NONNULL void * safe_malloc(size_t Sz)
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.