LLVM  13.0.0git
TargetRegisterInfo.cpp
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1 //==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the TargetRegisterInfo interface.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/ArrayRef.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/Config/llvm-config.h"
28 #include "llvm/IR/Attributes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/MC/MCRegisterInfo.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/Printable.h"
39 #include <cassert>
40 #include <utility>
41 
42 #define DEBUG_TYPE "target-reg-info"
43 
44 using namespace llvm;
45 
46 static cl::opt<unsigned>
47  HugeSizeForSplit("huge-size-for-split", cl::Hidden,
48  cl::desc("A threshold of live range size which may cause "
49  "high compile time cost in global splitting."),
50  cl::init(5000));
51 
54  const char *const *SRINames,
55  const LaneBitmask *SRILaneMasks,
56  LaneBitmask SRICoveringLanes,
57  const RegClassInfo *const RCIs,
58  unsigned Mode)
59  : InfoDesc(ID), SubRegIndexNames(SRINames),
60  SubRegIndexLaneMasks(SRILaneMasks),
61  RegClassBegin(RCB), RegClassEnd(RCE),
62  CoveringLanes(SRICoveringLanes),
63  RCInfos(RCIs), HwMode(Mode) {
64 }
65 
67 
69  const MachineFunction &MF, const LiveInterval &VirtReg) const {
71  const MachineRegisterInfo &MRI = MF.getRegInfo();
72  MachineInstr *MI = MRI.getUniqueVRegDef(VirtReg.reg());
73  if (MI && TII->isTriviallyReMaterializable(*MI) &&
74  VirtReg.size() > HugeSizeForSplit)
75  return false;
76  return true;
77 }
78 
80  MCRegister Reg) const {
81  for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
82  RegisterSet.set(*AI);
83 }
84 
86  ArrayRef<MCPhysReg> Exceptions) const {
87  // Check that all super registers of reserved regs are reserved as well.
88  BitVector Checked(getNumRegs());
89  for (unsigned Reg : RegisterSet.set_bits()) {
90  if (Checked[Reg])
91  continue;
92  for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
93  if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
94  dbgs() << "Error: Super register " << printReg(*SR, this)
95  << " of reserved register " << printReg(Reg, this)
96  << " is not reserved.\n";
97  return false;
98  }
99 
100  // We transitively check superregs. So we can remember this for later
101  // to avoid compiletime explosion in deep register hierarchies.
102  Checked.set(*SR);
103  }
104  }
105  return true;
106 }
107 
108 namespace llvm {
109 
111  unsigned SubIdx, const MachineRegisterInfo *MRI) {
112  return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {
113  if (!Reg)
114  OS << "$noreg";
115  else if (Register::isStackSlot(Reg))
116  OS << "SS#" << Register::stackSlot2Index(Reg);
117  else if (Register::isVirtualRegister(Reg)) {
118  StringRef Name = MRI ? MRI->getVRegName(Reg) : "";
119  if (Name != "") {
120  OS << '%' << Name;
121  } else {
122  OS << '%' << Register::virtReg2Index(Reg);
123  }
124  } else if (!TRI)
125  OS << '$' << "physreg" << Reg;
126  else if (Reg < TRI->getNumRegs()) {
127  OS << '$';
128  printLowerCase(TRI->getName(Reg), OS);
129  } else
130  llvm_unreachable("Register kind is unsupported.");
131 
132  if (SubIdx) {
133  if (TRI)
134  OS << ':' << TRI->getSubRegIndexName(SubIdx);
135  else
136  OS << ":sub(" << SubIdx << ')';
137  }
138  });
139 }
140 
142  return Printable([Unit, TRI](raw_ostream &OS) {
143  // Generic printout when TRI is missing.
144  if (!TRI) {
145  OS << "Unit~" << Unit;
146  return;
147  }
148 
149  // Check for invalid register units.
150  if (Unit >= TRI->getNumRegUnits()) {
151  OS << "BadUnit~" << Unit;
152  return;
153  }
154 
155  // Normal units have at least one root.
156  MCRegUnitRootIterator Roots(Unit, TRI);
157  assert(Roots.isValid() && "Unit has no roots.");
158  OS << TRI->getName(*Roots);
159  for (++Roots; Roots.isValid(); ++Roots)
160  OS << '~' << TRI->getName(*Roots);
161  });
162 }
163 
165  return Printable([Unit, TRI](raw_ostream &OS) {
166  if (Register::isVirtualRegister(Unit)) {
167  OS << '%' << Register::virtReg2Index(Unit);
168  } else {
169  OS << printRegUnit(Unit, TRI);
170  }
171  });
172 }
173 
175  const TargetRegisterInfo *TRI) {
176  return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
177  if (RegInfo.getRegClassOrNull(Reg))
178  OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
179  else if (RegInfo.getRegBankOrNull(Reg))
180  OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
181  else {
182  OS << "_";
183  assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
184  "Generic registers must have a valid type");
185  }
186  });
187 }
188 
189 } // end namespace llvm
190 
191 /// getAllocatableClass - Return the maximal subclass of the given register
192 /// class that is alloctable, or NULL.
193 const TargetRegisterClass *
195  if (!RC || RC->isAllocatable())
196  return RC;
197 
198  for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
199  ++It) {
200  const TargetRegisterClass *SubRC = getRegClass(It.getID());
201  if (SubRC->isAllocatable())
202  return SubRC;
203  }
204  return nullptr;
205 }
206 
207 /// getMinimalPhysRegClass - Returns the Register Class of a physical
208 /// register of the given type, picking the most sub register class of
209 /// the right type that contains this physreg.
210 const TargetRegisterClass *
213  "reg must be a physical register");
214 
215  // Pick the most sub register class of the right type that contains
216  // this physreg.
217  const TargetRegisterClass* BestRC = nullptr;
218  for (const TargetRegisterClass* RC : regclasses()) {
219  if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
220  RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
221  BestRC = RC;
222  }
223 
224  assert(BestRC && "Couldn't find the register class");
225  return BestRC;
226 }
227 
228 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
229 /// registers for the specific register class.
231  const TargetRegisterClass *RC, BitVector &R){
232  assert(RC->isAllocatable() && "invalid for nonallocatable sets");
234  for (unsigned i = 0; i != Order.size(); ++i)
235  R.set(Order[i]);
236 }
237 
239  const TargetRegisterClass *RC) const {
240  BitVector Allocatable(getNumRegs());
241  if (RC) {
242  // A register class with no allocatable subclass returns an empty set.
243  const TargetRegisterClass *SubClass = getAllocatableClass(RC);
244  if (SubClass)
245  getAllocatableSetForRC(MF, SubClass, Allocatable);
246  } else {
247  for (const TargetRegisterClass *C : regclasses())
248  if (C->isAllocatable())
249  getAllocatableSetForRC(MF, C, Allocatable);
250  }
251 
252  // Mask out the reserved registers
254  Allocatable &= Reserved.flip();
255 
256  return Allocatable;
257 }
258 
259 static inline
261  const uint32_t *B,
262  const TargetRegisterInfo *TRI) {
263  for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
264  if (unsigned Common = *A++ & *B++)
265  return TRI->getRegClass(I + countTrailingZeros(Common));
266  return nullptr;
267 }
268 
269 const TargetRegisterClass *
271  const TargetRegisterClass *B) const {
272  // First take care of the trivial cases.
273  if (A == B)
274  return A;
275  if (!A || !B)
276  return nullptr;
277 
278  // Register classes are ordered topologically, so the largest common
279  // sub-class it the common sub-class with the smallest ID.
280  return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);
281 }
282 
283 const TargetRegisterClass *
285  const TargetRegisterClass *B,
286  unsigned Idx) const {
287  assert(A && B && "Missing register class");
288  assert(Idx && "Bad sub-register index");
289 
290  // Find Idx in the list of super-register indices.
291  for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
292  if (RCI.getSubReg() == Idx)
293  // The bit mask contains all register classes that are projected into B
294  // by Idx. Find a class that is also a sub-class of A.
295  return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
296  return nullptr;
297 }
298 
300 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
301  const TargetRegisterClass *RCB, unsigned SubB,
302  unsigned &PreA, unsigned &PreB) const {
303  assert(RCA && SubA && RCB && SubB && "Invalid arguments");
304 
305  // Search all pairs of sub-register indices that project into RCA and RCB
306  // respectively. This is quadratic, but usually the sets are very small. On
307  // most targets like X86, there will only be a single sub-register index
308  // (e.g., sub_16bit projecting into GR16).
309  //
310  // The worst case is a register class like DPR on ARM.
311  // We have indices dsub_0..dsub_7 projecting into that class.
312  //
313  // It is very common that one register class is a sub-register of the other.
314  // Arrange for RCA to be the larger register so the answer will be found in
315  // the first iteration. This makes the search linear for the most common
316  // case.
317  const TargetRegisterClass *BestRC = nullptr;
318  unsigned *BestPreA = &PreA;
319  unsigned *BestPreB = &PreB;
320  if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
321  std::swap(RCA, RCB);
322  std::swap(SubA, SubB);
323  std::swap(BestPreA, BestPreB);
324  }
325 
326  // Also terminate the search one we have found a register class as small as
327  // RCA.
328  unsigned MinSize = getRegSizeInBits(*RCA);
329 
330  for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
331  unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
332  for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
333  // Check if a common super-register class exists for this index pair.
334  const TargetRegisterClass *RC =
335  firstCommonClass(IA.getMask(), IB.getMask(), this);
336  if (!RC || getRegSizeInBits(*RC) < MinSize)
337  continue;
338 
339  // The indexes must compose identically: PreA+SubA == PreB+SubB.
340  unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
341  if (FinalA != FinalB)
342  continue;
343 
344  // Is RC a better candidate than BestRC?
345  if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))
346  continue;
347 
348  // Yes, RC is the smallest super-register seen so far.
349  BestRC = RC;
350  *BestPreA = IA.getSubReg();
351  *BestPreB = IB.getSubReg();
352 
353  // Bail early if we reached MinSize. We won't find a better candidate.
354  if (getRegSizeInBits(*BestRC) == MinSize)
355  return BestRC;
356  }
357  }
358  return BestRC;
359 }
360 
361 /// Check if the registers defined by the pair (RegisterClass, SubReg)
362 /// share the same register file.
364  const TargetRegisterClass *DefRC,
365  unsigned DefSubReg,
366  const TargetRegisterClass *SrcRC,
367  unsigned SrcSubReg) {
368  // Same register class.
369  if (DefRC == SrcRC)
370  return true;
371 
372  // Both operands are sub registers. Check if they share a register class.
373  unsigned SrcIdx, DefIdx;
374  if (SrcSubReg && DefSubReg) {
375  return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
376  SrcIdx, DefIdx) != nullptr;
377  }
378 
379  // At most one of the register is a sub register, make it Src to avoid
380  // duplicating the test.
381  if (!SrcSubReg) {
382  std::swap(DefSubReg, SrcSubReg);
383  std::swap(DefRC, SrcRC);
384  }
385 
386  // One of the register is a sub register, check if we can get a superclass.
387  if (SrcSubReg)
388  return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
389 
390  // Plain copy.
391  return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
392 }
393 
395  unsigned DefSubReg,
396  const TargetRegisterClass *SrcRC,
397  unsigned SrcSubReg) const {
398  // If this source does not incur a cross register bank copy, use it.
399  return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
400 }
401 
402 // Compute target-independent register allocator hints to help eliminate copies.
404  Register VirtReg, ArrayRef<MCPhysReg> Order,
406  const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
407  const MachineRegisterInfo &MRI = MF.getRegInfo();
408  const std::pair<Register, SmallVector<Register, 4>> &Hints_MRI =
409  MRI.getRegAllocationHints(VirtReg);
410 
411  SmallSet<Register, 32> HintedRegs;
412  // First hint may be a target hint.
413  bool Skip = (Hints_MRI.first != 0);
414  for (auto Reg : Hints_MRI.second) {
415  if (Skip) {
416  Skip = false;
417  continue;
418  }
419 
420  // Target-independent hints are either a physical or a virtual register.
421  Register Phys = Reg;
422  if (VRM && Phys.isVirtual())
423  Phys = VRM->getPhys(Phys);
424 
425  // Don't add the same reg twice (Hints_MRI may contain multiple virtual
426  // registers allocated to the same physreg).
427  if (!HintedRegs.insert(Phys).second)
428  continue;
429  // Check that Phys is a valid hint in VirtReg's register class.
430  if (!Phys.isPhysical())
431  continue;
432  if (MRI.isReserved(Phys))
433  continue;
434  // Check that Phys is in the allocation order. We shouldn't heed hints
435  // from VirtReg's register class if they aren't in the allocation order. The
436  // target probably has a reason for removing the register.
437  if (!is_contained(Order, Phys))
438  continue;
439 
440  // All clear, tell the register allocator to prefer this register.
441  Hints.push_back(Phys);
442  }
443  return false;
444 }
445 
447  MCRegister PhysReg, const MachineFunction &MF) const {
448  if (PhysReg == 0)
449  return false;
450  const uint32_t *callerPreservedRegs =
452  if (callerPreservedRegs) {
454  "Expected physical register");
455  return (callerPreservedRegs[PhysReg / 32] >> PhysReg % 32) & 1;
456  }
457  return false;
458 }
459 
461  return !MF.getFunction().hasFnAttribute("no-realign-stack");
462 }
463 
465  const MachineFrameInfo &MFI = MF.getFrameInfo();
467  const Function &F = MF.getFunction();
468  return F.hasFnAttribute("stackrealign") ||
469  (MFI.getMaxAlign() > TFI->getStackAlign()) ||
470  F.hasFnAttribute(Attribute::StackAlignment);
471 }
472 
474  const uint32_t *mask1) const {
475  unsigned N = (getNumRegs()+31) / 32;
476  for (unsigned I = 0; I < N; ++I)
477  if ((mask0[I] & mask1[I]) != mask0[I])
478  return false;
479  return true;
480 }
481 
482 unsigned
484  const MachineRegisterInfo &MRI) const {
485  const TargetRegisterClass *RC{};
486  if (Reg.isPhysical()) {
487  // The size is not directly available for physical registers.
488  // Instead, we need to access a register class that contains Reg and
489  // get the size of that register class.
491  } else {
492  LLT Ty = MRI.getType(Reg);
493  unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
494  // If Reg is not a generic register, query the register class to
495  // get its size.
496  if (RegSize)
497  return RegSize;
498  // Since Reg is not a generic register, it must have a register class.
499  RC = MRI.getRegClass(Reg);
500  }
501  assert(RC && "Unable to deduce the register class");
502  return getRegSizeInBits(*RC);
503 }
504 
506  const MachineRegisterInfo &MRI, const TargetRegisterClass *RC,
507  LaneBitmask LaneMask, SmallVectorImpl<unsigned> &NeededIndexes) const {
508  SmallVector<unsigned, 8> PossibleIndexes;
509  unsigned BestIdx = 0;
510  unsigned BestCover = 0;
511 
512  for (unsigned Idx = 1, E = getNumSubRegIndices(); Idx < E; ++Idx) {
513  // Is this index even compatible with the given class?
514  if (getSubClassWithSubReg(RC, Idx) != RC)
515  continue;
516  LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx);
517  // Early exit if we found a perfect match.
518  if (SubRegMask == LaneMask) {
519  BestIdx = Idx;
520  break;
521  }
522 
523  // The index must not cover any lanes outside \p LaneMask.
524  if ((SubRegMask & ~LaneMask).any())
525  continue;
526 
527  unsigned PopCount = SubRegMask.getNumLanes();
528  PossibleIndexes.push_back(Idx);
529  if (PopCount > BestCover) {
530  BestCover = PopCount;
531  BestIdx = Idx;
532  }
533  }
534 
535  // Abort if we cannot possibly implement the COPY with the given indexes.
536  if (BestIdx == 0)
537  return 0;
538 
539  NeededIndexes.push_back(BestIdx);
540 
541  // Greedy heuristic: Keep iterating keeping the best covering subreg index
542  // each time.
543  LaneBitmask LanesLeft = LaneMask & ~getSubRegIndexLaneMask(BestIdx);
544  while (LanesLeft.any()) {
545  unsigned BestIdx = 0;
546  int BestCover = std::numeric_limits<int>::min();
547  for (unsigned Idx : PossibleIndexes) {
548  LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx);
549  // Early exit if we found a perfect match.
550  if (SubRegMask == LanesLeft) {
551  BestIdx = Idx;
552  break;
553  }
554 
555  // Try to cover as much of the remaining lanes as possible but
556  // as few of the already covered lanes as possible.
557  int Cover = (SubRegMask & LanesLeft).getNumLanes() -
558  (SubRegMask & ~LanesLeft).getNumLanes();
559  if (Cover > BestCover) {
560  BestCover = Cover;
561  BestIdx = Idx;
562  }
563  }
564 
565  if (BestIdx == 0)
566  return 0; // Impossible to handle
567 
568  NeededIndexes.push_back(BestIdx);
569 
570  LanesLeft &= ~getSubRegIndexLaneMask(BestIdx);
571  }
572 
573  return BestIdx;
574 }
575 
576 Register
578  const MachineRegisterInfo *MRI) const {
579  while (true) {
580  const MachineInstr *MI = MRI->getVRegDef(SrcReg);
581  if (!MI->isCopyLike())
582  return SrcReg;
583 
584  Register CopySrcReg;
585  if (MI->isCopy())
586  CopySrcReg = MI->getOperand(1).getReg();
587  else {
588  assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
589  CopySrcReg = MI->getOperand(2).getReg();
590  }
591 
592  if (!CopySrcReg.isVirtual())
593  return CopySrcReg;
594 
595  SrcReg = CopySrcReg;
596  }
597 }
598 
600  Register SrcReg, const MachineRegisterInfo *MRI) const {
601  while (true) {
602  const MachineInstr *MI = MRI->getVRegDef(SrcReg);
603  // Found the real definition, return it if it has a single use.
604  if (!MI->isCopyLike())
605  return MRI->hasOneNonDBGUse(SrcReg) ? SrcReg : Register();
606 
607  Register CopySrcReg;
608  if (MI->isCopy())
609  CopySrcReg = MI->getOperand(1).getReg();
610  else {
611  assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
612  CopySrcReg = MI->getOperand(2).getReg();
613  }
614 
615  // Continue only if the next definition in the chain is for a virtual
616  // register that has a single use.
617  if (!CopySrcReg.isVirtual() || !MRI->hasOneNonDBGUse(CopySrcReg))
618  return Register();
619 
620  SrcReg = CopySrcReg;
621  }
622 }
623 
625  const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
626  assert(!Offset.getScalable() && "Scalable offsets are not handled");
627  DIExpression::appendOffset(Ops, Offset.getFixed());
628 }
629 
630 DIExpression *
632  unsigned PrependFlags,
633  const StackOffset &Offset) const {
634  assert((PrependFlags &
637  "Unsupported prepend flag");
638  SmallVector<uint64_t, 16> OffsetExpr;
639  if (PrependFlags & DIExpression::DerefBefore)
640  OffsetExpr.push_back(dwarf::DW_OP_deref);
641  getOffsetOpcodes(Offset, OffsetExpr);
642  if (PrependFlags & DIExpression::DerefAfter)
643  OffsetExpr.push_back(dwarf::DW_OP_deref);
644  return DIExpression::prependOpcodes(Expr, OffsetExpr,
645  PrependFlags & DIExpression::StackValue,
646  PrependFlags & DIExpression::EntryValue);
647 }
648 
649 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
651 void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex,
652  const TargetRegisterInfo *TRI) {
653  dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
654 }
655 #endif
llvm::LaneBitmask
Definition: LaneBitmask.h:39
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:597
llvm::TargetRegisterInfo::shouldRegionSplitForVirtReg
virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Region split has a high compile time cost especially for large live range.
Definition: TargetRegisterInfo.cpp:68
llvm::TargetRegisterInfo::~TargetRegisterInfo
virtual ~TargetRegisterInfo()
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:499
MathExtras.h
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
TargetFrameLowering.h
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:42
llvm::MachineRegisterInfo::getVRegName
StringRef getVRegName(Register Reg) const
Definition: MachineRegisterInfo.h:428
llvm::printVRegOrUnit
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
Definition: TargetRegisterInfo.cpp:164
DebugInfoMetadata.h
llvm::TargetRegisterClass::isAllocatable
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
Definition: TargetRegisterInfo.h:115
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
Printable.h
llvm::Function
Definition: Function.h:61
llvm::TargetRegisterInfo::dumpReg
static void dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
Definition: TargetRegisterInfo.cpp:651
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::SmallVector< unsigned, 8 >
llvm::SuperRegClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1118
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::LaneBitmask::getNumLanes
unsigned getNumLanes() const
Definition: LaneBitmask.h:75
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::TargetRegisterInfo::getReservedRegs
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
llvm::TargetRegisterInfo::getAllocatableSet
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
Definition: TargetRegisterInfo.cpp:238
llvm::MachineRegisterInfo::getUniqueVRegDef
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:411
llvm::TargetRegisterInfo::getOffsetOpcodes
virtual void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const
Gets the DWARF expression opcodes for Offset.
Definition: TargetRegisterInfo.cpp:624
llvm::TargetRegisterInfo::shouldRealignStack
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
Definition: TargetRegisterInfo.cpp:464
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::Register::stackSlot2Index
static int stackSlot2Index(Register Reg)
Compute the frame index from a register value representing a stack slot.
Definition: Register.h:52
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::TargetRegisterInfo::markSuperRegs
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const
Mark a register and all its aliases as reserved in the given set.
Definition: TargetRegisterInfo.cpp:79
TargetInstrInfo.h
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:90
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:345
getAllocatableSetForRC
static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R)
getAllocatableSetForRC - Toggle the bits that represent allocatable registers for the specific regist...
Definition: TargetRegisterInfo.cpp:230
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::TargetRegisterInfo::isCalleeSavedPhysReg
virtual bool isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
This is a wrapper around getCallPreservedMask().
Definition: TargetRegisterInfo.cpp:446
STLExtras.h
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2559
llvm::TargetRegisterInfo::RegClassInfo
Definition: TargetRegisterInfo.h:235
llvm::MCRegisterInfo::getNumRegUnits
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
Definition: MCRegisterInfo.h:505
RegisterSet
SmallSet< unsigned, 4 > RegisterSet
Definition: Thumb2ITBlockPass.cpp:39
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MCRegisterInfo::getNumSubRegIndices
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
Definition: MCRegisterInfo.h:498
llvm::TargetRegisterClass::getSubClassMask
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
Definition: TargetRegisterInfo.h:156
llvm::LegalityPredicates::any
Predicate any(Predicate P0, Predicate P1)
True iff P0 or P1 are true.
Definition: LegalizerInfo.h:209
llvm::BitMaskClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1216
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
MachineValueType.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
CommandLine.h
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
llvm::TargetRegisterInfo::canRealignStack
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
Definition: TargetRegisterInfo.cpp:460
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:361
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::LLT::getSizeInBits
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:109
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:99
llvm::Register::isStackSlot
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
Definition: Register.h:44
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:900
llvm::TargetRegisterClass::getRawAllocationOrder
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Definition: TargetRegisterInfo.h:197
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
BitVector.h
llvm::LiveRange::size
size_t size() const
Definition: LiveInterval.h:297
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:284
llvm::BitVector
Definition: BitVector.h:74
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
llvm::SuperRegClassIterator
Definition: TargetRegisterInfo.h:1099
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:400
llvm::printRegUnit
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
Definition: TargetRegisterInfo.cpp:141
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::TargetRegisterInfo::regclasses
iterator_range< regclass_iterator > regclasses() const
Definition: TargetRegisterInfo.h:713
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:473
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::cl::opt
Definition: CommandLine.h:1419
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:723
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:228
llvm::DIExpression::StackValue
@ StackValue
Definition: DebugInfoMetadata.h:2755
VirtRegMap.h
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:729
llvm::TargetRegisterInfo::getCommonSuperRegClass
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
Definition: TargetRegisterInfo.cpp:300
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::VirtRegMap::getPhys
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:106
llvm::TargetRegisterInfo::getRegAllocationHints
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Definition: TargetRegisterInfo.cpp:403
llvm::LaneBitmask::any
constexpr bool any() const
Definition: LaneBitmask.h:52
StringExtras.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:440
MCRegisterInfo.h
llvm::StringRef::lower
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:108
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1570
ArrayRef.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:651
llvm::DIExpression::DerefBefore
@ DerefBefore
Definition: DebugInfoMetadata.h:2753
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:39
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:840
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:270
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:641
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::printRegClassOrBank
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
Definition: TargetRegisterInfo.cpp:174
llvm::TargetRegisterInfo::TargetRegisterInfo
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, unsigned Mode=0)
Definition: TargetRegisterInfo.cpp:52
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
Matrix
Live Register Matrix
Definition: LiveRegMatrix.cpp:44
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:156
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:419
llvm::TargetRegisterInfo::composeSubRegIndices
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Definition: TargetRegisterInfo.h:615
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::TargetRegisterInfo::getCoveringSubRegIndexes
bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
Try to find one or more subregister indexes to cover LaneMask.
Definition: TargetRegisterInfo.cpp:505
if
if(llvm_vc STREQUAL "") set(fake_version_inc "$
Definition: CMakeLists.txt:14
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Definition: TargetRegisterInfo.h:297
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
Compiler.h
TargetSubtargetInfo.h
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
llvm::MachineRegisterInfo::getRegAllocationHints
const std::pair< Register, SmallVector< Register, 4 > > & getRegAllocationHints(Register VReg) const
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg.
Definition: MachineRegisterInfo.h:814
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:585
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetRegisterInfo::lookThruSingleUseCopyChain
virtual Register lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const
Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain bac...
Definition: TargetRegisterInfo.cpp:599
Attributes.h
llvm::TargetRegisterInfo::shouldRewriteCopySrc
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
Definition: TargetRegisterInfo.cpp:394
llvm::DIExpression::appendOffset
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
Definition: DebugInfoMetadata.cpp:1210
llvm::DIExpression::prependOpcodes
static DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)
Prepend DIExpr with the given opcodes and optionally turn it into a stack value.
Definition: DebugInfoMetadata.cpp:1329
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::TargetRegisterInfo::lookThruCopyLike
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
Definition: TargetRegisterInfo.cpp:577
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:93
llvm::DIExpression::DerefAfter
@ DerefAfter
Definition: DebugInfoMetadata.h:2754
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:274
MachineFrameInfo.h
firstCommonClass
static const TargetRegisterClass * firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI)
Definition: TargetRegisterInfo.cpp:260
llvm::RegisterBank::getName
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:51
shareSameRegisterFile
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg)
Check if the registers defined by the pair (RegisterClass, SubReg) share the same register file.
Definition: TargetRegisterInfo.cpp:363
Function.h
llvm::MachineRegisterInfo::getRegBankOrNull
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
Definition: MachineRegisterInfo.h:660
llvm::TargetRegisterInfo::getNumRegClasses
unsigned getNumRegClasses() const
Definition: TargetRegisterInfo.h:717
llvm::TargetRegisterInfo::regclass_iterator
const TargetRegisterClass *const * regclass_iterator
Definition: TargetRegisterInfo.h:233
LiveInterval.h
llvm::MCRegUnitRootIterator
MCRegUnitRootIterator enumerates the root registers of a register unit.
Definition: MCRegisterInfo.h:746
llvm::TargetRegisterClass::hasSubClass
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
Definition: TargetRegisterInfo.h:119
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
llvm::Printable
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:37
N
#define N
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::PseudoProbeAttributes::Reserved
@ Reserved
llvm::LiveInterval::reg
Register reg() const
Definition: LiveInterval.h:711
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::TargetRegisterInfoDesc
Extra information, not in MCRegisterDesc, about registers.
Definition: TargetRegisterInfo.h:211
llvm::TargetRegisterInfo::getAllocatableClass
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
Definition: TargetRegisterInfo.cpp:194
llvm::SmallVectorImpl< MCPhysReg >
llvm::BitMaskClassIterator
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
Definition: TargetRegisterInfo.h:1145
HugeSizeForSplit
static cl::opt< unsigned > HugeSizeForSplit("huge-size-for-split", cl::Hidden, cl::desc("A threshold of live range size which may cause " "high compile time cost in global splitting."), cl::init(5000))
llvm::TargetRegisterInfo::checkAllSuperRegsMarked
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well.
Definition: TargetRegisterInfo.cpp:85
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::cl::desc
Definition: CommandLine.h:411
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:211
llvm::TargetRegisterInfo::getSubRegIndexName
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Definition: TargetRegisterInfo.h:351
raw_ostream.h
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
TargetRegisterInfo.h
Debug.h
llvm::DIExpression::EntryValue
@ EntryValue
Definition: DebugInfoMetadata.h:2756
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:471
llvm::TargetRegisterInfo::prependOffsetExpression
DIExpression * prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const
Prepends a DWARF expression for Offset to DIExpression Expr.
Definition: TargetRegisterInfo.cpp:631
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
SmallSet.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40
llvm::LLT
Definition: LowLevelTypeImpl.h:40