LLVM 19.0.0git
TargetRegisterInfo.cpp
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1//==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the TargetRegisterInfo interface.
10//
11//===----------------------------------------------------------------------===//
12
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/SmallSet.h"
29#include "llvm/Config/llvm-config.h"
30#include "llvm/IR/Attributes.h"
32#include "llvm/IR/Function.h"
36#include "llvm/Support/Debug.h"
40#include <cassert>
41#include <utility>
42
43#define DEBUG_TYPE "target-reg-info"
44
45using namespace llvm;
46
48 HugeSizeForSplit("huge-size-for-split", cl::Hidden,
49 cl::desc("A threshold of live range size which may cause "
50 "high compile time cost in global splitting."),
51 cl::init(5000));
52
55 regclass_iterator RCE, const char *const *SRINames,
56 const SubRegCoveredBits *SubIdxRanges, const LaneBitmask *SRILaneMasks,
57 LaneBitmask SRICoveringLanes, const RegClassInfo *const RCIs,
58 const MVT::SimpleValueType *const RCVTLists, unsigned Mode)
59 : InfoDesc(ID), SubRegIndexNames(SRINames), SubRegIdxRanges(SubIdxRanges),
60 SubRegIndexLaneMasks(SRILaneMasks), RegClassBegin(RCB), RegClassEnd(RCE),
61 CoveringLanes(SRICoveringLanes), RCInfos(RCIs), RCVTLists(RCVTLists),
62 HwMode(Mode) {}
63
65
67 const MachineFunction &MF, const LiveInterval &VirtReg) const {
70 MachineInstr *MI = MRI.getUniqueVRegDef(VirtReg.reg());
71 if (MI && TII->isTriviallyReMaterializable(*MI) &&
72 VirtReg.size() > HugeSizeForSplit)
73 return false;
74 return true;
75}
76
78 MCRegister Reg) const {
79 for (MCPhysReg SR : superregs_inclusive(Reg))
80 RegisterSet.set(SR);
81}
82
84 ArrayRef<MCPhysReg> Exceptions) const {
85 // Check that all super registers of reserved regs are reserved as well.
86 BitVector Checked(getNumRegs());
87 for (unsigned Reg : RegisterSet.set_bits()) {
88 if (Checked[Reg])
89 continue;
90 for (MCPhysReg SR : superregs(Reg)) {
91 if (!RegisterSet[SR] && !is_contained(Exceptions, Reg)) {
92 dbgs() << "Error: Super register " << printReg(SR, this)
93 << " of reserved register " << printReg(Reg, this)
94 << " is not reserved.\n";
95 return false;
96 }
97
98 // We transitively check superregs. So we can remember this for later
99 // to avoid compiletime explosion in deep register hierarchies.
100 Checked.set(SR);
101 }
102 }
103 return true;
104}
105
106namespace llvm {
107
109 unsigned SubIdx, const MachineRegisterInfo *MRI) {
110 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {
111 if (!Reg)
112 OS << "$noreg";
113 else if (Register::isStackSlot(Reg))
114 OS << "SS#" << Register::stackSlot2Index(Reg);
115 else if (Reg.isVirtual()) {
116 StringRef Name = MRI ? MRI->getVRegName(Reg) : "";
117 if (Name != "") {
118 OS << '%' << Name;
119 } else {
120 OS << '%' << Register::virtReg2Index(Reg);
121 }
122 } else if (!TRI)
123 OS << '$' << "physreg" << Reg;
124 else if (Reg < TRI->getNumRegs()) {
125 OS << '$';
126 printLowerCase(TRI->getName(Reg), OS);
127 } else
128 llvm_unreachable("Register kind is unsupported.");
129
130 if (SubIdx) {
131 if (TRI)
132 OS << ':' << TRI->getSubRegIndexName(SubIdx);
133 else
134 OS << ":sub(" << SubIdx << ')';
135 }
136 });
137}
138
140 return Printable([Unit, TRI](raw_ostream &OS) {
141 // Generic printout when TRI is missing.
142 if (!TRI) {
143 OS << "Unit~" << Unit;
144 return;
145 }
146
147 // Check for invalid register units.
148 if (Unit >= TRI->getNumRegUnits()) {
149 OS << "BadUnit~" << Unit;
150 return;
151 }
152
153 // Normal units have at least one root.
154 MCRegUnitRootIterator Roots(Unit, TRI);
155 assert(Roots.isValid() && "Unit has no roots.");
156 OS << TRI->getName(*Roots);
157 for (++Roots; Roots.isValid(); ++Roots)
158 OS << '~' << TRI->getName(*Roots);
159 });
160}
161
163 return Printable([Unit, TRI](raw_ostream &OS) {
164 if (Register::isVirtualRegister(Unit)) {
165 OS << '%' << Register::virtReg2Index(Unit);
166 } else {
167 OS << printRegUnit(Unit, TRI);
168 }
169 });
170}
171
173 const TargetRegisterInfo *TRI) {
174 return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
175 if (RegInfo.getRegClassOrNull(Reg))
176 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
177 else if (RegInfo.getRegBankOrNull(Reg))
178 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
179 else {
180 OS << "_";
181 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
182 "Generic registers must have a valid type");
183 }
184 });
185}
186
187} // end namespace llvm
188
189/// getAllocatableClass - Return the maximal subclass of the given register
190/// class that is alloctable, or NULL.
193 if (!RC || RC->isAllocatable())
194 return RC;
195
196 for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
197 ++It) {
198 const TargetRegisterClass *SubRC = getRegClass(It.getID());
199 if (SubRC->isAllocatable())
200 return SubRC;
201 }
202 return nullptr;
203}
204
205/// getMinimalPhysRegClass - Returns the Register Class of a physical
206/// register of the given type, picking the most sub register class of
207/// the right type that contains this physreg.
211 "reg must be a physical register");
212
213 // Pick the most sub register class of the right type that contains
214 // this physreg.
215 const TargetRegisterClass* BestRC = nullptr;
216 for (const TargetRegisterClass* RC : regclasses()) {
217 if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
218 RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
219 BestRC = RC;
220 }
221
222 assert(BestRC && "Couldn't find the register class");
223 return BestRC;
224}
225
229 "reg must be a physical register");
230
231 // Pick the most sub register class of the right type that contains
232 // this physreg.
233 const TargetRegisterClass *BestRC = nullptr;
234 for (const TargetRegisterClass *RC : regclasses()) {
235 if ((!Ty.isValid() || isTypeLegalForClass(*RC, Ty)) && RC->contains(reg) &&
236 (!BestRC || BestRC->hasSubClass(RC)))
237 BestRC = RC;
238 }
239
240 return BestRC;
241}
242
243/// getAllocatableSetForRC - Toggle the bits that represent allocatable
244/// registers for the specific register class.
246 const TargetRegisterClass *RC, BitVector &R){
247 assert(RC->isAllocatable() && "invalid for nonallocatable sets");
249 for (MCPhysReg PR : Order)
250 R.set(PR);
251}
252
254 const TargetRegisterClass *RC) const {
255 BitVector Allocatable(getNumRegs());
256 if (RC) {
257 // A register class with no allocatable subclass returns an empty set.
258 const TargetRegisterClass *SubClass = getAllocatableClass(RC);
259 if (SubClass)
260 getAllocatableSetForRC(MF, SubClass, Allocatable);
261 } else {
262 for (const TargetRegisterClass *C : regclasses())
263 if (C->isAllocatable())
264 getAllocatableSetForRC(MF, C, Allocatable);
265 }
266
267 // Mask out the reserved registers
268 const MachineRegisterInfo &MRI = MF.getRegInfo();
269 const BitVector &Reserved = MRI.getReservedRegs();
270 Allocatable.reset(Reserved);
271
272 return Allocatable;
273}
274
275static inline
277 const uint32_t *B,
278 const TargetRegisterInfo *TRI) {
279 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
280 if (unsigned Common = *A++ & *B++)
281 return TRI->getRegClass(I + llvm::countr_zero(Common));
282 return nullptr;
283}
284
287 const TargetRegisterClass *B) const {
288 // First take care of the trivial cases.
289 if (A == B)
290 return A;
291 if (!A || !B)
292 return nullptr;
293
294 // Register classes are ordered topologically, so the largest common
295 // sub-class it the common sub-class with the smallest ID.
296 return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);
297}
298
301 const TargetRegisterClass *B,
302 unsigned Idx) const {
303 assert(A && B && "Missing register class");
304 assert(Idx && "Bad sub-register index");
305
306 // Find Idx in the list of super-register indices.
307 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
308 if (RCI.getSubReg() == Idx)
309 // The bit mask contains all register classes that are projected into B
310 // by Idx. Find a class that is also a sub-class of A.
311 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
312 return nullptr;
313}
314
316getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
317 const TargetRegisterClass *RCB, unsigned SubB,
318 unsigned &PreA, unsigned &PreB) const {
319 assert(RCA && SubA && RCB && SubB && "Invalid arguments");
320
321 // Search all pairs of sub-register indices that project into RCA and RCB
322 // respectively. This is quadratic, but usually the sets are very small. On
323 // most targets like X86, there will only be a single sub-register index
324 // (e.g., sub_16bit projecting into GR16).
325 //
326 // The worst case is a register class like DPR on ARM.
327 // We have indices dsub_0..dsub_7 projecting into that class.
328 //
329 // It is very common that one register class is a sub-register of the other.
330 // Arrange for RCA to be the larger register so the answer will be found in
331 // the first iteration. This makes the search linear for the most common
332 // case.
333 const TargetRegisterClass *BestRC = nullptr;
334 unsigned *BestPreA = &PreA;
335 unsigned *BestPreB = &PreB;
336 if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
337 std::swap(RCA, RCB);
338 std::swap(SubA, SubB);
339 std::swap(BestPreA, BestPreB);
340 }
341
342 // Also terminate the search one we have found a register class as small as
343 // RCA.
344 unsigned MinSize = getRegSizeInBits(*RCA);
345
346 for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
347 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
348 for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
349 // Check if a common super-register class exists for this index pair.
350 const TargetRegisterClass *RC =
351 firstCommonClass(IA.getMask(), IB.getMask(), this);
352 if (!RC || getRegSizeInBits(*RC) < MinSize)
353 continue;
354
355 // The indexes must compose identically: PreA+SubA == PreB+SubB.
356 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
357 if (FinalA != FinalB)
358 continue;
359
360 // Is RC a better candidate than BestRC?
361 if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))
362 continue;
363
364 // Yes, RC is the smallest super-register seen so far.
365 BestRC = RC;
366 *BestPreA = IA.getSubReg();
367 *BestPreB = IB.getSubReg();
368
369 // Bail early if we reached MinSize. We won't find a better candidate.
370 if (getRegSizeInBits(*BestRC) == MinSize)
371 return BestRC;
372 }
373 }
374 return BestRC;
375}
376
377/// Check if the registers defined by the pair (RegisterClass, SubReg)
378/// share the same register file.
380 const TargetRegisterClass *DefRC,
381 unsigned DefSubReg,
382 const TargetRegisterClass *SrcRC,
383 unsigned SrcSubReg) {
384 // Same register class.
385 if (DefRC == SrcRC)
386 return true;
387
388 // Both operands are sub registers. Check if they share a register class.
389 unsigned SrcIdx, DefIdx;
390 if (SrcSubReg && DefSubReg) {
391 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
392 SrcIdx, DefIdx) != nullptr;
393 }
394
395 // At most one of the register is a sub register, make it Src to avoid
396 // duplicating the test.
397 if (!SrcSubReg) {
398 std::swap(DefSubReg, SrcSubReg);
399 std::swap(DefRC, SrcRC);
400 }
401
402 // One of the register is a sub register, check if we can get a superclass.
403 if (SrcSubReg)
404 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
405
406 // Plain copy.
407 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
408}
409
411 unsigned DefSubReg,
412 const TargetRegisterClass *SrcRC,
413 unsigned SrcSubReg) const {
414 // If this source does not incur a cross register bank copy, use it.
415 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
416}
417
418// Compute target-independent register allocator hints to help eliminate copies.
420 Register VirtReg, ArrayRef<MCPhysReg> Order,
422 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
423 const MachineRegisterInfo &MRI = MF.getRegInfo();
424 const std::pair<unsigned, SmallVector<Register, 4>> &Hints_MRI =
425 MRI.getRegAllocationHints(VirtReg);
426
427 SmallSet<Register, 32> HintedRegs;
428 // First hint may be a target hint.
429 bool Skip = (Hints_MRI.first != 0);
430 for (auto Reg : Hints_MRI.second) {
431 if (Skip) {
432 Skip = false;
433 continue;
434 }
435
436 // Target-independent hints are either a physical or a virtual register.
437 Register Phys = Reg;
438 if (VRM && Phys.isVirtual())
439 Phys = VRM->getPhys(Phys);
440
441 // Don't add the same reg twice (Hints_MRI may contain multiple virtual
442 // registers allocated to the same physreg).
443 if (!HintedRegs.insert(Phys).second)
444 continue;
445 // Check that Phys is a valid hint in VirtReg's register class.
446 if (!Phys.isPhysical())
447 continue;
448 if (MRI.isReserved(Phys))
449 continue;
450 // Check that Phys is in the allocation order. We shouldn't heed hints
451 // from VirtReg's register class if they aren't in the allocation order. The
452 // target probably has a reason for removing the register.
453 if (!is_contained(Order, Phys))
454 continue;
455
456 // All clear, tell the register allocator to prefer this register.
457 Hints.push_back(Phys);
458 }
459 return false;
460}
461
463 MCRegister PhysReg, const MachineFunction &MF) const {
464 if (PhysReg == 0)
465 return false;
466 const uint32_t *callerPreservedRegs =
468 if (callerPreservedRegs) {
470 "Expected physical register");
471 return (callerPreservedRegs[PhysReg / 32] >> PhysReg % 32) & 1;
472 }
473 return false;
474}
475
477 return MF.getFrameInfo().isStackRealignable();
478}
479
481 return MF.getFrameInfo().shouldRealignStack();
482}
483
485 const uint32_t *mask1) const {
486 unsigned N = (getNumRegs()+31) / 32;
487 for (unsigned I = 0; I < N; ++I)
488 if ((mask0[I] & mask1[I]) != mask0[I])
489 return false;
490 return true;
491}
492
495 const MachineRegisterInfo &MRI) const {
496 const TargetRegisterClass *RC{};
497 if (Reg.isPhysical()) {
498 // The size is not directly available for physical registers.
499 // Instead, we need to access a register class that contains Reg and
500 // get the size of that register class.
501 RC = getMinimalPhysRegClass(Reg);
502 assert(RC && "Unable to deduce the register class");
503 return getRegSizeInBits(*RC);
504 }
505 LLT Ty = MRI.getType(Reg);
506 if (Ty.isValid())
507 return Ty.getSizeInBits();
508
509 // Since Reg is not a generic register, it may have a register class.
510 RC = MRI.getRegClass(Reg);
511 assert(RC && "Unable to deduce the register class");
512 return getRegSizeInBits(*RC);
513}
514
517 LaneBitmask LaneMask, SmallVectorImpl<unsigned> &NeededIndexes) const {
518 SmallVector<unsigned, 8> PossibleIndexes;
519 unsigned BestIdx = 0;
520 unsigned BestCover = 0;
521
522 for (unsigned Idx = 1, E = getNumSubRegIndices(); Idx < E; ++Idx) {
523 // Is this index even compatible with the given class?
524 if (getSubClassWithSubReg(RC, Idx) != RC)
525 continue;
527 // Early exit if we found a perfect match.
528 if (SubRegMask == LaneMask) {
529 BestIdx = Idx;
530 break;
531 }
532
533 // The index must not cover any lanes outside \p LaneMask.
534 if ((SubRegMask & ~LaneMask).any())
535 continue;
536
537 unsigned PopCount = SubRegMask.getNumLanes();
538 PossibleIndexes.push_back(Idx);
539 if (PopCount > BestCover) {
540 BestCover = PopCount;
541 BestIdx = Idx;
542 }
543 }
544
545 // Abort if we cannot possibly implement the COPY with the given indexes.
546 if (BestIdx == 0)
547 return false;
548
549 NeededIndexes.push_back(BestIdx);
550
551 // Greedy heuristic: Keep iterating keeping the best covering subreg index
552 // each time.
553 LaneBitmask LanesLeft = LaneMask & ~getSubRegIndexLaneMask(BestIdx);
554 while (LanesLeft.any()) {
555 unsigned BestIdx = 0;
556 int BestCover = std::numeric_limits<int>::min();
557 for (unsigned Idx : PossibleIndexes) {
559 // Early exit if we found a perfect match.
560 if (SubRegMask == LanesLeft) {
561 BestIdx = Idx;
562 break;
563 }
564
565 // Do not cover already-covered lanes to avoid creating cycles
566 // in copy bundles (= bundle contains copies that write to the
567 // registers).
568 if ((SubRegMask & ~LanesLeft).any())
569 continue;
570
571 // Try to cover as many of the remaining lanes as possible.
572 const int Cover = (SubRegMask & LanesLeft).getNumLanes();
573 if (Cover > BestCover) {
574 BestCover = Cover;
575 BestIdx = Idx;
576 }
577 }
578
579 if (BestIdx == 0)
580 return false; // Impossible to handle
581
582 NeededIndexes.push_back(BestIdx);
583
584 LanesLeft &= ~getSubRegIndexLaneMask(BestIdx);
585 }
586
587 return BestIdx;
588}
589
592 "This is not a subregister index");
593 return SubRegIdxRanges[HwMode * getNumSubRegIndices() + Idx].Size;
594}
595
598 "This is not a subregister index");
599 return SubRegIdxRanges[HwMode * getNumSubRegIndices() + Idx].Offset;
600}
601
604 const MachineRegisterInfo *MRI) const {
605 while (true) {
606 const MachineInstr *MI = MRI->getVRegDef(SrcReg);
607 if (!MI->isCopyLike())
608 return SrcReg;
609
610 Register CopySrcReg;
611 if (MI->isCopy())
612 CopySrcReg = MI->getOperand(1).getReg();
613 else {
614 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
615 CopySrcReg = MI->getOperand(2).getReg();
616 }
617
618 if (!CopySrcReg.isVirtual())
619 return CopySrcReg;
620
621 SrcReg = CopySrcReg;
622 }
623}
624
626 Register SrcReg, const MachineRegisterInfo *MRI) const {
627 while (true) {
628 const MachineInstr *MI = MRI->getVRegDef(SrcReg);
629 // Found the real definition, return it if it has a single use.
630 if (!MI->isCopyLike())
631 return MRI->hasOneNonDBGUse(SrcReg) ? SrcReg : Register();
632
633 Register CopySrcReg;
634 if (MI->isCopy())
635 CopySrcReg = MI->getOperand(1).getReg();
636 else {
637 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
638 CopySrcReg = MI->getOperand(2).getReg();
639 }
640
641 // Continue only if the next definition in the chain is for a virtual
642 // register that has a single use.
643 if (!CopySrcReg.isVirtual() || !MRI->hasOneNonDBGUse(CopySrcReg))
644 return Register();
645
646 SrcReg = CopySrcReg;
647 }
648}
649
651 const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
652 assert(!Offset.getScalable() && "Scalable offsets are not handled");
653 DIExpression::appendOffset(Ops, Offset.getFixed());
654}
655
658 unsigned PrependFlags,
659 const StackOffset &Offset) const {
660 assert((PrependFlags &
663 "Unsupported prepend flag");
664 SmallVector<uint64_t, 16> OffsetExpr;
665 if (PrependFlags & DIExpression::DerefBefore)
666 OffsetExpr.push_back(dwarf::DW_OP_deref);
667 getOffsetOpcodes(Offset, OffsetExpr);
668 if (PrependFlags & DIExpression::DerefAfter)
669 OffsetExpr.push_back(dwarf::DW_OP_deref);
670 return DIExpression::prependOpcodes(Expr, OffsetExpr,
671 PrependFlags & DIExpression::StackValue,
672 PrependFlags & DIExpression::EntryValue);
673}
674
675#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
677void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex,
678 const TargetRegisterInfo *TRI) {
679 dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
680}
681#endif
unsigned const MachineRegisterInfo * MRI
This file contains the simple types necessary to represent the attributes associated with functions a...
This file implements the BitVector class.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:537
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file contains constants used for implementing Dwarf debug support.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
Live Register Matrix
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
if(VerifyEach)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
raw_pwrite_stream & OS
This file defines the SmallSet class.
This file contains some functions that are useful when dealing with strings.
static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R)
getAllocatableSetForRC - Toggle the bits that represent allocatable registers for the specific regist...
static const TargetRegisterClass * firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI)
static cl::opt< unsigned > HugeSizeForSplit("huge-size-for-split", cl::Hidden, cl::desc("A threshold of live range size which may cause " "high compile time cost in global splitting."), cl::init(5000))
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg)
Check if the registers defined by the pair (RegisterClass, SubReg) share the same register file.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
BitVector & reset()
Definition: BitVector.h:392
BitVector & set()
Definition: BitVector.h:351
DWARF expression.
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
static DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)
Prepend DIExpr with the given opcodes and optionally turn it into a stack value.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:264
constexpr bool isValid() const
Definition: LowLevelType.h:145
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:193
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:687
Register reg() const
Definition: LiveInterval.h:718
size_t size() const
Definition: LiveInterval.h:305
MCRegUnitRootIterator enumerates the root registers of a register unit.
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
iterator_range< MCSuperRegIterator > superregs(MCRegister Reg) const
Return an iterator range over all super-registers of Reg, excluding Reg.
iterator_range< MCSuperRegIterator > superregs_inclusive(MCRegister Reg) const
Return an iterator range over all super-registers of Reg, including Reg.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Machine Value Type.
bool shouldRealignStack() const
Return true if stack realignment is forced by function attributes or if the stack alignment.
bool isStackRealignable() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:49
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static constexpr bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful to be able to store a non-negative frame index in a variable tha...
Definition: Register.h:44
static int stackSlot2Index(Register Reg)
Compute the frame index from a register value representing a stack slot.
Definition: Register.h:52
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:179
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string lower() const
Definition: StringRef.cpp:111
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
TargetInstrInfo - Interface to description of machine instruction set.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const TargetRegisterClass *const * regclass_iterator
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
iterator_range< regclass_iterator > regclasses() const
virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Region split has a high compile time cost especially for large live range.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const
Mark a register and all its aliases as reserved in the given set.
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
virtual Register lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const
Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain bac...
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
static void dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const SubRegCoveredBits *SubIdxRanges, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, const MVT::SimpleValueType *const RCVTLists, unsigned Mode=0)
DIExpression * prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const
Prepends a DWARF expression for Offset to DIExpression Expr.
virtual bool isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
This is a wrapper around getCallPreservedMask().
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
Try to find one or more subregister indexes to cover LaneMask.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
virtual void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const
Gets the DWARF expression opcodes for Offset.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
virtual const TargetInstrInfo * getInstrInfo() const
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:105
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: bit.h:215
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1879
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:860
#define N
constexpr bool any() const
Definition: LaneBitmask.h:53
unsigned getNumLanes() const
Definition: LaneBitmask.h:76
Extra information, not in MCRegisterDesc, about registers.
SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg index, -1 in any being invalid...