LLVM  13.0.0git
NVPTXTargetTransformInfo.h
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1 //===-- NVPTXTargetTransformInfo.h - NVPTX specific TTI ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file a TargetTransformInfo::Concept conforming object specific to the
10 /// NVPTX target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
18 
19 #include "NVPTXTargetMachine.h"
24 
25 namespace llvm {
26 
27 class NVPTXTTIImpl : public BasicTTIImplBase<NVPTXTTIImpl> {
29  typedef TargetTransformInfo TTI;
30  friend BaseT;
31 
32  const NVPTXSubtarget *ST;
33  const NVPTXTargetLowering *TLI;
34 
35  const NVPTXSubtarget *getST() const { return ST; };
36  const NVPTXTargetLowering *getTLI() const { return TLI; };
37 
38 public:
39  explicit NVPTXTTIImpl(const NVPTXTargetMachine *TM, const Function &F)
40  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl()),
41  TLI(ST->getTargetLowering()) {}
42 
43  bool hasBranchDivergence() { return true; }
44 
45  bool isSourceOfDivergence(const Value *V);
46 
47  unsigned getFlatAddressSpace() const {
49  }
50 
52  IntrinsicInst &II) const;
53 
54  // Loads and stores can be vectorized if the alignment is at least as big as
55  // the load/store we want to vectorize.
56  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
57  unsigned AddrSpace) const {
58  return Alignment >= ChainSizeInBytes;
59  }
60  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
61  unsigned AddrSpace) const {
62  return isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment, AddrSpace);
63  }
64 
65  // NVPTX has infinite registers of all kinds, but the actual machine doesn't.
66  // We conservatively return 1 here which is just enough to enable the
67  // vectorizers but disables heuristics based on the number of registers.
68  // FIXME: Return a more reasonable number, while keeping an eye on
69  // LoopVectorizer's unrolling heuristics.
70  unsigned getNumberOfRegisters(bool Vector) const { return 1; }
71 
72  // Only <2 x half> should be vectorized, so always return 32 for the vector
73  // register size.
75  return TypeSize::getFixed(32);
76  }
77  unsigned getMinVectorRegisterBitWidth() const { return 32; }
78 
79  // We don't want to prevent inlining because of target-cpu and -features
80  // attributes that were added to newer versions of LLVM/Clang: There are
81  // no incompatible functions in PTX, ptxas will throw errors in such cases.
82  bool areInlineCompatible(const Function *Caller,
83  const Function *Callee) const {
84  return true;
85  }
86 
87  // Increase the inlining cost threshold by a factor of 5, reflecting that
88  // calls are particularly expensive in NVPTX.
89  unsigned getInliningThresholdMultiplier() { return 5; }
90 
92  unsigned Opcode, Type *Ty,
99  const Instruction *CxtI = nullptr);
100 
103 
106 
107  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) {
108  // Volatile loads/stores are only supported for shared and global address
109  // spaces, or for generic AS that maps to them.
110  if (!(AddrSpace == llvm::ADDRESS_SPACE_GENERIC ||
111  AddrSpace == llvm::ADDRESS_SPACE_GLOBAL ||
112  AddrSpace == llvm::ADDRESS_SPACE_SHARED))
113  return false;
114 
115  switch(I->getOpcode()){
116  default:
117  return false;
118  case Instruction::Load:
119  case Instruction::Store:
120  return true;
121  }
122  }
123 };
124 
125 } // end namespace llvm
126 
127 #endif
llvm::InstructionCost
Definition: InstructionCost.h:26
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:210
llvm
Definition: AllocatorList.h:23
llvm::NVPTXTTIImpl::hasBranchDivergence
bool hasBranchDivergence()
Definition: NVPTXTargetTransformInfo.h:43
llvm::Function
Definition: Function.h:61
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:167
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:443
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::NVPTXTTIImpl::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Definition: NVPTXTargetTransformInfo.h:47
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:529
llvm::Optional
Definition: APInt.h:33
llvm::NVPTXTTIImpl::NVPTXTTIImpl
NVPTXTTIImpl(const NVPTXTargetMachine *TM, const Function &F)
Definition: NVPTXTargetTransformInfo.h:39
llvm::NVPTXTargetMachine
NVPTXTargetMachine.
Definition: NVPTXTargetMachine.h:24
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:48
TargetLowering.h
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:908
llvm::ADDRESS_SPACE_GLOBAL
@ ADDRESS_SPACE_GLOBAL
Definition: NVPTXBaseInfo.h:23
llvm::Instruction
Definition: Instruction.h:45
llvm::NVPTXTTIImpl::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: NVPTXTargetTransformInfo.h:82
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:284
llvm::NVPTXSubtarget
Definition: NVPTXSubtarget.h:31
llvm::NVPTXTTIImpl
Definition: NVPTXTargetTransformInfo.h:27
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:423
NVPTXBaseInfo.h
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:908
llvm::ADDRESS_SPACE_SHARED
@ ADDRESS_SPACE_SHARED
Definition: NVPTXBaseInfo.h:24
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:76
llvm::NVPTXTTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(bool Vector) const
Definition: NVPTXTargetTransformInfo.h:70
llvm::NVPTXTTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: NVPTXTargetTransformInfo.cpp:371
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:900
llvm::NVPTXTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: NVPTXTargetTransformInfo.cpp:416
llvm::NVPTXTTIImpl::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: NVPTXTargetTransformInfo.h:60
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:767
llvm::ADDRESS_SPACE_GENERIC
@ ADDRESS_SPACE_GENERIC
Definition: NVPTXBaseInfo.h:22
llvm::NVPTXTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: NVPTXTargetTransformInfo.h:74
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:901
llvm::NVPTXTargetLowering
Definition: NVPTXISelLowering.h:440
llvm::NVPTXTTIImpl::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier()
Definition: NVPTXTargetTransformInfo.h:89
llvm::TypeSize
Definition: TypeSize.h:417
NVPTXTargetMachine.h
llvm::NVPTXTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
Definition: NVPTXTargetTransformInfo.cpp:404
llvm::NVPTXTTIImpl::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace)
Definition: NVPTXTargetTransformInfo.h:107
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::NVPTXTTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: NVPTXTargetTransformInfo.h:77
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:929
TargetTransformInfo.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::NVPTXTTIImpl::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: NVPTXTargetTransformInfo.cpp:364
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
BasicTTIImpl.h
llvm::NVPTXTTIImpl::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V)
Definition: NVPTXTargetTransformInfo.cpp:71
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:211
llvm::NVPTXTTIImpl::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: NVPTXTargetTransformInfo.h:56