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16 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
41 TLI(ST->getTargetLowering()) {}
62 unsigned AddrSpace)
const {
63 return Alignment >= ChainSizeInBytes;
66 unsigned AddrSpace)
const {
120 switch(
I->getOpcode()){
This is an optimization pass for GlobalISel generic memory operations.
bool hasBranchDivergence()
Represents a single loop in the control flow graph.
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
The main scalar evolution driver.
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
The instances of the Type class are immutable: once they are created, they are never changed.
unsigned getFlatAddressSpace() const
NVPTXTTIImpl(const NVPTXTargetMachine *TM, const Function &F)
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
This struct is a compact representation of a valid (non-zero power of two) alignment.
static TypeSize getFixed(ScalarTy MinVal)
Base class which can be used to help build a TTI implementation.
unsigned getNumberOfRegisters(bool Vector) const
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
static const Function * getParent(const Value *V)
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
unsigned getInliningThresholdMultiplier()
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace)
The core instruction combiner logic.
A wrapper class for inspecting calls to intrinsic functions.
unsigned getMinVectorRegisterBitWidth() const
const char LLVMTargetMachineRef TM
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
bool isSourceOfDivergence(const Value *V)
LLVM Value Representation.
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const