LLVM 19.0.0git
TargetTransformInfoImpl.h
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1//===- TargetTransformInfoImpl.h --------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file provides helpers for the implementation of
10/// a TargetTransformInfo-conforming class.
11///
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
15#define LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
16
20#include "llvm/IR/DataLayout.h"
23#include "llvm/IR/Operator.h"
25#include <optional>
26#include <utility>
27
28namespace llvm {
29
30class Function;
31
32/// Base class for use as a mix-in that aids implementing
33/// a TargetTransformInfo-compatible class.
35protected:
37
38 const DataLayout &DL;
39
41
42public:
43 // Provide value semantics. MSVC requires that we spell all of these out.
46
47 const DataLayout &getDataLayout() const { return DL; }
48
49 InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr,
52 // In the basic model, we just assume that all-constant GEPs will be folded
53 // into their uses via addressing modes.
54 for (const Value *Operand : Operands)
55 if (!isa<Constant>(Operand))
56 return TTI::TCC_Basic;
57
58 return TTI::TCC_Free;
59 }
60
62 unsigned &JTSize,
64 BlockFrequencyInfo *BFI) const {
65 (void)PSI;
66 (void)BFI;
67 JTSize = 0;
68 return SI.getNumCases();
69 }
70
71 unsigned getInliningThresholdMultiplier() const { return 1; }
74 return 8;
75 }
76 unsigned adjustInliningThreshold(const CallBase *CB) const { return 0; }
77 unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const {
78 return 0;
79 };
80
81 int getInlinerVectorBonusPercent() const { return 150; }
82
84 return TTI::TCC_Expensive;
85 }
86
88 return 64;
89 }
90
91 // Although this default value is arbitrary, it is not random. It is assumed
92 // that a condition that evaluates the same way by a higher percentage than
93 // this is best represented as control flow. Therefore, the default value N
94 // should be set such that the win from N% correct executions is greater than
95 // the loss from (100 - N)% mispredicted executions for the majority of
96 // intended targets.
98 return BranchProbability(99, 100);
99 }
100
101 bool hasBranchDivergence(const Function *F = nullptr) const { return false; }
102
103 bool isSourceOfDivergence(const Value *V) const { return false; }
104
105 bool isAlwaysUniform(const Value *V) const { return false; }
106
107 bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const {
108 return false;
109 }
110
111 bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const {
112 return true;
113 }
114
115 unsigned getFlatAddressSpace() const { return -1; }
116
118 Intrinsic::ID IID) const {
119 return false;
120 }
121
122 bool isNoopAddrSpaceCast(unsigned, unsigned) const { return false; }
124 return AS == 0;
125 };
126
127 unsigned getAssumedAddrSpace(const Value *V) const { return -1; }
128
129 bool isSingleThreaded() const { return false; }
130
131 std::pair<const Value *, unsigned>
133 return std::make_pair(nullptr, -1);
134 }
135
137 Value *NewV) const {
138 return nullptr;
139 }
140
141 bool isLoweredToCall(const Function *F) const {
142 assert(F && "A concrete function must be provided to this routine.");
143
144 // FIXME: These should almost certainly not be handled here, and instead
145 // handled with the help of TLI or the target itself. This was largely
146 // ported from existing analysis heuristics here so that such refactorings
147 // can take place in the future.
148
149 if (F->isIntrinsic())
150 return false;
151
152 if (F->hasLocalLinkage() || !F->hasName())
153 return true;
154
155 StringRef Name = F->getName();
156
157 // These will all likely lower to a single selection DAG node.
158 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl" ||
159 Name == "fabs" || Name == "fabsf" || Name == "fabsl" || Name == "sin" ||
160 Name == "fmin" || Name == "fminf" || Name == "fminl" ||
161 Name == "fmax" || Name == "fmaxf" || Name == "fmaxl" ||
162 Name == "sinf" || Name == "sinl" || Name == "cos" || Name == "cosf" ||
163 Name == "cosl" || Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl")
164 return false;
165
166 // These are all likely to be optimized into something smaller.
167 if (Name == "pow" || Name == "powf" || Name == "powl" || Name == "exp2" ||
168 Name == "exp2l" || Name == "exp2f" || Name == "floor" ||
169 Name == "floorf" || Name == "ceil" || Name == "round" ||
170 Name == "ffs" || Name == "ffsl" || Name == "abs" || Name == "labs" ||
171 Name == "llabs")
172 return false;
173
174 return true;
175 }
176
179 HardwareLoopInfo &HWLoopInfo) const {
180 return false;
181 }
182
183 bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const { return false; }
184
186 getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const {
188 }
189
190 std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
191 IntrinsicInst &II) const {
192 return std::nullopt;
193 }
194
195 std::optional<Value *>
197 APInt DemandedMask, KnownBits &Known,
198 bool &KnownBitsComputed) const {
199 return std::nullopt;
200 }
201
203 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
204 APInt &UndefElts2, APInt &UndefElts3,
205 std::function<void(Instruction *, unsigned, APInt, APInt &)>
206 SimplifyAndSetOp) const {
207 return std::nullopt;
208 }
209
212 OptimizationRemarkEmitter *) const {}
213
215 TTI::PeelingPreferences &) const {}
216
217 bool isLegalAddImmediate(int64_t Imm) const { return false; }
218
219 bool isLegalICmpImmediate(int64_t Imm) const { return false; }
220
221 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
222 bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
223 Instruction *I = nullptr) const {
224 // Guess that only reg and reg+reg addressing is allowed. This heuristic is
225 // taken from the implementation of LSR.
226 return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1);
227 }
228
229 bool isLSRCostLess(const TTI::LSRCost &C1, const TTI::LSRCost &C2) const {
230 return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds,
231 C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
232 std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds,
233 C2.ScaleCost, C2.ImmCost, C2.SetupCost);
234 }
235
236 bool isNumRegsMajorCostOfLSR() const { return true; }
237
238 bool shouldFoldTerminatingConditionAfterLSR() const { return false; }
239
240 bool isProfitableLSRChainElement(Instruction *I) const { return false; }
241
242 bool canMacroFuseCmp() const { return false; }
243
246 TargetLibraryInfo *LibInfo) const {
247 return false;
248 }
249
252 return TTI::AMK_None;
253 }
254
255 bool isLegalMaskedStore(Type *DataType, Align Alignment) const {
256 return false;
257 }
258
259 bool isLegalMaskedLoad(Type *DataType, Align Alignment) const {
260 return false;
261 }
262
263 bool isLegalNTStore(Type *DataType, Align Alignment) const {
264 // By default, assume nontemporal memory stores are available for stores
265 // that are aligned and have a size that is a power of 2.
266 unsigned DataSize = DL.getTypeStoreSize(DataType);
267 return Alignment >= DataSize && isPowerOf2_32(DataSize);
268 }
269
270 bool isLegalNTLoad(Type *DataType, Align Alignment) const {
271 // By default, assume nontemporal memory loads are available for loads that
272 // are aligned and have a size that is a power of 2.
273 unsigned DataSize = DL.getTypeStoreSize(DataType);
274 return Alignment >= DataSize && isPowerOf2_32(DataSize);
275 }
276
277 bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const {
278 return false;
279 }
280
281 bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
282 return false;
283 }
284
285 bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
286 return false;
287 }
288
289 bool forceScalarizeMaskedGather(VectorType *DataType, Align Alignment) const {
290 return false;
291 }
292
294 Align Alignment) const {
295 return false;
296 }
297
298 bool isLegalMaskedCompressStore(Type *DataType) const { return false; }
299
300 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
301 const SmallBitVector &OpcodeMask) const {
302 return false;
303 }
304
305 bool isLegalMaskedExpandLoad(Type *DataType) const { return false; }
306
307 bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const {
308 return false;
309 }
310
311 bool enableOrderedReductions() const { return false; }
312
313 bool hasDivRemOp(Type *DataType, bool IsSigned) const { return false; }
314
315 bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const {
316 return false;
317 }
318
319 bool prefersVectorizedAddressing() const { return true; }
320
322 int64_t BaseOffset, bool HasBaseReg,
323 int64_t Scale,
324 unsigned AddrSpace) const {
325 // Guess that all legal addressing mode are free.
326 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
327 AddrSpace))
328 return 0;
329 return -1;
330 }
331
332 bool LSRWithInstrQueries() const { return false; }
333
334 bool isTruncateFree(Type *Ty1, Type *Ty2) const { return false; }
335
336 bool isProfitableToHoist(Instruction *I) const { return true; }
337
338 bool useAA() const { return false; }
339
340 bool isTypeLegal(Type *Ty) const { return false; }
341
342 unsigned getRegUsageForType(Type *Ty) const { return 1; }
343
344 bool shouldBuildLookupTables() const { return true; }
345
346 bool shouldBuildLookupTablesForConstant(Constant *C) const { return true; }
347
348 bool shouldBuildRelLookupTables() const { return false; }
349
350 bool useColdCCForColdCall(Function &F) const { return false; }
351
353 const APInt &DemandedElts,
354 bool Insert, bool Extract,
356 return 0;
357 }
358
363 return 0;
364 }
365
366 bool supportsEfficientVectorElementLoadStore() const { return false; }
367
368 bool supportsTailCalls() const { return true; }
369
370 bool enableAggressiveInterleaving(bool LoopHasReductions) const {
371 return false;
372 }
373
375 bool IsZeroCmp) const {
376 return {};
377 }
378
379 bool enableSelectOptimize() const { return true; }
380
382 // If the select is a logical-and/logical-or then it is better treated as a
383 // and/or by the backend.
384 using namespace llvm::PatternMatch;
385 return isa<SelectInst>(I) &&
388 }
389
390 bool enableInterleavedAccessVectorization() const { return false; }
391
392 bool enableMaskedInterleavedAccessVectorization() const { return false; }
393
394 bool isFPVectorizationPotentiallyUnsafe() const { return false; }
395
397 unsigned AddressSpace, Align Alignment,
398 unsigned *Fast) const {
399 return false;
400 }
401
402 TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const {
403 return TTI::PSK_Software;
404 }
405
406 bool haveFastSqrt(Type *Ty) const { return false; }
407
408 bool isExpensiveToSpeculativelyExecute(const Instruction *I) { return true; }
409
410 bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { return true; }
411
414 }
415
416 InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
417 const APInt &Imm, Type *Ty) const {
418 return 0;
419 }
420
423 return TTI::TCC_Basic;
424 }
425
426 InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
427 const APInt &Imm, Type *Ty,
429 Instruction *Inst = nullptr) const {
430 return TTI::TCC_Free;
431 }
432
434 const APInt &Imm, Type *Ty,
436 return TTI::TCC_Free;
437 }
438
440 const Function &Fn) const {
441 return false;
442 }
443
444 unsigned getNumberOfRegisters(unsigned ClassID) const { return 8; }
445
446 unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
447 return Vector ? 1 : 0;
448 };
449
450 const char *getRegisterClassName(unsigned ClassID) const {
451 switch (ClassID) {
452 default:
453 return "Generic::Unknown Register Class";
454 case 0:
455 return "Generic::ScalarRC";
456 case 1:
457 return "Generic::VectorRC";
458 }
459 }
460
462 return TypeSize::getFixed(32);
463 }
464
465 unsigned getMinVectorRegisterBitWidth() const { return 128; }
466
467 std::optional<unsigned> getMaxVScale() const { return std::nullopt; }
468 std::optional<unsigned> getVScaleForTuning() const { return std::nullopt; }
469 bool isVScaleKnownToBeAPowerOfTwo() const { return false; }
470
471 bool
473 return false;
474 }
475
476 ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const {
477 return ElementCount::get(0, IsScalable);
478 }
479
480 unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const { return 0; }
481 unsigned getStoreMinimumVF(unsigned VF, Type *, Type *) const { return VF; }
482
484 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
485 AllowPromotionWithoutCommonHeader = false;
486 return false;
487 }
488
489 unsigned getCacheLineSize() const { return 0; }
490 std::optional<unsigned>
492 switch (Level) {
494 [[fallthrough]];
496 return std::nullopt;
497 }
498 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
499 }
500
501 std::optional<unsigned>
503 switch (Level) {
505 [[fallthrough]];
507 return std::nullopt;
508 }
509
510 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
511 }
512
513 std::optional<unsigned> getMinPageSize() const { return {}; }
514
515 unsigned getPrefetchDistance() const { return 0; }
516 unsigned getMinPrefetchStride(unsigned NumMemAccesses,
517 unsigned NumStridedMemAccesses,
518 unsigned NumPrefetches, bool HasCall) const {
519 return 1;
520 }
521 unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; }
522 bool enableWritePrefetching() const { return false; }
523 bool shouldPrefetchAddressSpace(unsigned AS) const { return !AS; }
524
525 unsigned getMaxInterleaveFactor(ElementCount VF) const { return 1; }
526
528 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
531 const Instruction *CxtI = nullptr) const {
532 // Widenable conditions will eventually lower into constants, so some
533 // operations with them will be trivially optimized away.
534 auto IsWidenableCondition = [](const Value *V) {
535 if (auto *II = dyn_cast<IntrinsicInst>(V))
536 if (II->getIntrinsicID() == Intrinsic::experimental_widenable_condition)
537 return true;
538 return false;
539 };
540 // FIXME: A number of transformation tests seem to require these values
541 // which seems a little odd for how arbitary there are.
542 switch (Opcode) {
543 default:
544 break;
545 case Instruction::FDiv:
546 case Instruction::FRem:
547 case Instruction::SDiv:
548 case Instruction::SRem:
549 case Instruction::UDiv:
550 case Instruction::URem:
551 // FIXME: Unlikely to be true for CodeSize.
552 return TTI::TCC_Expensive;
553 case Instruction::And:
554 case Instruction::Or:
555 if (any_of(Args, IsWidenableCondition))
556 return TTI::TCC_Free;
557 break;
558 }
559
560 // Assume a 3cy latency for fp arithmetic ops.
562 if (Ty->getScalarType()->isFloatingPointTy())
563 return 3;
564
565 return 1;
566 }
567
569 unsigned Opcode1,
570 const SmallBitVector &OpcodeMask,
573 }
574
578 ArrayRef<const Value *> Args = std::nullopt) const {
579 return 1;
580 }
581
582 InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
585 const Instruction *I) const {
586 switch (Opcode) {
587 default:
588 break;
589 case Instruction::IntToPtr: {
590 unsigned SrcSize = Src->getScalarSizeInBits();
591 if (DL.isLegalInteger(SrcSize) &&
592 SrcSize <= DL.getPointerTypeSizeInBits(Dst))
593 return 0;
594 break;
595 }
596 case Instruction::PtrToInt: {
597 unsigned DstSize = Dst->getScalarSizeInBits();
598 if (DL.isLegalInteger(DstSize) &&
599 DstSize >= DL.getPointerTypeSizeInBits(Src))
600 return 0;
601 break;
602 }
603 case Instruction::BitCast:
604 if (Dst == Src || (Dst->isPointerTy() && Src->isPointerTy()))
605 // Identity and pointer-to-pointer casts are free.
606 return 0;
607 break;
608 case Instruction::Trunc: {
609 // trunc to a native type is free (assuming the target has compare and
610 // shift-right of the same width).
611 TypeSize DstSize = DL.getTypeSizeInBits(Dst);
612 if (!DstSize.isScalable() && DL.isLegalInteger(DstSize.getFixedValue()))
613 return 0;
614 break;
615 }
616 }
617 return 1;
618 }
619
621 VectorType *VecTy,
622 unsigned Index) const {
623 return 1;
624 }
625
627 const Instruction *I = nullptr) const {
628 // A phi would be free, unless we're costing the throughput because it
629 // will require a register.
630 if (Opcode == Instruction::PHI && CostKind != TTI::TCK_RecipThroughput)
631 return 0;
632 return 1;
633 }
634
635 InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
636 CmpInst::Predicate VecPred,
638 const Instruction *I) const {
639 return 1;
640 }
641
644 unsigned Index, Value *Op0,
645 Value *Op1) const {
646 return 1;
647 }
648
651 unsigned Index) const {
652 return 1;
653 }
654
655 unsigned getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF,
656 const APInt &DemandedDstElts,
658 return 1;
659 }
660
661 InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
662 unsigned AddressSpace,
665 const Instruction *I) const {
666 return 1;
667 }
668
669 InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
670 unsigned AddressSpace,
672 const Instruction *I) const {
673 return 1;
674 }
675
677 Align Alignment, unsigned AddressSpace,
679 return 1;
680 }
681
683 const Value *Ptr, bool VariableMask,
684 Align Alignment,
686 const Instruction *I = nullptr) const {
687 return 1;
688 }
689
691 const Value *Ptr, bool VariableMask,
692 Align Alignment,
694 const Instruction *I = nullptr) const {
696 }
697
699 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
700 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
701 bool UseMaskForCond, bool UseMaskForGaps) const {
702 return 1;
703 }
704
707 switch (ICA.getID()) {
708 default:
709 break;
710 case Intrinsic::annotation:
711 case Intrinsic::assume:
712 case Intrinsic::sideeffect:
713 case Intrinsic::pseudoprobe:
714 case Intrinsic::arithmetic_fence:
715 case Intrinsic::dbg_assign:
716 case Intrinsic::dbg_declare:
717 case Intrinsic::dbg_value:
718 case Intrinsic::dbg_label:
719 case Intrinsic::invariant_start:
720 case Intrinsic::invariant_end:
721 case Intrinsic::launder_invariant_group:
722 case Intrinsic::strip_invariant_group:
723 case Intrinsic::is_constant:
724 case Intrinsic::lifetime_start:
725 case Intrinsic::lifetime_end:
726 case Intrinsic::experimental_noalias_scope_decl:
727 case Intrinsic::objectsize:
728 case Intrinsic::ptr_annotation:
729 case Intrinsic::var_annotation:
730 case Intrinsic::experimental_gc_result:
731 case Intrinsic::experimental_gc_relocate:
732 case Intrinsic::coro_alloc:
733 case Intrinsic::coro_begin:
734 case Intrinsic::coro_free:
735 case Intrinsic::coro_end:
736 case Intrinsic::coro_frame:
737 case Intrinsic::coro_size:
738 case Intrinsic::coro_align:
739 case Intrinsic::coro_suspend:
740 case Intrinsic::coro_subfn_addr:
741 case Intrinsic::threadlocal_address:
742 case Intrinsic::experimental_widenable_condition:
743 case Intrinsic::ssa_copy:
744 // These intrinsics don't actually represent code after lowering.
745 return 0;
746 }
747 return 1;
748 }
749
753 return 1;
754 }
755
756 // Assume that we have a register of the right size for the type.
757 unsigned getNumberOfParts(Type *Tp) const { return 1; }
758
760 const SCEV *) const {
761 return 0;
762 }
763
765 std::optional<FastMathFlags> FMF,
766 TTI::TargetCostKind) const {
767 return 1;
768 }
769
772 TTI::TargetCostKind) const {
773 return 1;
774 }
775
776 InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned,
777 Type *ResTy, VectorType *Ty,
778 FastMathFlags FMF,
780 return 1;
781 }
782
784 VectorType *Ty,
786 return 1;
787 }
788
790 return 0;
791 }
792
794 return false;
795 }
796
798 // Note for overrides: You must ensure for all element unordered-atomic
799 // memory intrinsics that all power-of-2 element sizes up to, and
800 // including, the return value of this method have a corresponding
801 // runtime lib call. These runtime lib call definitions can be found
802 // in RuntimeLibcalls.h
803 return 0;
804 }
805
807 Type *ExpectedType) const {
808 return nullptr;
809 }
810
811 Type *
813 unsigned SrcAddrSpace, unsigned DestAddrSpace,
814 unsigned SrcAlign, unsigned DestAlign,
815 std::optional<uint32_t> AtomicElementSize) const {
816 return AtomicElementSize ? Type::getIntNTy(Context, *AtomicElementSize * 8)
818 }
819
821 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
822 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
823 unsigned SrcAlign, unsigned DestAlign,
824 std::optional<uint32_t> AtomicCpySize) const {
825 unsigned OpSizeInBytes = AtomicCpySize ? *AtomicCpySize : 1;
826 Type *OpType = Type::getIntNTy(Context, OpSizeInBytes * 8);
827 for (unsigned i = 0; i != RemainingBytes; i += OpSizeInBytes)
828 OpsOut.push_back(OpType);
829 }
830
831 bool areInlineCompatible(const Function *Caller,
832 const Function *Callee) const {
833 return (Caller->getFnAttribute("target-cpu") ==
834 Callee->getFnAttribute("target-cpu")) &&
835 (Caller->getFnAttribute("target-features") ==
836 Callee->getFnAttribute("target-features"));
837 }
838
839 unsigned getInlineCallPenalty(const Function *F, const CallBase &Call,
840 unsigned DefaultCallPenalty) const {
841 return DefaultCallPenalty;
842 }
843
844 bool areTypesABICompatible(const Function *Caller, const Function *Callee,
845 const ArrayRef<Type *> &Types) const {
846 return (Caller->getFnAttribute("target-cpu") ==
847 Callee->getFnAttribute("target-cpu")) &&
848 (Caller->getFnAttribute("target-features") ==
849 Callee->getFnAttribute("target-features"));
850 }
851
853 const DataLayout &DL) const {
854 return false;
855 }
856
858 const DataLayout &DL) const {
859 return false;
860 }
861
862 unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { return 128; }
863
864 bool isLegalToVectorizeLoad(LoadInst *LI) const { return true; }
865
866 bool isLegalToVectorizeStore(StoreInst *SI) const { return true; }
867
868 bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
869 unsigned AddrSpace) const {
870 return true;
871 }
872
873 bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
874 unsigned AddrSpace) const {
875 return true;
876 }
877
879 ElementCount VF) const {
880 return true;
881 }
882
883 bool isElementTypeLegalForScalableVector(Type *Ty) const { return true; }
884
885 unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
886 unsigned ChainSizeInBytes,
887 VectorType *VecTy) const {
888 return VF;
889 }
890
891 unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
892 unsigned ChainSizeInBytes,
893 VectorType *VecTy) const {
894 return VF;
895 }
896
897 bool preferInLoopReduction(unsigned Opcode, Type *Ty,
898 TTI::ReductionFlags Flags) const {
899 return false;
900 }
901
902 bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
903 TTI::ReductionFlags Flags) const {
904 return false;
905 }
906
908 return true;
909 }
910
911 bool shouldExpandReduction(const IntrinsicInst *II) const { return true; }
912
913 unsigned getGISelRematGlobalCost() const { return 1; }
914
915 unsigned getMinTripCountTailFoldingThreshold() const { return 0; }
916
917 bool supportsScalableVectors() const { return false; }
918
919 bool enableScalableVectorization() const { return false; }
920
921 bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
922 Align Alignment) const {
923 return false;
924 }
925
930 /* OperatorStrategy */ TargetTransformInfo::VPLegalization::Convert);
931 }
932
933 bool hasArmWideBranch(bool) const { return false; }
934
935 unsigned getMaxNumArgs() const { return UINT_MAX; }
936
937protected:
938 // Obtain the minimum required size to hold the value (without the sign)
939 // In case of a vector it returns the min required size for one element.
940 unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const {
941 if (isa<ConstantDataVector>(Val) || isa<ConstantVector>(Val)) {
942 const auto *VectorValue = cast<Constant>(Val);
943
944 // In case of a vector need to pick the max between the min
945 // required size for each element
946 auto *VT = cast<FixedVectorType>(Val->getType());
947
948 // Assume unsigned elements
949 isSigned = false;
950
951 // The max required size is the size of the vector element type
952 unsigned MaxRequiredSize =
953 VT->getElementType()->getPrimitiveSizeInBits().getFixedValue();
954
955 unsigned MinRequiredSize = 0;
956 for (unsigned i = 0, e = VT->getNumElements(); i < e; ++i) {
957 if (auto *IntElement =
958 dyn_cast<ConstantInt>(VectorValue->getAggregateElement(i))) {
959 bool signedElement = IntElement->getValue().isNegative();
960 // Get the element min required size.
961 unsigned ElementMinRequiredSize =
962 IntElement->getValue().getSignificantBits() - 1;
963 // In case one element is signed then all the vector is signed.
964 isSigned |= signedElement;
965 // Save the max required bit size between all the elements.
966 MinRequiredSize = std::max(MinRequiredSize, ElementMinRequiredSize);
967 } else {
968 // not an int constant element
969 return MaxRequiredSize;
970 }
971 }
972 return MinRequiredSize;
973 }
974
975 if (const auto *CI = dyn_cast<ConstantInt>(Val)) {
976 isSigned = CI->getValue().isNegative();
977 return CI->getValue().getSignificantBits() - 1;
978 }
979
980 if (const auto *Cast = dyn_cast<SExtInst>(Val)) {
981 isSigned = true;
982 return Cast->getSrcTy()->getScalarSizeInBits() - 1;
983 }
984
985 if (const auto *Cast = dyn_cast<ZExtInst>(Val)) {
986 isSigned = false;
987 return Cast->getSrcTy()->getScalarSizeInBits();
988 }
989
990 isSigned = false;
991 return Val->getType()->getScalarSizeInBits();
992 }
993
994 bool isStridedAccess(const SCEV *Ptr) const {
995 return Ptr && isa<SCEVAddRecExpr>(Ptr);
996 }
997
999 const SCEV *Ptr) const {
1000 if (!isStridedAccess(Ptr))
1001 return nullptr;
1002 const SCEVAddRecExpr *AddRec = cast<SCEVAddRecExpr>(Ptr);
1003 return dyn_cast<SCEVConstant>(AddRec->getStepRecurrence(*SE));
1004 }
1005
1007 int64_t MergeDistance) const {
1008 const SCEVConstant *Step = getConstantStrideStep(SE, Ptr);
1009 if (!Step)
1010 return false;
1011 APInt StrideVal = Step->getAPInt();
1012 if (StrideVal.getBitWidth() > 64)
1013 return false;
1014 // FIXME: Need to take absolute value for negative stride case.
1015 return StrideVal.getSExtValue() < MergeDistance;
1016 }
1017};
1018
1019/// CRTP base class for use as a mix-in that aids implementing
1020/// a TargetTransformInfo-compatible class.
1021template <typename T>
1023private:
1025
1026protected:
1028
1029public:
1031
1035 assert(PointeeType && Ptr && "can't get GEPCost of nullptr");
1036 auto *BaseGV = dyn_cast<GlobalValue>(Ptr->stripPointerCasts());
1037 bool HasBaseReg = (BaseGV == nullptr);
1038
1039 auto PtrSizeBits = DL.getPointerTypeSizeInBits(Ptr->getType());
1040 APInt BaseOffset(PtrSizeBits, 0);
1041 int64_t Scale = 0;
1042
1043 auto GTI = gep_type_begin(PointeeType, Operands);
1044 Type *TargetType = nullptr;
1045
1046 // Handle the case where the GEP instruction has a single operand,
1047 // the basis, therefore TargetType is a nullptr.
1048 if (Operands.empty())
1049 return !BaseGV ? TTI::TCC_Free : TTI::TCC_Basic;
1050
1051 for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) {
1052 TargetType = GTI.getIndexedType();
1053 // We assume that the cost of Scalar GEP with constant index and the
1054 // cost of Vector GEP with splat constant index are the same.
1055 const ConstantInt *ConstIdx = dyn_cast<ConstantInt>(*I);
1056 if (!ConstIdx)
1057 if (auto Splat = getSplatValue(*I))
1058 ConstIdx = dyn_cast<ConstantInt>(Splat);
1059 if (StructType *STy = GTI.getStructTypeOrNull()) {
1060 // For structures the index is always splat or scalar constant
1061 assert(ConstIdx && "Unexpected GEP index");
1062 uint64_t Field = ConstIdx->getZExtValue();
1063 BaseOffset += DL.getStructLayout(STy)->getElementOffset(Field);
1064 } else {
1065 // If this operand is a scalable type, bail out early.
1066 // TODO: Make isLegalAddressingMode TypeSize aware.
1067 if (TargetType->isScalableTy())
1068 return TTI::TCC_Basic;
1069 int64_t ElementSize =
1070 GTI.getSequentialElementStride(DL).getFixedValue();
1071 if (ConstIdx) {
1072 BaseOffset +=
1073 ConstIdx->getValue().sextOrTrunc(PtrSizeBits) * ElementSize;
1074 } else {
1075 // Needs scale register.
1076 if (Scale != 0)
1077 // No addressing mode takes two scale registers.
1078 return TTI::TCC_Basic;
1079 Scale = ElementSize;
1080 }
1081 }
1082 }
1083
1084 // If we haven't been provided a hint, use the target type for now.
1085 //
1086 // TODO: Take a look at potentially removing this: This is *slightly* wrong
1087 // as it's possible to have a GEP with a foldable target type but a memory
1088 // access that isn't foldable. For example, this load isn't foldable on
1089 // RISC-V:
1090 //
1091 // %p = getelementptr i32, ptr %base, i32 42
1092 // %x = load <2 x i32>, ptr %p
1093 if (!AccessType)
1094 AccessType = TargetType;
1095
1096 // If the final address of the GEP is a legal addressing mode for the given
1097 // access type, then we can fold it into its users.
1098 if (static_cast<T *>(this)->isLegalAddressingMode(
1099 AccessType, const_cast<GlobalValue *>(BaseGV),
1100 BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale,
1101 Ptr->getType()->getPointerAddressSpace()))
1102 return TTI::TCC_Free;
1103
1104 // TODO: Instead of returning TCC_Basic here, we should use
1105 // getArithmeticInstrCost. Or better yet, provide a hook to let the target
1106 // model it.
1107 return TTI::TCC_Basic;
1108 }
1109
1111 const Value *Base,
1113 Type *AccessTy,
1116 // In the basic model we take into account GEP instructions only
1117 // (although here can come alloca instruction, a value, constants and/or
1118 // constant expressions, PHIs, bitcasts ... whatever allowed to be used as a
1119 // pointer). Typically, if Base is a not a GEP-instruction and all the
1120 // pointers are relative to the same base address, all the rest are
1121 // either GEP instructions, PHIs, bitcasts or constants. When we have same
1122 // base, we just calculate cost of each non-Base GEP as an ADD operation if
1123 // any their index is a non-const.
1124 // If no known dependecies between the pointers cost is calculated as a sum
1125 // of costs of GEP instructions.
1126 for (const Value *V : Ptrs) {
1127 const auto *GEP = dyn_cast<GetElementPtrInst>(V);
1128 if (!GEP)
1129 continue;
1130 if (Info.isSameBase() && V != Base) {
1131 if (GEP->hasAllConstantIndices())
1132 continue;
1133 Cost += static_cast<T *>(this)->getArithmeticInstrCost(
1134 Instruction::Add, GEP->getType(), CostKind,
1136 std::nullopt);
1137 } else {
1138 SmallVector<const Value *> Indices(GEP->indices());
1139 Cost += static_cast<T *>(this)->getGEPCost(GEP->getSourceElementType(),
1140 GEP->getPointerOperand(),
1141 Indices, AccessTy, CostKind);
1142 }
1143 }
1144 return Cost;
1145 }
1146
1150 using namespace llvm::PatternMatch;
1151
1152 auto *TargetTTI = static_cast<T *>(this);
1153 // Handle non-intrinsic calls, invokes, and callbr.
1154 // FIXME: Unlikely to be true for anything but CodeSize.
1155 auto *CB = dyn_cast<CallBase>(U);
1156 if (CB && !isa<IntrinsicInst>(U)) {
1157 if (const Function *F = CB->getCalledFunction()) {
1158 if (!TargetTTI->isLoweredToCall(F))
1159 return TTI::TCC_Basic; // Give a basic cost if it will be lowered
1160
1161 return TTI::TCC_Basic * (F->getFunctionType()->getNumParams() + 1);
1162 }
1163 // For indirect or other calls, scale cost by number of arguments.
1164 return TTI::TCC_Basic * (CB->arg_size() + 1);
1165 }
1166
1167 Type *Ty = U->getType();
1168 unsigned Opcode = Operator::getOpcode(U);
1169 auto *I = dyn_cast<Instruction>(U);
1170 switch (Opcode) {
1171 default:
1172 break;
1173 case Instruction::Call: {
1174 assert(isa<IntrinsicInst>(U) && "Unexpected non-intrinsic call");
1175 auto *Intrinsic = cast<IntrinsicInst>(U);
1176 IntrinsicCostAttributes CostAttrs(Intrinsic->getIntrinsicID(), *CB);
1177 return TargetTTI->getIntrinsicInstrCost(CostAttrs, CostKind);
1178 }
1179 case Instruction::Br:
1180 case Instruction::Ret:
1181 case Instruction::PHI:
1182 case Instruction::Switch:
1183 return TargetTTI->getCFInstrCost(Opcode, CostKind, I);
1184 case Instruction::ExtractValue:
1185 case Instruction::Freeze:
1186 return TTI::TCC_Free;
1187 case Instruction::Alloca:
1188 if (cast<AllocaInst>(U)->isStaticAlloca())
1189 return TTI::TCC_Free;
1190 break;
1191 case Instruction::GetElementPtr: {
1192 const auto *GEP = cast<GEPOperator>(U);
1193 Type *AccessType = nullptr;
1194 // For now, only provide the AccessType in the simple case where the GEP
1195 // only has one user.
1196 if (GEP->hasOneUser() && I)
1197 AccessType = I->user_back()->getAccessType();
1198
1199 return TargetTTI->getGEPCost(GEP->getSourceElementType(),
1200 Operands.front(), Operands.drop_front(),
1201 AccessType, CostKind);
1202 }
1203 case Instruction::Add:
1204 case Instruction::FAdd:
1205 case Instruction::Sub:
1206 case Instruction::FSub:
1207 case Instruction::Mul:
1208 case Instruction::FMul:
1209 case Instruction::UDiv:
1210 case Instruction::SDiv:
1211 case Instruction::FDiv:
1212 case Instruction::URem:
1213 case Instruction::SRem:
1214 case Instruction::FRem:
1215 case Instruction::Shl:
1216 case Instruction::LShr:
1217 case Instruction::AShr:
1218 case Instruction::And:
1219 case Instruction::Or:
1220 case Instruction::Xor:
1221 case Instruction::FNeg: {
1223 TTI::OperandValueInfo Op2Info;
1224 if (Opcode != Instruction::FNeg)
1225 Op2Info = TTI::getOperandInfo(Operands[1]);
1226 return TargetTTI->getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
1227 Op2Info, Operands, I);
1228 }
1229 case Instruction::IntToPtr:
1230 case Instruction::PtrToInt:
1231 case Instruction::SIToFP:
1232 case Instruction::UIToFP:
1233 case Instruction::FPToUI:
1234 case Instruction::FPToSI:
1235 case Instruction::Trunc:
1236 case Instruction::FPTrunc:
1237 case Instruction::BitCast:
1238 case Instruction::FPExt:
1239 case Instruction::SExt:
1240 case Instruction::ZExt:
1241 case Instruction::AddrSpaceCast: {
1242 Type *OpTy = Operands[0]->getType();
1243 return TargetTTI->getCastInstrCost(
1244 Opcode, Ty, OpTy, TTI::getCastContextHint(I), CostKind, I);
1245 }
1246 case Instruction::Store: {
1247 auto *SI = cast<StoreInst>(U);
1248 Type *ValTy = Operands[0]->getType();
1250 return TargetTTI->getMemoryOpCost(Opcode, ValTy, SI->getAlign(),
1251 SI->getPointerAddressSpace(), CostKind,
1252 OpInfo, I);
1253 }
1254 case Instruction::Load: {
1255 // FIXME: Arbitary cost which could come from the backend.
1257 return 4;
1258 auto *LI = cast<LoadInst>(U);
1259 Type *LoadType = U->getType();
1260 // If there is a non-register sized type, the cost estimation may expand
1261 // it to be several instructions to load into multiple registers on the
1262 // target. But, if the only use of the load is a trunc instruction to a
1263 // register sized type, the instruction selector can combine these
1264 // instructions to be a single load. So, in this case, we use the
1265 // destination type of the trunc instruction rather than the load to
1266 // accurately estimate the cost of this load instruction.
1267 if (CostKind == TTI::TCK_CodeSize && LI->hasOneUse() &&
1268 !LoadType->isVectorTy()) {
1269 if (const TruncInst *TI = dyn_cast<TruncInst>(*LI->user_begin()))
1270 LoadType = TI->getDestTy();
1271 }
1272 return TargetTTI->getMemoryOpCost(Opcode, LoadType, LI->getAlign(),
1274 {TTI::OK_AnyValue, TTI::OP_None}, I);
1275 }
1276 case Instruction::Select: {
1277 const Value *Op0, *Op1;
1278 if (match(U, m_LogicalAnd(m_Value(Op0), m_Value(Op1))) ||
1279 match(U, m_LogicalOr(m_Value(Op0), m_Value(Op1)))) {
1280 // select x, y, false --> x & y
1281 // select x, true, y --> x | y
1282 const auto Op1Info = TTI::getOperandInfo(Op0);
1283 const auto Op2Info = TTI::getOperandInfo(Op1);
1284 assert(Op0->getType()->getScalarSizeInBits() == 1 &&
1285 Op1->getType()->getScalarSizeInBits() == 1);
1286
1288 return TargetTTI->getArithmeticInstrCost(
1289 match(U, m_LogicalOr()) ? Instruction::Or : Instruction::And, Ty,
1290 CostKind, Op1Info, Op2Info, Operands, I);
1291 }
1292 Type *CondTy = Operands[0]->getType();
1293 return TargetTTI->getCmpSelInstrCost(Opcode, U->getType(), CondTy,
1295 CostKind, I);
1296 }
1297 case Instruction::ICmp:
1298 case Instruction::FCmp: {
1299 Type *ValTy = Operands[0]->getType();
1300 // TODO: Also handle ICmp/FCmp constant expressions.
1301 return TargetTTI->getCmpSelInstrCost(Opcode, ValTy, U->getType(),
1302 I ? cast<CmpInst>(I)->getPredicate()
1304 CostKind, I);
1305 }
1306 case Instruction::InsertElement: {
1307 auto *IE = dyn_cast<InsertElementInst>(U);
1308 if (!IE)
1309 return TTI::TCC_Basic; // FIXME
1310 unsigned Idx = -1;
1311 if (auto *CI = dyn_cast<ConstantInt>(Operands[2]))
1312 if (CI->getValue().getActiveBits() <= 32)
1313 Idx = CI->getZExtValue();
1314 return TargetTTI->getVectorInstrCost(*IE, Ty, CostKind, Idx);
1315 }
1316 case Instruction::ShuffleVector: {
1317 auto *Shuffle = dyn_cast<ShuffleVectorInst>(U);
1318 if (!Shuffle)
1319 return TTI::TCC_Basic; // FIXME
1320
1321 auto *VecTy = cast<VectorType>(U->getType());
1322 auto *VecSrcTy = cast<VectorType>(Operands[0]->getType());
1323 int NumSubElts, SubIndex;
1324
1325 if (Shuffle->changesLength()) {
1326 // Treat a 'subvector widening' as a free shuffle.
1327 if (Shuffle->increasesLength() && Shuffle->isIdentityWithPadding())
1328 return 0;
1329
1330 if (Shuffle->isExtractSubvectorMask(SubIndex))
1331 return TargetTTI->getShuffleCost(TTI::SK_ExtractSubvector, VecSrcTy,
1332 Shuffle->getShuffleMask(), CostKind,
1333 SubIndex, VecTy, Operands);
1334
1335 if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1336 return TargetTTI->getShuffleCost(
1337 TTI::SK_InsertSubvector, VecTy, Shuffle->getShuffleMask(),
1338 CostKind, SubIndex,
1339 FixedVectorType::get(VecTy->getScalarType(), NumSubElts),
1340 Operands);
1341
1342 int ReplicationFactor, VF;
1343 if (Shuffle->isReplicationMask(ReplicationFactor, VF)) {
1344 APInt DemandedDstElts =
1345 APInt::getZero(Shuffle->getShuffleMask().size());
1346 for (auto I : enumerate(Shuffle->getShuffleMask())) {
1347 if (I.value() != PoisonMaskElem)
1348 DemandedDstElts.setBit(I.index());
1349 }
1350 return TargetTTI->getReplicationShuffleCost(
1351 VecSrcTy->getElementType(), ReplicationFactor, VF,
1352 DemandedDstElts, CostKind);
1353 }
1354
1355 return CostKind == TTI::TCK_RecipThroughput ? -1 : 1;
1356 }
1357
1358 if (Shuffle->isIdentity())
1359 return 0;
1360
1361 if (Shuffle->isReverse())
1362 return TargetTTI->getShuffleCost(TTI::SK_Reverse, VecTy,
1363 Shuffle->getShuffleMask(), CostKind, 0,
1364 nullptr, Operands);
1365
1366 if (Shuffle->isSelect())
1367 return TargetTTI->getShuffleCost(TTI::SK_Select, VecTy,
1368 Shuffle->getShuffleMask(), CostKind, 0,
1369 nullptr, Operands);
1370
1371 if (Shuffle->isTranspose())
1372 return TargetTTI->getShuffleCost(TTI::SK_Transpose, VecTy,
1373 Shuffle->getShuffleMask(), CostKind, 0,
1374 nullptr, Operands);
1375
1376 if (Shuffle->isZeroEltSplat())
1377 return TargetTTI->getShuffleCost(TTI::SK_Broadcast, VecTy,
1378 Shuffle->getShuffleMask(), CostKind, 0,
1379 nullptr, Operands);
1380
1381 if (Shuffle->isSingleSource())
1382 return TargetTTI->getShuffleCost(TTI::SK_PermuteSingleSrc, VecTy,
1383 Shuffle->getShuffleMask(), CostKind, 0,
1384 nullptr, Operands);
1385
1386 if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1387 return TargetTTI->getShuffleCost(
1388 TTI::SK_InsertSubvector, VecTy, Shuffle->getShuffleMask(), CostKind,
1389 SubIndex, FixedVectorType::get(VecTy->getScalarType(), NumSubElts),
1390 Operands);
1391
1392 if (Shuffle->isSplice(SubIndex))
1393 return TargetTTI->getShuffleCost(TTI::SK_Splice, VecTy,
1394 Shuffle->getShuffleMask(), CostKind,
1395 SubIndex, nullptr, Operands);
1396
1397 return TargetTTI->getShuffleCost(TTI::SK_PermuteTwoSrc, VecTy,
1398 Shuffle->getShuffleMask(), CostKind, 0,
1399 nullptr, Operands);
1400 }
1401 case Instruction::ExtractElement: {
1402 auto *EEI = dyn_cast<ExtractElementInst>(U);
1403 if (!EEI)
1404 return TTI::TCC_Basic; // FIXME
1405 unsigned Idx = -1;
1406 if (auto *CI = dyn_cast<ConstantInt>(Operands[1]))
1407 if (CI->getValue().getActiveBits() <= 32)
1408 Idx = CI->getZExtValue();
1409 Type *DstTy = Operands[0]->getType();
1410 return TargetTTI->getVectorInstrCost(*EEI, DstTy, CostKind, Idx);
1411 }
1412 }
1413
1414 // By default, just classify everything as 'basic' or -1 to represent that
1415 // don't know the throughput cost.
1417 }
1418
1420 auto *TargetTTI = static_cast<T *>(this);
1421 SmallVector<const Value *, 4> Ops(I->operand_values());
1422 InstructionCost Cost = TargetTTI->getInstructionCost(
1425 }
1426
1427 bool supportsTailCallFor(const CallBase *CB) const {
1428 return static_cast<const T *>(this)->supportsTailCalls();
1429 }
1430};
1431} // namespace llvm
1432
1433#endif
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
return RetTy
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
std::string Name
static bool isSigned(unsigned int Opcode)
Hexagon Common GEP
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
LLVMContext & Context
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static SymbolRef::Type getType(const Symbol *Sym)
Definition: TapiFile.cpp:40
This pass exposes codegen information to IR-level passes.
Class for arbitrary precision integers.
Definition: APInt.h:76
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
Definition: APInt.h:1302
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1433
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition: APInt.cpp:1010
static APInt getZero(unsigned numBits)
Get the '0' value for the specified bit-width.
Definition: APInt.h:178
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1507
an instruction to allocate memory on the stack
Definition: Instructions.h:59
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A cache of @llvm.assume calls within a function.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Conditional or Unconditional Branch instruction.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1457
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:967
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:153
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:144
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
bool isLegalInteger(uint64_t Width) const
Returns true if the specified type is known to be a native integer type supported by the CPU.
Definition: DataLayout.h:260
const StructLayout * getStructLayout(StructType *Ty) const
Returns a StructLayout object, indicating the alignment of the struct, its size, and the offsets of i...
Definition: DataLayout.cpp:720
unsigned getPointerTypeSizeInBits(Type *) const
Layout pointer size, in bits, based on the type.
Definition: DataLayout.cpp:763
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:672
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Definition: DataLayout.h:472
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:162
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
Definition: TypeSize.h:302
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:20
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
Definition: Type.cpp:692
The core instruction combiner logic.
Definition: InstCombiner.h:47
static InstructionCost getInvalid(CostType Val=0)
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:47
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:54
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:184
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:44
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
Definition: Operator.h:41
The optimization diagnostic interface.
Analysis providing profile information.
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:71
This node represents a polynomial recurrence on the trip count of the specified loop.
const SCEV * getStepRecurrence(ScalarEvolution &SE) const
Constructs and returns the recurrence indicating how much this expression steps by.
This class represents a constant integer value.
const APInt & getAPInt() const
This class represents an analyzed expression in the program.
The main scalar evolution driver.
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
An instruction for storing to memory.
Definition: Instructions.h:317
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TypeSize getElementOffset(unsigned Idx) const
Definition: DataLayout.h:651
Class to represent struct types.
Definition: DerivedTypes.h:216
Multiway switch.
Provides information about what library functions are available for the current target.
Base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
const DataLayout & getDataLayout() const
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicCpySize) const
bool isLegalToVectorizeStore(StoreInst *SI) const
bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const
bool shouldTreatInstructionLikeSelect(const Instruction *I)
bool isLegalToVectorizeLoad(LoadInst *LI) const
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
std::optional< unsigned > getVScaleForTuning() const
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
bool isLegalICmpImmediate(int64_t Imm) const
unsigned getRegUsageForType(Type *Ty) const
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) const
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
void getPeelingPreferences(Loop *, ScalarEvolution &, TTI::PeelingPreferences &) const
bool isAlwaysUniform(const Value *V) const
bool isProfitableToHoist(Instruction *I) const
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
bool isLSRCostLess(const TTI::LSRCost &C1, const TTI::LSRCost &C2) const
bool isExpensiveToSpeculativelyExecute(const Instruction *I)
bool isTruncateFree(Type *Ty1, Type *Ty2) const
bool isStridedAccess(const SCEV *Ptr) const
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
InstructionCost getArithmeticReductionCost(unsigned, VectorType *, std::optional< FastMathFlags > FMF, TTI::TargetCostKind) const
InstructionCost getFPOpCost(Type *Ty) const
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
bool isLegalMaskedExpandLoad(Type *DataType) const
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
InstructionCost getMemcpyCost(const Instruction *I) const
unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
std::optional< unsigned > getMaxVScale() const
TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const
bool isProfitableLSRChainElement(Instruction *I) const
InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const
bool preferToKeepConstantsAttached(const Instruction &Inst, const Function &Fn) const
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
InstructionCost getStridedMemoryOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
bool isNoopAddrSpaceCast(unsigned, unsigned) const
unsigned getStoreMinimumVF(unsigned VF, Type *, Type *) const
InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, TTI::TargetCostKind CostKind, unsigned Index) const
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
TargetTransformInfoImplBase(TargetTransformInfoImplBase &&Arg)
TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
void getUnrollingPreferences(Loop *, ScalarEvolution &, TTI::UnrollingPreferences &, OptimizationRemarkEmitter *) const
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicElementSize) const
std::optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const
unsigned getAssumedAddrSpace(const Value *V) const
bool isLegalNTStore(Type *DataType, Align Alignment) const
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
unsigned adjustInliningThreshold(const CallBase *CB) const
BranchProbability getPredictableBranchThreshold() const
std::optional< unsigned > getMinPageSize() const
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind) const
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, unsigned *Fast) const
const SCEVConstant * getConstantStrideStep(ScalarEvolution *SE, const SCEV *Ptr) const
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
bool shouldPrefetchAddressSpace(unsigned AS) const
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
unsigned getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
bool isSourceOfDivergence(const Value *V) const
bool enableAggressiveInterleaving(bool LoopHasReductions) const
unsigned getMaxInterleaveFactor(ElementCount VF) const
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I) const
std::optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info, TTI::OperandValueInfo Opd2Info, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr) const
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
bool forceScalarizeMaskedGather(VectorType *DataType, Align Alignment) const
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const
bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
bool hasDivRemOp(Type *DataType, bool IsSigned) const
InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *, const SCEV *) const
bool isLegalMaskedCompressStore(Type *DataType) const
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I) const
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt) const
bool preferInLoopReduction(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr) const
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance) const
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind) const
bool isLoweredToCall(const Function *F) const
bool hasBranchDivergence(const Function *F=nullptr) const
TargetTransformInfoImplBase(const DataLayout &DL)
const char * getRegisterClassName(unsigned ClassID) const
bool isElementTypeLegalForScalableVector(Type *Ty) const
bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind) const
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
TailFoldingStyle getPreferredTailFoldingStyle(bool IVUpdateMayOverflow=true) const
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *, FastMathFlags, TTI::TargetCostKind) const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1) const
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo, const Instruction *I) const
bool useColdCCForColdCall(Function &F) const
bool shouldExpandReduction(const IntrinsicInst *II) const
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
unsigned getNumberOfRegisters(unsigned ClassID) const
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType, TTI::TargetCostKind CostKind) const
bool isLegalNTLoad(Type *DataType, Align Alignment) const
std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
bool forceScalarizeMaskedScatter(VectorType *DataType, Align Alignment) const
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const
TargetTransformInfoImplBase(const TargetTransformInfoImplBase &Arg)=default
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
bool shouldBuildLookupTablesForConstant(Constant *C) const
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
bool supportsTailCallFor(const CallBase *CB) const
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType, TTI::TargetCostKind CostKind)
InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const TTI::PointersChainInfo &Info, Type *AccessTy, TTI::TargetCostKind CostKind)
InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
bool isExpensiveToSpeculativelyExecute(const Instruction *I)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
static OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
TargetCostKind
The kind of cost model.
@ TCK_RecipThroughput
Reciprocal throughput.
@ TCK_CodeSize
Instruction code size.
@ TCK_SizeAndLatency
The weighted sum of size and latency.
@ TCK_Latency
The latency of instruction.
PopcntSupportKind
Flags indicating the kind of support for population count.
@ TCC_Expensive
The cost of a 'div' instruction on x86.
@ TCC_Free
Expected to fold away in lowering.
@ TCC_Basic
The cost of a typical 'add' instruction.
MemIndexedMode
The type of load/store indexing.
ShuffleKind
The various kinds of shuffle patterns for vector queries.
@ SK_InsertSubvector
InsertSubvector. Index indicates start offset.
@ SK_Select
Selects elements from the corresponding lane of either source operand.
@ SK_PermuteSingleSrc
Shuffle elements of single source vector with any shuffle mask.
@ SK_Transpose
Transpose two vectors.
@ SK_Splice
Concatenates elements from the first input vector with elements of the second input vector.
@ SK_Broadcast
Broadcast element 0 to all other elements.
@ SK_PermuteTwoSrc
Merge elements from two source vectors into one with any shuffle mask.
@ SK_Reverse
Reverse the order of the vector.
@ SK_ExtractSubvector
ExtractSubvector Index indicates start offset.
CastContextHint
Represents a hint about the context in which a cast is used.
CacheLevel
The possible cache levels.
This class represents a truncation of integer types.
static constexpr TypeSize getFixed(ScalarTy ExactSize)
Definition: TypeSize.h:330
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:265
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
static IntegerType * getInt8Ty(LLVMContext &C)
bool isFloatingPointTy() const
Return true if this is one of the floating-point types.
Definition: Type.h:185
bool isScalableTy() const
Return true if this is a type whose size is a known multiple of vscale.
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:348
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
Base class of all SIMD vector types.
Definition: DerivedTypes.h:403
constexpr ScalarTy getFixedValue() const
Definition: TypeSize.h:187
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:171
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
auto m_LogicalOr()
Matches L || R where L and R are arbitrary values.
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:76
auto m_LogicalAnd()
Matches L && R where L and R are arbitrary values.
match_combine_or< LTy, RTy > m_CombineOr(const LTy &L, const RTy &R)
Combine two pattern matchers matching L || R.
Definition: PatternMatch.h:218
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Length
Definition: DWP.cpp:456
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are are tuples (A,...
Definition: STLExtras.h:2386
AddressSpace
Definition: NVPTXBaseInfo.h:21
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1738
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:264
constexpr int PoisonMaskElem
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:191
gep_type_iterator gep_type_begin(const User *GEP)
InstructionCost Cost
@ DataWithoutLaneMask
Same as Data, but avoids using the get.active.lane.mask intrinsic to calculate the mask and instead i...
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Attributes of a target dependent hardware loop.
Information about a load/store intrinsic defined by the target.
Returns options for expansion of memcmp. IsZeroCmp is.
Describe known properties for a set of pointers.
Flags describing the kind of vector reduction.
Parameters that control the generic loop unrolling transformation.