LLVM  14.0.0git
TargetTransformInfoImpl.h
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1 //===- TargetTransformInfoImpl.h --------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file provides helpers for the implementation of
10 /// a TargetTransformInfo-conforming class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
15 #define LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
16 
20 #include "llvm/IR/DataLayout.h"
21 #include "llvm/IR/Function.h"
23 #include "llvm/IR/IntrinsicInst.h"
24 #include "llvm/IR/Operator.h"
25 #include "llvm/IR/PatternMatch.h"
26 #include "llvm/IR/Type.h"
27 
28 using namespace llvm::PatternMatch;
29 
30 namespace llvm {
31 
32 /// Base class for use as a mix-in that aids implementing
33 /// a TargetTransformInfo-compatible class.
35 protected:
37 
38  const DataLayout &DL;
39 
41 
42 public:
43  // Provide value semantics. MSVC requires that we spell all of these out.
45  : DL(Arg.DL) {}
47 
48  const DataLayout &getDataLayout() const { return DL; }
49 
50  InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr,
53  // In the basic model, we just assume that all-constant GEPs will be folded
54  // into their uses via addressing modes.
55  for (unsigned Idx = 0, Size = Operands.size(); Idx != Size; ++Idx)
56  if (!isa<Constant>(Operands[Idx]))
57  return TTI::TCC_Basic;
58 
59  return TTI::TCC_Free;
60  }
61 
63  unsigned &JTSize,
64  ProfileSummaryInfo *PSI,
65  BlockFrequencyInfo *BFI) const {
66  (void)PSI;
67  (void)BFI;
68  JTSize = 0;
69  return SI.getNumCases();
70  }
71 
72  unsigned getInliningThresholdMultiplier() const { return 1; }
73  unsigned adjustInliningThreshold(const CallBase *CB) const { return 0; }
74 
75  int getInlinerVectorBonusPercent() const { return 150; }
76 
78  return TTI::TCC_Expensive;
79  }
80 
81  // Although this default value is arbitrary, it is not random. It is assumed
82  // that a condition that evaluates the same way by a higher percentage than
83  // this is best represented as control flow. Therefore, the default value N
84  // should be set such that the win from N% correct executions is greater than
85  // the loss from (100 - N)% mispredicted executions for the majority of
86  // intended targets.
88  return BranchProbability(99, 100);
89  }
90 
91  bool hasBranchDivergence() const { return false; }
92 
93  bool useGPUDivergenceAnalysis() const { return false; }
94 
95  bool isSourceOfDivergence(const Value *V) const { return false; }
96 
97  bool isAlwaysUniform(const Value *V) const { return false; }
98 
99  unsigned getFlatAddressSpace() const { return -1; }
100 
102  Intrinsic::ID IID) const {
103  return false;
104  }
105 
106  bool isNoopAddrSpaceCast(unsigned, unsigned) const { return false; }
108  return AS == 0;
109  };
110 
111  unsigned getAssumedAddrSpace(const Value *V) const { return -1; }
112 
114  Value *NewV) const {
115  return nullptr;
116  }
117 
118  bool isLoweredToCall(const Function *F) const {
119  assert(F && "A concrete function must be provided to this routine.");
120 
121  // FIXME: These should almost certainly not be handled here, and instead
122  // handled with the help of TLI or the target itself. This was largely
123  // ported from existing analysis heuristics here so that such refactorings
124  // can take place in the future.
125 
126  if (F->isIntrinsic())
127  return false;
128 
129  if (F->hasLocalLinkage() || !F->hasName())
130  return true;
131 
132  StringRef Name = F->getName();
133 
134  // These will all likely lower to a single selection DAG node.
135  if (Name == "copysign" || Name == "copysignf" || Name == "copysignl" ||
136  Name == "fabs" || Name == "fabsf" || Name == "fabsl" || Name == "sin" ||
137  Name == "fmin" || Name == "fminf" || Name == "fminl" ||
138  Name == "fmax" || Name == "fmaxf" || Name == "fmaxl" ||
139  Name == "sinf" || Name == "sinl" || Name == "cos" || Name == "cosf" ||
140  Name == "cosl" || Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl")
141  return false;
142 
143  // These are all likely to be optimized into something smaller.
144  if (Name == "pow" || Name == "powf" || Name == "powl" || Name == "exp2" ||
145  Name == "exp2l" || Name == "exp2f" || Name == "floor" ||
146  Name == "floorf" || Name == "ceil" || Name == "round" ||
147  Name == "ffs" || Name == "ffsl" || Name == "abs" || Name == "labs" ||
148  Name == "llabs")
149  return false;
150 
151  return true;
152  }
153 
155  AssumptionCache &AC, TargetLibraryInfo *LibInfo,
156  HardwareLoopInfo &HWLoopInfo) const {
157  return false;
158  }
159 
162  DominatorTree *DT,
163  const LoopAccessInfo *LAI) const {
164  return false;
165  }
166 
167  bool emitGetActiveLaneMask() const {
168  return false;
169  }
170 
172  IntrinsicInst &II) const {
173  return None;
174  }
175 
178  APInt DemandedMask, KnownBits &Known,
179  bool &KnownBitsComputed) const {
180  return None;
181  }
182 
184  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
185  APInt &UndefElts2, APInt &UndefElts3,
186  std::function<void(Instruction *, unsigned, APInt, APInt &)>
187  SimplifyAndSetOp) const {
188  return None;
189  }
190 
193  OptimizationRemarkEmitter *) const {}
194 
196  TTI::PeelingPreferences &) const {}
197 
198  bool isLegalAddImmediate(int64_t Imm) const { return false; }
199 
200  bool isLegalICmpImmediate(int64_t Imm) const { return false; }
201 
202  bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
203  bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
204  Instruction *I = nullptr) const {
205  // Guess that only reg and reg+reg addressing is allowed. This heuristic is
206  // taken from the implementation of LSR.
207  return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1);
208  }
209 
211  return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds,
212  C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
213  std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds,
214  C2.ScaleCost, C2.ImmCost, C2.SetupCost);
215  }
216 
217  bool isNumRegsMajorCostOfLSR() const { return true; }
218 
219  bool isProfitableLSRChainElement(Instruction *I) const { return false; }
220 
221  bool canMacroFuseCmp() const { return false; }
222 
225  TargetLibraryInfo *LibInfo) const {
226  return false;
227  }
228 
231  return TTI::AMK_None;
232  }
233 
234  bool isLegalMaskedStore(Type *DataType, Align Alignment) const {
235  return false;
236  }
237 
238  bool isLegalMaskedLoad(Type *DataType, Align Alignment) const {
239  return false;
240  }
241 
242  bool isLegalNTStore(Type *DataType, Align Alignment) const {
243  // By default, assume nontemporal memory stores are available for stores
244  // that are aligned and have a size that is a power of 2.
245  unsigned DataSize = DL.getTypeStoreSize(DataType);
246  return Alignment >= DataSize && isPowerOf2_32(DataSize);
247  }
248 
249  bool isLegalNTLoad(Type *DataType, Align Alignment) const {
250  // By default, assume nontemporal memory loads are available for loads that
251  // are aligned and have a size that is a power of 2.
252  unsigned DataSize = DL.getTypeStoreSize(DataType);
253  return Alignment >= DataSize && isPowerOf2_32(DataSize);
254  }
255 
256  bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
257  return false;
258  }
259 
260  bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
261  return false;
262  }
263 
264  bool isLegalMaskedCompressStore(Type *DataType) const { return false; }
265 
266  bool isLegalMaskedExpandLoad(Type *DataType) const { return false; }
267 
268  bool enableOrderedReductions() const { return false; }
269 
270  bool hasDivRemOp(Type *DataType, bool IsSigned) const { return false; }
271 
272  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const {
273  return false;
274  }
275 
276  bool prefersVectorizedAddressing() const { return true; }
277 
279  int64_t BaseOffset, bool HasBaseReg,
280  int64_t Scale,
281  unsigned AddrSpace) const {
282  // Guess that all legal addressing mode are free.
283  if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
284  AddrSpace))
285  return 0;
286  return -1;
287  }
288 
289  bool LSRWithInstrQueries() const { return false; }
290 
291  bool isTruncateFree(Type *Ty1, Type *Ty2) const { return false; }
292 
293  bool isProfitableToHoist(Instruction *I) const { return true; }
294 
295  bool useAA() const { return false; }
296 
297  bool isTypeLegal(Type *Ty) const { return false; }
298 
299  InstructionCost getRegUsageForType(Type *Ty) const { return 1; }
300 
301  bool shouldBuildLookupTables() const { return true; }
302 
303  bool shouldBuildLookupTablesForConstant(Constant *C) const { return true; }
304 
305  bool shouldBuildRelLookupTables() const { return false; }
306 
307  bool useColdCCForColdCall(Function &F) const { return false; }
308 
310  const APInt &DemandedElts,
311  bool Insert, bool Extract) const {
312  return 0;
313  }
314 
316  ArrayRef<Type *> Tys) const {
317  return 0;
318  }
319 
320  bool supportsEfficientVectorElementLoadStore() const { return false; }
321 
322  bool enableAggressiveInterleaving(bool LoopHasReductions) const {
323  return false;
324  }
325 
327  bool IsZeroCmp) const {
328  return {};
329  }
330 
331  bool enableInterleavedAccessVectorization() const { return false; }
332 
333  bool enableMaskedInterleavedAccessVectorization() const { return false; }
334 
335  bool isFPVectorizationPotentiallyUnsafe() const { return false; }
336 
338  unsigned AddressSpace, Align Alignment,
339  bool *Fast) const {
340  return false;
341  }
342 
343  TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const {
344  return TTI::PSK_Software;
345  }
346 
347  bool haveFastSqrt(Type *Ty) const { return false; }
348 
349  bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { return true; }
350 
353  }
354 
355  InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
356  const APInt &Imm, Type *Ty) const {
357  return 0;
358  }
359 
362  return TTI::TCC_Basic;
363  }
364 
365  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
366  const APInt &Imm, Type *Ty,
368  Instruction *Inst = nullptr) const {
369  return TTI::TCC_Free;
370  }
371 
373  const APInt &Imm, Type *Ty,
375  return TTI::TCC_Free;
376  }
377 
378  unsigned getNumberOfRegisters(unsigned ClassID) const { return 8; }
379 
380  unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
381  return Vector ? 1 : 0;
382  };
383 
384  const char *getRegisterClassName(unsigned ClassID) const {
385  switch (ClassID) {
386  default:
387  return "Generic::Unknown Register Class";
388  case 0:
389  return "Generic::ScalarRC";
390  case 1:
391  return "Generic::VectorRC";
392  }
393  }
394 
396  return TypeSize::getFixed(32);
397  }
398 
399  unsigned getMinVectorRegisterBitWidth() const { return 128; }
400 
402 
403  bool shouldMaximizeVectorBandwidth() const { return false; }
404 
405  ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const {
406  return ElementCount::get(0, IsScalable);
407  }
408 
409  unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const { return 0; }
410 
412  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
413  AllowPromotionWithoutCommonHeader = false;
414  return false;
415  }
416 
417  unsigned getCacheLineSize() const { return 0; }
418 
421  switch (Level) {
425  return llvm::Optional<unsigned>();
426  }
427  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
428  }
429 
432  switch (Level) {
436  return llvm::Optional<unsigned>();
437  }
438 
439  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
440  }
441 
442  unsigned getPrefetchDistance() const { return 0; }
443  unsigned getMinPrefetchStride(unsigned NumMemAccesses,
444  unsigned NumStridedMemAccesses,
445  unsigned NumPrefetches, bool HasCall) const {
446  return 1;
447  }
448  unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; }
449  bool enableWritePrefetching() const { return false; }
450 
451  unsigned getMaxInterleaveFactor(unsigned VF) const { return 1; }
452 
454  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
455  TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info,
456  TTI::OperandValueProperties Opd1PropInfo,
458  const Instruction *CxtI = nullptr) const {
459  // FIXME: A number of transformation tests seem to require these values
460  // which seems a little odd for how arbitary there are.
461  switch (Opcode) {
462  default:
463  break;
464  case Instruction::FDiv:
465  case Instruction::FRem:
466  case Instruction::SDiv:
467  case Instruction::SRem:
468  case Instruction::UDiv:
469  case Instruction::URem:
470  // FIXME: Unlikely to be true for CodeSize.
471  return TTI::TCC_Expensive;
472  }
473  return 1;
474  }
475 
477  ArrayRef<int> Mask, int Index,
478  VectorType *SubTp) const {
479  return 1;
480  }
481 
482  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
485  const Instruction *I) const {
486  switch (Opcode) {
487  default:
488  break;
489  case Instruction::IntToPtr: {
490  unsigned SrcSize = Src->getScalarSizeInBits();
491  if (DL.isLegalInteger(SrcSize) &&
492  SrcSize <= DL.getPointerTypeSizeInBits(Dst))
493  return 0;
494  break;
495  }
496  case Instruction::PtrToInt: {
497  unsigned DstSize = Dst->getScalarSizeInBits();
498  if (DL.isLegalInteger(DstSize) &&
499  DstSize >= DL.getPointerTypeSizeInBits(Src))
500  return 0;
501  break;
502  }
503  case Instruction::BitCast:
504  if (Dst == Src || (Dst->isPointerTy() && Src->isPointerTy()))
505  // Identity and pointer-to-pointer casts are free.
506  return 0;
507  break;
508  case Instruction::Trunc: {
509  // trunc to a native type is free (assuming the target has compare and
510  // shift-right of the same width).
511  TypeSize DstSize = DL.getTypeSizeInBits(Dst);
512  if (!DstSize.isScalable() && DL.isLegalInteger(DstSize.getFixedSize()))
513  return 0;
514  break;
515  }
516  }
517  return 1;
518  }
519 
521  VectorType *VecTy,
522  unsigned Index) const {
523  return 1;
524  }
525 
527  const Instruction *I = nullptr) const {
528  // A phi would be free, unless we're costing the throughput because it
529  // will require a register.
530  if (Opcode == Instruction::PHI && CostKind != TTI::TCK_RecipThroughput)
531  return 0;
532  return 1;
533  }
534 
535  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
536  CmpInst::Predicate VecPred,
538  const Instruction *I) const {
539  return 1;
540  }
541 
542  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
543  unsigned Index) const {
544  return 1;
545  }
546 
547  InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
548  unsigned AddressSpace,
550  const Instruction *I) const {
551  return 1;
552  }
553 
555  Align Alignment, unsigned AddressSpace,
557  return 1;
558  }
559 
560  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
561  const Value *Ptr, bool VariableMask,
562  Align Alignment,
564  const Instruction *I = nullptr) const {
565  return 1;
566  }
567 
569  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
570  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
571  bool UseMaskForCond, bool UseMaskForGaps) const {
572  return 1;
573  }
574 
577  switch (ICA.getID()) {
578  default:
579  break;
580  case Intrinsic::annotation:
581  case Intrinsic::assume:
582  case Intrinsic::sideeffect:
583  case Intrinsic::pseudoprobe:
584  case Intrinsic::arithmetic_fence:
585  case Intrinsic::dbg_declare:
586  case Intrinsic::dbg_value:
587  case Intrinsic::dbg_label:
588  case Intrinsic::invariant_start:
589  case Intrinsic::invariant_end:
590  case Intrinsic::launder_invariant_group:
591  case Intrinsic::strip_invariant_group:
592  case Intrinsic::is_constant:
593  case Intrinsic::lifetime_start:
594  case Intrinsic::lifetime_end:
595  case Intrinsic::experimental_noalias_scope_decl:
596  case Intrinsic::objectsize:
597  case Intrinsic::ptr_annotation:
598  case Intrinsic::var_annotation:
599  case Intrinsic::experimental_gc_result:
600  case Intrinsic::experimental_gc_relocate:
601  case Intrinsic::coro_alloc:
602  case Intrinsic::coro_begin:
603  case Intrinsic::coro_free:
604  case Intrinsic::coro_end:
605  case Intrinsic::coro_frame:
606  case Intrinsic::coro_size:
607  case Intrinsic::coro_suspend:
608  case Intrinsic::coro_param:
609  case Intrinsic::coro_subfn_addr:
610  // These intrinsics don't actually represent code after lowering.
611  return 0;
612  }
613  return 1;
614  }
615 
617  ArrayRef<Type *> Tys,
619  return 1;
620  }
621 
622  unsigned getNumberOfParts(Type *Tp) const { return 0; }
623 
625  const SCEV *) const {
626  return 0;
627  }
628 
631  TTI::TargetCostKind) const {
632  return 1;
633  }
634 
636  TTI::TargetCostKind) const {
637  return 1;
638  }
639 
641  getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned, Type *ResTy,
642  VectorType *Ty,
644  return 1;
645  }
646 
648  return 0;
649  }
650 
652  return false;
653  }
654 
656  // Note for overrides: You must ensure for all element unordered-atomic
657  // memory intrinsics that all power-of-2 element sizes up to, and
658  // including, the return value of this method have a corresponding
659  // runtime lib call. These runtime lib call definitions can be found
660  // in RuntimeLibcalls.h
661  return 0;
662  }
663 
665  Type *ExpectedType) const {
666  return nullptr;
667  }
668 
670  unsigned SrcAddrSpace, unsigned DestAddrSpace,
671  unsigned SrcAlign, unsigned DestAlign) const {
672  return Type::getInt8Ty(Context);
673  }
674 
677  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
678  unsigned SrcAlign, unsigned DestAlign) const {
679  for (unsigned i = 0; i != RemainingBytes; ++i)
680  OpsOut.push_back(Type::getInt8Ty(Context));
681  }
682 
683  bool areInlineCompatible(const Function *Caller,
684  const Function *Callee) const {
685  return (Caller->getFnAttribute("target-cpu") ==
686  Callee->getFnAttribute("target-cpu")) &&
687  (Caller->getFnAttribute("target-features") ==
688  Callee->getFnAttribute("target-features"));
689  }
690 
692  const Function *Callee,
694  return (Caller->getFnAttribute("target-cpu") ==
695  Callee->getFnAttribute("target-cpu")) &&
696  (Caller->getFnAttribute("target-features") ==
697  Callee->getFnAttribute("target-features"));
698  }
699 
701  const DataLayout &DL) const {
702  return false;
703  }
704 
706  const DataLayout &DL) const {
707  return false;
708  }
709 
710  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { return 128; }
711 
712  bool isLegalToVectorizeLoad(LoadInst *LI) const { return true; }
713 
714  bool isLegalToVectorizeStore(StoreInst *SI) const { return true; }
715 
716  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
717  unsigned AddrSpace) const {
718  return true;
719  }
720 
721  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
722  unsigned AddrSpace) const {
723  return true;
724  }
725 
727  ElementCount VF) const {
728  return true;
729  }
730 
731  bool isElementTypeLegalForScalableVector(Type *Ty) const { return true; }
732 
733  unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
734  unsigned ChainSizeInBytes,
735  VectorType *VecTy) const {
736  return VF;
737  }
738 
739  unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
740  unsigned ChainSizeInBytes,
741  VectorType *VecTy) const {
742  return VF;
743  }
744 
745  bool preferInLoopReduction(unsigned Opcode, Type *Ty,
746  TTI::ReductionFlags Flags) const {
747  return false;
748  }
749 
750  bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
751  TTI::ReductionFlags Flags) const {
752  return false;
753  }
754 
755  bool shouldExpandReduction(const IntrinsicInst *II) const { return true; }
756 
757  unsigned getGISelRematGlobalCost() const { return 1; }
758 
759  bool supportsScalableVectors() const { return false; }
760 
761  bool hasActiveVectorLength() const { return false; }
762 
766  /* EVLParamStrategy */ TargetTransformInfo::VPLegalization::Discard,
767  /* OperatorStrategy */ TargetTransformInfo::VPLegalization::Convert);
768  }
769 
770 protected:
771  // Obtain the minimum required size to hold the value (without the sign)
772  // In case of a vector it returns the min required size for one element.
773  unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const {
774  if (isa<ConstantDataVector>(Val) || isa<ConstantVector>(Val)) {
775  const auto *VectorValue = cast<Constant>(Val);
776 
777  // In case of a vector need to pick the max between the min
778  // required size for each element
779  auto *VT = cast<FixedVectorType>(Val->getType());
780 
781  // Assume unsigned elements
782  isSigned = false;
783 
784  // The max required size is the size of the vector element type
785  unsigned MaxRequiredSize =
786  VT->getElementType()->getPrimitiveSizeInBits().getFixedSize();
787 
788  unsigned MinRequiredSize = 0;
789  for (unsigned i = 0, e = VT->getNumElements(); i < e; ++i) {
790  if (auto *IntElement =
791  dyn_cast<ConstantInt>(VectorValue->getAggregateElement(i))) {
792  bool signedElement = IntElement->getValue().isNegative();
793  // Get the element min required size.
794  unsigned ElementMinRequiredSize =
795  IntElement->getValue().getMinSignedBits() - 1;
796  // In case one element is signed then all the vector is signed.
797  isSigned |= signedElement;
798  // Save the max required bit size between all the elements.
799  MinRequiredSize = std::max(MinRequiredSize, ElementMinRequiredSize);
800  } else {
801  // not an int constant element
802  return MaxRequiredSize;
803  }
804  }
805  return MinRequiredSize;
806  }
807 
808  if (const auto *CI = dyn_cast<ConstantInt>(Val)) {
809  isSigned = CI->getValue().isNegative();
810  return CI->getValue().getMinSignedBits() - 1;
811  }
812 
813  if (const auto *Cast = dyn_cast<SExtInst>(Val)) {
814  isSigned = true;
815  return Cast->getSrcTy()->getScalarSizeInBits() - 1;
816  }
817 
818  if (const auto *Cast = dyn_cast<ZExtInst>(Val)) {
819  isSigned = false;
820  return Cast->getSrcTy()->getScalarSizeInBits();
821  }
822 
823  isSigned = false;
824  return Val->getType()->getScalarSizeInBits();
825  }
826 
827  bool isStridedAccess(const SCEV *Ptr) const {
828  return Ptr && isa<SCEVAddRecExpr>(Ptr);
829  }
830 
832  const SCEV *Ptr) const {
833  if (!isStridedAccess(Ptr))
834  return nullptr;
835  const SCEVAddRecExpr *AddRec = cast<SCEVAddRecExpr>(Ptr);
836  return dyn_cast<SCEVConstant>(AddRec->getStepRecurrence(*SE));
837  }
838 
840  int64_t MergeDistance) const {
841  const SCEVConstant *Step = getConstantStrideStep(SE, Ptr);
842  if (!Step)
843  return false;
844  APInt StrideVal = Step->getAPInt();
845  if (StrideVal.getBitWidth() > 64)
846  return false;
847  // FIXME: Need to take absolute value for negative stride case.
848  return StrideVal.getSExtValue() < MergeDistance;
849  }
850 };
851 
852 /// CRTP base class for use as a mix-in that aids implementing
853 /// a TargetTransformInfo-compatible class.
854 template <typename T>
856 private:
858 
859 protected:
861 
862 public:
863  using BaseT::getGEPCost;
864 
865  InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr,
868  assert(PointeeType && Ptr && "can't get GEPCost of nullptr");
869  assert(cast<PointerType>(Ptr->getType()->getScalarType())
870  ->isOpaqueOrPointeeTypeMatches(PointeeType) &&
871  "explicit pointee type doesn't match operand's pointee type");
872  auto *BaseGV = dyn_cast<GlobalValue>(Ptr->stripPointerCasts());
873  bool HasBaseReg = (BaseGV == nullptr);
874 
875  auto PtrSizeBits = DL.getPointerTypeSizeInBits(Ptr->getType());
876  APInt BaseOffset(PtrSizeBits, 0);
877  int64_t Scale = 0;
878 
879  auto GTI = gep_type_begin(PointeeType, Operands);
880  Type *TargetType = nullptr;
881 
882  // Handle the case where the GEP instruction has a single operand,
883  // the basis, therefore TargetType is a nullptr.
884  if (Operands.empty())
885  return !BaseGV ? TTI::TCC_Free : TTI::TCC_Basic;
886 
887  for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) {
888  TargetType = GTI.getIndexedType();
889  // We assume that the cost of Scalar GEP with constant index and the
890  // cost of Vector GEP with splat constant index are the same.
891  const ConstantInt *ConstIdx = dyn_cast<ConstantInt>(*I);
892  if (!ConstIdx)
893  if (auto Splat = getSplatValue(*I))
894  ConstIdx = dyn_cast<ConstantInt>(Splat);
895  if (StructType *STy = GTI.getStructTypeOrNull()) {
896  // For structures the index is always splat or scalar constant
897  assert(ConstIdx && "Unexpected GEP index");
898  uint64_t Field = ConstIdx->getZExtValue();
899  BaseOffset += DL.getStructLayout(STy)->getElementOffset(Field);
900  } else {
901  // If this operand is a scalable type, bail out early.
902  // TODO: handle scalable vectors
903  if (isa<ScalableVectorType>(TargetType))
904  return TTI::TCC_Basic;
905  int64_t ElementSize =
906  DL.getTypeAllocSize(GTI.getIndexedType()).getFixedSize();
907  if (ConstIdx) {
908  BaseOffset +=
909  ConstIdx->getValue().sextOrTrunc(PtrSizeBits) * ElementSize;
910  } else {
911  // Needs scale register.
912  if (Scale != 0)
913  // No addressing mode takes two scale registers.
914  return TTI::TCC_Basic;
915  Scale = ElementSize;
916  }
917  }
918  }
919 
920  if (static_cast<T *>(this)->isLegalAddressingMode(
921  TargetType, const_cast<GlobalValue *>(BaseGV),
922  BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale,
923  Ptr->getType()->getPointerAddressSpace()))
924  return TTI::TCC_Free;
925  return TTI::TCC_Basic;
926  }
927 
930  auto *TargetTTI = static_cast<T *>(this);
931  // Handle non-intrinsic calls, invokes, and callbr.
932  // FIXME: Unlikely to be true for anything but CodeSize.
933  auto *CB = dyn_cast<CallBase>(U);
934  if (CB && !isa<IntrinsicInst>(U)) {
935  if (const Function *F = CB->getCalledFunction()) {
936  if (!TargetTTI->isLoweredToCall(F))
937  return TTI::TCC_Basic; // Give a basic cost if it will be lowered
938 
939  return TTI::TCC_Basic * (F->getFunctionType()->getNumParams() + 1);
940  }
941  // For indirect or other calls, scale cost by number of arguments.
942  return TTI::TCC_Basic * (CB->arg_size() + 1);
943  }
944 
945  Type *Ty = U->getType();
946  Type *OpTy =
947  U->getNumOperands() == 1 ? U->getOperand(0)->getType() : nullptr;
948  unsigned Opcode = Operator::getOpcode(U);
949  auto *I = dyn_cast<Instruction>(U);
950  switch (Opcode) {
951  default:
952  break;
953  case Instruction::Call: {
954  assert(isa<IntrinsicInst>(U) && "Unexpected non-intrinsic call");
955  auto *Intrinsic = cast<IntrinsicInst>(U);
956  IntrinsicCostAttributes CostAttrs(Intrinsic->getIntrinsicID(), *CB);
957  return TargetTTI->getIntrinsicInstrCost(CostAttrs, CostKind);
958  }
959  case Instruction::Br:
960  case Instruction::Ret:
961  case Instruction::PHI:
962  case Instruction::Switch:
963  return TargetTTI->getCFInstrCost(Opcode, CostKind, I);
964  case Instruction::ExtractValue:
965  case Instruction::Freeze:
966  return TTI::TCC_Free;
967  case Instruction::Alloca:
968  if (cast<AllocaInst>(U)->isStaticAlloca())
969  return TTI::TCC_Free;
970  break;
971  case Instruction::GetElementPtr: {
972  const auto *GEP = cast<GEPOperator>(U);
973  return TargetTTI->getGEPCost(GEP->getSourceElementType(),
974  GEP->getPointerOperand(),
975  Operands.drop_front(), CostKind);
976  }
977  case Instruction::Add:
978  case Instruction::FAdd:
979  case Instruction::Sub:
980  case Instruction::FSub:
981  case Instruction::Mul:
982  case Instruction::FMul:
983  case Instruction::UDiv:
984  case Instruction::SDiv:
985  case Instruction::FDiv:
986  case Instruction::URem:
987  case Instruction::SRem:
988  case Instruction::FRem:
989  case Instruction::Shl:
990  case Instruction::LShr:
991  case Instruction::AShr:
992  case Instruction::And:
993  case Instruction::Or:
994  case Instruction::Xor:
995  case Instruction::FNeg: {
998  TTI::OperandValueKind Op1VK =
999  TTI::getOperandInfo(U->getOperand(0), Op1VP);
1000  TTI::OperandValueKind Op2VK = Opcode != Instruction::FNeg ?
1003  return TargetTTI->getArithmeticInstrCost(Opcode, Ty, CostKind,
1004  Op1VK, Op2VK,
1005  Op1VP, Op2VP, Operands, I);
1006  }
1007  case Instruction::IntToPtr:
1008  case Instruction::PtrToInt:
1009  case Instruction::SIToFP:
1010  case Instruction::UIToFP:
1011  case Instruction::FPToUI:
1012  case Instruction::FPToSI:
1013  case Instruction::Trunc:
1014  case Instruction::FPTrunc:
1015  case Instruction::BitCast:
1016  case Instruction::FPExt:
1017  case Instruction::SExt:
1018  case Instruction::ZExt:
1019  case Instruction::AddrSpaceCast:
1020  return TargetTTI->getCastInstrCost(
1021  Opcode, Ty, OpTy, TTI::getCastContextHint(I), CostKind, I);
1022  case Instruction::Store: {
1023  auto *SI = cast<StoreInst>(U);
1024  Type *ValTy = U->getOperand(0)->getType();
1025  return TargetTTI->getMemoryOpCost(Opcode, ValTy, SI->getAlign(),
1026  SI->getPointerAddressSpace(),
1027  CostKind, I);
1028  }
1029  case Instruction::Load: {
1030  auto *LI = cast<LoadInst>(U);
1031  return TargetTTI->getMemoryOpCost(Opcode, U->getType(), LI->getAlign(),
1032  LI->getPointerAddressSpace(),
1033  CostKind, I);
1034  }
1035  case Instruction::Select: {
1036  const Value *Op0, *Op1;
1037  if (match(U, m_LogicalAnd(m_Value(Op0), m_Value(Op1))) ||
1038  match(U, m_LogicalOr(m_Value(Op0), m_Value(Op1)))) {
1039  // select x, y, false --> x & y
1040  // select x, true, y --> x | y
1043  TTI::OperandValueKind Op1VK = TTI::getOperandInfo(Op0, Op1VP);
1044  TTI::OperandValueKind Op2VK = TTI::getOperandInfo(Op1, Op2VP);
1045  assert(Op0->getType()->getScalarSizeInBits() == 1 &&
1046  Op1->getType()->getScalarSizeInBits() == 1);
1047 
1049  return TargetTTI->getArithmeticInstrCost(
1050  match(U, m_LogicalOr()) ? Instruction::Or : Instruction::And, Ty,
1051  CostKind, Op1VK, Op2VK, Op1VP, Op2VP, Operands, I);
1052  }
1053  Type *CondTy = U->getOperand(0)->getType();
1054  return TargetTTI->getCmpSelInstrCost(Opcode, U->getType(), CondTy,
1056  CostKind, I);
1057  }
1058  case Instruction::ICmp:
1059  case Instruction::FCmp: {
1060  Type *ValTy = U->getOperand(0)->getType();
1061  // TODO: Also handle ICmp/FCmp constant expressions.
1062  return TargetTTI->getCmpSelInstrCost(Opcode, ValTy, U->getType(),
1063  I ? cast<CmpInst>(I)->getPredicate()
1065  CostKind, I);
1066  }
1067  case Instruction::InsertElement: {
1068  auto *IE = dyn_cast<InsertElementInst>(U);
1069  if (!IE)
1070  return TTI::TCC_Basic; // FIXME
1071  unsigned Idx = -1;
1072  if (auto *CI = dyn_cast<ConstantInt>(IE->getOperand(2)))
1073  if (CI->getValue().getActiveBits() <= 32)
1074  Idx = CI->getZExtValue();
1075  return TargetTTI->getVectorInstrCost(Opcode, Ty, Idx);
1076  }
1077  case Instruction::ShuffleVector: {
1078  auto *Shuffle = dyn_cast<ShuffleVectorInst>(U);
1079  if (!Shuffle)
1080  return TTI::TCC_Basic; // FIXME
1081 
1082  auto *VecTy = cast<VectorType>(U->getType());
1083  auto *VecSrcTy = cast<VectorType>(U->getOperand(0)->getType());
1084  int NumSubElts, SubIndex;
1085 
1086  if (Shuffle->changesLength()) {
1087  // Treat a 'subvector widening' as a free shuffle.
1088  if (Shuffle->increasesLength() && Shuffle->isIdentityWithPadding())
1089  return 0;
1090 
1091  if (Shuffle->isExtractSubvectorMask(SubIndex))
1092  return TargetTTI->getShuffleCost(TTI::SK_ExtractSubvector, VecSrcTy,
1093  Shuffle->getShuffleMask(), SubIndex,
1094  VecTy);
1095 
1096  if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1097  return TargetTTI->getShuffleCost(
1098  TTI::SK_InsertSubvector, VecTy, Shuffle->getShuffleMask(),
1099  SubIndex,
1100  FixedVectorType::get(VecTy->getScalarType(), NumSubElts));
1101 
1102  return CostKind == TTI::TCK_RecipThroughput ? -1 : 1;
1103  }
1104 
1105  if (Shuffle->isIdentity())
1106  return 0;
1107 
1108  if (Shuffle->isReverse())
1109  return TargetTTI->getShuffleCost(TTI::SK_Reverse, VecTy,
1110  Shuffle->getShuffleMask(), 0, nullptr);
1111 
1112  if (Shuffle->isSelect())
1113  return TargetTTI->getShuffleCost(TTI::SK_Select, VecTy,
1114  Shuffle->getShuffleMask(), 0, nullptr);
1115 
1116  if (Shuffle->isTranspose())
1117  return TargetTTI->getShuffleCost(TTI::SK_Transpose, VecTy,
1118  Shuffle->getShuffleMask(), 0, nullptr);
1119 
1120  if (Shuffle->isZeroEltSplat())
1121  return TargetTTI->getShuffleCost(TTI::SK_Broadcast, VecTy,
1122  Shuffle->getShuffleMask(), 0, nullptr);
1123 
1124  if (Shuffle->isSingleSource())
1125  return TargetTTI->getShuffleCost(TTI::SK_PermuteSingleSrc, VecTy,
1126  Shuffle->getShuffleMask(), 0, nullptr);
1127 
1128  if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1129  return TargetTTI->getShuffleCost(
1130  TTI::SK_InsertSubvector, VecTy, Shuffle->getShuffleMask(), SubIndex,
1131  FixedVectorType::get(VecTy->getScalarType(), NumSubElts));
1132 
1133  return TargetTTI->getShuffleCost(TTI::SK_PermuteTwoSrc, VecTy,
1134  Shuffle->getShuffleMask(), 0, nullptr);
1135  }
1136  case Instruction::ExtractElement: {
1137  auto *EEI = dyn_cast<ExtractElementInst>(U);
1138  if (!EEI)
1139  return TTI::TCC_Basic; // FIXME
1140  unsigned Idx = -1;
1141  if (auto *CI = dyn_cast<ConstantInt>(EEI->getOperand(1)))
1142  if (CI->getValue().getActiveBits() <= 32)
1143  Idx = CI->getZExtValue();
1144  Type *DstTy = U->getOperand(0)->getType();
1145  return TargetTTI->getVectorInstrCost(Opcode, DstTy, Idx);
1146  }
1147  }
1148  // By default, just classify everything as 'basic'.
1149  return TTI::TCC_Basic;
1150  }
1151 
1153  SmallVector<const Value *, 4> Operands(I->operand_values());
1154  if (getUserCost(I, Operands, TTI::TCK_Latency) == TTI::TCC_Free)
1155  return 0;
1156 
1157  if (isa<LoadInst>(I))
1158  return 4;
1159 
1160  Type *DstTy = I->getType();
1161 
1162  // Usually an intrinsic is a simple instruction.
1163  // A real function call is much slower.
1164  if (auto *CI = dyn_cast<CallInst>(I)) {
1165  const Function *F = CI->getCalledFunction();
1166  if (!F || static_cast<T *>(this)->isLoweredToCall(F))
1167  return 40;
1168  // Some intrinsics return a value and a flag, we use the value type
1169  // to decide its latency.
1170  if (StructType *StructTy = dyn_cast<StructType>(DstTy))
1171  DstTy = StructTy->getElementType(0);
1172  // Fall through to simple instructions.
1173  }
1174 
1175  if (VectorType *VectorTy = dyn_cast<VectorType>(DstTy))
1176  DstTy = VectorTy->getElementType();
1177  if (DstTy->isFloatingPointTy())
1178  return 3;
1179 
1180  return 1;
1181  }
1182 };
1183 } // namespace llvm
1184 
1185 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::CacheLevel::L1D
@ L1D
llvm::orc::BaseT
RTTIExtends< ObjectLinkingLayer, ObjectLayer > BaseT
Definition: ObjectLinkingLayer.cpp:615
llvm::TargetTransformInfoImplBase::canHaveNonUndefGlobalInitializerInAddressSpace
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Definition: TargetTransformInfoImpl.h:107
llvm::TargetTransformInfoImplBase::getCacheLineSize
unsigned getCacheLineSize() const
Definition: TargetTransformInfoImpl.h:417
llvm::TargetTransformInfo::SK_Select
@ SK_Select
Selects elements from the corresponding lane of either source operand.
Definition: TargetTransformInfo.h:862
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm::TargetTransformInfoImplBase::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Definition: TargetTransformInfoImpl.h:154
llvm::TargetTransformInfo::LSRCost::NumRegs
unsigned NumRegs
Definition: TargetTransformInfo.h:418
llvm::TargetTransformInfo::TCC_Expensive
@ TCC_Expensive
The cost of a 'div' instruction on x86.
Definition: TargetTransformInfo.h:264
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1338
llvm::TargetTransformInfoImplBase::useAA
bool useAA() const
Definition: TargetTransformInfoImpl.h:295
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetTransformInfoImplBase::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, const LoopAccessInfo *LAI) const
Definition: TargetTransformInfoImpl.h:160
llvm::TargetTransformInfo::MemIndexedMode
MemIndexedMode
The type of load/store indexing.
Definition: TargetTransformInfo.h:1286
llvm::TargetTransformInfo::TCK_Latency
@ TCK_Latency
The latency of instruction.
Definition: TargetTransformInfo.h:213
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
llvm::TargetTransformInfoImplBase::enableOrderedReductions
bool enableOrderedReductions() const
Definition: TargetTransformInfoImpl.h:268
llvm::TargetTransformInfoImplBase::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const
Definition: TargetTransformInfoImpl.h:111
llvm::TargetTransformInfoImplBase::isStridedAccess
bool isStridedAccess(const SCEV *Ptr) const
Definition: TargetTransformInfoImpl.h:827
IntrinsicInst.h
llvm::ElementCount
Definition: TypeSize.h:386
llvm::TargetTransformInfoImplBase::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: TargetTransformInfoImpl.h:401
llvm::TypeSize::getFixedSize
ScalarTy getFixedSize() const
Definition: TypeSize.h:426
T
llvm::Function
Definition: Function.h:62
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::TargetTransformInfoImplBase::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const
Definition: TargetTransformInfoImpl.h:200
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:592
llvm::TargetTransformInfoImplCRTPBase::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:928
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
GetElementPtrTypeIterator.h
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:308
llvm::ConstantInt::getValue
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:133
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::TargetTransformInfoImplBase::isLSRCostLess
bool isLSRCostLess(TTI::LSRCost &C1, TTI::LSRCost &C2) const
Definition: TargetTransformInfoImpl.h:210
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1474
llvm::TargetTransformInfoImplBase::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType) const
Definition: TargetTransformInfoImpl.h:266
llvm::TargetTransformInfoImplBase::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *, const SCEV *) const
Definition: TargetTransformInfoImpl.h:624
llvm::TargetTransformInfoImplBase::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Definition: TargetTransformInfoImpl.h:99
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:366
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:734
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:460
llvm::TargetTransformInfoImplBase::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: TargetTransformInfoImpl.h:399
llvm::TargetTransformInfoImplBase::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent() const
Definition: TargetTransformInfoImpl.h:75
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:151
llvm::TargetTransformInfoImplBase::TTI
TargetTransformInfo TTI
Definition: TargetTransformInfoImpl.h:36
llvm::TargetTransformInfoImplBase::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:278
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1381
llvm::TargetTransformInfo::LSRCost::NumIVMuls
unsigned NumIVMuls
Definition: TargetTransformInfo.h:420
llvm::TargetTransformInfoImplBase::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: TargetTransformInfoImpl.h:384
llvm::TargetTransformInfoImplBase::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:710
llvm::TargetTransformInfoImplBase::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Definition: TargetTransformInfoImpl.h:343
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1410
llvm::TargetTransformInfo::VPLegalization::Convert
@ Convert
Definition: TargetTransformInfo.h:1388
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:535
llvm::TargetTransformInfoImplBase::isLegalToVectorizeStore
bool isLegalToVectorizeStore(StoreInst *SI) const
Definition: TargetTransformInfoImpl.h:714
llvm::TargetTransformInfoImplBase::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const
Definition: TargetTransformInfoImpl.h:293
llvm::Optional
Definition: APInt.h:33
Operator.h
llvm::TargetTransformInfoImplBase::areFunctionArgsABICompatible
bool areFunctionArgsABICompatible(const Function *Caller, const Function *Callee, SmallPtrSetImpl< Argument * > &Args) const
Definition: TargetTransformInfoImpl.h:691
llvm::TargetTransformInfoImplBase::hasActiveVectorLength
bool hasActiveVectorLength() const
Definition: TargetTransformInfoImpl.h:761
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::TargetTransformInfoImplBase::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Definition: TargetTransformInfoImpl.h:93
llvm::TargetTransformInfoImplBase::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:360
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(const DataLayout &DL)
Definition: TargetTransformInfoImpl.h:40
llvm::TargetTransformInfoImplCRTPBase::getGEPCost
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:865
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::gep_type_begin
gep_type_iterator gep_type_begin(const User *GEP)
Definition: GetElementPtrTypeIterator.h:139
llvm::TargetTransformInfoImplBase::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *, VectorType *, bool, TTI::TargetCostKind) const
Definition: TargetTransformInfoImpl.h:635
llvm::Type::isFloatingPointTy
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Definition: Type.h:162
llvm::TargetTransformInfoImplBase::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:260
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetTransformInfo::SK_PermuteSingleSrc
@ SK_PermuteSingleSrc
Shuffle elements of single source vector with any shuffle mask.
Definition: TargetTransformInfo.h:870
llvm::TargetTransformInfoImplBase::haveFastSqrt
bool haveFastSqrt(Type *Ty) const
Definition: TargetTransformInfoImpl.h:347
llvm::Type::getInt8Ty
static IntegerType * getInt8Ty(LLVMContext &C)
Definition: Type.cpp:239
llvm::TargetTransformInfoImplBase::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization() const
Definition: TargetTransformInfoImpl.h:331
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:299
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:948
llvm::TargetTransformInfoImplBase::getConstantStrideStep
const SCEVConstant * getConstantStrideStep(ScalarEvolution *SE, const SCEV *Ptr) const
Definition: TargetTransformInfoImpl.h:831
llvm::TargetTransformInfoImplBase::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Definition: TargetTransformInfoImpl.h:101
llvm::TargetTransformInfo::SK_Broadcast
@ SK_Broadcast
Broadcast element 0 to all other elements.
Definition: TargetTransformInfo.h:860
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::TargetTransformInfo::LSRCost::AddRecCost
unsigned AddRecCost
Definition: TargetTransformInfo.h:419
llvm::TargetTransformInfoImplBase::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Definition: TargetTransformInfoImpl.h:291
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:48
llvm::TargetTransformInfoImplBase::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: TargetTransformInfoImpl.h:683
llvm::TargetTransformInfoImplBase::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: TargetTransformInfoImpl.h:405
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::TargetTransformInfo::LSRCost::SetupCost
unsigned SetupCost
Definition: TargetTransformInfo.h:423
llvm::TargetTransformInfoImplBase::getExtendedAddReductionCost
InstructionCost getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:641
llvm::TargetTransformInfoImplBase::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR() const
Definition: TargetTransformInfoImpl.h:217
llvm::TargetTransformInfoImplBase::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: TargetTransformInfoImpl.h:726
llvm::TargetTransformInfoImplBase::getPredictableBranchThreshold
BranchProbability getPredictableBranchThreshold() const
Definition: TargetTransformInfoImpl.h:87
llvm::TargetTransformInfoImplBase::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, bool *Fast) const
Definition: TargetTransformInfoImpl.h:337
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::TargetTransformInfoImplBase::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Definition: TargetTransformInfoImpl.h:270
llvm::TargetTransformInfo::SK_PermuteTwoSrc
@ SK_PermuteTwoSrc
Merge elements from two source vectors into one with any shuffle mask.
Definition: TargetTransformInfo.h:868
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::LinearPolySize< ElementCount >::get
static ElementCount get(ScalarTy MinVal, bool Scalable)
Definition: TypeSize.h:290
llvm::TargetTransformInfo::getCastContextHint
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
Definition: TargetTransformInfo.cpp:737
llvm::TargetTransformInfoImplBase::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF) const
Definition: TargetTransformInfoImpl.h:451
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(TargetTransformInfoImplBase &&Arg)
Definition: TargetTransformInfoImpl.h:46
llvm::TargetTransformInfoImplBase
Base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:34
llvm::TargetTransformInfoImplBase::getCacheAssociativity
llvm::Optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const
Definition: TargetTransformInfoImpl.h:431
llvm::PatternMatch::match
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
llvm::TargetTransformInfoImplBase::getPrefetchDistance
unsigned getPrefetchDistance() const
Definition: TargetTransformInfoImpl.h:442
llvm::TargetTransformInfoImplBase::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: TargetTransformInfoImpl.h:378
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:886
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:859
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1062
llvm::TargetTransformInfoImplBase::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:234
llvm::User
Definition: User.h:44
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetTransformInfoImplBase::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Definition: TargetTransformInfoImpl.h:303
llvm::TargetTransformInfoImplBase::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const
Definition: TargetTransformInfoImpl.h:542
llvm::TargetTransformInfoImplBase::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfoImpl.h:669
llvm::TargetTransformInfoImplBase::hasBranchDivergence
bool hasBranchDivergence() const
Definition: TargetTransformInfoImpl.h:91
llvm::TargetTransformInfoImplBase::isIndexedStoreLegal
bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
Definition: TargetTransformInfoImpl.h:705
llvm::TargetTransformInfoImplBase::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Definition: TargetTransformInfoImpl.h:301
llvm::Instruction
Definition: Instruction.h:45
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:191
llvm::TargetTransformInfoImplBase::getNumberOfParts
unsigned getNumberOfParts(Type *Tp) const
Definition: TargetTransformInfoImpl.h:622
llvm::TargetTransformInfoImplBase::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
Definition: TargetTransformInfoImpl.h:365
llvm::Operator::getOpcode
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
Definition: Operator.h:41
llvm::TargetTransformInfoImplBase::isTypeLegal
bool isTypeLegal(Type *Ty) const
Definition: TargetTransformInfoImpl.h:297
llvm::TargetTransformInfoImplBase::isLegalAddressingMode
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:202
llvm::TargetTransformInfoImplBase::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:526
llvm::TargetTransformInfoImplBase::getRegUsageForType
InstructionCost getRegUsageForType(Type *Ty) const
Definition: TargetTransformInfoImpl.h:299
llvm::TargetTransformInfoImplBase::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
Definition: TargetTransformInfoImpl.h:664
llvm::TargetTransformInfoImplCRTPBase
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:855
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetTransformInfoImplBase::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:272
PatternMatch.h
llvm::TargetTransformInfoImplBase::getCostOfKeepingLiveOverCall
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
Definition: TargetTransformInfoImpl.h:647
llvm::TargetTransformInfoImplBase::enableWritePrefetching
bool enableWritePrefetching() const
Definition: TargetTransformInfoImpl.h:449
llvm::FixedVectorType::get
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
Definition: Type.cpp:686
llvm::TargetTransformInfoImplBase::enableMemCmpExpansion
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: TargetTransformInfoImpl.h:326
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:153
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::TargetTransformInfoImplBase::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Definition: TargetTransformInfoImpl.h:95
llvm::TargetTransformInfoImplBase::getVPLegalizationStrategy
TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: TargetTransformInfoImpl.h:764
llvm::TargetTransformInfoImplBase::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:554
llvm::None
const NoneType None
Definition: None.h:23
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:284
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
Type.h
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:118
llvm::TargetTransformInfoImplBase::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:560
llvm::TargetTransformInfo::PSK_Software
@ PSK_Software
Definition: TargetTransformInfo.h:592
llvm::TargetTransformInfoImplBase::getCacheSize
llvm::Optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const
Definition: TargetTransformInfoImpl.h:420
llvm::TargetTransformInfoImplBase::emitGetActiveLaneMask
bool emitGetActiveLaneMask() const
Definition: TargetTransformInfoImpl.h:167
llvm::TargetTransformInfoImplBase::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I) const
Definition: TargetTransformInfoImpl.h:219
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::ARM_PROC::IE
@ IE
Definition: ARMBaseInfo.h:27
llvm::TargetTransformInfoImplBase::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: TargetTransformInfoImpl.h:183
llvm::TargetTransformInfoImplBase::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: TargetTransformInfoImpl.h:750
llvm::TargetTransformInfoImplBase::supportsScalableVectors
bool supportsScalableVectors() const
Definition: TargetTransformInfoImpl.h:759
llvm::TargetTransformInfoImplBase::enableMaskedInterleavedAccessVectorization
bool enableMaskedInterleavedAccessVectorization() const
Definition: TargetTransformInfoImpl.h:333
llvm::TargetTransformInfo::SK_Reverse
@ SK_Reverse
Reverse the order of the vector.
Definition: TargetTransformInfo.h:861
llvm::TargetTransformInfoImplCRTPBase::TargetTransformInfoImplCRTPBase
TargetTransformInfoImplCRTPBase(const DataLayout &DL)
Definition: TargetTransformInfoImpl.h:860
llvm::TargetTransformInfoImplBase::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:616
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
VectorUtils.h
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:77
llvm::TargetTransformInfoImplBase::canMacroFuseCmp
bool canMacroFuseCmp() const
Definition: TargetTransformInfoImpl.h:221
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:304
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::TargetTransformInfo::SK_InsertSubvector
@ SK_InsertSubvector
InsertSubvector. Index indicates start offset.
Definition: TargetTransformInfo.h:866
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetTransformInfoImplBase::getEstimatedNumberOfCaseClusters
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Definition: TargetTransformInfoImpl.h:62
llvm::TargetTransformInfoImplBase::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:242
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::TargetTransformInfoImplBase::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth() const
Definition: TargetTransformInfoImpl.h:403
uint64_t
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:414
llvm::TargetTransformInfoImplBase::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:721
llvm::PatternMatch::m_LogicalOr
LogicalOp_match< LHS, RHS, Instruction::Or > m_LogicalOr(const LHS &L, const RHS &R)
Matches L || R either in the form of L | R or L ? true : R.
Definition: PatternMatch.h:2522
llvm::TargetTransformInfoImplBase::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned, VectorType *, Optional< FastMathFlags > FMF, TTI::TargetCostKind) const
Definition: TargetTransformInfoImpl.h:629
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::TargetTransformInfoImplBase::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Definition: TargetTransformInfoImpl.h:177
llvm::TargetTransformInfoImplBase::getPreferredAddressingMode
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Definition: TargetTransformInfoImpl.h:230
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:428
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfoImplBase::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:482
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:886
llvm::LoopAccessInfo
Drive the analysis of memory accesses in the loop.
Definition: LoopAccessAnalysis.h:515
llvm::SCEVConstant
This class represents a constant integer value.
Definition: ScalarEvolutionExpressions.h:47
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetTransformInfo::VPLegalization::Discard
@ Discard
Definition: TargetTransformInfo.h:1386
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::TargetTransformInfoImplBase::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
Definition: TargetTransformInfoImpl.h:411
llvm::TargetTransformInfoImplBase::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Definition: TargetTransformInfoImpl.h:118
llvm::CmpInst::BAD_ICMP_PREDICATE
@ BAD_ICMP_PREDICATE
Definition: InstrTypes.h:753
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::TargetTransformInfo::LSRCost::ScaleCost
unsigned ScaleCost
Definition: TargetTransformInfo.h:424
llvm::TargetTransformInfoImplBase::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
Definition: TargetTransformInfoImpl.h:315
llvm::TargetTransformInfoImplBase::getInterleavedMemoryOpCost
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) const
Definition: TargetTransformInfoImpl.h:568
llvm::TargetTransformInfoImplBase::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: TargetTransformInfoImpl.h:651
llvm::TargetTransformInfoImplBase::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Definition: TargetTransformInfoImpl.h:322
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:878
llvm::PatternMatch::m_Value
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:76
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::TargetTransformInfoImplBase::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned, unsigned) const
Definition: TargetTransformInfoImpl.h:106
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:761
llvm::TargetTransformInfoImplBase::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:249
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:262
llvm::TargetTransformInfoImplBase::isElementTypeLegalForScalableVector
bool isElementTypeLegalForScalableVector(Type *Ty) const
Definition: TargetTransformInfoImpl.h:731
llvm::TargetTransformInfoImplBase::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: TargetTransformInfoImpl.h:755
llvm::TargetTransformInfoImplBase::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier() const
Definition: TargetTransformInfoImpl.h:72
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LoopInfo
Definition: LoopInfo.h:1083
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
DataLayout.h
llvm::StructType
Class to represent struct types.
Definition: DerivedTypes.h:213
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:41
llvm::TargetTransformInfoImplBase::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfoImpl.h:757
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::TargetTransformInfoImplCRTPBase::getInstructionLatency
InstructionCost getInstructionLatency(const Instruction *I)
Definition: TargetTransformInfoImpl.h:1152
llvm::TargetTransformInfoImplBase::LSRWithInstrQueries
bool LSRWithInstrQueries() const
Definition: TargetTransformInfoImpl.h:289
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::TargetTransformInfoImplBase::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
Definition: TargetTransformInfoImpl.h:309
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetTransformInfoImplBase::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
Definition: TargetTransformInfoImpl.h:320
llvm::TargetTransformInfoImplBase::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Definition: TargetTransformInfoImpl.h:349
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::TargetTransformInfoImplBase::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:535
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:639
llvm::TargetTransformInfoImplBase::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:238
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:421
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:879
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:286
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:175
llvm::TargetTransformInfo::SK_Transpose
@ SK_Transpose
Transpose two vectors.
Definition: TargetTransformInfo.h:865
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::TargetTransformInfoImplBase::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfoImpl.h:675
llvm::Value::stripPointerCasts
const Value * stripPointerCasts() const
Strip off pointer casts, all-zero GEPs and address space casts.
Definition: Value.cpp:687
llvm::TargetTransformInfo::CacheLevel::L2D
@ L2D
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:142
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:206
llvm::TargetTransformInfoImplBase::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr) const
Definition: TargetTransformInfoImpl.h:453
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:162
llvm::TargetTransformInfoImplBase::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: TargetTransformInfoImpl.h:745
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::KnownBits
Definition: KnownBits.h:23
llvm::TargetTransformInfoImplBase::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef< int > Mask, int Index, VectorType *SubTp) const
Definition: TargetTransformInfoImpl.h:476
llvm::TargetTransformInfo::LSRCost::NumBaseAdds
unsigned NumBaseAdds
Definition: TargetTransformInfo.h:421
llvm::TargetTransformInfoImplBase::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: TargetTransformInfoImpl.h:655
llvm::TargetTransformInfoImplBase::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const
Definition: TargetTransformInfoImpl.h:448
llvm::TargetTransformInfoImplBase::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:372
llvm::TargetTransformInfoImplBase::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I) const
Definition: TargetTransformInfoImpl.h:77
llvm::TargetTransformInfoImplBase::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Definition: TargetTransformInfoImpl.h:113
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:390
VPLegalization
TargetTransformInfo::VPLegalization VPLegalization
Definition: ExpandVectorPredication.cpp:36
llvm::APInt::sextOrTrunc
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition: APInt.cpp:978
llvm::TargetTransformInfoImplBase::minRequiredElementSize
unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const
Definition: TargetTransformInfoImpl.h:773
llvm::TypeSize
Definition: TypeSize.h:417
llvm::SCEVAddRecExpr
This node represents a polynomial recurrence on the trip count of the specified loop.
Definition: ScalarEvolutionExpressions.h:352
Function.h
llvm::TargetTransformInfoImplBase::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfoImpl.h:733
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::TargetTransformInfoImplBase::isIndexedLoadLegal
bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
Definition: TargetTransformInfoImpl.h:700
llvm::TargetTransformInfoImplBase::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Definition: TargetTransformInfoImpl.h:443
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:221
llvm::User::operand_values
iterator_range< value_op_iterator > operand_values()
Definition: User.h:266
llvm::TargetTransformInfo::LSRCost::ImmCost
unsigned ImmCost
Definition: TargetTransformInfo.h:422
llvm::TargetTransformInfoImplBase::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const
Definition: TargetTransformInfoImpl.h:198
llvm::TargetTransformInfoImplBase::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:547
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:183
llvm::TargetTransformInfoImplBase::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: TargetTransformInfoImpl.h:380
llvm::TargetTransformInfoImplBase::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: TargetTransformInfoImpl.h:395
llvm::TargetTransformInfoImplBase::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Definition: TargetTransformInfoImpl.h:223
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfoImplBase::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: TargetTransformInfoImpl.h:171
llvm::SCEVConstant::getAPInt
const APInt & getAPInt() const
Definition: ScalarEvolutionExpressions.h:57
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:95
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::TargetTransformInfoImplBase::getUnrollingPreferences
void getUnrollingPreferences(Loop *, ScalarEvolution &, TTI::UnrollingPreferences &, OptimizationRemarkEmitter *) const
Definition: TargetTransformInfoImpl.h:191
llvm::TargetTransformInfoImplBase::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
Definition: TargetTransformInfoImpl.h:520
llvm::TargetTransformInfoImplBase::isConstantStridedAccessLessThan
bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance) const
Definition: TargetTransformInfoImpl.h:839
llvm::TargetTransformInfoImplBase::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe() const
Definition: TargetTransformInfoImpl.h:335
ScalarEvolutionExpressions.h
llvm::TargetTransformInfoImplBase::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: TargetTransformInfoImpl.h:97
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:71
llvm::TargetTransformInfoImplBase::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType) const
Definition: TargetTransformInfoImpl.h:264
llvm::User::getNumOperands
unsigned getNumOperands() const
Definition: User.h:191
llvm::IntrinsicCostAttributes::getID
Intrinsic::ID getID() const
Definition: TargetTransformInfo.h:148
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:907
llvm::TargetTransformInfoImplBase::isLegalToVectorizeLoad
bool isLegalToVectorizeLoad(LoadInst *LI) const
Definition: TargetTransformInfoImpl.h:712
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
TargetTransformInfo.h
llvm::PatternMatch
Definition: PatternMatch.h:47
llvm::SmallVectorImpl< int >
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:70
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1161
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
llvm::TargetTransformInfoImplBase::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfoImpl.h:739
llvm::TargetTransformInfoImplBase::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:716
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:172
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(const TargetTransformInfoImplBase &Arg)
Definition: TargetTransformInfoImpl.h:44
llvm::TargetTransformInfoImplBase::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:256
llvm::TargetTransformInfo::getOperandInfo
static OperandValueKind getOperandInfo(const Value *V, OperandValueProperties &OpProps)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
Definition: TargetTransformInfo.cpp:665
llvm::TargetTransformInfo::TCC_Basic
@ TCC_Basic
The cost of a typical 'add' instruction.
Definition: TargetTransformInfo.h:263
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3212
llvm::OptimizedStructLayoutField
A field in a structure.
Definition: OptimizedStructLayout.h:45
llvm::TargetTransformInfoImplBase::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Definition: TargetTransformInfoImpl.h:305
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::TargetTransformInfoImplBase::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: TargetTransformInfoImpl.h:73
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3068
llvm::TargetTransformInfoImplBase::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:575
llvm::TargetTransformInfoImplBase::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Definition: TargetTransformInfoImpl.h:276
llvm::TargetTransformInfoImplBase::useColdCCForColdCall
bool useColdCCForColdCall(Function &F) const
Definition: TargetTransformInfoImpl.h:307
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:212
llvm::TargetTransformInfoImplBase::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const
Definition: TargetTransformInfoImpl.h:355
llvm::TargetTransformInfo::AMK_None
@ AMK_None
Definition: TargetTransformInfo.h:642
llvm::TargetTransformInfo::SK_ExtractSubvector
@ SK_ExtractSubvector
ExtractSubvector Index indicates start offset.
Definition: TargetTransformInfo.h:867
llvm::PatternMatch::m_LogicalAnd
LogicalOp_match< LHS, RHS, Instruction::And > m_LogicalAnd(const LHS &L, const RHS &R)
Matches L && R either in the form of L & R or L ? R : false.
Definition: PatternMatch.h:2504
llvm::TargetTransformInfoImplBase::getPeelingPreferences
void getPeelingPreferences(Loop *, ScalarEvolution &, TTI::PeelingPreferences &) const
Definition: TargetTransformInfoImpl.h:195
llvm::SCEVAddRecExpr::getStepRecurrence
const SCEV * getStepRecurrence(ScalarEvolution &SE) const
Constructs and returns the recurrence indicating how much this expression steps by.
Definition: ScalarEvolutionExpressions.h:370
llvm::TargetTransformInfoImplBase::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: TargetTransformInfoImpl.h:409
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::TargetTransformInfoImplBase::getFPOpCost
InstructionCost getFPOpCost(Type *Ty) const
Definition: TargetTransformInfoImpl.h:351