LLVM  14.0.0git
TargetTransformInfoImpl.h
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1 //===- TargetTransformInfoImpl.h --------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file provides helpers for the implementation of
10 /// a TargetTransformInfo-conforming class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
15 #define LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
16 
20 #include "llvm/IR/DataLayout.h"
21 #include "llvm/IR/Function.h"
23 #include "llvm/IR/IntrinsicInst.h"
24 #include "llvm/IR/Operator.h"
25 #include "llvm/IR/PatternMatch.h"
26 #include "llvm/IR/Type.h"
27 
28 using namespace llvm::PatternMatch;
29 
30 namespace llvm {
31 
32 /// Base class for use as a mix-in that aids implementing
33 /// a TargetTransformInfo-compatible class.
35 protected:
37 
38  const DataLayout &DL;
39 
41 
42 public:
43  // Provide value semantics. MSVC requires that we spell all of these out.
45  : DL(Arg.DL) {}
47 
48  const DataLayout &getDataLayout() const { return DL; }
49 
51  getGEPCost(Type *PointeeType, const Value *Ptr,
54  // In the basic model, we just assume that all-constant GEPs will be folded
55  // into their uses via addressing modes.
56  for (unsigned Idx = 0, Size = Operands.size(); Idx != Size; ++Idx)
57  if (!isa<Constant>(Operands[Idx]))
58  return TTI::TCC_Basic;
59 
60  return TTI::TCC_Free;
61  }
62 
64  unsigned &JTSize,
65  ProfileSummaryInfo *PSI,
66  BlockFrequencyInfo *BFI) const {
67  (void)PSI;
68  (void)BFI;
69  JTSize = 0;
70  return SI.getNumCases();
71  }
72 
73  unsigned getInliningThresholdMultiplier() const { return 1; }
74  unsigned adjustInliningThreshold(const CallBase *CB) const { return 0; }
75 
76  int getInlinerVectorBonusPercent() const { return 150; }
77 
79  return TTI::TCC_Expensive;
80  }
81 
82  // Although this default value is arbitrary, it is not random. It is assumed
83  // that a condition that evaluates the same way by a higher percentage than
84  // this is best represented as control flow. Therefore, the default value N
85  // should be set such that the win from N% correct executions is greater than
86  // the loss from (100 - N)% mispredicted executions for the majority of
87  // intended targets.
89  return BranchProbability(99, 100);
90  }
91 
92  bool hasBranchDivergence() const { return false; }
93 
94  bool useGPUDivergenceAnalysis() const { return false; }
95 
96  bool isSourceOfDivergence(const Value *V) const { return false; }
97 
98  bool isAlwaysUniform(const Value *V) const { return false; }
99 
100  unsigned getFlatAddressSpace() const { return -1; }
101 
103  Intrinsic::ID IID) const {
104  return false;
105  }
106 
107  bool isNoopAddrSpaceCast(unsigned, unsigned) const { return false; }
108 
109  unsigned getAssumedAddrSpace(const Value *V) const { return -1; }
110 
112  Value *NewV) const {
113  return nullptr;
114  }
115 
116  bool isLoweredToCall(const Function *F) const {
117  assert(F && "A concrete function must be provided to this routine.");
118 
119  // FIXME: These should almost certainly not be handled here, and instead
120  // handled with the help of TLI or the target itself. This was largely
121  // ported from existing analysis heuristics here so that such refactorings
122  // can take place in the future.
123 
124  if (F->isIntrinsic())
125  return false;
126 
127  if (F->hasLocalLinkage() || !F->hasName())
128  return true;
129 
130  StringRef Name = F->getName();
131 
132  // These will all likely lower to a single selection DAG node.
133  if (Name == "copysign" || Name == "copysignf" || Name == "copysignl" ||
134  Name == "fabs" || Name == "fabsf" || Name == "fabsl" || Name == "sin" ||
135  Name == "fmin" || Name == "fminf" || Name == "fminl" ||
136  Name == "fmax" || Name == "fmaxf" || Name == "fmaxl" ||
137  Name == "sinf" || Name == "sinl" || Name == "cos" || Name == "cosf" ||
138  Name == "cosl" || Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl")
139  return false;
140 
141  // These are all likely to be optimized into something smaller.
142  if (Name == "pow" || Name == "powf" || Name == "powl" || Name == "exp2" ||
143  Name == "exp2l" || Name == "exp2f" || Name == "floor" ||
144  Name == "floorf" || Name == "ceil" || Name == "round" ||
145  Name == "ffs" || Name == "ffsl" || Name == "abs" || Name == "labs" ||
146  Name == "llabs")
147  return false;
148 
149  return true;
150  }
151 
153  AssumptionCache &AC, TargetLibraryInfo *LibInfo,
154  HardwareLoopInfo &HWLoopInfo) const {
155  return false;
156  }
157 
160  DominatorTree *DT,
161  const LoopAccessInfo *LAI) const {
162  return false;
163  }
164 
165  bool emitGetActiveLaneMask() const {
166  return false;
167  }
168 
170  IntrinsicInst &II) const {
171  return None;
172  }
173 
176  APInt DemandedMask, KnownBits &Known,
177  bool &KnownBitsComputed) const {
178  return None;
179  }
180 
182  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
183  APInt &UndefElts2, APInt &UndefElts3,
184  std::function<void(Instruction *, unsigned, APInt, APInt &)>
185  SimplifyAndSetOp) const {
186  return None;
187  }
188 
191  OptimizationRemarkEmitter *) const {}
192 
194  TTI::PeelingPreferences &) const {}
195 
196  bool isLegalAddImmediate(int64_t Imm) const { return false; }
197 
198  bool isLegalICmpImmediate(int64_t Imm) const { return false; }
199 
200  bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
201  bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
202  Instruction *I = nullptr) const {
203  // Guess that only reg and reg+reg addressing is allowed. This heuristic is
204  // taken from the implementation of LSR.
205  return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1);
206  }
207 
209  return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds,
210  C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
211  std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds,
212  C2.ScaleCost, C2.ImmCost, C2.SetupCost);
213  }
214 
215  bool isNumRegsMajorCostOfLSR() const { return true; }
216 
217  bool isProfitableLSRChainElement(Instruction *I) const { return false; }
218 
219  bool canMacroFuseCmp() const { return false; }
220 
223  TargetLibraryInfo *LibInfo) const {
224  return false;
225  }
226 
229  return TTI::AMK_None;
230  }
231 
232  bool isLegalMaskedStore(Type *DataType, Align Alignment) const {
233  return false;
234  }
235 
236  bool isLegalMaskedLoad(Type *DataType, Align Alignment) const {
237  return false;
238  }
239 
240  bool isLegalNTStore(Type *DataType, Align Alignment) const {
241  // By default, assume nontemporal memory stores are available for stores
242  // that are aligned and have a size that is a power of 2.
243  unsigned DataSize = DL.getTypeStoreSize(DataType);
244  return Alignment >= DataSize && isPowerOf2_32(DataSize);
245  }
246 
247  bool isLegalNTLoad(Type *DataType, Align Alignment) const {
248  // By default, assume nontemporal memory loads are available for loads that
249  // are aligned and have a size that is a power of 2.
250  unsigned DataSize = DL.getTypeStoreSize(DataType);
251  return Alignment >= DataSize && isPowerOf2_32(DataSize);
252  }
253 
254  bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
255  return false;
256  }
257 
258  bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
259  return false;
260  }
261 
262  bool isLegalMaskedCompressStore(Type *DataType) const { return false; }
263 
264  bool isLegalMaskedExpandLoad(Type *DataType) const { return false; }
265 
266  bool hasDivRemOp(Type *DataType, bool IsSigned) const { return false; }
267 
268  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const {
269  return false;
270  }
271 
272  bool prefersVectorizedAddressing() const { return true; }
273 
275  int64_t BaseOffset, bool HasBaseReg,
276  int64_t Scale,
277  unsigned AddrSpace) const {
278  // Guess that all legal addressing mode are free.
279  if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
280  AddrSpace))
281  return 0;
282  return -1;
283  }
284 
285  bool LSRWithInstrQueries() const { return false; }
286 
287  bool isTruncateFree(Type *Ty1, Type *Ty2) const { return false; }
288 
289  bool isProfitableToHoist(Instruction *I) const { return true; }
290 
291  bool useAA() const { return false; }
292 
293  bool isTypeLegal(Type *Ty) const { return false; }
294 
295  InstructionCost getRegUsageForType(Type *Ty) const { return 1; }
296 
297  bool shouldBuildLookupTables() const { return true; }
298 
299  bool shouldBuildLookupTablesForConstant(Constant *C) const { return true; }
300 
301  bool shouldBuildRelLookupTables() const { return false; }
302 
303  bool useColdCCForColdCall(Function &F) const { return false; }
304 
306  const APInt &DemandedElts,
307  bool Insert, bool Extract) const {
308  return 0;
309  }
310 
312  ArrayRef<Type *> Tys) const {
313  return 0;
314  }
315 
316  bool supportsEfficientVectorElementLoadStore() const { return false; }
317 
318  bool enableAggressiveInterleaving(bool LoopHasReductions) const {
319  return false;
320  }
321 
323  bool IsZeroCmp) const {
324  return {};
325  }
326 
327  bool enableInterleavedAccessVectorization() const { return false; }
328 
329  bool enableMaskedInterleavedAccessVectorization() const { return false; }
330 
331  bool isFPVectorizationPotentiallyUnsafe() const { return false; }
332 
334  unsigned AddressSpace, Align Alignment,
335  bool *Fast) const {
336  return false;
337  }
338 
339  TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const {
340  return TTI::PSK_Software;
341  }
342 
343  bool haveFastSqrt(Type *Ty) const { return false; }
344 
345  bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { return true; }
346 
349  }
350 
351  InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
352  const APInt &Imm, Type *Ty) const {
353  return 0;
354  }
355 
358  return TTI::TCC_Basic;
359  }
360 
361  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
362  const APInt &Imm, Type *Ty,
364  Instruction *Inst = nullptr) const {
365  return TTI::TCC_Free;
366  }
367 
369  const APInt &Imm, Type *Ty,
371  return TTI::TCC_Free;
372  }
373 
374  unsigned getNumberOfRegisters(unsigned ClassID) const { return 8; }
375 
376  unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
377  return Vector ? 1 : 0;
378  };
379 
380  const char *getRegisterClassName(unsigned ClassID) const {
381  switch (ClassID) {
382  default:
383  return "Generic::Unknown Register Class";
384  case 0:
385  return "Generic::ScalarRC";
386  case 1:
387  return "Generic::VectorRC";
388  }
389  }
390 
392  return TypeSize::getFixed(32);
393  }
394 
395  unsigned getMinVectorRegisterBitWidth() const { return 128; }
396 
398 
399  bool shouldMaximizeVectorBandwidth() const { return false; }
400 
401  ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const {
402  return ElementCount::get(0, IsScalable);
403  }
404 
405  unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const { return 0; }
406 
408  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
409  AllowPromotionWithoutCommonHeader = false;
410  return false;
411  }
412 
413  unsigned getCacheLineSize() const { return 0; }
414 
417  switch (Level) {
421  return llvm::Optional<unsigned>();
422  }
423  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
424  }
425 
428  switch (Level) {
432  return llvm::Optional<unsigned>();
433  }
434 
435  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
436  }
437 
438  unsigned getPrefetchDistance() const { return 0; }
439  unsigned getMinPrefetchStride(unsigned NumMemAccesses,
440  unsigned NumStridedMemAccesses,
441  unsigned NumPrefetches, bool HasCall) const {
442  return 1;
443  }
444  unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; }
445  bool enableWritePrefetching() const { return false; }
446 
447  unsigned getMaxInterleaveFactor(unsigned VF) const { return 1; }
448 
450  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
451  TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info,
452  TTI::OperandValueProperties Opd1PropInfo,
454  const Instruction *CxtI = nullptr) const {
455  // FIXME: A number of transformation tests seem to require these values
456  // which seems a little odd for how arbitary there are.
457  switch (Opcode) {
458  default:
459  break;
460  case Instruction::FDiv:
461  case Instruction::FRem:
462  case Instruction::SDiv:
463  case Instruction::SRem:
464  case Instruction::UDiv:
465  case Instruction::URem:
466  // FIXME: Unlikely to be true for CodeSize.
467  return TTI::TCC_Expensive;
468  }
469  return 1;
470  }
471 
473  ArrayRef<int> Mask, int Index,
474  VectorType *SubTp) const {
475  return 1;
476  }
477 
478  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
481  const Instruction *I) const {
482  switch (Opcode) {
483  default:
484  break;
485  case Instruction::IntToPtr: {
486  unsigned SrcSize = Src->getScalarSizeInBits();
487  if (DL.isLegalInteger(SrcSize) &&
488  SrcSize <= DL.getPointerTypeSizeInBits(Dst))
489  return 0;
490  break;
491  }
492  case Instruction::PtrToInt: {
493  unsigned DstSize = Dst->getScalarSizeInBits();
494  if (DL.isLegalInteger(DstSize) &&
495  DstSize >= DL.getPointerTypeSizeInBits(Src))
496  return 0;
497  break;
498  }
499  case Instruction::BitCast:
500  if (Dst == Src || (Dst->isPointerTy() && Src->isPointerTy()))
501  // Identity and pointer-to-pointer casts are free.
502  return 0;
503  break;
504  case Instruction::Trunc: {
505  // trunc to a native type is free (assuming the target has compare and
506  // shift-right of the same width).
507  TypeSize DstSize = DL.getTypeSizeInBits(Dst);
508  if (!DstSize.isScalable() && DL.isLegalInteger(DstSize.getFixedSize()))
509  return 0;
510  break;
511  }
512  }
513  return 1;
514  }
515 
517  VectorType *VecTy,
518  unsigned Index) const {
519  return 1;
520  }
521 
523  const Instruction *I = nullptr) const {
524  // A phi would be free, unless we're costing the throughput because it
525  // will require a register.
526  if (Opcode == Instruction::PHI && CostKind != TTI::TCK_RecipThroughput)
527  return 0;
528  return 1;
529  }
530 
531  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
532  CmpInst::Predicate VecPred,
534  const Instruction *I) const {
535  return 1;
536  }
537 
538  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
539  unsigned Index) const {
540  return 1;
541  }
542 
543  InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
544  unsigned AddressSpace,
546  const Instruction *I) const {
547  return 1;
548  }
549 
551  Align Alignment, unsigned AddressSpace,
553  return 1;
554  }
555 
556  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
557  const Value *Ptr, bool VariableMask,
558  Align Alignment,
560  const Instruction *I = nullptr) const {
561  return 1;
562  }
563 
565  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
566  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
567  bool UseMaskForCond, bool UseMaskForGaps) const {
568  return 1;
569  }
570 
573  switch (ICA.getID()) {
574  default:
575  break;
576  case Intrinsic::annotation:
577  case Intrinsic::assume:
578  case Intrinsic::sideeffect:
579  case Intrinsic::pseudoprobe:
580  case Intrinsic::arithmetic_fence:
581  case Intrinsic::dbg_declare:
582  case Intrinsic::dbg_value:
583  case Intrinsic::dbg_label:
584  case Intrinsic::invariant_start:
585  case Intrinsic::invariant_end:
586  case Intrinsic::launder_invariant_group:
587  case Intrinsic::strip_invariant_group:
588  case Intrinsic::is_constant:
589  case Intrinsic::lifetime_start:
590  case Intrinsic::lifetime_end:
591  case Intrinsic::experimental_noalias_scope_decl:
592  case Intrinsic::objectsize:
593  case Intrinsic::ptr_annotation:
594  case Intrinsic::var_annotation:
595  case Intrinsic::experimental_gc_result:
596  case Intrinsic::experimental_gc_relocate:
597  case Intrinsic::coro_alloc:
598  case Intrinsic::coro_begin:
599  case Intrinsic::coro_free:
600  case Intrinsic::coro_end:
601  case Intrinsic::coro_frame:
602  case Intrinsic::coro_size:
603  case Intrinsic::coro_suspend:
604  case Intrinsic::coro_param:
605  case Intrinsic::coro_subfn_addr:
606  // These intrinsics don't actually represent code after lowering.
607  return 0;
608  }
609  return 1;
610  }
611 
613  ArrayRef<Type *> Tys,
615  return 1;
616  }
617 
618  unsigned getNumberOfParts(Type *Tp) const { return 0; }
619 
621  const SCEV *) const {
622  return 0;
623  }
624 
627  TTI::TargetCostKind) const {
628  return 1;
629  }
630 
632  TTI::TargetCostKind) const {
633  return 1;
634  }
635 
637  bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty,
639  return 1;
640  }
641 
643  return 0;
644  }
645 
647  return false;
648  }
649 
651  // Note for overrides: You must ensure for all element unordered-atomic
652  // memory intrinsics that all power-of-2 element sizes up to, and
653  // including, the return value of this method have a corresponding
654  // runtime lib call. These runtime lib call definitions can be found
655  // in RuntimeLibcalls.h
656  return 0;
657  }
658 
660  Type *ExpectedType) const {
661  return nullptr;
662  }
663 
665  unsigned SrcAddrSpace, unsigned DestAddrSpace,
666  unsigned SrcAlign, unsigned DestAlign) const {
667  return Type::getInt8Ty(Context);
668  }
669 
672  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
673  unsigned SrcAlign, unsigned DestAlign) const {
674  for (unsigned i = 0; i != RemainingBytes; ++i)
675  OpsOut.push_back(Type::getInt8Ty(Context));
676  }
677 
678  bool areInlineCompatible(const Function *Caller,
679  const Function *Callee) const {
680  return (Caller->getFnAttribute("target-cpu") ==
681  Callee->getFnAttribute("target-cpu")) &&
682  (Caller->getFnAttribute("target-features") ==
683  Callee->getFnAttribute("target-features"));
684  }
685 
687  const Function *Callee,
689  return (Caller->getFnAttribute("target-cpu") ==
690  Callee->getFnAttribute("target-cpu")) &&
691  (Caller->getFnAttribute("target-features") ==
692  Callee->getFnAttribute("target-features"));
693  }
694 
696  const DataLayout &DL) const {
697  return false;
698  }
699 
701  const DataLayout &DL) const {
702  return false;
703  }
704 
705  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { return 128; }
706 
707  bool isLegalToVectorizeLoad(LoadInst *LI) const { return true; }
708 
709  bool isLegalToVectorizeStore(StoreInst *SI) const { return true; }
710 
711  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
712  unsigned AddrSpace) const {
713  return true;
714  }
715 
716  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
717  unsigned AddrSpace) const {
718  return true;
719  }
720 
722  ElementCount VF) const {
723  return true;
724  }
725 
726  bool isElementTypeLegalForScalableVector(Type *Ty) const { return true; }
727 
728  unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
729  unsigned ChainSizeInBytes,
730  VectorType *VecTy) const {
731  return VF;
732  }
733 
734  unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
735  unsigned ChainSizeInBytes,
736  VectorType *VecTy) const {
737  return VF;
738  }
739 
740  bool preferInLoopReduction(unsigned Opcode, Type *Ty,
741  TTI::ReductionFlags Flags) const {
742  return false;
743  }
744 
745  bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
746  TTI::ReductionFlags Flags) const {
747  return false;
748  }
749 
750  bool shouldExpandReduction(const IntrinsicInst *II) const { return true; }
751 
752  unsigned getGISelRematGlobalCost() const { return 1; }
753 
754  bool supportsScalableVectors() const { return false; }
755 
756  bool hasActiveVectorLength() const { return false; }
757 
761  /* EVLParamStrategy */ TargetTransformInfo::VPLegalization::Discard,
762  /* OperatorStrategy */ TargetTransformInfo::VPLegalization::Convert);
763  }
764 
765 protected:
766  // Obtain the minimum required size to hold the value (without the sign)
767  // In case of a vector it returns the min required size for one element.
768  unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const {
769  if (isa<ConstantDataVector>(Val) || isa<ConstantVector>(Val)) {
770  const auto *VectorValue = cast<Constant>(Val);
771 
772  // In case of a vector need to pick the max between the min
773  // required size for each element
774  auto *VT = cast<FixedVectorType>(Val->getType());
775 
776  // Assume unsigned elements
777  isSigned = false;
778 
779  // The max required size is the size of the vector element type
780  unsigned MaxRequiredSize =
781  VT->getElementType()->getPrimitiveSizeInBits().getFixedSize();
782 
783  unsigned MinRequiredSize = 0;
784  for (unsigned i = 0, e = VT->getNumElements(); i < e; ++i) {
785  if (auto *IntElement =
786  dyn_cast<ConstantInt>(VectorValue->getAggregateElement(i))) {
787  bool signedElement = IntElement->getValue().isNegative();
788  // Get the element min required size.
789  unsigned ElementMinRequiredSize =
790  IntElement->getValue().getMinSignedBits() - 1;
791  // In case one element is signed then all the vector is signed.
792  isSigned |= signedElement;
793  // Save the max required bit size between all the elements.
794  MinRequiredSize = std::max(MinRequiredSize, ElementMinRequiredSize);
795  } else {
796  // not an int constant element
797  return MaxRequiredSize;
798  }
799  }
800  return MinRequiredSize;
801  }
802 
803  if (const auto *CI = dyn_cast<ConstantInt>(Val)) {
804  isSigned = CI->getValue().isNegative();
805  return CI->getValue().getMinSignedBits() - 1;
806  }
807 
808  if (const auto *Cast = dyn_cast<SExtInst>(Val)) {
809  isSigned = true;
810  return Cast->getSrcTy()->getScalarSizeInBits() - 1;
811  }
812 
813  if (const auto *Cast = dyn_cast<ZExtInst>(Val)) {
814  isSigned = false;
815  return Cast->getSrcTy()->getScalarSizeInBits();
816  }
817 
818  isSigned = false;
819  return Val->getType()->getScalarSizeInBits();
820  }
821 
822  bool isStridedAccess(const SCEV *Ptr) const {
823  return Ptr && isa<SCEVAddRecExpr>(Ptr);
824  }
825 
827  const SCEV *Ptr) const {
828  if (!isStridedAccess(Ptr))
829  return nullptr;
830  const SCEVAddRecExpr *AddRec = cast<SCEVAddRecExpr>(Ptr);
831  return dyn_cast<SCEVConstant>(AddRec->getStepRecurrence(*SE));
832  }
833 
835  int64_t MergeDistance) const {
836  const SCEVConstant *Step = getConstantStrideStep(SE, Ptr);
837  if (!Step)
838  return false;
839  APInt StrideVal = Step->getAPInt();
840  if (StrideVal.getBitWidth() > 64)
841  return false;
842  // FIXME: Need to take absolute value for negative stride case.
843  return StrideVal.getSExtValue() < MergeDistance;
844  }
845 };
846 
847 /// CRTP base class for use as a mix-in that aids implementing
848 /// a TargetTransformInfo-compatible class.
849 template <typename T>
851 private:
853 
854 protected:
856 
857 public:
858  using BaseT::getGEPCost;
859 
861  getGEPCost(Type *PointeeType, const Value *Ptr,
864  assert(PointeeType && Ptr && "can't get GEPCost of nullptr");
865  assert(cast<PointerType>(Ptr->getType()->getScalarType())
866  ->isOpaqueOrPointeeTypeMatches(PointeeType) &&
867  "explicit pointee type doesn't match operand's pointee type");
868  auto *BaseGV = dyn_cast<GlobalValue>(Ptr->stripPointerCasts());
869  bool HasBaseReg = (BaseGV == nullptr);
870 
871  auto PtrSizeBits = DL.getPointerTypeSizeInBits(Ptr->getType());
872  APInt BaseOffset(PtrSizeBits, 0);
873  int64_t Scale = 0;
874 
875  auto GTI = gep_type_begin(PointeeType, Operands);
876  Type *TargetType = nullptr;
877 
878  // Handle the case where the GEP instruction has a single operand,
879  // the basis, therefore TargetType is a nullptr.
880  if (Operands.empty())
881  return !BaseGV ? TTI::TCC_Free : TTI::TCC_Basic;
882 
883  for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) {
884  TargetType = GTI.getIndexedType();
885  // We assume that the cost of Scalar GEP with constant index and the
886  // cost of Vector GEP with splat constant index are the same.
887  const ConstantInt *ConstIdx = dyn_cast<ConstantInt>(*I);
888  if (!ConstIdx)
889  if (auto Splat = getSplatValue(*I))
890  ConstIdx = dyn_cast<ConstantInt>(Splat);
891  if (StructType *STy = GTI.getStructTypeOrNull()) {
892  // For structures the index is always splat or scalar constant
893  assert(ConstIdx && "Unexpected GEP index");
894  uint64_t Field = ConstIdx->getZExtValue();
895  BaseOffset += DL.getStructLayout(STy)->getElementOffset(Field);
896  } else {
897  // If this operand is a scalable type, bail out early.
898  // TODO: handle scalable vectors
899  if (isa<ScalableVectorType>(TargetType))
900  return TTI::TCC_Basic;
901  int64_t ElementSize =
902  DL.getTypeAllocSize(GTI.getIndexedType()).getFixedSize();
903  if (ConstIdx) {
904  BaseOffset +=
905  ConstIdx->getValue().sextOrTrunc(PtrSizeBits) * ElementSize;
906  } else {
907  // Needs scale register.
908  if (Scale != 0)
909  // No addressing mode takes two scale registers.
910  return TTI::TCC_Basic;
911  Scale = ElementSize;
912  }
913  }
914  }
915 
916  if (static_cast<T *>(this)->isLegalAddressingMode(
917  TargetType, const_cast<GlobalValue *>(BaseGV),
918  BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale,
919  Ptr->getType()->getPointerAddressSpace()))
920  return TTI::TCC_Free;
921  return TTI::TCC_Basic;
922  }
923 
926  auto *TargetTTI = static_cast<T *>(this);
927  // Handle non-intrinsic calls, invokes, and callbr.
928  // FIXME: Unlikely to be true for anything but CodeSize.
929  auto *CB = dyn_cast<CallBase>(U);
930  if (CB && !isa<IntrinsicInst>(U)) {
931  if (const Function *F = CB->getCalledFunction()) {
932  if (!TargetTTI->isLoweredToCall(F))
933  return TTI::TCC_Basic; // Give a basic cost if it will be lowered
934 
935  return TTI::TCC_Basic * (F->getFunctionType()->getNumParams() + 1);
936  }
937  // For indirect or other calls, scale cost by number of arguments.
938  return TTI::TCC_Basic * (CB->arg_size() + 1);
939  }
940 
941  Type *Ty = U->getType();
942  Type *OpTy =
943  U->getNumOperands() == 1 ? U->getOperand(0)->getType() : nullptr;
944  unsigned Opcode = Operator::getOpcode(U);
945  auto *I = dyn_cast<Instruction>(U);
946  switch (Opcode) {
947  default:
948  break;
949  case Instruction::Call: {
950  assert(isa<IntrinsicInst>(U) && "Unexpected non-intrinsic call");
951  auto *Intrinsic = cast<IntrinsicInst>(U);
952  IntrinsicCostAttributes CostAttrs(Intrinsic->getIntrinsicID(), *CB);
953  return TargetTTI->getIntrinsicInstrCost(CostAttrs, CostKind);
954  }
955  case Instruction::Br:
956  case Instruction::Ret:
957  case Instruction::PHI:
958  case Instruction::Switch:
959  return TargetTTI->getCFInstrCost(Opcode, CostKind, I);
960  case Instruction::ExtractValue:
961  case Instruction::Freeze:
962  return TTI::TCC_Free;
963  case Instruction::Alloca:
964  if (cast<AllocaInst>(U)->isStaticAlloca())
965  return TTI::TCC_Free;
966  break;
967  case Instruction::GetElementPtr: {
968  const GEPOperator *GEP = cast<GEPOperator>(U);
969  return TargetTTI->getGEPCost(GEP->getSourceElementType(),
970  GEP->getPointerOperand(),
971  Operands.drop_front());
972  }
973  case Instruction::Add:
974  case Instruction::FAdd:
975  case Instruction::Sub:
976  case Instruction::FSub:
977  case Instruction::Mul:
978  case Instruction::FMul:
979  case Instruction::UDiv:
980  case Instruction::SDiv:
981  case Instruction::FDiv:
982  case Instruction::URem:
983  case Instruction::SRem:
984  case Instruction::FRem:
985  case Instruction::Shl:
986  case Instruction::LShr:
987  case Instruction::AShr:
988  case Instruction::And:
989  case Instruction::Or:
990  case Instruction::Xor:
991  case Instruction::FNeg: {
994  TTI::OperandValueKind Op1VK =
995  TTI::getOperandInfo(U->getOperand(0), Op1VP);
996  TTI::OperandValueKind Op2VK = Opcode != Instruction::FNeg ?
999  return TargetTTI->getArithmeticInstrCost(Opcode, Ty, CostKind,
1000  Op1VK, Op2VK,
1001  Op1VP, Op2VP, Operands, I);
1002  }
1003  case Instruction::IntToPtr:
1004  case Instruction::PtrToInt:
1005  case Instruction::SIToFP:
1006  case Instruction::UIToFP:
1007  case Instruction::FPToUI:
1008  case Instruction::FPToSI:
1009  case Instruction::Trunc:
1010  case Instruction::FPTrunc:
1011  case Instruction::BitCast:
1012  case Instruction::FPExt:
1013  case Instruction::SExt:
1014  case Instruction::ZExt:
1015  case Instruction::AddrSpaceCast:
1016  return TargetTTI->getCastInstrCost(
1017  Opcode, Ty, OpTy, TTI::getCastContextHint(I), CostKind, I);
1018  case Instruction::Store: {
1019  auto *SI = cast<StoreInst>(U);
1020  Type *ValTy = U->getOperand(0)->getType();
1021  return TargetTTI->getMemoryOpCost(Opcode, ValTy, SI->getAlign(),
1022  SI->getPointerAddressSpace(),
1023  CostKind, I);
1024  }
1025  case Instruction::Load: {
1026  auto *LI = cast<LoadInst>(U);
1027  return TargetTTI->getMemoryOpCost(Opcode, U->getType(), LI->getAlign(),
1028  LI->getPointerAddressSpace(),
1029  CostKind, I);
1030  }
1031  case Instruction::Select: {
1032  const Value *Op0, *Op1;
1033  if (match(U, m_LogicalAnd(m_Value(Op0), m_Value(Op1))) ||
1034  match(U, m_LogicalOr(m_Value(Op0), m_Value(Op1)))) {
1035  // select x, y, false --> x & y
1036  // select x, true, y --> x | y
1039  TTI::OperandValueKind Op1VK = TTI::getOperandInfo(Op0, Op1VP);
1040  TTI::OperandValueKind Op2VK = TTI::getOperandInfo(Op1, Op2VP);
1041  assert(Op0->getType()->getScalarSizeInBits() == 1 &&
1042  Op1->getType()->getScalarSizeInBits() == 1);
1043 
1045  return TargetTTI->getArithmeticInstrCost(
1046  match(U, m_LogicalOr()) ? Instruction::Or : Instruction::And, Ty,
1047  CostKind, Op1VK, Op2VK, Op1VP, Op2VP, Operands, I);
1048  }
1049  Type *CondTy = U->getOperand(0)->getType();
1050  return TargetTTI->getCmpSelInstrCost(Opcode, U->getType(), CondTy,
1052  CostKind, I);
1053  }
1054  case Instruction::ICmp:
1055  case Instruction::FCmp: {
1056  Type *ValTy = U->getOperand(0)->getType();
1057  // TODO: Also handle ICmp/FCmp constant expressions.
1058  return TargetTTI->getCmpSelInstrCost(Opcode, ValTy, U->getType(),
1059  I ? cast<CmpInst>(I)->getPredicate()
1061  CostKind, I);
1062  }
1063  case Instruction::InsertElement: {
1064  auto *IE = dyn_cast<InsertElementInst>(U);
1065  if (!IE)
1066  return TTI::TCC_Basic; // FIXME
1067  auto *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1068  unsigned Idx = CI ? CI->getZExtValue() : -1;
1069  return TargetTTI->getVectorInstrCost(Opcode, Ty, Idx);
1070  }
1071  case Instruction::ShuffleVector: {
1072  auto *Shuffle = dyn_cast<ShuffleVectorInst>(U);
1073  if (!Shuffle)
1074  return TTI::TCC_Basic; // FIXME
1075 
1076  auto *VecTy = cast<VectorType>(U->getType());
1077  auto *VecSrcTy = cast<VectorType>(U->getOperand(0)->getType());
1078  int NumSubElts, SubIndex;
1079 
1080  if (Shuffle->changesLength()) {
1081  // Treat a 'subvector widening' as a free shuffle.
1082  if (Shuffle->increasesLength() && Shuffle->isIdentityWithPadding())
1083  return 0;
1084 
1085  if (Shuffle->isExtractSubvectorMask(SubIndex))
1086  return TargetTTI->getShuffleCost(TTI::SK_ExtractSubvector, VecSrcTy,
1087  Shuffle->getShuffleMask(), SubIndex,
1088  VecTy);
1089 
1090  if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1091  return TargetTTI->getShuffleCost(
1092  TTI::SK_InsertSubvector, VecTy, Shuffle->getShuffleMask(),
1093  SubIndex,
1094  FixedVectorType::get(VecTy->getScalarType(), NumSubElts));
1095 
1096  return CostKind == TTI::TCK_RecipThroughput ? -1 : 1;
1097  }
1098 
1099  if (Shuffle->isIdentity())
1100  return 0;
1101 
1102  if (Shuffle->isReverse())
1103  return TargetTTI->getShuffleCost(TTI::SK_Reverse, VecTy,
1104  Shuffle->getShuffleMask(), 0, nullptr);
1105 
1106  if (Shuffle->isSelect())
1107  return TargetTTI->getShuffleCost(TTI::SK_Select, VecTy,
1108  Shuffle->getShuffleMask(), 0, nullptr);
1109 
1110  if (Shuffle->isTranspose())
1111  return TargetTTI->getShuffleCost(TTI::SK_Transpose, VecTy,
1112  Shuffle->getShuffleMask(), 0, nullptr);
1113 
1114  if (Shuffle->isZeroEltSplat())
1115  return TargetTTI->getShuffleCost(TTI::SK_Broadcast, VecTy,
1116  Shuffle->getShuffleMask(), 0, nullptr);
1117 
1118  if (Shuffle->isSingleSource())
1119  return TargetTTI->getShuffleCost(TTI::SK_PermuteSingleSrc, VecTy,
1120  Shuffle->getShuffleMask(), 0, nullptr);
1121 
1122  if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1123  return TargetTTI->getShuffleCost(
1124  TTI::SK_InsertSubvector, VecTy, Shuffle->getShuffleMask(), SubIndex,
1125  FixedVectorType::get(VecTy->getScalarType(), NumSubElts));
1126 
1127  return TargetTTI->getShuffleCost(TTI::SK_PermuteTwoSrc, VecTy,
1128  Shuffle->getShuffleMask(), 0, nullptr);
1129  }
1130  case Instruction::ExtractElement: {
1131  unsigned Idx = -1;
1132  auto *EEI = dyn_cast<ExtractElementInst>(U);
1133  if (!EEI)
1134  return TTI::TCC_Basic; // FIXME
1135 
1136  auto *CI = dyn_cast<ConstantInt>(EEI->getOperand(1));
1137  if (CI)
1138  Idx = CI->getZExtValue();
1139 
1140  return TargetTTI->getVectorInstrCost(Opcode, U->getOperand(0)->getType(),
1141  Idx);
1142  }
1143  }
1144  // By default, just classify everything as 'basic'.
1145  return TTI::TCC_Basic;
1146  }
1147 
1149  SmallVector<const Value *, 4> Operands(I->operand_values());
1150  if (getUserCost(I, Operands, TTI::TCK_Latency) == TTI::TCC_Free)
1151  return 0;
1152 
1153  if (isa<LoadInst>(I))
1154  return 4;
1155 
1156  Type *DstTy = I->getType();
1157 
1158  // Usually an intrinsic is a simple instruction.
1159  // A real function call is much slower.
1160  if (auto *CI = dyn_cast<CallInst>(I)) {
1161  const Function *F = CI->getCalledFunction();
1162  if (!F || static_cast<T *>(this)->isLoweredToCall(F))
1163  return 40;
1164  // Some intrinsics return a value and a flag, we use the value type
1165  // to decide its latency.
1166  if (StructType *StructTy = dyn_cast<StructType>(DstTy))
1167  DstTy = StructTy->getElementType(0);
1168  // Fall through to simple instructions.
1169  }
1170 
1171  if (VectorType *VectorTy = dyn_cast<VectorType>(DstTy))
1172  DstTy = VectorTy->getElementType();
1173  if (DstTy->isFloatingPointTy())
1174  return 3;
1175 
1176  return 1;
1177  }
1178 };
1179 } // namespace llvm
1180 
1181 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::CacheLevel::L1D
@ L1D
llvm::orc::BaseT
RTTIExtends< ObjectLinkingLayer, ObjectLayer > BaseT
Definition: ObjectLinkingLayer.cpp:608
llvm::TargetTransformInfoImplBase::getCacheLineSize
unsigned getCacheLineSize() const
Definition: TargetTransformInfoImpl.h:413
llvm::TargetTransformInfo::SK_Select
@ SK_Select
Selects elements from the corresponding lane of either source operand.
Definition: TargetTransformInfo.h:855
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm::TargetTransformInfoImplBase::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Definition: TargetTransformInfoImpl.h:152
llvm::TargetTransformInfo::LSRCost::NumRegs
unsigned NumRegs
Definition: TargetTransformInfo.h:414
llvm::TargetTransformInfo::TCC_Expensive
@ TCC_Expensive
The cost of a 'div' instruction on x86.
Definition: TargetTransformInfo.h:264
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1331
llvm::TargetTransformInfoImplBase::useAA
bool useAA() const
Definition: TargetTransformInfoImpl.h:291
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::TargetTransformInfoImplBase::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, const LoopAccessInfo *LAI) const
Definition: TargetTransformInfoImpl.h:158
llvm::TargetTransformInfo::MemIndexedMode
MemIndexedMode
The type of load/store indexing.
Definition: TargetTransformInfo.h:1279
llvm::TargetTransformInfo::TCK_Latency
@ TCK_Latency
The latency of instruction.
Definition: TargetTransformInfo.h:213
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
llvm::TargetTransformInfoImplBase::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const
Definition: TargetTransformInfoImpl.h:109
llvm::TargetTransformInfoImplBase::isStridedAccess
bool isStridedAccess(const SCEV *Ptr) const
Definition: TargetTransformInfoImpl.h:822
IntrinsicInst.h
llvm::Type::isPointerTy
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:228
llvm::ElementCount
Definition: TypeSize.h:386
llvm::TargetTransformInfoImplBase::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: TargetTransformInfoImpl.h:397
llvm::TypeSize::getFixedSize
ScalarTy getFixedSize() const
Definition: TypeSize.h:426
llvm::Function
Definition: Function.h:61
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::TargetTransformInfoImplBase::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const
Definition: TargetTransformInfoImpl.h:198
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:588
llvm::TargetTransformInfoImplCRTPBase::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:924
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
GetElementPtrTypeIterator.h
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:319
llvm::ConstantInt::getValue
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:133
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::TargetTransformInfoImplBase::getExtendedAddReductionCost
InstructionCost getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfoImpl.h:636
llvm::TargetTransformInfoImplBase::isLSRCostLess
bool isLSRCostLess(TTI::LSRCost &C1, TTI::LSRCost &C2) const
Definition: TargetTransformInfoImpl.h:208
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1643
llvm::TargetTransformInfoImplBase::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType) const
Definition: TargetTransformInfoImpl.h:264
llvm::TargetTransformInfoImplBase::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *, const SCEV *) const
Definition: TargetTransformInfoImpl.h:620
llvm::TargetTransformInfoImplBase::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Definition: TargetTransformInfoImpl.h:100
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:360
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:733
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:443
llvm::TargetTransformInfoImplBase::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: TargetTransformInfoImpl.h:395
llvm::TargetTransformInfoImplBase::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent() const
Definition: TargetTransformInfoImpl.h:76
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:151
llvm::TargetTransformInfoImplBase::TTI
TargetTransformInfo TTI
Definition: TargetTransformInfoImpl.h:36
llvm::TargetTransformInfoImplBase::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:274
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1374
llvm::TargetTransformInfo::LSRCost::NumIVMuls
unsigned NumIVMuls
Definition: TargetTransformInfo.h:416
llvm::TargetTransformInfoImplBase::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: TargetTransformInfoImpl.h:380
llvm::TargetTransformInfoImplBase::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:705
llvm::TargetTransformInfoImplBase::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Definition: TargetTransformInfoImpl.h:339
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1581
llvm::TargetTransformInfo::VPLegalization::Convert
@ Convert
Definition: TargetTransformInfo.h:1381
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:531
llvm::TargetTransformInfoImplBase::isLegalToVectorizeStore
bool isLegalToVectorizeStore(StoreInst *SI) const
Definition: TargetTransformInfoImpl.h:709
llvm::TargetTransformInfoImplBase::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const
Definition: TargetTransformInfoImpl.h:289
llvm::Optional
Definition: APInt.h:33
T
#define T
Definition: Mips16ISelLowering.cpp:341
Operator.h
llvm::TargetTransformInfoImplBase::areFunctionArgsABICompatible
bool areFunctionArgsABICompatible(const Function *Caller, const Function *Callee, SmallPtrSetImpl< Argument * > &Args) const
Definition: TargetTransformInfoImpl.h:686
llvm::TargetTransformInfoImplBase::hasActiveVectorLength
bool hasActiveVectorLength() const
Definition: TargetTransformInfoImpl.h:756
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::TargetTransformInfoImplBase::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Definition: TargetTransformInfoImpl.h:94
llvm::TargetTransformInfoImplBase::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:356
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(const DataLayout &DL)
Definition: TargetTransformInfoImpl.h:40
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::gep_type_begin
gep_type_iterator gep_type_begin(const User *GEP)
Definition: GetElementPtrTypeIterator.h:139
llvm::TargetTransformInfoImplBase::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *, VectorType *, bool, TTI::TargetCostKind) const
Definition: TargetTransformInfoImpl.h:631
llvm::Type::isFloatingPointTy
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Definition: Type.h:162
llvm::TargetTransformInfoImplBase::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:258
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetTransformInfo::SK_PermuteSingleSrc
@ SK_PermuteSingleSrc
Shuffle elements of single source vector with any shuffle mask.
Definition: TargetTransformInfo.h:863
llvm::TargetTransformInfoImplBase::haveFastSqrt
bool haveFastSqrt(Type *Ty) const
Definition: TargetTransformInfoImpl.h:343
llvm::Type::getInt8Ty
static IntegerType * getInt8Ty(LLVMContext &C)
Definition: Type.cpp:201
llvm::TargetTransformInfoImplBase::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization() const
Definition: TargetTransformInfoImpl.h:327
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:299
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:941
llvm::TargetTransformInfoImplBase::getConstantStrideStep
const SCEVConstant * getConstantStrideStep(ScalarEvolution *SE, const SCEV *Ptr) const
Definition: TargetTransformInfoImpl.h:826
llvm::TargetTransformInfoImplCRTPBase::getGEPCost
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency)
Definition: TargetTransformInfoImpl.h:861
llvm::TargetTransformInfoImplBase::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Definition: TargetTransformInfoImpl.h:102
llvm::TargetTransformInfo::SK_Broadcast
@ SK_Broadcast
Broadcast element 0 to all other elements.
Definition: TargetTransformInfo.h:853
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::TargetTransformInfo::LSRCost::AddRecCost
unsigned AddRecCost
Definition: TargetTransformInfo.h:415
llvm::TargetTransformInfoImplBase::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Definition: TargetTransformInfoImpl.h:287
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:48
llvm::TargetTransformInfoImplBase::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: TargetTransformInfoImpl.h:678
llvm::TargetTransformInfoImplBase::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: TargetTransformInfoImpl.h:401
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::TargetTransformInfo::LSRCost::SetupCost
unsigned SetupCost
Definition: TargetTransformInfo.h:419
llvm::TargetTransformInfoImplBase::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR() const
Definition: TargetTransformInfoImpl.h:215
llvm::TargetTransformInfoImplBase::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: TargetTransformInfoImpl.h:721
llvm::TargetTransformInfoImplBase::getPredictableBranchThreshold
BranchProbability getPredictableBranchThreshold() const
Definition: TargetTransformInfoImpl.h:88
llvm::TargetTransformInfoImplBase::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, bool *Fast) const
Definition: TargetTransformInfoImpl.h:333
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::TargetTransformInfoImplBase::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Definition: TargetTransformInfoImpl.h:266
llvm::TargetTransformInfo::SK_PermuteTwoSrc
@ SK_PermuteTwoSrc
Merge elements from two source vectors into one with any shuffle mask.
Definition: TargetTransformInfo.h:861
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::LinearPolySize< ElementCount >::get
static ElementCount get(ScalarTy MinVal, bool Scalable)
Definition: TypeSize.h:290
llvm::TargetTransformInfo::getCastContextHint
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
Definition: TargetTransformInfo.cpp:732
llvm::TargetTransformInfoImplBase::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF) const
Definition: TargetTransformInfoImpl.h:447
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(TargetTransformInfoImplBase &&Arg)
Definition: TargetTransformInfoImpl.h:46
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::TargetTransformInfoImplBase
Base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:34
llvm::TargetTransformInfoImplBase::getCacheAssociativity
llvm::Optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const
Definition: TargetTransformInfoImpl.h:427
llvm::PatternMatch::match
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
llvm::TargetTransformInfoImplBase::getPrefetchDistance
unsigned getPrefetchDistance() const
Definition: TargetTransformInfoImpl.h:438
llvm::TargetTransformInfoImplBase::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: TargetTransformInfoImpl.h:374
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:879
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:852
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1055
llvm::TargetTransformInfoImplBase::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:232
llvm::User
Definition: User.h:44
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetTransformInfoImplBase::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Definition: TargetTransformInfoImpl.h:299
llvm::TargetTransformInfoImplBase::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const
Definition: TargetTransformInfoImpl.h:538
llvm::TargetTransformInfoImplBase::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfoImpl.h:664
llvm::TargetTransformInfoImplBase::hasBranchDivergence
bool hasBranchDivergence() const
Definition: TargetTransformInfoImpl.h:92
llvm::TargetTransformInfoImplBase::isIndexedStoreLegal
bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
Definition: TargetTransformInfoImpl.h:700
llvm::TargetTransformInfoImplBase::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Definition: TargetTransformInfoImpl.h:297
llvm::Instruction
Definition: Instruction.h:45
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:153
llvm::TargetTransformInfoImplBase::getNumberOfParts
unsigned getNumberOfParts(Type *Tp) const
Definition: TargetTransformInfoImpl.h:618
llvm::TargetTransformInfoImplBase::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
Definition: TargetTransformInfoImpl.h:361
llvm::Operator::getOpcode
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
Definition: Operator.h:41
llvm::TargetTransformInfoImplBase::isTypeLegal
bool isTypeLegal(Type *Ty) const
Definition: TargetTransformInfoImpl.h:293
llvm::TargetTransformInfoImplBase::isLegalAddressingMode
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:200
llvm::TargetTransformInfoImplBase::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:522
llvm::TargetTransformInfoImplBase::getRegUsageForType
InstructionCost getRegUsageForType(Type *Ty) const
Definition: TargetTransformInfoImpl.h:295
llvm::TargetTransformInfoImplBase::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
Definition: TargetTransformInfoImpl.h:659
llvm::TargetTransformInfoImplCRTPBase
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:850
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetTransformInfoImplBase::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:268
PatternMatch.h
llvm::TargetTransformInfoImplBase::getCostOfKeepingLiveOverCall
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
Definition: TargetTransformInfoImpl.h:642
llvm::TargetTransformInfoImplBase::enableWritePrefetching
bool enableWritePrefetching() const
Definition: TargetTransformInfoImpl.h:445
llvm::FixedVectorType::get
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
Definition: Type.cpp:650
llvm::TargetTransformInfoImplBase::enableMemCmpExpansion
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: TargetTransformInfoImpl.h:322
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:153
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::TargetTransformInfoImplBase::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Definition: TargetTransformInfoImpl.h:96
llvm::TargetTransformInfoImplBase::getVPLegalizationStrategy
TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: TargetTransformInfoImpl.h:759
llvm::TargetTransformInfoImplBase::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:550
llvm::None
const NoneType None
Definition: None.h:23
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:284
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
Type.h
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:118
llvm::TargetTransformInfoImplBase::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:556
llvm::TargetTransformInfo::PSK_Software
@ PSK_Software
Definition: TargetTransformInfo.h:588
llvm::TargetTransformInfoImplBase::getCacheSize
llvm::Optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const
Definition: TargetTransformInfoImpl.h:416
llvm::TargetTransformInfoImplBase::emitGetActiveLaneMask
bool emitGetActiveLaneMask() const
Definition: TargetTransformInfoImpl.h:165
llvm::TargetTransformInfoImplBase::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I) const
Definition: TargetTransformInfoImpl.h:217
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::ARM_PROC::IE
@ IE
Definition: ARMBaseInfo.h:27
llvm::TargetTransformInfoImplBase::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: TargetTransformInfoImpl.h:181
llvm::TargetTransformInfoImplBase::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: TargetTransformInfoImpl.h:745
llvm::TargetTransformInfoImplBase::supportsScalableVectors
bool supportsScalableVectors() const
Definition: TargetTransformInfoImpl.h:754
llvm::TargetTransformInfoImplBase::enableMaskedInterleavedAccessVectorization
bool enableMaskedInterleavedAccessVectorization() const
Definition: TargetTransformInfoImpl.h:329
llvm::TargetTransformInfo::SK_Reverse
@ SK_Reverse
Reverse the order of the vector.
Definition: TargetTransformInfo.h:854
llvm::TargetTransformInfoImplCRTPBase::TargetTransformInfoImplCRTPBase
TargetTransformInfoImplCRTPBase(const DataLayout &DL)
Definition: TargetTransformInfoImpl.h:855
llvm::TargetTransformInfoImplBase::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:612
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:388
VectorUtils.h
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:78
llvm::TargetTransformInfoImplBase::canMacroFuseCmp
bool canMacroFuseCmp() const
Definition: TargetTransformInfoImpl.h:219
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:304
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::TargetTransformInfo::SK_InsertSubvector
@ SK_InsertSubvector
InsertSubvector. Index indicates start offset.
Definition: TargetTransformInfo.h:859
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetTransformInfoImplBase::getEstimatedNumberOfCaseClusters
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Definition: TargetTransformInfoImpl.h:63
llvm::TargetTransformInfoImplBase::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:240
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::TargetTransformInfoImplBase::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth() const
Definition: TargetTransformInfoImpl.h:399
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:410
llvm::TargetTransformInfoImplBase::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:716
llvm::PatternMatch::m_LogicalOr
LogicalOp_match< LHS, RHS, Instruction::Or > m_LogicalOr(const LHS &L, const RHS &R)
Matches L || R either in the form of L | R or L ? true : R.
Definition: PatternMatch.h:2510
llvm::TargetTransformInfoImplBase::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned, VectorType *, Optional< FastMathFlags > FMF, TTI::TargetCostKind) const
Definition: TargetTransformInfoImpl.h:625
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::TargetTransformInfoImplBase::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Definition: TargetTransformInfoImpl.h:175
llvm::TargetTransformInfoImplBase::getPreferredAddressingMode
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Definition: TargetTransformInfoImpl.h:228
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:424
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfoImplBase::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:478
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:879
llvm::LoopAccessInfo
Drive the analysis of memory accesses in the loop.
Definition: LoopAccessAnalysis.h:525
llvm::SCEVConstant
This class represents a constant integer value.
Definition: ScalarEvolutionExpressions.h:47
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetTransformInfo::VPLegalization::Discard
@ Discard
Definition: TargetTransformInfo.h:1379
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::TargetTransformInfoImplBase::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
Definition: TargetTransformInfoImpl.h:407
llvm::TargetTransformInfoImplBase::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Definition: TargetTransformInfoImpl.h:116
llvm::CmpInst::BAD_ICMP_PREDICATE
@ BAD_ICMP_PREDICATE
Definition: InstrTypes.h:753
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::TargetTransformInfo::LSRCost::ScaleCost
unsigned ScaleCost
Definition: TargetTransformInfo.h:420
llvm::TargetTransformInfoImplBase::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
Definition: TargetTransformInfoImpl.h:311
llvm::TargetTransformInfoImplBase::getInterleavedMemoryOpCost
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) const
Definition: TargetTransformInfoImpl.h:564
llvm::TargetTransformInfoImplBase::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: TargetTransformInfoImpl.h:646
llvm::TargetTransformInfoImplBase::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Definition: TargetTransformInfoImpl.h:318
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:871
llvm::GEPOperator
Definition: Operator.h:458
llvm::PatternMatch::m_Value
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:76
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::TargetTransformInfoImplBase::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned, unsigned) const
Definition: TargetTransformInfoImpl.h:107
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:754
llvm::TargetTransformInfoImplBase::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:247
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:262
llvm::TargetTransformInfoImplBase::isElementTypeLegalForScalableVector
bool isElementTypeLegalForScalableVector(Type *Ty) const
Definition: TargetTransformInfoImpl.h:726
llvm::TargetTransformInfoImplBase::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: TargetTransformInfoImpl.h:750
llvm::TargetTransformInfoImplBase::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier() const
Definition: TargetTransformInfoImpl.h:73
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LoopInfo
Definition: LoopInfo.h:1083
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
DataLayout.h
llvm::StructType
Class to represent struct types.
Definition: DerivedTypes.h:212
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:41
llvm::TargetTransformInfo::TCK_SizeAndLatency
@ TCK_SizeAndLatency
The weighted sum of size and latency.
Definition: TargetTransformInfo.h:215
llvm::TargetTransformInfoImplBase::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfoImpl.h:752
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::TargetTransformInfoImplCRTPBase::getInstructionLatency
InstructionCost getInstructionLatency(const Instruction *I)
Definition: TargetTransformInfoImpl.h:1148
llvm::TargetTransformInfoImplBase::LSRWithInstrQueries
bool LSRWithInstrQueries() const
Definition: TargetTransformInfoImpl.h:285
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::TargetTransformInfoImplBase::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
Definition: TargetTransformInfoImpl.h:305
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetTransformInfoImplBase::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
Definition: TargetTransformInfoImpl.h:316
llvm::TargetTransformInfoImplBase::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Definition: TargetTransformInfoImpl.h:345
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::TargetTransformInfoImplBase::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:531
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:635
llvm::TargetTransformInfoImplBase::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:236
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:421
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:872
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:175
llvm::TargetTransformInfo::SK_Transpose
@ SK_Transpose
Transpose two vectors.
Definition: TargetTransformInfo.h:858
llvm::TargetTransformInfoImplBase::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfoImpl.h:670
llvm::Value::stripPointerCasts
const Value * stripPointerCasts() const
Strip off pointer casts, all-zero GEPs and address space casts.
Definition: Value.cpp:675
llvm::TargetTransformInfo::CacheLevel::L2D
@ L2D
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:142
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:206
llvm::TargetTransformInfoImplBase::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr) const
Definition: TargetTransformInfoImpl.h:449
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:162
llvm::TargetTransformInfoImplBase::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: TargetTransformInfoImpl.h:740
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::KnownBits
Definition: KnownBits.h:23
llvm::TargetTransformInfoImplBase::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef< int > Mask, int Index, VectorType *SubTp) const
Definition: TargetTransformInfoImpl.h:472
llvm::TargetTransformInfo::LSRCost::NumBaseAdds
unsigned NumBaseAdds
Definition: TargetTransformInfo.h:417
llvm::TargetTransformInfoImplBase::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: TargetTransformInfoImpl.h:650
llvm::TargetTransformInfoImplBase::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const
Definition: TargetTransformInfoImpl.h:444
llvm::TargetTransformInfoImplBase::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:368
llvm::TargetTransformInfoImplBase::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I) const
Definition: TargetTransformInfoImpl.h:78
llvm::TargetTransformInfoImplBase::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Definition: TargetTransformInfoImpl.h:111
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:390
VPLegalization
TargetTransformInfo::VPLegalization VPLegalization
Definition: ExpandVectorPredication.cpp:36
llvm::APInt::sextOrTrunc
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition: APInt.cpp:960
llvm::TargetTransformInfoImplBase::minRequiredElementSize
unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const
Definition: TargetTransformInfoImpl.h:768
llvm::TypeSize
Definition: TypeSize.h:417
llvm::SCEVAddRecExpr
This node represents a polynomial recurrence on the trip count of the specified loop.
Definition: ScalarEvolutionExpressions.h:352
Function.h
llvm::TargetTransformInfoImplBase::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfoImpl.h:728
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::TargetTransformInfoImplBase::isIndexedLoadLegal
bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
Definition: TargetTransformInfoImpl.h:695
llvm::TargetTransformInfoImplBase::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Definition: TargetTransformInfoImpl.h:439
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:219
llvm::User::operand_values
iterator_range< value_op_iterator > operand_values()
Definition: User.h:266
llvm::TargetTransformInfo::LSRCost::ImmCost
unsigned ImmCost
Definition: TargetTransformInfo.h:418
llvm::TargetTransformInfoImplBase::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const
Definition: TargetTransformInfoImpl.h:196
llvm::TargetTransformInfoImplBase::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:543
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:183
llvm::TargetTransformInfoImplBase::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: TargetTransformInfoImpl.h:376
llvm::TargetTransformInfoImplBase::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: TargetTransformInfoImpl.h:391
llvm::TargetTransformInfoImplBase::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Definition: TargetTransformInfoImpl.h:221
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfoImplBase::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: TargetTransformInfoImpl.h:169
llvm::SCEVConstant::getAPInt
const APInt & getAPInt() const
Definition: ScalarEvolutionExpressions.h:57
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:95
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::TargetTransformInfoImplBase::getUnrollingPreferences
void getUnrollingPreferences(Loop *, ScalarEvolution &, TTI::UnrollingPreferences &, OptimizationRemarkEmitter *) const
Definition: TargetTransformInfoImpl.h:189
llvm::TargetTransformInfoImplBase::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
Definition: TargetTransformInfoImpl.h:516
llvm::TargetTransformInfoImplBase::isConstantStridedAccessLessThan
bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance) const
Definition: TargetTransformInfoImpl.h:834
llvm::TargetTransformInfoImplBase::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe() const
Definition: TargetTransformInfoImpl.h:331
ScalarEvolutionExpressions.h
llvm::TargetTransformInfoImplBase::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: TargetTransformInfoImpl.h:98
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:67
llvm::TargetTransformInfoImplBase::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType) const
Definition: TargetTransformInfoImpl.h:262
llvm::User::getNumOperands
unsigned getNumOperands() const
Definition: User.h:191
llvm::IntrinsicCostAttributes::getID
Intrinsic::ID getID() const
Definition: TargetTransformInfo.h:148
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:900
llvm::TargetTransformInfoImplBase::isLegalToVectorizeLoad
bool isLegalToVectorizeLoad(LoadInst *LI) const
Definition: TargetTransformInfoImpl.h:707
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
TargetTransformInfo.h
llvm::PatternMatch
Definition: PatternMatch.h:47
llvm::SmallVectorImpl< int >
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:70
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1161
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
llvm::TargetTransformInfoImplBase::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfoImpl.h:734
llvm::TargetTransformInfoImplBase::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:711
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:172
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(const TargetTransformInfoImplBase &Arg)
Definition: TargetTransformInfoImpl.h:44
llvm::TargetTransformInfoImplBase::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:254
llvm::TargetTransformInfo::getOperandInfo
static OperandValueKind getOperandInfo(const Value *V, OperandValueProperties &OpProps)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
Definition: TargetTransformInfo.cpp:660
llvm::TargetTransformInfo::TCC_Basic
@ TCC_Basic
The cost of a typical 'add' instruction.
Definition: TargetTransformInfo.h:263
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3206
llvm::OptimizedStructLayoutField
A field in a structure.
Definition: OptimizedStructLayout.h:45
llvm::TargetTransformInfoImplBase::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Definition: TargetTransformInfoImpl.h:301
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::TargetTransformInfoImplBase::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: TargetTransformInfoImpl.h:74
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3062
llvm::TargetTransformInfoImplBase::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:571
llvm::TargetTransformInfoImplBase::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Definition: TargetTransformInfoImpl.h:272
llvm::TargetTransformInfoImplBase::useColdCCForColdCall
bool useColdCCForColdCall(Function &F) const
Definition: TargetTransformInfoImpl.h:303
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:212
llvm::TargetTransformInfoImplBase::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const
Definition: TargetTransformInfoImpl.h:351
llvm::TargetTransformInfo::AMK_None
@ AMK_None
Definition: TargetTransformInfo.h:638
llvm::TargetTransformInfo::SK_ExtractSubvector
@ SK_ExtractSubvector
ExtractSubvector Index indicates start offset.
Definition: TargetTransformInfo.h:860
llvm::PatternMatch::m_LogicalAnd
LogicalOp_match< LHS, RHS, Instruction::And > m_LogicalAnd(const LHS &L, const RHS &R)
Matches L && R either in the form of L & R or L ? R : false.
Definition: PatternMatch.h:2499
llvm::TargetTransformInfoImplBase::getPeelingPreferences
void getPeelingPreferences(Loop *, ScalarEvolution &, TTI::PeelingPreferences &) const
Definition: TargetTransformInfoImpl.h:193
llvm::SCEVAddRecExpr::getStepRecurrence
const SCEV * getStepRecurrence(ScalarEvolution &SE) const
Constructs and returns the recurrence indicating how much this expression steps by.
Definition: ScalarEvolutionExpressions.h:370
llvm::TargetTransformInfoImplBase::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: TargetTransformInfoImpl.h:405
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::TargetTransformInfoImplBase::getFPOpCost
InstructionCost getFPOpCost(Type *Ty) const
Definition: TargetTransformInfoImpl.h:347