LLVM  16.0.0git
TargetTransformInfoImpl.h
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1 //===- TargetTransformInfoImpl.h --------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file provides helpers for the implementation of
10 /// a TargetTransformInfo-conforming class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
15 #define LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
16 
20 #include "llvm/IR/DataLayout.h"
22 #include "llvm/IR/IntrinsicInst.h"
23 #include "llvm/IR/Operator.h"
24 #include "llvm/IR/PatternMatch.h"
25 #include <utility>
26 
27 namespace llvm {
28 
29 class Function;
30 
31 /// Base class for use as a mix-in that aids implementing
32 /// a TargetTransformInfo-compatible class.
34 protected:
36 
37  const DataLayout &DL;
38 
40 
41 public:
42  // Provide value semantics. MSVC requires that we spell all of these out.
45 
46  const DataLayout &getDataLayout() const { return DL; }
47 
48  InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr,
51  // In the basic model, we just assume that all-constant GEPs will be folded
52  // into their uses via addressing modes.
53  for (const Value *Operand : Operands)
54  if (!isa<Constant>(Operand))
55  return TTI::TCC_Basic;
56 
57  return TTI::TCC_Free;
58  }
59 
61  unsigned &JTSize,
62  ProfileSummaryInfo *PSI,
63  BlockFrequencyInfo *BFI) const {
64  (void)PSI;
65  (void)BFI;
66  JTSize = 0;
67  return SI.getNumCases();
68  }
69 
70  unsigned getInliningThresholdMultiplier() const { return 1; }
71  unsigned adjustInliningThreshold(const CallBase *CB) const { return 0; }
72 
73  int getInlinerVectorBonusPercent() const { return 150; }
74 
76  return TTI::TCC_Expensive;
77  }
78 
79  // Although this default value is arbitrary, it is not random. It is assumed
80  // that a condition that evaluates the same way by a higher percentage than
81  // this is best represented as control flow. Therefore, the default value N
82  // should be set such that the win from N% correct executions is greater than
83  // the loss from (100 - N)% mispredicted executions for the majority of
84  // intended targets.
86  return BranchProbability(99, 100);
87  }
88 
89  bool hasBranchDivergence() const { return false; }
90 
91  bool useGPUDivergenceAnalysis() const { return false; }
92 
93  bool isSourceOfDivergence(const Value *V) const { return false; }
94 
95  bool isAlwaysUniform(const Value *V) const { return false; }
96 
97  unsigned getFlatAddressSpace() const { return -1; }
98 
100  Intrinsic::ID IID) const {
101  return false;
102  }
103 
104  bool isNoopAddrSpaceCast(unsigned, unsigned) const { return false; }
106  return AS == 0;
107  };
108 
109  unsigned getAssumedAddrSpace(const Value *V) const { return -1; }
110 
111  std::pair<const Value *, unsigned>
112  getPredicatedAddrSpace(const Value *V) const {
113  return std::make_pair(nullptr, -1);
114  }
115 
117  Value *NewV) const {
118  return nullptr;
119  }
120 
121  bool isLoweredToCall(const Function *F) const {
122  assert(F && "A concrete function must be provided to this routine.");
123 
124  // FIXME: These should almost certainly not be handled here, and instead
125  // handled with the help of TLI or the target itself. This was largely
126  // ported from existing analysis heuristics here so that such refactorings
127  // can take place in the future.
128 
129  if (F->isIntrinsic())
130  return false;
131 
132  if (F->hasLocalLinkage() || !F->hasName())
133  return true;
134 
135  StringRef Name = F->getName();
136 
137  // These will all likely lower to a single selection DAG node.
138  if (Name == "copysign" || Name == "copysignf" || Name == "copysignl" ||
139  Name == "fabs" || Name == "fabsf" || Name == "fabsl" || Name == "sin" ||
140  Name == "fmin" || Name == "fminf" || Name == "fminl" ||
141  Name == "fmax" || Name == "fmaxf" || Name == "fmaxl" ||
142  Name == "sinf" || Name == "sinl" || Name == "cos" || Name == "cosf" ||
143  Name == "cosl" || Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl")
144  return false;
145 
146  // These are all likely to be optimized into something smaller.
147  if (Name == "pow" || Name == "powf" || Name == "powl" || Name == "exp2" ||
148  Name == "exp2l" || Name == "exp2f" || Name == "floor" ||
149  Name == "floorf" || Name == "ceil" || Name == "round" ||
150  Name == "ffs" || Name == "ffsl" || Name == "abs" || Name == "labs" ||
151  Name == "llabs")
152  return false;
153 
154  return true;
155  }
156 
158  AssumptionCache &AC, TargetLibraryInfo *LibInfo,
159  HardwareLoopInfo &HWLoopInfo) const {
160  return false;
161  }
162 
165  DominatorTree *DT,
167  InterleavedAccessInfo *IAI) const {
168  return false;
169  }
170 
172  return PredicationStyle::None;
173  }
174 
176  IntrinsicInst &II) const {
177  return None;
178  }
179 
182  APInt DemandedMask, KnownBits &Known,
183  bool &KnownBitsComputed) const {
184  return None;
185  }
186 
188  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
189  APInt &UndefElts2, APInt &UndefElts3,
190  std::function<void(Instruction *, unsigned, APInt, APInt &)>
191  SimplifyAndSetOp) const {
192  return None;
193  }
194 
197  OptimizationRemarkEmitter *) const {}
198 
200  TTI::PeelingPreferences &) const {}
201 
202  bool isLegalAddImmediate(int64_t Imm) const { return false; }
203 
204  bool isLegalICmpImmediate(int64_t Imm) const { return false; }
205 
206  bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
207  bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
208  Instruction *I = nullptr) const {
209  // Guess that only reg and reg+reg addressing is allowed. This heuristic is
210  // taken from the implementation of LSR.
211  return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1);
212  }
213 
214  bool isLSRCostLess(const TTI::LSRCost &C1, const TTI::LSRCost &C2) const {
215  return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds,
216  C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
217  std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds,
218  C2.ScaleCost, C2.ImmCost, C2.SetupCost);
219  }
220 
221  bool isNumRegsMajorCostOfLSR() const { return true; }
222 
223  bool isProfitableLSRChainElement(Instruction *I) const { return false; }
224 
225  bool canMacroFuseCmp() const { return false; }
226 
229  TargetLibraryInfo *LibInfo) const {
230  return false;
231  }
232 
235  return TTI::AMK_None;
236  }
237 
238  bool isLegalMaskedStore(Type *DataType, Align Alignment) const {
239  return false;
240  }
241 
242  bool isLegalMaskedLoad(Type *DataType, Align Alignment) const {
243  return false;
244  }
245 
246  bool isLegalNTStore(Type *DataType, Align Alignment) const {
247  // By default, assume nontemporal memory stores are available for stores
248  // that are aligned and have a size that is a power of 2.
249  unsigned DataSize = DL.getTypeStoreSize(DataType);
250  return Alignment >= DataSize && isPowerOf2_32(DataSize);
251  }
252 
253  bool isLegalNTLoad(Type *DataType, Align Alignment) const {
254  // By default, assume nontemporal memory loads are available for loads that
255  // are aligned and have a size that is a power of 2.
256  unsigned DataSize = DL.getTypeStoreSize(DataType);
257  return Alignment >= DataSize && isPowerOf2_32(DataSize);
258  }
259 
260  bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const {
261  return false;
262  }
263 
264  bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
265  return false;
266  }
267 
268  bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
269  return false;
270  }
271 
272  bool forceScalarizeMaskedGather(VectorType *DataType, Align Alignment) const {
273  return false;
274  }
275 
277  Align Alignment) const {
278  return false;
279  }
280 
281  bool isLegalMaskedCompressStore(Type *DataType) const { return false; }
282 
283  bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
284  const SmallBitVector &OpcodeMask) const {
285  return false;
286  }
287 
288  bool isLegalMaskedExpandLoad(Type *DataType) const { return false; }
289 
290  bool enableOrderedReductions() const { return false; }
291 
292  bool hasDivRemOp(Type *DataType, bool IsSigned) const { return false; }
293 
294  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const {
295  return false;
296  }
297 
298  bool prefersVectorizedAddressing() const { return true; }
299 
301  int64_t BaseOffset, bool HasBaseReg,
302  int64_t Scale,
303  unsigned AddrSpace) const {
304  // Guess that all legal addressing mode are free.
305  if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
306  AddrSpace))
307  return 0;
308  return -1;
309  }
310 
311  bool LSRWithInstrQueries() const { return false; }
312 
313  bool isTruncateFree(Type *Ty1, Type *Ty2) const { return false; }
314 
315  bool isProfitableToHoist(Instruction *I) const { return true; }
316 
317  bool useAA() const { return false; }
318 
319  bool isTypeLegal(Type *Ty) const { return false; }
320 
321  unsigned getRegUsageForType(Type *Ty) const { return 1; }
322 
323  bool shouldBuildLookupTables() const { return true; }
324 
325  bool shouldBuildLookupTablesForConstant(Constant *C) const { return true; }
326 
327  bool shouldBuildRelLookupTables() const { return false; }
328 
329  bool useColdCCForColdCall(Function &F) const { return false; }
330 
332  const APInt &DemandedElts,
333  bool Insert, bool Extract) const {
334  return 0;
335  }
336 
338  ArrayRef<Type *> Tys) const {
339  return 0;
340  }
341 
342  bool supportsEfficientVectorElementLoadStore() const { return false; }
343 
344  bool supportsTailCalls() const { return true; }
345 
346  bool supportsTailCallFor(const CallBase *CB) const {
347  return supportsTailCalls();
348  }
349 
350  bool enableAggressiveInterleaving(bool LoopHasReductions) const {
351  return false;
352  }
353 
355  bool IsZeroCmp) const {
356  return {};
357  }
358 
359  bool enableInterleavedAccessVectorization() const { return false; }
360 
361  bool enableMaskedInterleavedAccessVectorization() const { return false; }
362 
363  bool isFPVectorizationPotentiallyUnsafe() const { return false; }
364 
366  unsigned AddressSpace, Align Alignment,
367  bool *Fast) const {
368  return false;
369  }
370 
371  TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const {
372  return TTI::PSK_Software;
373  }
374 
375  bool haveFastSqrt(Type *Ty) const { return false; }
376 
377  bool isExpensiveToSpeculativelyExecute(const Instruction *I) { return true; }
378 
379  bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { return true; }
380 
383  }
384 
385  InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
386  const APInt &Imm, Type *Ty) const {
387  return 0;
388  }
389 
392  return TTI::TCC_Basic;
393  }
394 
395  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
396  const APInt &Imm, Type *Ty,
398  Instruction *Inst = nullptr) const {
399  return TTI::TCC_Free;
400  }
401 
403  const APInt &Imm, Type *Ty,
405  return TTI::TCC_Free;
406  }
407 
408  unsigned getNumberOfRegisters(unsigned ClassID) const { return 8; }
409 
410  unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
411  return Vector ? 1 : 0;
412  };
413 
414  const char *getRegisterClassName(unsigned ClassID) const {
415  switch (ClassID) {
416  default:
417  return "Generic::Unknown Register Class";
418  case 0:
419  return "Generic::ScalarRC";
420  case 1:
421  return "Generic::VectorRC";
422  }
423  }
424 
426  return TypeSize::getFixed(32);
427  }
428 
429  unsigned getMinVectorRegisterBitWidth() const { return 128; }
430 
433 
434  bool
436  return false;
437  }
438 
439  ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const {
440  return ElementCount::get(0, IsScalable);
441  }
442 
443  unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const { return 0; }
444  unsigned getStoreMinimumVF(unsigned VF, Type *, Type *) const { return VF; }
445 
447  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
448  AllowPromotionWithoutCommonHeader = false;
449  return false;
450  }
451 
452  unsigned getCacheLineSize() const { return 0; }
453 
456  switch (Level) {
458  [[fallthrough]];
460  return llvm::Optional<unsigned>();
461  }
462  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
463  }
464 
467  switch (Level) {
469  [[fallthrough]];
471  return llvm::Optional<unsigned>();
472  }
473 
474  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
475  }
476 
477  unsigned getPrefetchDistance() const { return 0; }
478  unsigned getMinPrefetchStride(unsigned NumMemAccesses,
479  unsigned NumStridedMemAccesses,
480  unsigned NumPrefetches, bool HasCall) const {
481  return 1;
482  }
483  unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; }
484  bool enableWritePrefetching() const { return false; }
485  bool shouldPrefetchAddressSpace(unsigned AS) const { return !AS; }
486 
487  unsigned getMaxInterleaveFactor(unsigned VF) const { return 1; }
488 
490  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
491  TTI::OperandValueInfo Opd1Info, TTI::OperandValueInfo Opd2Info,
493  const Instruction *CxtI = nullptr) const {
494  // FIXME: A number of transformation tests seem to require these values
495  // which seems a little odd for how arbitary there are.
496  switch (Opcode) {
497  default:
498  break;
499  case Instruction::FDiv:
500  case Instruction::FRem:
501  case Instruction::SDiv:
502  case Instruction::SRem:
503  case Instruction::UDiv:
504  case Instruction::URem:
505  // FIXME: Unlikely to be true for CodeSize.
506  return TTI::TCC_Expensive;
507  }
508 
509  // Assume a 3cy latency for fp arithmetic ops.
510  if (CostKind == TTI::TCK_Latency)
511  if (Ty->getScalarType()->isFloatingPointTy())
512  return 3;
513 
514  return 1;
515  }
516 
520  VectorType *SubTp,
522  return 1;
523  }
524 
525  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
528  const Instruction *I) const {
529  switch (Opcode) {
530  default:
531  break;
532  case Instruction::IntToPtr: {
533  unsigned SrcSize = Src->getScalarSizeInBits();
534  if (DL.isLegalInteger(SrcSize) &&
535  SrcSize <= DL.getPointerTypeSizeInBits(Dst))
536  return 0;
537  break;
538  }
539  case Instruction::PtrToInt: {
540  unsigned DstSize = Dst->getScalarSizeInBits();
541  if (DL.isLegalInteger(DstSize) &&
542  DstSize >= DL.getPointerTypeSizeInBits(Src))
543  return 0;
544  break;
545  }
546  case Instruction::BitCast:
547  if (Dst == Src || (Dst->isPointerTy() && Src->isPointerTy()))
548  // Identity and pointer-to-pointer casts are free.
549  return 0;
550  break;
551  case Instruction::Trunc: {
552  // trunc to a native type is free (assuming the target has compare and
553  // shift-right of the same width).
554  TypeSize DstSize = DL.getTypeSizeInBits(Dst);
555  if (!DstSize.isScalable() && DL.isLegalInteger(DstSize.getFixedSize()))
556  return 0;
557  break;
558  }
559  }
560  return 1;
561  }
562 
564  VectorType *VecTy,
565  unsigned Index) const {
566  return 1;
567  }
568 
570  const Instruction *I = nullptr) const {
571  // A phi would be free, unless we're costing the throughput because it
572  // will require a register.
574  return 0;
575  return 1;
576  }
577 
578  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
579  CmpInst::Predicate VecPred,
581  const Instruction *I) const {
582  return 1;
583  }
584 
585  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
586  unsigned Index) const {
587  return 1;
588  }
589 
591  unsigned Index) const {
592  return 1;
593  }
594 
595  unsigned getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF,
596  const APInt &DemandedDstElts,
598  return 1;
599  }
600 
601  InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
602  unsigned AddressSpace,
604  TTI::OperandValueInfo OpInfo,
605  const Instruction *I) const {
606  return 1;
607  }
608 
609  InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
610  unsigned AddressSpace,
612  const Instruction *I) const {
613  return 1;
614  }
615 
617  Align Alignment, unsigned AddressSpace,
619  return 1;
620  }
621 
622  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
623  const Value *Ptr, bool VariableMask,
624  Align Alignment,
626  const Instruction *I = nullptr) const {
627  return 1;
628  }
629 
631  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
632  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
633  bool UseMaskForCond, bool UseMaskForGaps) const {
634  return 1;
635  }
636 
639  switch (ICA.getID()) {
640  default:
641  break;
642  case Intrinsic::annotation:
643  case Intrinsic::assume:
644  case Intrinsic::sideeffect:
645  case Intrinsic::pseudoprobe:
646  case Intrinsic::arithmetic_fence:
647  case Intrinsic::dbg_declare:
648  case Intrinsic::dbg_value:
649  case Intrinsic::dbg_label:
650  case Intrinsic::invariant_start:
651  case Intrinsic::invariant_end:
652  case Intrinsic::launder_invariant_group:
653  case Intrinsic::strip_invariant_group:
654  case Intrinsic::is_constant:
655  case Intrinsic::lifetime_start:
656  case Intrinsic::lifetime_end:
657  case Intrinsic::experimental_noalias_scope_decl:
658  case Intrinsic::objectsize:
659  case Intrinsic::ptr_annotation:
660  case Intrinsic::var_annotation:
661  case Intrinsic::experimental_gc_result:
662  case Intrinsic::experimental_gc_relocate:
663  case Intrinsic::coro_alloc:
664  case Intrinsic::coro_begin:
665  case Intrinsic::coro_free:
666  case Intrinsic::coro_end:
667  case Intrinsic::coro_frame:
668  case Intrinsic::coro_size:
669  case Intrinsic::coro_align:
670  case Intrinsic::coro_suspend:
671  case Intrinsic::coro_subfn_addr:
672  case Intrinsic::threadlocal_address:
673  // These intrinsics don't actually represent code after lowering.
674  return 0;
675  }
676  return 1;
677  }
678 
680  ArrayRef<Type *> Tys,
682  return 1;
683  }
684 
685  // Assume that we have a register of the right size for the type.
686  unsigned getNumberOfParts(Type *Tp) const { return 1; }
687 
689  const SCEV *) const {
690  return 0;
691  }
692 
695  TTI::TargetCostKind) const {
696  return 1;
697  }
698 
700  TTI::TargetCostKind) const {
701  return 1;
702  }
703 
704  InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned,
705  Type *ResTy, VectorType *Ty,
708  return 1;
709  }
710 
711  InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy,
712  VectorType *Ty,
714  return 1;
715  }
716 
718  return 0;
719  }
720 
722  return false;
723  }
724 
726  // Note for overrides: You must ensure for all element unordered-atomic
727  // memory intrinsics that all power-of-2 element sizes up to, and
728  // including, the return value of this method have a corresponding
729  // runtime lib call. These runtime lib call definitions can be found
730  // in RuntimeLibcalls.h
731  return 0;
732  }
733 
735  Type *ExpectedType) const {
736  return nullptr;
737  }
738 
740  unsigned SrcAddrSpace, unsigned DestAddrSpace,
741  unsigned SrcAlign, unsigned DestAlign,
742  Optional<uint32_t> AtomicElementSize) const {
743  return AtomicElementSize ? Type::getIntNTy(Context, *AtomicElementSize * 8)
745  }
746 
749  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
750  unsigned SrcAlign, unsigned DestAlign,
751  Optional<uint32_t> AtomicCpySize) const {
752  unsigned OpSizeInBytes = AtomicCpySize ? *AtomicCpySize : 1;
753  Type *OpType = Type::getIntNTy(Context, OpSizeInBytes * 8);
754  for (unsigned i = 0; i != RemainingBytes; i += OpSizeInBytes)
755  OpsOut.push_back(OpType);
756  }
757 
758  bool areInlineCompatible(const Function *Caller,
759  const Function *Callee) const {
760  return (Caller->getFnAttribute("target-cpu") ==
761  Callee->getFnAttribute("target-cpu")) &&
762  (Caller->getFnAttribute("target-features") ==
763  Callee->getFnAttribute("target-features"));
764  }
765 
766  bool areTypesABICompatible(const Function *Caller, const Function *Callee,
767  const ArrayRef<Type *> &Types) const {
768  return (Caller->getFnAttribute("target-cpu") ==
769  Callee->getFnAttribute("target-cpu")) &&
770  (Caller->getFnAttribute("target-features") ==
771  Callee->getFnAttribute("target-features"));
772  }
773 
775  const DataLayout &DL) const {
776  return false;
777  }
778 
780  const DataLayout &DL) const {
781  return false;
782  }
783 
784  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { return 128; }
785 
786  bool isLegalToVectorizeLoad(LoadInst *LI) const { return true; }
787 
788  bool isLegalToVectorizeStore(StoreInst *SI) const { return true; }
789 
790  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
791  unsigned AddrSpace) const {
792  return true;
793  }
794 
795  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
796  unsigned AddrSpace) const {
797  return true;
798  }
799 
801  ElementCount VF) const {
802  return true;
803  }
804 
805  bool isElementTypeLegalForScalableVector(Type *Ty) const { return true; }
806 
807  unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
808  unsigned ChainSizeInBytes,
809  VectorType *VecTy) const {
810  return VF;
811  }
812 
813  unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
814  unsigned ChainSizeInBytes,
815  VectorType *VecTy) const {
816  return VF;
817  }
818 
819  bool preferInLoopReduction(unsigned Opcode, Type *Ty,
820  TTI::ReductionFlags Flags) const {
821  return false;
822  }
823 
824  bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
825  TTI::ReductionFlags Flags) const {
826  return false;
827  }
828 
829  bool shouldExpandReduction(const IntrinsicInst *II) const { return true; }
830 
831  unsigned getGISelRematGlobalCost() const { return 1; }
832 
833  unsigned getMinTripCountTailFoldingThreshold() const { return 0; }
834 
835  bool supportsScalableVectors() const { return false; }
836 
837  bool enableScalableVectorization() const { return false; }
838 
839  bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
840  Align Alignment) const {
841  return false;
842  }
843 
847  /* EVLParamStrategy */ TargetTransformInfo::VPLegalization::Discard,
848  /* OperatorStrategy */ TargetTransformInfo::VPLegalization::Convert);
849  }
850 
851 protected:
852  // Obtain the minimum required size to hold the value (without the sign)
853  // In case of a vector it returns the min required size for one element.
854  unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const {
855  if (isa<ConstantDataVector>(Val) || isa<ConstantVector>(Val)) {
856  const auto *VectorValue = cast<Constant>(Val);
857 
858  // In case of a vector need to pick the max between the min
859  // required size for each element
860  auto *VT = cast<FixedVectorType>(Val->getType());
861 
862  // Assume unsigned elements
863  isSigned = false;
864 
865  // The max required size is the size of the vector element type
866  unsigned MaxRequiredSize =
867  VT->getElementType()->getPrimitiveSizeInBits().getFixedSize();
868 
869  unsigned MinRequiredSize = 0;
870  for (unsigned i = 0, e = VT->getNumElements(); i < e; ++i) {
871  if (auto *IntElement =
872  dyn_cast<ConstantInt>(VectorValue->getAggregateElement(i))) {
873  bool signedElement = IntElement->getValue().isNegative();
874  // Get the element min required size.
875  unsigned ElementMinRequiredSize =
876  IntElement->getValue().getMinSignedBits() - 1;
877  // In case one element is signed then all the vector is signed.
878  isSigned |= signedElement;
879  // Save the max required bit size between all the elements.
880  MinRequiredSize = std::max(MinRequiredSize, ElementMinRequiredSize);
881  } else {
882  // not an int constant element
883  return MaxRequiredSize;
884  }
885  }
886  return MinRequiredSize;
887  }
888 
889  if (const auto *CI = dyn_cast<ConstantInt>(Val)) {
890  isSigned = CI->getValue().isNegative();
891  return CI->getValue().getMinSignedBits() - 1;
892  }
893 
894  if (const auto *Cast = dyn_cast<SExtInst>(Val)) {
895  isSigned = true;
896  return Cast->getSrcTy()->getScalarSizeInBits() - 1;
897  }
898 
899  if (const auto *Cast = dyn_cast<ZExtInst>(Val)) {
900  isSigned = false;
901  return Cast->getSrcTy()->getScalarSizeInBits();
902  }
903 
904  isSigned = false;
905  return Val->getType()->getScalarSizeInBits();
906  }
907 
908  bool isStridedAccess(const SCEV *Ptr) const {
909  return Ptr && isa<SCEVAddRecExpr>(Ptr);
910  }
911 
913  const SCEV *Ptr) const {
914  if (!isStridedAccess(Ptr))
915  return nullptr;
916  const SCEVAddRecExpr *AddRec = cast<SCEVAddRecExpr>(Ptr);
917  return dyn_cast<SCEVConstant>(AddRec->getStepRecurrence(*SE));
918  }
919 
921  int64_t MergeDistance) const {
922  const SCEVConstant *Step = getConstantStrideStep(SE, Ptr);
923  if (!Step)
924  return false;
925  APInt StrideVal = Step->getAPInt();
926  if (StrideVal.getBitWidth() > 64)
927  return false;
928  // FIXME: Need to take absolute value for negative stride case.
929  return StrideVal.getSExtValue() < MergeDistance;
930  }
931 };
932 
933 /// CRTP base class for use as a mix-in that aids implementing
934 /// a TargetTransformInfo-compatible class.
935 template <typename T>
937 private:
939 
940 protected:
942 
943 public:
944  using BaseT::getGEPCost;
945 
946  InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr,
949  assert(PointeeType && Ptr && "can't get GEPCost of nullptr");
950  assert(cast<PointerType>(Ptr->getType()->getScalarType())
951  ->isOpaqueOrPointeeTypeMatches(PointeeType) &&
952  "explicit pointee type doesn't match operand's pointee type");
953  auto *BaseGV = dyn_cast<GlobalValue>(Ptr->stripPointerCasts());
954  bool HasBaseReg = (BaseGV == nullptr);
955 
956  auto PtrSizeBits = DL.getPointerTypeSizeInBits(Ptr->getType());
957  APInt BaseOffset(PtrSizeBits, 0);
958  int64_t Scale = 0;
959 
960  auto GTI = gep_type_begin(PointeeType, Operands);
961  Type *TargetType = nullptr;
962 
963  // Handle the case where the GEP instruction has a single operand,
964  // the basis, therefore TargetType is a nullptr.
965  if (Operands.empty())
966  return !BaseGV ? TTI::TCC_Free : TTI::TCC_Basic;
967 
968  for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) {
969  TargetType = GTI.getIndexedType();
970  // We assume that the cost of Scalar GEP with constant index and the
971  // cost of Vector GEP with splat constant index are the same.
972  const ConstantInt *ConstIdx = dyn_cast<ConstantInt>(*I);
973  if (!ConstIdx)
974  if (auto Splat = getSplatValue(*I))
975  ConstIdx = dyn_cast<ConstantInt>(Splat);
976  if (StructType *STy = GTI.getStructTypeOrNull()) {
977  // For structures the index is always splat or scalar constant
978  assert(ConstIdx && "Unexpected GEP index");
979  uint64_t Field = ConstIdx->getZExtValue();
980  BaseOffset += DL.getStructLayout(STy)->getElementOffset(Field);
981  } else {
982  // If this operand is a scalable type, bail out early.
983  // TODO: handle scalable vectors
984  if (isa<ScalableVectorType>(TargetType))
985  return TTI::TCC_Basic;
986  int64_t ElementSize =
987  DL.getTypeAllocSize(GTI.getIndexedType()).getFixedSize();
988  if (ConstIdx) {
989  BaseOffset +=
990  ConstIdx->getValue().sextOrTrunc(PtrSizeBits) * ElementSize;
991  } else {
992  // Needs scale register.
993  if (Scale != 0)
994  // No addressing mode takes two scale registers.
995  return TTI::TCC_Basic;
996  Scale = ElementSize;
997  }
998  }
999  }
1000 
1001  if (static_cast<T *>(this)->isLegalAddressingMode(
1002  TargetType, const_cast<GlobalValue *>(BaseGV),
1003  BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale,
1004  Ptr->getType()->getPointerAddressSpace()))
1005  return TTI::TCC_Free;
1006  return TTI::TCC_Basic;
1007  }
1008 
1012  using namespace llvm::PatternMatch;
1013 
1014  auto *TargetTTI = static_cast<T *>(this);
1015  // Handle non-intrinsic calls, invokes, and callbr.
1016  // FIXME: Unlikely to be true for anything but CodeSize.
1017  auto *CB = dyn_cast<CallBase>(U);
1018  if (CB && !isa<IntrinsicInst>(U)) {
1019  if (const Function *F = CB->getCalledFunction()) {
1020  if (!TargetTTI->isLoweredToCall(F))
1021  return TTI::TCC_Basic; // Give a basic cost if it will be lowered
1022 
1023  return TTI::TCC_Basic * (F->getFunctionType()->getNumParams() + 1);
1024  }
1025  // For indirect or other calls, scale cost by number of arguments.
1026  return TTI::TCC_Basic * (CB->arg_size() + 1);
1027  }
1028 
1029  Type *Ty = U->getType();
1030  unsigned Opcode = Operator::getOpcode(U);
1031  auto *I = dyn_cast<Instruction>(U);
1032  switch (Opcode) {
1033  default:
1034  break;
1035  case Instruction::Call: {
1036  assert(isa<IntrinsicInst>(U) && "Unexpected non-intrinsic call");
1037  auto *Intrinsic = cast<IntrinsicInst>(U);
1038  IntrinsicCostAttributes CostAttrs(Intrinsic->getIntrinsicID(), *CB);
1039  return TargetTTI->getIntrinsicInstrCost(CostAttrs, CostKind);
1040  }
1041  case Instruction::Br:
1042  case Instruction::Ret:
1043  case Instruction::PHI:
1044  case Instruction::Switch:
1045  return TargetTTI->getCFInstrCost(Opcode, CostKind, I);
1046  case Instruction::ExtractValue:
1047  case Instruction::Freeze:
1048  return TTI::TCC_Free;
1049  case Instruction::Alloca:
1050  if (cast<AllocaInst>(U)->isStaticAlloca())
1051  return TTI::TCC_Free;
1052  break;
1053  case Instruction::GetElementPtr: {
1054  const auto *GEP = cast<GEPOperator>(U);
1055  return TargetTTI->getGEPCost(GEP->getSourceElementType(),
1056  GEP->getPointerOperand(),
1057  Operands.drop_front(), CostKind);
1058  }
1059  case Instruction::Add:
1060  case Instruction::FAdd:
1061  case Instruction::Sub:
1062  case Instruction::FSub:
1063  case Instruction::Mul:
1064  case Instruction::FMul:
1065  case Instruction::UDiv:
1066  case Instruction::SDiv:
1067  case Instruction::FDiv:
1068  case Instruction::URem:
1069  case Instruction::SRem:
1070  case Instruction::FRem:
1071  case Instruction::Shl:
1072  case Instruction::LShr:
1073  case Instruction::AShr:
1074  case Instruction::And:
1075  case Instruction::Or:
1076  case Instruction::Xor:
1077  case Instruction::FNeg: {
1078  const TTI::OperandValueInfo Op1Info = TTI::getOperandInfo(U->getOperand(0));
1079  TTI::OperandValueInfo Op2Info;
1080  if (Opcode != Instruction::FNeg)
1081  Op2Info = TTI::getOperandInfo(U->getOperand(1));
1083  return TargetTTI->getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
1084  Op2Info, Operands, I);
1085  }
1086  case Instruction::IntToPtr:
1087  case Instruction::PtrToInt:
1088  case Instruction::SIToFP:
1089  case Instruction::UIToFP:
1090  case Instruction::FPToUI:
1091  case Instruction::FPToSI:
1092  case Instruction::Trunc:
1093  case Instruction::FPTrunc:
1094  case Instruction::BitCast:
1095  case Instruction::FPExt:
1096  case Instruction::SExt:
1097  case Instruction::ZExt:
1098  case Instruction::AddrSpaceCast: {
1099  Type *OpTy = U->getOperand(0)->getType();
1100  return TargetTTI->getCastInstrCost(
1101  Opcode, Ty, OpTy, TTI::getCastContextHint(I), CostKind, I);
1102  }
1103  case Instruction::Store: {
1104  auto *SI = cast<StoreInst>(U);
1105  Type *ValTy = U->getOperand(0)->getType();
1107  return TargetTTI->getMemoryOpCost(Opcode, ValTy, SI->getAlign(),
1108  SI->getPointerAddressSpace(), CostKind,
1109  OpInfo, I);
1110  }
1111  case Instruction::Load: {
1112  // FIXME: Arbitary cost which could come from the backend.
1113  if (CostKind == TTI::TCK_Latency)
1114  return 4;
1115  auto *LI = cast<LoadInst>(U);
1116  Type *LoadType = U->getType();
1117  // If there is a non-register sized type, the cost estimation may expand
1118  // it to be several instructions to load into multiple registers on the
1119  // target. But, if the only use of the load is a trunc instruction to a
1120  // register sized type, the instruction selector can combine these
1121  // instructions to be a single load. So, in this case, we use the
1122  // destination type of the trunc instruction rather than the load to
1123  // accurately estimate the cost of this load instruction.
1124  if (CostKind == TTI::TCK_CodeSize && LI->hasOneUse() &&
1125  !LoadType->isVectorTy()) {
1126  if (const TruncInst *TI = dyn_cast<TruncInst>(*LI->user_begin()))
1127  LoadType = TI->getDestTy();
1128  }
1129  return TargetTTI->getMemoryOpCost(Opcode, LoadType, LI->getAlign(),
1131  {TTI::OK_AnyValue, TTI::OP_None}, I);
1132  }
1133  case Instruction::Select: {
1134  const Value *Op0, *Op1;
1135  if (match(U, m_LogicalAnd(m_Value(Op0), m_Value(Op1))) ||
1136  match(U, m_LogicalOr(m_Value(Op0), m_Value(Op1)))) {
1137  // select x, y, false --> x & y
1138  // select x, true, y --> x | y
1139  const auto Op1Info = TTI::getOperandInfo(Op0);
1140  const auto Op2Info = TTI::getOperandInfo(Op1);
1141  assert(Op0->getType()->getScalarSizeInBits() == 1 &&
1142  Op1->getType()->getScalarSizeInBits() == 1);
1143 
1145  return TargetTTI->getArithmeticInstrCost(
1146  match(U, m_LogicalOr()) ? Instruction::Or : Instruction::And, Ty,
1147  CostKind, Op1Info, Op2Info, Operands, I);
1148  }
1149  Type *CondTy = U->getOperand(0)->getType();
1150  return TargetTTI->getCmpSelInstrCost(Opcode, U->getType(), CondTy,
1152  CostKind, I);
1153  }
1154  case Instruction::ICmp:
1155  case Instruction::FCmp: {
1156  Type *ValTy = U->getOperand(0)->getType();
1157  // TODO: Also handle ICmp/FCmp constant expressions.
1158  return TargetTTI->getCmpSelInstrCost(Opcode, ValTy, U->getType(),
1159  I ? cast<CmpInst>(I)->getPredicate()
1161  CostKind, I);
1162  }
1163  case Instruction::InsertElement: {
1164  auto *IE = dyn_cast<InsertElementInst>(U);
1165  if (!IE)
1166  return TTI::TCC_Basic; // FIXME
1167  unsigned Idx = -1;
1168  if (auto *CI = dyn_cast<ConstantInt>(IE->getOperand(2)))
1169  if (CI->getValue().getActiveBits() <= 32)
1170  Idx = CI->getZExtValue();
1171  return TargetTTI->getVectorInstrCost(*IE, Ty, Idx);
1172  }
1173  case Instruction::ShuffleVector: {
1174  auto *Shuffle = dyn_cast<ShuffleVectorInst>(U);
1175  if (!Shuffle)
1176  return TTI::TCC_Basic; // FIXME
1177 
1178  auto *VecTy = cast<VectorType>(U->getType());
1179  auto *VecSrcTy = cast<VectorType>(U->getOperand(0)->getType());
1180  int NumSubElts, SubIndex;
1181 
1182  if (Shuffle->changesLength()) {
1183  // Treat a 'subvector widening' as a free shuffle.
1184  if (Shuffle->increasesLength() && Shuffle->isIdentityWithPadding())
1185  return 0;
1186 
1187  if (Shuffle->isExtractSubvectorMask(SubIndex))
1188  return TargetTTI->getShuffleCost(TTI::SK_ExtractSubvector, VecSrcTy,
1189  Shuffle->getShuffleMask(), CostKind,
1190  SubIndex, VecTy, Operands);
1191 
1192  if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1193  return TargetTTI->getShuffleCost(
1194  TTI::SK_InsertSubvector, VecTy, Shuffle->getShuffleMask(),
1195  CostKind, SubIndex,
1196  FixedVectorType::get(VecTy->getScalarType(), NumSubElts),
1197  Operands);
1198 
1199  int ReplicationFactor, VF;
1200  if (Shuffle->isReplicationMask(ReplicationFactor, VF)) {
1201  APInt DemandedDstElts =
1202  APInt::getNullValue(Shuffle->getShuffleMask().size());
1203  for (auto I : enumerate(Shuffle->getShuffleMask())) {
1204  if (I.value() != UndefMaskElem)
1205  DemandedDstElts.setBit(I.index());
1206  }
1207  return TargetTTI->getReplicationShuffleCost(
1208  VecSrcTy->getElementType(), ReplicationFactor, VF,
1209  DemandedDstElts, CostKind);
1210  }
1211 
1212  return CostKind == TTI::TCK_RecipThroughput ? -1 : 1;
1213  }
1214 
1215  if (Shuffle->isIdentity())
1216  return 0;
1217 
1218  if (Shuffle->isReverse())
1219  return TargetTTI->getShuffleCost(TTI::SK_Reverse, VecTy,
1220  Shuffle->getShuffleMask(), CostKind, 0,
1221  nullptr, Operands);
1222 
1223  if (Shuffle->isSelect())
1224  return TargetTTI->getShuffleCost(TTI::SK_Select, VecTy,
1225  Shuffle->getShuffleMask(), CostKind, 0,
1226  nullptr, Operands);
1227 
1228  if (Shuffle->isTranspose())
1229  return TargetTTI->getShuffleCost(TTI::SK_Transpose, VecTy,
1230  Shuffle->getShuffleMask(), CostKind, 0,
1231  nullptr, Operands);
1232 
1233  if (Shuffle->isZeroEltSplat())
1234  return TargetTTI->getShuffleCost(TTI::SK_Broadcast, VecTy,
1235  Shuffle->getShuffleMask(), CostKind, 0,
1236  nullptr, Operands);
1237 
1238  if (Shuffle->isSingleSource())
1239  return TargetTTI->getShuffleCost(TTI::SK_PermuteSingleSrc, VecTy,
1240  Shuffle->getShuffleMask(), CostKind, 0,
1241  nullptr, Operands);
1242 
1243  if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1244  return TargetTTI->getShuffleCost(
1245  TTI::SK_InsertSubvector, VecTy, Shuffle->getShuffleMask(), CostKind,
1246  SubIndex, FixedVectorType::get(VecTy->getScalarType(), NumSubElts),
1247  Operands);
1248 
1249  if (Shuffle->isSplice(SubIndex))
1250  return TargetTTI->getShuffleCost(TTI::SK_Splice, VecTy,
1251  Shuffle->getShuffleMask(), CostKind,
1252  SubIndex, nullptr, Operands);
1253 
1254  return TargetTTI->getShuffleCost(TTI::SK_PermuteTwoSrc, VecTy,
1255  Shuffle->getShuffleMask(), CostKind, 0,
1256  nullptr, Operands);
1257  }
1258  case Instruction::ExtractElement: {
1259  auto *EEI = dyn_cast<ExtractElementInst>(U);
1260  if (!EEI)
1261  return TTI::TCC_Basic; // FIXME
1262  unsigned Idx = -1;
1263  if (auto *CI = dyn_cast<ConstantInt>(EEI->getOperand(1)))
1264  if (CI->getValue().getActiveBits() <= 32)
1265  Idx = CI->getZExtValue();
1266  Type *DstTy = U->getOperand(0)->getType();
1267  return TargetTTI->getVectorInstrCost(*EEI, DstTy, Idx);
1268  }
1269  }
1270 
1271  // By default, just classify everything as 'basic' or -1 to represent that
1272  // don't know the throughput cost.
1274  }
1275 
1277  auto *TargetTTI = static_cast<T *>(this);
1278  SmallVector<const Value *, 4> Ops(I->operand_values());
1279  InstructionCost Cost = TargetTTI->getInstructionCost(
1282  }
1283 };
1284 } // namespace llvm
1285 
1286 #endif
i
i
Definition: README.txt:29
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::CacheLevel::L1D
@ L1D
llvm::TargetTransformInfoImplBase::canHaveNonUndefGlobalInitializerInAddressSpace
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Definition: TargetTransformInfoImpl.h:105
llvm::TargetTransformInfoImplBase::getCacheLineSize
unsigned getCacheLineSize() const
Definition: TargetTransformInfoImpl.h:452
llvm::TargetTransformInfo::SK_Select
@ SK_Select
Selects elements from the corresponding lane of either source operand.
Definition: TargetTransformInfo.h:887
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:217
llvm::TargetTransformInfoImplBase::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Definition: TargetTransformInfoImpl.h:157
llvm::TargetTransformInfo::LSRCost::NumRegs
unsigned NumRegs
Definition: TargetTransformInfo.h:404
llvm::TargetTransformInfo::TCC_Expensive
@ TCC_Expensive
The cost of a 'div' instruction on x86.
Definition: TargetTransformInfo.h:245
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1452
llvm::TargetTransformInfoImplBase::getVectorInstrCost
InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, unsigned Index) const
Definition: TargetTransformInfoImpl.h:590
llvm::TargetTransformInfoImplBase::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=None) const
Definition: TargetTransformInfoImpl.h:517
llvm::TargetTransformInfoImplBase::useAA
bool useAA() const
Definition: TargetTransformInfoImpl.h:317
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetTransformInfo::MemIndexedMode
MemIndexedMode
The type of load/store indexing.
Definition: TargetTransformInfo.h:1400
llvm::TargetTransformInfo::TCK_Latency
@ TCK_Latency
The latency of instruction.
Definition: TargetTransformInfo.h:219
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::TargetTransformInfoImplBase::enableOrderedReductions
bool enableOrderedReductions() const
Definition: TargetTransformInfoImpl.h:290
llvm::TargetTransformInfoImplBase::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const
Definition: TargetTransformInfoImpl.h:109
PHI
Rewrite undef for PHI
Definition: AMDGPURewriteUndefForPHI.cpp:101
llvm::TargetTransformInfoImplBase::isStridedAccess
bool isStridedAccess(const SCEV *Ptr) const
Definition: TargetTransformInfoImpl.h:908
IntrinsicInst.h
llvm::TargetTransformInfoImplBase::isLSRCostLess
bool isLSRCostLess(const TTI::LSRCost &C1, const TTI::LSRCost &C2) const
Definition: TargetTransformInfoImpl.h:214
llvm::ElementCount
Definition: TypeSize.h:404
llvm::TargetTransformInfoImplBase::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: TargetTransformInfoImpl.h:431
llvm::TypeSize::getFixedSize
ScalarTy getFixedSize() const
Definition: TypeSize.h:444
T
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:546
llvm::TargetTransformInfoImplBase::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const
Definition: TargetTransformInfoImpl.h:204
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:583
llvm::DataLayout::getTypeSizeInBits
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:673
llvm::TargetTransformInfoImplCRTPBase::getInstructionCost
InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:1009
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
GetElementPtrTypeIterator.h
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:314
llvm::ConstantInt::getValue
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:133
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1181
llvm::DataLayout::getPointerTypeSizeInBits
unsigned getPointerTypeSizeInBits(Type *) const
Layout pointer size, in bits, based on the type.
Definition: DataLayout.cpp:721
llvm::enumerate
detail::enumerator< R > enumerate(R &&TheRange)
Given an input range, returns a new range whose values are are pair (A,B) such that A is the 0-based ...
Definition: STLExtras.h:2068
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1478
llvm::DataLayout::getTypeStoreSize
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Definition: DataLayout.h:474
llvm::TargetTransformInfoImplBase::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType) const
Definition: TargetTransformInfoImpl.h:288
llvm::TargetTransformInfoImplBase::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *, const SCEV *) const
Definition: TargetTransformInfoImpl.h:688
llvm::TargetTransformInfoImplBase::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Definition: TargetTransformInfoImpl.h:97
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:371
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:172
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:729
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::LoopVectorizationLegality
LoopVectorizationLegality checks if it is legal to vectorize a loop, and to what vectorization factor...
Definition: LoopVectorizationLegality.h:241
llvm::TargetTransformInfoImplBase::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: TargetTransformInfoImpl.h:429
llvm::TargetTransformInfoImplBase::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent() const
Definition: TargetTransformInfoImpl.h:73
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:166
llvm::TargetTransformInfoImplBase::TTI
TargetTransformInfo TTI
Definition: TargetTransformInfoImpl.h:35
llvm::TargetTransformInfoImplBase::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:300
llvm::TargetTransformInfo::TCK_CodeSize
@ TCK_CodeSize
Instruction code size.
Definition: TargetTransformInfo.h:220
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1506
llvm::DataLayout::getStructLayout
const StructLayout * getStructLayout(StructType *Ty) const
Returns a StructLayout object, indicating the alignment of the struct, its size, and the offsets of i...
Definition: DataLayout.cpp:678
llvm::TargetTransformInfo::LSRCost::NumIVMuls
unsigned NumIVMuls
Definition: TargetTransformInfo.h:406
llvm::TargetTransformInfoImplBase::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: TargetTransformInfoImpl.h:414
llvm::TargetTransformInfoImplBase::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:784
llvm::TargetTransformInfoImplBase::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Definition: TargetTransformInfoImpl.h:371
llvm::TargetTransformInfoImplBase::getMulAccReductionCost
InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:711
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1411
llvm::TargetTransformInfo::VPLegalization::Convert
@ Convert
Definition: TargetTransformInfo.h:1513
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:526
llvm::TargetTransformInfoImplBase::isLegalAltInstr
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
Definition: TargetTransformInfoImpl.h:283
llvm::TargetTransformInfoImplBase::isLegalToVectorizeStore
bool isLegalToVectorizeStore(StoreInst *SI) const
Definition: TargetTransformInfoImpl.h:788
llvm::TargetTransformInfoImplBase::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const
Definition: TargetTransformInfoImpl.h:315
llvm::Optional
Definition: APInt.h:33
llvm::TargetTransformInfoImplBase::supportsTailCalls
bool supportsTailCalls() const
Definition: TargetTransformInfoImpl.h:344
Vector
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
T
#define T
Definition: Mips16ISelLowering.cpp:341
Operator.h
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
llvm::TargetTransformInfoImplBase::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Definition: TargetTransformInfoImpl.h:91
llvm::TargetTransformInfoImplBase::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:390
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(const DataLayout &DL)
Definition: TargetTransformInfoImpl.h:39
llvm::TargetTransformInfoImplCRTPBase::getGEPCost
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:946
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:458
llvm::gep_type_begin
gep_type_iterator gep_type_begin(const User *GEP)
Definition: GetElementPtrTypeIterator.h:123
llvm::TargetTransformInfoImplBase::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *, VectorType *, bool, TTI::TargetCostKind) const
Definition: TargetTransformInfoImpl.h:699
llvm::Type::isFloatingPointTy
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Definition: Type.h:168
llvm::TargetTransformInfo::OperandValueInfo
Definition: TargetTransformInfo.h:921
llvm::TargetTransformInfoImplBase::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:268
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::TargetTransformInfo::SK_PermuteSingleSrc
@ SK_PermuteSingleSrc
Shuffle elements of single source vector with any shuffle mask.
Definition: TargetTransformInfo.h:895
llvm::TargetTransformInfoImplBase::haveFastSqrt
bool haveFastSqrt(Type *Ty) const
Definition: TargetTransformInfoImpl.h:375
llvm::Type::getInt8Ty
static IntegerType * getInt8Ty(LLVMContext &C)
Definition: Type.cpp:237
llvm::TargetTransformInfoImplBase::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization() const
Definition: TargetTransformInfoImpl.h:359
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:298
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:1018
llvm::TargetTransformInfoImplBase::getConstantStrideStep
const SCEVConstant * getConstantStrideStep(ScalarEvolution *SE, const SCEV *Ptr) const
Definition: TargetTransformInfoImpl.h:912
llvm::TargetTransformInfoImplBase::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Definition: TargetTransformInfoImpl.h:99
llvm::TargetTransformInfo::SK_Broadcast
@ SK_Broadcast
Broadcast element 0 to all other elements.
Definition: TargetTransformInfo.h:885
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::TargetTransformInfo::LSRCost::AddRecCost
unsigned AddRecCost
Definition: TargetTransformInfo.h:405
llvm::TargetTransformInfoImplBase::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Definition: TargetTransformInfoImpl.h:313
llvm::UndefMaskElem
constexpr int UndefMaskElem
Definition: Instructions.h:1996
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:46
llvm::TargetTransformInfoImplBase::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: TargetTransformInfoImpl.h:758
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:35
llvm::TargetTransformInfoImplBase::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: TargetTransformInfoImpl.h:439
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::TargetTransformInfo::LSRCost::SetupCost
unsigned SetupCost
Definition: TargetTransformInfo.h:409
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetTransformInfoImplBase::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR() const
Definition: TargetTransformInfoImpl.h:221
llvm::TargetTransformInfoImplBase::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: TargetTransformInfoImpl.h:800
llvm::TargetTransformInfoImplBase::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, LoopVectorizationLegality *LVL, InterleavedAccessInfo *IAI) const
Definition: TargetTransformInfoImpl.h:163
llvm::TargetTransformInfoImplBase::getPredictableBranchThreshold
BranchProbability getPredictableBranchThreshold() const
Definition: TargetTransformInfoImpl.h:85
llvm::TargetTransformInfoImplBase::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, bool *Fast) const
Definition: TargetTransformInfoImpl.h:365
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::TargetTransformInfoImplBase::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Definition: TargetTransformInfoImpl.h:292
llvm::TargetTransformInfo::SK_PermuteTwoSrc
@ SK_PermuteTwoSrc
Merge elements from two source vectors into one with any shuffle mask.
Definition: TargetTransformInfo.h:893
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::LinearPolySize< ElementCount >::get
static ElementCount get(ScalarTy MinVal, bool Scalable)
Definition: TypeSize.h:289
llvm::TargetTransformInfoImplBase::getReplicationShuffleCost
unsigned getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:595
llvm::TargetTransformInfo::getCastContextHint
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
Definition: TargetTransformInfo.cpp:808
llvm::TargetTransformInfoImplBase::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF) const
Definition: TargetTransformInfoImpl.h:487
llvm::APInt::setBit
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
Definition: APInt.h:1280
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(TargetTransformInfoImplBase &&Arg)
Definition: TargetTransformInfoImpl.h:44
llvm::TargetTransformInfoImplBase
Base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:33
llvm::TargetTransformInfoImplBase::getCacheAssociativity
llvm::Optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const
Definition: TargetTransformInfoImpl.h:466
llvm::PatternMatch::match
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
llvm::TargetTransformInfoImplBase::getPrefetchDistance
unsigned getPrefetchDistance() const
Definition: TargetTransformInfoImpl.h:477
llvm::TargetTransformInfoImplBase::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: TargetTransformInfoImpl.h:408
InlinePriorityMode::Cost
@ Cost
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:884
llvm::TargetTransformInfoImplBase::hasActiveVectorLength
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:839
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1136
llvm::TargetTransformInfoImplBase::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:238
llvm::User
Definition: User.h:44
llvm::TargetTransformInfoImplBase::forceScalarizeMaskedScatter
bool forceScalarizeMaskedScatter(VectorType *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:276
llvm::TargetTransformInfoImplCRTPBase::isExpensiveToSpeculativelyExecute
bool isExpensiveToSpeculativelyExecute(const Instruction *I)
Definition: TargetTransformInfoImpl.h:1276
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetTransformInfoImplBase::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Definition: TargetTransformInfoImpl.h:325
llvm::TargetTransformInfoImplBase::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const
Definition: TargetTransformInfoImpl.h:585
llvm::TargetTransformInfoImplBase::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicElementSize) const
Definition: TargetTransformInfoImpl.h:739
llvm::Type::isVectorTy
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:232
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::TargetTransformInfoImplBase::hasBranchDivergence
bool hasBranchDivergence() const
Definition: TargetTransformInfoImpl.h:89
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::TargetTransformInfoImplBase::isIndexedStoreLegal
bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
Definition: TargetTransformInfoImpl.h:779
llvm::TargetTransformInfoImplBase::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Definition: TargetTransformInfoImpl.h:323
llvm::Instruction
Definition: Instruction.h:42
llvm::InterleavedAccessInfo
Drive the analysis of interleaved memory accesses in the loop.
Definition: VectorUtils.h:751
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:189
llvm::TargetTransformInfoImplBase::getNumberOfParts
unsigned getNumberOfParts(Type *Tp) const
Definition: TargetTransformInfoImpl.h:686
llvm::TargetTransformInfoImplBase::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
Definition: TargetTransformInfoImpl.h:395
llvm::Operator::getOpcode
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
Definition: Operator.h:42
llvm::TargetTransformInfoImplBase::isTypeLegal
bool isTypeLegal(Type *Ty) const
Definition: TargetTransformInfoImpl.h:319
llvm::TargetTransformInfoImplBase::isLegalAddressingMode
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:206
llvm::TargetTransformInfoImplBase::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicCpySize) const
Definition: TargetTransformInfoImpl.h:747
llvm::TargetTransformInfoImplBase::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:569
llvm::TargetTransformInfoImplBase::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
Definition: TargetTransformInfoImpl.h:734
llvm::TargetTransformInfoImplCRTPBase
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:936
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetTransformInfoImplBase::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:294
llvm::TargetTransformInfoImplBase::getPredicatedAddrSpace
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
Definition: TargetTransformInfoImpl.h:112
PatternMatch.h
llvm::TargetTransformInfoImplBase::getCostOfKeepingLiveOverCall
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
Definition: TargetTransformInfoImpl.h:717
llvm::TargetTransformInfoImplBase::enableWritePrefetching
bool enableWritePrefetching() const
Definition: TargetTransformInfoImpl.h:484
llvm::FixedVectorType::get
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
Definition: Type.cpp:684
llvm::TargetTransformInfoImplBase::enableMemCmpExpansion
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: TargetTransformInfoImpl.h:354
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:155
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::TargetTransformInfoImplBase::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Definition: TargetTransformInfoImpl.h:93
llvm::TargetTransformInfoImplBase::getVPLegalizationStrategy
TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: TargetTransformInfoImpl.h:845
llvm::TargetTransformInfoImplBase::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:616
llvm::None
const NoneType None
Definition: None.h:24
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:119
llvm::TargetTransformInfoImplBase::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:601
llvm::TargetTransformInfoImplBase::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:622
llvm::TargetTransformInfo::PSK_Software
@ PSK_Software
Definition: TargetTransformInfo.h:583
llvm::TargetTransformInfoImplBase::getCacheSize
llvm::Optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const
Definition: TargetTransformInfoImpl.h:455
llvm::TargetTransformInfoImplBase::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I) const
Definition: TargetTransformInfoImpl.h:223
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::TargetTransformInfoImplBase::supportsTailCallFor
bool supportsTailCallFor(const CallBase *CB) const
Definition: TargetTransformInfoImpl.h:346
llvm::ARM_PROC::IE
@ IE
Definition: ARMBaseInfo.h:27
llvm::TargetTransformInfoImplBase::getGEPCost
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:48
llvm::TargetTransformInfoImplBase::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: TargetTransformInfoImpl.h:187
llvm::TargetTransformInfoImplBase::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: TargetTransformInfoImpl.h:824
llvm::TargetTransformInfoImplBase::supportsScalableVectors
bool supportsScalableVectors() const
Definition: TargetTransformInfoImpl.h:835
llvm::TargetTransformInfoImplBase::enableMaskedInterleavedAccessVectorization
bool enableMaskedInterleavedAccessVectorization() const
Definition: TargetTransformInfoImpl.h:361
llvm::TargetTransformInfo::SK_Reverse
@ SK_Reverse
Reverse the order of the vector.
Definition: TargetTransformInfo.h:886
llvm::TargetTransformInfoImplCRTPBase::TargetTransformInfoImplCRTPBase
TargetTransformInfoImplCRTPBase(const DataLayout &DL)
Definition: TargetTransformInfoImpl.h:941
llvm::TargetTransformInfoImplBase::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:679
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
VectorUtils.h
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:75
llvm::TargetTransformInfoImplBase::canMacroFuseCmp
bool canMacroFuseCmp() const
Definition: TargetTransformInfoImpl.h:225
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:298
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::TargetTransformInfo::SK_InsertSubvector
@ SK_InsertSubvector
InsertSubvector. Index indicates start offset.
Definition: TargetTransformInfo.h:891
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetTransformInfoImplBase::getEstimatedNumberOfCaseClusters
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Definition: TargetTransformInfoImpl.h:60
llvm::TargetTransformInfoImplBase::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:246
uint64_t
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:400
llvm::TargetTransformInfoImplBase::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:795
llvm::PatternMatch::m_LogicalOr
LogicalOp_match< LHS, RHS, Instruction::Or > m_LogicalOr(const LHS &L, const RHS &R)
Matches L || R either in the form of L | R or L ? true : R.
Definition: PatternMatch.h:2555
llvm::TargetTransformInfoImplBase::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned, VectorType *, Optional< FastMathFlags > FMF, TTI::TargetCostKind) const
Definition: TargetTransformInfoImpl.h:693
llvm::TruncInst
This class represents a truncation of integer types.
Definition: Instructions.h:4811
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::TargetTransformInfoImplBase::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Definition: TargetTransformInfoImpl.h:181
llvm::TargetTransformInfoImplBase::getPreferredAddressingMode
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Definition: TargetTransformInfoImpl.h:234
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:414
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetTransformInfoImplBase::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:525
llvm::SCEVConstant
This class represents a constant integer value.
Definition: ScalarEvolutionExpressions.h:60
llvm::TargetTransformInfoImplBase::isExpensiveToSpeculativelyExecute
bool isExpensiveToSpeculativelyExecute(const Instruction *I)
Definition: TargetTransformInfoImpl.h:377
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetTransformInfo::VPLegalization::Discard
@ Discard
Definition: TargetTransformInfo.h:1511
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::TargetTransformInfoImplBase::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
Definition: TargetTransformInfoImpl.h:446
llvm::TargetTransformInfoImplBase::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Definition: TargetTransformInfoImpl.h:121
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::CmpInst::BAD_ICMP_PREDICATE
@ BAD_ICMP_PREDICATE
Definition: InstrTypes.h:752
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::TargetTransformInfo::LSRCost::ScaleCost
unsigned ScaleCost
Definition: TargetTransformInfo.h:410
llvm::TargetTransformInfoImplBase::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
Definition: TargetTransformInfoImpl.h:337
llvm::TargetTransformInfo::SK_Splice
@ SK_Splice
Concatenates elements from the first input vector with elements of the second input vector.
Definition: TargetTransformInfo.h:897
llvm::TargetTransformInfoImplBase::getInterleavedMemoryOpCost
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) const
Definition: TargetTransformInfoImpl.h:630
llvm::TargetTransformInfoImplBase::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: TargetTransformInfoImpl.h:721
llvm::TargetTransformInfoImplBase::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Definition: TargetTransformInfoImpl.h:350
llvm::TargetTransformInfoImplBase::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info, TTI::OperandValueInfo Opd2Info, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr) const
Definition: TargetTransformInfoImpl.h:489
llvm::PatternMatch::m_Value
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:76
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::TargetTransformInfoImplBase::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned, unsigned) const
Definition: TargetTransformInfoImpl.h:104
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:778
llvm::TargetTransformInfoImplBase::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:253
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:243
llvm::TargetTransformInfoImplBase::isElementTypeLegalForScalableVector
bool isElementTypeLegalForScalableVector(Type *Ty) const
Definition: TargetTransformInfoImpl.h:805
llvm::TargetTransformInfoImplBase::getVPMemoryOpCost
InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:609
llvm::TargetTransformInfoImplBase::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: TargetTransformInfoImpl.h:829
llvm::TargetTransformInfoImplBase::getStoreMinimumVF
unsigned getStoreMinimumVF(unsigned VF, Type *, Type *) const
Definition: TargetTransformInfoImpl.h:444
llvm::TargetTransformInfoImplBase::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier() const
Definition: TargetTransformInfoImpl.h:70
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LoopInfo
Definition: LoopInfo.h:1105
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
Mul
BinaryOperator * Mul
Definition: X86PartialReduction.cpp:70
DataLayout.h
llvm::StructType
Class to represent struct types.
Definition: DerivedTypes.h:213
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::TargetTransformInfoImplBase::isLegalBroadcastLoad
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
Definition: TargetTransformInfoImpl.h:260
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:42
llvm::TargetTransformInfo::TCK_SizeAndLatency
@ TCK_SizeAndLatency
The weighted sum of size and latency.
Definition: TargetTransformInfo.h:221
llvm::TargetTransformInfoImplBase::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfoImpl.h:831
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::TargetTransformInfoImplBase::LSRWithInstrQueries
bool LSRWithInstrQueries() const
Definition: TargetTransformInfoImpl.h:311
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::TargetTransformInfoImplBase::getVScaleForTuning
Optional< unsigned > getVScaleForTuning() const
Definition: TargetTransformInfoImpl.h:432
llvm::TargetTransformInfoImplBase::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
Definition: TargetTransformInfoImpl.h:331
llvm::TargetTransformInfoImplBase::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
Definition: TargetTransformInfoImpl.h:342
llvm::TargetTransformInfoImplBase::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Definition: TargetTransformInfoImpl.h:379
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::TargetTransformInfoImplBase::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:578
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:630
llvm::TargetTransformInfoImplBase::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:242
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:429
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:174
llvm::TargetTransformInfo::SK_Transpose
@ SK_Transpose
Transpose two vectors.
Definition: TargetTransformInfo.h:890
llvm::DataLayout::isLegalInteger
bool isLegalInteger(uint64_t Width) const
Returns true if the specified type is known to be a native integer type supported by the CPU.
Definition: DataLayout.h:266
llvm::TargetTransformInfo::CacheLevel::L2D
@ L2D
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:142
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:187
llvm::APInt::getNullValue
static APInt getNullValue(unsigned numBits)
NOTE: This is soft-deprecated. Please use getZero() instead.
Definition: APInt.h:180
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:164
llvm::TargetTransformInfoImplBase::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: TargetTransformInfoImpl.h:819
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::KnownBits
Definition: KnownBits.h:23
llvm::Type::getIntNTy
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
Definition: Type.cpp:243
llvm::TargetTransformInfo::LSRCost::NumBaseAdds
unsigned NumBaseAdds
Definition: TargetTransformInfo.h:407
llvm::TargetTransformInfoImplBase::forceScalarizeMaskedGather
bool forceScalarizeMaskedGather(VectorType *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:272
llvm::TargetTransformInfoImplBase::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: TargetTransformInfoImpl.h:725
llvm::TargetTransformInfoImplBase::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const
Definition: TargetTransformInfoImpl.h:483
llvm::TargetTransformInfoImplBase::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:402
llvm::StructLayout::getElementOffset
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:652
llvm::TargetTransformInfoImplBase::getExtendedReductionCost
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:704
llvm::TargetTransformInfoImplBase::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I) const
Definition: TargetTransformInfoImpl.h:75
llvm::TargetTransformInfoImplBase::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Definition: TargetTransformInfoImpl.h:116
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:395
VPLegalization
TargetTransformInfo::VPLegalization VPLegalization
Definition: ExpandVectorPredication.cpp:35
llvm::TargetTransformInfo::getOperandInfo
static OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
Definition: TargetTransformInfo.cpp:725
llvm::APInt::sextOrTrunc
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition: APInt.cpp:1002
llvm::TargetTransformInfoImplBase::minRequiredElementSize
unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const
Definition: TargetTransformInfoImpl.h:854
llvm::TypeSize
Definition: TypeSize.h:435
llvm::SCEVAddRecExpr
This node represents a polynomial recurrence on the trip count of the specified loop.
Definition: ScalarEvolutionExpressions.h:342
llvm::TargetTransformInfoImplBase::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfoImpl.h:807
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::TargetTransformInfoImplBase::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
Definition: TargetTransformInfoImpl.h:435
llvm::TargetTransformInfoImplBase::isIndexedLoadLegal
bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
Definition: TargetTransformInfoImpl.h:774
llvm::TargetTransformInfoImplBase::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Definition: TargetTransformInfoImpl.h:478
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:222
llvm::User::operand_values
iterator_range< value_op_iterator > operand_values()
Definition: User.h:266
llvm::TargetTransformInfo::LSRCost::ImmCost
unsigned ImmCost
Definition: TargetTransformInfo.h:408
llvm::TargetTransformInfoImplBase::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const
Definition: TargetTransformInfoImpl.h:202
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:185
llvm::TargetTransformInfoImplBase::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: TargetTransformInfoImpl.h:410
llvm::PredicationStyle
PredicationStyle
Definition: TargetTransformInfo.h:165
llvm::TargetTransformInfoImplBase::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: TargetTransformInfoImpl.h:425
llvm::TargetTransformInfoImplBase::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Definition: TargetTransformInfoImpl.h:227
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfoImplBase::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: TargetTransformInfoImpl.h:175
llvm::TargetTransformInfoImplBase::DL
const DataLayout & DL
Definition: TargetTransformInfoImpl.h:37
llvm::SCEVConstant::getAPInt
const APInt & getAPInt() const
Definition: ScalarEvolutionExpressions.h:70
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:96
llvm::TargetTransformInfoImplBase::getUnrollingPreferences
void getUnrollingPreferences(Loop *, ScalarEvolution &, TTI::UnrollingPreferences &, OptimizationRemarkEmitter *) const
Definition: TargetTransformInfoImpl.h:195
llvm::TargetTransformInfoImplBase::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
Definition: TargetTransformInfoImpl.h:563
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::TargetTransformInfoImplBase::isConstantStridedAccessLessThan
bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance) const
Definition: TargetTransformInfoImpl.h:920
llvm::TargetTransformInfoImplBase::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe() const
Definition: TargetTransformInfoImpl.h:363
ScalarEvolutionExpressions.h
llvm::TargetTransformInfoImplBase::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: TargetTransformInfoImpl.h:95
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:69
llvm::TargetTransformInfoImplBase::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType) const
Definition: TargetTransformInfoImpl.h:281
llvm::TargetTransformInfoImplBase::getMinTripCountTailFoldingThreshold
unsigned getMinTripCountTailFoldingThreshold() const
Definition: TargetTransformInfoImpl.h:833
isSigned
static bool isSigned(unsigned int Opcode)
Definition: ExpandLargeDivRem.cpp:52
llvm::IntrinsicCostAttributes::getID
Intrinsic::ID getID() const
Definition: TargetTransformInfo.h:150
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:962
llvm::TargetTransformInfoImplBase::isLegalToVectorizeLoad
bool isLegalToVectorizeLoad(LoadInst *LI) const
Definition: TargetTransformInfoImpl.h:786
TargetTransformInfo.h
llvm::TargetTransformInfoImplBase::shouldPrefetchAddressSpace
bool shouldPrefetchAddressSpace(unsigned AS) const
Definition: TargetTransformInfoImpl.h:485
llvm::PatternMatch
Definition: PatternMatch.h:47
llvm::SmallVectorImpl< int >
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:71
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1174
llvm::TargetTransformInfoImplBase::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfoImpl.h:813
llvm::TargetTransformInfoImplBase::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:790
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:171
llvm::TargetTransformInfoImplBase::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:264
llvm::TargetTransformInfoImplBase::enableScalableVectorization
bool enableScalableVectorization() const
Definition: TargetTransformInfoImpl.h:837
llvm::TargetTransformInfo::TCC_Basic
@ TCC_Basic
The cost of a typical 'add' instruction.
Definition: TargetTransformInfo.h:244
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3278
llvm::OptimizedStructLayoutField
A field in a structure.
Definition: OptimizedStructLayout.h:45
llvm::TargetTransformInfoImplBase::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Definition: TargetTransformInfoImpl.h:327
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::TargetTransformInfoImplBase::emitGetActiveLaneMask
PredicationStyle emitGetActiveLaneMask() const
Definition: TargetTransformInfoImpl.h:171
llvm::TargetTransformInfoImplBase::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: TargetTransformInfoImpl.h:71
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3134
llvm::TargetTransformInfoImplBase::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:637
llvm::TargetTransformInfoImplBase::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Definition: TargetTransformInfoImpl.h:298
llvm::TargetTransformInfoImplBase::useColdCCForColdCall
bool useColdCCForColdCall(Function &F) const
Definition: TargetTransformInfoImpl.h:329
llvm::PredicationStyle::None
@ None
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:218
llvm::TargetTransformInfoImplBase::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const
Definition: TargetTransformInfoImpl.h:385
llvm::TargetTransformInfo::AMK_None
@ AMK_None
Definition: TargetTransformInfo.h:633
llvm::TargetTransformInfo::SK_ExtractSubvector
@ SK_ExtractSubvector
ExtractSubvector Index indicates start offset.
Definition: TargetTransformInfo.h:892
llvm::PatternMatch::m_LogicalAnd
LogicalOp_match< LHS, RHS, Instruction::And > m_LogicalAnd(const LHS &L, const RHS &R)
Matches L && R either in the form of L & R or L ? R : false.
Definition: PatternMatch.h:2537
llvm::codeview::PublicSymFlags::Function
@ Function
llvm::TargetTransformInfoImplBase::getPeelingPreferences
void getPeelingPreferences(Loop *, ScalarEvolution &, TTI::PeelingPreferences &) const
Definition: TargetTransformInfoImpl.h:199
llvm::SCEVAddRecExpr::getStepRecurrence
const SCEV * getStepRecurrence(ScalarEvolution &SE) const
Constructs and returns the recurrence indicating how much this expression steps by.
Definition: ScalarEvolutionExpressions.h:360
llvm::TargetTransformInfoImplBase::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: TargetTransformInfoImpl.h:443
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::DataLayout::getTypeAllocSize
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:506
llvm::TargetTransformInfoImplBase::getFPOpCost
InstructionCost getFPOpCost(Type *Ty) const
Definition: TargetTransformInfoImpl.h:381
llvm::TargetTransformInfoImplBase::areTypesABICompatible
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
Definition: TargetTransformInfoImpl.h:766
llvm::TargetTransformInfoImplBase::getRegUsageForType
unsigned getRegUsageForType(Type *Ty) const
Definition: TargetTransformInfoImpl.h:321