LLVM  13.0.0git
TargetTransformInfoImpl.h
Go to the documentation of this file.
1 //===- TargetTransformInfoImpl.h --------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file provides helpers for the implementation of
10 /// a TargetTransformInfo-conforming class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
15 #define LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
16 
20 #include "llvm/IR/DataLayout.h"
21 #include "llvm/IR/Function.h"
23 #include "llvm/IR/IntrinsicInst.h"
24 #include "llvm/IR/Operator.h"
25 #include "llvm/IR/PatternMatch.h"
26 #include "llvm/IR/Type.h"
27 
28 using namespace llvm::PatternMatch;
29 
30 namespace llvm {
31 
32 /// Base class for use as a mix-in that aids implementing
33 /// a TargetTransformInfo-compatible class.
35 protected:
37 
38  const DataLayout &DL;
39 
41 
42 public:
43  // Provide value semantics. MSVC requires that we spell all of these out.
45  : DL(Arg.DL) {}
47 
48  const DataLayout &getDataLayout() const { return DL; }
49 
50  int getGEPCost(Type *PointeeType, const Value *Ptr,
53  // In the basic model, we just assume that all-constant GEPs will be folded
54  // into their uses via addressing modes.
55  for (unsigned Idx = 0, Size = Operands.size(); Idx != Size; ++Idx)
56  if (!isa<Constant>(Operands[Idx]))
57  return TTI::TCC_Basic;
58 
59  return TTI::TCC_Free;
60  }
61 
63  unsigned &JTSize,
64  ProfileSummaryInfo *PSI,
65  BlockFrequencyInfo *BFI) const {
66  (void)PSI;
67  (void)BFI;
68  JTSize = 0;
69  return SI.getNumCases();
70  }
71 
72  unsigned getInliningThresholdMultiplier() const { return 1; }
73  unsigned adjustInliningThreshold(const CallBase *CB) const { return 0; }
74 
75  int getInlinerVectorBonusPercent() const { return 150; }
76 
77  unsigned getMemcpyCost(const Instruction *I) const {
78  return TTI::TCC_Expensive;
79  }
80 
81  // Although this default value is arbitrary, it is not random. It is assumed
82  // that a condition that evaluates the same way by a higher percentage than
83  // this is best represented as control flow. Therefore, the default value N
84  // should be set such that the win from N% correct executions is greater than
85  // the loss from (100 - N)% mispredicted executions for the majority of
86  // intended targets.
88  return BranchProbability(99, 100);
89  }
90 
91  bool hasBranchDivergence() const { return false; }
92 
93  bool useGPUDivergenceAnalysis() const { return false; }
94 
95  bool isSourceOfDivergence(const Value *V) const { return false; }
96 
97  bool isAlwaysUniform(const Value *V) const { return false; }
98 
99  unsigned getFlatAddressSpace() const { return -1; }
100 
102  Intrinsic::ID IID) const {
103  return false;
104  }
105 
106  bool isNoopAddrSpaceCast(unsigned, unsigned) const { return false; }
107 
108  unsigned getAssumedAddrSpace(const Value *V) const { return -1; }
109 
111  Value *NewV) const {
112  return nullptr;
113  }
114 
115  bool isLoweredToCall(const Function *F) const {
116  assert(F && "A concrete function must be provided to this routine.");
117 
118  // FIXME: These should almost certainly not be handled here, and instead
119  // handled with the help of TLI or the target itself. This was largely
120  // ported from existing analysis heuristics here so that such refactorings
121  // can take place in the future.
122 
123  if (F->isIntrinsic())
124  return false;
125 
126  if (F->hasLocalLinkage() || !F->hasName())
127  return true;
128 
129  StringRef Name = F->getName();
130 
131  // These will all likely lower to a single selection DAG node.
132  if (Name == "copysign" || Name == "copysignf" || Name == "copysignl" ||
133  Name == "fabs" || Name == "fabsf" || Name == "fabsl" || Name == "sin" ||
134  Name == "fmin" || Name == "fminf" || Name == "fminl" ||
135  Name == "fmax" || Name == "fmaxf" || Name == "fmaxl" ||
136  Name == "sinf" || Name == "sinl" || Name == "cos" || Name == "cosf" ||
137  Name == "cosl" || Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl")
138  return false;
139 
140  // These are all likely to be optimized into something smaller.
141  if (Name == "pow" || Name == "powf" || Name == "powl" || Name == "exp2" ||
142  Name == "exp2l" || Name == "exp2f" || Name == "floor" ||
143  Name == "floorf" || Name == "ceil" || Name == "round" ||
144  Name == "ffs" || Name == "ffsl" || Name == "abs" || Name == "labs" ||
145  Name == "llabs")
146  return false;
147 
148  return true;
149  }
150 
152  AssumptionCache &AC, TargetLibraryInfo *LibInfo,
153  HardwareLoopInfo &HWLoopInfo) const {
154  return false;
155  }
156 
159  DominatorTree *DT,
160  const LoopAccessInfo *LAI) const {
161  return false;
162  }
163 
164  bool emitGetActiveLaneMask() const {
165  return false;
166  }
167 
169  IntrinsicInst &II) const {
170  return None;
171  }
172 
175  APInt DemandedMask, KnownBits &Known,
176  bool &KnownBitsComputed) const {
177  return None;
178  }
179 
181  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
182  APInt &UndefElts2, APInt &UndefElts3,
183  std::function<void(Instruction *, unsigned, APInt, APInt &)>
184  SimplifyAndSetOp) const {
185  return None;
186  }
187 
189  TTI::UnrollingPreferences &) const {}
190 
192  TTI::PeelingPreferences &) const {}
193 
194  bool isLegalAddImmediate(int64_t Imm) const { return false; }
195 
196  bool isLegalICmpImmediate(int64_t Imm) const { return false; }
197 
198  bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
199  bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
200  Instruction *I = nullptr) const {
201  // Guess that only reg and reg+reg addressing is allowed. This heuristic is
202  // taken from the implementation of LSR.
203  return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1);
204  }
205 
207  return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds,
208  C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
209  std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds,
210  C2.ScaleCost, C2.ImmCost, C2.SetupCost);
211  }
212 
213  bool isNumRegsMajorCostOfLSR() const { return true; }
214 
215  bool isProfitableLSRChainElement(Instruction *I) const { return false; }
216 
217  bool canMacroFuseCmp() const { return false; }
218 
221  TargetLibraryInfo *LibInfo) const {
222  return false;
223  }
224 
227  return TTI::AMK_None;
228  }
229 
230  bool isLegalMaskedStore(Type *DataType, Align Alignment) const {
231  return false;
232  }
233 
234  bool isLegalMaskedLoad(Type *DataType, Align Alignment) const {
235  return false;
236  }
237 
238  bool isLegalNTStore(Type *DataType, Align Alignment) const {
239  // By default, assume nontemporal memory stores are available for stores
240  // that are aligned and have a size that is a power of 2.
241  unsigned DataSize = DL.getTypeStoreSize(DataType);
242  return Alignment >= DataSize && isPowerOf2_32(DataSize);
243  }
244 
245  bool isLegalNTLoad(Type *DataType, Align Alignment) const {
246  // By default, assume nontemporal memory loads are available for loads that
247  // are aligned and have a size that is a power of 2.
248  unsigned DataSize = DL.getTypeStoreSize(DataType);
249  return Alignment >= DataSize && isPowerOf2_32(DataSize);
250  }
251 
252  bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
253  return false;
254  }
255 
256  bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
257  return false;
258  }
259 
260  bool isLegalMaskedCompressStore(Type *DataType) const { return false; }
261 
262  bool isLegalMaskedExpandLoad(Type *DataType) const { return false; }
263 
264  bool hasDivRemOp(Type *DataType, bool IsSigned) const { return false; }
265 
266  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const {
267  return false;
268  }
269 
270  bool prefersVectorizedAddressing() const { return true; }
271 
272  int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
273  bool HasBaseReg, int64_t Scale,
274  unsigned AddrSpace) const {
275  // Guess that all legal addressing mode are free.
276  if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
277  AddrSpace))
278  return 0;
279  return -1;
280  }
281 
282  bool LSRWithInstrQueries() const { return false; }
283 
284  bool isTruncateFree(Type *Ty1, Type *Ty2) const { return false; }
285 
286  bool isProfitableToHoist(Instruction *I) const { return true; }
287 
288  bool useAA() const { return false; }
289 
290  bool isTypeLegal(Type *Ty) const { return false; }
291 
292  unsigned getRegUsageForType(Type *Ty) const { return 1; }
293 
294  bool shouldBuildLookupTables() const { return true; }
295 
296  bool shouldBuildLookupTablesForConstant(Constant *C) const { return true; }
297 
298  bool shouldBuildRelLookupTables() const { return false; }
299 
300  bool useColdCCForColdCall(Function &F) const { return false; }
301 
302  unsigned getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts,
303  bool Insert, bool Extract) const {
304  return 0;
305  }
306 
308  ArrayRef<Type *> Tys) const {
309  return 0;
310  }
311 
312  bool supportsEfficientVectorElementLoadStore() const { return false; }
313 
314  bool enableAggressiveInterleaving(bool LoopHasReductions) const {
315  return false;
316  }
317 
319  bool IsZeroCmp) const {
320  return {};
321  }
322 
323  bool enableInterleavedAccessVectorization() const { return false; }
324 
325  bool enableMaskedInterleavedAccessVectorization() const { return false; }
326 
327  bool isFPVectorizationPotentiallyUnsafe() const { return false; }
328 
330  unsigned AddressSpace, Align Alignment,
331  bool *Fast) const {
332  return false;
333  }
334 
335  TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const {
336  return TTI::PSK_Software;
337  }
338 
339  bool haveFastSqrt(Type *Ty) const { return false; }
340 
341  bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { return true; }
342 
343  unsigned getFPOpCost(Type *Ty) const {
345  }
346 
347  int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
348  Type *Ty) const {
349  return 0;
350  }
351 
352  unsigned getIntImmCost(const APInt &Imm, Type *Ty,
354  return TTI::TCC_Basic;
355  }
356 
357  unsigned getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
359  Instruction *Inst = nullptr) const {
360  return TTI::TCC_Free;
361  }
362 
363  unsigned getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
364  const APInt &Imm, Type *Ty,
366  return TTI::TCC_Free;
367  }
368 
369  unsigned getNumberOfRegisters(unsigned ClassID) const { return 8; }
370 
371  unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
372  return Vector ? 1 : 0;
373  };
374 
375  const char *getRegisterClassName(unsigned ClassID) const {
376  switch (ClassID) {
377  default:
378  return "Generic::Unknown Register Class";
379  case 0:
380  return "Generic::ScalarRC";
381  case 1:
382  return "Generic::VectorRC";
383  }
384  }
385 
387  return TypeSize::getFixed(32);
388  }
389 
390  unsigned getMinVectorRegisterBitWidth() const { return 128; }
391 
393 
394  bool shouldMaximizeVectorBandwidth(bool OptSize) const { return false; }
395 
396  ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const {
397  return ElementCount::get(0, IsScalable);
398  }
399 
400  unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const { return 0; }
401 
403  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
404  AllowPromotionWithoutCommonHeader = false;
405  return false;
406  }
407 
408  unsigned getCacheLineSize() const { return 0; }
409 
412  switch (Level) {
416  return llvm::Optional<unsigned>();
417  }
418  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
419  }
420 
423  switch (Level) {
427  return llvm::Optional<unsigned>();
428  }
429 
430  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
431  }
432 
433  unsigned getPrefetchDistance() const { return 0; }
434  unsigned getMinPrefetchStride(unsigned NumMemAccesses,
435  unsigned NumStridedMemAccesses,
436  unsigned NumPrefetches, bool HasCall) const {
437  return 1;
438  }
439  unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; }
440  bool enableWritePrefetching() const { return false; }
441 
442  unsigned getMaxInterleaveFactor(unsigned VF) const { return 1; }
443 
444  unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
446  TTI::OperandValueKind Opd1Info,
447  TTI::OperandValueKind Opd2Info,
448  TTI::OperandValueProperties Opd1PropInfo,
449  TTI::OperandValueProperties Opd2PropInfo,
451  const Instruction *CxtI = nullptr) const {
452  // FIXME: A number of transformation tests seem to require these values
453  // which seems a little odd for how arbitary there are.
454  switch (Opcode) {
455  default:
456  break;
457  case Instruction::FDiv:
458  case Instruction::FRem:
459  case Instruction::SDiv:
460  case Instruction::SRem:
461  case Instruction::UDiv:
462  case Instruction::URem:
463  // FIXME: Unlikely to be true for CodeSize.
464  return TTI::TCC_Expensive;
465  }
466  return 1;
467  }
468 
470  ArrayRef<int> Mask, int Index,
471  VectorType *SubTp) const {
472  return 1;
473  }
474 
475  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
478  const Instruction *I) const {
479  switch (Opcode) {
480  default:
481  break;
482  case Instruction::IntToPtr: {
483  unsigned SrcSize = Src->getScalarSizeInBits();
484  if (DL.isLegalInteger(SrcSize) &&
485  SrcSize <= DL.getPointerTypeSizeInBits(Dst))
486  return 0;
487  break;
488  }
489  case Instruction::PtrToInt: {
490  unsigned DstSize = Dst->getScalarSizeInBits();
491  if (DL.isLegalInteger(DstSize) &&
492  DstSize >= DL.getPointerTypeSizeInBits(Src))
493  return 0;
494  break;
495  }
496  case Instruction::BitCast:
497  if (Dst == Src || (Dst->isPointerTy() && Src->isPointerTy()))
498  // Identity and pointer-to-pointer casts are free.
499  return 0;
500  break;
501  case Instruction::Trunc: {
502  // trunc to a native type is free (assuming the target has compare and
503  // shift-right of the same width).
504  TypeSize DstSize = DL.getTypeSizeInBits(Dst);
505  if (!DstSize.isScalable() && DL.isLegalInteger(DstSize.getFixedSize()))
506  return 0;
507  break;
508  }
509  }
510  return 1;
511  }
512 
514  VectorType *VecTy,
515  unsigned Index) const {
516  return 1;
517  }
518 
519  unsigned getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
520  const Instruction *I = nullptr) const {
521  // A phi would be free, unless we're costing the throughput because it
522  // will require a register.
523  if (Opcode == Instruction::PHI && CostKind != TTI::TCK_RecipThroughput)
524  return 0;
525  return 1;
526  }
527 
528  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
529  CmpInst::Predicate VecPred,
531  const Instruction *I) const {
532  return 1;
533  }
534 
535  unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
536  unsigned Index) const {
537  return 1;
538  }
539 
540  InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
541  unsigned AddressSpace,
543  const Instruction *I) const {
544  return 1;
545  }
546 
548  Align Alignment, unsigned AddressSpace,
550  return 1;
551  }
552 
553  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
554  const Value *Ptr, bool VariableMask,
555  Align Alignment,
557  const Instruction *I = nullptr) const {
558  return 1;
559  }
560 
562  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
563  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
564  bool UseMaskForCond, bool UseMaskForGaps) const {
565  return 1;
566  }
567 
570  switch (ICA.getID()) {
571  default:
572  break;
573  case Intrinsic::annotation:
574  case Intrinsic::assume:
575  case Intrinsic::sideeffect:
576  case Intrinsic::pseudoprobe:
577  case Intrinsic::dbg_declare:
578  case Intrinsic::dbg_value:
579  case Intrinsic::dbg_label:
580  case Intrinsic::invariant_start:
581  case Intrinsic::invariant_end:
582  case Intrinsic::launder_invariant_group:
583  case Intrinsic::strip_invariant_group:
584  case Intrinsic::is_constant:
585  case Intrinsic::lifetime_start:
586  case Intrinsic::lifetime_end:
587  case Intrinsic::experimental_noalias_scope_decl:
588  case Intrinsic::objectsize:
589  case Intrinsic::ptr_annotation:
590  case Intrinsic::var_annotation:
591  case Intrinsic::experimental_gc_result:
592  case Intrinsic::experimental_gc_relocate:
593  case Intrinsic::coro_alloc:
594  case Intrinsic::coro_begin:
595  case Intrinsic::coro_free:
596  case Intrinsic::coro_end:
597  case Intrinsic::coro_frame:
598  case Intrinsic::coro_size:
599  case Intrinsic::coro_suspend:
600  case Intrinsic::coro_param:
601  case Intrinsic::coro_subfn_addr:
602  // These intrinsics don't actually represent code after lowering.
603  return 0;
604  }
605  return 1;
606  }
607 
610  return 1;
611  }
612 
613  unsigned getNumberOfParts(Type *Tp) const { return 0; }
614 
616  const SCEV *) const {
617  return 0;
618  }
619 
621  TTI::TargetCostKind) const {
622  return 1;
623  }
624 
626  TTI::TargetCostKind) const {
627  return 1;
628  }
629 
631  bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty,
633  return 1;
634  }
635 
637  return 0;
638  }
639 
641  return false;
642  }
643 
645  // Note for overrides: You must ensure for all element unordered-atomic
646  // memory intrinsics that all power-of-2 element sizes up to, and
647  // including, the return value of this method have a corresponding
648  // runtime lib call. These runtime lib call definitions can be found
649  // in RuntimeLibcalls.h
650  return 0;
651  }
652 
654  Type *ExpectedType) const {
655  return nullptr;
656  }
657 
659  unsigned SrcAddrSpace, unsigned DestAddrSpace,
660  unsigned SrcAlign, unsigned DestAlign) const {
661  return Type::getInt8Ty(Context);
662  }
663 
666  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
667  unsigned SrcAlign, unsigned DestAlign) const {
668  for (unsigned i = 0; i != RemainingBytes; ++i)
669  OpsOut.push_back(Type::getInt8Ty(Context));
670  }
671 
672  bool areInlineCompatible(const Function *Caller,
673  const Function *Callee) const {
674  return (Caller->getFnAttribute("target-cpu") ==
675  Callee->getFnAttribute("target-cpu")) &&
676  (Caller->getFnAttribute("target-features") ==
677  Callee->getFnAttribute("target-features"));
678  }
679 
681  const Function *Callee,
683  return (Caller->getFnAttribute("target-cpu") ==
684  Callee->getFnAttribute("target-cpu")) &&
685  (Caller->getFnAttribute("target-features") ==
686  Callee->getFnAttribute("target-features"));
687  }
688 
690  const DataLayout &DL) const {
691  return false;
692  }
693 
695  const DataLayout &DL) const {
696  return false;
697  }
698 
699  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { return 128; }
700 
701  bool isLegalToVectorizeLoad(LoadInst *LI) const { return true; }
702 
703  bool isLegalToVectorizeStore(StoreInst *SI) const { return true; }
704 
705  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
706  unsigned AddrSpace) const {
707  return true;
708  }
709 
710  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
711  unsigned AddrSpace) const {
712  return true;
713  }
714 
716  ElementCount VF) const {
717  return true;
718  }
719 
720  unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
721  unsigned ChainSizeInBytes,
722  VectorType *VecTy) const {
723  return VF;
724  }
725 
726  unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
727  unsigned ChainSizeInBytes,
728  VectorType *VecTy) const {
729  return VF;
730  }
731 
732  bool preferInLoopReduction(unsigned Opcode, Type *Ty,
733  TTI::ReductionFlags Flags) const {
734  return false;
735  }
736 
737  bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
738  TTI::ReductionFlags Flags) const {
739  return false;
740  }
741 
742  bool shouldExpandReduction(const IntrinsicInst *II) const { return true; }
743 
744  unsigned getGISelRematGlobalCost() const { return 1; }
745 
746  bool supportsScalableVectors() const { return false; }
747 
748  bool hasActiveVectorLength() const { return false; }
749 
750 protected:
751  // Obtain the minimum required size to hold the value (without the sign)
752  // In case of a vector it returns the min required size for one element.
753  unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const {
754  if (isa<ConstantDataVector>(Val) || isa<ConstantVector>(Val)) {
755  const auto *VectorValue = cast<Constant>(Val);
756 
757  // In case of a vector need to pick the max between the min
758  // required size for each element
759  auto *VT = cast<FixedVectorType>(Val->getType());
760 
761  // Assume unsigned elements
762  isSigned = false;
763 
764  // The max required size is the size of the vector element type
765  unsigned MaxRequiredSize =
766  VT->getElementType()->getPrimitiveSizeInBits().getFixedSize();
767 
768  unsigned MinRequiredSize = 0;
769  for (unsigned i = 0, e = VT->getNumElements(); i < e; ++i) {
770  if (auto *IntElement =
771  dyn_cast<ConstantInt>(VectorValue->getAggregateElement(i))) {
772  bool signedElement = IntElement->getValue().isNegative();
773  // Get the element min required size.
774  unsigned ElementMinRequiredSize =
775  IntElement->getValue().getMinSignedBits() - 1;
776  // In case one element is signed then all the vector is signed.
777  isSigned |= signedElement;
778  // Save the max required bit size between all the elements.
779  MinRequiredSize = std::max(MinRequiredSize, ElementMinRequiredSize);
780  } else {
781  // not an int constant element
782  return MaxRequiredSize;
783  }
784  }
785  return MinRequiredSize;
786  }
787 
788  if (const auto *CI = dyn_cast<ConstantInt>(Val)) {
789  isSigned = CI->getValue().isNegative();
790  return CI->getValue().getMinSignedBits() - 1;
791  }
792 
793  if (const auto *Cast = dyn_cast<SExtInst>(Val)) {
794  isSigned = true;
795  return Cast->getSrcTy()->getScalarSizeInBits() - 1;
796  }
797 
798  if (const auto *Cast = dyn_cast<ZExtInst>(Val)) {
799  isSigned = false;
800  return Cast->getSrcTy()->getScalarSizeInBits();
801  }
802 
803  isSigned = false;
804  return Val->getType()->getScalarSizeInBits();
805  }
806 
807  bool isStridedAccess(const SCEV *Ptr) const {
808  return Ptr && isa<SCEVAddRecExpr>(Ptr);
809  }
810 
812  const SCEV *Ptr) const {
813  if (!isStridedAccess(Ptr))
814  return nullptr;
815  const SCEVAddRecExpr *AddRec = cast<SCEVAddRecExpr>(Ptr);
816  return dyn_cast<SCEVConstant>(AddRec->getStepRecurrence(*SE));
817  }
818 
820  int64_t MergeDistance) const {
821  const SCEVConstant *Step = getConstantStrideStep(SE, Ptr);
822  if (!Step)
823  return false;
824  APInt StrideVal = Step->getAPInt();
825  if (StrideVal.getBitWidth() > 64)
826  return false;
827  // FIXME: Need to take absolute value for negative stride case.
828  return StrideVal.getSExtValue() < MergeDistance;
829  }
830 };
831 
832 /// CRTP base class for use as a mix-in that aids implementing
833 /// a TargetTransformInfo-compatible class.
834 template <typename T>
836 private:
838 
839 protected:
841 
842 public:
843  using BaseT::getGEPCost;
844 
845  int getGEPCost(Type *PointeeType, const Value *Ptr,
848  assert(PointeeType && Ptr && "can't get GEPCost of nullptr");
849  // TODO: will remove this when pointers have an opaque type.
851  PointeeType &&
852  "explicit pointee type doesn't match operand's pointee type");
853  auto *BaseGV = dyn_cast<GlobalValue>(Ptr->stripPointerCasts());
854  bool HasBaseReg = (BaseGV == nullptr);
855 
856  auto PtrSizeBits = DL.getPointerTypeSizeInBits(Ptr->getType());
857  APInt BaseOffset(PtrSizeBits, 0);
858  int64_t Scale = 0;
859 
860  auto GTI = gep_type_begin(PointeeType, Operands);
861  Type *TargetType = nullptr;
862 
863  // Handle the case where the GEP instruction has a single operand,
864  // the basis, therefore TargetType is a nullptr.
865  if (Operands.empty())
866  return !BaseGV ? TTI::TCC_Free : TTI::TCC_Basic;
867 
868  for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) {
869  TargetType = GTI.getIndexedType();
870  // We assume that the cost of Scalar GEP with constant index and the
871  // cost of Vector GEP with splat constant index are the same.
872  const ConstantInt *ConstIdx = dyn_cast<ConstantInt>(*I);
873  if (!ConstIdx)
874  if (auto Splat = getSplatValue(*I))
875  ConstIdx = dyn_cast<ConstantInt>(Splat);
876  if (StructType *STy = GTI.getStructTypeOrNull()) {
877  // For structures the index is always splat or scalar constant
878  assert(ConstIdx && "Unexpected GEP index");
879  uint64_t Field = ConstIdx->getZExtValue();
880  BaseOffset += DL.getStructLayout(STy)->getElementOffset(Field);
881  } else {
882  // If this operand is a scalable type, bail out early.
883  // TODO: handle scalable vectors
884  if (isa<ScalableVectorType>(TargetType))
885  return TTI::TCC_Basic;
886  int64_t ElementSize =
887  DL.getTypeAllocSize(GTI.getIndexedType()).getFixedSize();
888  if (ConstIdx) {
889  BaseOffset +=
890  ConstIdx->getValue().sextOrTrunc(PtrSizeBits) * ElementSize;
891  } else {
892  // Needs scale register.
893  if (Scale != 0)
894  // No addressing mode takes two scale registers.
895  return TTI::TCC_Basic;
896  Scale = ElementSize;
897  }
898  }
899  }
900 
901  if (static_cast<T *>(this)->isLegalAddressingMode(
902  TargetType, const_cast<GlobalValue *>(BaseGV),
903  BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale,
904  Ptr->getType()->getPointerAddressSpace()))
905  return TTI::TCC_Free;
906  return TTI::TCC_Basic;
907  }
908 
911  auto *TargetTTI = static_cast<T *>(this);
912  // Handle non-intrinsic calls, invokes, and callbr.
913  // FIXME: Unlikely to be true for anything but CodeSize.
914  auto *CB = dyn_cast<CallBase>(U);
915  if (CB && !isa<IntrinsicInst>(U)) {
916  if (const Function *F = CB->getCalledFunction()) {
917  if (!TargetTTI->isLoweredToCall(F))
918  return TTI::TCC_Basic; // Give a basic cost if it will be lowered
919 
920  return TTI::TCC_Basic * (F->getFunctionType()->getNumParams() + 1);
921  }
922  // For indirect or other calls, scale cost by number of arguments.
923  return TTI::TCC_Basic * (CB->arg_size() + 1);
924  }
925 
926  Type *Ty = U->getType();
927  Type *OpTy =
928  U->getNumOperands() == 1 ? U->getOperand(0)->getType() : nullptr;
929  unsigned Opcode = Operator::getOpcode(U);
930  auto *I = dyn_cast<Instruction>(U);
931  switch (Opcode) {
932  default:
933  break;
934  case Instruction::Call: {
935  assert(isa<IntrinsicInst>(U) && "Unexpected non-intrinsic call");
936  auto *Intrinsic = cast<IntrinsicInst>(U);
937  IntrinsicCostAttributes CostAttrs(Intrinsic->getIntrinsicID(), *CB);
938  return TargetTTI->getIntrinsicInstrCost(CostAttrs, CostKind);
939  }
940  case Instruction::Br:
941  case Instruction::Ret:
942  case Instruction::PHI:
943  case Instruction::Switch:
944  return TargetTTI->getCFInstrCost(Opcode, CostKind, I);
945  case Instruction::ExtractValue:
946  case Instruction::Freeze:
947  return TTI::TCC_Free;
948  case Instruction::Alloca:
949  if (cast<AllocaInst>(U)->isStaticAlloca())
950  return TTI::TCC_Free;
951  break;
952  case Instruction::GetElementPtr: {
953  const GEPOperator *GEP = cast<GEPOperator>(U);
954  return TargetTTI->getGEPCost(GEP->getSourceElementType(),
955  GEP->getPointerOperand(),
956  Operands.drop_front());
957  }
958  case Instruction::Add:
959  case Instruction::FAdd:
960  case Instruction::Sub:
961  case Instruction::FSub:
962  case Instruction::Mul:
963  case Instruction::FMul:
964  case Instruction::UDiv:
965  case Instruction::SDiv:
966  case Instruction::FDiv:
967  case Instruction::URem:
968  case Instruction::SRem:
969  case Instruction::FRem:
970  case Instruction::Shl:
971  case Instruction::LShr:
972  case Instruction::AShr:
973  case Instruction::And:
974  case Instruction::Or:
975  case Instruction::Xor:
976  case Instruction::FNeg: {
979  TTI::OperandValueKind Op1VK =
980  TTI::getOperandInfo(U->getOperand(0), Op1VP);
981  TTI::OperandValueKind Op2VK = Opcode != Instruction::FNeg ?
984  return TargetTTI->getArithmeticInstrCost(Opcode, Ty, CostKind,
985  Op1VK, Op2VK,
986  Op1VP, Op2VP, Operands, I);
987  }
988  case Instruction::IntToPtr:
989  case Instruction::PtrToInt:
990  case Instruction::SIToFP:
991  case Instruction::UIToFP:
992  case Instruction::FPToUI:
993  case Instruction::FPToSI:
994  case Instruction::Trunc:
995  case Instruction::FPTrunc:
996  case Instruction::BitCast:
997  case Instruction::FPExt:
998  case Instruction::SExt:
999  case Instruction::ZExt:
1000  case Instruction::AddrSpaceCast:
1001  return TargetTTI->getCastInstrCost(
1002  Opcode, Ty, OpTy, TTI::getCastContextHint(I), CostKind, I);
1003  case Instruction::Store: {
1004  auto *SI = cast<StoreInst>(U);
1005  Type *ValTy = U->getOperand(0)->getType();
1006  return TargetTTI->getMemoryOpCost(Opcode, ValTy, SI->getAlign(),
1007  SI->getPointerAddressSpace(),
1008  CostKind, I);
1009  }
1010  case Instruction::Load: {
1011  auto *LI = cast<LoadInst>(U);
1012  return TargetTTI->getMemoryOpCost(Opcode, U->getType(), LI->getAlign(),
1013  LI->getPointerAddressSpace(),
1014  CostKind, I);
1015  }
1016  case Instruction::Select: {
1017  const Value *Op0, *Op1;
1018  if (match(U, m_LogicalAnd(m_Value(Op0), m_Value(Op1))) ||
1019  match(U, m_LogicalOr(m_Value(Op0), m_Value(Op1)))) {
1020  // select x, y, false --> x & y
1021  // select x, true, y --> x | y
1024  TTI::OperandValueKind Op1VK = TTI::getOperandInfo(Op0, Op1VP);
1025  TTI::OperandValueKind Op2VK = TTI::getOperandInfo(Op1, Op2VP);
1026  assert(Op0->getType()->getScalarSizeInBits() == 1 &&
1027  Op1->getType()->getScalarSizeInBits() == 1);
1028 
1030  return TargetTTI->getArithmeticInstrCost(
1031  match(U, m_LogicalOr()) ? Instruction::Or : Instruction::And, Ty,
1032  CostKind, Op1VK, Op2VK, Op1VP, Op2VP, Operands, I);
1033  }
1034  Type *CondTy = U->getOperand(0)->getType();
1035  return TargetTTI->getCmpSelInstrCost(Opcode, U->getType(), CondTy,
1037  CostKind, I);
1038  }
1039  case Instruction::ICmp:
1040  case Instruction::FCmp: {
1041  Type *ValTy = U->getOperand(0)->getType();
1042  // TODO: Also handle ICmp/FCmp constant expressions.
1043  return TargetTTI->getCmpSelInstrCost(Opcode, ValTy, U->getType(),
1044  I ? cast<CmpInst>(I)->getPredicate()
1046  CostKind, I);
1047  }
1048  case Instruction::InsertElement: {
1049  auto *IE = dyn_cast<InsertElementInst>(U);
1050  if (!IE)
1051  return TTI::TCC_Basic; // FIXME
1052  auto *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1053  unsigned Idx = CI ? CI->getZExtValue() : -1;
1054  return TargetTTI->getVectorInstrCost(Opcode, Ty, Idx);
1055  }
1056  case Instruction::ShuffleVector: {
1057  auto *Shuffle = dyn_cast<ShuffleVectorInst>(U);
1058  if (!Shuffle)
1059  return TTI::TCC_Basic; // FIXME
1060  auto *VecTy = cast<VectorType>(U->getType());
1061  auto *VecSrcTy = cast<VectorType>(U->getOperand(0)->getType());
1062 
1063  // TODO: Identify and add costs for insert subvector, etc.
1064  int SubIndex;
1065  if (Shuffle->isExtractSubvectorMask(SubIndex))
1066  return TargetTTI->getShuffleCost(TTI::SK_ExtractSubvector, VecSrcTy,
1067  Shuffle->getShuffleMask(), SubIndex,
1068  VecTy);
1069  else if (Shuffle->changesLength())
1070  return CostKind == TTI::TCK_RecipThroughput ? -1 : 1;
1071  else if (Shuffle->isIdentity())
1072  return 0;
1073  else if (Shuffle->isReverse())
1074  return TargetTTI->getShuffleCost(TTI::SK_Reverse, VecTy,
1075  Shuffle->getShuffleMask(), 0, nullptr);
1076  else if (Shuffle->isSelect())
1077  return TargetTTI->getShuffleCost(TTI::SK_Select, VecTy,
1078  Shuffle->getShuffleMask(), 0, nullptr);
1079  else if (Shuffle->isTranspose())
1080  return TargetTTI->getShuffleCost(TTI::SK_Transpose, VecTy,
1081  Shuffle->getShuffleMask(), 0, nullptr);
1082  else if (Shuffle->isZeroEltSplat())
1083  return TargetTTI->getShuffleCost(TTI::SK_Broadcast, VecTy,
1084  Shuffle->getShuffleMask(), 0, nullptr);
1085  else if (Shuffle->isSingleSource())
1086  return TargetTTI->getShuffleCost(TTI::SK_PermuteSingleSrc, VecTy,
1087  Shuffle->getShuffleMask(), 0, nullptr);
1088 
1089  return TargetTTI->getShuffleCost(TTI::SK_PermuteTwoSrc, VecTy,
1090  Shuffle->getShuffleMask(), 0, nullptr);
1091  }
1092  case Instruction::ExtractElement: {
1093  unsigned Idx = -1;
1094  auto *EEI = dyn_cast<ExtractElementInst>(U);
1095  if (!EEI)
1096  return TTI::TCC_Basic; // FIXME
1097 
1098  auto *CI = dyn_cast<ConstantInt>(EEI->getOperand(1));
1099  if (CI)
1100  Idx = CI->getZExtValue();
1101 
1102  // Try to match a reduction (a series of shufflevector and vector ops
1103  // followed by an extractelement).
1104  unsigned RdxOpcode;
1105  VectorType *RdxType;
1106  bool IsPairwise;
1107  switch (TTI::matchVectorReduction(EEI, RdxOpcode, RdxType, IsPairwise)) {
1108  case TTI::RK_Arithmetic:
1109  return TargetTTI->getArithmeticReductionCost(RdxOpcode, RdxType,
1110  IsPairwise, CostKind);
1111  case TTI::RK_MinMax:
1112  return TargetTTI->getMinMaxReductionCost(
1113  RdxType, cast<VectorType>(CmpInst::makeCmpResultType(RdxType)),
1114  IsPairwise, /*IsUnsigned=*/false, CostKind);
1116  return TargetTTI->getMinMaxReductionCost(
1117  RdxType, cast<VectorType>(CmpInst::makeCmpResultType(RdxType)),
1118  IsPairwise, /*IsUnsigned=*/true, CostKind);
1119  case TTI::RK_None:
1120  break;
1121  }
1122  return TargetTTI->getVectorInstrCost(Opcode, U->getOperand(0)->getType(),
1123  Idx);
1124  }
1125  }
1126  // By default, just classify everything as 'basic'.
1127  return TTI::TCC_Basic;
1128  }
1129 
1131  SmallVector<const Value *, 4> Operands(I->operand_values());
1132  if (getUserCost(I, Operands, TTI::TCK_Latency) == TTI::TCC_Free)
1133  return 0;
1134 
1135  if (isa<LoadInst>(I))
1136  return 4;
1137 
1138  Type *DstTy = I->getType();
1139 
1140  // Usually an intrinsic is a simple instruction.
1141  // A real function call is much slower.
1142  if (auto *CI = dyn_cast<CallInst>(I)) {
1143  const Function *F = CI->getCalledFunction();
1144  if (!F || static_cast<T *>(this)->isLoweredToCall(F))
1145  return 40;
1146  // Some intrinsics return a value and a flag, we use the value type
1147  // to decide its latency.
1148  if (StructType *StructTy = dyn_cast<StructType>(DstTy))
1149  DstTy = StructTy->getElementType(0);
1150  // Fall through to simple instructions.
1151  }
1152 
1153  if (VectorType *VectorTy = dyn_cast<VectorType>(DstTy))
1154  DstTy = VectorTy->getElementType();
1155  if (DstTy->isFloatingPointTy())
1156  return 3;
1157 
1158  return 1;
1159  }
1160 };
1161 } // namespace llvm
1162 
1163 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
llvm::InstructionCost
Definition: InstructionCost.h:26
llvm::TargetTransformInfo::CacheLevel::L1D
@ L1D
llvm::EngineKind::Kind
Kind
Definition: ExecutionEngine.h:524
llvm::orc::BaseT
RTTIExtends< ObjectLinkingLayer, ObjectLayer > BaseT
Definition: ObjectLinkingLayer.cpp:471
llvm::TargetTransformInfoImplBase::getCacheLineSize
unsigned getCacheLineSize() const
Definition: TargetTransformInfoImpl.h:408
llvm::TargetTransformInfo::SK_Select
@ SK_Select
Selects elements from the corresponding lane of either source operand.
Definition: TargetTransformInfo.h:848
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm::TargetTransformInfoImplBase::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Definition: TargetTransformInfoImpl.h:151
llvm::TargetTransformInfo::LSRCost::NumRegs
unsigned NumRegs
Definition: TargetTransformInfo.h:413
llvm::TargetTransformInfo::TCC_Expensive
@ TCC_Expensive
The cost of a 'div' instruction on x86.
Definition: TargetTransformInfo.h:264
llvm
Definition: AllocatorList.h:23
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1331
llvm::TargetTransformInfoImplBase::getCallInstrCost
unsigned getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:608
llvm::TargetTransformInfoImplCRTPBase::getGEPCost
int getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency)
Definition: TargetTransformInfoImpl.h:845
llvm::TargetTransformInfoImplBase::useAA
bool useAA() const
Definition: TargetTransformInfoImpl.h:288
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::TargetTransformInfoImplBase::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, const LoopAccessInfo *LAI) const
Definition: TargetTransformInfoImpl.h:157
llvm::TargetTransformInfo::MemIndexedMode
MemIndexedMode
The type of load/store indexing.
Definition: TargetTransformInfo.h:1282
llvm::TargetTransformInfo::TCK_Latency
@ TCK_Latency
The latency of instruction.
Definition: TargetTransformInfo.h:213
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:722
llvm::TargetTransformInfoImplBase::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const
Definition: TargetTransformInfoImpl.h:108
llvm::TargetTransformInfoImplBase::isStridedAccess
bool isStridedAccess(const SCEV *Ptr) const
Definition: TargetTransformInfoImpl.h:807
IntrinsicInst.h
llvm::Type::isPointerTy
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:229
llvm::ElementCount
Definition: TypeSize.h:386
llvm::TargetTransformInfoImplBase::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: TargetTransformInfoImpl.h:392
llvm::TargetTransformInfoImplBase::getIntImmCostIntrin
unsigned getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:363
llvm::TypeSize::getFixedSize
ScalarTy getFixedSize() const
Definition: TypeSize.h:426
llvm::Function
Definition: Function.h:61
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:529
llvm::TargetTransformInfoImplBase::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const
Definition: TargetTransformInfoImpl.h:196
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:586
llvm::TargetTransformInfoImplCRTPBase::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:909
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
GetElementPtrTypeIterator.h
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:317
llvm::ConstantInt::getValue
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:131
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::TargetTransformInfoImplBase::getExtendedAddReductionCost
InstructionCost getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfoImpl.h:630
llvm::TargetTransformInfoImplBase::isLSRCostLess
bool isLSRCostLess(TTI::LSRCost &C1, TTI::LSRCost &C2) const
Definition: TargetTransformInfoImpl.h:206
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1643
llvm::TargetTransformInfoImplBase::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType) const
Definition: TargetTransformInfoImpl.h:262
llvm::TargetTransformInfoImplBase::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Definition: TargetTransformInfoImpl.h:99
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:350
llvm::CmpInst::makeCmpResultType
static Type * makeCmpResultType(Type *opnd_type)
Create a result type for fcmp/icmp.
Definition: InstrTypes.h:1034
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:693
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:443
llvm::TargetTransformInfoImplBase::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: TargetTransformInfoImpl.h:390
llvm::TargetTransformInfoImplBase::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent() const
Definition: TargetTransformInfoImpl.h:75
llvm::TargetTransformInfoImplBase::getIntImmCodeSizeCost
int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const
Definition: TargetTransformInfoImpl.h:347
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:151
llvm::TargetTransformInfoImplBase::TTI
TargetTransformInfo TTI
Definition: TargetTransformInfoImpl.h:36
llvm::TargetTransformInfo::LSRCost::NumIVMuls
unsigned NumIVMuls
Definition: TargetTransformInfo.h:415
llvm::TargetTransformInfoImplBase::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: TargetTransformInfoImpl.h:375
llvm::TargetTransformInfoImplBase::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:699
llvm::TargetTransformInfoImplBase::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Definition: TargetTransformInfoImpl.h:335
llvm::TargetTransformInfoImplBase::getOperandsScalarizationOverhead
unsigned getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
Definition: TargetTransformInfoImpl.h:307
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1581
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:529
llvm::TargetTransformInfoImplBase::isLegalToVectorizeStore
bool isLegalToVectorizeStore(StoreInst *SI) const
Definition: TargetTransformInfoImpl.h:703
llvm::TargetTransformInfoImplBase::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const
Definition: TargetTransformInfoImpl.h:286
llvm::Optional
Definition: APInt.h:33
T
#define T
Definition: Mips16ISelLowering.cpp:341
Operator.h
llvm::TargetTransformInfoImplBase::areFunctionArgsABICompatible
bool areFunctionArgsABICompatible(const Function *Caller, const Function *Callee, SmallPtrSetImpl< Argument * > &Args) const
Definition: TargetTransformInfoImpl.h:680
llvm::TargetTransformInfoImplBase::hasActiveVectorLength
bool hasActiveVectorLength() const
Definition: TargetTransformInfoImpl.h:748
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::TargetTransformInfoImplBase::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Definition: TargetTransformInfoImpl.h:93
llvm::TargetTransformInfoImplBase::getArithmeticInstrCost
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr) const
Definition: TargetTransformInfoImpl.h:444
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(const DataLayout &DL)
Definition: TargetTransformInfoImpl.h:40
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:492
llvm::gep_type_begin
gep_type_iterator gep_type_begin(const User *GEP)
Definition: GetElementPtrTypeIterator.h:139
llvm::Type::isFloatingPointTy
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Definition: Type.h:163
llvm::TargetTransformInfoImplBase::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:256
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetTransformInfo::SK_PermuteSingleSrc
@ SK_PermuteSingleSrc
Shuffle elements of single source vector with any shuffle mask.
Definition: TargetTransformInfo.h:856
llvm::TargetTransformInfoImplBase::haveFastSqrt
bool haveFastSqrt(Type *Ty) const
Definition: TargetTransformInfoImpl.h:339
llvm::Type::getInt8Ty
static IntegerType * getInt8Ty(LLVMContext &C)
Definition: Type.cpp:202
llvm::TargetTransformInfoImplBase::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization() const
Definition: TargetTransformInfoImpl.h:323
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:299
llvm::TargetTransformInfoImplBase::getIntImmCostInst
unsigned getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
Definition: TargetTransformInfoImpl.h:357
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:965
llvm::TargetTransformInfoImplBase::getConstantStrideStep
const SCEVConstant * getConstantStrideStep(ScalarEvolution *SE, const SCEV *Ptr) const
Definition: TargetTransformInfoImpl.h:811
llvm::TargetTransformInfoImplBase::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Definition: TargetTransformInfoImpl.h:101
llvm::TargetTransformInfo::SK_Broadcast
@ SK_Broadcast
Broadcast element 0 to all other elements.
Definition: TargetTransformInfo.h:846
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::TargetTransformInfoImplBase::getScalarizationOverhead
unsigned getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
Definition: TargetTransformInfoImpl.h:302
llvm::TargetTransformInfo::LSRCost::AddRecCost
unsigned AddRecCost
Definition: TargetTransformInfo.h:414
llvm::TargetTransformInfoImplBase::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Definition: TargetTransformInfoImpl.h:284
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:48
llvm::TargetTransformInfoImplBase::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: TargetTransformInfoImpl.h:672
llvm::TargetTransformInfoImplBase::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: TargetTransformInfoImpl.h:396
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::TargetTransformInfo::LSRCost::SetupCost
unsigned SetupCost
Definition: TargetTransformInfo.h:418
llvm::TargetTransformInfoImplBase::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR() const
Definition: TargetTransformInfoImpl.h:213
llvm::TargetTransformInfoImplBase::getVectorInstrCost
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const
Definition: TargetTransformInfoImpl.h:535
llvm::TargetTransformInfoImplBase::getCostOfKeepingLiveOverCall
unsigned getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
Definition: TargetTransformInfoImpl.h:636
llvm::TargetTransformInfoImplBase::getPredictableBranchThreshold
BranchProbability getPredictableBranchThreshold() const
Definition: TargetTransformInfoImpl.h:87
llvm::TargetTransformInfoImplBase::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, bool *Fast) const
Definition: TargetTransformInfoImpl.h:329
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:77
llvm::TargetTransformInfoImplBase::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Definition: TargetTransformInfoImpl.h:264
llvm::TargetTransformInfo::SK_PermuteTwoSrc
@ SK_PermuteTwoSrc
Merge elements from two source vectors into one with any shuffle mask.
Definition: TargetTransformInfo.h:854
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::LinearPolySize< ElementCount >::get
static ElementCount get(ScalarTy MinVal, bool Scalable)
Definition: TypeSize.h:290
llvm::TargetTransformInfo::getCastContextHint
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
Definition: TargetTransformInfo.cpp:728
llvm::TargetTransformInfoImplBase::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF) const
Definition: TargetTransformInfoImpl.h:442
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(TargetTransformInfoImplBase &&Arg)
Definition: TargetTransformInfoImpl.h:46
llvm::TargetTransformInfoImplBase
Base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:34
llvm::TargetTransformInfoImplBase::getCacheAssociativity
llvm::Optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const
Definition: TargetTransformInfoImpl.h:422
llvm::PatternMatch::match
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
llvm::TargetTransformInfoImplBase::getPrefetchDistance
unsigned getPrefetchDistance() const
Definition: TargetTransformInfoImpl.h:433
llvm::TargetTransformInfoImplBase::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: TargetTransformInfoImpl.h:369
llvm::TargetTransformInfoImplBase::getAddressComputationCost
unsigned getAddressComputationCost(Type *Tp, ScalarEvolution *, const SCEV *) const
Definition: TargetTransformInfoImpl.h:615
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:903
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:845
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1079
llvm::TargetTransformInfoImplBase::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:230
llvm::User
Definition: User.h:44
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetTransformInfoImplBase::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Definition: TargetTransformInfoImpl.h:296
llvm::TargetTransformInfoImplBase::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth(bool OptSize) const
Definition: TargetTransformInfoImpl.h:394
SI
@ SI
Definition: SIInstrInfo.cpp:7342
llvm::TargetTransformInfoImplBase::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfoImpl.h:658
llvm::TargetTransformInfoImplBase::hasBranchDivergence
bool hasBranchDivergence() const
Definition: TargetTransformInfoImpl.h:91
llvm::TargetTransformInfoImplBase::isIndexedStoreLegal
bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
Definition: TargetTransformInfoImpl.h:694
llvm::TargetTransformInfoImplBase::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Definition: TargetTransformInfoImpl.h:294
llvm::Instruction
Definition: Instruction.h:45
llvm::TargetTransformInfo::RK_Arithmetic
@ RK_Arithmetic
Not a reduction.
Definition: TargetTransformInfo.h:863
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:154
llvm::TargetTransformInfoImplBase::getNumberOfParts
unsigned getNumberOfParts(Type *Tp) const
Definition: TargetTransformInfoImpl.h:613
llvm::Operator::getOpcode
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
Definition: Operator.h:40
llvm::TargetTransformInfoImplBase::isTypeLegal
bool isTypeLegal(Type *Ty) const
Definition: TargetTransformInfoImpl.h:290
llvm::TargetTransformInfoImplBase::isLegalAddressingMode
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:198
llvm::TargetTransformInfoImplBase::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
Definition: TargetTransformInfoImpl.h:653
llvm::TargetTransformInfo::matchVectorReduction
static ReductionKind matchVectorReduction(const ExtractElementInst *ReduxRoot, unsigned &Opcode, VectorType *&Ty, bool &IsPairwise)
Definition: TargetTransformInfo.cpp:1317
llvm::TargetTransformInfoImplCRTPBase
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:835
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::TargetTransformInfoImplBase::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:266
PatternMatch.h
llvm::TargetTransformInfoImplBase::enableWritePrefetching
bool enableWritePrefetching() const
Definition: TargetTransformInfoImpl.h:440
llvm::TargetTransformInfoImplBase::enableMemCmpExpansion
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: TargetTransformInfoImpl.h:318
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:154
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::TargetTransformInfoImplBase::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Definition: TargetTransformInfoImpl.h:95
llvm::TargetTransformInfoImplBase::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:547
llvm::None
const NoneType None
Definition: None.h:23
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:284
Type.h
llvm::TargetTransformInfoImplBase::getCFInstrCost
unsigned getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:519
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:116
llvm::TargetTransformInfo::RK_UnsignedMinMax
@ RK_UnsignedMinMax
Min/max reduction data.
Definition: TargetTransformInfo.h:865
llvm::TargetTransformInfoImplBase::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:553
llvm::TargetTransformInfo::PSK_Software
@ PSK_Software
Definition: TargetTransformInfo.h:586
llvm::TargetTransformInfoImplBase::getCacheSize
llvm::Optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const
Definition: TargetTransformInfoImpl.h:411
llvm::TargetTransformInfoImplBase::emitGetActiveLaneMask
bool emitGetActiveLaneMask() const
Definition: TargetTransformInfoImpl.h:164
llvm::TargetTransformInfoImplBase::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I) const
Definition: TargetTransformInfoImpl.h:215
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::ARM_PROC::IE
@ IE
Definition: ARMBaseInfo.h:27
llvm::TargetTransformInfoImplBase::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: TargetTransformInfoImpl.h:180
llvm::TargetTransformInfoImplBase::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: TargetTransformInfoImpl.h:737
llvm::TargetTransformInfoImplBase::supportsScalableVectors
bool supportsScalableVectors() const
Definition: TargetTransformInfoImpl.h:746
llvm::TargetTransformInfoImplBase::enableMaskedInterleavedAccessVectorization
bool enableMaskedInterleavedAccessVectorization() const
Definition: TargetTransformInfoImpl.h:325
llvm::TargetTransformInfo::SK_Reverse
@ SK_Reverse
Reverse the order of the vector.
Definition: TargetTransformInfo.h:847
llvm::TargetTransformInfoImplCRTPBase::TargetTransformInfoImplCRTPBase
TargetTransformInfoImplCRTPBase(const DataLayout &DL)
Definition: TargetTransformInfoImpl.h:840
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:391
VectorUtils.h
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:78
llvm::TargetTransformInfoImplBase::canMacroFuseCmp
bool canMacroFuseCmp() const
Definition: TargetTransformInfoImpl.h:217
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:303
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetTransformInfoImplBase::getEstimatedNumberOfCaseClusters
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Definition: TargetTransformInfoImpl.h:62
llvm::TargetTransformInfoImplBase::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:238
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:409
llvm::TargetTransformInfoImplBase::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:710
llvm::PatternMatch::m_LogicalOr
LogicalOp_match< LHS, RHS, Instruction::Or > m_LogicalOr(const LHS &L, const RHS &R)
Matches L || R either in the form of L | R or L ? true : R.
Definition: PatternMatch.h:2457
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:58
llvm::TargetTransformInfoImplBase::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Definition: TargetTransformInfoImpl.h:174
llvm::TargetTransformInfoImplBase::getPreferredAddressingMode
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Definition: TargetTransformInfoImpl.h:226
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:423
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfoImplBase::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:475
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:903
llvm::LoopAccessInfo
Drive the analysis of memory accesses in the loop.
Definition: LoopAccessAnalysis.h:519
llvm::SCEVConstant
This class represents a constant integer value.
Definition: ScalarEvolutionExpressions.h:47
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetTransformInfoImplBase::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
Definition: TargetTransformInfoImpl.h:402
llvm::TargetTransformInfoImplBase::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Definition: TargetTransformInfoImpl.h:115
llvm::CmpInst::BAD_ICMP_PREDICATE
@ BAD_ICMP_PREDICATE
Definition: InstrTypes.h:755
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::TargetTransformInfo::LSRCost::ScaleCost
unsigned ScaleCost
Definition: TargetTransformInfo.h:419
llvm::TargetTransformInfoImplBase::getInterleavedMemoryOpCost
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) const
Definition: TargetTransformInfoImpl.h:561
llvm::TargetTransformInfoImplBase::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: TargetTransformInfoImpl.h:640
llvm::TargetTransformInfoImplBase::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Definition: TargetTransformInfoImpl.h:314
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:895
llvm::GEPOperator
Definition: Operator.h:457
llvm::PatternMatch::m_Value
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:76
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::TargetTransformInfoImplBase::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned, unsigned) const
Definition: TargetTransformInfoImpl.h:106
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:750
llvm::TargetTransformInfoImplBase::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:245
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:262
llvm::TargetTransformInfoImplBase::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: TargetTransformInfoImpl.h:742
llvm::TargetTransformInfoImplBase::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier() const
Definition: TargetTransformInfoImpl.h:72
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LoopInfo
Definition: LoopInfo.h:1079
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
DataLayout.h
llvm::StructType
Class to represent struct types.
Definition: DerivedTypes.h:212
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:41
llvm::TargetTransformInfo::TCK_SizeAndLatency
@ TCK_SizeAndLatency
The weighted sum of size and latency.
Definition: TargetTransformInfo.h:215
llvm::TargetTransformInfoImplBase::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfoImpl.h:744
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::TargetTransformInfoImplCRTPBase::getInstructionLatency
InstructionCost getInstructionLatency(const Instruction *I)
Definition: TargetTransformInfoImpl.h:1130
llvm::TargetTransformInfoImplBase::LSRWithInstrQueries
bool LSRWithInstrQueries() const
Definition: TargetTransformInfoImpl.h:282
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BranchProbability
Definition: BranchProbability.h:30
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetTransformInfoImplBase::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
Definition: TargetTransformInfoImpl.h:312
llvm::TargetTransformInfoImplBase::getScalingFactorCost
int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:272
llvm::TargetTransformInfoImplBase::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Definition: TargetTransformInfoImpl.h:341
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::TargetTransformInfoImplBase::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:528
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:633
llvm::TargetTransformInfoImplBase::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:234
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:419
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:896
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:281
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:174
llvm::TargetTransformInfo::SK_Transpose
@ SK_Transpose
Transpose two vectors.
Definition: TargetTransformInfo.h:851
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::TargetTransformInfoImplBase::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfoImpl.h:664
llvm::Value::stripPointerCasts
const Value * stripPointerCasts() const
Strip off pointer casts, all-zero GEPs and address space casts.
Definition: Value.cpp:636
llvm::TargetTransformInfo::CacheLevel::L2D
@ L2D
llvm::TargetTransformInfoImplBase::getIntImmCost
unsigned getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:352
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:140
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:205
llvm::TargetTransformInfoImplBase::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc, ElementCount VF) const
Definition: TargetTransformInfoImpl.h:715
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:163
llvm::TargetTransformInfoImplBase::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: TargetTransformInfoImpl.h:732
llvm::TargetTransformInfoImplBase::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned, VectorType *, bool, TTI::TargetCostKind) const
Definition: TargetTransformInfoImpl.h:620
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::KnownBits
Definition: KnownBits.h:23
llvm::TargetTransformInfo::LSRCost::NumBaseAdds
unsigned NumBaseAdds
Definition: TargetTransformInfo.h:416
llvm::TargetTransformInfoImplBase::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: TargetTransformInfoImpl.h:644
llvm::TargetTransformInfoImplBase::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const
Definition: TargetTransformInfoImpl.h:439
llvm::TargetTransformInfoImplBase::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Definition: TargetTransformInfoImpl.h:110
llvm::APInt::sextOrTrunc
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition: APInt.cpp:956
llvm::TargetTransformInfoImplBase::minRequiredElementSize
unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const
Definition: TargetTransformInfoImpl.h:753
llvm::TypeSize
Definition: TypeSize.h:417
llvm::SCEVAddRecExpr
This node represents a polynomial recurrence on the trip count of the specified loop.
Definition: ScalarEvolutionExpressions.h:352
Function.h
llvm::TargetTransformInfoImplBase::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfoImpl.h:720
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::TargetTransformInfoImplBase::isIndexedLoadLegal
bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
Definition: TargetTransformInfoImpl.h:689
llvm::TargetTransformInfoImplBase::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Definition: TargetTransformInfoImpl.h:434
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:207
llvm::User::operand_values
iterator_range< value_op_iterator > operand_values()
Definition: User.h:266
llvm::TargetTransformInfo::LSRCost::ImmCost
unsigned ImmCost
Definition: TargetTransformInfo.h:417
llvm::TargetTransformInfoImplBase::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const
Definition: TargetTransformInfoImpl.h:194
llvm::TargetTransformInfoImplBase::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:540
llvm::TargetTransformInfoImplBase::getMemcpyCost
unsigned getMemcpyCost(const Instruction *I) const
Definition: TargetTransformInfoImpl.h:77
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:184
llvm::TargetTransformInfoImplBase::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: TargetTransformInfoImpl.h:371
llvm::TargetTransformInfoImplBase::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: TargetTransformInfoImpl.h:386
llvm::TargetTransformInfoImplBase::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Definition: TargetTransformInfoImpl.h:219
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfoImplBase::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: TargetTransformInfoImpl.h:168
llvm::SCEVConstant::getAPInt
const APInt & getAPInt() const
Definition: ScalarEvolutionExpressions.h:57
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:93
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::TargetTransformInfoImplBase::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
Definition: TargetTransformInfoImpl.h:513
llvm::TargetTransformInfoImplBase::isConstantStridedAccessLessThan
bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance) const
Definition: TargetTransformInfoImpl.h:819
llvm::TargetTransformInfoImplBase::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe() const
Definition: TargetTransformInfoImpl.h:327
ScalarEvolutionExpressions.h
llvm::TargetTransformInfoImplBase::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: TargetTransformInfoImpl.h:97
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:66
llvm::TargetTransformInfoImplBase::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType) const
Definition: TargetTransformInfoImpl.h:260
llvm::User::getNumOperands
unsigned getNumOperands() const
Definition: User.h:191
llvm::IntrinsicCostAttributes::getID
Intrinsic::ID getID() const
Definition: TargetTransformInfo.h:146
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:924
llvm::TargetTransformInfoImplBase::isLegalToVectorizeLoad
bool isLegalToVectorizeLoad(LoadInst *LI) const
Definition: TargetTransformInfoImpl.h:701
llvm::Type::getPointerElementType
Type * getPointerElementType() const
Definition: Type.h:378
llvm::TargetTransformInfoImplBase::getShuffleCost
unsigned getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef< int > Mask, int Index, VectorType *SubTp) const
Definition: TargetTransformInfoImpl.h:469
llvm::TargetTransformInfo::RK_MinMax
@ RK_MinMax
Binary reduction data.
Definition: TargetTransformInfo.h:864
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
TargetTransformInfo.h
llvm::TargetTransformInfoImplBase::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *, VectorType *, bool, bool, TTI::TargetCostKind) const
Definition: TargetTransformInfoImpl.h:625
llvm::PatternMatch
Definition: PatternMatch.h:47
llvm::SmallVectorImpl< int >
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:68
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1164
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
llvm::TargetTransformInfo::RK_None
@ RK_None
Definition: TargetTransformInfo.h:862
llvm::TargetTransformInfoImplBase::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfoImpl.h:726
llvm::TargetTransformInfoImplBase::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:705
llvm::TargetTransformInfoImplBase::getFPOpCost
unsigned getFPOpCost(Type *Ty) const
Definition: TargetTransformInfoImpl.h:343
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:171
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(const TargetTransformInfoImplBase &Arg)
Definition: TargetTransformInfoImpl.h:44
llvm::TargetTransformInfoImplBase::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:252
llvm::TargetTransformInfo::getOperandInfo
static OperandValueKind getOperandInfo(const Value *V, OperandValueProperties &OpProps)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
Definition: TargetTransformInfo.cpp:657
llvm::TargetTransformInfo::TCC_Basic
@ TCC_Basic
The cost of a typical 'add' instruction.
Definition: TargetTransformInfo.h:263
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3149
llvm::OptimizedStructLayoutField
A field in a structure.
Definition: OptimizedStructLayout.h:45
llvm::TargetTransformInfoImplBase::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Definition: TargetTransformInfoImpl.h:298
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::TargetTransformInfoImplBase::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: TargetTransformInfoImpl.h:73
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3005
llvm::TargetTransformInfoImplBase::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:568
llvm::TargetTransformInfoImplBase::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Definition: TargetTransformInfoImpl.h:270
llvm::TargetTransformInfoImplBase::useColdCCForColdCall
bool useColdCCForColdCall(Function &F) const
Definition: TargetTransformInfoImpl.h:300
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:212
llvm::TargetTransformInfo::AMK_None
@ AMK_None
Definition: TargetTransformInfo.h:636
llvm::TargetTransformInfo::SK_ExtractSubvector
@ SK_ExtractSubvector
ExtractSubvector Index indicates start offset.
Definition: TargetTransformInfo.h:853
llvm::PatternMatch::m_LogicalAnd
LogicalOp_match< LHS, RHS, Instruction::And > m_LogicalAnd(const LHS &L, const RHS &R)
Matches L && R either in the form of L & R or L ? R : false.
Definition: PatternMatch.h:2446
llvm::TargetTransformInfoImplBase::getPeelingPreferences
void getPeelingPreferences(Loop *, ScalarEvolution &, TTI::PeelingPreferences &) const
Definition: TargetTransformInfoImpl.h:191
llvm::TargetTransformInfoImplBase::getUnrollingPreferences
void getUnrollingPreferences(Loop *, ScalarEvolution &, TTI::UnrollingPreferences &) const
Definition: TargetTransformInfoImpl.h:188
llvm::SCEVAddRecExpr::getStepRecurrence
const SCEV * getStepRecurrence(ScalarEvolution &SE) const
Constructs and returns the recurrence indicating how much this expression steps by.
Definition: ScalarEvolutionExpressions.h:369
llvm::TargetTransformInfoImplBase::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: TargetTransformInfoImpl.h:400
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::TargetTransformInfoImplBase::getRegUsageForType
unsigned getRegUsageForType(Type *Ty) const
Definition: TargetTransformInfoImpl.h:292