This pass provides access to the codegen interfaces that are needed for IR-level transformations. More...

#include "llvm/Analysis/TargetTransformInfo.h"

Classes
class	Concept

struct	LSRCost

struct	MemCmpExpansionOptions
	Returns options for expansion of memcmp. IsZeroCmp is. More...

struct	OperandValueInfo

struct	PeelingPreferences

struct	ReductionFlags
	Flags describing the kind of vector reduction. More...

struct	UnrollingPreferences
	Parameters that control the generic loop unrolling transformation. More...

struct	VPLegalization

Public Member Functions
template<typename T >
	TargetTransformInfo (T Impl)
	Construct a TTI object using a type implementing the `Concept` API below. More...

	TargetTransformInfo (const DataLayout &DL)
	Construct a baseline TTI object using a minimal implementation of the `Concept` API below. More...

	TargetTransformInfo (TargetTransformInfo &&Arg)

TargetTransformInfo &	operator= (TargetTransformInfo &&RHS)

	~TargetTransformInfo ()

bool	invalidate (Function &, const PreservedAnalyses &, FunctionAnalysisManager::Invalidator &)
	Handle the invalidation of this information. More...

Vector Predication Information
Whether the target supports the evl parameter of VP intrinsic efficiently in hardware, for the given opcode and type/alignment. (see LLVM Language Reference - "Vector Predication Intrinsics"). Use of evl is discouraged when that is not the case.
bool	hasActiveVectorLength (unsigned Opcode, Type *DataType, Align Alignment) const

VPLegalization	getVPLegalizationStrategy (const VPIntrinsic &PI) const

Generic Target Information
enum	TargetCostKind { TCK_RecipThroughput, TCK_Latency, TCK_CodeSize, TCK_SizeAndLatency }
	The kind of cost model. More...

enum	TargetCostConstants { TCC_Free = 0, TCC_Basic = 1, TCC_Expensive = 4 }
	Underlying constants for 'cost' values in this interface. More...

InstructionCost	getGEPCost (Type PointeeType, const Value Ptr, ArrayRef< const Value * > Operands, TargetCostKind CostKind=TCK_SizeAndLatency) const
	Estimate the cost of a GEP operation when lowered. More...

unsigned	getInliningThresholdMultiplier () const

unsigned	adjustInliningThreshold (const CallBase *CB) const

int	getInlinerVectorBonusPercent () const

InstructionCost	getMemcpyCost (const Instruction *I) const

unsigned	getEstimatedNumberOfCaseClusters (const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo PSI, BlockFrequencyInfo BFI) const

InstructionCost	getInstructionCost (const User U, ArrayRef< const Value > Operands, TargetCostKind CostKind) const
	Estimate the cost of a given IR user when lowered. More...

InstructionCost	getInstructionCost (const User *U, TargetCostKind CostKind) const
	This is a helper function which calls the three-argument getInstructionCost with `Operands` which are the current operands U has. More...

BranchProbability	getPredictableBranchThreshold () const
	If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly. More...

bool	hasBranchDivergence () const
	Return true if branch divergence exists. More...

bool	useGPUDivergenceAnalysis () const
	Return true if the target prefers to use GPU divergence analysis to replace the legacy version. More...

bool	isSourceOfDivergence (const Value *V) const
	Returns whether V is a source of divergence. More...

bool	isAlwaysUniform (const Value *V) const

unsigned	getFlatAddressSpace () const
	Returns the address space ID for a target's 'flat' address space. More...

bool	collectFlatAddressOperands (SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
	Return any intrinsic address operand indexes which may be rewritten if they use a flat address space pointer. More...

bool	isNoopAddrSpaceCast (unsigned FromAS, unsigned ToAS) const

bool	canHaveNonUndefGlobalInitializerInAddressSpace (unsigned AS) const
	Return true if globals in this address space can have initializers other than `undef`. More...

unsigned	getAssumedAddrSpace (const Value *V) const

std::pair< const Value *, unsigned >	getPredicatedAddrSpace (const Value *V) const

Value *	rewriteIntrinsicWithAddressSpace (IntrinsicInst II, Value OldV, Value *NewV) const
	Rewrite intrinsic call `II` such that `OldV` will be replaced with `NewV`, which has a different address space. More...

bool	isLoweredToCall (const Function *F) const
	Test whether calls to a function lower to actual program function calls. More...

void	getUnrollingPreferences (Loop L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter ORE) const
	Get target-customized preferences for the generic loop unrolling transformation. More...

bool	isHardwareLoopProfitable (Loop L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo LibInfo, HardwareLoopInfo &HWLoopInfo) const
	Query the target whether it would be profitable to convert the given loop into a hardware loop. More...

bool	preferPredicateOverEpilogue (Loop L, LoopInfo LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo TLI, DominatorTree DT, LoopVectorizationLegality LVL, InterleavedAccessInfo IAI) const
	Query the target whether it would be prefered to create a predicated vector loop, which can avoid the need to emit a scalar epilogue loop. More...

PredicationStyle	emitGetActiveLaneMask () const
	Query the target whether lowering of the llvm.get.active.lane.mask intrinsic is supported and how the mask should be used. More...

void	getPeelingPreferences (Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
	Get target-customized preferences for the generic loop peeling transformation. More...

Optional< Instruction * >	instCombineIntrinsic (InstCombiner &IC, IntrinsicInst &II) const
	Targets can implement their own combinations for target-specific intrinsics. More...

Optional< Value * >	simplifyDemandedUseBitsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
	Can be used to implement target-specific instruction combining. More...

Optional< Value * >	simplifyDemandedVectorEltsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
	Can be used to implement target-specific instruction combining. More...

Scalar Target Information
enum	PopcntSupportKind { PSK_Software, PSK_SlowHardware, PSK_FastHardware }
	Flags indicating the kind of support for population count. More...

enum	AddressingModeKind { AMK_PreIndexed, AMK_PostIndexed, AMK_None }

bool	isLegalAddImmediate (int64_t Imm) const
	Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register. More...

bool	isLegalICmpImmediate (int64_t Imm) const
	Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register. More...

bool	isLegalAddressingMode (Type Ty, GlobalValue BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr) const
	Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. More...

bool	isLSRCostLess (const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const
	Return true if LSR cost of C1 is lower than C2. More...

bool	isNumRegsMajorCostOfLSR () const
	Return true if LSR major cost is number of registers. More...

bool	isProfitableLSRChainElement (Instruction *I) const

bool	canMacroFuseCmp () const
	Return true if the target can fuse a compare and branch. More...

bool	canSaveCmp (Loop L, BranchInst BI, ScalarEvolution SE, LoopInfo LI, DominatorTree DT, AssumptionCache AC, TargetLibraryInfo LibInfo) const
	Return true if the target can save a compare for loop count, for example hardware loop saves a compare. More...

AddressingModeKind	getPreferredAddressingMode (const Loop L, ScalarEvolution SE) const
	Return the preferred addressing mode LSR should make efforts to generate. More...

bool	isLegalMaskedStore (Type *DataType, Align Alignment) const
	Return true if the target supports masked store. More...

bool	isLegalMaskedLoad (Type *DataType, Align Alignment) const
	Return true if the target supports masked load. More...

bool	isLegalNTStore (Type *DataType, Align Alignment) const
	Return true if the target supports nontemporal store. More...

bool	isLegalNTLoad (Type *DataType, Align Alignment) const
	Return true if the target supports nontemporal load. More...

bool	isLegalBroadcastLoad (Type *ElementTy, ElementCount NumElements) const
	\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy>. More...

bool	isLegalMaskedScatter (Type *DataType, Align Alignment) const
	Return true if the target supports masked scatter. More...

bool	isLegalMaskedGather (Type *DataType, Align Alignment) const
	Return true if the target supports masked gather. More...

bool	forceScalarizeMaskedGather (VectorType *Type, Align Alignment) const
	Return true if the target forces scalarizing of llvm.masked.gather intrinsics. More...

bool	forceScalarizeMaskedScatter (VectorType *Type, Align Alignment) const
	Return true if the target forces scalarizing of llvm.masked.scatter intrinsics. More...

bool	isLegalMaskedCompressStore (Type *DataType) const
	Return true if the target supports masked compress store. More...

bool	isLegalMaskedExpandLoad (Type *DataType) const
	Return true if the target supports masked expand load. More...

bool	isLegalAltInstr (VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
	Return true if this is an alternating opcode pattern that can be lowered to a single instruction on the target. More...

bool	enableOrderedReductions () const
	Return true if we should be enabling ordered reductions for the target. More...

bool	hasDivRemOp (Type *DataType, bool IsSigned) const
	Return true if the target has a unified operation to calculate division and remainder. More...

bool	hasVolatileVariant (Instruction *I, unsigned AddrSpace) const
	Return true if the given instruction (assumed to be a memory access instruction) has a volatile variant. More...

bool	prefersVectorizedAddressing () const
	Return true if target doesn't mind addresses in vectors. More...

InstructionCost	getScalingFactorCost (Type Ty, GlobalValue BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
	Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More...

bool	LSRWithInstrQueries () const
	Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAddressingMode(). More...

bool	isTruncateFree (Type Ty1, Type Ty2) const
	Return true if it's free to truncate a value of type Ty1 to type Ty2. More...

bool	isProfitableToHoist (Instruction *I) const
	Return true if it is profitable to hoist instruction in the then/else to before if. More...

bool	useAA () const

bool	isTypeLegal (Type *Ty) const
	Return true if this type is legal. More...

unsigned	getRegUsageForType (Type *Ty) const
	Returns the estimated number of registers required to represent `Ty`. More...

bool	shouldBuildLookupTables () const
	Return true if switches should be turned into lookup tables for the target. More...

bool	shouldBuildLookupTablesForConstant (Constant *C) const
	Return true if switches should be turned into lookup tables containing this constant value for the target. More...

bool	shouldBuildRelLookupTables () const
	Return true if lookup tables should be turned into relative lookup tables. More...

bool	useColdCCForColdCall (Function &F) const
	Return true if the input function which is cold at all call sites, should use coldcc calling convention. More...

InstructionCost	getScalarizationOverhead (VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
	Estimate the overhead of scalarizing an instruction. More...

InstructionCost	getOperandsScalarizationOverhead (ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
	Estimate the overhead of scalarizing an instructions unique non-constant operands. More...

bool	supportsEfficientVectorElementLoadStore () const
	If target has efficient vector element load/store instructions, it can return true here so that insertion/extraction costs are not added to the scalarization cost of a load/store. More...

bool	supportsTailCalls () const
	If the target supports tail calls. More...

bool	supportsTailCallFor (const CallBase *CB) const
	If target supports tail call on `CB`. More...

bool	enableAggressiveInterleaving (bool LoopHasReductions) const
	Don't restrict interleaved unrolling to small loops. More...

MemCmpExpansionOptions	enableMemCmpExpansion (bool OptSize, bool IsZeroCmp) const

bool	enableInterleavedAccessVectorization () const
	Enable matching of interleaved access groups. More...

bool	enableMaskedInterleavedAccessVectorization () const
	Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore vectorized using masked vector loads/stores. More...

bool	isFPVectorizationPotentiallyUnsafe () const
	Indicate that it is potentially unsafe to automatically vectorize floating-point operations because the semantics of vector and scalar floating-point semantics may differ. More...

bool	allowsMisalignedMemoryAccesses (LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), bool *Fast=nullptr) const
	Determine if the target supports unaligned memory accesses. More...

PopcntSupportKind	getPopcntSupport (unsigned IntTyWidthInBit) const
	Return hardware support for population count. More...

bool	haveFastSqrt (Type *Ty) const
	Return true if the hardware has a fast square-root instruction. More...

bool	isExpensiveToSpeculativelyExecute (const Instruction *I) const
	Return true if the cost of the instruction is too high to speculatively execute and should be kept behind a branch. More...

bool	isFCmpOrdCheaperThanFCmpZero (Type *Ty) const
	Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a comparison against a constant FP zero value. More...

InstructionCost	getFPOpCost (Type *Ty) const
	Return the expected cost of supporting the floating point operation of the specified type. More...

InstructionCost	getIntImmCost (const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
	Return the expected cost of materializing for the given integer immediate of the specified type. More...

InstructionCost	getIntImmCostInst (unsigned Opc, unsigned Idx, const APInt &Imm, Type Ty, TargetCostKind CostKind, Instruction Inst=nullptr) const
	Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction. More...

InstructionCost	getIntImmCostIntrin (Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const

InstructionCost	getIntImmCodeSizeCost (unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
	Return the expected cost for the given integer when optimising for size. More...

Vector Target Information
enum	ShuffleKind { SK_Broadcast, SK_Reverse, SK_Select, SK_Transpose, SK_InsertSubvector, SK_ExtractSubvector, SK_PermuteTwoSrc, SK_PermuteSingleSrc, SK_Splice }
	The various kinds of shuffle patterns for vector queries. More...

enum	OperandValueKind { OK_AnyValue, OK_UniformValue, OK_UniformConstantValue, OK_NonUniformConstantValue }
	Additional information about an operand's possible values. More...

enum	OperandValueProperties { OP_None = 0, OP_PowerOf2 = 1, OP_NegatedPowerOf2 = 2 }
	Additional properties of an operand's values. More...

enum	RegisterKind { RGK_Scalar, RGK_FixedWidthVector, RGK_ScalableVector }

enum	CacheLevel { CacheLevel::L1D, CacheLevel::L2D }
	The possible cache levels. More...

enum	CastContextHint : uint8_t { CastContextHint::None, CastContextHint::Normal, CastContextHint::Masked, CastContextHint::GatherScatter, CastContextHint::Interleave, CastContextHint::Reversed }
	Represents a hint about the context in which a cast is used. More...

enum	MemIndexedMode { MIM_Unindexed, MIM_PreInc, MIM_PreDec, MIM_PostInc, MIM_PostDec }
	The type of load/store indexing. More...

unsigned	getNumberOfRegisters (unsigned ClassID) const

unsigned	getRegisterClassForType (bool Vector, Type *Ty=nullptr) const

const char *	getRegisterClassName (unsigned ClassID) const

TypeSize	getRegisterBitWidth (RegisterKind K) const

unsigned	getMinVectorRegisterBitWidth () const

Optional< unsigned >	getMaxVScale () const

Optional< unsigned >	getVScaleForTuning () const

bool	shouldMaximizeVectorBandwidth (TargetTransformInfo::RegisterKind K) const

ElementCount	getMinimumVF (unsigned ElemWidth, bool IsScalable) const

unsigned	getMaximumVF (unsigned ElemWidth, unsigned Opcode) const

unsigned	getStoreMinimumVF (unsigned VF, Type ScalarMemTy, Type ScalarValTy) const

bool	shouldConsiderAddressTypePromotion (const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const

unsigned	getCacheLineSize () const

Optional< unsigned >	getCacheSize (CacheLevel Level) const

Optional< unsigned >	getCacheAssociativity (CacheLevel Level) const

unsigned	getPrefetchDistance () const

unsigned	getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
	Some HW prefetchers can handle accesses up to a certain constant stride. More...

unsigned	getMaxPrefetchIterationsAhead () const

bool	enableWritePrefetching () const

bool	shouldPrefetchAddressSpace (unsigned AS) const

unsigned	getMaxInterleaveFactor (unsigned VF) const

InstructionCost	getArithmeticInstrCost (unsigned Opcode, Type Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr) const
	This is an approximation of reciprocal throughput of a math/logic op. More...

InstructionCost	getShuffleCost (ShuffleKind Kind, VectorType Tp, ArrayRef< int > Mask=None, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, int Index=0, VectorType SubTp=nullptr, ArrayRef< const Value * > Args=None) const

InstructionCost	getCastInstrCost (unsigned Opcode, Type Dst, Type Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const

InstructionCost	getExtractWithExtendCost (unsigned Opcode, Type Dst, VectorType VecTy, unsigned Index) const

InstructionCost	getCFInstrCost (unsigned Opcode, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const

InstructionCost	getCmpSelInstrCost (unsigned Opcode, Type ValTy, Type CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const

InstructionCost	getVectorInstrCost (unsigned Opcode, Type *Val, unsigned Index=-1) const

InstructionCost	getVectorInstrCost (const Instruction &I, Type *Val, unsigned Index=-1) const

InstructionCost	getReplicationShuffleCost (Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)

InstructionCost	getMemoryOpCost (unsigned Opcode, Type Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueInfo OpdInfo={OK_AnyValue, OP_None}, const Instruction I=nullptr) const

InstructionCost	getVPMemoryOpCost (unsigned Opcode, Type Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction I=nullptr) const

InstructionCost	getMaskedMemoryOpCost (unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const

InstructionCost	getGatherScatterOpCost (unsigned Opcode, Type DataTy, const Value Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const

InstructionCost	getInterleavedMemoryOpCost (unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, bool UseMaskForCond=false, bool UseMaskForGaps=false) const

InstructionCost	getArithmeticReductionCost (unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
	Calculate the cost of vector reduction intrinsics. More...

InstructionCost	getMinMaxReductionCost (VectorType Ty, VectorType CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const

InstructionCost	getMulAccReductionCost (bool IsUnsigned, Type ResTy, VectorType Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
	Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add reduction with multiply and optional extensions. More...

InstructionCost	getExtendedReductionCost (unsigned Opcode, bool IsUnsigned, Type ResTy, VectorType Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
	Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of a reduction with an extension. More...

InstructionCost	getIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const

InstructionCost	getCallInstrCost (Function F, Type RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency) const

unsigned	getNumberOfParts (Type *Tp) const

InstructionCost	getAddressComputationCost (Type Ty, ScalarEvolution SE=nullptr, const SCEV *Ptr=nullptr) const

InstructionCost	getCostOfKeepingLiveOverCall (ArrayRef< Type * > Tys) const

bool	getTgtMemIntrinsic (IntrinsicInst *Inst, MemIntrinsicInfo &Info) const

unsigned	getAtomicMemIntrinsicMaxElementSize () const

Value *	getOrCreateResultFromMemIntrinsic (IntrinsicInst Inst, Type ExpectedType) const

Type *	getMemcpyLoopLoweringType (LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicElementSize=None) const

void	getMemcpyLoopResidualLoweringType (SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicCpySize=None) const

bool	areInlineCompatible (const Function Caller, const Function Callee) const

bool	areTypesABICompatible (const Function Caller, const Function Callee, const ArrayRef< Type * > &Types) const

bool	isIndexedLoadLegal (enum MemIndexedMode Mode, Type *Ty) const

bool	isIndexedStoreLegal (enum MemIndexedMode Mode, Type *Ty) const

unsigned	getLoadStoreVecRegBitWidth (unsigned AddrSpace) const

bool	isLegalToVectorizeLoad (LoadInst *LI) const

bool	isLegalToVectorizeStore (StoreInst *SI) const

bool	isLegalToVectorizeLoadChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const

bool	isLegalToVectorizeStoreChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const

bool	isLegalToVectorizeReduction (const RecurrenceDescriptor &RdxDesc, ElementCount VF) const

bool	isElementTypeLegalForScalableVector (Type *Ty) const

unsigned	getLoadVectorFactor (unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const

unsigned	getStoreVectorFactor (unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const

bool	preferInLoopReduction (unsigned Opcode, Type *Ty, ReductionFlags Flags) const

bool	preferPredicatedReductionSelect (unsigned Opcode, Type *Ty, ReductionFlags Flags) const

bool	shouldExpandReduction (const IntrinsicInst *II) const

unsigned	getGISelRematGlobalCost () const

unsigned	getMinTripCountTailFoldingThreshold () const

bool	supportsScalableVectors () const

bool	enableScalableVectorization () const

static OperandValueInfo	getOperandInfo (const Value *V)
	Collect properties of V used in cost analysis, e.g. OP_PowerOf2. More...

static CastContextHint	getCastContextHint (const Instruction *I)
	Calculates a CastContextHint from `I`. More...

static bool	requiresOrderedReduction (Optional< FastMathFlags > FMF)
	A helper function to determine the type of reduction algorithm used for a given `Opcode` and set of FastMathFlags `FMF`. More...

Detailed Description

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

Definition at line 172 of file TargetTransformInfo.h.

Member Enumeration Documentation

◆ AddressingModeKind

enum llvm::TargetTransformInfo::AddressingModeKind

Enumerator
AMK_PreIndexed
AMK_PostIndexed
AMK_None

Definition at line 630 of file TargetTransformInfo.h.

◆ CacheLevel

enum llvm::TargetTransformInfo::CacheLevel

strong

The possible cache levels.

Enumerator
L1D
L2D

Definition at line 1018 of file TargetTransformInfo.h.

◆ CastContextHint

enum llvm::TargetTransformInfo::CastContextHint : uint8_t

strong

Represents a hint about the context in which a cast is used.

For zext/sext, the context of the cast is the operand, which must be a load of some kind. For trunc, the context is of the cast is the single user of the instruction, which must be a store of some kind.

This enum allows the vectorizer to give getCastInstrCost an idea of the type of cast it's dealing with, as not every cast is equal. For instance, the zext of a load may be free, but the zext of an interleaving load can be (very) expensive!

See getCastContextHint to compute a CastContextHint from a cast Instruction*. Callers can use it if they don't need to override the context and just want it to be calculated from the instruction.

FIXME: This handles the types of load/store that the vectorizer can produce, which are the cases where the context instruction is most likely to be incorrect. There are other situations where that can happen too, which might be handled here but in the long run a more general solution of costing multiple instructions at the same times may be better.

Enumerator
None	The cast is not used with a load/store of any kind.
Normal	The cast is used with a normal load/store.
Masked	The cast is used with a masked load/store.
GatherScatter	The cast is used with a gather/scatter.
Interleave	The cast is used with an interleaved load/store.
Reversed	The cast is used with a reversed load/store.

Definition at line 1136 of file TargetTransformInfo.h.

◆ MemIndexedMode

enum llvm::TargetTransformInfo::MemIndexedMode

The type of load/store indexing.

Enumerator
MIM_Unindexed	No indexing.
MIM_PreInc	Pre-incrementing.
MIM_PreDec	Pre-decrementing.
MIM_PostInc	Post-incrementing.
MIM_PostDec	Post-decrementing.

Definition at line 1400 of file TargetTransformInfo.h.

◆ OperandValueKind

enum llvm::TargetTransformInfo::OperandValueKind

Additional information about an operand's possible values.

Enumerator
OK_AnyValue
OK_UniformValue
OK_UniformConstantValue
OK_NonUniformConstantValue

Definition at line 904 of file TargetTransformInfo.h.

◆ OperandValueProperties

enum llvm::TargetTransformInfo::OperandValueProperties

Additional properties of an operand's values.

Enumerator
OP_None
OP_PowerOf2
OP_NegatedPowerOf2

Definition at line 912 of file TargetTransformInfo.h.

◆ PopcntSupportKind

enum llvm::TargetTransformInfo::PopcntSupportKind

Flags indicating the kind of support for population count.

Compared to the SW implementation, HW support is supposed to significantly boost the performance when the population is dense, and it may or may not degrade performance if the population is sparse. A HW support is considered as "Fast" if it can outperform, or is on a par with, SW implementation when the population is sparse; otherwise, it is considered as "Slow".

Enumerator
PSK_Software
PSK_SlowHardware
PSK_FastHardware

Definition at line 583 of file TargetTransformInfo.h.

◆ RegisterKind

enum llvm::TargetTransformInfo::RegisterKind

Enumerator
RGK_Scalar
RGK_FixedWidthVector
RGK_ScalableVector

Definition at line 962 of file TargetTransformInfo.h.

◆ ShuffleKind

enum llvm::TargetTransformInfo::ShuffleKind

The various kinds of shuffle patterns for vector queries.

Enumerator
SK_Broadcast	Broadcast element 0 to all other elements.
SK_Reverse	Reverse the order of the vector.
SK_Select	Selects elements from the corresponding lane of either source operand. This is equivalent to a vector select with a constant condition operand.
SK_Transpose	Transpose two vectors.
SK_InsertSubvector	InsertSubvector. Index indicates start offset.
SK_ExtractSubvector	ExtractSubvector Index indicates start offset.
SK_PermuteTwoSrc	Merge elements from two source vectors into one with any shuffle mask.
SK_PermuteSingleSrc	Shuffle elements of single source vector with any shuffle mask.
SK_Splice	Concatenates elements from the first input vector with elements of the second input vector. Returning a vector of the same type as the input vectors. Index indicates start offset in first input vector.

Definition at line 884 of file TargetTransformInfo.h.

◆ TargetCostConstants

enum llvm::TargetTransformInfo::TargetCostConstants

Underlying constants for 'cost' values in this interface.

Many APIs in this interface return a cost. This enum defines the fundamental values that should be used to interpret (and produce) those costs. The costs are returned as an int rather than a member of this enumeration because it is expected that the cost of one IR instruction may have a multiplicative factor to it or otherwise won't fit directly into the enum. Moreover, it is common to sum or average costs which works better as simple integral values. Thus this enum only provides constants. Also note that the returned costs are signed integers to make it natural to add, subtract, and test with zero (a common boundary condition). It is not expected that 2^32 is a realistic cost to be modeling at any point.

Note that these costs should usually reflect the intersection of code-size cost and execution cost. A free instruction is typically one that folds into another instruction. For example, reg-to-reg moves can often be skipped by renaming the registers in the CPU, but they still are encoded and thus wouldn't be considered 'free' here.

Enumerator
TCC_Free	Expected to fold away in lowering.
TCC_Basic	The cost of a typical 'add' instruction.
TCC_Expensive	The cost of a 'div' instruction on x86.

Definition at line 242 of file TargetTransformInfo.h.

◆ TargetCostKind

enum llvm::TargetTransformInfo::TargetCostKind

The kind of cost model.

There are several different cost models that can be customized by the target. The normalization of each cost model may be target specific. e.g. TCK_SizeAndLatency should be comparable to target thresholds such as those derived from MCSchedModel::LoopMicroOpBufferSize etc.

Enumerator
TCK_RecipThroughput	Reciprocal throughput.
TCK_Latency	The latency of instruction.
TCK_CodeSize	Instruction code size.
TCK_SizeAndLatency	The weighted sum of size and latency.

Definition at line 217 of file TargetTransformInfo.h.

Constructor & Destructor Documentation

◆ TargetTransformInfo() [1/3]

template<typename T >

llvm::TargetTransformInfo::TargetTransformInfo ( T Impl )

Construct a TTI object using a type implementing the Concept API below.

This is used by targets to construct a TTI wrapping their target-specific implementation that encodes appropriate costs for their target.

Definition at line 2556 of file TargetTransformInfo.h.

References T.

◆ TargetTransformInfo() [2/3]

TargetTransformInfo::TargetTransformInfo ( const DataLayout & DL )

explicit

Construct a baseline TTI object using a minimal implementation of the Concept API below.

The TTI implementation will reflect the information in the DataLayout provided if non-null.

Definition at line 184 of file TargetTransformInfo.cpp.

◆ TargetTransformInfo() [3/3]

TargetTransformInfo::TargetTransformInfo ( TargetTransformInfo && Arg )

Definition at line 189 of file TargetTransformInfo.cpp.

◆ ~TargetTransformInfo()

TargetTransformInfo::~TargetTransformInfo ( )

default

Member Function Documentation

◆ adjustInliningThreshold()

unsigned TargetTransformInfo::adjustInliningThreshold ( const CallBase * CB ) const

Returns: A value to be added to the inlining threshold.

Definition at line 202 of file TargetTransformInfo.cpp.

◆ allowsMisalignedMemoryAccesses()

bool TargetTransformInfo::allowsMisalignedMemoryAccesses	(	LLVMContext &	Context,
		unsigned	BitWidth,
		unsigned	AddressSpace = `0`,
		Align	Alignment = `Align(1)`,
		bool *	Fast = `nullptr`
	)		const

Determine if the target supports unaligned memory accesses.

Definition at line 557 of file TargetTransformInfo.cpp.

References llvm::BitWidth, and Context.

Referenced by foldConsecutiveLoads().

◆ areInlineCompatible()

bool TargetTransformInfo::areInlineCompatible	(	const Function *	Caller,
		const Function *	Callee
	)		const

Returns: True if the two functions have compatible attributes for inlining purposes.

Definition at line 1066 of file TargetTransformInfo.cpp.

References Callee.

Referenced by functionsHaveCompatibleAttributes().

◆ areTypesABICompatible()

bool TargetTransformInfo::areTypesABICompatible	(	const Function *	Caller,
		const Function *	Callee,
		const ArrayRef< Type * > &	Types
	)		const

Returns: True if the caller and callee agree on how Types will be passed to or returned from the callee. to the callee.

Parameters

Types List of types to check.

Definition at line 1071 of file TargetTransformInfo.cpp.

References Callee.

◆ canHaveNonUndefGlobalInitializerInAddressSpace()

bool TargetTransformInfo::canHaveNonUndefGlobalInitializerInAddressSpace ( unsigned AS ) const

Return true if globals in this address space can have initializers other than undef.

Definition at line 267 of file TargetTransformInfo.cpp.

◆ canMacroFuseCmp()

bool TargetTransformInfo::canMacroFuseCmp ( ) const

Return true if the target can fuse a compare and branch.

Loop-strength-reduction (LSR) uses that knowledge to adjust its cost calculation for the instructions in a loop.

Definition at line 371 of file TargetTransformInfo.cpp.

◆ canSaveCmp()

bool TargetTransformInfo::canSaveCmp	(	Loop *	L,
		BranchInst **	BI,
		ScalarEvolution *	SE,
		LoopInfo *	LI,
		DominatorTree *	DT,
		AssumptionCache *	AC,
		TargetLibraryInfo *	LibInfo
	)		const

Return true if the target can save a compare for loop count, for example hardware loop saves a compare.

Definition at line 375 of file TargetTransformInfo.cpp.

◆ collectFlatAddressOperands()

bool TargetTransformInfo::collectFlatAddressOperands	(	SmallVectorImpl< int > &	OpIndexes,
		Intrinsic::ID	IID
	)		const

Return any intrinsic address operand indexes which may be rewritten if they use a flat address space pointer.

Returns: true if the intrinsic was handled.

Definition at line 257 of file TargetTransformInfo.cpp.

◆ emitGetActiveLaneMask()

PredicationStyle TargetTransformInfo::emitGetActiveLaneMask ( ) const

Query the target whether lowering of the llvm.get.active.lane.mask intrinsic is supported and how the mask should be used.

A return value of PredicationStyle::Data indicates the mask is used as data only, whereas PredicationStyle::DataAndControlFlow indicates we should also use the mask for control flow in the loop. If unsupported the return value is PredicationStyle::None.

Definition at line 303 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizationCostModel::useActiveLaneMaskForControlFlow().

◆ enableAggressiveInterleaving()

bool TargetTransformInfo::enableAggressiveInterleaving ( bool LoopHasReductions ) const

Don't restrict interleaved unrolling to small loops.

Definition at line 535 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizationCostModel::selectInterleaveCount().

◆ enableInterleavedAccessVectorization()

bool TargetTransformInfo::enableInterleavedAccessVectorization ( ) const

Enable matching of interleaved access groups.

Definition at line 545 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizePass::processLoop().

◆ enableMaskedInterleavedAccessVectorization()

bool TargetTransformInfo::enableMaskedInterleavedAccessVectorization ( ) const

Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore vectorized using masked vector loads/stores.

Definition at line 549 of file TargetTransformInfo.cpp.

Referenced by useMaskedInterleavedAccesses().

◆ enableMemCmpExpansion()

TargetTransformInfo::MemCmpExpansionOptions TargetTransformInfo::enableMemCmpExpansion	(	bool	OptSize,
		bool	IsZeroCmp
	)		const

Definition at line 541 of file TargetTransformInfo.cpp.

◆ enableOrderedReductions()

bool TargetTransformInfo::enableOrderedReductions ( ) const

Return true if we should be enabling ordered reductions for the target.

Definition at line 446 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizePass::processLoop().

◆ enableScalableVectorization()

bool TargetTransformInfo::enableScalableVectorization ( ) const

Returns: true when scalable vectorization is preferred.

Definition at line 1165 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizeHints::LoopVectorizeHints().

◆ enableWritePrefetching()

bool TargetTransformInfo::enableWritePrefetching ( ) const

Returns: True if prefetching should also be done for writes.

Definition at line 712 of file TargetTransformInfo.cpp.

◆ forceScalarizeMaskedGather()

bool TargetTransformInfo::forceScalarizeMaskedGather	(	VectorType *	Type,
		Align	Alignment
	)		const

Return true if the target forces scalarizing of llvm.masked.gather intrinsics.

Definition at line 428 of file TargetTransformInfo.cpp.

Referenced by canVectorizeLoads(), and optimizeCallInst().

◆ forceScalarizeMaskedScatter()

bool TargetTransformInfo::forceScalarizeMaskedScatter	(	VectorType *	Type,
		Align	Alignment
	)		const

Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.

Definition at line 433 of file TargetTransformInfo.cpp.

Referenced by optimizeCallInst().

◆ getAddressComputationCost()

InstructionCost TargetTransformInfo::getAddressComputationCost	(	Type *	Ty,
		ScalarEvolution *	SE = `nullptr`,
		const SCEV *	Ptr = `nullptr`
	)		const

Returns: The cost of the address computation. For most targets this can be merged into the instruction indexing mode. Some targets might want to distinguish between address computation for memory operations on vector types and scalar types. Such targets should override this function. The 'SE' parameter holds pointer for the scalar evolution object which is used in order to get the Ptr step value in case of constant stride. The 'Ptr' parameter holds SCEV of the access pointer.

Definition at line 984 of file TargetTransformInfo.cpp.

References assert(), Cost, and Ptr.

Referenced by chainToBasePointerCost().

◆ getArithmeticInstrCost()

InstructionCost TargetTransformInfo::getArithmeticInstrCost	(	unsigned	Opcode,
		Type *	Ty,
		TTI::TargetCostKind	CostKind = `TTI::TCK_RecipThroughput`,
		TTI::OperandValueInfo	Opd1Info = `{TTI::OK_AnyValue, TTI::OP_None}`,
		TTI::OperandValueInfo	Opd2Info = `{TTI::OK_AnyValue, TTI::OP_None}`,
		ArrayRef< const Value * >	Args = `ArrayRef<const Value *>()`,
		const Instruction *	CxtI = `nullptr`
	)		const

This is an approximation of reciprocal throughput of a math/logic op.

A higher cost indicates less expected throughput. From Agner Fog's guides, reciprocal throughput is "the average number of clock cycles per instruction when the instructions are not part of a limiting dependency chain." Therefore, costs should be scaled to account for multiple execution units on the target that can process this type of instruction. For example, if there are 5 scalar integer units and 2 vector integer units that can calculate an 'add' in a single cycle, this model should indicate that the cost of the vector add instruction is 2.5 times the cost of the scalar add instruction. Args is an optional argument which holds the instruction operands values so the TTI can analyze those values searching for special cases or optimizations based on those values. CxtI is the optional original context instruction, if one exists, to provide even more information.

Definition at line 785 of file TargetTransformInfo.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), Cost, and CostKind.

Referenced by costAndCollectOperands(), llvm::FoldBranchToCommonDest(), llvm::LoopVectorizationCostModel::getDivRemSpeculationCost(), and visitIVCast().

◆ getArithmeticReductionCost()

InstructionCost TargetTransformInfo::getArithmeticReductionCost	(	unsigned	Opcode,
		VectorType *	Ty,
		Optional< FastMathFlags >	FMF,
		TTI::TargetCostKind	CostKind = `TTI::TCK_RecipThroughput`
	)		const

Calculate the cost of vector reduction intrinsics.

This is the cost of reducing the vector value of type Ty to a scalar value using the operation denoted by Opcode. The FastMathFlags parameter FMF indicates what type of reduction we are performing:

Tree-wise. This is the typical 'fast' reduction performed that involves successively splitting a vector into half and doing the operation on the pair of halves until you have a scalar value. For example: (v0, v1, v2, v3) ((v0+v2), (v1+v3), undef, undef) ((v0+v2+v1+v3), undef, undef, undef) This is the default behaviour for integer operations, whereas for floating point we only do this if FMF indicates that reassociation is allowed.
Ordered. For a vector with N elements this involves performing N operations in lane order, starting with an initial scalar value, i.e. result = InitVal + v0 result = result + v1 result = result + v2 result = result + v3 This is only the case for FP operations and when reassociation is not allowed.

Definition at line 997 of file TargetTransformInfo.cpp.

References assert(), Cost, and CostKind.

◆ getAssumedAddrSpace()

unsigned TargetTransformInfo::getAssumedAddrSpace ( const Value * V ) const

Definition at line 272 of file TargetTransformInfo.cpp.

Referenced by isAddressExpression().

◆ getAtomicMemIntrinsicMaxElementSize()

unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize ( ) const

Returns: The maximum element size, in bytes, for an element unordered-atomic memory intrinsic.

Definition at line 1038 of file TargetTransformInfo.cpp.

◆ getCacheAssociativity()

llvm::Optional< unsigned > TargetTransformInfo::getCacheAssociativity ( CacheLevel Level ) const

Returns: The associativity of the cache level, if available.

Definition at line 693 of file TargetTransformInfo.cpp.

◆ getCacheLineSize()

unsigned TargetTransformInfo::getCacheLineSize ( ) const

Returns: The size of a cache line in bytes.

Definition at line 682 of file TargetTransformInfo.cpp.

References CacheLineSize.

◆ getCacheSize()

llvm::Optional< unsigned > TargetTransformInfo::getCacheSize ( CacheLevel Level ) const

Returns: The size of the cache level in bytes, if available.

Definition at line 688 of file TargetTransformInfo.cpp.

◆ getCallInstrCost()

InstructionCost TargetTransformInfo::getCallInstrCost	(	Function *	F,
		Type *	RetTy,
		ArrayRef< Type * >	Tys,
		TTI::TargetCostKind	CostKind = `TTI::TCK_SizeAndLatency`
	)		const

Returns: The cost of Call instructions.

Definition at line 971 of file TargetTransformInfo.cpp.

References assert(), Cost, CostKind, and F.

Referenced by llvm::LoopVectorizationCostModel::getVectorCallCost(), and getVectorCallCosts().

◆ getCastContextHint()

TTI::CastContextHint TargetTransformInfo::getCastContextHint ( const Instruction * I )

static

Calculates a CastContextHint from I.

This should be used by callers of getCastInstrCost if they wish to determine the context from some instruction.

Returns: the CastContextHint for ZExt/SExt/Trunc, None if I is nullptr, or if it's another type of cast.

Definition at line 808 of file TargetTransformInfo.cpp.

References GatherScatter, llvm::IntrinsicInst::getIntrinsicID(), I, llvm::SPII::Load, Masked, None, Normal, and llvm::SPII::Store.

Referenced by chainToBasePointerCost(), and llvm::TargetTransformInfoImplCRTPBase< AMDGPUTTIImpl >::getInstructionCost().

◆ getCastInstrCost()

InstructionCost TargetTransformInfo::getCastInstrCost	(	unsigned	Opcode,
		Type *	Dst,
		Type *	Src,
		TTI::CastContextHint	CCH,
		TTI::TargetCostKind	CostKind = `TTI::TCK_SizeAndLatency`,
		const Instruction *	I = `nullptr`
	)		const

Returns: The expected cost of cast instructions, such as bitcast, trunc, zext, etc. If there is an existing instruction that holds Opcode, it may be passed in the 'I' parameter.

Definition at line 851 of file TargetTransformInfo.cpp.

References assert(), Cost, CostKind, and I.

Referenced by chainToBasePointerCost(), costAndCollectOperands(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), and tryToFPToSat().

◆ getCFInstrCost()

InstructionCost TargetTransformInfo::getCFInstrCost	(	unsigned	Opcode,
		TTI::TargetCostKind	CostKind = `TTI::TCK_SizeAndLatency`,
		const Instruction *	I = `nullptr`
	)		const

Returns: The expected cost of control-flow related instructions such as Phi, Ret, Br, Switch.

Definition at line 870 of file TargetTransformInfo.cpp.

References assert(), Cost, CostKind, and I.

Referenced by findCostForOutputBlocks(), and llvm::LoopVectorizationCostModel::getDivRemSpeculationCost().

◆ getCmpSelInstrCost()

InstructionCost TargetTransformInfo::getCmpSelInstrCost	(	unsigned	Opcode,
		Type *	ValTy,
		Type *	CondTy,
		CmpInst::Predicate	VecPred,
		TTI::TargetCostKind	CostKind = `TTI::TCK_RecipThroughput`,
		const Instruction *	I = `nullptr`
	)		const

Returns: The expected cost of compare and select instructions. If there is an existing instruction that holds Opcode, it may be passed in the 'I' parameter. The VecPred parameter can be used to indicate the select is using a compare with the specified predicate as condition. When vector types are passed, VecPred must be used for all lanes.

Definition at line 879 of file TargetTransformInfo.cpp.

References assert(), Cost, CostKind, and I.

Referenced by costAndCollectOperands(), findCostForOutputBlocks(), llvm::LoopVectorizationCostModel::getDivRemSpeculationCost(), and validateAndCostRequiredSelects().

◆ getCostOfKeepingLiveOverCall()

InstructionCost TargetTransformInfo::getCostOfKeepingLiveOverCall ( ArrayRef< Type * > Tys ) const

Returns: The cost, if any, of keeping values of the given types alive over a callsite.

Some types may require the use of register classes that do not have any callee-saved registers, so would require a spill and fill.

Definition at line 1029 of file TargetTransformInfo.cpp.

Referenced by llvm::slpvectorizer::BoUpSLP::getSpillCost().

◆ getEstimatedNumberOfCaseClusters()

unsigned TargetTransformInfo::getEstimatedNumberOfCaseClusters	(	const SwitchInst &	SI,
		unsigned &	JTSize,
		ProfileSummaryInfo *	PSI,
		BlockFrequencyInfo *	BFI
	)		const

Returns: The estimated number of case clusters when lowering 'SI'. JTSize Set a jump table size only when SI is suitable for a jump table.

Definition at line 217 of file TargetTransformInfo.cpp.

References llvm::AMDGPUISD::BFI, and SI.

◆ getExtendedReductionCost()

InstructionCost TargetTransformInfo::getExtendedReductionCost	(	unsigned	Opcode,
		bool	IsUnsigned,
		Type *	ResTy,
		VectorType *	Ty,
		Optional< FastMathFlags >	FMF,
		TTI::TargetCostKind	CostKind = `TTI::TCK_RecipThroughput`
	)		const

Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of a reduction with an extension.

This is the cost of as: ResTy vecreduce.opcode(ext(Ty A)).

Definition at line 1015 of file TargetTransformInfo.cpp.

References CostKind.

◆ getExtractWithExtendCost()

InstructionCost TargetTransformInfo::getExtractWithExtendCost	(	unsigned	Opcode,
		Type *	Dst,
		VectorType *	VecTy,
		unsigned	Index
	)		const

Returns: The expected cost of a sign- or zero-extended vector extract. Use Index = -1 to indicate that there is no information about the index value.

Definition at line 862 of file TargetTransformInfo.cpp.

References assert(), and Cost.

Referenced by llvm::slpvectorizer::BoUpSLP::getTreeCost().

◆ getFlatAddressSpace()

unsigned TargetTransformInfo::getFlatAddressSpace ( ) const

Returns the address space ID for a target's 'flat' address space.

Note this is not necessarily the same as addrspace(0), which LLVM sometimes refers to as the generic address space. The flat address space is a generic address space that can be used access multiple segments of memory with different address spaces. Access of a memory location through a pointer with this address space is expected to be legal but slower compared to the same memory location accessed through a pointer with a different address space. This is for targets with different pointer representations which can be converted with the addrspacecast instruction. If a pointer is converted to this address space, optimizations should attempt to replace the access with the source address space.

Returns: ~0u if the target does not have such a flat address space to optimize away.

Definition at line 253 of file TargetTransformInfo.cpp.

◆ getFPOpCost()

InstructionCost TargetTransformInfo::getFPOpCost ( Type * Ty ) const

Return the expected cost of supporting the floating point operation of the specified type.

Definition at line 584 of file TargetTransformInfo.cpp.

References assert(), and Cost.

◆ getGatherScatterOpCost()

InstructionCost TargetTransformInfo::getGatherScatterOpCost	(	unsigned	Opcode,
		Type *	DataTy,
		const Value *	Ptr,
		bool	VariableMask,
		Align	Alignment,
		TTI::TargetCostKind	CostKind = `TTI::TCK_RecipThroughput`,
		const Instruction *	I = `nullptr`
	)		const

Returns: The cost of Gather or Scatter operation Opcode - is a type of memory access Load or Store DataTy - a vector type of the data to be loaded or stored Ptr - pointer [or vector of pointers] - address[es] in memory VariableMask - true when the memory access is predicated with a mask that is not a compile-time constant Alignment - alignment of single element I - the optional original context instruction, if one exists, e.g. the load/store to transform or the call to the gather/scatter intrinsic

Definition at line 942 of file TargetTransformInfo.cpp.

References assert(), Cost, CostKind, I, and Ptr.

◆ getGEPCost()

InstructionCost TargetTransformInfo::getGEPCost	(	Type *	PointeeType,
		const Value *	Ptr,
		ArrayRef< const Value * >	Operands,
		TTI::TargetCostKind	CostKind = `TCK_SizeAndLatency`
	)		const

Estimate the cost of a GEP operation when lowered.

Definition at line 211 of file TargetTransformInfo.cpp.

References CostKind, Operands, and Ptr.

Referenced by isGEPFoldable().

◆ getGISelRematGlobalCost()

unsigned TargetTransformInfo::getGISelRematGlobalCost ( ) const

Returns: the size cost of rematerializing a GlobalValue address relative to a stack reload.

Definition at line 1153 of file TargetTransformInfo.cpp.

Referenced by llvm::TargetLoweringBase::shouldLocalize().

◆ getInlinerVectorBonusPercent()

int TargetTransformInfo::getInlinerVectorBonusPercent ( ) const

Returns: Vector bonus in percent.

Vector bonuses: We want to more aggressively inline vector-dense kernels and apply this bonus based on the percentage of vector instructions. A bonus is applied if the vector instructions exceed 50% and half that amount is applied if it exceeds 10%. Note that these bonuses are some what arbitrary and evolved over time by accident as much as because they are principled bonuses. FIXME: It would be nice to base the bonus values on something more scientific. A target may has no bonus on vector instructions.

Definition at line 206 of file TargetTransformInfo.cpp.

◆ getInliningThresholdMultiplier()

unsigned TargetTransformInfo::getInliningThresholdMultiplier ( ) const

Returns: A value by which our inlining threshold should be multiplied. This is primarily used to bump up the inlining threshold wholesale on targets where calls are unusually expensive.

TODO: This is a rather blunt instrument. Perhaps altering the costs of individual classes of instructions would be better.

Definition at line 197 of file TargetTransformInfo.cpp.

◆ getInstructionCost() [1/2]

InstructionCost TargetTransformInfo::getInstructionCost	(	const User *	U,
		ArrayRef< const Value * >	Operands,
		TargetCostKind	CostKind
	)		const

Estimate the cost of a given IR user when lowered.

This can estimate the cost of either a ConstantExpr or Instruction when lowered.

Operands is a list of operands which can be a result of transformations of the current operands. The number of the operands on the list must equal to the number of the current operands the IR user has. Their order on the list must be the same as the order of the current operands the IR user has.

The returned cost is defined in terms of TargetCostConstants, see its comments for a detailed explanation of the cost values.

Definition at line 224 of file TargetTransformInfo.cpp.

References assert(), Cost, CostKind, Operands, and TCK_RecipThroughput.

Referenced by llvm::CodeMetrics::analyzeBasicBlock(), analyzeLoopUnrollCost(), canSplitCallSite(), checkOuterLoopInsts(), llvm::ComputeSpeculationCost(), computeSpeculationCost(), llvm::FoldBranchToCommonDest(), llvm::OutlinableRegion::getBenefit(), GeneratedRTChecks::getCost(), getInstructionCost(), getJumpThreadDuplicationCost(), getOutliningBenefit(), isFreeInLoop(), mergeConditionalStoreToAddress(), llvm::CostModelPrinterPass::run(), and unswitchBestCondition().

◆ getInstructionCost() [2/2]

InstructionCost llvm::TargetTransformInfo::getInstructionCost	(	const User *	U,
		TargetCostKind	CostKind
	)		const

inline

This is a helper function which calls the three-argument getInstructionCost with Operands which are the current operands U has.

Definition at line 308 of file TargetTransformInfo.h.

References CostKind, getInstructionCost(), llvm::User::operand_values(), and Operands.

◆ getInterleavedMemoryOpCost()

InstructionCost TargetTransformInfo::getInterleavedMemoryOpCost	(	unsigned	Opcode,
		Type *	VecTy,
		unsigned	Factor,
		ArrayRef< unsigned >	Indices,
		Align	Alignment,
		unsigned	AddressSpace,
		TTI::TargetCostKind	CostKind = `TTI::TCK_RecipThroughput`,
		bool	UseMaskForCond = `false`,
		bool	UseMaskForGaps = `false`
	)		const

Returns: The cost of the interleaved memory operation. Opcode is the memory operation code VecTy is the vector type of the interleaved access. Factor is the interleave factor Indices is the indices for interleaved load members (as interleaved load allows gaps) Alignment is the alignment of the memory operation AddressSpace is address space of the pointer. UseMaskForCond indicates if the memory access is predicated. UseMaskForGaps indicates if gaps should be masked.

Definition at line 951 of file TargetTransformInfo.cpp.

References assert(), Cost, and CostKind.

◆ getIntImmCodeSizeCost()

InstructionCost TargetTransformInfo::getIntImmCodeSizeCost	(	unsigned	Opc,
		unsigned	Idx,
		const APInt &	Imm,
		Type *	Ty
	)		const

Return the expected cost for the given integer when optimising for size.

This is different than the other integer immediate cost functions in that it is subtarget agnostic. This is useful when you e.g. target one ISA such as Aarch32 but smaller encodings could be possible with another such as Thumb. This return value is used as a penalty when the total costs for a constant is calculated (the bigger the cost, the more beneficial constant hoisting is).

Definition at line 590 of file TargetTransformInfo.cpp.

References assert(), Cost, and llvm::RISCVMatInt::Imm.

◆ getIntImmCost()

InstructionCost TargetTransformInfo::getIntImmCost	(	const APInt &	Imm,
		Type *	Ty,
		TTI::TargetCostKind	CostKind
	)		const

Return the expected cost of materializing for the given integer immediate of the specified type.

Definition at line 600 of file TargetTransformInfo.cpp.

References assert(), Cost, CostKind, and llvm::RISCVMatInt::Imm.

Referenced by tryUnmergingGEPsAcrossIndirectBr().

◆ getIntImmCostInst()

InstructionCost TargetTransformInfo::getIntImmCostInst	(	unsigned	Opc,
		unsigned	Idx,
		const APInt &	Imm,
		Type *	Ty,
		TTI::TargetCostKind	CostKind,
		Instruction *	Inst = `nullptr`
	)		const

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction.

The cost can be zero if the immediate can be folded into the specified instruction.

Definition at line 607 of file TargetTransformInfo.cpp.

References assert(), Cost, CostKind, and llvm::RISCVMatInt::Imm.

◆ getIntImmCostIntrin()

InstructionCost TargetTransformInfo::getIntImmCostIntrin	(	Intrinsic::ID	IID,
		unsigned	Idx,
		const APInt &	Imm,
		Type *	Ty,
		TTI::TargetCostKind	CostKind
	)		const

Definition at line 617 of file TargetTransformInfo.cpp.

References assert(), Cost, CostKind, and llvm::RISCVMatInt::Imm.

◆ getIntrinsicInstrCost()

InstructionCost TargetTransformInfo::getIntrinsicInstrCost	(	const IntrinsicCostAttributes &	ICA,
		TTI::TargetCostKind	CostKind
	)		const

Returns

The cost of Intrinsic instructions. Analyses the real arguments. Three cases are handled: 1. scalar instruction 2. vector instruction

scalar instruction which is to be vectorized.

Definition at line 963 of file TargetTransformInfo.cpp.

References assert(), Cost, and CostKind.

Referenced by getVectorCallCosts(), llvm::LoopVectorizationCostModel::getVectorIntrinsicCost(), llvm::CostModelPrinterPass::run(), and tryToFPToSat().

◆ getLoadStoreVecRegBitWidth()

unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth ( unsigned AddrSpace ) const

Returns: The bitwidth of the largest vector type that should be used to load/store in the given address space.

Definition at line 1087 of file TargetTransformInfo.cpp.

◆ getLoadVectorFactor()

unsigned TargetTransformInfo::getLoadVectorFactor	(	unsigned	VF,
		unsigned	LoadSize,
		unsigned	ChainSizeInBytes,
		VectorType *	VecTy
	)		const

Returns: The new vector factor value if the target doesn't support SizeInBytes loads or has a better vector factor.

Definition at line 1120 of file TargetTransformInfo.cpp.

◆ getMaskedMemoryOpCost()

InstructionCost TargetTransformInfo::getMaskedMemoryOpCost	(	unsigned	Opcode,
		Type *	Src,
		Align	Alignment,
		unsigned	AddressSpace,
		TTI::TargetCostKind	CostKind = `TTI::TCK_RecipThroughput`
	)		const

Returns: The cost of masked Load and Store instructions.

Definition at line 933 of file TargetTransformInfo.cpp.

References assert(), Cost, and CostKind.

◆ getMaximumVF()

unsigned TargetTransformInfo::getMaximumVF	(	unsigned	ElemWidth,
		unsigned	Opcode
	)		const

Returns: The maximum vectorization factor for types of given element bit width and opcode, or 0 if there is no maximum VF. Currently only used by the SLP vectorizer.

Definition at line 666 of file TargetTransformInfo.cpp.

Referenced by llvm::slpvectorizer::BoUpSLP::getMaximumVF().

◆ getMaxInterleaveFactor()

unsigned TargetTransformInfo::getMaxInterleaveFactor ( unsigned VF ) const

Returns: The maximum interleave factor that any transform should try to perform for this target. This number depends on the level of parallelism and the number of execution units in the CPU.

Definition at line 720 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizePass::runImpl(), and llvm::LoopVectorizationCostModel::selectInterleaveCount().

◆ getMaxPrefetchIterationsAhead()

unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead ( ) const

Returns: The maximum number of iterations to prefetch ahead. If the required number of iterations is more than this number, no prefetching is performed.

Definition at line 708 of file TargetTransformInfo.cpp.

◆ getMaxVScale()

Optional< unsigned > TargetTransformInfo::getMaxVScale ( ) const

Returns: The maximum value of vscale if the target specifies an architectural maximum vector length, and None otherwise.

Definition at line 648 of file TargetTransformInfo.cpp.

◆ getMemcpyCost()

InstructionCost TargetTransformInfo::getMemcpyCost ( const Instruction * I ) const

Returns: the expected cost of a memcpy, which could e.g. depend on the source/destination type and alignment and the number of bytes copied.

Definition at line 991 of file TargetTransformInfo.cpp.

References assert(), Cost, and I.

◆ getMemcpyLoopLoweringType()

Type * TargetTransformInfo::getMemcpyLoopLoweringType	(	LLVMContext &	Context,
		Value *	Length,
		unsigned	SrcAddrSpace,
		unsigned	DestAddrSpace,
		unsigned	SrcAlign,
		unsigned	DestAlign,
		Optional< uint32_t >	AtomicElementSize = `None`
	)		const

Returns: The type to use in a loop expansion of a memcpy call.

Definition at line 1047 of file TargetTransformInfo.cpp.

References Context.

Referenced by llvm::createMemCpyLoopKnownSize().

◆ getMemcpyLoopResidualLoweringType()

void TargetTransformInfo::getMemcpyLoopResidualLoweringType	(	SmallVectorImpl< Type * > &	OpsOut,
		LLVMContext &	Context,
		unsigned	RemainingBytes,
		unsigned	SrcAddrSpace,
		unsigned	DestAddrSpace,
		unsigned	SrcAlign,
		unsigned	DestAlign,
		Optional< uint32_t >	AtomicCpySize = `None`
	)		const

Parameters

[out]	OpsOut	The operand types to copy RemainingBytes of memory.
	RemainingBytes	The number of bytes to copy.

Calculates the operand types to use when copying RemainingBytes of memory, where source and destination alignments are SrcAlign and DestAlign respectively.

Definition at line 1056 of file TargetTransformInfo.cpp.

References Context.

Referenced by llvm::createMemCpyLoopKnownSize().

◆ getMemoryOpCost()

InstructionCost TargetTransformInfo::getMemoryOpCost	(	unsigned	Opcode,
		Type *	Src,
		Align	Alignment,
		unsigned	AddressSpace,
		TTI::TargetCostKind	CostKind = `TTI::TCK_RecipThroughput`,
		TTI::OperandValueInfo	OpInfo = `{OK_AnyValue, OP_None}`,
		const Instruction *	I = `nullptr`
	)		const

Returns: The cost of Load and Store instructions.

Definition at line 921 of file TargetTransformInfo.cpp.

References assert(), Cost, CostKind, and I.

Referenced by findCostForOutputBlocks().

◆ getMinimumVF()

ElementCount TargetTransformInfo::getMinimumVF	(	unsigned	ElemWidth,
		bool	IsScalable
	)		const

Returns: The minimum vectorization factor for types of given element bit width, or 0 if there is no minimum VF. The returned value only applies when shouldMaximizeVectorBandwidth returns true. If IsScalable is true, the returned ElementCount must be a scalable VF.

Definition at line 661 of file TargetTransformInfo.cpp.

◆ getMinMaxReductionCost()

InstructionCost TargetTransformInfo::getMinMaxReductionCost	(	VectorType *	Ty,
		VectorType *	CondTy,
		bool	IsUnsigned,
		TTI::TargetCostKind	CostKind = `TTI::TCK_RecipThroughput`
	)		const

Definition at line 1006 of file TargetTransformInfo.cpp.

References assert(), Cost, and CostKind.

◆ getMinPrefetchStride()

unsigned TargetTransformInfo::getMinPrefetchStride	(	unsigned	NumMemAccesses,
		unsigned	NumStridedMemAccesses,
		unsigned	NumPrefetches,
		bool	HasCall
	)		const

Some HW prefetchers can handle accesses up to a certain constant stride.

Sometimes prefetching is beneficial even below the HW prefetcher limit, and the arguments provided are meant to serve as a basis for deciding this for a particular loop.

Parameters

NumMemAccesses	Number of memory accesses in the loop.
NumStridedMemAccesses	Number of the memory accesses that ScalarEvolution could find a known stride for.
NumPrefetches	Number of software prefetches that will be emitted as determined by the addresses involved and the cache line size.
HasCall	True if the loop contains a call.

Returns: This is the minimum stride in bytes where it makes sense to start adding SW prefetches. The default is 1, i.e. prefetch with any stride.

Definition at line 701 of file TargetTransformInfo.cpp.

◆ getMinTripCountTailFoldingThreshold()

unsigned TargetTransformInfo::getMinTripCountTailFoldingThreshold ( ) const

Returns: the lower bound of a trip count to decide on vectorization while tail-folding.

Definition at line 1157 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizePass::processLoop().

◆ getMinVectorRegisterBitWidth()

unsigned TargetTransformInfo::getMinVectorRegisterBitWidth ( ) const

Returns: The width of the smallest vector register type.

Definition at line 644 of file TargetTransformInfo.cpp.

Referenced by llvm::slpvectorizer::BoUpSLP::BoUpSLP().

◆ getMulAccReductionCost()

InstructionCost TargetTransformInfo::getMulAccReductionCost	(	bool	IsUnsigned,
		Type *	ResTy,
		VectorType *	Ty,
		TTI::TargetCostKind	CostKind = `TTI::TCK_RecipThroughput`
	)		const

Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add reduction with multiply and optional extensions.

This is the cost of as: ResTy vecreduce.add(mul (A, B)). ResTy vecreduce.add(mul(ext(Ty A), ext(Ty B)).

Definition at line 1022 of file TargetTransformInfo.cpp.

References CostKind.

◆ getNumberOfParts()

unsigned TargetTransformInfo::getNumberOfParts ( Type * Tp ) const

Returns: The number of pieces into which the provided type must be split during legalization. Zero is returned when the answer is unknown.

Definition at line 979 of file TargetTransformInfo.cpp.

Referenced by computeExtractCost(), and llvm::slpvectorizer::BoUpSLP::optimizeGatherSequence().

◆ getNumberOfRegisters()

unsigned TargetTransformInfo::getNumberOfRegisters ( unsigned ClassID ) const

Returns: the number of registers in the target-provided register class.

Definition at line 626 of file TargetTransformInfo.cpp.

Referenced by llvm::SLPVectorizerPass::runImpl(), llvm::LoopVectorizePass::runImpl(), and llvm::LoopVectorizationCostModel::selectInterleaveCount().

◆ getOperandInfo()

TargetTransformInfo::OperandValueInfo TargetTransformInfo::getOperandInfo ( const Value * V )

static

Collect properties of V used in cost analysis, e.g. OP_PowerOf2.

Definition at line 725 of file TargetTransformInfo.cpp.

References E, llvm::getSplatValue(), I, OK_AnyValue, OK_NonUniformConstantValue, OK_UniformConstantValue, OK_UniformValue, OP_NegatedPowerOf2, OP_None, and OP_PowerOf2.

Referenced by llvm::LoopVectorizationCostModel::getDivRemSpeculationCost(), llvm::TargetTransformInfoImplCRTPBase< AMDGPUTTIImpl >::getInstructionCost(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost().

◆ getOperandsScalarizationOverhead()

InstructionCost TargetTransformInfo::getOperandsScalarizationOverhead	(	ArrayRef< const Value * >	Args,
		ArrayRef< Type * >	Tys
	)		const

Estimate the overhead of scalarizing an instructions unique non-constant operands.

The (potentially vector) types to use for each of argument are passes via Tys.

Definition at line 518 of file TargetTransformInfo.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Key::Args.

◆ getOrCreateResultFromMemIntrinsic()

Value * TargetTransformInfo::getOrCreateResultFromMemIntrinsic	(	IntrinsicInst *	Inst,
		Type *	ExpectedType
	)		const

Returns: A value which is the result of the given memory intrinsic. New instructions may be created to extract the result from the given intrinsic memory operation. Returns nullptr if the target cannot create a result from the given intrinsic.

Definition at line 1042 of file TargetTransformInfo.cpp.

◆ getPeelingPreferences()

void TargetTransformInfo::getPeelingPreferences	(	Loop *	L,
		ScalarEvolution &	SE,
		PeelingPreferences &	PP
	)		const

Get target-customized preferences for the generic loop peeling transformation.

The caller will initialize PP with the current target-independent defaults with information from L and SE.

Definition at line 336 of file TargetTransformInfo.cpp.

Referenced by llvm::gatherPeelingPreferences().

◆ getPopcntSupport()

TargetTransformInfo::PopcntSupportKind TargetTransformInfo::getPopcntSupport ( unsigned IntTyWidthInBit ) const

Return hardware support for population count.

Definition at line 567 of file TargetTransformInfo.cpp.

◆ getPredicatedAddrSpace()

std::pair< const Value *, unsigned > TargetTransformInfo::getPredicatedAddrSpace ( const Value * V ) const

Definition at line 277 of file TargetTransformInfo.cpp.

◆ getPredictableBranchThreshold()

BranchProbability TargetTransformInfo::getPredictableBranchThreshold ( ) const

If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly.

Definition at line 233 of file TargetTransformInfo.cpp.

Referenced by FoldTwoEntryPHINode(), isFormingBranchFromSelectProfitable(), and shouldFoldCondBranchesToCommonDestination().

◆ getPreferredAddressingMode()

TTI::AddressingModeKind TargetTransformInfo::getPreferredAddressingMode	(	const Loop *	L,
		ScalarEvolution *	SE
	)		const

Return the preferred addressing mode LSR should make efforts to generate.

Definition at line 383 of file TargetTransformInfo.cpp.

◆ getPrefetchDistance()

unsigned TargetTransformInfo::getPrefetchDistance ( ) const

Returns: How much before a load we should place the prefetch instruction. This is currently measured in number of instructions.

Definition at line 697 of file TargetTransformInfo.cpp.

◆ getRegisterBitWidth()

TypeSize TargetTransformInfo::getRegisterBitWidth ( TargetTransformInfo::RegisterKind K ) const

Returns: The width of the largest scalar or vector register type.

Definition at line 639 of file TargetTransformInfo.cpp.

Referenced by llvm::slpvectorizer::BoUpSLP::BoUpSLP(), and llvm::LoopVectorizationPlanner::planInVPlanNativePath().

◆ getRegisterClassForType()

unsigned TargetTransformInfo::getRegisterClassForType	(	bool	Vector,
		Type *	Ty = `nullptr`
	)		const

Returns: the target-provided register class ID for the provided type, accounting for type promotion and other type-legalization techniques that the target might apply. However, it specifically does not account for the scalarization or splitting of vector types. Should a vector type require scalarization or splitting into multiple underlying vector registers, that type should be mapped to a register class containing no registers. Specifically, this is designed to provide a simple, high-level view of the register allocation later performed by the backend. These register classes don't necessarily map onto the register classes used by the backend. FIXME: It's not currently possible to determine how many registers are used by the provided type.

Definition at line 630 of file TargetTransformInfo.cpp.

References Vector.

Referenced by llvm::LoopVectorizationCostModel::calculateRegisterUsage(), llvm::SLPVectorizerPass::runImpl(), and llvm::LoopVectorizePass::runImpl().

◆ getRegisterClassName()

const char * TargetTransformInfo::getRegisterClassName ( unsigned ClassID ) const

Returns: the target-provided register class name

Definition at line 635 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizationCostModel::calculateRegisterUsage(), and llvm::LoopVectorizationCostModel::selectInterleaveCount().

◆ getRegUsageForType()

unsigned TargetTransformInfo::getRegUsageForType ( Type * Ty ) const

Returns the estimated number of registers required to represent Ty.

Definition at line 490 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizationCostModel::calculateRegisterUsage().

◆ getReplicationShuffleCost()

InstructionCost TargetTransformInfo::getReplicationShuffleCost	(	Type *	EltTy,
		int	ReplicationFactor,
		int	VF,
		const APInt &	DemandedDstElts,
		TTI::TargetCostKind	CostKind
	)

Returns: The cost of replication shuffle of VF elements typed EltTy ReplicationFactor times.

For example, the mask for ReplicationFactor=3 and VF=4 is: <0,0,0,1,1,1,2,2,2,3,3,3>

Definition at line 912 of file TargetTransformInfo.cpp.

References assert(), Cost, and CostKind.

◆ getScalarizationOverhead()

InstructionCost TargetTransformInfo::getScalarizationOverhead	(	VectorType *	Ty,
		const APInt &	DemandedElts,
		bool	Insert,
		bool	Extract
	)		const

Estimate the overhead of scalarizing an instruction.

Insert and Extract are set if the demanded result elements need to be inserted and/or extracted from vectors.

Definition at line 512 of file TargetTransformInfo.cpp.

References Insert.

Referenced by llvm::slpvectorizer::BoUpSLP::getTreeCost().

◆ getScalingFactorCost()

InstructionCost TargetTransformInfo::getScalingFactorCost	(	Type *	Ty,
		GlobalValue *	BaseGV,
		int64_t	BaseOffset,
		bool	HasBaseReg,
		int64_t	Scale,
		unsigned	AddrSpace = `0`
	)		const

Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type.

If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value. TODO: Handle pre/postinc as well.

Definition at line 463 of file TargetTransformInfo.cpp.

References assert(), and Cost.

Referenced by getScalingFactorCost().

◆ getShuffleCost()

InstructionCost TargetTransformInfo::getShuffleCost	(	ShuffleKind	Kind,
		VectorType *	Tp,
		ArrayRef< int >	Mask = `None`,
		TTI::TargetCostKind	CostKind = `TTI::TCK_RecipThroughput`,
		int	Index = `0`,
		VectorType *	SubTp = `nullptr`,
		ArrayRef< const Value * >	Args = `None`
	)		const

Returns: The cost of a shuffle instruction of kind Kind and of type Tp. The exact mask may be passed as Mask, or else the array will be empty. The index and subtype parameters are used by the subvector insertion and extraction shuffle kinds to show the insert/extract point and the type of the subvector being inserted/extracted. The operands of the shuffle can be passed through Args, which helps improve the cost estimation in some cases, like in broadcast loads. NOTE: For subvector extractions Tp represents the source type.

Definition at line 797 of file TargetTransformInfo.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), Cost, CostKind, and llvm::BitmaskEnumDetail::Mask().

Referenced by computeExtractCost(), and llvm::slpvectorizer::BoUpSLP::getTreeCost().

◆ getStoreMinimumVF()

unsigned TargetTransformInfo::getStoreMinimumVF	(	unsigned	VF,
		Type *	ScalarMemTy,
		Type *	ScalarValTy
	)		const

Returns: The minimum vectorization factor for the store instruction. Given the initial estimation of the minimum vector factor and store value type, it tries to find possible lowest VF, which still might be profitable for the vectorization.

Parameters

VF	Initial estimation of the minimum vector factor.
ScalarMemTy	Scalar memory type of the store operation.
ScalarValTy	Scalar type of the stored value. Currently only used by the SLP vectorizer.

Definition at line 671 of file TargetTransformInfo.cpp.

◆ getStoreVectorFactor()

unsigned TargetTransformInfo::getStoreVectorFactor	(	unsigned	VF,
		unsigned	StoreSize,
		unsigned	ChainSizeInBytes,
		VectorType *	VecTy
	)		const

Returns: The new vector factor value if the target doesn't support SizeInBytes stores or has a better vector factor.

Definition at line 1127 of file TargetTransformInfo.cpp.

◆ getTgtMemIntrinsic()

bool TargetTransformInfo::getTgtMemIntrinsic	(	IntrinsicInst *	Inst,
		MemIntrinsicInfo &	Info
	)		const

Returns: True if the intrinsic is a supported memory intrinsic. Info will contain additional information - whether the intrinsic may write or read to memory, volatility and the pointer. Info is undefined if false is returned.

Definition at line 1033 of file TargetTransformInfo.cpp.

References Info.

Referenced by getAccessType(), and isAddressUse().

◆ getUnrollingPreferences()

void TargetTransformInfo::getUnrollingPreferences	(	Loop *	L,
		ScalarEvolution &	SE,
		UnrollingPreferences &	UP,
		OptimizationRemarkEmitter *	ORE
	)		const

Get target-customized preferences for the generic loop unrolling transformation.

The caller will initialize UP with the current target-independent defaults.

Definition at line 330 of file TargetTransformInfo.cpp.

Referenced by llvm::gatherUnrollingPreferences().

◆ getVectorInstrCost() [1/2]

InstructionCost TargetTransformInfo::getVectorInstrCost	(	const Instruction &	I,
		Type *	Val,
		unsigned	Index = `-1`
	)		const

Returns: The expected cost of vector Insert and Extract. This is used when instruction is available, and implementation asserts 'I' is not nullptr.

A typical suitable use case is cost estimation when vector instruction exists (e.g., from basic blocks during transformation).

Definition at line 901 of file TargetTransformInfo.cpp.

References assert(), Cost, and I.

◆ getVectorInstrCost() [2/2]

InstructionCost TargetTransformInfo::getVectorInstrCost	(	unsigned	Opcode,
		Type *	Val,
		unsigned	Index = `-1`
	)		const

Returns: The expected cost of vector Insert and Extract. Use -1 to indicate that there is no information on the index value. This is used when the instruction is not available; a typical use case is to provision the cost of vectorization/scalarization in vectorizer passes.

Definition at line 890 of file TargetTransformInfo.cpp.

References assert(), and Cost.

Referenced by llvm::slpvectorizer::BoUpSLP::getTreeCost().

◆ getVPLegalizationStrategy()

TargetTransformInfo::VPLegalization TargetTransformInfo::getVPLegalizationStrategy ( const VPIntrinsic & PI ) const

Returns: How the target needs this vector-predicated operation to be transformed.

Definition at line 1145 of file TargetTransformInfo.cpp.

◆ getVPMemoryOpCost()

InstructionCost llvm::TargetTransformInfo::getVPMemoryOpCost	(	unsigned	Opcode,
		Type *	Src,
		Align	Alignment,
		unsigned	AddressSpace,
		TTI::TargetCostKind	CostKind = `TTI::TCK_RecipThroughput`,
		const Instruction *	I = `nullptr`
	)		const

Returns: The cost of VP Load and Store instructions.

◆ getVScaleForTuning()

Optional< unsigned > TargetTransformInfo::getVScaleForTuning ( ) const

Returns: the value of vscale to tune the cost model for.

Definition at line 652 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizationCostModel::getVScaleForTuning().

◆ hasActiveVectorLength()

bool TargetTransformInfo::hasActiveVectorLength	(	unsigned	Opcode,
		Type *	DataType,
		Align	Alignment
	)		const

Definition at line 1169 of file TargetTransformInfo.cpp.

◆ hasBranchDivergence()

bool TargetTransformInfo::hasBranchDivergence ( ) const

Return true if branch divergence exists.

Branch divergence has a significantly negative impact on GPU performance when threads in the same wavefront take different paths due to conditional branches.

Definition at line 237 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizationCostModel::computeMaxVF(), llvm::JumpThreadingPass::run(), llvm::SpeculativeExecutionPass::runImpl(), llvm::LegacyDivergenceAnalysis::runOnFunction(), and unswitchLoop().

◆ hasDivRemOp()

bool TargetTransformInfo::hasDivRemOp	(	Type *	DataType,
		bool	IsSigned
	)		const

Return true if the target has a unified operation to calculate division and remainder.

If so, the additional implicit multiplication and subtraction required to calculate a remainder from division are free. This can enable more aggressive transformations for division and remainder than would typically be allowed using throughput or size cost models.

Definition at line 450 of file TargetTransformInfo.cpp.

Referenced by optimizeDivRem().

◆ hasVolatileVariant()

bool TargetTransformInfo::hasVolatileVariant	(	Instruction *	I,
		unsigned	AddrSpace
	)		const

Return true if the given instruction (assumed to be a memory access instruction) has a volatile variant.

If that's the case then we can avoid addrspacecast to generic AS for volatile loads/stores. Default implementation returns false, which prevents address space inference for volatile loads/stores.

Definition at line 454 of file TargetTransformInfo.cpp.

References I.

Referenced by isSimplePointerUseValidToReplace().

◆ haveFastSqrt()

bool TargetTransformInfo::haveFastSqrt ( Type * Ty ) const

Return true if the hardware has a fast square-root instruction.

Definition at line 571 of file TargetTransformInfo.cpp.

Referenced by foldSqrt(), and runPartiallyInlineLibCalls().

◆ instCombineIntrinsic()

Optional< Instruction * > TargetTransformInfo::instCombineIntrinsic	(	InstCombiner &	IC,
		IntrinsicInst &	II
	)		const

Targets can implement their own combinations for target-specific intrinsics.

This function will be called from the InstCombine pass every time a target-specific intrinsic is encountered.

Returns: None to not do anything target specific or a value that will be returned from the InstCombiner. It is possible to return null and stop further processing of the intrinsic by returning nullptr.

Definition at line 308 of file TargetTransformInfo.cpp.

Referenced by llvm::InstCombiner::targetInstCombineIntrinsic().

◆ invalidate()

bool llvm::TargetTransformInfo::invalidate	(	Function &	,
		const PreservedAnalyses &	,
		FunctionAnalysisManager::Invalidator &
	)

inline

Handle the invalidation of this information.

When used as a result of TargetIRAnalysis this method will be called when the function this was computed for changes. When it returns false, the information is preserved across those changes.

Definition at line 201 of file TargetTransformInfo.h.

◆ isAlwaysUniform()

bool llvm::TargetTransformInfo::isAlwaysUniform ( const Value * V ) const

Definition at line 249 of file TargetTransformInfo.cpp.

Referenced by llvm::DivergenceInfo::DivergenceInfo().

◆ isElementTypeLegalForScalableVector()

bool TargetTransformInfo::isElementTypeLegalForScalableVector ( Type * Ty ) const

Returns: True if the given type is supported for scalable vectors

Definition at line 1116 of file TargetTransformInfo.cpp.

◆ isExpensiveToSpeculativelyExecute()

bool TargetTransformInfo::isExpensiveToSpeculativelyExecute ( const Instruction * I ) const

Return true if the cost of the instruction is too high to speculatively execute and should be kept behind a branch.

This normally just wraps around a getInstructionCost() call, but some targets might report a low TCK_SizeAndLatency value that is incompatible with the fixed TCC_Expensive value. NOTE: This assumes the instruction passes isSafeToSpeculativelyExecute().

Definition at line 575 of file TargetTransformInfo.cpp.

References I.

Referenced by sinkSelectOperand().

◆ isFCmpOrdCheaperThanFCmpZero()

bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero ( Type * Ty ) const

Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a comparison against a constant FP zero value.

Targets should override this if materializing a 0.0 for comparison is generally as cheap as checking for ordered/unordered.

Definition at line 580 of file TargetTransformInfo.cpp.

Referenced by optimizeSQRT().

◆ isFPVectorizationPotentiallyUnsafe()

bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe ( ) const

Indicate that it is potentially unsafe to automatically vectorize floating-point operations because the semantics of vector and scalar floating-point semantics may differ.

For example, ARM NEON v7 SIMD math does not support IEEE-754 denormal numbers, while depending on the platform, scalar floating-point math does. This applies to floating-point math operations and calls, not memory operations, shuffles, or casts.

Definition at line 553 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizePass::processLoop().

◆ isHardwareLoopProfitable()

bool TargetTransformInfo::isHardwareLoopProfitable	(	Loop *	L,
		ScalarEvolution &	SE,
		AssumptionCache &	AC,
		TargetLibraryInfo *	LibInfo,
		HardwareLoopInfo &	HWLoopInfo
	)		const

Query the target whether it would be profitable to convert the given loop into a hardware loop.

Definition at line 290 of file TargetTransformInfo.cpp.

◆ isIndexedLoadLegal()

bool TargetTransformInfo::isIndexedLoadLegal	(	enum MemIndexedMode	Mode,
		Type *	Ty
	)		const

Returns: True if the specified indexed load for the given type is legal.

Definition at line 1077 of file TargetTransformInfo.cpp.

References Mode.

Referenced by mayUsePostIncMode().

◆ isIndexedStoreLegal()

bool TargetTransformInfo::isIndexedStoreLegal	(	enum MemIndexedMode	Mode,
		Type *	Ty
	)		const

Returns: True if the specified indexed store for the given type is legal.

Definition at line 1082 of file TargetTransformInfo.cpp.

References Mode.

Referenced by mayUsePostIncMode().

◆ isLegalAddImmediate()

bool TargetTransformInfo::isLegalAddImmediate ( int64_t Imm ) const

Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register.

Definition at line 341 of file TargetTransformInfo.cpp.

References llvm::RISCVMatInt::Imm.

◆ isLegalAddressingMode()

bool TargetTransformInfo::isLegalAddressingMode	(	Type *	Ty,
		GlobalValue *	BaseGV,
		int64_t	BaseOffset,
		bool	HasBaseReg,
		int64_t	Scale,
		unsigned	AddrSpace = `0`,
		Instruction *	I = `nullptr`
	)		const

Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

The type may be VoidTy, in which case only return true if the addressing mode is legal for a load/store of any legal type. If target returns true in LSRWithInstrQueries(), I may be valid. TODO: Handle pre/postinc as well.

Definition at line 349 of file TargetTransformInfo.cpp.

References I.

Referenced by isAddFoldable(), and isAMCompletelyFolded().

◆ isLegalAltInstr()

bool TargetTransformInfo::isLegalAltInstr	(	VectorType *	VecTy,
		unsigned	Opcode0,
		unsigned	Opcode1,
		const SmallBitVector &	OpcodeMask
	)		const

Return true if this is an alternating opcode pattern that can be lowered to a single instruction on the target.

In X86 this is for the addsub instruction which corrsponds to a Shuffle + Fadd + FSub pattern in IR. This function expectes two opcodes: Opcode1 and Opcode2 being selected by OpcodeMask. The mask contains one bit per lane and is a 0 when Opcode0 is selected and 1 when Opcode1 is selected. VecTy is the vector type of the instruction to be generated.

Definition at line 417 of file TargetTransformInfo.cpp.

Referenced by llvm::slpvectorizer::BoUpSLP::reorderTopToBottom().

◆ isLegalBroadcastLoad()

bool TargetTransformInfo::isLegalBroadcastLoad	(	Type *	ElementTy,
		ElementCount	NumElements
	)		const

\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy>.

Definition at line 407 of file TargetTransformInfo.cpp.

◆ isLegalICmpImmediate()

bool TargetTransformInfo::isLegalICmpImmediate ( int64_t Imm ) const

Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

Definition at line 345 of file TargetTransformInfo.cpp.

References llvm::RISCVMatInt::Imm.

Referenced by isAMCompletelyFolded().

◆ isLegalMaskedCompressStore()

bool TargetTransformInfo::isLegalMaskedCompressStore ( Type * DataType ) const

Return true if the target supports masked compress store.

Definition at line 438 of file TargetTransformInfo.cpp.

Referenced by optimizeCallInst().

◆ isLegalMaskedExpandLoad()

bool TargetTransformInfo::isLegalMaskedExpandLoad ( Type * DataType ) const

Return true if the target supports masked expand load.

Definition at line 442 of file TargetTransformInfo.cpp.

Referenced by optimizeCallInst().

◆ isLegalMaskedGather()

bool TargetTransformInfo::isLegalMaskedGather	(	Type *	DataType,
		Align	Alignment
	)		const

Return true if the target supports masked gather.

Definition at line 412 of file TargetTransformInfo.cpp.

Referenced by canVectorizeLoads(), llvm::LoopVectorizationCostModel::isLegalGatherOrScatter(), llvm::LoopVectorizationCostModel::isScalarWithPredication(), and optimizeCallInst().

◆ isLegalMaskedLoad()

bool TargetTransformInfo::isLegalMaskedLoad	(	Type *	DataType,
		Align	Alignment
	)		const

Return true if the target supports masked load.

Definition at line 393 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizationCostModel::interleavedAccessCanBeWidened(), llvm::LoopVectorizationCostModel::isLegalMaskedLoad(), and optimizeCallInst().

◆ isLegalMaskedScatter()

bool TargetTransformInfo::isLegalMaskedScatter	(	Type *	DataType,
		Align	Alignment
	)		const

Return true if the target supports masked scatter.

Definition at line 423 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizationCostModel::isLegalGatherOrScatter(), llvm::LoopVectorizationCostModel::isScalarWithPredication(), and optimizeCallInst().

◆ isLegalMaskedStore()

bool TargetTransformInfo::isLegalMaskedStore	(	Type *	DataType,
		Align	Alignment
	)		const

Return true if the target supports masked store.

Definition at line 388 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizationCostModel::interleavedAccessCanBeWidened(), llvm::LoopVectorizationCostModel::isLegalMaskedStore(), and optimizeCallInst().

◆ isLegalNTLoad()

bool TargetTransformInfo::isLegalNTLoad	(	Type *	DataType,
		Align	Alignment
	)		const

Return true if the target supports nontemporal load.

Definition at line 403 of file TargetTransformInfo.cpp.

◆ isLegalNTStore()

bool TargetTransformInfo::isLegalNTStore	(	Type *	DataType,
		Align	Alignment
	)		const

Return true if the target supports nontemporal store.

Definition at line 398 of file TargetTransformInfo.cpp.

◆ isLegalToVectorizeLoad()

bool TargetTransformInfo::isLegalToVectorizeLoad ( LoadInst * LI ) const

Returns: True if the load instruction is legal to vectorize.

Definition at line 1091 of file TargetTransformInfo.cpp.

◆ isLegalToVectorizeLoadChain()

bool TargetTransformInfo::isLegalToVectorizeLoadChain	(	unsigned	ChainSizeInBytes,
		Align	Alignment,
		unsigned	AddrSpace
	)		const

Returns: True if it is legal to vectorize the given load chain.

Definition at line 1099 of file TargetTransformInfo.cpp.

◆ isLegalToVectorizeReduction()

bool TargetTransformInfo::isLegalToVectorizeReduction	(	const RecurrenceDescriptor &	RdxDesc,
		ElementCount	VF
	)		const

Returns: True if it is legal to vectorize the given reduction kind.

Definition at line 1111 of file TargetTransformInfo.cpp.

◆ isLegalToVectorizeStore()

bool TargetTransformInfo::isLegalToVectorizeStore ( StoreInst * SI ) const

Returns: True if the store instruction is legal to vectorize.

Definition at line 1095 of file TargetTransformInfo.cpp.

References SI.

◆ isLegalToVectorizeStoreChain()

bool TargetTransformInfo::isLegalToVectorizeStoreChain	(	unsigned	ChainSizeInBytes,
		Align	Alignment,
		unsigned	AddrSpace
	)		const

Returns: True if it is legal to vectorize the given store chain.

Definition at line 1105 of file TargetTransformInfo.cpp.

◆ isLoweredToCall()

bool TargetTransformInfo::isLoweredToCall ( const Function * F ) const

Test whether calls to a function lower to actual program function calls.

The idea is to test whether the program is likely to require a 'call' instruction or equivalent in order to call the given function.

FIXME: It's not clear that this is a good or useful query API. Client's should probably move to simpler cost metrics using the above. Alternatively, we could split the cost interface into distinct code-size and execution-speed costs. This would allow modelling the core of this query more accurately as a call is a single small instruction, but incurs significant execution cost.

Definition at line 286 of file TargetTransformInfo.cpp.

References F.

Referenced by llvm::CodeMetrics::analyzeBasicBlock(), analyzeLoopUnrollCost(), and runCGProfilePass().

◆ isLSRCostLess()

bool TargetTransformInfo::isLSRCostLess	(	const TargetTransformInfo::LSRCost &	C1,
		const TargetTransformInfo::LSRCost &	C2
	)		const

Return true if LSR cost of C1 is lower than C2.

Definition at line 358 of file TargetTransformInfo.cpp.

References C1.

◆ isNoopAddrSpaceCast()

bool TargetTransformInfo::isNoopAddrSpaceCast	(	unsigned	FromAS,
		unsigned	ToAS
	)		const

Definition at line 262 of file TargetTransformInfo.cpp.

Referenced by isNoopPtrIntCastPair().

◆ isNumRegsMajorCostOfLSR()

bool TargetTransformInfo::isNumRegsMajorCostOfLSR ( ) const

Return true if LSR major cost is number of registers.

Targets which implement their own isLSRCostLess and unset number of registers as major cost should return false, otherwise return true.

Definition at line 363 of file TargetTransformInfo.cpp.

◆ isProfitableLSRChainElement()

bool TargetTransformInfo::isProfitableLSRChainElement ( Instruction * I ) const

Returns: true if LSR should not optimize a chain that includes I.

Definition at line 367 of file TargetTransformInfo.cpp.

References I.

Referenced by isProfitableChain().

◆ isProfitableToHoist()

bool TargetTransformInfo::isProfitableToHoist ( Instruction * I ) const

Return true if it is profitable to hoist instruction in the then/else to before if.

Definition at line 480 of file TargetTransformInfo.cpp.

References I.

◆ isSourceOfDivergence()

bool TargetTransformInfo::isSourceOfDivergence ( const Value * V ) const

Returns whether V is a source of divergence.

This function provides the target-dependent information for the target-independent LegacyDivergenceAnalysis. LegacyDivergenceAnalysis first builds the dependency graph, and then runs the reachability algorithm starting with the sources of divergence.

Definition at line 245 of file TargetTransformInfo.cpp.

Referenced by llvm::DivergenceInfo::DivergenceInfo().

◆ isTruncateFree()

bool TargetTransformInfo::isTruncateFree	(	Type *	Ty1,
		Type *	Ty2
	)		const

Return true if it's free to truncate a value of type Ty1 to type Ty2.

e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX.

Definition at line 476 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizationCostModel::isOptimizableIVTruncate(), and llvm::SCEVExpander::replaceCongruentIVs().

◆ isTypeLegal()

bool TargetTransformInfo::isTypeLegal ( Type * Ty ) const

Return true if this type is legal.

Definition at line 486 of file TargetTransformInfo.cpp.

Referenced by llvm::computeMinimumValueSizes(), foldConsecutiveLoads(), isLoadCombineCandidateImpl(), and isTypeLegalForLookupTable().

◆ LSRWithInstrQueries()

bool TargetTransformInfo::LSRWithInstrQueries ( ) const

Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAddressingMode().

This is needed on SystemZ, where e.g. a memcpy can only have a 12 bit unsigned immediate offset and no index register.

Definition at line 472 of file TargetTransformInfo.cpp.

Referenced by isAMCompletelyFolded().

◆ operator=()

TargetTransformInfo & TargetTransformInfo::operator= ( TargetTransformInfo && RHS )

Definition at line 192 of file TargetTransformInfo.cpp.

References move, and RHS.

◆ preferInLoopReduction()

bool TargetTransformInfo::preferInLoopReduction	(	unsigned	Opcode,
		Type *	Ty,
		ReductionFlags	Flags
	)		const

Returns: True if the target prefers reductions in loop.

Definition at line 1134 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizationCostModel::collectElementTypesForWidening(), and llvm::LoopVectorizationCostModel::collectInLoopReductions().

◆ preferPredicatedReductionSelect()

bool TargetTransformInfo::preferPredicatedReductionSelect	(	unsigned	Opcode,
		Type *	Ty,
		ReductionFlags	Flags
	)		const

Returns: True if the target prefers reductions select kept in the loop when tail folding. i.e. loop: p = phi (0, s) a = add (p, x) s = select (mask, a, p) vecreduce.add(s)

As opposed to the normal scheme of p = phi (0, a) which allows the select to be pulled out of the loop. If the select(.., add, ..) can be predicated by the target, this can lead to cleaner code generation.

Definition at line 1139 of file TargetTransformInfo.cpp.

Referenced by llvm::InnerLoopVectorizer::fixReduction().

◆ preferPredicateOverEpilogue()

bool TargetTransformInfo::preferPredicateOverEpilogue	(	Loop *	L,
		LoopInfo *	LI,
		ScalarEvolution &	SE,
		AssumptionCache &	AC,
		TargetLibraryInfo *	TLI,
		DominatorTree *	DT,
		LoopVectorizationLegality *	LVL,
		InterleavedAccessInfo *	IAI
	)		const

Query the target whether it would be prefered to create a predicated vector loop, which can avoid the need to emit a scalar epilogue loop.

Definition at line 296 of file TargetTransformInfo.cpp.

Referenced by getScalarEpilogueLowering().

◆ prefersVectorizedAddressing()

bool TargetTransformInfo::prefersVectorizedAddressing ( ) const

Return true if target doesn't mind addresses in vectors.

Definition at line 459 of file TargetTransformInfo.cpp.

Referenced by llvm::LoopVectorizationCostModel::setCostBasedWideningDecision().

◆ requiresOrderedReduction()

static bool llvm::TargetTransformInfo::requiresOrderedReduction ( Optional< FastMathFlags > FMF )

inlinestatic

A helper function to determine the type of reduction algorithm used for a given Opcode and set of FastMathFlags FMF.

Definition at line 1264 of file TargetTransformInfo.h.

References llvm::None.

Referenced by llvm::RISCVTTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::GCNTTIImpl::getArithmeticReductionCost(), llvm::ARMTTIImpl::getArithmeticReductionCost(), llvm::AArch64TTIImpl::getArithmeticReductionCost(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticReductionCost().

◆ rewriteIntrinsicWithAddressSpace()

Value * TargetTransformInfo::rewriteIntrinsicWithAddressSpace	(	IntrinsicInst *	II,
		Value *	OldV,
		Value *	NewV
	)		const

Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address space.

This should happen for every operand index that collectFlatAddressOperands returned for the intrinsic.

Returns: nullptr if the intrinsic was not handled. Otherwise, returns the new value (which may be the original II with modified operands).

Definition at line 281 of file TargetTransformInfo.cpp.

◆ shouldBuildLookupTables()

bool TargetTransformInfo::shouldBuildLookupTables ( ) const

Return true if switches should be turned into lookup tables for the target.

Definition at line 494 of file TargetTransformInfo.cpp.

Referenced by SwitchToLookupTable().

◆ shouldBuildLookupTablesForConstant()

bool TargetTransformInfo::shouldBuildLookupTablesForConstant ( Constant * C ) const

Return true if switches should be turned into lookup tables containing this constant value for the target.

Definition at line 498 of file TargetTransformInfo.cpp.

Referenced by ValidLookupTableConstant().

◆ shouldBuildRelLookupTables()

bool TargetTransformInfo::shouldBuildRelLookupTables ( ) const

Return true if lookup tables should be turned into relative lookup tables.

Definition at line 503 of file TargetTransformInfo.cpp.

◆ shouldConsiderAddressTypePromotion()

bool TargetTransformInfo::shouldConsiderAddressTypePromotion	(	const Instruction &	I,
		bool &	AllowPromotionWithoutCommonHeader
	)		const

Returns: True if it should be considered for address type promotion. AllowPromotionWithoutCommonHeader Set true if promoting I is profitable without finding other extensions fed by the same input.

Definition at line 676 of file TargetTransformInfo.cpp.

References I.

◆ shouldExpandReduction()

bool TargetTransformInfo::shouldExpandReduction ( const IntrinsicInst * II ) const

Returns: True if the target wants to expand the given reduction intrinsic into a shuffle sequence.

Definition at line 1149 of file TargetTransformInfo.cpp.

◆ shouldMaximizeVectorBandwidth()

bool TargetTransformInfo::shouldMaximizeVectorBandwidth ( TargetTransformInfo::RegisterKind K ) const

Returns: True if the vectorization factor should be chosen to make the vector of the smallest element type match the size of a vector register. For wider element types, this could result in creating vectors that span multiple vector registers. If false, the vectorization factor will be chosen based on the size of the widest element type. K Register Kind for vectorization.

Definition at line 656 of file TargetTransformInfo.cpp.

◆ shouldPrefetchAddressSpace()

bool TargetTransformInfo::shouldPrefetchAddressSpace ( unsigned AS ) const

Returns: if target want to issue a prefetch in address space AS.

Definition at line 716 of file TargetTransformInfo.cpp.

◆ simplifyDemandedUseBitsIntrinsic()

Optional< Value * > TargetTransformInfo::simplifyDemandedUseBitsIntrinsic	(	InstCombiner &	IC,
		IntrinsicInst &	II,
		APInt	DemandedMask,
		KnownBits &	Known,
		bool &	KnownBitsComputed
	)		const

Can be used to implement target-specific instruction combining.

See also: instCombineIntrinsic

Definition at line 313 of file TargetTransformInfo.cpp.

Referenced by llvm::InstCombiner::targetSimplifyDemandedUseBitsIntrinsic().

◆ simplifyDemandedVectorEltsIntrinsic()

Optional< Value * > TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic	(	InstCombiner &	IC,
		IntrinsicInst &	II,
		APInt	DemandedElts,
		APInt &	UndefElts,
		APInt &	UndefElts2,
		APInt &	UndefElts3,
		std::function< void(Instruction *, unsigned, APInt, APInt &)>	SimplifyAndSetOp
	)		const

Can be used to implement target-specific instruction combining.

See also: instCombineIntrinsic

Definition at line 320 of file TargetTransformInfo.cpp.

Referenced by llvm::InstCombiner::targetSimplifyDemandedVectorEltsIntrinsic().

◆ supportsEfficientVectorElementLoadStore()

bool TargetTransformInfo::supportsEfficientVectorElementLoadStore ( ) const

If target has efficient vector element load/store instructions, it can return true here so that insertion/extraction costs are not added to the scalarization cost of a load/store.

Definition at line 523 of file TargetTransformInfo.cpp.

◆ supportsScalableVectors()

bool TargetTransformInfo::supportsScalableVectors ( ) const

Returns: True if the target supports scalable vectors.

Definition at line 1161 of file TargetTransformInfo.cpp.

◆ supportsTailCallFor()

bool TargetTransformInfo::supportsTailCallFor ( const CallBase * CB ) const

If target supports tail call on CB.

Definition at line 531 of file TargetTransformInfo.cpp.

Referenced by addMustTailToCoroResumes().

◆ supportsTailCalls()

bool TargetTransformInfo::supportsTailCalls ( ) const

If the target supports tail calls.

Definition at line 527 of file TargetTransformInfo.cpp.

Referenced by splitSwitchCoroutine().

◆ useAA()

bool TargetTransformInfo::useAA ( ) const

Definition at line 484 of file TargetTransformInfo.cpp.

◆ useColdCCForColdCall()

bool TargetTransformInfo::useColdCCForColdCall ( Function & F ) const

Return true if the input function which is cold at all call sites, should use coldcc calling convention.

Definition at line 507 of file TargetTransformInfo.cpp.

References F.

Referenced by OptimizeFunctions().

◆ useGPUDivergenceAnalysis()

bool TargetTransformInfo::useGPUDivergenceAnalysis ( ) const

Return true if the target prefers to use GPU divergence analysis to replace the legacy version.

Definition at line 241 of file TargetTransformInfo.cpp.

The documentation for this class was generated from the following files:

include/llvm/Analysis/TargetTransformInfo.h
lib/Analysis/TargetTransformInfo.cpp

Classes

Public Member Functions

Generic Target Information

Scalar Target Information

Vector Target Information

Detailed Description

Member Enumeration Documentation

◆ AddressingModeKind

◆ CacheLevel

◆ CastContextHint

◆ MemIndexedMode

◆ OperandValueKind

◆ OperandValueProperties

◆ PopcntSupportKind

◆ RegisterKind

◆ ShuffleKind

◆ TargetCostConstants

◆ TargetCostKind

Constructor & Destructor Documentation

◆ TargetTransformInfo() [1/3]

◆ TargetTransformInfo() [2/3]

◆ TargetTransformInfo() [3/3]

◆ ~TargetTransformInfo()

Member Function Documentation

◆ adjustInliningThreshold()

◆ allowsMisalignedMemoryAccesses()

◆ areInlineCompatible()

◆ areTypesABICompatible()

◆ canHaveNonUndefGlobalInitializerInAddressSpace()

◆ canMacroFuseCmp()

◆ canSaveCmp()

◆ collectFlatAddressOperands()

◆ emitGetActiveLaneMask()

◆ enableAggressiveInterleaving()

◆ enableInterleavedAccessVectorization()

◆ enableMaskedInterleavedAccessVectorization()

◆ enableMemCmpExpansion()

◆ enableOrderedReductions()

◆ enableScalableVectorization()

◆ enableWritePrefetching()

◆ forceScalarizeMaskedGather()

◆ forceScalarizeMaskedScatter()

◆ getAddressComputationCost()

◆ getArithmeticInstrCost()

◆ getArithmeticReductionCost()

◆ getAssumedAddrSpace()

◆ getAtomicMemIntrinsicMaxElementSize()

◆ getCacheAssociativity()

◆ getCacheLineSize()

◆ getCacheSize()

◆ getCallInstrCost()

◆ getCastContextHint()

◆ getCastInstrCost()

◆ getCFInstrCost()

◆ getCmpSelInstrCost()

◆ getCostOfKeepingLiveOverCall()

◆ getEstimatedNumberOfCaseClusters()

◆ getExtendedReductionCost()

◆ getExtractWithExtendCost()

◆ getFlatAddressSpace()

◆ getFPOpCost()

◆ getGatherScatterOpCost()

◆ getGEPCost()

◆ getGISelRematGlobalCost()

◆ getInlinerVectorBonusPercent()

◆ getInliningThresholdMultiplier()

◆ getInstructionCost() [1/2]

◆ getInstructionCost() [2/2]

◆ getInterleavedMemoryOpCost()

◆ getIntImmCodeSizeCost()

◆ getIntImmCost()

◆ getIntImmCostInst()

◆ getIntImmCostIntrin()

◆ getIntrinsicInstrCost()

◆ getLoadStoreVecRegBitWidth()

◆ getLoadVectorFactor()

◆ getMaskedMemoryOpCost()

◆ getMaximumVF()

◆ getMaxInterleaveFactor()

◆ getMaxPrefetchIterationsAhead()