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21 #ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
22 #define LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
121 Type *RetTy =
nullptr;
134 bool TypeBasedOnly =
false);
377 std::pair<const Value *, unsigned>
563 KnownBits & Known,
bool &KnownBitsComputed)
const;
570 SimplifyAndSetOp)
const;
604 bool HasBaseReg, int64_t Scale,
605 unsigned AddrSpace = 0,
708 int64_t BaseOffset,
bool HasBaseReg,
710 unsigned AddrSpace = 0)
const;
754 const APInt &DemandedElts,
755 bool Insert,
bool Extract,
808 bool IsZeroCmp)
const;
834 unsigned *Fast =
nullptr)
const;
1002 unsigned getMaximumVF(
unsigned ElemWidth,
unsigned Opcode)
const;
1013 Type *ScalarValTy)
const;
1019 const Instruction &
I,
bool &AllowPromotionWithoutCommonHeader)
const;
1063 unsigned NumStridedMemAccesses,
1064 unsigned NumPrefetches,
bool HasCall)
const;
1102 unsigned Opcode,
Type *Ty,
1106 ArrayRef<const Value *>
Args = ArrayRef<const Value *>(),
1107 const Instruction *CxtI =
nullptr)
const;
1119 ArrayRef<int>
Mask = std::nullopt,
1122 ArrayRef<const Value *>
Args = std::nullopt)
const;
1173 unsigned Index)
const;
1201 Value *Op1 =
nullptr)
const;
1211 unsigned Index = -1)
const;
1220 const APInt &DemandedDstElts,
1229 const Instruction *
I =
nullptr)
const;
1236 const Instruction *
I =
nullptr)
const;
1253 unsigned Opcode, Type *DataTy,
const Value *
Ptr,
bool VariableMask,
1255 const Instruction *
I =
nullptr)
const;
1268 unsigned Opcode, Type *VecTy,
unsigned Factor, ArrayRef<unsigned> Indices,
1271 bool UseMaskForCond =
false,
bool UseMaskForGaps =
false)
const;
1276 return FMF && !(*FMF).allowReassoc();
1304 unsigned Opcode,
VectorType *Ty, std::optional<FastMathFlags> FMF,
1326 std::optional<FastMathFlags> FMF,
1353 const SCEV *
Ptr =
nullptr)
const;
1377 Type *ExpectedType)
const;
1382 unsigned DestAddrSpace,
unsigned SrcAlign,
unsigned DestAlign,
1383 std::optional<uint32_t> AtomicElementSize = std::nullopt)
const;
1393 unsigned RemainingBytes,
unsigned SrcAddrSpace,
unsigned DestAddrSpace,
1394 unsigned SrcAlign,
unsigned DestAlign,
1395 std::optional<uint32_t> AtomicCpySize = std::nullopt)
const;
1436 unsigned AddrSpace)
const;
1440 unsigned AddrSpace)
const;
1452 unsigned ChainSizeInBytes,
1458 unsigned ChainSizeInBytes,
1518 Align Alignment)
const;
1563 template <
typename T>
class Model;
1565 std::unique_ptr<Concept> TTIImpl;
1599 virtual std::pair<const Value *, unsigned>
1603 Value *NewV)
const = 0;
1624 KnownBits & Known,
bool &KnownBitsComputed) = 0;
1629 SimplifyAndSetOp) = 0;
1633 int64_t BaseOffset,
bool HasBaseReg,
1634 int64_t Scale,
unsigned AddrSpace,
1655 Align Alignment) = 0;
1657 Align Alignment) = 0;
1669 bool HasBaseReg, int64_t Scale,
1670 unsigned AddrSpace) = 0;
1674 virtual bool useAA() = 0;
1682 const APInt &DemandedElts,
1683 bool Insert,
bool Extract,
1703 unsigned *Fast) = 0;
1722 Type *Ty =
nullptr)
const = 0;
1726 virtual std::optional<unsigned>
getMaxVScale()
const = 0;
1731 bool IsScalable)
const = 0;
1732 virtual unsigned getMaximumVF(
unsigned ElemWidth,
unsigned Opcode)
const = 0;
1734 Type *ScalarValTy)
const = 0;
1736 const Instruction &
I,
bool &AllowPromotionWithoutCommonHeader) = 0;
1754 unsigned NumStridedMemAccesses,
1755 unsigned NumPrefetches,
1756 bool HasCall)
const = 0;
1786 unsigned Index) = 0;
1801 unsigned Index) = 0;
1805 const APInt &DemandedDstElts,
1823 bool VariableMask,
Align Alignment,
1830 bool UseMaskForCond =
false,
bool UseMaskForGaps =
false) = 0;
1833 std::optional<FastMathFlags> FMF,
1840 std::optional<FastMathFlags> FMF,
1860 Type *ExpectedType) = 0;
1863 unsigned DestAddrSpace,
unsigned SrcAlign,
unsigned DestAlign,
1864 std::optional<uint32_t> AtomicElementSize)
const = 0;
1868 unsigned RemainingBytes,
unsigned SrcAddrSpace,
unsigned DestAddrSpace,
1869 unsigned SrcAlign,
unsigned DestAlign,
1870 std::optional<uint32_t> AtomicCpySize)
const = 0;
1883 unsigned AddrSpace)
const = 0;
1886 unsigned AddrSpace)
const = 0;
1891 unsigned ChainSizeInBytes,
1894 unsigned ChainSizeInBytes,
1908 Align Alignment)
const = 0;
1913 template <
typename T>
1919 ~
Model()
override =
default;
1921 const DataLayout &getDataLayout()
const override {
1922 return Impl.getDataLayout();
1932 return Impl.getInliningThresholdMultiplier();
1935 return Impl.adjustInliningThreshold(CB);
1938 return Impl.getInlinerVectorBonusPercent();
1941 return Impl.getMemcpyCost(
I);
1949 return Impl.getPredictableBranchThreshold();
1953 return Impl.useGPUDivergenceAnalysis();
1956 return Impl.isSourceOfDivergence(V);
1960 return Impl.isAlwaysUniform(V);
1967 return Impl.collectFlatAddressOperands(OpIndexes, IID);
1971 return Impl.isNoopAddrSpaceCast(FromAS, ToAS);
1976 return Impl.canHaveNonUndefGlobalInitializerInAddressSpace(AS);
1980 return Impl.getAssumedAddrSpace(V);
1985 std::pair<const Value *, unsigned>
1987 return Impl.getPredicatedAddrSpace(V);
1991 Value *NewV)
const override {
1992 return Impl.rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
1996 return Impl.isLoweredToCall(
F);
1999 UnrollingPreferences &UP,
2000 OptimizationRemarkEmitter *ORE)
override {
2001 return Impl.getUnrollingPreferences(L, SE, UP, ORE);
2004 PeelingPreferences &PP)
override {
2005 return Impl.getPeelingPreferences(L, SE, PP);
2008 AssumptionCache &AC, TargetLibraryInfo *LibInfo,
2009 HardwareLoopInfo &HWLoopInfo)
override {
2010 return Impl.isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
2013 AssumptionCache &AC, TargetLibraryInfo *TLI,
2015 LoopVectorizationLegality *LVL,
2016 InterleavedAccessInfo *IAI)
override {
2017 return Impl.preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LVL, IAI);
2020 return Impl.emitGetActiveLaneMask();
2022 std::optional<Instruction *>
2024 return Impl.instCombineIntrinsic(IC, II);
2026 std::optional<Value *>
2028 APInt DemandedMask, KnownBits &Known,
2029 bool &KnownBitsComputed)
override {
2030 return Impl.simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
2034 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
2035 APInt &UndefElts2, APInt &UndefElts3,
2036 std::function<
void(Instruction *,
unsigned, APInt, APInt &)>
2037 SimplifyAndSetOp)
override {
2038 return Impl.simplifyDemandedVectorEltsIntrinsic(
2039 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
2043 return Impl.isLegalAddImmediate(
Imm);
2046 return Impl.isLegalICmpImmediate(
Imm);
2049 bool HasBaseReg, int64_t Scale,
unsigned AddrSpace,
2050 Instruction *
I)
override {
2051 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
2055 const TargetTransformInfo::LSRCost &C2)
override {
2056 return Impl.isLSRCostLess(
C1, C2);
2059 return Impl.isNumRegsMajorCostOfLSR();
2062 return Impl.isProfitableLSRChainElement(
I);
2065 bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI,
2066 DominatorTree *DT, AssumptionCache *AC,
2067 TargetLibraryInfo *LibInfo)
override {
2068 return Impl.canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
2072 ScalarEvolution *SE)
const override {
2073 return Impl.getPreferredAddressingMode(L, SE);
2076 return Impl.isLegalMaskedStore(DataType, Alignment);
2079 return Impl.isLegalMaskedLoad(DataType, Alignment);
2082 return Impl.isLegalNTStore(DataType, Alignment);
2085 return Impl.isLegalNTLoad(DataType, Alignment);
2088 ElementCount NumElements)
const override {
2089 return Impl.isLegalBroadcastLoad(ElementTy, NumElements);
2092 return Impl.isLegalMaskedScatter(DataType, Alignment);
2095 return Impl.isLegalMaskedGather(DataType, Alignment);
2098 Align Alignment)
override {
2099 return Impl.forceScalarizeMaskedGather(DataType, Alignment);
2102 Align Alignment)
override {
2103 return Impl.forceScalarizeMaskedScatter(DataType, Alignment);
2106 return Impl.isLegalMaskedCompressStore(DataType);
2109 return Impl.isLegalMaskedExpandLoad(DataType);
2112 const SmallBitVector &OpcodeMask)
const override {
2113 return Impl.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask);
2116 return Impl.enableOrderedReductions();
2118 bool hasDivRemOp(Type *DataType,
bool IsSigned)
override {
2119 return Impl.hasDivRemOp(DataType, IsSigned);
2122 return Impl.hasVolatileVariant(
I, AddrSpace);
2125 return Impl.prefersVectorizedAddressing();
2128 int64_t BaseOffset,
bool HasBaseReg,
2130 unsigned AddrSpace)
override {
2131 return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
2136 return Impl.isTruncateFree(Ty1, Ty2);
2139 return Impl.isProfitableToHoist(
I);
2141 bool useAA()
override {
return Impl.useAA(); }
2142 bool isTypeLegal(Type *Ty)
override {
return Impl.isTypeLegal(Ty); }
2144 return Impl.getRegUsageForType(Ty);
2147 return Impl.shouldBuildLookupTables();
2150 return Impl.shouldBuildLookupTablesForConstant(
C);
2153 return Impl.shouldBuildRelLookupTables();
2156 return Impl.useColdCCForColdCall(
F);
2160 const APInt &DemandedElts,
2161 bool Insert,
bool Extract,
2163 return Impl.getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
2168 ArrayRef<Type *> Tys,
2170 return Impl.getOperandsScalarizationOverhead(
Args, Tys,
CostKind);
2174 return Impl.supportsEfficientVectorElementLoadStore();
2179 return Impl.supportsTailCallFor(CB);
2183 return Impl.enableAggressiveInterleaving(LoopHasReductions);
2186 bool IsZeroCmp)
const override {
2187 return Impl.enableMemCmpExpansion(OptSize, IsZeroCmp);
2190 return Impl.enableInterleavedAccessVectorization();
2193 return Impl.enableSelectOptimize();
2196 return Impl.enableMaskedInterleavedAccessVectorization();
2199 return Impl.isFPVectorizationPotentiallyUnsafe();
2203 unsigned *Fast)
override {
2208 return Impl.getPopcntSupport(IntTyWidthInBit);
2210 bool haveFastSqrt(Type *Ty)
override {
return Impl.haveFastSqrt(Ty); }
2213 return Impl.isExpensiveToSpeculativelyExecute(
I);
2217 return Impl.isFCmpOrdCheaperThanFCmpZero(Ty);
2221 return Impl.getFPOpCost(Ty);
2225 const APInt &
Imm, Type *Ty)
override {
2226 return Impl.getIntImmCodeSizeCost(Opc, Idx,
Imm, Ty);
2233 const APInt &
Imm, Type *Ty,
2235 Instruction *Inst =
nullptr)
override {
2236 return Impl.getIntImmCostInst(Opc, Idx,
Imm, Ty,
CostKind, Inst);
2239 const APInt &
Imm, Type *Ty,
2241 return Impl.getIntImmCostIntrin(IID, Idx,
Imm, Ty,
CostKind);
2244 return Impl.getNumberOfRegisters(ClassID);
2247 Type *Ty =
nullptr)
const override {
2248 return Impl.getRegisterClassForType(Vector, Ty);
2251 return Impl.getRegisterClassName(ClassID);
2254 return Impl.getRegisterBitWidth(K);
2257 return Impl.getMinVectorRegisterBitWidth();
2259 std::optional<unsigned>
getMaxVScale()
const override {
2260 return Impl.getMaxVScale();
2263 return Impl.getVScaleForTuning();
2267 return Impl.shouldMaximizeVectorBandwidth(K);
2270 bool IsScalable)
const override {
2271 return Impl.getMinimumVF(ElemWidth, IsScalable);
2273 unsigned getMaximumVF(
unsigned ElemWidth,
unsigned Opcode)
const override {
2274 return Impl.getMaximumVF(ElemWidth, Opcode);
2277 Type *ScalarValTy)
const override {
2278 return Impl.getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy);
2281 const Instruction &
I,
bool &AllowPromotionWithoutCommonHeader)
override {
2282 return Impl.shouldConsiderAddressTypePromotion(
2283 I, AllowPromotionWithoutCommonHeader);
2285 unsigned getCacheLineSize()
const override {
return Impl.getCacheLineSize(); }
2287 return Impl.getCacheSize(Level);
2289 std::optional<unsigned>
2291 return Impl.getCacheAssociativity(Level);
2297 return Impl.getPrefetchDistance();
2304 unsigned NumStridedMemAccesses,
2305 unsigned NumPrefetches,
2306 bool HasCall)
const override {
2307 return Impl.getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
2308 NumPrefetches, HasCall);
2315 return Impl.getMaxPrefetchIterationsAhead();
2320 return Impl.enableWritePrefetching();
2325 return Impl.shouldPrefetchAddressSpace(AS);
2329 return Impl.getMaxInterleaveFactor(VF);
2333 ProfileSummaryInfo *PSI,
2334 BlockFrequencyInfo *
BFI)
override {
2335 return Impl.getEstimatedNumberOfCaseClusters(
SI, JTSize, PSI,
BFI);
2339 OperandValueInfo Opd1Info, OperandValueInfo Opd2Info,
2340 ArrayRef<const Value *>
Args,
2341 const Instruction *CxtI =
nullptr)
override {
2342 return Impl.getArithmeticInstrCost(Opcode, Ty,
CostKind, Opd1Info, Opd2Info,
2350 ArrayRef<const Value *>
Args)
override {
2356 const Instruction *
I)
override {
2357 return Impl.getCastInstrCost(Opcode, Dst, Src, CCH,
CostKind,
I);
2361 unsigned Index)
override {
2362 return Impl.getExtractWithExtendCost(Opcode, Dst, VecTy,
Index);
2365 const Instruction *
I =
nullptr)
override {
2366 return Impl.getCFInstrCost(Opcode,
CostKind,
I);
2371 const Instruction *
I)
override {
2372 return Impl.getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred,
CostKind,
I);
2377 Value *Op1)
override {
2378 return Impl.getVectorInstrCost(Opcode, Val,
CostKind,
Index, Op0, Op1);
2382 unsigned Index)
override {
2387 const APInt &DemandedDstElts,
2389 return Impl.getReplicationShuffleCost(EltTy, ReplicationFactor, VF,
2395 OperandValueInfo OpInfo,
2396 const Instruction *
I)
override {
2403 const Instruction *
I)
override {
2404 return Impl.getVPMemoryOpCost(Opcode, Src, Alignment,
AddressSpace,
2410 return Impl.getMaskedMemoryOpCost(Opcode, Src, Alignment,
AddressSpace,
2415 bool VariableMask,
Align Alignment,
2417 const Instruction *
I =
nullptr)
override {
2418 return Impl.getGatherScatterOpCost(Opcode, DataTy,
Ptr, VariableMask,
2422 unsigned Opcode, Type *VecTy,
unsigned Factor, ArrayRef<unsigned> Indices,
2424 bool UseMaskForCond,
bool UseMaskForGaps)
override {
2425 return Impl.getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2427 UseMaskForCond, UseMaskForGaps);
2431 std::optional<FastMathFlags> FMF,
2433 return Impl.getArithmeticReductionCost(Opcode, Ty, FMF,
CostKind);
2438 return Impl.getMinMaxReductionCost(Ty, CondTy, IsUnsigned,
CostKind);
2441 unsigned Opcode,
bool IsUnsigned, Type *ResTy,
VectorType *Ty,
2442 std::optional<FastMathFlags> FMF,
2444 return Impl.getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF,
2448 bool IsUnsigned, Type *ResTy,
VectorType *Ty,
2450 return Impl.getMulAccReductionCost(IsUnsigned, ResTy, Ty,
CostKind);
2454 return Impl.getIntrinsicInstrCost(ICA,
CostKind);
2457 ArrayRef<Type *> Tys,
2459 return Impl.getCallInstrCost(
F, RetTy, Tys,
CostKind);
2462 return Impl.getNumberOfParts(Tp);
2465 const SCEV *
Ptr)
override {
2466 return Impl.getAddressComputationCost(Ty, SE,
Ptr);
2469 return Impl.getCostOfKeepingLiveOverCall(Tys);
2472 MemIntrinsicInfo &
Info)
override {
2473 return Impl.getTgtMemIntrinsic(Inst,
Info);
2476 return Impl.getAtomicMemIntrinsicMaxElementSize();
2479 Type *ExpectedType)
override {
2480 return Impl.getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
2484 unsigned DestAddrSpace,
unsigned SrcAlign,
unsigned DestAlign,
2485 std::optional<uint32_t> AtomicElementSize)
const override {
2486 return Impl.getMemcpyLoopLoweringType(
Context,
Length, SrcAddrSpace,
2487 DestAddrSpace, SrcAlign, DestAlign,
2491 SmallVectorImpl<Type *> &OpsOut, LLVMContext &
Context,
2492 unsigned RemainingBytes,
unsigned SrcAddrSpace,
unsigned DestAddrSpace,
2493 unsigned SrcAlign,
unsigned DestAlign,
2494 std::optional<uint32_t> AtomicCpySize)
const override {
2495 Impl.getMemcpyLoopResidualLoweringType(OpsOut,
Context, RemainingBytes,
2496 SrcAddrSpace, DestAddrSpace,
2497 SrcAlign, DestAlign, AtomicCpySize);
2500 const Function *Callee)
const override {
2501 return Impl.areInlineCompatible(Caller, Callee);
2504 const ArrayRef<Type *> &Types)
const override {
2505 return Impl.areTypesABICompatible(Caller, Callee, Types);
2508 return Impl.isIndexedLoadLegal(
Mode, Ty, getDataLayout());
2511 return Impl.isIndexedStoreLegal(
Mode, Ty, getDataLayout());
2514 return Impl.getLoadStoreVecRegBitWidth(AddrSpace);
2517 return Impl.isLegalToVectorizeLoad(LI);
2520 return Impl.isLegalToVectorizeStore(
SI);
2523 unsigned AddrSpace)
const override {
2524 return Impl.isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
2528 unsigned AddrSpace)
const override {
2529 return Impl.isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
2533 ElementCount VF)
const override {
2534 return Impl.isLegalToVectorizeReduction(RdxDesc, VF);
2537 return Impl.isElementTypeLegalForScalableVector(Ty);
2540 unsigned ChainSizeInBytes,
2542 return Impl.getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
2545 unsigned ChainSizeInBytes,
2547 return Impl.getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
2550 ReductionFlags Flags)
const override {
2551 return Impl.preferInLoopReduction(Opcode, Ty, Flags);
2554 ReductionFlags Flags)
const override {
2555 return Impl.preferPredicatedReductionSelect(Opcode, Ty, Flags);
2558 return Impl.preferEpilogueVectorization();
2562 return Impl.shouldExpandReduction(II);
2566 return Impl.getGISelRematGlobalCost();
2570 return Impl.getMinTripCountTailFoldingThreshold();
2574 return Impl.supportsScalableVectors();
2578 return Impl.enableScalableVectorization();
2582 Align Alignment)
const override {
2583 return Impl.hasActiveVectorLength(Opcode, DataType, Alignment);
2588 return Impl.getVPLegalizationStrategy(PI);
2592 template <
typename T>
2625 : TTICallback(
Arg.TTICallback) {}
2629 TTICallback =
RHS.TTICallback;
2665 std::optional<TargetTransformInfo>
TTI;
2667 virtual void anchor();
A set of analyses that are preserved following a run of a transformation pass.
Analysis pass providing the TargetTransformInfo.
This is an optimization pass for GlobalISel generic memory operations.
Value * PtrVal
This is the pointer that the intrinsic is loading from or storing to.
A parsed version of the target data layout string in and methods for querying it.
Vector Rotate Left Mask Mask Insert
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
ImmutablePass class - This class is used to provide information that does not need to be run.
Represents a single loop in the control flow graph.
instcombine should handle this C2 when C1
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Type * getReturnType() const
The main scalar evolution driver.
LoopVectorizationLegality checks if it is legal to vectorize a loop, and to what vectorization factor...
const IntrinsicInst * getInst() const
TargetIRAnalysis & operator=(const TargetIRAnalysis &RHS)
TargetIRAnalysis(TargetIRAnalysis &&Arg)
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
The instances of the Type class are immutable: once they are created, they are never changed.
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid(), bool TypeBasedOnly=false)
Convenience struct for specifying and reasoning about fast-math flags.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
InstructionCost getScalarizationCost() const
bool skipScalarizationCost() const
LLVM Basic Block Representation.
FastMathFlags getFlags() const
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const SmallVectorImpl< Type * > & getArgTypes() const
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
TargetIRAnalysis(const TargetIRAnalysis &Arg)
(vector float) vec_cmpeq(*A, *B) C
Class to represent integer types.
Drive the analysis of interleaved memory accesses in the loop.
Analysis containing CSE Info
API to communicate dependencies between analyses during invalidation.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Analysis providing profile information.
mir Rename Register Operands
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
Base class of all SIMD vector types.
AtomicOrdering
Atomic ordering for LLVM's memory model.
This class represents an analyzed expression in the program.
An instruction for storing to memory.
This is an important base class in LLVM.
HardwareLoopInfo()=delete
TargetTransformInfo Result
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
This is an important class for using LLVM in a threaded context.
A special type used by analysis passes to provide an address that identifies that particular analysis...
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
print Print MemDeps of function
A CRTP mix-in that provides informational APIs needed for analysis passes.
Class for arbitrary precision integers.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
A cache of @llvm.assume calls within a function.
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
An instruction for reading from memory.
TargetIRAnalysis()
Default construct a target IR analysis.
amdgpu Simplify well known AMD library false FunctionCallee Callee
TargetIRAnalysis & operator=(TargetIRAnalysis &&RHS)
This is the common base class for vector predication intrinsics.
constexpr unsigned BitWidth
AMDGPU Lower Kernel Arguments
Provides information about what library functions are available for the current target.
iterator_range< value_op_iterator > operand_values()
Result run(const Function &F, FunctionAnalysisManager &)
HardwareLoopInfo(Loop *L)
The core instruction combiner logic.
A wrapper class for inspecting calls to intrinsic functions.
Attributes of a target dependent hardware loop.
static InstructionCost getInvalid(CostType Val=0)
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Intrinsic::ID getID() const
bool canAnalyze(LoopInfo &LI)
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
Information about a load/store intrinsic defined by the target.
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
A container for analyses that lazily runs them and caches their results.
unsigned short MatchingId
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
bool isTypeBasedOnly() const
Conditional or Unconditional Branch instruction.
LLVM Value Representation.
const SmallVectorImpl< const Value * > & getArgs() const