LLVM 18.0.0git
TargetTransformInfo.h
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1//===- TargetTransformInfo.h ------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This pass exposes codegen information to IR-level passes. Every
10/// transformation that uses codegen information is broken into three parts:
11/// 1. The IR-level analysis pass.
12/// 2. The IR-level transformation interface which provides the needed
13/// information.
14/// 3. Codegen-level implementation which uses target-specific hooks.
15///
16/// This file defines #2, which is the interface that IR-level transformations
17/// use for querying the codegen.
18///
19//===----------------------------------------------------------------------===//
20
21#ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
22#define LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
23
25#include "llvm/IR/FMF.h"
26#include "llvm/IR/InstrTypes.h"
27#include "llvm/IR/PassManager.h"
28#include "llvm/Pass.h"
32#include <functional>
33#include <optional>
34#include <utility>
35
36namespace llvm {
37
38namespace Intrinsic {
39typedef unsigned ID;
40}
41
42class AllocaInst;
43class AssumptionCache;
44class BlockFrequencyInfo;
45class DominatorTree;
46class BranchInst;
47class CallBase;
48class Function;
49class GlobalValue;
50class InstCombiner;
51class OptimizationRemarkEmitter;
52class InterleavedAccessInfo;
53class IntrinsicInst;
54class LoadInst;
55class Loop;
56class LoopInfo;
57class LoopVectorizationLegality;
58class ProfileSummaryInfo;
59class RecurrenceDescriptor;
60class SCEV;
61class ScalarEvolution;
62class StoreInst;
63class SwitchInst;
64class TargetLibraryInfo;
65class Type;
66class User;
67class Value;
68class VPIntrinsic;
69struct KnownBits;
70
71/// Information about a load/store intrinsic defined by the target.
73 /// This is the pointer that the intrinsic is loading from or storing to.
74 /// If this is non-null, then analysis/optimization passes can assume that
75 /// this intrinsic is functionally equivalent to a load/store from this
76 /// pointer.
77 Value *PtrVal = nullptr;
78
79 // Ordering for atomic operations.
81
82 // Same Id is set by the target for corresponding load/store intrinsics.
83 unsigned short MatchingId = 0;
84
85 bool ReadMem = false;
86 bool WriteMem = false;
87 bool IsVolatile = false;
88
89 bool isUnordered() const {
93 }
94};
95
96/// Attributes of a target dependent hardware loop.
98 HardwareLoopInfo() = delete;
100 Loop *L = nullptr;
103 const SCEV *ExitCount = nullptr;
105 Value *LoopDecrement = nullptr; // Decrement the loop counter by this
106 // value in every iteration.
107 bool IsNestingLegal = false; // Can a hardware loop be a parent to
108 // another hardware loop?
109 bool CounterInReg = false; // Should loop counter be updated in
110 // the loop via a phi?
111 bool PerformEntryTest = false; // Generate the intrinsic which also performs
112 // icmp ne zero on the loop counter value and
113 // produces an i1 to guard the loop entry.
115 DominatorTree &DT, bool ForceNestedLoop = false,
116 bool ForceHardwareLoopPHI = false);
117 bool canAnalyze(LoopInfo &LI);
118};
119
121 const IntrinsicInst *II = nullptr;
122 Type *RetTy = nullptr;
123 Intrinsic::ID IID;
124 SmallVector<Type *, 4> ParamTys;
126 FastMathFlags FMF;
127 // If ScalarizationCost is UINT_MAX, the cost of scalarizing the
128 // arguments and the return value will be computed based on types.
129 InstructionCost ScalarizationCost = InstructionCost::getInvalid();
130
131public:
133 Intrinsic::ID Id, const CallBase &CI,
135 bool TypeBasedOnly = false);
136
138 Intrinsic::ID Id, Type *RTy, ArrayRef<Type *> Tys,
139 FastMathFlags Flags = FastMathFlags(), const IntrinsicInst *I = nullptr,
141
144
148 const IntrinsicInst *I = nullptr,
150
151 Intrinsic::ID getID() const { return IID; }
152 const IntrinsicInst *getInst() const { return II; }
153 Type *getReturnType() const { return RetTy; }
154 FastMathFlags getFlags() const { return FMF; }
155 InstructionCost getScalarizationCost() const { return ScalarizationCost; }
157 const SmallVectorImpl<Type *> &getArgTypes() const { return ParamTys; }
158
159 bool isTypeBasedOnly() const {
160 return Arguments.empty();
161 }
162
163 bool skipScalarizationCost() const { return ScalarizationCost.isValid(); }
164};
165
167 /// Don't use tail folding
168 None,
169 /// Use predicate only to mask operations on data in the loop.
170 /// When the VL is not known to be a power-of-2, this method requires a
171 /// runtime overflow check for the i + VL in the loop because it compares the
172 /// scalar induction variable against the tripcount rounded up by VL which may
173 /// overflow. When the VL is a power-of-2, both the increment and uprounded
174 /// tripcount will overflow to 0, which does not require a runtime check
175 /// since the loop is exited when the loop induction variable equals the
176 /// uprounded trip-count, which are both 0.
177 Data,
178 /// Same as Data, but avoids using the get.active.lane.mask intrinsic to
179 /// calculate the mask and instead implements this with a
180 /// splat/stepvector/cmp.
181 /// FIXME: Can this kind be removed now that SelectionDAGBuilder expands the
182 /// active.lane.mask intrinsic when it is not natively supported?
184 /// Use predicate to control both data and control flow.
185 /// This method always requires a runtime overflow check for the i + VL
186 /// increment inside the loop, because it uses the result direclty in the
187 /// active.lane.mask to calculate the mask for the next iteration. If the
188 /// increment overflows, the mask is no longer correct.
190 /// Use predicate to control both data and control flow, but modify
191 /// the trip count so that a runtime overflow check can be avoided
192 /// and such that the scalar epilogue loop can always be removed.
194};
195
202 : TLI(TLI), LVL(LVL), IAI(IAI) {}
203};
204
205class TargetTransformInfo;
207
208/// This pass provides access to the codegen interfaces that are needed
209/// for IR-level transformations.
211public:
212 /// Construct a TTI object using a type implementing the \c Concept
213 /// API below.
214 ///
215 /// This is used by targets to construct a TTI wrapping their target-specific
216 /// implementation that encodes appropriate costs for their target.
217 template <typename T> TargetTransformInfo(T Impl);
218
219 /// Construct a baseline TTI object using a minimal implementation of
220 /// the \c Concept API below.
221 ///
222 /// The TTI implementation will reflect the information in the DataLayout
223 /// provided if non-null.
224 explicit TargetTransformInfo(const DataLayout &DL);
225
226 // Provide move semantics.
229
230 // We need to define the destructor out-of-line to define our sub-classes
231 // out-of-line.
233
234 /// Handle the invalidation of this information.
235 ///
236 /// When used as a result of \c TargetIRAnalysis this method will be called
237 /// when the function this was computed for changes. When it returns false,
238 /// the information is preserved across those changes.
241 // FIXME: We should probably in some way ensure that the subtarget
242 // information for a function hasn't changed.
243 return false;
244 }
245
246 /// \name Generic Target Information
247 /// @{
248
249 /// The kind of cost model.
250 ///
251 /// There are several different cost models that can be customized by the
252 /// target. The normalization of each cost model may be target specific.
253 /// e.g. TCK_SizeAndLatency should be comparable to target thresholds such as
254 /// those derived from MCSchedModel::LoopMicroOpBufferSize etc.
256 TCK_RecipThroughput, ///< Reciprocal throughput.
257 TCK_Latency, ///< The latency of instruction.
258 TCK_CodeSize, ///< Instruction code size.
259 TCK_SizeAndLatency ///< The weighted sum of size and latency.
260 };
261
262 /// Underlying constants for 'cost' values in this interface.
263 ///
264 /// Many APIs in this interface return a cost. This enum defines the
265 /// fundamental values that should be used to interpret (and produce) those
266 /// costs. The costs are returned as an int rather than a member of this
267 /// enumeration because it is expected that the cost of one IR instruction
268 /// may have a multiplicative factor to it or otherwise won't fit directly
269 /// into the enum. Moreover, it is common to sum or average costs which works
270 /// better as simple integral values. Thus this enum only provides constants.
271 /// Also note that the returned costs are signed integers to make it natural
272 /// to add, subtract, and test with zero (a common boundary condition). It is
273 /// not expected that 2^32 is a realistic cost to be modeling at any point.
274 ///
275 /// Note that these costs should usually reflect the intersection of code-size
276 /// cost and execution cost. A free instruction is typically one that folds
277 /// into another instruction. For example, reg-to-reg moves can often be
278 /// skipped by renaming the registers in the CPU, but they still are encoded
279 /// and thus wouldn't be considered 'free' here.
281 TCC_Free = 0, ///< Expected to fold away in lowering.
282 TCC_Basic = 1, ///< The cost of a typical 'add' instruction.
283 TCC_Expensive = 4 ///< The cost of a 'div' instruction on x86.
284 };
285
286 /// Estimate the cost of a GEP operation when lowered.
287 ///
288 /// \p PointeeType is the source element type of the GEP.
289 /// \p Ptr is the base pointer operand.
290 /// \p Operands is the list of indices following the base pointer.
291 ///
292 /// \p AccessType is a hint as to what type of memory might be accessed by
293 /// users of the GEP. getGEPCost will use it to determine if the GEP can be
294 /// folded into the addressing mode of a load/store. If AccessType is null,
295 /// then the resulting target type based off of PointeeType will be used as an
296 /// approximation.
298 getGEPCost(Type *PointeeType, const Value *Ptr,
299 ArrayRef<const Value *> Operands, Type *AccessType = nullptr,
301
302 /// Describe known properties for a set of pointers.
304 /// All the GEPs in a set have same base address.
305 unsigned IsSameBaseAddress : 1;
306 /// These properties only valid if SameBaseAddress is set.
307 /// True if all pointers are separated by a unit stride.
308 unsigned IsUnitStride : 1;
309 /// True if distance between any two neigbouring pointers is a known value.
310 unsigned IsKnownStride : 1;
311 unsigned Reserved : 29;
312
313 bool isSameBase() const { return IsSameBaseAddress; }
314 bool isUnitStride() const { return IsSameBaseAddress && IsUnitStride; }
316
318 return {/*IsSameBaseAddress=*/1, /*IsUnitStride=*/1,
319 /*IsKnownStride=*/1, 0};
320 }
322 return {/*IsSameBaseAddress=*/1, /*IsUnitStride=*/0,
323 /*IsKnownStride=*/1, 0};
324 }
326 return {/*IsSameBaseAddress=*/1, /*IsUnitStride=*/0,
327 /*IsKnownStride=*/0, 0};
328 }
329 };
330 static_assert(sizeof(PointersChainInfo) == 4, "Was size increase justified?");
331
332 /// Estimate the cost of a chain of pointers (typically pointer operands of a
333 /// chain of loads or stores within same block) operations set when lowered.
334 /// \p AccessTy is the type of the loads/stores that will ultimately use the
335 /// \p Ptrs.
338 const PointersChainInfo &Info, Type *AccessTy,
340
341 ) const;
342
343 /// \returns A value by which our inlining threshold should be multiplied.
344 /// This is primarily used to bump up the inlining threshold wholesale on
345 /// targets where calls are unusually expensive.
346 ///
347 /// TODO: This is a rather blunt instrument. Perhaps altering the costs of
348 /// individual classes of instructions would be better.
349 unsigned getInliningThresholdMultiplier() const;
350
353
354 /// \returns A value to be added to the inlining threshold.
355 unsigned adjustInliningThreshold(const CallBase *CB) const;
356
357 /// \returns The cost of having an Alloca in the caller if not inlined, to be
358 /// added to the threshold
359 unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const;
360
361 /// \returns Vector bonus in percent.
362 ///
363 /// Vector bonuses: We want to more aggressively inline vector-dense kernels
364 /// and apply this bonus based on the percentage of vector instructions. A
365 /// bonus is applied if the vector instructions exceed 50% and half that
366 /// amount is applied if it exceeds 10%. Note that these bonuses are some what
367 /// arbitrary and evolved over time by accident as much as because they are
368 /// principled bonuses.
369 /// FIXME: It would be nice to base the bonus values on something more
370 /// scientific. A target may has no bonus on vector instructions.
372
373 /// \return the expected cost of a memcpy, which could e.g. depend on the
374 /// source/destination type and alignment and the number of bytes copied.
376
377 /// Returns the maximum memset / memcpy size in bytes that still makes it
378 /// profitable to inline the call.
380
381 /// \return The estimated number of case clusters when lowering \p 'SI'.
382 /// \p JTSize Set a jump table size only when \p SI is suitable for a jump
383 /// table.
385 unsigned &JTSize,
387 BlockFrequencyInfo *BFI) const;
388
389 /// Estimate the cost of a given IR user when lowered.
390 ///
391 /// This can estimate the cost of either a ConstantExpr or Instruction when
392 /// lowered.
393 ///
394 /// \p Operands is a list of operands which can be a result of transformations
395 /// of the current operands. The number of the operands on the list must equal
396 /// to the number of the current operands the IR user has. Their order on the
397 /// list must be the same as the order of the current operands the IR user
398 /// has.
399 ///
400 /// The returned cost is defined in terms of \c TargetCostConstants, see its
401 /// comments for a detailed explanation of the cost values.
405
406 /// This is a helper function which calls the three-argument
407 /// getInstructionCost with \p Operands which are the current operands U has.
409 TargetCostKind CostKind) const {
410 SmallVector<const Value *, 4> Operands(U->operand_values());
412 }
413
414 /// If a branch or a select condition is skewed in one direction by more than
415 /// this factor, it is very likely to be predicted correctly.
417
418 /// Return true if branch divergence exists.
419 ///
420 /// Branch divergence has a significantly negative impact on GPU performance
421 /// when threads in the same wavefront take different paths due to conditional
422 /// branches.
423 ///
424 /// If \p F is passed, provides a context function. If \p F is known to only
425 /// execute in a single threaded environment, the target may choose to skip
426 /// uniformity analysis and assume all values are uniform.
427 bool hasBranchDivergence(const Function *F = nullptr) const;
428
429 /// Returns whether V is a source of divergence.
430 ///
431 /// This function provides the target-dependent information for
432 /// the target-independent UniformityAnalysis.
433 bool isSourceOfDivergence(const Value *V) const;
434
435 // Returns true for the target specific
436 // set of operations which produce uniform result
437 // even taking non-uniform arguments
438 bool isAlwaysUniform(const Value *V) const;
439
440 /// Query the target whether the specified address space cast from FromAS to
441 /// ToAS is valid.
442 bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const;
443
444 /// Return false if a \p AS0 address cannot possibly alias a \p AS1 address.
445 bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const;
446
447 /// Returns the address space ID for a target's 'flat' address space. Note
448 /// this is not necessarily the same as addrspace(0), which LLVM sometimes
449 /// refers to as the generic address space. The flat address space is a
450 /// generic address space that can be used access multiple segments of memory
451 /// with different address spaces. Access of a memory location through a
452 /// pointer with this address space is expected to be legal but slower
453 /// compared to the same memory location accessed through a pointer with a
454 /// different address space.
455 //
456 /// This is for targets with different pointer representations which can
457 /// be converted with the addrspacecast instruction. If a pointer is converted
458 /// to this address space, optimizations should attempt to replace the access
459 /// with the source address space.
460 ///
461 /// \returns ~0u if the target does not have such a flat address space to
462 /// optimize away.
463 unsigned getFlatAddressSpace() const;
464
465 /// Return any intrinsic address operand indexes which may be rewritten if
466 /// they use a flat address space pointer.
467 ///
468 /// \returns true if the intrinsic was handled.
470 Intrinsic::ID IID) const;
471
472 bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const;
473
474 /// Return true if globals in this address space can have initializers other
475 /// than `undef`.
477
478 unsigned getAssumedAddrSpace(const Value *V) const;
479
480 bool isSingleThreaded() const;
481
482 std::pair<const Value *, unsigned>
483 getPredicatedAddrSpace(const Value *V) const;
484
485 /// Rewrite intrinsic call \p II such that \p OldV will be replaced with \p
486 /// NewV, which has a different address space. This should happen for every
487 /// operand index that collectFlatAddressOperands returned for the intrinsic.
488 /// \returns nullptr if the intrinsic was not handled. Otherwise, returns the
489 /// new value (which may be the original \p II with modified operands).
491 Value *NewV) const;
492
493 /// Test whether calls to a function lower to actual program function
494 /// calls.
495 ///
496 /// The idea is to test whether the program is likely to require a 'call'
497 /// instruction or equivalent in order to call the given function.
498 ///
499 /// FIXME: It's not clear that this is a good or useful query API. Client's
500 /// should probably move to simpler cost metrics using the above.
501 /// Alternatively, we could split the cost interface into distinct code-size
502 /// and execution-speed costs. This would allow modelling the core of this
503 /// query more accurately as a call is a single small instruction, but
504 /// incurs significant execution cost.
505 bool isLoweredToCall(const Function *F) const;
506
507 struct LSRCost {
508 /// TODO: Some of these could be merged. Also, a lexical ordering
509 /// isn't always optimal.
510 unsigned Insns;
511 unsigned NumRegs;
512 unsigned AddRecCost;
513 unsigned NumIVMuls;
514 unsigned NumBaseAdds;
515 unsigned ImmCost;
516 unsigned SetupCost;
517 unsigned ScaleCost;
518 };
519
520 /// Parameters that control the generic loop unrolling transformation.
522 /// The cost threshold for the unrolled loop. Should be relative to the
523 /// getInstructionCost values returned by this API, and the expectation is
524 /// that the unrolled loop's instructions when run through that interface
525 /// should not exceed this cost. However, this is only an estimate. Also,
526 /// specific loops may be unrolled even with a cost above this threshold if
527 /// deemed profitable. Set this to UINT_MAX to disable the loop body cost
528 /// restriction.
529 unsigned Threshold;
530 /// If complete unrolling will reduce the cost of the loop, we will boost
531 /// the Threshold by a certain percent to allow more aggressive complete
532 /// unrolling. This value provides the maximum boost percentage that we
533 /// can apply to Threshold (The value should be no less than 100).
534 /// BoostedThreshold = Threshold * min(RolledCost / UnrolledCost,
535 /// MaxPercentThresholdBoost / 100)
536 /// E.g. if complete unrolling reduces the loop execution time by 50%
537 /// then we boost the threshold by the factor of 2x. If unrolling is not
538 /// expected to reduce the running time, then we do not increase the
539 /// threshold.
541 /// The cost threshold for the unrolled loop when optimizing for size (set
542 /// to UINT_MAX to disable).
544 /// The cost threshold for the unrolled loop, like Threshold, but used
545 /// for partial/runtime unrolling (set to UINT_MAX to disable).
547 /// The cost threshold for the unrolled loop when optimizing for size, like
548 /// OptSizeThreshold, but used for partial/runtime unrolling (set to
549 /// UINT_MAX to disable).
551 /// A forced unrolling factor (the number of concatenated bodies of the
552 /// original loop in the unrolled loop body). When set to 0, the unrolling
553 /// transformation will select an unrolling factor based on the current cost
554 /// threshold and other factors.
555 unsigned Count;
556 /// Default unroll count for loops with run-time trip count.
558 // Set the maximum unrolling factor. The unrolling factor may be selected
559 // using the appropriate cost threshold, but may not exceed this number
560 // (set to UINT_MAX to disable). This does not apply in cases where the
561 // loop is being fully unrolled.
562 unsigned MaxCount;
563 /// Set the maximum unrolling factor for full unrolling. Like MaxCount, but
564 /// applies even if full unrolling is selected. This allows a target to fall
565 /// back to Partial unrolling if full unrolling is above FullUnrollMaxCount.
567 // Represents number of instructions optimized when "back edge"
568 // becomes "fall through" in unrolled loop.
569 // For now we count a conditional branch on a backedge and a comparison
570 // feeding it.
571 unsigned BEInsns;
572 /// Allow partial unrolling (unrolling of loops to expand the size of the
573 /// loop body, not only to eliminate small constant-trip-count loops).
575 /// Allow runtime unrolling (unrolling of loops to expand the size of the
576 /// loop body even when the number of loop iterations is not known at
577 /// compile time).
579 /// Allow generation of a loop remainder (extra iterations after unroll).
581 /// Allow emitting expensive instructions (such as divisions) when computing
582 /// the trip count of a loop for runtime unrolling.
584 /// Apply loop unroll on any kind of loop
585 /// (mainly to loops that fail runtime unrolling).
586 bool Force;
587 /// Allow using trip count upper bound to unroll loops.
589 /// Allow unrolling of all the iterations of the runtime loop remainder.
591 /// Allow unroll and jam. Used to enable unroll and jam for the target.
593 /// Threshold for unroll and jam, for inner loop size. The 'Threshold'
594 /// value above is used during unroll and jam for the outer loop size.
595 /// This value is used in the same manner to limit the size of the inner
596 /// loop.
598 /// Don't allow loop unrolling to simulate more than this number of
599 /// iterations when checking full unroll profitability
601 /// Don't disable runtime unroll for the loops which were vectorized.
603 };
604
605 /// Get target-customized preferences for the generic loop unrolling
606 /// transformation. The caller will initialize UP with the current
607 /// target-independent defaults.
610 OptimizationRemarkEmitter *ORE) const;
611
612 /// Query the target whether it would be profitable to convert the given loop
613 /// into a hardware loop.
616 HardwareLoopInfo &HWLoopInfo) const;
617
618 /// Query the target whether it would be prefered to create a predicated
619 /// vector loop, which can avoid the need to emit a scalar epilogue loop.
621
622 /// Query the target what the preferred style of tail folding is.
623 /// \param IVUpdateMayOverflow Tells whether it is known if the IV update
624 /// may (or will never) overflow for the suggested VF/UF in the given loop.
625 /// Targets can use this information to select a more optimal tail folding
626 /// style. The value conservatively defaults to true, such that no assumptions
627 /// are made on overflow.
629 getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const;
630
631 // Parameters that control the loop peeling transformation
633 /// A forced peeling factor (the number of bodied of the original loop
634 /// that should be peeled off before the loop body). When set to 0, the
635 /// a peeling factor based on profile information and other factors.
636 unsigned PeelCount;
637 /// Allow peeling off loop iterations.
639 /// Allow peeling off loop iterations for loop nests.
641 /// Allow peeling basing on profile. Uses to enable peeling off all
642 /// iterations basing on provided profile.
643 /// If the value is true the peeling cost model can decide to peel only
644 /// some iterations and in this case it will set this to false.
646 };
647
648 /// Get target-customized preferences for the generic loop peeling
649 /// transformation. The caller will initialize \p PP with the current
650 /// target-independent defaults with information from \p L and \p SE.
652 PeelingPreferences &PP) const;
653
654 /// Targets can implement their own combinations for target-specific
655 /// intrinsics. This function will be called from the InstCombine pass every
656 /// time a target-specific intrinsic is encountered.
657 ///
658 /// \returns std::nullopt to not do anything target specific or a value that
659 /// will be returned from the InstCombiner. It is possible to return null and
660 /// stop further processing of the intrinsic by returning nullptr.
661 std::optional<Instruction *> instCombineIntrinsic(InstCombiner & IC,
662 IntrinsicInst & II) const;
663 /// Can be used to implement target-specific instruction combining.
664 /// \see instCombineIntrinsic
665 std::optional<Value *> simplifyDemandedUseBitsIntrinsic(
666 InstCombiner & IC, IntrinsicInst & II, APInt DemandedMask,
667 KnownBits & Known, bool &KnownBitsComputed) const;
668 /// Can be used to implement target-specific instruction combining.
669 /// \see instCombineIntrinsic
670 std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
671 InstCombiner & IC, IntrinsicInst & II, APInt DemandedElts,
672 APInt & UndefElts, APInt & UndefElts2, APInt & UndefElts3,
673 std::function<void(Instruction *, unsigned, APInt, APInt &)>
674 SimplifyAndSetOp) const;
675 /// @}
676
677 /// \name Scalar Target Information
678 /// @{
679
680 /// Flags indicating the kind of support for population count.
681 ///
682 /// Compared to the SW implementation, HW support is supposed to
683 /// significantly boost the performance when the population is dense, and it
684 /// may or may not degrade performance if the population is sparse. A HW
685 /// support is considered as "Fast" if it can outperform, or is on a par
686 /// with, SW implementation when the population is sparse; otherwise, it is
687 /// considered as "Slow".
689
690 /// Return true if the specified immediate is legal add immediate, that
691 /// is the target has add instructions which can add a register with the
692 /// immediate without having to materialize the immediate into a register.
693 bool isLegalAddImmediate(int64_t Imm) const;
694
695 /// Return true if the specified immediate is legal icmp immediate,
696 /// that is the target has icmp instructions which can compare a register
697 /// against the immediate without having to materialize the immediate into a
698 /// register.
699 bool isLegalICmpImmediate(int64_t Imm) const;
700
701 /// Return true if the addressing mode represented by AM is legal for
702 /// this target, for a load/store of the specified type.
703 /// The type may be VoidTy, in which case only return true if the addressing
704 /// mode is legal for a load/store of any legal type.
705 /// If target returns true in LSRWithInstrQueries(), I may be valid.
706 /// TODO: Handle pre/postinc as well.
707 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
708 bool HasBaseReg, int64_t Scale,
709 unsigned AddrSpace = 0,
710 Instruction *I = nullptr) const;
711
712 /// Return true if LSR cost of C1 is lower than C2.
714 const TargetTransformInfo::LSRCost &C2) const;
715
716 /// Return true if LSR major cost is number of registers. Targets which
717 /// implement their own isLSRCostLess and unset number of registers as major
718 /// cost should return false, otherwise return true.
719 bool isNumRegsMajorCostOfLSR() const;
720
721 /// Return true if LSR should attempts to replace a use of an otherwise dead
722 /// primary IV in the latch condition with another IV available in the loop.
723 /// When successful, makes the primary IV dead.
725
726 /// \returns true if LSR should not optimize a chain that includes \p I.
728
729 /// Return true if the target can fuse a compare and branch.
730 /// Loop-strength-reduction (LSR) uses that knowledge to adjust its cost
731 /// calculation for the instructions in a loop.
732 bool canMacroFuseCmp() const;
733
734 /// Return true if the target can save a compare for loop count, for example
735 /// hardware loop saves a compare.
736 bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI,
738 TargetLibraryInfo *LibInfo) const;
739
744 };
745
746 /// Return the preferred addressing mode LSR should make efforts to generate.
748 ScalarEvolution *SE) const;
749
750 /// Return true if the target supports masked store.
751 bool isLegalMaskedStore(Type *DataType, Align Alignment) const;
752 /// Return true if the target supports masked load.
753 bool isLegalMaskedLoad(Type *DataType, Align Alignment) const;
754
755 /// Return true if the target supports nontemporal store.
756 bool isLegalNTStore(Type *DataType, Align Alignment) const;
757 /// Return true if the target supports nontemporal load.
758 bool isLegalNTLoad(Type *DataType, Align Alignment) const;
759
760 /// \Returns true if the target supports broadcasting a load to a vector of
761 /// type <NumElements x ElementTy>.
762 bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const;
763
764 /// Return true if the target supports masked scatter.
765 bool isLegalMaskedScatter(Type *DataType, Align Alignment) const;
766 /// Return true if the target supports masked gather.
767 bool isLegalMaskedGather(Type *DataType, Align Alignment) const;
768 /// Return true if the target forces scalarizing of llvm.masked.gather
769 /// intrinsics.
770 bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const;
771 /// Return true if the target forces scalarizing of llvm.masked.scatter
772 /// intrinsics.
773 bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const;
774
775 /// Return true if the target supports masked compress store.
776 bool isLegalMaskedCompressStore(Type *DataType) const;
777 /// Return true if the target supports masked expand load.
778 bool isLegalMaskedExpandLoad(Type *DataType) const;
779
780 /// Return true if this is an alternating opcode pattern that can be lowered
781 /// to a single instruction on the target. In X86 this is for the addsub
782 /// instruction which corrsponds to a Shuffle + Fadd + FSub pattern in IR.
783 /// This function expectes two opcodes: \p Opcode1 and \p Opcode2 being
784 /// selected by \p OpcodeMask. The mask contains one bit per lane and is a `0`
785 /// when \p Opcode0 is selected and `1` when Opcode1 is selected.
786 /// \p VecTy is the vector type of the instruction to be generated.
787 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
788 const SmallBitVector &OpcodeMask) const;
789
790 /// Return true if we should be enabling ordered reductions for the target.
791 bool enableOrderedReductions() const;
792
793 /// Return true if the target has a unified operation to calculate division
794 /// and remainder. If so, the additional implicit multiplication and
795 /// subtraction required to calculate a remainder from division are free. This
796 /// can enable more aggressive transformations for division and remainder than
797 /// would typically be allowed using throughput or size cost models.
798 bool hasDivRemOp(Type *DataType, bool IsSigned) const;
799
800 /// Return true if the given instruction (assumed to be a memory access
801 /// instruction) has a volatile variant. If that's the case then we can avoid
802 /// addrspacecast to generic AS for volatile loads/stores. Default
803 /// implementation returns false, which prevents address space inference for
804 /// volatile loads/stores.
805 bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const;
806
807 /// Return true if target doesn't mind addresses in vectors.
808 bool prefersVectorizedAddressing() const;
809
810 /// Return the cost of the scaling factor used in the addressing
811 /// mode represented by AM for this target, for a load/store
812 /// of the specified type.
813 /// If the AM is supported, the return value must be >= 0.
814 /// If the AM is not supported, it returns a negative value.
815 /// TODO: Handle pre/postinc as well.
817 int64_t BaseOffset, bool HasBaseReg,
818 int64_t Scale,
819 unsigned AddrSpace = 0) const;
820
821 /// Return true if the loop strength reduce pass should make
822 /// Instruction* based TTI queries to isLegalAddressingMode(). This is
823 /// needed on SystemZ, where e.g. a memcpy can only have a 12 bit unsigned
824 /// immediate offset and no index register.
825 bool LSRWithInstrQueries() const;
826
827 /// Return true if it's free to truncate a value of type Ty1 to type
828 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
829 /// by referencing its sub-register AX.
830 bool isTruncateFree(Type *Ty1, Type *Ty2) const;
831
832 /// Return true if it is profitable to hoist instruction in the
833 /// then/else to before if.
834 bool isProfitableToHoist(Instruction *I) const;
835
836 bool useAA() const;
837
838 /// Return true if this type is legal.
839 bool isTypeLegal(Type *Ty) const;
840
841 /// Returns the estimated number of registers required to represent \p Ty.
842 unsigned getRegUsageForType(Type *Ty) const;
843
844 /// Return true if switches should be turned into lookup tables for the
845 /// target.
846 bool shouldBuildLookupTables() const;
847
848 /// Return true if switches should be turned into lookup tables
849 /// containing this constant value for the target.
851
852 /// Return true if lookup tables should be turned into relative lookup tables.
853 bool shouldBuildRelLookupTables() const;
854
855 /// Return true if the input function which is cold at all call sites,
856 /// should use coldcc calling convention.
857 bool useColdCCForColdCall(Function &F) const;
858
859 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
860 /// are set if the demanded result elements need to be inserted and/or
861 /// extracted from vectors.
863 const APInt &DemandedElts,
864 bool Insert, bool Extract,
866
867 /// Estimate the overhead of scalarizing an instructions unique
868 /// non-constant operands. The (potentially vector) types to use for each of
869 /// argument are passes via Tys.
874
875 /// If target has efficient vector element load/store instructions, it can
876 /// return true here so that insertion/extraction costs are not added to
877 /// the scalarization cost of a load/store.
879
880 /// If the target supports tail calls.
881 bool supportsTailCalls() const;
882
883 /// If target supports tail call on \p CB
884 bool supportsTailCallFor(const CallBase *CB) const;
885
886 /// Don't restrict interleaved unrolling to small loops.
887 bool enableAggressiveInterleaving(bool LoopHasReductions) const;
888
889 /// Returns options for expansion of memcmp. IsZeroCmp is
890 // true if this is the expansion of memcmp(p1, p2, s) == 0.
892 // Return true if memcmp expansion is enabled.
893 operator bool() const { return MaxNumLoads > 0; }
894
895 // Maximum number of load operations.
896 unsigned MaxNumLoads = 0;
897
898 // The list of available load sizes (in bytes), sorted in decreasing order.
900
901 // For memcmp expansion when the memcmp result is only compared equal or
902 // not-equal to 0, allow up to this number of load pairs per block. As an
903 // example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
904 // a0 = load2bytes &a[0]
905 // b0 = load2bytes &b[0]
906 // a2 = load1byte &a[2]
907 // b2 = load1byte &b[2]
908 // r = cmp eq (a0 ^ b0 | a2 ^ b2), 0
909 unsigned NumLoadsPerBlock = 1;
910
911 // Set to true to allow overlapping loads. For example, 7-byte compares can
912 // be done with two 4-byte compares instead of 4+2+1-byte compares. This
913 // requires all loads in LoadSizes to be doable in an unaligned way.
915
916 // Sometimes, the amount of data that needs to be compared is smaller than
917 // the standard register size, but it cannot be loaded with just one load
918 // instruction. For example, if the size of the memory comparison is 6
919 // bytes, we can handle it more efficiently by loading all 6 bytes in a
920 // single block and generating an 8-byte number, instead of generating two
921 // separate blocks with conditional jumps for 4 and 2 byte loads. This
922 // approach simplifies the process and produces the comparison result as
923 // normal. This array lists the allowed sizes of memcmp tails that can be
924 // merged into one block
926 };
928 bool IsZeroCmp) const;
929
930 /// Should the Select Optimization pass be enabled and ran.
931 bool enableSelectOptimize() const;
932
933 /// Enable matching of interleaved access groups.
935
936 /// Enable matching of interleaved access groups that contain predicated
937 /// accesses or gaps and therefore vectorized using masked
938 /// vector loads/stores.
940
941 /// Indicate that it is potentially unsafe to automatically vectorize
942 /// floating-point operations because the semantics of vector and scalar
943 /// floating-point semantics may differ. For example, ARM NEON v7 SIMD math
944 /// does not support IEEE-754 denormal numbers, while depending on the
945 /// platform, scalar floating-point math does.
946 /// This applies to floating-point math operations and calls, not memory
947 /// operations, shuffles, or casts.
949
950 /// Determine if the target supports unaligned memory accesses.
952 unsigned AddressSpace = 0,
953 Align Alignment = Align(1),
954 unsigned *Fast = nullptr) const;
955
956 /// Return hardware support for population count.
957 PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;
958
959 /// Return true if the hardware has a fast square-root instruction.
960 bool haveFastSqrt(Type *Ty) const;
961
962 /// Return true if the cost of the instruction is too high to speculatively
963 /// execute and should be kept behind a branch.
964 /// This normally just wraps around a getInstructionCost() call, but some
965 /// targets might report a low TCK_SizeAndLatency value that is incompatible
966 /// with the fixed TCC_Expensive value.
967 /// NOTE: This assumes the instruction passes isSafeToSpeculativelyExecute().
969
970 /// Return true if it is faster to check if a floating-point value is NaN
971 /// (or not-NaN) versus a comparison against a constant FP zero value.
972 /// Targets should override this if materializing a 0.0 for comparison is
973 /// generally as cheap as checking for ordered/unordered.
974 bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const;
975
976 /// Return the expected cost of supporting the floating point operation
977 /// of the specified type.
979
980 /// Return the expected cost of materializing for the given integer
981 /// immediate of the specified type.
982 InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
984
985 /// Return the expected cost of materialization for the given integer
986 /// immediate of the specified type for a given instruction. The cost can be
987 /// zero if the immediate can be folded into the specified instruction.
988 InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx,
989 const APInt &Imm, Type *Ty,
991 Instruction *Inst = nullptr) const;
993 const APInt &Imm, Type *Ty,
995
996 /// Return the expected cost for the given integer when optimising
997 /// for size. This is different than the other integer immediate cost
998 /// functions in that it is subtarget agnostic. This is useful when you e.g.
999 /// target one ISA such as Aarch32 but smaller encodings could be possible
1000 /// with another such as Thumb. This return value is used as a penalty when
1001 /// the total costs for a constant is calculated (the bigger the cost, the
1002 /// more beneficial constant hoisting is).
1003 InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx,
1004 const APInt &Imm, Type *Ty) const;
1005 /// @}
1006
1007 /// \name Vector Target Information
1008 /// @{
1009
1010 /// The various kinds of shuffle patterns for vector queries.
1012 SK_Broadcast, ///< Broadcast element 0 to all other elements.
1013 SK_Reverse, ///< Reverse the order of the vector.
1014 SK_Select, ///< Selects elements from the corresponding lane of
1015 ///< either source operand. This is equivalent to a
1016 ///< vector select with a constant condition operand.
1017 SK_Transpose, ///< Transpose two vectors.
1018 SK_InsertSubvector, ///< InsertSubvector. Index indicates start offset.
1019 SK_ExtractSubvector, ///< ExtractSubvector Index indicates start offset.
1020 SK_PermuteTwoSrc, ///< Merge elements from two source vectors into one
1021 ///< with any shuffle mask.
1022 SK_PermuteSingleSrc, ///< Shuffle elements of single source vector with any
1023 ///< shuffle mask.
1024 SK_Splice ///< Concatenates elements from the first input vector
1025 ///< with elements of the second input vector. Returning
1026 ///< a vector of the same type as the input vectors.
1027 ///< Index indicates start offset in first input vector.
1029
1030 /// Additional information about an operand's possible values.
1032 OK_AnyValue, // Operand can have any value.
1033 OK_UniformValue, // Operand is uniform (splat of a value).
1034 OK_UniformConstantValue, // Operand is uniform constant.
1035 OK_NonUniformConstantValue // Operand is a non uniform constant value.
1037
1038 /// Additional properties of an operand's values.
1043 };
1044
1045 // Describe the values an operand can take. We're in the process
1046 // of migrating uses of OperandValueKind and OperandValueProperties
1047 // to use this class, and then will change the internal representation.
1051
1052 bool isConstant() const {
1054 }
1055 bool isUniform() const {
1057 }
1058 bool isPowerOf2() const {
1059 return Properties == OP_PowerOf2;
1060 }
1061 bool isNegatedPowerOf2() const {
1063 }
1064
1066 return {Kind, OP_None};
1067 }
1068 };
1069
1070 /// \return the number of registers in the target-provided register class.
1071 unsigned getNumberOfRegisters(unsigned ClassID) const;
1072
1073 /// \return the target-provided register class ID for the provided type,
1074 /// accounting for type promotion and other type-legalization techniques that
1075 /// the target might apply. However, it specifically does not account for the
1076 /// scalarization or splitting of vector types. Should a vector type require
1077 /// scalarization or splitting into multiple underlying vector registers, that
1078 /// type should be mapped to a register class containing no registers.
1079 /// Specifically, this is designed to provide a simple, high-level view of the
1080 /// register allocation later performed by the backend. These register classes
1081 /// don't necessarily map onto the register classes used by the backend.
1082 /// FIXME: It's not currently possible to determine how many registers
1083 /// are used by the provided type.
1084 unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const;
1085
1086 /// \return the target-provided register class name
1087 const char *getRegisterClassName(unsigned ClassID) const;
1088
1090
1091 /// \return The width of the largest scalar or vector register type.
1093
1094 /// \return The width of the smallest vector register type.
1095 unsigned getMinVectorRegisterBitWidth() const;
1096
1097 /// \return The maximum value of vscale if the target specifies an
1098 /// architectural maximum vector length, and std::nullopt otherwise.
1099 std::optional<unsigned> getMaxVScale() const;
1100
1101 /// \return the value of vscale to tune the cost model for.
1102 std::optional<unsigned> getVScaleForTuning() const;
1103
1104 /// \return true if vscale is known to be a power of 2
1105 bool isVScaleKnownToBeAPowerOfTwo() const;
1106
1107 /// \return True if the vectorization factor should be chosen to
1108 /// make the vector of the smallest element type match the size of a
1109 /// vector register. For wider element types, this could result in
1110 /// creating vectors that span multiple vector registers.
1111 /// If false, the vectorization factor will be chosen based on the
1112 /// size of the widest element type.
1113 /// \p K Register Kind for vectorization.
1115
1116 /// \return The minimum vectorization factor for types of given element
1117 /// bit width, or 0 if there is no minimum VF. The returned value only
1118 /// applies when shouldMaximizeVectorBandwidth returns true.
1119 /// If IsScalable is true, the returned ElementCount must be a scalable VF.
1120 ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const;
1121
1122 /// \return The maximum vectorization factor for types of given element
1123 /// bit width and opcode, or 0 if there is no maximum VF.
1124 /// Currently only used by the SLP vectorizer.
1125 unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const;
1126
1127 /// \return The minimum vectorization factor for the store instruction. Given
1128 /// the initial estimation of the minimum vector factor and store value type,
1129 /// it tries to find possible lowest VF, which still might be profitable for
1130 /// the vectorization.
1131 /// \param VF Initial estimation of the minimum vector factor.
1132 /// \param ScalarMemTy Scalar memory type of the store operation.
1133 /// \param ScalarValTy Scalar type of the stored value.
1134 /// Currently only used by the SLP vectorizer.
1135 unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
1136 Type *ScalarValTy) const;
1137
1138 /// \return True if it should be considered for address type promotion.
1139 /// \p AllowPromotionWithoutCommonHeader Set true if promoting \p I is
1140 /// profitable without finding other extensions fed by the same input.
1142 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const;
1143
1144 /// \return The size of a cache line in bytes.
1145 unsigned getCacheLineSize() const;
1146
1147 /// The possible cache levels
1148 enum class CacheLevel {
1149 L1D, // The L1 data cache
1150 L2D, // The L2 data cache
1151
1152 // We currently do not model L3 caches, as their sizes differ widely between
1153 // microarchitectures. Also, we currently do not have a use for L3 cache
1154 // size modeling yet.
1155 };
1156
1157 /// \return The size of the cache level in bytes, if available.
1158 std::optional<unsigned> getCacheSize(CacheLevel Level) const;
1159
1160 /// \return The associativity of the cache level, if available.
1161 std::optional<unsigned> getCacheAssociativity(CacheLevel Level) const;
1162
1163 /// \return How much before a load we should place the prefetch
1164 /// instruction. This is currently measured in number of
1165 /// instructions.
1166 unsigned getPrefetchDistance() const;
1167
1168 /// Some HW prefetchers can handle accesses up to a certain constant stride.
1169 /// Sometimes prefetching is beneficial even below the HW prefetcher limit,
1170 /// and the arguments provided are meant to serve as a basis for deciding this
1171 /// for a particular loop.
1172 ///
1173 /// \param NumMemAccesses Number of memory accesses in the loop.
1174 /// \param NumStridedMemAccesses Number of the memory accesses that
1175 /// ScalarEvolution could find a known stride
1176 /// for.
1177 /// \param NumPrefetches Number of software prefetches that will be
1178 /// emitted as determined by the addresses
1179 /// involved and the cache line size.
1180 /// \param HasCall True if the loop contains a call.
1181 ///
1182 /// \return This is the minimum stride in bytes where it makes sense to start
1183 /// adding SW prefetches. The default is 1, i.e. prefetch with any
1184 /// stride.
1185 unsigned getMinPrefetchStride(unsigned NumMemAccesses,
1186 unsigned NumStridedMemAccesses,
1187 unsigned NumPrefetches, bool HasCall) const;
1188
1189 /// \return The maximum number of iterations to prefetch ahead. If
1190 /// the required number of iterations is more than this number, no
1191 /// prefetching is performed.
1192 unsigned getMaxPrefetchIterationsAhead() const;
1193
1194 /// \return True if prefetching should also be done for writes.
1195 bool enableWritePrefetching() const;
1196
1197 /// \return if target want to issue a prefetch in address space \p AS.
1198 bool shouldPrefetchAddressSpace(unsigned AS) const;
1199
1200 /// \return The maximum interleave factor that any transform should try to
1201 /// perform for this target. This number depends on the level of parallelism
1202 /// and the number of execution units in the CPU.
1203 unsigned getMaxInterleaveFactor(ElementCount VF) const;
1204
1205 /// Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
1206 static OperandValueInfo getOperandInfo(const Value *V);
1207
1208 /// This is an approximation of reciprocal throughput of a math/logic op.
1209 /// A higher cost indicates less expected throughput.
1210 /// From Agner Fog's guides, reciprocal throughput is "the average number of
1211 /// clock cycles per instruction when the instructions are not part of a
1212 /// limiting dependency chain."
1213 /// Therefore, costs should be scaled to account for multiple execution units
1214 /// on the target that can process this type of instruction. For example, if
1215 /// there are 5 scalar integer units and 2 vector integer units that can
1216 /// calculate an 'add' in a single cycle, this model should indicate that the
1217 /// cost of the vector add instruction is 2.5 times the cost of the scalar
1218 /// add instruction.
1219 /// \p Args is an optional argument which holds the instruction operands
1220 /// values so the TTI can analyze those values searching for special
1221 /// cases or optimizations based on those values.
1222 /// \p CxtI is the optional original context instruction, if one exists, to
1223 /// provide even more information.
1225 unsigned Opcode, Type *Ty,
1228 TTI::OperandValueInfo Opd2Info = {TTI::OK_AnyValue, TTI::OP_None},
1229 ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
1230 const Instruction *CxtI = nullptr) const;
1231
1232 /// \return The cost of a shuffle instruction of kind Kind and of type Tp.
1233 /// The exact mask may be passed as Mask, or else the array will be empty.
1234 /// The index and subtype parameters are used by the subvector insertion and
1235 /// extraction shuffle kinds to show the insert/extract point and the type of
1236 /// the subvector being inserted/extracted. The operands of the shuffle can be
1237 /// passed through \p Args, which helps improve the cost estimation in some
1238 /// cases, like in broadcast loads.
1239 /// NOTE: For subvector extractions Tp represents the source type.
1240 InstructionCost
1242 ArrayRef<int> Mask = std::nullopt,
1244 int Index = 0, VectorType *SubTp = nullptr,
1245 ArrayRef<const Value *> Args = std::nullopt) const;
1246
1247 /// Represents a hint about the context in which a cast is used.
1248 ///
1249 /// For zext/sext, the context of the cast is the operand, which must be a
1250 /// load of some kind. For trunc, the context is of the cast is the single
1251 /// user of the instruction, which must be a store of some kind.
1252 ///
1253 /// This enum allows the vectorizer to give getCastInstrCost an idea of the
1254 /// type of cast it's dealing with, as not every cast is equal. For instance,
1255 /// the zext of a load may be free, but the zext of an interleaving load can
1256 //// be (very) expensive!
1257 ///
1258 /// See \c getCastContextHint to compute a CastContextHint from a cast
1259 /// Instruction*. Callers can use it if they don't need to override the
1260 /// context and just want it to be calculated from the instruction.
1261 ///
1262 /// FIXME: This handles the types of load/store that the vectorizer can
1263 /// produce, which are the cases where the context instruction is most
1264 /// likely to be incorrect. There are other situations where that can happen
1265 /// too, which might be handled here but in the long run a more general
1266 /// solution of costing multiple instructions at the same times may be better.
1267 enum class CastContextHint : uint8_t {
1268 None, ///< The cast is not used with a load/store of any kind.
1269 Normal, ///< The cast is used with a normal load/store.
1270 Masked, ///< The cast is used with a masked load/store.
1271 GatherScatter, ///< The cast is used with a gather/scatter.
1272 Interleave, ///< The cast is used with an interleaved load/store.
1273 Reversed, ///< The cast is used with a reversed load/store.
1274 };
1275
1276 /// Calculates a CastContextHint from \p I.
1277 /// This should be used by callers of getCastInstrCost if they wish to
1278 /// determine the context from some instruction.
1279 /// \returns the CastContextHint for ZExt/SExt/Trunc, None if \p I is nullptr,
1280 /// or if it's another type of cast.
1282
1283 /// \return The expected cost of cast instructions, such as bitcast, trunc,
1284 /// zext, etc. If there is an existing instruction that holds Opcode, it
1285 /// may be passed in the 'I' parameter.
1287 getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
1290 const Instruction *I = nullptr) const;
1291
1292 /// \return The expected cost of a sign- or zero-extended vector extract. Use
1293 /// Index = -1 to indicate that there is no information about the index value.
1295 VectorType *VecTy,
1296 unsigned Index) const;
1297
1298 /// \return The expected cost of control-flow related instructions such as
1299 /// Phi, Ret, Br, Switch.
1301 getCFInstrCost(unsigned Opcode,
1303 const Instruction *I = nullptr) const;
1304
1305 /// \returns The expected cost of compare and select instructions. If there
1306 /// is an existing instruction that holds Opcode, it may be passed in the
1307 /// 'I' parameter. The \p VecPred parameter can be used to indicate the select
1308 /// is using a compare with the specified predicate as condition. When vector
1309 /// types are passed, \p VecPred must be used for all lanes.
1311 getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
1312 CmpInst::Predicate VecPred,
1314 const Instruction *I = nullptr) const;
1315
1316 /// \return The expected cost of vector Insert and Extract.
1317 /// Use -1 to indicate that there is no information on the index value.
1318 /// This is used when the instruction is not available; a typical use
1319 /// case is to provision the cost of vectorization/scalarization in
1320 /// vectorizer passes.
1323 unsigned Index = -1, Value *Op0 = nullptr,
1324 Value *Op1 = nullptr) const;
1325
1326 /// \return The expected cost of vector Insert and Extract.
1327 /// This is used when instruction is available, and implementation
1328 /// asserts 'I' is not nullptr.
1329 ///
1330 /// A typical suitable use case is cost estimation when vector instruction
1331 /// exists (e.g., from basic blocks during transformation).
1334 unsigned Index = -1) const;
1335
1336 /// \return The cost of replication shuffle of \p VF elements typed \p EltTy
1337 /// \p ReplicationFactor times.
1338 ///
1339 /// For example, the mask for \p ReplicationFactor=3 and \p VF=4 is:
1340 /// <0,0,0,1,1,1,2,2,2,3,3,3>
1341 InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor,
1342 int VF,
1343 const APInt &DemandedDstElts,
1345
1346 /// \return The cost of Load and Store instructions.
1348 getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
1349 unsigned AddressSpace,
1351 OperandValueInfo OpdInfo = {OK_AnyValue, OP_None},
1352 const Instruction *I = nullptr) const;
1353
1354 /// \return The cost of VP Load and Store instructions.
1355 InstructionCost
1356 getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
1357 unsigned AddressSpace,
1359 const Instruction *I = nullptr) const;
1360
1361 /// \return The cost of masked Load and Store instructions.
1363 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1365
1366 /// \return The cost of Gather or Scatter operation
1367 /// \p Opcode - is a type of memory access Load or Store
1368 /// \p DataTy - a vector type of the data to be loaded or stored
1369 /// \p Ptr - pointer [or vector of pointers] - address[es] in memory
1370 /// \p VariableMask - true when the memory access is predicated with a mask
1371 /// that is not a compile-time constant
1372 /// \p Alignment - alignment of single element
1373 /// \p I - the optional original context instruction, if one exists, e.g. the
1374 /// load/store to transform or the call to the gather/scatter intrinsic
1376 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
1378 const Instruction *I = nullptr) const;
1379
1380 /// \return The cost of the interleaved memory operation.
1381 /// \p Opcode is the memory operation code
1382 /// \p VecTy is the vector type of the interleaved access.
1383 /// \p Factor is the interleave factor
1384 /// \p Indices is the indices for interleaved load members (as interleaved
1385 /// load allows gaps)
1386 /// \p Alignment is the alignment of the memory operation
1387 /// \p AddressSpace is address space of the pointer.
1388 /// \p UseMaskForCond indicates if the memory access is predicated.
1389 /// \p UseMaskForGaps indicates if gaps should be masked.
1391 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
1392 Align Alignment, unsigned AddressSpace,
1394 bool UseMaskForCond = false, bool UseMaskForGaps = false) const;
1395
1396 /// A helper function to determine the type of reduction algorithm used
1397 /// for a given \p Opcode and set of FastMathFlags \p FMF.
1398 static bool requiresOrderedReduction(std::optional<FastMathFlags> FMF) {
1399 return FMF && !(*FMF).allowReassoc();
1400 }
1401
1402 /// Calculate the cost of vector reduction intrinsics.
1403 ///
1404 /// This is the cost of reducing the vector value of type \p Ty to a scalar
1405 /// value using the operation denoted by \p Opcode. The FastMathFlags
1406 /// parameter \p FMF indicates what type of reduction we are performing:
1407 /// 1. Tree-wise. This is the typical 'fast' reduction performed that
1408 /// involves successively splitting a vector into half and doing the
1409 /// operation on the pair of halves until you have a scalar value. For
1410 /// example:
1411 /// (v0, v1, v2, v3)
1412 /// ((v0+v2), (v1+v3), undef, undef)
1413 /// ((v0+v2+v1+v3), undef, undef, undef)
1414 /// This is the default behaviour for integer operations, whereas for
1415 /// floating point we only do this if \p FMF indicates that
1416 /// reassociation is allowed.
1417 /// 2. Ordered. For a vector with N elements this involves performing N
1418 /// operations in lane order, starting with an initial scalar value, i.e.
1419 /// result = InitVal + v0
1420 /// result = result + v1
1421 /// result = result + v2
1422 /// result = result + v3
1423 /// This is only the case for FP operations and when reassociation is not
1424 /// allowed.
1425 ///
1427 unsigned Opcode, VectorType *Ty, std::optional<FastMathFlags> FMF,
1429
1433
1434 /// Calculate the cost of an extended reduction pattern, similar to
1435 /// getArithmeticReductionCost of an Add reduction with multiply and optional
1436 /// extensions. This is the cost of as:
1437 /// ResTy vecreduce.add(mul (A, B)).
1438 /// ResTy vecreduce.add(mul(ext(Ty A), ext(Ty B)).
1440 bool IsUnsigned, Type *ResTy, VectorType *Ty,
1442
1443 /// Calculate the cost of an extended reduction pattern, similar to
1444 /// getArithmeticReductionCost of a reduction with an extension.
1445 /// This is the cost of as:
1446 /// ResTy vecreduce.opcode(ext(Ty A)).
1448 unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
1449 FastMathFlags FMF,
1451
1452 /// \returns The cost of Intrinsic instructions. Analyses the real arguments.
1453 /// Three cases are handled: 1. scalar instruction 2. vector instruction
1454 /// 3. scalar instruction which is to be vectorized.
1457
1458 /// \returns The cost of Call instructions.
1462
1463 /// \returns The number of pieces into which the provided type must be
1464 /// split during legalization. Zero is returned when the answer is unknown.
1465 unsigned getNumberOfParts(Type *Tp) const;
1466
1467 /// \returns The cost of the address computation. For most targets this can be
1468 /// merged into the instruction indexing mode. Some targets might want to
1469 /// distinguish between address computation for memory operations on vector
1470 /// types and scalar types. Such targets should override this function.
1471 /// The 'SE' parameter holds pointer for the scalar evolution object which
1472 /// is used in order to get the Ptr step value in case of constant stride.
1473 /// The 'Ptr' parameter holds SCEV of the access pointer.
1475 ScalarEvolution *SE = nullptr,
1476 const SCEV *Ptr = nullptr) const;
1477
1478 /// \returns The cost, if any, of keeping values of the given types alive
1479 /// over a callsite.
1480 ///
1481 /// Some types may require the use of register classes that do not have
1482 /// any callee-saved registers, so would require a spill and fill.
1484
1485 /// \returns True if the intrinsic is a supported memory intrinsic. Info
1486 /// will contain additional information - whether the intrinsic may write
1487 /// or read to memory, volatility and the pointer. Info is undefined
1488 /// if false is returned.
1490
1491 /// \returns The maximum element size, in bytes, for an element
1492 /// unordered-atomic memory intrinsic.
1493 unsigned getAtomicMemIntrinsicMaxElementSize() const;
1494
1495 /// \returns A value which is the result of the given memory intrinsic. New
1496 /// instructions may be created to extract the result from the given intrinsic
1497 /// memory operation. Returns nullptr if the target cannot create a result
1498 /// from the given intrinsic.
1500 Type *ExpectedType) const;
1501
1502 /// \returns The type to use in a loop expansion of a memcpy call.
1504 LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
1505 unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign,
1506 std::optional<uint32_t> AtomicElementSize = std::nullopt) const;
1507
1508 /// \param[out] OpsOut The operand types to copy RemainingBytes of memory.
1509 /// \param RemainingBytes The number of bytes to copy.
1510 ///
1511 /// Calculates the operand types to use when copying \p RemainingBytes of
1512 /// memory, where source and destination alignments are \p SrcAlign and
1513 /// \p DestAlign respectively.
1515 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
1516 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
1517 unsigned SrcAlign, unsigned DestAlign,
1518 std::optional<uint32_t> AtomicCpySize = std::nullopt) const;
1519
1520 /// \returns True if the two functions have compatible attributes for inlining
1521 /// purposes.
1522 bool areInlineCompatible(const Function *Caller,
1523 const Function *Callee) const;
1524
1525 /// Returns a penalty for invoking call \p Call in \p F.
1526 /// For example, if a function F calls a function G, which in turn calls
1527 /// function H, then getInlineCallPenalty(F, H()) would return the
1528 /// penalty of calling H from F, e.g. after inlining G into F.
1529 /// \p DefaultCallPenalty is passed to give a default penalty that
1530 /// the target can amend or override.
1531 unsigned getInlineCallPenalty(const Function *F, const CallBase &Call,
1532 unsigned DefaultCallPenalty) const;
1533
1534 /// \returns True if the caller and callee agree on how \p Types will be
1535 /// passed to or returned from the callee.
1536 /// to the callee.
1537 /// \param Types List of types to check.
1538 bool areTypesABICompatible(const Function *Caller, const Function *Callee,
1539 const ArrayRef<Type *> &Types) const;
1540
1541 /// The type of load/store indexing.
1543 MIM_Unindexed, ///< No indexing.
1544 MIM_PreInc, ///< Pre-incrementing.
1545 MIM_PreDec, ///< Pre-decrementing.
1546 MIM_PostInc, ///< Post-incrementing.
1547 MIM_PostDec ///< Post-decrementing.
1549
1550 /// \returns True if the specified indexed load for the given type is legal.
1551 bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const;
1552
1553 /// \returns True if the specified indexed store for the given type is legal.
1554 bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const;
1555
1556 /// \returns The bitwidth of the largest vector type that should be used to
1557 /// load/store in the given address space.
1558 unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
1559
1560 /// \returns True if the load instruction is legal to vectorize.
1561 bool isLegalToVectorizeLoad(LoadInst *LI) const;
1562
1563 /// \returns True if the store instruction is legal to vectorize.
1564 bool isLegalToVectorizeStore(StoreInst *SI) const;
1565
1566 /// \returns True if it is legal to vectorize the given load chain.
1567 bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
1568 unsigned AddrSpace) const;
1569
1570 /// \returns True if it is legal to vectorize the given store chain.
1571 bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
1572 unsigned AddrSpace) const;
1573
1574 /// \returns True if it is legal to vectorize the given reduction kind.
1576 ElementCount VF) const;
1577
1578 /// \returns True if the given type is supported for scalable vectors
1580
1581 /// \returns The new vector factor value if the target doesn't support \p
1582 /// SizeInBytes loads or has a better vector factor.
1583 unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
1584 unsigned ChainSizeInBytes,
1585 VectorType *VecTy) const;
1586
1587 /// \returns The new vector factor value if the target doesn't support \p
1588 /// SizeInBytes stores or has a better vector factor.
1589 unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
1590 unsigned ChainSizeInBytes,
1591 VectorType *VecTy) const;
1592
1593 /// Flags describing the kind of vector reduction.
1595 ReductionFlags() = default;
1596 bool IsMaxOp =
1597 false; ///< If the op a min/max kind, true if it's a max operation.
1598 bool IsSigned = false; ///< Whether the operation is a signed int reduction.
1599 bool NoNaN =
1600 false; ///< If op is an fp min/max, whether NaNs may be present.
1601 };
1602
1603 /// \returns True if the target prefers reductions in loop.
1604 bool preferInLoopReduction(unsigned Opcode, Type *Ty,
1605 ReductionFlags Flags) const;
1606
1607 /// \returns True if the target prefers reductions select kept in the loop
1608 /// when tail folding. i.e.
1609 /// loop:
1610 /// p = phi (0, s)
1611 /// a = add (p, x)
1612 /// s = select (mask, a, p)
1613 /// vecreduce.add(s)
1614 ///
1615 /// As opposed to the normal scheme of p = phi (0, a) which allows the select
1616 /// to be pulled out of the loop. If the select(.., add, ..) can be predicated
1617 /// by the target, this can lead to cleaner code generation.
1618 bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
1619 ReductionFlags Flags) const;
1620
1621 /// Return true if the loop vectorizer should consider vectorizing an
1622 /// otherwise scalar epilogue loop.
1623 bool preferEpilogueVectorization() const;
1624
1625 /// \returns True if the target wants to expand the given reduction intrinsic
1626 /// into a shuffle sequence.
1627 bool shouldExpandReduction(const IntrinsicInst *II) const;
1628
1629 /// \returns the size cost of rematerializing a GlobalValue address relative
1630 /// to a stack reload.
1631 unsigned getGISelRematGlobalCost() const;
1632
1633 /// \returns the lower bound of a trip count to decide on vectorization
1634 /// while tail-folding.
1635 unsigned getMinTripCountTailFoldingThreshold() const;
1636
1637 /// \returns True if the target supports scalable vectors.
1638 bool supportsScalableVectors() const;
1639
1640 /// \return true when scalable vectorization is preferred.
1641 bool enableScalableVectorization() const;
1642
1643 /// \name Vector Predication Information
1644 /// @{
1645 /// Whether the target supports the %evl parameter of VP intrinsic efficiently
1646 /// in hardware, for the given opcode and type/alignment. (see LLVM Language
1647 /// Reference - "Vector Predication Intrinsics").
1648 /// Use of %evl is discouraged when that is not the case.
1649 bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
1650 Align Alignment) const;
1651
1654 // keep the predicating parameter
1656 // where legal, discard the predicate parameter
1658 // transform into something else that is also predicating
1659 Convert = 2
1661
1662 // How to transform the EVL parameter.
1663 // Legal: keep the EVL parameter as it is.
1664 // Discard: Ignore the EVL parameter where it is safe to do so.
1665 // Convert: Fold the EVL into the mask parameter.
1667
1668 // How to transform the operator.
1669 // Legal: The target supports this operator.
1670 // Convert: Convert this to a non-VP operation.
1671 // The 'Discard' strategy is invalid.
1673
1674 bool shouldDoNothing() const {
1675 return (EVLParamStrategy == Legal) && (OpStrategy == Legal);
1676 }
1679 };
1680
1681 /// \returns How the target needs this vector-predicated operation to be
1682 /// transformed.
1684 /// @}
1685
1686 /// \returns Whether a 32-bit branch instruction is available in Arm or Thumb
1687 /// state.
1688 ///
1689 /// Used by the LowerTypeTests pass, which constructs an IR inline assembler
1690 /// node containing a jump table in a format suitable for the target, so it
1691 /// needs to know what format of jump table it can legally use.
1692 ///
1693 /// For non-Arm targets, this function isn't used. It defaults to returning
1694 /// false, but it shouldn't matter what it returns anyway.
1695 bool hasArmWideBranch(bool Thumb) const;
1696
1697 /// \return The maximum number of function arguments the target supports.
1698 unsigned getMaxNumArgs() const;
1699
1700 /// @}
1701
1702private:
1703 /// The abstract base class used to type erase specific TTI
1704 /// implementations.
1705 class Concept;
1706
1707 /// The template model for the base class which wraps a concrete
1708 /// implementation in a type erased interface.
1709 template <typename T> class Model;
1710
1711 std::unique_ptr<Concept> TTIImpl;
1712};
1713
1715public:
1716 virtual ~Concept() = 0;
1717 virtual const DataLayout &getDataLayout() const = 0;
1718 virtual InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr,
1720 Type *AccessType,
1722 virtual InstructionCost
1724 const TTI::PointersChainInfo &Info, Type *AccessTy,
1726 virtual unsigned getInliningThresholdMultiplier() const = 0;
1728 virtual unsigned
1730 virtual unsigned adjustInliningThreshold(const CallBase *CB) = 0;
1731 virtual int getInlinerVectorBonusPercent() const = 0;
1732 virtual unsigned getCallerAllocaCost(const CallBase *CB,
1733 const AllocaInst *AI) const = 0;
1736 virtual unsigned
1738 ProfileSummaryInfo *PSI,
1739 BlockFrequencyInfo *BFI) = 0;
1744 virtual bool hasBranchDivergence(const Function *F = nullptr) = 0;
1745 virtual bool isSourceOfDivergence(const Value *V) = 0;
1746 virtual bool isAlwaysUniform(const Value *V) = 0;
1747 virtual bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const = 0;
1748 virtual bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const = 0;
1749 virtual unsigned getFlatAddressSpace() = 0;
1751 Intrinsic::ID IID) const = 0;
1752 virtual bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const = 0;
1753 virtual bool
1755 virtual unsigned getAssumedAddrSpace(const Value *V) const = 0;
1756 virtual bool isSingleThreaded() const = 0;
1757 virtual std::pair<const Value *, unsigned>
1758 getPredicatedAddrSpace(const Value *V) const = 0;
1760 Value *OldV,
1761 Value *NewV) const = 0;
1762 virtual bool isLoweredToCall(const Function *F) = 0;
1765 OptimizationRemarkEmitter *ORE) = 0;
1767 PeelingPreferences &PP) = 0;
1769 AssumptionCache &AC,
1770 TargetLibraryInfo *LibInfo,
1771 HardwareLoopInfo &HWLoopInfo) = 0;
1773 virtual TailFoldingStyle
1774 getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) = 0;
1775 virtual std::optional<Instruction *> instCombineIntrinsic(
1776 InstCombiner &IC, IntrinsicInst &II) = 0;
1777 virtual std::optional<Value *> simplifyDemandedUseBitsIntrinsic(
1778 InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask,
1779 KnownBits & Known, bool &KnownBitsComputed) = 0;
1780 virtual std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
1781 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts,
1782 APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
1783 std::function<void(Instruction *, unsigned, APInt, APInt &)>
1784 SimplifyAndSetOp) = 0;
1785 virtual bool isLegalAddImmediate(int64_t Imm) = 0;
1786 virtual bool isLegalICmpImmediate(int64_t Imm) = 0;
1787 virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
1788 int64_t BaseOffset, bool HasBaseReg,
1789 int64_t Scale, unsigned AddrSpace,
1790 Instruction *I) = 0;
1792 const TargetTransformInfo::LSRCost &C2) = 0;
1793 virtual bool isNumRegsMajorCostOfLSR() = 0;
1796 virtual bool canMacroFuseCmp() = 0;
1797 virtual bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE,
1799 TargetLibraryInfo *LibInfo) = 0;
1800 virtual AddressingModeKind
1802 virtual bool isLegalMaskedStore(Type *DataType, Align Alignment) = 0;
1803 virtual bool isLegalMaskedLoad(Type *DataType, Align Alignment) = 0;
1804 virtual bool isLegalNTStore(Type *DataType, Align Alignment) = 0;
1805 virtual bool isLegalNTLoad(Type *DataType, Align Alignment) = 0;
1806 virtual bool isLegalBroadcastLoad(Type *ElementTy,
1807 ElementCount NumElements) const = 0;
1808 virtual bool isLegalMaskedScatter(Type *DataType, Align Alignment) = 0;
1809 virtual bool isLegalMaskedGather(Type *DataType, Align Alignment) = 0;
1811 Align Alignment) = 0;
1813 Align Alignment) = 0;
1814 virtual bool isLegalMaskedCompressStore(Type *DataType) = 0;
1815 virtual bool isLegalMaskedExpandLoad(Type *DataType) = 0;
1816 virtual bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0,
1817 unsigned Opcode1,
1818 const SmallBitVector &OpcodeMask) const = 0;
1819 virtual bool enableOrderedReductions() = 0;
1820 virtual bool hasDivRemOp(Type *DataType, bool IsSigned) = 0;
1821 virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) = 0;
1824 int64_t BaseOffset,
1825 bool HasBaseReg, int64_t Scale,
1826 unsigned AddrSpace) = 0;
1827 virtual bool LSRWithInstrQueries() = 0;
1828 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) = 0;
1830 virtual bool useAA() = 0;
1831 virtual bool isTypeLegal(Type *Ty) = 0;
1832 virtual unsigned getRegUsageForType(Type *Ty) = 0;
1833 virtual bool shouldBuildLookupTables() = 0;
1835 virtual bool shouldBuildRelLookupTables() = 0;
1836 virtual bool useColdCCForColdCall(Function &F) = 0;
1838 const APInt &DemandedElts,
1839 bool Insert, bool Extract,
1841 virtual InstructionCost
1843 ArrayRef<Type *> Tys,
1846 virtual bool supportsTailCalls() = 0;
1847 virtual bool supportsTailCallFor(const CallBase *CB) = 0;
1848 virtual bool enableAggressiveInterleaving(bool LoopHasReductions) = 0;
1850 enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const = 0;
1851 virtual bool enableSelectOptimize() = 0;
1856 unsigned BitWidth,
1857 unsigned AddressSpace,
1858 Align Alignment,
1859 unsigned *Fast) = 0;
1860 virtual PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) = 0;
1861 virtual bool haveFastSqrt(Type *Ty) = 0;
1863 virtual bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) = 0;
1865 virtual InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx,
1866 const APInt &Imm, Type *Ty) = 0;
1867 virtual InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
1869 virtual InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx,
1870 const APInt &Imm, Type *Ty,
1872 Instruction *Inst = nullptr) = 0;
1874 const APInt &Imm, Type *Ty,
1876 virtual unsigned getNumberOfRegisters(unsigned ClassID) const = 0;
1877 virtual unsigned getRegisterClassForType(bool Vector,
1878 Type *Ty = nullptr) const = 0;
1879 virtual const char *getRegisterClassName(unsigned ClassID) const = 0;
1881 virtual unsigned getMinVectorRegisterBitWidth() const = 0;
1882 virtual std::optional<unsigned> getMaxVScale() const = 0;
1883 virtual std::optional<unsigned> getVScaleForTuning() const = 0;
1884 virtual bool isVScaleKnownToBeAPowerOfTwo() const = 0;
1885 virtual bool
1887 virtual ElementCount getMinimumVF(unsigned ElemWidth,
1888 bool IsScalable) const = 0;
1889 virtual unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const = 0;
1890 virtual unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
1891 Type *ScalarValTy) const = 0;
1893 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) = 0;
1894 virtual unsigned getCacheLineSize() const = 0;
1895 virtual std::optional<unsigned> getCacheSize(CacheLevel Level) const = 0;
1896 virtual std::optional<unsigned> getCacheAssociativity(CacheLevel Level)
1897 const = 0;
1898
1899 /// \return How much before a load we should place the prefetch
1900 /// instruction. This is currently measured in number of
1901 /// instructions.
1902 virtual unsigned getPrefetchDistance() const = 0;
1903
1904 /// \return Some HW prefetchers can handle accesses up to a certain
1905 /// constant stride. This is the minimum stride in bytes where it
1906 /// makes sense to start adding SW prefetches. The default is 1,
1907 /// i.e. prefetch with any stride. Sometimes prefetching is beneficial
1908 /// even below the HW prefetcher limit, and the arguments provided are
1909 /// meant to serve as a basis for deciding this for a particular loop.
1910 virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses,
1911 unsigned NumStridedMemAccesses,
1912 unsigned NumPrefetches,
1913 bool HasCall) const = 0;
1914
1915 /// \return The maximum number of iterations to prefetch ahead. If
1916 /// the required number of iterations is more than this number, no
1917 /// prefetching is performed.
1918 virtual unsigned getMaxPrefetchIterationsAhead() const = 0;
1919
1920 /// \return True if prefetching should also be done for writes.
1921 virtual bool enableWritePrefetching() const = 0;
1922
1923 /// \return if target want to issue a prefetch in address space \p AS.
1924 virtual bool shouldPrefetchAddressSpace(unsigned AS) const = 0;
1925
1926 virtual unsigned getMaxInterleaveFactor(ElementCount VF) = 0;
1928 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
1929 OperandValueInfo Opd1Info, OperandValueInfo Opd2Info,
1930 ArrayRef<const Value *> Args, const Instruction *CxtI = nullptr) = 0;
1931
1933 ArrayRef<int> Mask,
1935 int Index, VectorType *SubTp,
1936 ArrayRef<const Value *> Args) = 0;
1938 Type *Src, CastContextHint CCH,
1940 const Instruction *I) = 0;
1942 VectorType *VecTy,
1943 unsigned Index) = 0;
1946 const Instruction *I = nullptr) = 0;
1948 Type *CondTy,
1949 CmpInst::Predicate VecPred,
1951 const Instruction *I) = 0;
1954 unsigned Index, Value *Op0,
1955 Value *Op1) = 0;
1958 unsigned Index) = 0;
1959
1960 virtual InstructionCost
1961 getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF,
1962 const APInt &DemandedDstElts,
1964
1965 virtual InstructionCost
1966 getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
1968 OperandValueInfo OpInfo, const Instruction *I) = 0;
1970 Align Alignment,
1971 unsigned AddressSpace,
1973 const Instruction *I) = 0;
1974 virtual InstructionCost
1975 getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
1976 unsigned AddressSpace,
1978 virtual InstructionCost
1979 getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr,
1980 bool VariableMask, Align Alignment,
1982 const Instruction *I = nullptr) = 0;
1983
1985 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
1986 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
1987 bool UseMaskForCond = false, bool UseMaskForGaps = false) = 0;
1988 virtual InstructionCost
1990 std::optional<FastMathFlags> FMF,
1992 virtual InstructionCost
1996 unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
1997 FastMathFlags FMF,
2000 bool IsUnsigned, Type *ResTy, VectorType *Ty,
2002 virtual InstructionCost
2006 ArrayRef<Type *> Tys,
2008 virtual unsigned getNumberOfParts(Type *Tp) = 0;
2009 virtual InstructionCost
2011 virtual InstructionCost
2014 MemIntrinsicInfo &Info) = 0;
2015 virtual unsigned getAtomicMemIntrinsicMaxElementSize() const = 0;
2017 Type *ExpectedType) = 0;
2019 LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
2020 unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign,
2021 std::optional<uint32_t> AtomicElementSize) const = 0;
2022
2024 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
2025 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
2026 unsigned SrcAlign, unsigned DestAlign,
2027 std::optional<uint32_t> AtomicCpySize) const = 0;
2028 virtual bool areInlineCompatible(const Function *Caller,
2029 const Function *Callee) const = 0;
2030 virtual unsigned getInlineCallPenalty(const Function *F, const CallBase &Call,
2031 unsigned DefaultCallPenalty) const = 0;
2032 virtual bool areTypesABICompatible(const Function *Caller,
2033 const Function *Callee,
2034 const ArrayRef<Type *> &Types) const = 0;
2035 virtual bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const = 0;
2036 virtual bool isIndexedStoreLegal(MemIndexedMode Mode, Type *Ty) const = 0;
2037 virtual unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const = 0;
2038 virtual bool isLegalToVectorizeLoad(LoadInst *LI) const = 0;
2039 virtual bool isLegalToVectorizeStore(StoreInst *SI) const = 0;
2040 virtual bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
2041 Align Alignment,
2042 unsigned AddrSpace) const = 0;
2043 virtual bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
2044 Align Alignment,
2045 unsigned AddrSpace) const = 0;
2047 ElementCount VF) const = 0;
2048 virtual bool isElementTypeLegalForScalableVector(Type *Ty) const = 0;
2049 virtual unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
2050 unsigned ChainSizeInBytes,
2051 VectorType *VecTy) const = 0;
2052 virtual unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
2053 unsigned ChainSizeInBytes,
2054 VectorType *VecTy) const = 0;
2055 virtual bool preferInLoopReduction(unsigned Opcode, Type *Ty,
2056 ReductionFlags) const = 0;
2057 virtual bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
2058 ReductionFlags) const = 0;
2059 virtual bool preferEpilogueVectorization() const = 0;
2060
2061 virtual bool shouldExpandReduction(const IntrinsicInst *II) const = 0;
2062 virtual unsigned getGISelRematGlobalCost() const = 0;
2063 virtual unsigned getMinTripCountTailFoldingThreshold() const = 0;
2064 virtual bool enableScalableVectorization() const = 0;
2065 virtual bool supportsScalableVectors() const = 0;
2066 virtual bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
2067 Align Alignment) const = 0;
2068 virtual VPLegalization
2070 virtual bool hasArmWideBranch(bool Thumb) const = 0;
2071 virtual unsigned getMaxNumArgs() const = 0;
2072};
2073
2074template <typename T>
2075class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
2076 T Impl;
2077
2078public:
2079 Model(T Impl) : Impl(std::move(Impl)) {}
2080 ~Model() override = default;
2081
2082 const DataLayout &getDataLayout() const override {
2083 return Impl.getDataLayout();
2084 }
2085
2086 InstructionCost
2087 getGEPCost(Type *PointeeType, const Value *Ptr,
2088 ArrayRef<const Value *> Operands, Type *AccessType,
2090 return Impl.getGEPCost(PointeeType, Ptr, Operands, AccessType, CostKind);
2091 }
2092 InstructionCost getPointersChainCost(ArrayRef<const Value *> Ptrs,
2093 const Value *Base,
2094 const PointersChainInfo &Info,
2095 Type *AccessTy,
2096 TargetCostKind CostKind) override {
2097 return Impl.getPointersChainCost(Ptrs, Base, Info, AccessTy, CostKind);
2098 }
2099 unsigned getInliningThresholdMultiplier() const override {
2100 return Impl.getInliningThresholdMultiplier();
2101 }
2102 unsigned adjustInliningThreshold(const CallBase *CB) override {
2103 return Impl.adjustInliningThreshold(CB);
2104 }
2105 unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const override {
2106 return Impl.getInliningCostBenefitAnalysisSavingsMultiplier();
2107 }
2108 unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const override {
2109 return Impl.getInliningCostBenefitAnalysisProfitableMultiplier();
2110 }
2111 int getInlinerVectorBonusPercent() const override {
2112 return Impl.getInlinerVectorBonusPercent();
2113 }
2114 unsigned getCallerAllocaCost(const CallBase *CB,
2115 const AllocaInst *AI) const override {
2116 return Impl.getCallerAllocaCost(CB, AI);
2117 }
2118 InstructionCost getMemcpyCost(const Instruction *I) override {
2119 return Impl.getMemcpyCost(I);
2120 }
2121
2122 uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override {
2123 return Impl.getMaxMemIntrinsicInlineSizeThreshold();
2124 }
2125
2126 InstructionCost getInstructionCost(const User *U,
2127 ArrayRef<const Value *> Operands,
2128 TargetCostKind CostKind) override {
2129 return Impl.getInstructionCost(U, Operands, CostKind);
2130 }
2131 BranchProbability getPredictableBranchThreshold() override {
2132 return Impl.getPredictableBranchThreshold();
2133 }
2134 bool hasBranchDivergence(const Function *F = nullptr) override {
2135 return Impl.hasBranchDivergence(F);
2136 }
2137 bool isSourceOfDivergence(const Value *V) override {
2138 return Impl.isSourceOfDivergence(V);
2139 }
2140
2141 bool isAlwaysUniform(const Value *V) override {
2142 return Impl.isAlwaysUniform(V);
2143 }
2144
2145 bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const override {
2146 return Impl.isValidAddrSpaceCast(FromAS, ToAS);
2147 }
2148
2149 bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const override {
2150 return Impl.addrspacesMayAlias(AS0, AS1);
2151 }
2152
2153 unsigned getFlatAddressSpace() override { return Impl.getFlatAddressSpace(); }
2154
2155 bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
2156 Intrinsic::ID IID) const override {
2157 return Impl.collectFlatAddressOperands(OpIndexes, IID);
2158 }
2159
2160 bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const override {
2161 return Impl.isNoopAddrSpaceCast(FromAS, ToAS);
2162 }
2163
2164 bool
2165 canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const override {
2166 return Impl.canHaveNonUndefGlobalInitializerInAddressSpace(AS);
2167 }
2168
2169 unsigned getAssumedAddrSpace(const Value *V) const override {
2170 return Impl.getAssumedAddrSpace(V);
2171 }
2172
2173 bool isSingleThreaded() const override { return Impl.isSingleThreaded(); }
2174
2175 std::pair<const Value *, unsigned>
2176 getPredicatedAddrSpace(const Value *V) const override {
2177 return Impl.getPredicatedAddrSpace(V);
2178 }
2179
2180 Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV,
2181 Value *NewV) const override {
2182 return Impl.rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
2183 }
2184
2185 bool isLoweredToCall(const Function *F) override {
2186 return Impl.isLoweredToCall(F);
2187 }
2188 void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
2189 UnrollingPreferences &UP,
2190 OptimizationRemarkEmitter *ORE) override {
2191 return Impl.getUnrollingPreferences(L, SE, UP, ORE);
2192 }
2193 void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
2194 PeelingPreferences &PP) override {
2195 return Impl.getPeelingPreferences(L, SE, PP);
2196 }
2197 bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
2198 AssumptionCache &AC, TargetLibraryInfo *LibInfo,
2199 HardwareLoopInfo &HWLoopInfo) override {
2200 return Impl.isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
2201 }
2202 bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) override {
2203 return Impl.preferPredicateOverEpilogue(TFI);
2204 }
2206 getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) override {
2207 return Impl.getPreferredTailFoldingStyle(IVUpdateMayOverflow);
2208 }
2209 std::optional<Instruction *>
2210 instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) override {
2211 return Impl.instCombineIntrinsic(IC, II);
2212 }
2213 std::optional<Value *>
2214 simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
2215 APInt DemandedMask, KnownBits &Known,
2216 bool &KnownBitsComputed) override {
2217 return Impl.simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
2218 KnownBitsComputed);
2219 }
2220 std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
2221 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
2222 APInt &UndefElts2, APInt &UndefElts3,
2223 std::function<void(Instruction *, unsigned, APInt, APInt &)>
2224 SimplifyAndSetOp) override {
2225 return Impl.simplifyDemandedVectorEltsIntrinsic(
2226 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
2227 SimplifyAndSetOp);
2228 }
2229 bool isLegalAddImmediate(int64_t Imm) override {
2230 return Impl.isLegalAddImmediate(Imm);
2231 }
2232 bool isLegalICmpImmediate(int64_t Imm) override {
2233 return Impl.isLegalICmpImmediate(Imm);
2234 }
2235 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
2236 bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
2237 Instruction *I) override {
2238 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
2239 AddrSpace, I);
2240 }
2241 bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
2242 const TargetTransformInfo::LSRCost &C2) override {
2243 return Impl.isLSRCostLess(C1, C2);
2244 }
2245 bool isNumRegsMajorCostOfLSR() override {
2246 return Impl.isNumRegsMajorCostOfLSR();
2247 }
2248 bool shouldFoldTerminatingConditionAfterLSR() const override {
2249 return Impl.shouldFoldTerminatingConditionAfterLSR();
2250 }
2251 bool isProfitableLSRChainElement(Instruction *I) override {
2252 return Impl.isProfitableLSRChainElement(I);
2253 }
2254 bool canMacroFuseCmp() override { return Impl.canMacroFuseCmp(); }
2255 bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI,
2256 DominatorTree *DT, AssumptionCache *AC,
2257 TargetLibraryInfo *LibInfo) override {
2258 return Impl.canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
2259 }
2261 getPreferredAddressingMode(const Loop *L,
2262 ScalarEvolution *SE) const override {
2263 return Impl.getPreferredAddressingMode(L, SE);
2264 }
2265 bool isLegalMaskedStore(Type *DataType, Align Alignment) override {
2266 return Impl.isLegalMaskedStore(DataType, Alignment);
2267 }
2268 bool isLegalMaskedLoad(Type *DataType, Align Alignment) override {
2269 return Impl.isLegalMaskedLoad(DataType, Alignment);
2270 }
2271 bool isLegalNTStore(Type *DataType, Align Alignment) override {
2272 return Impl.isLegalNTStore(DataType, Alignment);
2273 }
2274 bool isLegalNTLoad(Type *DataType, Align Alignment) override {
2275 return Impl.isLegalNTLoad(DataType, Alignment);
2276 }
2277 bool isLegalBroadcastLoad(Type *ElementTy,
2278 ElementCount NumElements) const override {
2279 return Impl.isLegalBroadcastLoad(ElementTy, NumElements);
2280 }
2281 bool isLegalMaskedScatter(Type *DataType, Align Alignment) override {
2282 return Impl.isLegalMaskedScatter(DataType, Alignment);
2283 }
2284 bool isLegalMaskedGather(Type *DataType, Align Alignment) override {
2285 return Impl.isLegalMaskedGather(DataType, Alignment);
2286 }
2287 bool forceScalarizeMaskedGather(VectorType *DataType,
2288 Align Alignment) override {
2289 return Impl.forceScalarizeMaskedGather(DataType, Alignment);
2290 }
2291 bool forceScalarizeMaskedScatter(VectorType *DataType,
2292 Align Alignment) override {
2293 return Impl.forceScalarizeMaskedScatter(DataType, Alignment);
2294 }
2295 bool isLegalMaskedCompressStore(Type *DataType) override {
2296 return Impl.isLegalMaskedCompressStore(DataType);
2297 }
2298 bool isLegalMaskedExpandLoad(Type *DataType) override {
2299 return Impl.isLegalMaskedExpandLoad(DataType);
2300 }
2301 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
2302 const SmallBitVector &OpcodeMask) const override {
2303 return Impl.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask);
2304 }
2305 bool enableOrderedReductions() override {
2306 return Impl.enableOrderedReductions();
2307 }
2308 bool hasDivRemOp(Type *DataType, bool IsSigned) override {
2309 return Impl.hasDivRemOp(DataType, IsSigned);
2310 }
2311 bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) override {
2312 return Impl.hasVolatileVariant(I, AddrSpace);
2313 }
2314 bool prefersVectorizedAddressing() override {
2315 return Impl.prefersVectorizedAddressing();
2316 }
2317 InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
2318 int64_t BaseOffset, bool HasBaseReg,
2319 int64_t Scale,
2320 unsigned AddrSpace) override {
2321 return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
2322 AddrSpace);
2323 }
2324 bool LSRWithInstrQueries() override { return Impl.LSRWithInstrQueries(); }
2325 bool isTruncateFree(Type *Ty1, Type *Ty2) override {
2326 return Impl.isTruncateFree(Ty1, Ty2);
2327 }
2328 bool isProfitableToHoist(Instruction *I) override {
2329 return Impl.isProfitableToHoist(I);
2330 }
2331 bool useAA() override { return Impl.useAA(); }
2332 bool isTypeLegal(Type *Ty) override { return Impl.isTypeLegal(Ty); }
2333 unsigned getRegUsageForType(Type *Ty) override {
2334 return Impl.getRegUsageForType(Ty);
2335 }
2336 bool shouldBuildLookupTables() override {
2337 return Impl.shouldBuildLookupTables();
2338 }
2339 bool shouldBuildLookupTablesForConstant(Constant *C) override {
2340 return Impl.shouldBuildLookupTablesForConstant(C);
2341 }
2342 bool shouldBuildRelLookupTables() override {
2343 return Impl.shouldBuildRelLookupTables();
2344 }
2345 bool useColdCCForColdCall(Function &F) override {
2346 return Impl.useColdCCForColdCall(F);
2347 }
2348
2349 InstructionCost getScalarizationOverhead(VectorType *Ty,
2350 const APInt &DemandedElts,
2351 bool Insert, bool Extract,
2352 TargetCostKind CostKind) override {
2353 return Impl.getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
2354 CostKind);
2355 }
2356 InstructionCost
2357 getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
2358 ArrayRef<Type *> Tys,
2359 TargetCostKind CostKind) override {
2360 return Impl.getOperandsScalarizationOverhead(Args, Tys, CostKind);
2361 }
2362
2363 bool supportsEfficientVectorElementLoadStore() override {
2364 return Impl.supportsEfficientVectorElementLoadStore();
2365 }
2366
2367 bool supportsTailCalls() override { return Impl.supportsTailCalls(); }
2368 bool supportsTailCallFor(const CallBase *CB) override {
2369 return Impl.supportsTailCallFor(CB);
2370 }
2371
2372 bool enableAggressiveInterleaving(bool LoopHasReductions) override {
2373 return Impl.enableAggressiveInterleaving(LoopHasReductions);
2374 }
2375 MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
2376 bool IsZeroCmp) const override {
2377 return Impl.enableMemCmpExpansion(OptSize, IsZeroCmp);
2378 }
2379 bool enableInterleavedAccessVectorization() override {
2380 return Impl.enableInterleavedAccessVectorization();
2381 }
2382 bool enableSelectOptimize() override {
2383 return Impl.enableSelectOptimize();
2384 }
2385 bool enableMaskedInterleavedAccessVectorization() override {
2386 return Impl.enableMaskedInterleavedAccessVectorization();
2387 }
2388 bool isFPVectorizationPotentiallyUnsafe() override {
2389 return Impl.isFPVectorizationPotentiallyUnsafe();
2390 }
2391 bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth,
2392 unsigned AddressSpace, Align Alignment,
2393 unsigned *Fast) override {
2394 return Impl.allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
2395 Alignment, Fast);
2396 }
2397 PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) override {
2398 return Impl.getPopcntSupport(IntTyWidthInBit);
2399 }
2400 bool haveFastSqrt(Type *Ty) override { return Impl.haveFastSqrt(Ty); }
2401
2402 bool isExpensiveToSpeculativelyExecute(const Instruction* I) override {
2403 return Impl.isExpensiveToSpeculativelyExecute(I);
2404 }
2405
2406 bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) override {
2407 return Impl.isFCmpOrdCheaperThanFCmpZero(Ty);
2408 }
2409
2410 InstructionCost getFPOpCost(Type *Ty) override {
2411 return Impl.getFPOpCost(Ty);
2412 }
2413
2414 InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx,
2415 const APInt &Imm, Type *Ty) override {
2416 return Impl.getIntImmCodeSizeCost(Opc, Idx, Imm, Ty);
2417 }
2418 InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
2419 TargetCostKind CostKind) override {
2420 return Impl.getIntImmCost(Imm, Ty, CostKind);
2421 }
2422 InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx,
2423 const APInt &Imm, Type *Ty,
2425 Instruction *Inst = nullptr) override {
2426 return Impl.getIntImmCostInst(Opc, Idx, Imm, Ty, CostKind, Inst);
2427 }
2428 InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
2429 const APInt &Imm, Type *Ty,
2430 TargetCostKind CostKind) override {
2431 return Impl.getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
2432 }
2433 unsigned getNumberOfRegisters(unsigned ClassID) const override {
2434 return Impl.getNumberOfRegisters(ClassID);
2435 }
2436 unsigned getRegisterClassForType(bool Vector,
2437 Type *Ty = nullptr) const override {
2438 return Impl.getRegisterClassForType(Vector, Ty);
2439 }
2440 const char *getRegisterClassName(unsigned ClassID) const override {
2441 return Impl.getRegisterClassName(ClassID);
2442 }
2443 TypeSize getRegisterBitWidth(RegisterKind K) const override {
2444 return Impl.getRegisterBitWidth(K);
2445 }
2446 unsigned getMinVectorRegisterBitWidth() const override {
2447 return Impl.getMinVectorRegisterBitWidth();
2448 }
2449 std::optional<unsigned> getMaxVScale() const override {
2450 return Impl.getMaxVScale();
2451 }
2452 std::optional<unsigned> getVScaleForTuning() const override {
2453 return Impl.getVScaleForTuning();
2454 }
2455 bool isVScaleKnownToBeAPowerOfTwo() const override {
2456 return Impl.isVScaleKnownToBeAPowerOfTwo();
2457 }
2458 bool shouldMaximizeVectorBandwidth(
2459 TargetTransformInfo::RegisterKind K) const override {
2460 return Impl.shouldMaximizeVectorBandwidth(K);
2461 }
2462 ElementCount getMinimumVF(unsigned ElemWidth,
2463 bool IsScalable) const override {
2464 return Impl.getMinimumVF(ElemWidth, IsScalable);
2465 }
2466 unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const override {
2467 return Impl.getMaximumVF(ElemWidth, Opcode);
2468 }
2469 unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
2470 Type *ScalarValTy) const override {
2471 return Impl.getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy);
2472 }
2473 bool shouldConsiderAddressTypePromotion(
2474 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) override {
2475 return Impl.shouldConsiderAddressTypePromotion(
2476 I, AllowPromotionWithoutCommonHeader);
2477 }
2478 unsigned getCacheLineSize() const override { return Impl.getCacheLineSize(); }
2479 std::optional<unsigned> getCacheSize(CacheLevel Level) const override {
2480 return Impl.getCacheSize(Level);
2481 }
2482 std::optional<unsigned>
2483 getCacheAssociativity(CacheLevel Level) const override {
2484 return Impl.getCacheAssociativity(Level);
2485 }
2486
2487 /// Return the preferred prefetch distance in terms of instructions.
2488 ///
2489 unsigned getPrefetchDistance() const override {
2490 return Impl.getPrefetchDistance();
2491 }
2492
2493 /// Return the minimum stride necessary to trigger software
2494 /// prefetching.
2495 ///
2496 unsigned getMinPrefetchStride(unsigned NumMemAccesses,
2497 unsigned NumStridedMemAccesses,
2498 unsigned NumPrefetches,
2499 bool HasCall) const override {
2500 return Impl.getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
2501 NumPrefetches, HasCall);
2502 }
2503
2504 /// Return the maximum prefetch distance in terms of loop
2505 /// iterations.
2506 ///
2507 unsigned getMaxPrefetchIterationsAhead() const override {
2508 return Impl.getMaxPrefetchIterationsAhead();
2509 }
2510
2511 /// \return True if prefetching should also be done for writes.
2512 bool enableWritePrefetching() const override {
2513 return Impl.enableWritePrefetching();
2514 }
2515
2516 /// \return if target want to issue a prefetch in address space \p AS.
2517 bool shouldPrefetchAddressSpace(unsigned AS) const override {
2518 return Impl.shouldPrefetchAddressSpace(AS);
2519 }
2520
2521 unsigned getMaxInterleaveFactor(ElementCount VF) override {
2522 return Impl.getMaxInterleaveFactor(VF);
2523 }
2524 unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
2525 unsigned &JTSize,
2526 ProfileSummaryInfo *PSI,
2527 BlockFrequencyInfo *BFI) override {
2528 return Impl.getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
2529 }
2530 InstructionCost getArithmeticInstrCost(
2531 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
2532 OperandValueInfo Opd1Info, OperandValueInfo Opd2Info,
2533 ArrayRef<const Value *> Args,
2534 const Instruction *CxtI = nullptr) override {
2535 return Impl.getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info,
2536 Args, CxtI);
2537 }
2538
2539 InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp,
2540 ArrayRef<int> Mask,
2542 VectorType *SubTp,
2543 ArrayRef<const Value *> Args) override {
2544 return Impl.getShuffleCost(Kind, Tp, Mask, CostKind, Index, SubTp, Args);
2545 }
2546 InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
2547 CastContextHint CCH,
2549 const Instruction *I) override {
2550 return Impl.getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
2551 }
2552 InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst,
2553 VectorType *VecTy,
2554 unsigned Index) override {
2555 return Impl.getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
2556 }
2557 InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
2558 const Instruction *I = nullptr) override {
2559 return Impl.getCFInstrCost(Opcode, CostKind, I);
2560 }
2561 InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
2562 CmpInst::Predicate VecPred,
2564 const Instruction *I) override {
2565 return Impl.getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
2566 }
2567 InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
2569 unsigned Index, Value *Op0,
2570 Value *Op1) override {
2571 return Impl.getVectorInstrCost(Opcode, Val, CostKind, Index, Op0, Op1);
2572 }
2573 InstructionCost getVectorInstrCost(const Instruction &I, Type *Val,
2575 unsigned Index) override {
2576 return Impl.getVectorInstrCost(I, Val, CostKind, Index);
2577 }
2578 InstructionCost
2579 getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF,
2580 const APInt &DemandedDstElts,
2581 TTI::TargetCostKind CostKind) override {
2582 return Impl.getReplicationShuffleCost(EltTy, ReplicationFactor, VF,
2583 DemandedDstElts, CostKind);
2584 }
2585 InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
2586 unsigned AddressSpace,
2588 OperandValueInfo OpInfo,
2589 const Instruction *I) override {
2590 return Impl.getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind,
2591 OpInfo, I);
2592 }
2593 InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
2594 unsigned AddressSpace,
2596 const Instruction *I) override {
2597 return Impl.getVPMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
2598 CostKind, I);
2599 }
2600 InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
2601 Align Alignment, unsigned AddressSpace,
2602 TTI::TargetCostKind CostKind) override {
2603 return Impl.getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
2604 CostKind);
2605 }
2606 InstructionCost
2607 getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr,
2608 bool VariableMask, Align Alignment,
2610 const Instruction *I = nullptr) override {
2611 return Impl.getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
2612 Alignment, CostKind, I);
2613 }
2614 InstructionCost getInterleavedMemoryOpCost(
2615 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
2616 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
2617 bool UseMaskForCond, bool UseMaskForGaps) override {
2618 return Impl.getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2619 Alignment, AddressSpace, CostKind,
2620 UseMaskForCond, UseMaskForGaps);
2621 }
2622 InstructionCost
2623 getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
2624 std::optional<FastMathFlags> FMF,
2625 TTI::TargetCostKind CostKind) override {
2626 return Impl.getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
2627 }
2628 InstructionCost
2629 getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF,
2630 TTI::TargetCostKind CostKind) override {
2631 return Impl.getMinMaxReductionCost(IID, Ty, FMF, CostKind);
2632 }
2633 InstructionCost
2634 getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy,
2635 VectorType *Ty, FastMathFlags FMF,
2636 TTI::TargetCostKind CostKind) override {
2637 return Impl.getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF,
2638 CostKind);
2639 }
2640 InstructionCost
2641 getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty,
2642 TTI::TargetCostKind CostKind) override {
2643 return Impl.getMulAccReductionCost(IsUnsigned, ResTy, Ty, CostKind);
2644 }
2645 InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
2646 TTI::TargetCostKind CostKind) override {
2647 return Impl.getIntrinsicInstrCost(ICA, CostKind);
2648 }
2649 InstructionCost getCallInstrCost(Function *F, Type *RetTy,
2650 ArrayRef<Type *> Tys,
2651 TTI::TargetCostKind CostKind) override {
2652 return Impl.getCallInstrCost(F, RetTy, Tys, CostKind);
2653 }
2654 unsigned getNumberOfParts(Type *Tp) override {
2655 return Impl.getNumberOfParts(Tp);
2656 }
2657 InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE,
2658 const SCEV *Ptr) override {
2659 return Impl.getAddressComputationCost(Ty, SE, Ptr);
2660 }
2661 InstructionCost getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) override {
2662 return Impl.getCostOfKeepingLiveOverCall(Tys);
2663 }
2664 bool getTgtMemIntrinsic(IntrinsicInst *Inst,
2665 MemIntrinsicInfo &Info) override {
2666 return Impl.getTgtMemIntrinsic(Inst, Info);
2667 }
2668 unsigned getAtomicMemIntrinsicMaxElementSize() const override {
2669 return Impl.getAtomicMemIntrinsicMaxElementSize();
2670 }
2671 Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
2672 Type *ExpectedType) override {
2673 return Impl.getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
2674 }
2675 Type *getMemcpyLoopLoweringType(
2676 LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
2677 unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign,
2678 std::optional<uint32_t> AtomicElementSize) const override {
2679 return Impl.getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
2680 DestAddrSpace, SrcAlign, DestAlign,
2681 AtomicElementSize);
2682 }
2683 void getMemcpyLoopResidualLoweringType(
2684 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
2685 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
2686 unsigned SrcAlign, unsigned DestAlign,
2687 std::optional<uint32_t> AtomicCpySize) const override {
2688 Impl.getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
2689 SrcAddrSpace, DestAddrSpace,
2690 SrcAlign, DestAlign, AtomicCpySize);
2691 }
2692 bool areInlineCompatible(const Function *Caller,
2693 const Function *Callee) const override {
2694 return Impl.areInlineCompatible(Caller, Callee);
2695 }
2696 unsigned getInlineCallPenalty(const Function *F, const CallBase &Call,
2697 unsigned DefaultCallPenalty) const override {
2698 return Impl.getInlineCallPenalty(F, Call, DefaultCallPenalty);
2699 }
2700 bool areTypesABICompatible(const Function *Caller, const Function *Callee,
2701 const ArrayRef<Type *> &Types) const override {
2702 return Impl.areTypesABICompatible(Caller, Callee, Types);
2703 }
2704 bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const override {
2705 return Impl.isIndexedLoadLegal(Mode, Ty, getDataLayout());
2706 }
2707 bool isIndexedStoreLegal(MemIndexedMode Mode, Type *Ty) const override {
2708 return Impl.isIndexedStoreLegal(Mode, Ty, getDataLayout());
2709 }
2710 unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override {
2711 return Impl.getLoadStoreVecRegBitWidth(AddrSpace);
2712 }
2713 bool isLegalToVectorizeLoad(LoadInst *LI) const override {
2714 return Impl.isLegalToVectorizeLoad(LI);
2715 }
2716 bool isLegalToVectorizeStore(StoreInst *SI) const override {
2717 return Impl.isLegalToVectorizeStore(SI);
2718 }
2719 bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
2720 unsigned AddrSpace) const override {
2721 return Impl.isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
2722 AddrSpace);
2723 }
2724 bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
2725 unsigned AddrSpace) const override {
2726 return Impl.isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
2727 AddrSpace);
2728 }
2729 bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc,
2730 ElementCount VF) const override {
2731 return Impl.isLegalToVectorizeReduction(RdxDesc, VF);
2732 }
2733 bool isElementTypeLegalForScalableVector(Type *Ty) const override {
2734 return Impl.isElementTypeLegalForScalableVector(Ty);
2735 }
2736 unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
2737 unsigned ChainSizeInBytes,
2738 VectorType *VecTy) const override {
2739 return Impl.getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
2740 }
2741 unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
2742 unsigned ChainSizeInBytes,
2743 VectorType *VecTy) const override {
2744 return Impl.getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
2745 }
2746 bool preferInLoopReduction(unsigned Opcode, Type *Ty,
2747 ReductionFlags Flags) const override {
2748 return Impl.preferInLoopReduction(Opcode, Ty, Flags);
2749 }
2750 bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
2751 ReductionFlags Flags) const override {
2752 return Impl.preferPredicatedReductionSelect(Opcode, Ty, Flags);
2753 }
2754 bool preferEpilogueVectorization() const override {
2755 return Impl.preferEpilogueVectorization();
2756 }
2757
2758 bool shouldExpandReduction(const IntrinsicInst *II) const override {
2759 return Impl.shouldExpandReduction(II);
2760 }
2761
2762 unsigned getGISelRematGlobalCost() const override {
2763 return Impl.getGISelRematGlobalCost();
2764 }
2765
2766 unsigned getMinTripCountTailFoldingThreshold() const override {
2767 return Impl.getMinTripCountTailFoldingThreshold();
2768 }
2769
2770 bool supportsScalableVectors() const override {
2771 return Impl.supportsScalableVectors();
2772 }
2773
2774 bool enableScalableVectorization() const override {
2775 return Impl.enableScalableVectorization();
2776 }
2777
2778 bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
2779 Align Alignment) const override {
2780 return Impl.hasActiveVectorLength(Opcode, DataType, Alignment);
2781 }
2782
2784 getVPLegalizationStrategy(const VPIntrinsic &PI) const override {
2785 return Impl.getVPLegalizationStrategy(PI);
2786 }
2787
2788 bool hasArmWideBranch(bool Thumb) const override {
2789 return Impl.hasArmWideBranch(Thumb);
2790 }
2791
2792 unsigned getMaxNumArgs() const override {
2793 return Impl.getMaxNumArgs();
2794 }
2795};
2796
2797template <typename T>
2799 : TTIImpl(new Model<T>(Impl)) {}
2800
2801/// Analysis pass providing the \c TargetTransformInfo.
2802///
2803/// The core idea of the TargetIRAnalysis is to expose an interface through
2804/// which LLVM targets can analyze and provide information about the middle
2805/// end's target-independent IR. This supports use cases such as target-aware
2806/// cost modeling of IR constructs.
2807///
2808/// This is a function analysis because much of the cost modeling for targets
2809/// is done in a subtarget specific way and LLVM supports compiling different
2810/// functions targeting different subtargets in order to support runtime
2811/// dispatch according to the observed subtarget.
2812class TargetIRAnalysis : public AnalysisInfoMixin<TargetIRAnalysis> {
2813public:
2815
2816 /// Default construct a target IR analysis.
2817 ///
2818 /// This will use the module's datalayout to construct a baseline
2819 /// conservative TTI result.
2821
2822 /// Construct an IR analysis pass around a target-provide callback.
2823 ///
2824 /// The callback will be called with a particular function for which the TTI
2825 /// is needed and must return a TTI object for that function.
2826 TargetIRAnalysis(std::function<Result(const Function &)> TTICallback);
2827
2828 // Value semantics. We spell out the constructors for MSVC.
2830 : TTICallback(Arg.TTICallback) {}
2832 : TTICallback(std::move(Arg.TTICallback)) {}
2834 TTICallback = RHS.TTICallback;
2835 return *this;
2836 }
2838 TTICallback = std::move(RHS.TTICallback);
2839 return *this;
2840 }
2841
2843
2844private:
2846 static AnalysisKey Key;
2847
2848 /// The callback used to produce a result.
2849 ///
2850 /// We use a completely opaque callback so that targets can provide whatever
2851 /// mechanism they desire for constructing the TTI for a given function.
2852 ///
2853 /// FIXME: Should we really use std::function? It's relatively inefficient.
2854 /// It might be possible to arrange for even stateful callbacks to outlive
2855 /// the analysis and thus use a function_ref which would be lighter weight.
2856 /// This may also be less error prone as the callback is likely to reference
2857 /// the external TargetMachine, and that reference needs to never dangle.
2858 std::function<Result(const Function &)> TTICallback;
2859
2860 /// Helper function used as the callback in the default constructor.
2861 static Result getDefaultTTI(const Function &F);
2862};
2863
2864/// Wrapper pass for TargetTransformInfo.
2865///
2866/// This pass can be constructed from a TTI object which it stores internally
2867/// and is queried by passes.
2869 TargetIRAnalysis TIRA;
2870 std::optional<TargetTransformInfo> TTI;
2871
2872 virtual void anchor();
2873
2874public:
2875 static char ID;
2876
2877 /// We must provide a default constructor for the pass but it should
2878 /// never be used.
2879 ///
2880 /// Use the constructor below or call one of the creation routines.
2882
2884
2886};
2887
2888/// Create an analysis pass wrapper around a TTI object.
2889///
2890/// This analysis pass just holds the TTI instance and makes it available to
2891/// clients.
2893
2894} // namespace llvm
2895
2896#endif
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
AMDGPU Lower Kernel Arguments
Atomic ordering constants.
RelocType Type
Definition: COFFYAML.cpp:391
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
return RetTy
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
This file defines an InstructionCost class that is used when calculating the cost of an instruction,...
std::optional< unsigned > getMaxVScale(const Function &F, const TargetTransformInfo &TTI)
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
Machine InstCombiner
This header defines various interfaces for pass management in LLVM.
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
This file implements the SmallBitVector class.
Value * RHS
static constexpr uint32_t OpcodeMask
Definition: aarch32.h:219
static constexpr uint32_t Opcode
Definition: aarch32.h:200
Class for arbitrary precision integers.
Definition: APInt.h:76
an instruction to allocate memory on the stack
Definition: Instructions.h:58
API to communicate dependencies between analyses during invalidation.
Definition: PassManager.h:690
A container for analyses that lazily runs them and caches their results.
Definition: PassManager.h:649
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A cache of @llvm.assume calls within a function.
LLVM Basic Block Representation.
Definition: BasicBlock.h:60
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Conditional or Unconditional Branch instruction.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1227
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:748
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:165
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:20
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:282
The core instruction combiner logic.
Definition: InstCombiner.h:46
static InstructionCost getInvalid(CostType Val=0)
Class to represent integer types.
Definition: DerivedTypes.h:40
Drive the analysis of interleaved memory accesses in the loop.
Definition: VectorUtils.h:756
const SmallVectorImpl< Type * > & getArgTypes() const
const SmallVectorImpl< const Value * > & getArgs() const
InstructionCost getScalarizationCost() const
const IntrinsicInst * getInst() const
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:47
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:177
LoopVectorizationLegality checks if it is legal to vectorize a loop, and to what vectorization factor...
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:44
The optimization diagnostic interface.
A set of analyses that are preserved following a run of a transformation pass.
Definition: PassManager.h:172
Analysis providing profile information.
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:71
This class represents an analyzed expression in the program.
The main scalar evolution driver.
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
An instruction for storing to memory.
Definition: Instructions.h:301
Multiway switch.
Analysis pass providing the TargetTransformInfo.
TargetIRAnalysis(const TargetIRAnalysis &Arg)
TargetIRAnalysis & operator=(const TargetIRAnalysis &RHS)
Result run(const Function &F, FunctionAnalysisManager &)
TargetTransformInfo Result
TargetIRAnalysis()
Default construct a target IR analysis.
TargetIRAnalysis & operator=(TargetIRAnalysis &&RHS)
TargetIRAnalysis(TargetIRAnalysis &&Arg)
Provides information about what library functions are available for the current target.
Wrapper pass for TargetTransformInfo.
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
TargetTransformInfo & getTTI(const Function &F)
virtual std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed)=0
virtual InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr)=0
virtual TypeSize getRegisterBitWidth(RegisterKind K) const =0
virtual const DataLayout & getDataLayout() const =0
virtual bool isProfitableLSRChainElement(Instruction *I)=0
virtual InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)=0
virtual InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr)=0
virtual InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)=0
virtual void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)=0
virtual bool isLegalNTStore(Type *DataType, Align Alignment)=0
virtual unsigned adjustInliningThreshold(const CallBase *CB)=0
virtual bool isExpensiveToSpeculativelyExecute(const Instruction *I)=0
virtual bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const =0
virtual std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II)=0
virtual bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, ReductionFlags) const =0
virtual VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const =0
virtual bool isLegalNTLoad(Type *DataType, Align Alignment)=0
virtual bool enableOrderedReductions()=0
virtual PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit)=0
virtual unsigned getNumberOfRegisters(unsigned ClassID) const =0
virtual std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const =0
virtual bool isLegalMaskedGather(Type *DataType, Align Alignment)=0
virtual bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const =0
virtual InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind)=0
virtual bool shouldPrefetchAddressSpace(unsigned AS) const =0
virtual bool isFCmpOrdCheaperThanFCmpZero(Type *Ty)=0
virtual unsigned getMinVectorRegisterBitWidth() const =0
virtual std::optional< unsigned > getVScaleForTuning() const =0
virtual InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind)=0
virtual InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind)=0
virtual bool supportsEfficientVectorElementLoadStore()=0
virtual unsigned getRegUsageForType(Type *Ty)=0
virtual bool hasArmWideBranch(bool Thumb) const =0
virtual MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const =0
virtual InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput)=0
virtual InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, OperandValueInfo Opd1Info, OperandValueInfo Opd2Info, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr)=0
virtual unsigned getAssumedAddrSpace(const Value *V) const =0
virtual bool isTruncateFree(Type *Ty1, Type *Ty2)=0
virtual bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const =0
virtual InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType, TTI::TargetCostKind CostKind)=0
virtual InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TargetCostKind CostKind)=0
virtual bool shouldBuildLookupTables()=0
virtual bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const =0
virtual bool isLegalToVectorizeStore(StoreInst *SI) const =0
virtual unsigned getGISelRematGlobalCost() const =0
virtual unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const =0
virtual void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicCpySize) const =0
virtual InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace)=0
virtual bool forceScalarizeMaskedScatter(VectorType *DataType, Align Alignment)=0
virtual bool supportsTailCallFor(const CallBase *CB)=0
virtual std::optional< unsigned > getMaxVScale() const =0
virtual InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind)=0
virtual bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const =0
virtual unsigned getMaxNumArgs() const =0
virtual bool shouldExpandReduction(const IntrinsicInst *II) const =0
virtual bool enableWritePrefetching() const =0
virtual bool useColdCCForColdCall(Function &F)=0
virtual unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const =0
virtual bool preferInLoopReduction(unsigned Opcode, Type *Ty, ReductionFlags) const =0
virtual int getInlinerVectorBonusPercent() const =0
virtual unsigned getMaxPrefetchIterationsAhead() const =0
virtual bool isLegalMaskedScatter(Type *DataType, Align Alignment)=0
virtual bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const =0
virtual unsigned getCacheLineSize() const =0
virtual bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const =0
virtual unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const =0
virtual AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const =0
virtual bool shouldBuildLookupTablesForConstant(Constant *C)=0
virtual bool preferPredicateOverEpilogue(TailFoldingInfo *TFI)=0
virtual bool isProfitableToHoist(Instruction *I)=0
virtual InstructionCost getFPOpCost(Type *Ty)=0
virtual unsigned getMinTripCountTailFoldingThreshold() const =0
virtual bool enableMaskedInterleavedAccessVectorization()=0
virtual unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const =0
virtual bool isTypeLegal(Type *Ty)=0
virtual bool isLegalMaskedExpandLoad(Type *DataType)=0
virtual BranchProbability getPredictableBranchThreshold()=0
virtual bool enableScalableVectorization() const =0
virtual bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info)=0
virtual bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const =0
virtual const char * getRegisterClassName(unsigned ClassID) const =0
virtual unsigned getMaxInterleaveFactor(ElementCount VF)=0
virtual bool enableAggressiveInterleaving(bool LoopHasReductions)=0
virtual bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const =0
virtual bool haveFastSqrt(Type *Ty)=0
virtual std::optional< unsigned > getCacheSize(CacheLevel Level) const =0
virtual InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)=0
virtual InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const TTI::PointersChainInfo &Info, Type *AccessTy, TTI::TargetCostKind CostKind)=0
virtual void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP)=0
virtual std::optional< unsigned > getCacheAssociativity(CacheLevel Level) const =0
virtual bool supportsScalableVectors() const =0
virtual bool forceScalarizeMaskedGather(VectorType *DataType, Align Alignment)=0
virtual unsigned getNumberOfParts(Type *Tp)=0
virtual bool isLegalICmpImmediate(int64_t Imm)=0
virtual unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)=0
virtual InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)=0
virtual bool isElementTypeLegalForScalableVector(Type *Ty) const =0
virtual TailFoldingStyle getPreferredTailFoldingStyle(bool IVUpdateMayOverflow=true)=0
virtual bool hasDivRemOp(Type *DataType, bool IsSigned)=0
virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const =0
virtual bool shouldBuildRelLookupTables()=0
virtual InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys, TargetCostKind CostKind)=0
virtual bool isLoweredToCall(const Function *F)=0
virtual bool isSourceOfDivergence(const Value *V)=0
virtual bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const =0
virtual unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const =0
virtual bool isLegalMaskedLoad(Type *DataType, Align Alignment)=0
virtual InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput)=0
virtual bool isFPVectorizationPotentiallyUnsafe()=0
virtual Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType)=0
virtual unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const =0
virtual InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty)=0
virtual InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I)=0
virtual bool hasBranchDivergence(const Function *F=nullptr)=0
virtual InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)=0
virtual InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I)=0
virtual unsigned getInliningThresholdMultiplier() const =0
virtual InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)=0
virtual bool isLegalMaskedStore(Type *DataType, Align Alignment)=0
virtual InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, TTI::TargetCostKind CostKind, unsigned Index)=0
virtual bool isLegalToVectorizeLoad(LoadInst *LI) const =0
virtual bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const =0
virtual InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args)=0
virtual unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const =0
virtual bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2)=0
virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I)=0
virtual bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const =0
virtual InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)=0
virtual bool prefersVectorizedAddressing()=0
virtual uint64_t getMaxMemIntrinsicInlineSizeThreshold() const =0
virtual InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, OperandValueInfo OpInfo, const Instruction *I)=0
virtual bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo)=0
virtual Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicElementSize) const =0
virtual InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)=0
virtual bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo)=0
virtual bool isAlwaysUniform(const Value *V)=0
virtual InstructionCost getMemcpyCost(const Instruction *I)=0
virtual ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const =0
virtual bool areInlineCompatible(const Function *Caller, const Function *Callee) const =0
virtual bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const =0
virtual InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index)=0
virtual std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp)=0
virtual unsigned getFlatAddressSpace()=0
virtual InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)=0
virtual unsigned getPrefetchDistance() const =0
virtual bool shouldFoldTerminatingConditionAfterLSR() const =0
virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace)=0
virtual bool isLegalMaskedCompressStore(Type *DataType)=0
virtual bool isNumRegsMajorCostOfLSR()=0
virtual bool isSingleThreaded() const =0
virtual bool isLegalAddImmediate(int64_t Imm)=0
virtual Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const =0
virtual bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader)=0
virtual unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const =0
virtual bool isVScaleKnownToBeAPowerOfTwo() const =0
virtual InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys)=0
virtual bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const =0
virtual bool enableInterleavedAccessVectorization()=0
virtual unsigned getAtomicMemIntrinsicMaxElementSize() const =0
virtual bool preferEpilogueVectorization() const =0
virtual InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I)=0
virtual unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const =0
virtual bool isIndexedStoreLegal(MemIndexedMode Mode, Type *Ty) const =0
virtual bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, unsigned *Fast)=0
virtual unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const =0
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
bool isLegalToVectorizeLoad(LoadInst *LI) const
std::optional< unsigned > getVScaleForTuning() const
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const
Return false if a AS0 address cannot possibly alias a AS1 address.
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
bool isLegalToVectorizeStore(StoreInst *SI) const
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicCpySize=std::nullopt) const
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
bool preferInLoopReduction(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
bool isAlwaysUniform(const Value *V) const
unsigned getAssumedAddrSpace(const Value *V) const
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C2.
bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
bool hasBranchDivergence(const Function *F=nullptr) const
Return true if branch divergence exists.
MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE=nullptr, const SCEV *Ptr=nullptr) const
bool invalidate(Function &, const PreservedAnalyses &, FunctionAnalysisManager::Invalidator &)
Handle the invalidation of this information.
void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
bool shouldFoldTerminatingConditionAfterLSR() const
Return true if LSR should attempts to replace a use of an otherwise dead primary IV in the latch cond...
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
Estimate the overhead of scalarizing an instructions unique non-constant operands.
bool supportsTailCallFor(const CallBase *CB) const
If target supports tail call on CB.
std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
bool isProfitableLSRChainElement(Instruction *I) const
TypeSize getRegisterBitWidth(RegisterKind K) const
unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
Returns a penalty for invoking call Call in F.
bool isExpensiveToSpeculativelyExecute(const Instruction *I) const
Return true if the cost of the instruction is too high to speculatively execute and should be kept be...
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueInfo OpdInfo={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
std::optional< unsigned > getMaxVScale() const
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
InstructionCost getInstructionCost(const User *U, TargetCostKind CostKind) const
This is a helper function which calls the three-argument getInstructionCost with Operands which are t...
unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of vector reduction intrinsics.
unsigned getAtomicMemIntrinsicMaxElementSize() const
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
TailFoldingStyle getPreferredTailFoldingStyle(bool IVUpdateMayOverflow=true) const
Query the target what the preferred style of tail folding is.
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType=nullptr, TargetCostKind CostKind=TCK_SizeAndLatency) const
Estimate the cost of a GEP operation when lowered.
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
unsigned getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy...
bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of a reduc...
static OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add ...
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
bool isElementTypeLegalForScalableVector(Type *Ty) const
bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.gather intrinsics.
unsigned getMaxPrefetchIterationsAhead() const
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF=FastMathFlags(), TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
TargetCostKind
The kind of cost model.
@ TCK_RecipThroughput
Reciprocal throughput.
@ TCK_CodeSize
Instruction code size.
@ TCK_SizeAndLatency
The weighted sum of size and latency.
@ TCK_Latency
The latency of instruction.
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
bool enableSelectOptimize() const
Should the Select Optimization pass be enabled and ran.
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
OperandValueProperties
Additional properties of an operand's values.
InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const PointersChainInfo &Info, Type *AccessTy, TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Estimate the cost of a chain of pointers (typically pointer operands of a chain of loads or stores wi...
bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
bool isSourceOfDivergence(const Value *V) const
Returns whether V is a source of divergence.
bool isLegalMaskedCompressStore(Type *DataType) const
Return true if the target supports masked compress store.
bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
static bool requiresOrderedReduction(std::optional< FastMathFlags > FMF)
A helper function to determine the type of reduction algorithm used for a given Opcode and set of Fas...
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
std::optional< unsigned > getCacheAssociativity(CacheLevel Level) const
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
InstructionCost getMemcpyCost(const Instruction *I) const
unsigned adjustInliningThreshold(const CallBase *CB) const
bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
bool shouldPrefetchAddressSpace(unsigned AS) const
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
unsigned getMinVectorRegisterBitWidth() const
bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
bool hasArmWideBranch(bool Thumb) const
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
const char * getRegisterClassName(unsigned ClassID) const
bool preferEpilogueVectorization() const
Return true if the loop vectorizer should consider vectorizing an otherwise scalar epilogue loop.
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), unsigned *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask=std::nullopt, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, int Index=0, VectorType *SubTp=nullptr, ArrayRef< const Value * > Args=std::nullopt) const
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
bool isLegalMaskedExpandLoad(Type *DataType) const
Return true if the target supports masked expand load.
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
PopcntSupportKind
Flags indicating the kind of support for population count.
InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
unsigned getInliningThresholdMultiplier() const
unsigned getNumberOfRegisters(unsigned ClassID) const
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
Return true if this is an alternating opcode pattern that can be lowered to a single instruction on t...
bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Return true if the target supports masked store.
bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const
std::optional< unsigned > getCacheSize(CacheLevel Level) const
std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
TargetCostConstants
Underlying constants for 'cost' values in this interface.
@ TCC_Expensive
The cost of a 'div' instruction on x86.
@ TCC_Free
Expected to fold away in lowering.
@ TCC_Basic
The cost of a typical 'add' instruction.
bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
unsigned getMinTripCountTailFoldingThreshold() const
InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
unsigned getMaxInterleaveFactor(ElementCount VF) const
bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
unsigned getGISelRematGlobalCost() const
MemIndexedMode
The type of load/store indexing.
@ MIM_PostInc
Post-incrementing.
@ MIM_PostDec
Post-decrementing.
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
bool supportsTailCalls() const
If the target supports tail calls.
bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Query the target whether the specified address space cast from FromAS to ToAS is valid.
unsigned getNumberOfParts(Type *Tp) const
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicElementSize=std::nullopt) const
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind) const
Estimate the overhead of scalarizing an instruction.
bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const
Query the target whether it would be prefered to create a predicated vector loop, which can avoid the...
bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.
bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
bool shouldExpandReduction(const IntrinsicInst *II) const
TargetTransformInfo(T Impl)
Construct a TTI object using a type implementing the Concept API below.
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const
Returns the maximum memset / memcpy size in bytes that still makes it profitable to inline the call.
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index=-1, Value *Op0=nullptr, Value *Op1=nullptr) const
ShuffleKind
The various kinds of shuffle patterns for vector queries.
@ SK_InsertSubvector
InsertSubvector. Index indicates start offset.
@ SK_Select
Selects elements from the corresponding lane of either source operand.
@ SK_PermuteSingleSrc
Shuffle elements of single source vector with any shuffle mask.
@ SK_Transpose
Transpose two vectors.
@ SK_Splice
Concatenates elements from the first input vector with elements of the second input vector.
@ SK_Broadcast
Broadcast element 0 to all other elements.
@ SK_PermuteTwoSrc
Merge elements from two source vectors into one with any shuffle mask.
@ SK_Reverse
Reverse the order of the vector.
@ SK_ExtractSubvector
ExtractSubvector Index indicates start offset.
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency) const
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
CastContextHint
Represents a hint about the context in which a cast is used.
@ Reversed
The cast is used with a reversed load/store.
@ Masked
The cast is used with a masked load/store.
@ None
The cast is not used with a load/store of any kind.
@ Normal
The cast is used with a normal load/store.
@ Interleave
The cast is used with an interleaved load/store.
@ GatherScatter
The cast is used with a gather/scatter.
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
OperandValueKind
Additional information about an operand's possible values.
CacheLevel
The possible cache levels.
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked load.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Definition: Value.h:74
Base class of all SIMD vector types.
Definition: DerivedTypes.h:403
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
bool areInlineCompatible(const Function &Caller, const Function &Callee)
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Definition: MsgPackReader.h:53
@ User
could "use" a pointer
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Length
Definition: DWP.cpp:440
AddressSpace
Definition: NVPTXBaseInfo.h:21
AtomicOrdering
Atomic ordering for LLVM's memory model.
TargetTransformInfo TTI
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
@ None
Not a recurrence.
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:191
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1853
@ DataAndControlFlowWithoutRuntimeCheck
Use predicate to control both data and control flow, but modify the trip count so that a runtime over...
@ DataAndControlFlow
Use predicate to control both data and control flow.
@ DataWithoutLaneMask
Same as Data, but avoids using the get.active.lane.mask intrinsic to calculate the mask and instead i...
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
A CRTP mix-in that provides informational APIs needed for analysis passes.
Definition: PassManager.h:414
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: PassManager.h:89
Attributes of a target dependent hardware loop.
bool canAnalyze(LoopInfo &LI)
bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Information about a load/store intrinsic defined by the target.
Value * PtrVal
This is the pointer that the intrinsic is loading from or storing to.
InterleavedAccessInfo * IAI
TailFoldingInfo(TargetLibraryInfo *TLI, LoopVectorizationLegality *LVL, InterleavedAccessInfo *IAI)
TargetLibraryInfo * TLI
LoopVectorizationLegality * LVL
unsigned Insns
TODO: Some of these could be merged.
Returns options for expansion of memcmp. IsZeroCmp is.
bool AllowPeeling
Allow peeling off loop iterations.
bool AllowLoopNestsPeeling
Allow peeling off loop iterations for loop nests.
bool PeelProfiledIterations
Allow peeling basing on profile.
unsigned PeelCount
A forced peeling factor (the number of bodied of the original loop that should be peeled off before t...
Describe known properties for a set of pointers.
unsigned IsKnownStride
True if distance between any two neigbouring pointers is a known value.
unsigned IsUnitStride
These properties only valid if SameBaseAddress is set.
unsigned IsSameBaseAddress
All the GEPs in a set have same base address.
Flags describing the kind of vector reduction.
bool IsSigned
Whether the operation is a signed int reduction.
bool IsMaxOp
If the op a min/max kind, true if it's a max operation.
bool NoNaN
If op is an fp min/max, whether NaNs may be present.
Parameters that control the generic loop unrolling transformation.
unsigned Count
A forced unrolling factor (the number of concatenated bodies of the original loop in the unrolled loo...
bool UpperBound
Allow using trip count upper bound to unroll loops.
unsigned Threshold
The cost threshold for the unrolled loop.
bool Force
Apply loop unroll on any kind of loop (mainly to loops that fail runtime unrolling).
unsigned PartialOptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size, like OptSizeThreshold,...
bool UnrollVectorizedLoop
Don't disable runtime unroll for the loops which were vectorized.
unsigned DefaultUnrollRuntimeCount
Default unroll count for loops with run-time trip count.
unsigned MaxPercentThresholdBoost
If complete unrolling will reduce the cost of the loop, we will boost the Threshold by a certain perc...
unsigned UnrollAndJamInnerLoopThreshold
Threshold for unroll and jam, for inner loop size.
unsigned MaxIterationsCountToAnalyze
Don't allow loop unrolling to simulate more than this number of iterations when checking full unroll ...
bool AllowRemainder
Allow generation of a loop remainder (extra iterations after unroll).
bool UnrollAndJam
Allow unroll and jam. Used to enable unroll and jam for the target.
bool UnrollRemainder
Allow unrolling of all the iterations of the runtime loop remainder.
unsigned FullUnrollMaxCount
Set the maximum unrolling factor for full unrolling.
unsigned PartialThreshold
The cost threshold for the unrolled loop, like Threshold, but used for partial/runtime unrolling (set...
bool Runtime
Allow runtime unrolling (unrolling of loops to expand the size of the loop body even when the number ...
bool Partial
Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...
unsigned OptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size (set to UINT_MAX to disable).
bool AllowExpensiveTripCount
Allow emitting expensive instructions (such as divisions) when computing the trip count of a loop for...
VPLegalization(VPTransform EVLParamStrategy, VPTransform OpStrategy)