14#ifndef LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
15#define LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
17#define GET_REGINFO_HEADER
18#include "R600GenRegisterInfo.inc"
51 unsigned FIOperandNum,
Wrapper class representing virtual and physical registers.
This is an optimization pass for GlobalISel generic memory operations.
unsigned getHWRegIndex(unsigned Reg) const
const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const
get the register class of the specified type to use in the CFGStructurizer
BitVector getReservedRegs(const MachineFunction &MF) const override
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register's channel.
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
static unsigned getSubRegFromChannel(unsigned Channel)
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool isPhysRegLiveAcrossClauses(Register Reg) const
void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Register getFrameRegister(const MachineFunction &MF) const override