LLVM  14.0.0git
R600RegisterInfo.cpp
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1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// R600 implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "R600RegisterInfo.h"
16 #include "R600Defines.h"
17 #include "R600Subtarget.h"
18 
19 using namespace llvm;
20 
21 #define GET_REGINFO_TARGET_DESC
22 #include "R600GenRegisterInfo.inc"
23 
24 unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) {
25  static const uint16_t SubRegFromChannelTable[] = {
26  R600::sub0, R600::sub1, R600::sub2, R600::sub3,
27  R600::sub4, R600::sub5, R600::sub6, R600::sub7,
28  R600::sub8, R600::sub9, R600::sub10, R600::sub11,
29  R600::sub12, R600::sub13, R600::sub14, R600::sub15
30  };
31 
32  assert(Channel < array_lengthof(SubRegFromChannelTable));
33  return SubRegFromChannelTable[Channel];
34 }
35 
37  BitVector Reserved(getNumRegs());
38 
40  const R600InstrInfo *TII = ST.getInstrInfo();
41 
42  reserveRegisterTuples(Reserved, R600::ZERO);
43  reserveRegisterTuples(Reserved, R600::HALF);
44  reserveRegisterTuples(Reserved, R600::ONE);
45  reserveRegisterTuples(Reserved, R600::ONE_INT);
46  reserveRegisterTuples(Reserved, R600::NEG_HALF);
47  reserveRegisterTuples(Reserved, R600::NEG_ONE);
48  reserveRegisterTuples(Reserved, R600::PV_X);
49  reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X);
50  reserveRegisterTuples(Reserved, R600::ALU_CONST);
51  reserveRegisterTuples(Reserved, R600::PREDICATE_BIT);
52  reserveRegisterTuples(Reserved, R600::PRED_SEL_OFF);
53  reserveRegisterTuples(Reserved, R600::PRED_SEL_ZERO);
54  reserveRegisterTuples(Reserved, R600::PRED_SEL_ONE);
55  reserveRegisterTuples(Reserved, R600::INDIRECT_BASE_ADDR);
56 
57  for (TargetRegisterClass::iterator I = R600::R600_AddrRegClass.begin(),
58  E = R600::R600_AddrRegClass.end(); I != E; ++I) {
59  reserveRegisterTuples(Reserved, *I);
60  }
61 
62  TII->reserveIndirectRegisters(Reserved, MF, *this);
63 
64  return Reserved;
65 }
66 
67 // Dummy to not crash RegisterClassInfo.
68 static const MCPhysReg CalleeSavedReg = R600::NoRegister;
69 
71  const MachineFunction *) const {
72  return &CalleeSavedReg;
73 }
74 
76  return R600::NoRegister;
77 }
78 
79 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
80  return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
81 }
82 
83 unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
84  return GET_REG_INDEX(getEncodingValue(Reg));
85 }
86 
88  MVT VT) const {
89  switch(VT.SimpleTy) {
90  default:
91  case MVT::i32: return &R600::R600_TReg32RegClass;
92  }
93 }
94 
96  assert(!Reg.isVirtual());
97 
98  switch (Reg) {
99  case R600::OQAP:
100  case R600::OQBP:
101  case R600::AR_X:
102  return false;
103  default:
104  return true;
105  }
106 }
107 
109  int SPAdj,
110  unsigned FIOperandNum,
111  RegScavenger *RS) const {
112  llvm_unreachable("Subroutines not supported yet");
113 }
114 
115 void R600RegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
116  MCRegAliasIterator R(Reg, this, true);
117 
118  for (; R.isValid(); ++R)
119  Reserved.set(*R);
120 }
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
GET_REG_INDEX
#define GET_REG_INDEX(reg)
Definition: R600Defines.h:57
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
HW_CHAN_SHIFT
#define HW_CHAN_SHIFT
Definition: R600Defines.h:54
llvm::R600RegisterInfo::getSubRegFromChannel
static unsigned getSubRegFromChannel(unsigned Channel)
Definition: R600RegisterInfo.cpp:24
llvm::R600RegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Definition: R600RegisterInfo.cpp:70
llvm::R600RegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: R600RegisterInfo.cpp:108
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::R600RegisterInfo::getCFGStructurizerRegClass
const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const
get the register class of the specified type to use in the CFGStructurizer
Definition: R600RegisterInfo.cpp:87
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:321
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::R600RegisterInfo::reserveRegisterTuples
void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const
Definition: R600RegisterInfo.cpp:115
llvm::BitVector
Definition: BitVector.h:74
llvm::R600RegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: R600RegisterInfo.cpp:75
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1392
R600MCTargetDesc.h
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::R600Subtarget
Definition: R600Subtarget.h:35
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:20
llvm::RegScavenger
Definition: RegisterScavenging.h:34
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::R600RegisterInfo::getHWRegIndex
unsigned getHWRegIndex(unsigned Reg) const
Definition: R600RegisterInfo.cpp:83
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
R600RegisterInfo.h
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
CalleeSavedReg
static const MCPhysReg CalleeSavedReg
Definition: R600RegisterInfo.cpp:68
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
uint16_t
R600Subtarget.h
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::R600RegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: R600RegisterInfo.cpp:36
llvm::R600InstrInfo
Definition: R600InstrInfo.h:39
llvm::R600RegisterInfo::isPhysRegLiveAcrossClauses
bool isPhysRegLiveAcrossClauses(Register Reg) const
Definition: R600RegisterInfo.cpp:95
R600Defines.h
llvm::R600RegisterInfo::getHWRegChan
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register's channel.
Definition: R600RegisterInfo.cpp:79
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780